| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 27 | logplain |
| -rw-r--r-- | example_3.14-cache.lib | 2518 | logplain |
| -rw-r--r-- | example_3.14.bak | 4085 | logplain |
| -rw-r--r-- | example_3.14.cir | 518 | logplain |
| -rw-r--r-- | example_3.14.cir.ckt | 419 | logplain |
| -rw-r--r-- | example_3.14.cir.out | 455 | logplain |
| -rw-r--r-- | example_3.14.pro | 1410 | logplain |
| -rw-r--r-- | example_3.14.proj | 31 | logplain |
| -rw-r--r-- | example_3.14.sch | 4248 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |