| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | analysis | 27 | logplain |
| -rw-r--r-- | example_2.2-cache.bak | 1445 | logplain |
| -rw-r--r-- | example_2.2-cache.lib | 1861 | logplain |
| -rw-r--r-- | example_2.2.bak | 2819 | logplain |
| -rw-r--r-- | example_2.2.cir | 462 | logplain |
| -rw-r--r-- | example_2.2.cir.ckt | 294 | logplain |
| -rw-r--r-- | example_2.2.cir.out | 333 | logplain |
| -rw-r--r-- | example_2.2.pro | 1966 | logplain |
| -rw-r--r-- | example_2.2.proj | 30 | logplain |
| -rw-r--r-- | example_2.2.sch | 3458 | logplain |
 |
index : FreeEDA/.git | |
| Tool for circuit design, simulation, analysis and PCB design (previously known as Oscad) |
| summaryrefslogtreecommitdiff |