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author | Jayaram Pai | 2014-05-19 11:02:57 +0530 |
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committer | Jayaram Pai | 2014-05-19 11:02:57 +0530 |
commit | 8377256e7d90aa7ba1cb51f6164e99f81e2eb53c (patch) | |
tree | 5afcc8e82d7f7d4f6fbff900520bd8f05eb343ca /OSCAD/Examples/sedra_smith/chapter_2/example_2.2 | |
download | FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.tar.gz FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.tar.bz2 FreeEDA-8377256e7d90aa7ba1cb51f6164e99f81e2eb53c.zip |
initial commit
Diffstat (limited to 'OSCAD/Examples/sedra_smith/chapter_2/example_2.2')
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diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/analysis b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/analysis new file mode 100644 index 0000000..403e10c --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/analysis @@ -0,0 +1 @@ +.dc v2 0e-00 10e-00 1e-00 diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.bak new file mode 100644 index 0000000..fc013c5 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.bak @@ -0,0 +1,90 @@ +EESchema-LIBRARY Version 2.3 Date: Sunday 14 April 2013 04:43:15 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 30 H I C CNN +F1 "PWR_FLAG" 0 180 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* + SM1206 +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.lib b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.lib new file mode 100644 index 0000000..aea3592 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2-cache.lib @@ -0,0 +1,108 @@ +EESchema-LIBRARY Version 2.3 Date: Monday 13 May 2013 12:54:28 PM IST +#encoding utf-8 +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# iplot +# +DEF iplot U 0 20 Y Y 1 F N +F0 "U" -150 100 50 H V C CNN +F1 "iplot" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 -250 0 150 R 30 30 1 1 I +X - 2 250 0 150 L 30 30 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.bak b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.bak new file mode 100644 index 0000000..6ce76aa --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.bak @@ -0,0 +1,162 @@ +EESchema Schematic File Version 2 date Sunday 14 April 2013 04:43:15 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_2.2-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "14 apr 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PWR_FLAG #FLG01 +U 1 1 516A8F23 +P 4150 6650 +F 0 "#FLG01" H 4150 6745 30 0001 C CNN +F 1 "PWR_FLAG" H 4150 6830 30 0000 C CNN + 1 4150 6650 + 0 1 1 0 +$EndComp +Connection ~ 4150 6650 +Connection ~ 6350 4000 +Wire Wire Line + 6350 3350 6350 3150 +Connection ~ 4150 5200 +Wire Wire Line + 6350 5200 4150 5200 +Wire Wire Line + 4800 3150 4150 3150 +Wire Wire Line + 4150 5350 4150 4650 +Wire Wire Line + 6350 3150 5700 3150 +Wire Wire Line + 6350 4650 6350 4800 +Wire Wire Line + 4150 5750 4150 6000 +Wire Wire Line + 6350 3850 6350 4150 +Wire Wire Line + 4150 3150 4150 4150 +Wire Wire Line + 4150 6850 4150 6500 +$Comp +L GND #PWR02 +U 1 1 5167DAB9 +P 4150 6850 +F 0 "#PWR02" H 4150 6850 30 0001 C CNN +F 1 "GND" H 4150 6780 30 0001 C CNN + 1 4150 6850 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 5167DA8B +P 4150 6250 +F 0 "U1" H 4000 6350 50 0000 C CNN +F 1 "IPLOT" H 4300 6350 50 0000 C CNN + 1 4150 6250 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U2 +U 1 1 5167D9D2 +P 6350 3600 +F 0 "U2" H 6200 3700 50 0000 C CNN +F 1 "IPLOT" H 6500 3700 50 0000 C CNN + 1 6350 3600 + 0 1 1 0 +$EndComp +$Comp +L DIODE D2 +U 1 1 5167D956 +P 6350 5000 +F 0 "D2" H 6350 5100 40 0000 C CNN +F 1 "DIODE" H 6350 4900 40 0000 C CNN + 1 6350 5000 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 5167D912 +P 5250 3150 +F 0 "v1" H 5050 3250 60 0000 C CNN +F 1 "10V" H 5050 3100 60 0000 C CNN +F 2 "R1" H 4950 3150 60 0000 C CNN + 1 5250 3150 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5167D8E5 +P 6350 4400 +F 0 "R2" V 6430 4400 50 0000 C CNN +F 1 "10k" V 6350 4400 50 0000 C CNN + 1 6350 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5167D8B8 +P 4150 4400 +F 0 "R1" V 4230 4400 50 0000 C CNN +F 1 "5k" V 4150 4400 50 0000 C CNN + 1 4150 4400 + 1 0 0 -1 +$EndComp +$Comp +L DIODE D1 +U 1 1 5167D869 +P 4150 5550 +F 0 "D1" H 4150 5650 40 0000 C CNN +F 1 "DIODE" H 4150 5450 40 0000 C CNN + 1 4150 5550 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir new file mode 100644 index 0000000..a8ccf76 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir @@ -0,0 +1,17 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 13 May 2013 12:54:07 PM IST + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U3 6 VPLOT8_1 +v2 1 0 10V +v1 0 4 10V +U1 5 0 IPLOT +U2 1 7 IPLOT +D2 6 3 DIODE +R2 7 6 5k +R1 4 3 10k +D1 5 3 DIODE + +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.ckt b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.ckt new file mode 100644 index 0000000..ec3f080 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.ckt @@ -0,0 +1,17 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 12:54:07 pm ist + +* Plotting option vplot8_1 +v2 1 0 10v +v1 0 4 10v +V_u1 5 0 0 +V_u2 1 7 0 +d2 6 3 diode +r2 7 6 5k +r1 4 3 10k +d1 5 3 diode + +.dc v2 0e-00 10e-00 1e-00 +.plot v(6) +.plot i(V_u1) +.plot i(V_u2) +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.out b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.out new file mode 100644 index 0000000..b89d0e8 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.cir.out @@ -0,0 +1,22 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 13 may 2013 12:54:07 pm ist + +* Plotting option vplot8_1 +v2 1 0 10v +v1 0 4 10v +V_u1 5 0 0 +V_u2 1 7 0 +d2 6 3 diode +r2 7 6 5k +r1 4 3 10k +d1 5 3 diode + +.dc v2 0e-00 10e-00 1e-00 + +* Control Statements +.control +run +plot v(6) +plot i(V_u1) +plot i(V_u2) +.endc +.end diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.pro b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.pro new file mode 100644 index 0000000..49fe832 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.pro @@ -0,0 +1,84 @@ +update=Monday 13 May 2013 12:52:59 PM IST +last_client=eeschema +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=60 +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=/home/ambikeshwar/OSCAD/library/analogSpice +LibName32=/home/ambikeshwar/OSCAD/library/analogXSpice +LibName33=/home/ambikeshwar/OSCAD/library/convergenceAidSpice +LibName34=/home/ambikeshwar/OSCAD/library/converterSpice +LibName35=/home/ambikeshwar/OSCAD/library/digitalSpice +LibName36=/home/ambikeshwar/OSCAD/library/digitalXSpice +LibName37=/home/ambikeshwar/OSCAD/library/linearSpice +LibName38=/home/ambikeshwar/OSCAD/library/measurementSpice +LibName39=/home/ambikeshwar/OSCAD/library/portSpice +LibName40=/home/ambikeshwar/OSCAD/library/sourcesSpice +LibName41=/home/holy/OSCAD/library/analogSpice +LibName42=/home/holy/OSCAD/library/analogXSpice +LibName43=/home/holy/OSCAD/library/convergenceAidSpice +LibName44=/home/holy/OSCAD/library/converterSpice +LibName45=/home/holy/OSCAD/library/digitalSpice +LibName46=/home/holy/OSCAD/library/digitalXSpice +LibName47=/home/holy/OSCAD/library/linearSpice +LibName48=/home/holy/OSCAD/library/measurementSpice +LibName49=/home/holy/OSCAD/library/portSpice +LibName50=/home/holy/OSCAD/library/sourcesSpice diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.proj b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.proj new file mode 100644 index 0000000..049873b --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.proj @@ -0,0 +1 @@ +schematicFile example_2.2.sch diff --git a/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.sch b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.sch new file mode 100644 index 0000000..de929d7 --- /dev/null +++ b/OSCAD/Examples/sedra_smith/chapter_2/example_2.2/example_2.2.sch @@ -0,0 +1,195 @@ +EESchema Schematic File Version 2 date Monday 13 May 2013 12:54:28 PM IST +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:linearSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:example_2.2-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11700 8267 +encoding utf-8 +Sheet 1 1 +Title "" +Date "13 may 2013" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 6650 4750 +$Comp +L VPLOT8_1 U3 +U 1 1 519094DB +P 6650 4450 +F 0 "U3" H 6500 4550 50 0000 C CNN +F 1 "VPLOT8_1" H 6800 4550 50 0000 C CNN + 1 6650 4450 + 1 0 0 -1 +$EndComp +Connection ~ 6350 4750 +Wire Wire Line + 6350 4750 6650 4750 +Wire Wire Line + 5050 3150 5450 3150 +Wire Wire Line + 4150 6850 4150 6500 +Wire Wire Line + 4150 3150 4150 4150 +Wire Wire Line + 6350 3850 6350 4150 +Wire Wire Line + 4150 5750 4150 6000 +Wire Wire Line + 6350 4650 6350 4800 +Wire Wire Line + 4150 5350 4150 4650 +Wire Wire Line + 6350 5200 4150 5200 +Connection ~ 4150 5200 +Wire Wire Line + 6350 3350 6350 3150 +Connection ~ 6350 4000 +Connection ~ 4150 6650 +Wire Wire Line + 5250 3150 5250 3300 +Connection ~ 5250 3150 +$Comp +L GND #PWR01 +U 1 1 51909464 +P 5250 3300 +F 0 "#PWR01" H 5250 3300 30 0001 C CNN +F 1 "GND" H 5250 3230 30 0001 C CNN + 1 5250 3300 + 1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 51909454 +P 5900 3150 +F 0 "v2" H 5700 3250 60 0000 C CNN +F 1 "10V" H 5700 3100 60 0000 C CNN +F 2 "R1" H 5600 3150 60 0000 C CNN + 1 5900 3150 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 5167D912 +P 4600 3150 +F 0 "v1" H 4400 3250 60 0000 C CNN +F 1 "10V" H 4400 3100 60 0000 C CNN +F 2 "R1" H 4300 3150 60 0000 C CNN + 1 4600 3150 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 516A8F23 +P 4150 6650 +F 0 "#FLG02" H 4150 6745 30 0001 C CNN +F 1 "PWR_FLAG" H 4150 6830 30 0000 C CNN + 1 4150 6650 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR03 +U 1 1 5167DAB9 +P 4150 6850 +F 0 "#PWR03" H 4150 6850 30 0001 C CNN +F 1 "GND" H 4150 6780 30 0001 C CNN + 1 4150 6850 + 1 0 0 -1 +$EndComp +$Comp +L IPLOT U1 +U 1 1 5167DA8B +P 4150 6250 +F 0 "U1" H 4000 6350 50 0000 C CNN +F 1 "IPLOT" H 4300 6350 50 0000 C CNN + 1 4150 6250 + 0 1 1 0 +$EndComp +$Comp +L IPLOT U2 +U 1 1 5167D9D2 +P 6350 3600 +F 0 "U2" H 6200 3700 50 0000 C CNN +F 1 "IPLOT" H 6500 3700 50 0000 C CNN + 1 6350 3600 + 0 1 1 0 +$EndComp +$Comp +L DIODE D2 +U 1 1 5167D956 +P 6350 5000 +F 0 "D2" H 6350 5100 40 0000 C CNN +F 1 "DIODE" H 6350 4900 40 0000 C CNN + 1 6350 5000 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5167D8E5 +P 6350 4400 +F 0 "R2" V 6430 4400 50 0000 C CNN +F 1 "5k" V 6350 4400 50 0000 C CNN + 1 6350 4400 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 5167D8B8 +P 4150 4400 +F 0 "R1" V 4230 4400 50 0000 C CNN +F 1 "10k" V 4150 4400 50 0000 C CNN + 1 4150 4400 + 1 0 0 -1 +$EndComp +$Comp +L DIODE D1 +U 1 1 5167D869 +P 4150 5550 +F 0 "D1" H 4150 5650 40 0000 C CNN +F 1 "DIODE" H 4150 5450 40 0000 C CNN + 1 4150 5550 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC |