722 files changed, 215724 insertions, 0 deletions

diff --git a/include/405_dimm.h b/include/405_dimm.h
new file mode 100755
index 0000000..103a349
--- /dev/null
+++ b/include/405_dimm.h
@@ -0,0 +1,4 @@
+#ifndef _405_dimm_h_
+#define _405_dimm_h_
+long int walnut_dimm(void);
+#endif
diff --git a/include/405_mal.h b/include/405_mal.h
new file mode 100755
index 0000000..69d20c9
--- /dev/null
+++ b/include/405_mal.h
@@ -0,0 +1,114 @@
+/* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */
+/*----------------------------------------------------------------------------+
+|
+|	This source code has been made available to you by IBM on an AS-IS
+|	basis.	Anyone receiving this source is licensed under IBM
+|	copyrights to use it in any way he or she deems fit, including
+|	copying it, modifying it, compiling it, and redistributing it either
+|	with or without modifications.	No license under IBM patents or
+|	patent applications is to be implied by the copyright license.
+|
+|	Any user of this software should understand that IBM cannot provide
+|	technical support for this software and will not be responsible for
+|	any consequences resulting from the use of this software.
+|
+|	Any person who transfers this source code or any derivative work
+|	must include the IBM copyright notice, this paragraph, and the
+|	preceding two paragraphs in the transferred software.
+|
+|	COPYRIGHT   I B M   CORPORATION 1999
+|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+|
+|  File Name:	mal.h
+|
+|  Function:	Header file for the MAL (MADMAL) macro on the 405GP.
+|
+|  Author:	Mark Wisner
+|
+|  Change Activity-
+|
+|  Date	       Description of Change					   BY
+|  ---------   ---------------------					   ---
+|  29-Apr-99   Created							   MKW
+|
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+|  17-Nov-03  Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+|	      Added register bit definitions to support multiple channels
++----------------------------------------------------------------------------*/
+#ifndef _mal_h_
+#define _mal_h_
+/* MADMAL transmit and receive status/control bits  */
+/* for COMMAC bits, refer to the COMMAC header file */
+
+#define MAL_TX_CTRL_READY 0x8000
+#define MAL_TX_CTRL_WRAP  0x4000
+#define MAL_TX_CTRL_CM	  0x2000
+#define MAL_TX_CTRL_LAST  0x1000
+#define MAL_TX_CTRL_INTR  0x0400
+
+#define MAL_RX_CTRL_EMPTY 0x8000
+#define MAL_RX_CTRL_WRAP  0x4000
+#define MAL_RX_CTRL_CM	  0x2000
+#define MAL_RX_CTRL_LAST  0x1000
+#define MAL_RX_CTRL_FIRST 0x0800
+#define MAL_RX_CTRL_INTR  0x0400
+
+      /* Configuration Reg  */
+#define MAL_CR_MMSR	  0x80000000
+#define MAL_CR_PLBP_1	  0x00400000   /* lowsest is 00 */
+#define MAL_CR_PLBP_2	  0x00800000
+#define MAL_CR_PLBP_3	  0x00C00000   /* highest	*/
+#define MAL_CR_GA	  0x00200000
+#define MAL_CR_OA	  0x00100000
+#define MAL_CR_PLBLE	  0x00080000
+#define MAL_CR_PLBLT_1	0x00040000
+#define MAL_CR_PLBLT_2	0x00020000
+#define MAL_CR_PLBLT_3	0x00010000
+#define MAL_CR_PLBLT_4	0x00008000
+#define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */
+#define MAL_CR_PLBB	  0x00004000
+#define MAL_CR_OPBBL	  0x00000080
+#define MAL_CR_EOPIE	  0x00000004
+#define MAL_CR_LEA	  0x00000002
+#define MAL_CR_MSD	  0x00000001
+
+    /* Error Status Reg	   */
+#define MAL_ESR_EVB	  0x80000000
+#define MAL_ESR_CID	  0x40000000
+#define MAL_ESR_DE	  0x00100000
+#define MAL_ESR_ONE	  0x00080000
+#define MAL_ESR_OTE	  0x00040000
+#define MAL_ESR_OSE	  0x00020000
+#define MAL_ESR_PEIN	  0x00010000
+      /* same bit position as the IER */
+      /* VV			 VV   */
+#define MAL_ESR_DEI	  0x00000010
+#define MAL_ESR_ONEI	  0x00000008
+#define MAL_ESR_OTEI	  0x00000004
+#define MAL_ESR_OSEI	  0x00000002
+#define MAL_ESR_PBEI	  0x00000001
+      /* ^^			 ^^   */
+      /* Mal IER		      */
+#define MAL_IER_DE	  0x00000010
+#define MAL_IER_NE	  0x00000008
+#define MAL_IER_TE	  0x00000004
+#define MAL_IER_OPBE	  0x00000002
+#define MAL_IER_PLBE	  0x00000001
+
+/* MAL Channel Active Set and Reset Registers */
+#define MAL_TXRX_CASR	(0x80000000)
+
+#define MAL_TXRX_CASR_V(__x)  (__x)  /* Channel 0 shifts 0, channel 1 shifts 1, etc */
+
+
+/* MAL Buffer Descriptor structure */
+typedef struct {
+  short	 ctrl;		    /* MAL / Commac status control bits */
+  short	 data_len;	    /* Max length is 4K-1 (12 bits)	*/
+  char	*data_ptr;	    /* pointer to actual data buffer	*/
+} mal_desc_t;
+
+#endif
diff --git a/include/405gp_i2c.h b/include/405gp_i2c.h
new file mode 100755
index 0000000..5a9a497
--- /dev/null
+++ b/include/405gp_i2c.h
@@ -0,0 +1,64 @@
+#ifndef _405gp_i2c_h_
+#define _405gp_i2c_h_
+
+#define	   I2C_REGISTERS_BASE_ADDRESS 0xEF600500
+#define    IIC_MDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
+#define    IIC_SDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
+#define    IIC_LMADR	(I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
+#define    IIC_HMADR	(I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
+#define    IIC_CNTL	(I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
+#define    IIC_MDCNTL	(I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
+#define    IIC_STS	(I2C_REGISTERS_BASE_ADDRESS+IICSTS)
+#define    IIC_EXTSTS	(I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
+#define    IIC_LSADR	(I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
+#define    IIC_HSADR	(I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
+#define    IIC_CLKDIV	(I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
+#define    IIC_INTRMSK	(I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
+#define    IIC_XFRCNT	(I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
+#define    IIC_XTCNTLSS	(I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
+#define    IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
+
+/* MDCNTL Register Bit definition */
+#define    IIC_MDCNTL_HSCL 0x01
+#define    IIC_MDCNTL_EUBS 0x02
+#define    IIC_MDCNTL_EINT 0x04
+#define    IIC_MDCNTL_ESM  0x08
+#define    IIC_MDCNTL_FSM  0x10
+#define    IIC_MDCNTL_EGC  0x20
+#define    IIC_MDCNTL_FMDB 0x40
+#define    IIC_MDCNTL_FSDB 0x80
+
+/* CNTL Register Bit definition */
+#define    IIC_CNTL_PT     0x01
+#define    IIC_CNTL_READ   0x02
+#define    IIC_CNTL_CHT    0x04
+#define    IIC_CNTL_RPST   0x08
+/* bit 2/3 for Transfer count*/
+#define    IIC_CNTL_AMD    0x40
+#define    IIC_CNTL_HMT    0x80
+
+/* STS Register Bit definition */
+#define    IIC_STS_PT	   0X01
+#define    IIC_STS_IRQA    0x02
+#define    IIC_STS_ERR	   0X04
+#define    IIC_STS_SCMP    0x08
+#define    IIC_STS_MDBF    0x10
+#define    IIC_STS_MDBS    0X20
+#define    IIC_STS_SLPR    0x40
+#define    IIC_STS_SSS     0x80
+
+/* EXTSTS Register Bit definition */
+#define    IIC_EXTSTS_XFRA 0X01
+#define    IIC_EXTSTS_ICT  0X02
+#define    IIC_EXTSTS_LA   0X04
+
+/* XTCNTLSS Register Bit definition */
+#define    IIC_XTCNTLSS_SRST  0x01
+#define    IIC_XTCNTLSS_EPI   0x02
+#define    IIC_XTCNTLSS_SDBF  0x04
+#define    IIC_XTCNTLSS_SBDD  0x08
+#define    IIC_XTCNTLSS_SWS   0x10
+#define    IIC_XTCNTLSS_SWC   0x20
+#define    IIC_XTCNTLSS_SRS   0x40
+#define    IIC_XTCNTLSS_SRC   0x80
+#endif
diff --git a/include/405gp_pci.h b/include/405gp_pci.h
new file mode 100755
index 0000000..3c1adec
--- /dev/null
+++ b/include/405gp_pci.h
@@ -0,0 +1,52 @@
+#ifndef _405GP_PCI_H
+#define _405GP_PCI_H
+
+/*----------------------------------------------------------------------------+
+| 405GP PCI core memory map defines.
++----------------------------------------------------------------------------*/
+#define MIN_PCI_MEMADDR1    0x80000000
+#define MIN_PCI_MEMADDR2    0x00000000
+#define MIN_PLB_PCI_IOADDR  0xE8000000  /* PLB side of PCI I/O address space */
+#define MIN_PCI_PCI_IOADDR  0x00000000  /* PCI side of PCI I/O address space */
+#define MAX_PCI_DEVICES     32
+
+/*----------------------------------------------------------------------------+
+| Defines for the 405GP PCI Config address and data registers followed by
+| defines for the standard PCI device configuration header.
++----------------------------------------------------------------------------*/
+#define PCICFGADR       0xEEC00000
+#define PCICFGDATA      0xEEC00004
+
+#define PCIBUSNUM       0x40        /* 405GP specific parameters */
+#define PCISUBBUSNUM    0x41
+#define PCIDISCOUNT     0x42
+#define PCIBRDGOPT1     0x4A
+#define PCIBRDGOPT2     0x60
+
+/*----------------------------------------------------------------------------+
+| Defines for 405GP PCI Master local configuration regs.
++----------------------------------------------------------------------------*/
+#define PMM0LA          0xEF400000
+#define PMM0MA          0xEF400004
+#define PMM0PCILA       0xEF400008
+#define PMM0PCIHA       0xEF40000C
+#define PMM1LA          0xEF400010
+#define PMM1MA          0xEF400014
+#define PMM1PCILA       0xEF400018
+#define PMM1PCIHA       0xEF40001C
+#define PMM2LA          0xEF400020
+#define PMM2MA          0xEF400024
+#define PMM2PCILA       0xEF400028
+#define PMM2PCIHA       0xEF40002C
+
+/*----------------------------------------------------------------------------+
+| Defines for 405GP PCI Target local configuration regs.
++----------------------------------------------------------------------------*/
+#define PTM1MS          0xEF400030
+#define PTM1LA          0xEF400034
+#define PTM2MS          0xEF400038
+#define PTM2LA          0xEF40003C
+
+#define PCIDEVID_405GP 	0x0
+
+#endif
diff --git a/include/440_i2c.h b/include/440_i2c.h
new file mode 100755
index 0000000..9c90a9e
--- /dev/null
+++ b/include/440_i2c.h
@@ -0,0 +1,70 @@
+#ifndef _440_i2c_h_
+#define _440_i2c_h_
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define    I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
+#else
+#define    I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
+#endif /*CONFIG_440EP CONFIG_440GR*/
+
+#define	   I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
+#define    IIC_MDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
+#define    IIC_SDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
+#define    IIC_LMADR	(I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
+#define    IIC_HMADR	(I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
+#define    IIC_CNTL	(I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
+#define    IIC_MDCNTL	(I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
+#define    IIC_STS	(I2C_REGISTERS_BASE_ADDRESS+IICSTS)
+#define    IIC_EXTSTS	(I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
+#define    IIC_LSADR	(I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
+#define    IIC_HSADR	(I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
+#define    IIC_CLKDIV	(I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
+#define    IIC_INTRMSK	(I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
+#define    IIC_XFRCNT	(I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
+#define    IIC_XTCNTLSS	(I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
+#define    IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
+
+/* MDCNTL Register Bit definition */
+#define    IIC_MDCNTL_HSCL 0x01
+#define    IIC_MDCNTL_EUBS 0x02
+#define    IIC_MDCNTL_EINT 0x04
+#define    IIC_MDCNTL_ESM  0x08
+#define    IIC_MDCNTL_FSM  0x10
+#define    IIC_MDCNTL_EGC  0x20
+#define    IIC_MDCNTL_FMDB 0x40
+#define    IIC_MDCNTL_FSDB 0x80
+
+/* CNTL Register Bit definition */
+#define    IIC_CNTL_PT     0x01
+#define    IIC_CNTL_READ   0x02
+#define    IIC_CNTL_CHT    0x04
+#define    IIC_CNTL_RPST   0x08
+/* bit 2/3 for Transfer count*/
+#define    IIC_CNTL_AMD    0x40
+#define    IIC_CNTL_HMT    0x80
+
+/* STS Register Bit definition */
+#define    IIC_STS_PT	   0X01
+#define    IIC_STS_IRQA    0x02
+#define    IIC_STS_ERR	   0X04
+#define    IIC_STS_SCMP    0x08
+#define    IIC_STS_MDBF    0x10
+#define    IIC_STS_MDBS    0X20
+#define    IIC_STS_SLPR    0x40
+#define    IIC_STS_SSS     0x80
+
+/* EXTSTS Register Bit definition */
+#define    IIC_EXTSTS_XFRA 0X01
+#define    IIC_EXTSTS_ICT  0X02
+#define    IIC_EXTSTS_LA   0X04
+
+/* XTCNTLSS Register Bit definition */
+#define    IIC_XTCNTLSS_SRST  0x01
+#define    IIC_XTCNTLSS_EPI   0x02
+#define    IIC_XTCNTLSS_SDBF  0x04
+#define    IIC_XTCNTLSS_SBDD  0x08
+#define    IIC_XTCNTLSS_SWS   0x10
+#define    IIC_XTCNTLSS_SWC   0x20
+#define    IIC_XTCNTLSS_SRS   0x40
+#define    IIC_XTCNTLSS_SRC   0x80
+#endif
diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h
new file mode 100755
index 0000000..a628798
--- /dev/null
+++ b/include/74xx_7xx.h
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 74xx_7xx.h
+ *
+ * 74xx/7xx specific definitions
+ */
+
+#ifndef __MPC74XX_H__
+#define __MPC74XX_H__
+
+/*----------------------------------------------------------------
+ * Exception offsets (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET        0x0100      /* default system reset offset */
+
+/*----------------------------------------------------------------
+ * l2cr values
+ */
+#define l2cr		 1017
+
+#define L2CR_L2E         0x80000000 /* bit 0 - enable */
+#define L2CR_L2PE        0x40000000 /* bit 1 - data parity */
+#define L2CR_L2SIZ_2M    0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
+#define L2CR_L2SIZ_1M    0x30000000 /* ... 1MB */
+#define L2CR_L2SIZ_HM    0x20000000 /* ... 512K */
+#define L2CR_L2SIZ_QM    0x10000000 /* ... 256k */
+#define L2CR_L2CLK_1     0x02000000 /* bits 4-6 clock ratio div 1 */
+#define L2CR_L2CLK_1_5   0x04000000 /* bits 4-6 clock ratio div 1.5 */
+#define L2CR_L2CLK_2     0x08000000 /* bits 4-6 clock ratio div 2 */
+#define L2CR_L2CLK_2_5   0x0a000000 /* bits 4-6 clock ratio div 2.5 */
+#define L2CR_L2CLK_3     0x0c000000 /* bits 4-6 clock ratio div 3 */
+#define L2CR_L2CLK_3_5   0x06000000 /* bits 4-6 clock ratio div 3.5 */
+#define L2CR_L2CLK_4     0x0e000000 /* bits 4-6 clock ratio div 4 */
+#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
+#define L2CR_DO          0x00400000 /* bit 9 - enable caching of instr. in L2 */
+#define L2CR_L2I         0x00200000 /* bit 10 - global invalidate bit */
+#define L2CR_L2CTL       0x00100000 /* bit 11 - l2 ram control */
+#define L2CR_L2WT        0x00080000 /* bit 12 - l2 write-through */
+#define L2CR_TS          0x00040000 /* bit 13 - test support on */
+#define L2CR_TS_OFF      -L2CR_TS   /* bit 13 - test support off */
+#define L2CR_L2OH_5      0x00000000 /* bits 14-15 - output hold time = short */
+#define L2CR_L2OH_1      0x00010000 /* bits 14-15 - output hold time = medium */
+#define L2CR_L2OH_INV    0x00020000 /* bits 14-15 - output hold time = long */
+#define L2CR_L2IP        0x00000001 /* global invalidate in progress */
+
+/*----------------------------------------------------------------
+ * BAT settings.  Look in config_<BOARD>.h for the actual setup
+ */
+
+#define BATU_BL_128K            0x00000000
+#define BATU_BL_256K            0x00000004
+#define BATU_BL_512K            0x0000000c
+#define BATU_BL_1M              0x0000001c
+#define BATU_BL_2M              0x0000003c
+#define BATU_BL_4M              0x0000007c
+#define BATU_BL_8M              0x000000fc
+#define BATU_BL_16M             0x000001fc
+#define BATU_BL_32M             0x000003fc
+#define BATU_BL_64M             0x000007fc
+#define BATU_BL_128M            0x00000ffc
+#define BATU_BL_256M            0x00001ffc
+
+#define BATU_VS                 0x00000002
+#define BATU_VP                 0x00000001
+#define BATU_INVALID            0x00000000
+
+#define BATL_WRITETHROUGH       0x00000040
+#define BATL_CACHEINHIBIT       0x00000020
+#define BATL_MEMCOHERENCE	0x00000010
+#define BATL_GUARDEDSTORAGE     0x00000008
+#define BATL_NO_ACCESS		0x00000000
+
+#define BATL_PP_MSK		0x00000003
+#define BATL_PP_00		0x00000000 /* No access */
+#define BATL_PP_01		0x00000001 /* Read-only */
+#define BATL_PP_10		0x00000002 /* Read-write */
+#define BATL_PP_11		0x00000003
+
+#define BATL_PP_NO_ACCESS	BATL_PP_00
+#define BATL_PP_RO		BATL_PP_01
+#define BATL_PP_RW		BATL_PP_10
+
+#ifndef __ASSEMBLY__
+/* cpu ids we detect */
+typedef enum __cpu_t {
+	CPU_740, CPU_750,
+	CPU_740P, CPU_750P,
+	CPU_745, CPU_755,
+	CPU_750CX, CPU_750FX, CPU_750GX,
+	CPU_7400,
+	CPU_7410,
+	CPU_7450, CPU_7455, CPU_7457,
+	CPU_UNKNOWN} cpu_t;
+
+extern cpu_t get_cpu_type(void);
+
+#define l1icache_enable	icache_enable
+
+void l2cache_enable(void);
+void l1dcache_enable(void);
+
+static __inline__ unsigned long get_msr (void)
+{
+	unsigned long msr;
+	asm volatile("mfmsr %0" : "=r" (msr) :);
+	return msr;
+}
+
+static __inline__ void set_msr (unsigned long msr)
+{
+	asm volatile("mtmsr %0" : : "r" (msr));
+}
+
+static __inline__ unsigned long get_hid0 (void)
+{
+	unsigned long hid0;
+	asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
+	return hid0;
+}
+
+static __inline__ unsigned long get_hid1 (void)
+{
+	unsigned long hid1;
+	asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
+	return hid1;
+}
+
+static __inline__ void set_hid0 (unsigned long hid0)
+{
+	asm volatile("mtspr 1008, %0" : : "r" (hid0));
+}
+
+static __inline__ void set_hid1 (unsigned long hid1)
+{
+	asm volatile("mtspr 1009, %0" : : "r" (hid1));
+}
+
+#endif	/* __ASSEMBLY__ */
+#endif  /* __MPC74XX_H__ */
diff --git a/include/ACEX1K.h b/include/ACEX1K.h
new file mode 100755
index 0000000..f75c463
--- /dev/null
+++ b/include/ACEX1K.h
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2003
+ * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
+ *
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ACEX1K_H_
+#define _ACEX1K_H_
+
+#include <altera.h>
+
+extern int ACEX1K_load( Altera_desc *desc, void *image, size_t size );
+extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize );
+extern int ACEX1K_info( Altera_desc *desc );
+extern int ACEX1K_reloc( Altera_desc *desc, ulong reloc_off );
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	Altera_pre_fn		pre;
+	Altera_config_fn	config;
+	Altera_clk_fn		clk;
+	Altera_status_fn	status;
+	Altera_done_fn		done;
+	Altera_data_fn		data;
+	Altera_abort_fn		abort;
+	Altera_post_fn		post;
+	int			relocated;
+} Altera_ACEX1K_Passive_Serial_fns;
+
+/* Device Image Sizes
+ *********************************************************************/
+/* ACEX1K */
+/* FIXME: Which size do we mean?
+ * Datasheet says 1337000/8=167125Bytes,
+ * Filesize of an *.rbf file is 166965 Bytes
+ */
+#if 0
+#define Altera_EP1K100_SIZE  	1337000/8	/* 167125 Bytes */
+#endif
+#define Altera_EP1K100_SIZE  	(166965*8)
+
+/* Descriptor Macros
+ *********************************************************************/
+/* ACEX1K devices */
+#define Altera_EP1K100_DESC(iface, fn_table, cookie) \
+{ Altera_ACEX1K, iface, Altera_EP1K100_SIZE, fn_table, cookie }
+
+#endif /* _ACEX1K_H_ */
diff --git a/include/SA-1100.h b/include/SA-1100.h
new file mode 100755
index 0000000..9985783
--- /dev/null
+++ b/include/SA-1100.h
@@ -0,0 +1,2833 @@
+/*
+ *	FILE    	SA-1100.h
+ *
+ *	Version 	1.2
+ *	Author  	Copyright (c) Marc A. Viredaz, 1998
+ *	        	DEC Western Research Laboratory, Palo Alto, CA
+ *	Date    	January 1998 (April 1997)
+ *	System  	StrongARM SA-1100
+ *	Language	C or ARM Assembly
+ *	Purpose 	Definition of constants related to the StrongARM
+ *	        	SA-1100 microprocessor (Advanced RISC Machine (ARM)
+ *	        	architecture version 4). This file is based on the
+ *	        	StrongARM SA-1100 data sheet version 2.2.
+ *
+ *	        	Language-specific definitions are selected by the
+ *	        	macro "LANGUAGE", which should be defined as either
+ *	        	"C" (default) or "Assembly".
+ */
+
+
+#ifndef LANGUAGE
+# ifdef __ASSEMBLY__
+#  define LANGUAGE Assembly
+# else
+#  define LANGUAGE C
+# endif
+#endif
+
+#ifndef io_p2v
+#define io_p2v(PhAdd)	(PhAdd)
+#endif
+
+#include <asm/arch-sa1100/bitfield.h>
+
+#define C       	0
+#define Assembly	1
+
+
+#if LANGUAGE == C
+typedef unsigned short  Word16 ;
+typedef unsigned int    Word32 ;
+typedef Word32          Word ;
+typedef Word            Quad [4] ;
+typedef void            *Address ;
+typedef void            (*ExcpHndlr) (void) ;
+#endif /* LANGUAGE == C */
+
+
+/*
+ * Memory
+ */
+
+#define MemBnkSp	0x08000000	/* Memory Bank Space [byte]        */
+
+#define StMemBnkSp	MemBnkSp	/* Static Memory Bank Space [byte] */
+#define StMemBnk0Sp	StMemBnkSp	/* Static Memory Bank 0 Space      */
+					/* [byte]                          */
+#define StMemBnk1Sp	StMemBnkSp	/* Static Memory Bank 1 Space      */
+					/* [byte]                          */
+#define StMemBnk2Sp	StMemBnkSp	/* Static Memory Bank 2 Space      */
+					/* [byte]                          */
+#define StMemBnk3Sp	StMemBnkSp	/* Static Memory Bank 3 Space      */
+					/* [byte]                          */
+
+#define DRAMBnkSp	MemBnkSp	/* DRAM Bank Space [byte]          */
+#define DRAMBnk0Sp	DRAMBnkSp	/* DRAM Bank 0 Space [byte]        */
+#define DRAMBnk1Sp	DRAMBnkSp	/* DRAM Bank 1 Space [byte]        */
+#define DRAMBnk2Sp	DRAMBnkSp	/* DRAM Bank 2 Space [byte]        */
+#define DRAMBnk3Sp	DRAMBnkSp	/* DRAM Bank 3 Space [byte]        */
+
+#define ZeroMemSp	MemBnkSp	/* Zero Memory bank Space [byte]   */
+
+#define _StMemBnk(Nb)	        	/* Static Memory Bank [0..3]       */ \
+			(0x00000000 + (Nb)*StMemBnkSp)
+#define _StMemBnk0	_StMemBnk (0)	/* Static Memory Bank 0            */
+#define _StMemBnk1	_StMemBnk (1)	/* Static Memory Bank 1            */
+#define _StMemBnk2	_StMemBnk (2)	/* Static Memory Bank 2            */
+#define _StMemBnk3	_StMemBnk (3)	/* Static Memory Bank 3            */
+
+#if LANGUAGE == C
+typedef Quad    	StMemBnkType [StMemBnkSp/sizeof (Quad)] ;
+#define StMemBnk	        	/* Static Memory Bank [0..3]       */ \
+			((StMemBnkType *) io_p2v (_StMemBnk (0)))
+#define StMemBnk0	(StMemBnk [0])	/* Static Memory Bank 0            */
+#define StMemBnk1	(StMemBnk [1])	/* Static Memory Bank 1            */
+#define StMemBnk2	(StMemBnk [2])	/* Static Memory Bank 2            */
+#define StMemBnk3	(StMemBnk [3])	/* Static Memory Bank 3            */
+#endif /* LANGUAGE == C */
+
+#define _DRAMBnk(Nb)	        	/* DRAM Bank [0..3]                */ \
+			(0xC0000000 + (Nb)*DRAMBnkSp)
+#define _DRAMBnk0	_DRAMBnk (0)	/* DRAM Bank 0                     */
+#define _DRAMBnk1	_DRAMBnk (1)	/* DRAM Bank 1                     */
+#define _DRAMBnk2	_DRAMBnk (2)	/* DRAM Bank 2                     */
+#define _DRAMBnk3	_DRAMBnk (3)	/* DRAM Bank 3                     */
+
+#if LANGUAGE == C
+typedef Quad    	DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ;
+#define DRAMBnk 	        	/* DRAM Bank [0..3]                */ \
+			((DRAMBnkType *) io_p2v (_DRAMBnk (0)))
+#define DRAMBnk0	(DRAMBnk [0])	/* DRAM Bank 0                     */
+#define DRAMBnk1	(DRAMBnk [1])	/* DRAM Bank 1                     */
+#define DRAMBnk2	(DRAMBnk [2])	/* DRAM Bank 2                     */
+#define DRAMBnk3	(DRAMBnk [3])	/* DRAM Bank 3                     */
+#endif /* LANGUAGE == C */
+
+#define _ZeroMem	0xE0000000	/* Zero Memory bank                */
+
+#if LANGUAGE == C
+typedef Quad    	ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
+#define ZeroMem 	        	/* Zero Memory bank                */ \
+			(*((ZeroMemType *) io_p2v (_ZeroMem)))
+#endif /* LANGUAGE == C */
+
+
+/*
+ * Personal Computer Memory Card International Association (PCMCIA) sockets
+ */
+
+#define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
+#define PCMCIASp	(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]             */
+#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]         */
+#define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
+#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]      */
+
+#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]           */
+#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]       */
+#define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
+#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]    */
+
+#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]           */
+#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]       */
+#define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
+#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]    */
+
+#define _PCMCIA(Nb)	        	/* PCMCIA [0..1]                   */ \
+			(0x20000000 + (Nb)*PCMCIASp)
+#define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]               */
+#define _PCMCIAAttr(Nb)	        	/* PCMCIA Attribute [0..1]         */ \
+			(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
+#define _PCMCIAMem(Nb)	        	/* PCMCIA Memory [0..1]            */ \
+			(_PCMCIA (Nb) + 3*PCMCIAPrtSp)
+
+#define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0                        */
+#define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O                    */
+#define _PCMCIA0Attr	_PCMCIAAttr (0)	/* PCMCIA 0 Attribute              */
+#define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory                 */
+
+#define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1                        */
+#define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O                    */
+#define _PCMCIA1Attr	_PCMCIAAttr (1)	/* PCMCIA 1 Attribute              */
+#define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory                 */
+
+#if LANGUAGE == C
+
+typedef Quad    	PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ;
+typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
+
+#define PCMCIA0 	        	/* PCMCIA 0                        */ \
+			(*((PCMCIAType *) io_p2v (_PCMCIA0)))
+#define PCMCIA0IO	        	/* PCMCIA 0 I/O                    */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO)))
+#define PCMCIA0Attr	        	/* PCMCIA 0 Attribute              */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr)))
+#define PCMCIA0Mem	        	/* PCMCIA 0 Memory                 */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem)))
+
+#define PCMCIA1 	        	/* PCMCIA 1                        */ \
+			(*((PCMCIAType *) io_p2v (_PCMCIA1)))
+#define PCMCIA1IO	        	/* PCMCIA 1 I/O                    */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO)))
+#define PCMCIA1Attr	        	/* PCMCIA 1 Attribute              */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr)))
+#define PCMCIA1Mem	        	/* PCMCIA 1 Memory                 */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem)))
+
+#endif /* LANGUAGE == C */
+
+
+/*
+ * Universal Serial Bus (USB) Device Controller (UDC) control registers
+ *
+ * Registers
+ *    Ser0UDCCR 	Serial port 0 Universal Serial Bus (USB) Device
+ *              	Controller (UDC) Control Register (read/write).
+ *    Ser0UDCAR 	Serial port 0 Universal Serial Bus (USB) Device
+ *              	Controller (UDC) Address Register (read/write).
+ *    Ser0UDCOMP	Serial port 0 Universal Serial Bus (USB) Device
+ *              	Controller (UDC) Output Maximum Packet size register
+ *              	(read/write).
+ *    Ser0UDCIMP	Serial port 0 Universal Serial Bus (USB) Device
+ *              	Controller (UDC) Input Maximum Packet size register
+ *              	(read/write).
+ *    Ser0UDCCS0	Serial port 0 Universal Serial Bus (USB) Device
+ *              	Controller (UDC) Control/Status register end-point 0
+ *              	(read/write).
+ *    Ser0UDCCS1	Serial port 0 Universal Serial Bus (USB) Device
+ *              	Controller (UDC) Control/Status register end-point 1
+ *              	(output, read/write).
+ *    Ser0UDCCS2	Serial port 0 Universal Serial Bus (USB) Device
+ *              	Controller (UDC) Control/Status register end-point 2
+ *              	(input, read/write).
+ *    Ser0UDCD0 	Serial port 0 Universal Serial Bus (USB) Device
+ *              	Controller (UDC) Data register end-point 0
+ *              	(read/write).
+ *    Ser0UDCWC 	Serial port 0 Universal Serial Bus (USB) Device
+ *              	Controller (UDC) Write Count register end-point 0
+ *              	(read).
+ *    Ser0UDCDR 	Serial port 0 Universal Serial Bus (USB) Device
+ *              	Controller (UDC) Data Register (read/write).
+ *    Ser0UDCSR 	Serial port 0 Universal Serial Bus (USB) Device
+ *              	Controller (UDC) Status Register (read/write).
+ */
+
+#define _Ser0UDCCR	0x80000000	/* Ser. port 0 UDC Control Reg.    */
+#define _Ser0UDCAR	0x80000004	/* Ser. port 0 UDC Address Reg.    */
+#define _Ser0UDCOMP	0x80000008	/* Ser. port 0 UDC Output Maximum  */
+					/* Packet size reg.                */
+#define _Ser0UDCIMP	0x8000000C	/* Ser. port 0 UDC Input Maximum   */
+					/* Packet size reg.                */
+#define _Ser0UDCCS0	0x80000010	/* Ser. port 0 UDC Control/Status  */
+					/* reg. end-point 0                */
+#define _Ser0UDCCS1	0x80000014	/* Ser. port 0 UDC Control/Status  */
+					/* reg. end-point 1 (output)       */
+#define _Ser0UDCCS2	0x80000018	/* Ser. port 0 UDC Control/Status  */
+					/* reg. end-point 2 (input)        */
+#define _Ser0UDCD0	0x8000001C	/* Ser. port 0 UDC Data reg.       */
+					/* end-point 0                     */
+#define _Ser0UDCWC	0x80000020	/* Ser. port 0 UDC Write Count     */
+					/* reg. end-point 0                */
+#define _Ser0UDCDR	0x80000028	/* Ser. port 0 UDC Data Reg.       */
+#define _Ser0UDCSR	0x80000030	/* Ser. port 0 UDC Status Reg.     */
+
+#if LANGUAGE == C
+#define Ser0UDCCR	        	/* Ser. port 0 UDC Control Reg.    */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCCR)))
+#define Ser0UDCAR	        	/* Ser. port 0 UDC Address Reg.    */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCAR)))
+#define Ser0UDCOMP	        	/* Ser. port 0 UDC Output Maximum  */ \
+					/* Packet size reg.                */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCOMP)))
+#define Ser0UDCIMP	        	/* Ser. port 0 UDC Input Maximum   */ \
+					/* Packet size reg.                */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCIMP)))
+#define Ser0UDCCS0	        	/* Ser. port 0 UDC Control/Status  */ \
+					/* reg. end-point 0                */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCCS0)))
+#define Ser0UDCCS1	        	/* Ser. port 0 UDC Control/Status  */ \
+					/* reg. end-point 1 (output)       */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCCS1)))
+#define Ser0UDCCS2	        	/* Ser. port 0 UDC Control/Status  */ \
+					/* reg. end-point 2 (input)        */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCCS2)))
+#define Ser0UDCD0	        	/* Ser. port 0 UDC Data reg.       */ \
+					/* end-point 0                     */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCD0)))
+#define Ser0UDCWC	        	/* Ser. port 0 UDC Write Count     */ \
+					/* reg. end-point 0                */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCWC)))
+#define Ser0UDCDR	        	/* Ser. port 0 UDC Data Reg.       */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCDR)))
+#define Ser0UDCSR	        	/* Ser. port 0 UDC Status Reg.     */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCSR)))
+#endif /* LANGUAGE == C */
+
+#define UDCCR_UDD	0x00000001	/* UDC Disable                     */
+#define UDCCR_UDA	0x00000002	/* UDC Active (read)               */
+#define UDCCR_RESIM	0x00000004	/* Resume Interrupt Mask, per errata */
+#define UDCCR_EIM	0x00000008	/* End-point 0 Interrupt Mask      */
+					/* (disable)                       */
+#define UDCCR_RIM	0x00000010	/* Receive Interrupt Mask          */
+					/* (disable)                       */
+#define UDCCR_TIM	0x00000020	/* Transmit Interrupt Mask         */
+					/* (disable)                       */
+#define UDCCR_SRM	0x00000040	/* Suspend/Resume interrupt Mask   */
+					/* (disable)                       */
+#define UDCCR_SUSIM	UDCCR_SRM	/* Per errata, SRM just masks suspend */
+#define UDCCR_REM	0x00000080	/* REset interrupt Mask (disable)  */
+
+#define UDCAR_ADD	Fld (7, 0)	/* function ADDress                */
+
+#define UDCOMP_OUTMAXP	Fld (8, 0)	/* OUTput MAXimum Packet size - 1  */
+					/* [byte]                          */
+#define UDCOMP_OutMaxPkt(Size)  	/* Output Maximum Packet size      */ \
+					/* [1..256 byte]                   */ \
+			(((Size) - 1) << FShft (UDCOMP_OUTMAXP))
+
+#define UDCIMP_INMAXP	Fld (8, 0)	/* INput MAXimum Packet size - 1   */
+					/* [byte]                          */
+#define UDCIMP_InMaxPkt(Size)   	/* Input Maximum Packet size       */ \
+					/* [1..256 byte]                   */ \
+			(((Size) - 1) << FShft (UDCIMP_INMAXP))
+
+#define UDCCS0_OPR	0x00000001	/* Output Packet Ready (read)      */
+#define UDCCS0_IPR	0x00000002	/* Input Packet Ready              */
+#define UDCCS0_SST	0x00000004	/* Sent STall                      */
+#define UDCCS0_FST	0x00000008	/* Force STall                     */
+#define UDCCS0_DE	0x00000010	/* Data End                        */
+#define UDCCS0_SE	0x00000020	/* Setup End (read)                */
+#define UDCCS0_SO	0x00000040	/* Serviced Output packet ready    */
+					/* (write)                         */
+#define UDCCS0_SSE	0x00000080	/* Serviced Setup End (write)      */
+
+#define UDCCS1_RFS	0x00000001	/* Receive FIFO 12-bytes or more   */
+					/* Service request (read)          */
+#define UDCCS1_RPC	0x00000002	/* Receive Packet Complete         */
+#define UDCCS1_RPE	0x00000004	/* Receive Packet Error (read)     */
+#define UDCCS1_SST	0x00000008	/* Sent STall                      */
+#define UDCCS1_FST	0x00000010	/* Force STall                     */
+#define UDCCS1_RNE	0x00000020	/* Receive FIFO Not Empty (read)   */
+
+#define UDCCS2_TFS	0x00000001	/* Transmit FIFO 8-bytes or less   */
+					/* Service request (read)          */
+#define UDCCS2_TPC	0x00000002	/* Transmit Packet Complete        */
+#define UDCCS2_TPE	0x00000004	/* Transmit Packet Error (read)    */
+#define UDCCS2_TUR	0x00000008	/* Transmit FIFO Under-Run         */
+#define UDCCS2_SST	0x00000010	/* Sent STall                      */
+#define UDCCS2_FST	0x00000020	/* Force STall                     */
+
+#define UDCD0_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
+
+#define UDCWC_WC	Fld (4, 0)	/* Write Count                     */
+
+#define UDCDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
+
+#define UDCSR_EIR	0x00000001	/* End-point 0 Interrupt Request   */
+#define UDCSR_RIR	0x00000002	/* Receive Interrupt Request       */
+#define UDCSR_TIR	0x00000004	/* Transmit Interrupt Request      */
+#define UDCSR_SUSIR	0x00000008	/* SUSpend Interrupt Request       */
+#define UDCSR_RESIR	0x00000010	/* RESume Interrupt Request        */
+#define UDCSR_RSTIR	0x00000020	/* ReSeT Interrupt Request         */
+
+
+/*
+ * Universal Asynchronous Receiver/Transmitter (UART) control registers
+ *
+ * Registers
+ *    Ser1UTCR0 	Serial port 1 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Control Register 0
+ *              	(read/write).
+ *    Ser1UTCR1 	Serial port 1 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Control Register 1
+ *              	(read/write).
+ *    Ser1UTCR2 	Serial port 1 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Control Register 2
+ *              	(read/write).
+ *    Ser1UTCR3 	Serial port 1 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Control Register 3
+ *              	(read/write).
+ *    Ser1UTDR  	Serial port 1 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Data Register
+ *              	(read/write).
+ *    Ser1UTSR0 	Serial port 1 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Status Register 0
+ *              	(read/write).
+ *    Ser1UTSR1 	Serial port 1 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Status Register 1 (read).
+ *
+ *    Ser2UTCR0 	Serial port 2 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Control Register 0
+ *              	(read/write).
+ *    Ser2UTCR1 	Serial port 2 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Control Register 1
+ *              	(read/write).
+ *    Ser2UTCR2 	Serial port 2 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Control Register 2
+ *              	(read/write).
+ *    Ser2UTCR3 	Serial port 2 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Control Register 3
+ *              	(read/write).
+ *    Ser2UTCR4 	Serial port 2 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Control Register 4
+ *              	(read/write).
+ *    Ser2UTDR  	Serial port 2 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Data Register
+ *              	(read/write).
+ *    Ser2UTSR0 	Serial port 2 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Status Register 0
+ *              	(read/write).
+ *    Ser2UTSR1 	Serial port 2 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Status Register 1 (read).
+ *
+ *    Ser3UTCR0 	Serial port 3 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Control Register 0
+ *              	(read/write).
+ *    Ser3UTCR1 	Serial port 3 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Control Register 1
+ *              	(read/write).
+ *    Ser3UTCR2 	Serial port 3 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Control Register 2
+ *              	(read/write).
+ *    Ser3UTCR3 	Serial port 3 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Control Register 3
+ *              	(read/write).
+ *    Ser3UTDR  	Serial port 3 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Data Register
+ *              	(read/write).
+ *    Ser3UTSR0 	Serial port 3 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Status Register 0
+ *              	(read/write).
+ *    Ser3UTSR1 	Serial port 3 Universal Asynchronous
+ *              	Receiver/Transmitter (UART) Status Register 1 (read).
+ *
+ * Clocks
+ *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
+ *              	or 3.5795 MHz).
+ *    fua, Tua  	Frequency, period of the UART communication.
+ */
+
+#define _UTCR0(Nb)	        	/* UART Control Reg. 0 [1..3]      */ \
+			(0x80010000 + ((Nb) - 1)*0x00020000)
+#define _UTCR1(Nb)	        	/* UART Control Reg. 1 [1..3]      */ \
+			(0x80010004 + ((Nb) - 1)*0x00020000)
+#define _UTCR2(Nb)	        	/* UART Control Reg. 2 [1..3]      */ \
+			(0x80010008 + ((Nb) - 1)*0x00020000)
+#define _UTCR3(Nb)	        	/* UART Control Reg. 3 [1..3]      */ \
+			(0x8001000C + ((Nb) - 1)*0x00020000)
+#define _UTCR4(Nb)	        	/* UART Control Reg. 4 [2]         */ \
+			(0x80010010 + ((Nb) - 1)*0x00020000)
+#define _UTDR(Nb)	        	/* UART Data Reg. [1..3]           */ \
+			(0x80010014 + ((Nb) - 1)*0x00020000)
+#define _UTSR0(Nb)	        	/* UART Status Reg. 0 [1..3]       */ \
+			(0x8001001C + ((Nb) - 1)*0x00020000)
+#define _UTSR1(Nb)	        	/* UART Status Reg. 1 [1..3]       */ \
+			(0x80010020 + ((Nb) - 1)*0x00020000)
+
+#define _Ser1UTCR0	_UTCR0 (1)	/* Ser. port 1 UART Control Reg. 0 */
+#define _Ser1UTCR1	_UTCR1 (1)	/* Ser. port 1 UART Control Reg. 1 */
+#define _Ser1UTCR2	_UTCR2 (1)	/* Ser. port 1 UART Control Reg. 2 */
+#define _Ser1UTCR3	_UTCR3 (1)	/* Ser. port 1 UART Control Reg. 3 */
+#define _Ser1UTDR	_UTDR (1)	/* Ser. port 1 UART Data Reg.      */
+#define _Ser1UTSR0	_UTSR0 (1)	/* Ser. port 1 UART Status Reg. 0  */
+#define _Ser1UTSR1	_UTSR1 (1)	/* Ser. port 1 UART Status Reg. 1  */
+
+#define _Ser2UTCR0	_UTCR0 (2)	/* Ser. port 2 UART Control Reg. 0 */
+#define _Ser2UTCR1	_UTCR1 (2)	/* Ser. port 2 UART Control Reg. 1 */
+#define _Ser2UTCR2	_UTCR2 (2)	/* Ser. port 2 UART Control Reg. 2 */
+#define _Ser2UTCR3	_UTCR3 (2)	/* Ser. port 2 UART Control Reg. 3 */
+#define _Ser2UTCR4	_UTCR4 (2)	/* Ser. port 2 UART Control Reg. 4 */
+#define _Ser2UTDR	_UTDR (2)	/* Ser. port 2 UART Data Reg.      */
+#define _Ser2UTSR0	_UTSR0 (2)	/* Ser. port 2 UART Status Reg. 0  */
+#define _Ser2UTSR1	_UTSR1 (2)	/* Ser. port 2 UART Status Reg. 1  */
+
+#define _Ser3UTCR0	_UTCR0 (3)	/* Ser. port 3 UART Control Reg. 0 */
+#define _Ser3UTCR1	_UTCR1 (3)	/* Ser. port 3 UART Control Reg. 1 */
+#define _Ser3UTCR2	_UTCR2 (3)	/* Ser. port 3 UART Control Reg. 2 */
+#define _Ser3UTCR3	_UTCR3 (3)	/* Ser. port 3 UART Control Reg. 3 */
+#define _Ser3UTDR	_UTDR (3)	/* Ser. port 3 UART Data Reg.      */
+#define _Ser3UTSR0	_UTSR0 (3)	/* Ser. port 3 UART Status Reg. 0  */
+#define _Ser3UTSR1	_UTSR1 (3)	/* Ser. port 3 UART Status Reg. 1  */
+
+#if LANGUAGE == C
+
+#define Ser1UTCR0	        	/* Ser. port 1 UART Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser1UTCR0)))
+#define Ser1UTCR1	        	/* Ser. port 1 UART Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser1UTCR1)))
+#define Ser1UTCR2	        	/* Ser. port 1 UART Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser1UTCR2)))
+#define Ser1UTCR3	        	/* Ser. port 1 UART Control Reg. 3 */ \
+			(*((volatile Word *) io_p2v (_Ser1UTCR3)))
+#define Ser1UTDR	        	/* Ser. port 1 UART Data Reg.      */ \
+			(*((volatile Word *) io_p2v (_Ser1UTDR)))
+#define Ser1UTSR0	        	/* Ser. port 1 UART Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser1UTSR0)))
+#define Ser1UTSR1	        	/* Ser. port 1 UART Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser1UTSR1)))
+
+#define Ser2UTCR0	        	/* Ser. port 2 UART Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR0)))
+#define Ser2UTCR1	        	/* Ser. port 2 UART Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR1)))
+#define Ser2UTCR2	        	/* Ser. port 2 UART Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR2)))
+#define Ser2UTCR3	        	/* Ser. port 2 UART Control Reg. 3 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR3)))
+#define Ser2UTCR4	        	/* Ser. port 2 UART Control Reg. 4 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR4)))
+#define Ser2UTDR	        	/* Ser. port 2 UART Data Reg.      */ \
+			(*((volatile Word *) io_p2v (_Ser2UTDR)))
+#define Ser2UTSR0	        	/* Ser. port 2 UART Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser2UTSR0)))
+#define Ser2UTSR1	        	/* Ser. port 2 UART Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser2UTSR1)))
+
+#define Ser3UTCR0	        	/* Ser. port 3 UART Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser3UTCR0)))
+#define Ser3UTCR1	        	/* Ser. port 3 UART Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser3UTCR1)))
+#define Ser3UTCR2	        	/* Ser. port 3 UART Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser3UTCR2)))
+#define Ser3UTCR3	        	/* Ser. port 3 UART Control Reg. 3 */ \
+			(*((volatile Word *) io_p2v (_Ser3UTCR3)))
+#define Ser3UTDR	        	/* Ser. port 3 UART Data Reg.      */ \
+			(*((volatile Word *) io_p2v (_Ser3UTDR)))
+#define Ser3UTSR0	        	/* Ser. port 3 UART Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser3UTSR0)))
+#define Ser3UTSR1	        	/* Ser. port 3 UART Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser3UTSR1)))
+
+#elif LANGUAGE == Assembly
+#define Ser1UTCR0	( io_p2v (_Ser1UTCR0))
+#define Ser1UTCR1	( io_p2v (_Ser1UTCR1))
+#define Ser1UTCR2	( io_p2v (_Ser1UTCR2))
+#define Ser1UTCR3	( io_p2v (_Ser1UTCR3))
+#define Ser1UTDR	( io_p2v (_Ser1UTDR))
+#define Ser1UTSR0	( io_p2v (_Ser1UTSR0))
+#define Ser1UTSR1	( io_p2v (_Ser1UTSR1))
+
+#define Ser2UTCR0	( io_p2v (_Ser2UTCR0))
+#define Ser2UTCR1	( io_p2v (_Ser2UTCR1))
+#define Ser2UTCR2	( io_p2v (_Ser2UTCR2))
+#define Ser2UTCR3	( io_p2v (_Ser2UTCR3))
+#define Ser2UTCR4	( io_p2v (_Ser2UTCR4))
+#define Ser2UTDR	( io_p2v (_Ser2UTDR))
+#define Ser2UTSR0	( io_p2v (_Ser2UTSR0))
+#define Ser2UTSR1	( io_p2v (_Ser2UTSR1))
+
+#define Ser3UTCR0	( io_p2v (_Ser3UTCR0))
+#define Ser3UTCR1	( io_p2v (_Ser3UTCR1))
+#define Ser3UTCR2	( io_p2v (_Ser3UTCR2))
+#define Ser3UTCR3	( io_p2v (_Ser3UTCR3))
+#define Ser3UTDR	( io_p2v (_Ser3UTDR))
+#define Ser3UTSR0	( io_p2v (_Ser3UTSR0))
+#define Ser3UTSR1	( io_p2v (_Ser3UTSR1))
+
+#endif /* LANGUAGE == C */
+
+#define UTCR0_PE	0x00000001	/* Parity Enable                   */
+#define UTCR0_OES	0x00000002	/* Odd/Even parity Select          */
+#define UTCR0_OddPar	(UTCR0_OES*0)	/*  Odd Parity                     */
+#define UTCR0_EvenPar	(UTCR0_OES*1)	/*  Even Parity                    */
+#define UTCR0_SBS	0x00000004	/* Stop Bit Select                 */
+#define UTCR0_1StpBit	(UTCR0_SBS*0)	/*  1 Stop Bit per frame           */
+#define UTCR0_2StpBit	(UTCR0_SBS*1)	/*  2 Stop Bits per frame          */
+#define UTCR0_DSS	0x00000008	/* Data Size Select                */
+#define UTCR0_7BitData	(UTCR0_DSS*0)	/*  7-Bit Data                     */
+#define UTCR0_8BitData	(UTCR0_DSS*1)	/*  8-Bit Data                     */
+#define UTCR0_SCE	0x00000010	/* Sample Clock Enable             */
+					/* (ser. port 1: GPIO [18],        */
+					/* ser. port 3: GPIO [20])         */
+#define UTCR0_RCE	0x00000020	/* Receive Clock Edge select       */
+#define UTCR0_RcRsEdg	(UTCR0_RCE*0)	/*  Receive clock Rising-Edge      */
+#define UTCR0_RcFlEdg	(UTCR0_RCE*1)	/*  Receive clock Falling-Edge     */
+#define UTCR0_TCE	0x00000040	/* Transmit Clock Edge select      */
+#define UTCR0_TrRsEdg	(UTCR0_TCE*0)	/*  Transmit clock Rising-Edge     */
+#define UTCR0_TrFlEdg	(UTCR0_TCE*1)	/*  Transmit clock Falling-Edge    */
+#define UTCR0_Ser2IrDA	        	/* Ser. port 2 IrDA settings       */ \
+			(UTCR0_1StpBit + UTCR0_8BitData)
+
+#define UTCR1_BRD	Fld (4, 0)	/* Baud Rate Divisor/16 - 1 [11:8] */
+#define UTCR2_BRD	Fld (8, 0)	/* Baud Rate Divisor/16 - 1  [7:0] */
+					/* fua = fxtl/(16*(BRD[11:0] + 1)) */
+					/* Tua = 16*(BRD [11:0] + 1)*Txtl  */
+#define UTCR1_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \
+			(((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
+			 FShft (UTCR1_BRD))
+#define UTCR2_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \
+			(((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
+			 FShft (UTCR2_BRD))
+					/*  fua = fxtl/(16*Floor (Div/16)) */
+					/*  Tua = 16*Floor (Div/16)*Txtl   */
+#define UTCR1_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \
+			(((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
+			 FShft (UTCR1_BRD))
+#define UTCR2_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \
+			(((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
+			 FShft (UTCR2_BRD))
+					/*  fua = fxtl/(16*Ceil (Div/16))  */
+					/*  Tua = 16*Ceil (Div/16)*Txtl    */
+
+#define UTCR3_RXE	0x00000001	/* Receive Enable                  */
+#define UTCR3_TXE	0x00000002	/* Transmit Enable                 */
+#define UTCR3_BRK	0x00000004	/* BReaK mode                      */
+#define UTCR3_RIE	0x00000008	/* Receive FIFO 1/3-to-2/3-full or */
+					/* more Interrupt Enable           */
+#define UTCR3_TIE	0x00000010	/* Transmit FIFO 1/2-full or less  */
+					/* Interrupt Enable                */
+#define UTCR3_LBM	0x00000020	/* Look-Back Mode                  */
+#define UTCR3_Ser2IrDA	        	/* Ser. port 2 IrDA settings (RIE, */ \
+					/* TIE, LBM can be set or cleared) */ \
+			(UTCR3_RXE + UTCR3_TXE)
+
+#define UTCR4_HSE	0x00000001	/* Hewlett-Packard Serial InfraRed */
+					/* (HP-SIR) modulation Enable      */
+#define UTCR4_NRZ	(UTCR4_HSE*0)	/*  Non-Return to Zero modulation  */
+#define UTCR4_HPSIR	(UTCR4_HSE*1)	/*  HP-SIR modulation              */
+#define UTCR4_LPM	0x00000002	/* Low-Power Mode                  */
+#define UTCR4_Z3_16Bit	(UTCR4_LPM*0)	/*  Zero pulse = 3/16 Bit time     */
+#define UTCR4_Z1_6us	(UTCR4_LPM*1)	/*  Zero pulse = 1.6 us            */
+
+#define UTDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
+#if 0           	        	/* Hidden receive FIFO bits        */
+#define UTDR_PRE	0x00000100	/*  receive PaRity Error (read)    */
+#define UTDR_FRE	0x00000200	/*  receive FRaming Error (read)   */
+#define UTDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
+#endif /* 0 */
+
+#define UTSR0_TFS	0x00000001	/* Transmit FIFO 1/2-full or less  */
+					/* Service request (read)          */
+#define UTSR0_RFS	0x00000002	/* Receive FIFO 1/3-to-2/3-full or */
+					/* more Service request (read)     */
+#define UTSR0_RID	0x00000004	/* Receiver IDle                   */
+#define UTSR0_RBB	0x00000008	/* Receive Beginning of Break      */
+#define UTSR0_REB	0x00000010	/* Receive End of Break            */
+#define UTSR0_EIF	0x00000020	/* Error In FIFO (read)            */
+
+#define UTSR1_TBY	0x00000001	/* Transmitter BusY (read)         */
+#define UTSR1_RNE	0x00000002	/* Receive FIFO Not Empty (read)   */
+#define UTSR1_TNF	0x00000004	/* Transmit FIFO Not Full (read)   */
+#define UTSR1_PRE	0x00000008	/* receive PaRity Error (read)     */
+#define UTSR1_FRE	0x00000010	/* receive FRaming Error (read)    */
+#define UTSR1_ROR	0x00000020	/* Receive FIFO Over-Run (read)    */
+
+
+/*
+ * Synchronous Data Link Controller (SDLC) control registers
+ *
+ * Registers
+ *    Ser1SDCR0 	Serial port 1 Synchronous Data Link Controller (SDLC)
+ *              	Control Register 0 (read/write).
+ *    Ser1SDCR1 	Serial port 1 Synchronous Data Link Controller (SDLC)
+ *              	Control Register 1 (read/write).
+ *    Ser1SDCR2 	Serial port 1 Synchronous Data Link Controller (SDLC)
+ *              	Control Register 2 (read/write).
+ *    Ser1SDCR3 	Serial port 1 Synchronous Data Link Controller (SDLC)
+ *              	Control Register 3 (read/write).
+ *    Ser1SDCR4 	Serial port 1 Synchronous Data Link Controller (SDLC)
+ *              	Control Register 4 (read/write).
+ *    Ser1SDDR  	Serial port 1 Synchronous Data Link Controller (SDLC)
+ *              	Data Register (read/write).
+ *    Ser1SDSR0 	Serial port 1 Synchronous Data Link Controller (SDLC)
+ *              	Status Register 0 (read/write).
+ *    Ser1SDSR1 	Serial port 1 Synchronous Data Link Controller (SDLC)
+ *              	Status Register 1 (read/write).
+ *
+ * Clocks
+ *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
+ *              	or 3.5795 MHz).
+ *    fsd, Tsd  	Frequency, period of the SDLC communication.
+ */
+
+#define _Ser1SDCR0	0x80020060	/* Ser. port 1 SDLC Control Reg. 0 */
+#define _Ser1SDCR1	0x80020064	/* Ser. port 1 SDLC Control Reg. 1 */
+#define _Ser1SDCR2	0x80020068	/* Ser. port 1 SDLC Control Reg. 2 */
+#define _Ser1SDCR3	0x8002006C	/* Ser. port 1 SDLC Control Reg. 3 */
+#define _Ser1SDCR4	0x80020070	/* Ser. port 1 SDLC Control Reg. 4 */
+#define _Ser1SDDR	0x80020078	/* Ser. port 1 SDLC Data Reg.      */
+#define _Ser1SDSR0	0x80020080	/* Ser. port 1 SDLC Status Reg. 0  */
+#define _Ser1SDSR1	0x80020084	/* Ser. port 1 SDLC Status Reg. 1  */
+
+#if LANGUAGE == C
+#define Ser1SDCR0	        	/* Ser. port 1 SDLC Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR0)))
+#define Ser1SDCR1	        	/* Ser. port 1 SDLC Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR1)))
+#define Ser1SDCR2	        	/* Ser. port 1 SDLC Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR2)))
+#define Ser1SDCR3	        	/* Ser. port 1 SDLC Control Reg. 3 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR3)))
+#define Ser1SDCR4	        	/* Ser. port 1 SDLC Control Reg. 4 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR4)))
+#define Ser1SDDR	        	/* Ser. port 1 SDLC Data Reg.      */ \
+			(*((volatile Word *) io_p2v (_Ser1SDDR)))
+#define Ser1SDSR0	        	/* Ser. port 1 SDLC Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser1SDSR0)))
+#define Ser1SDSR1	        	/* Ser. port 1 SDLC Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser1SDSR1)))
+#endif /* LANGUAGE == C */
+
+#define SDCR0_SUS	0x00000001	/* SDLC/UART Select                */
+#define SDCR0_SDLC	(SDCR0_SUS*0)	/*  SDLC mode (TXD1 & RXD1)        */
+#define SDCR0_UART	(SDCR0_SUS*1)	/*  UART mode (TXD1 & RXD1)        */
+#define SDCR0_SDF	0x00000002	/* Single/Double start Flag select */
+#define SDCR0_SglFlg	(SDCR0_SDF*0)	/*  Single start Flag              */
+#define SDCR0_DblFlg	(SDCR0_SDF*1)	/*  Double start Flag              */
+#define SDCR0_LBM	0x00000004	/* Look-Back Mode                  */
+#define SDCR0_BMS	0x00000008	/* Bit Modulation Select           */
+#define SDCR0_FM0	(SDCR0_BMS*0)	/*  Freq. Modulation zero (0)      */
+#define SDCR0_NRZ	(SDCR0_BMS*1)	/*  Non-Return to Zero modulation  */
+#define SDCR0_SCE	0x00000010	/* Sample Clock Enable (GPIO [16]) */
+#define SDCR0_SCD	0x00000020	/* Sample Clock Direction select   */
+					/* (GPIO [16])                     */
+#define SDCR0_SClkIn	(SDCR0_SCD*0)	/*  Sample Clock Input             */
+#define SDCR0_SClkOut	(SDCR0_SCD*1)	/*  Sample Clock Output            */
+#define SDCR0_RCE	0x00000040	/* Receive Clock Edge select       */
+#define SDCR0_RcRsEdg	(SDCR0_RCE*0)	/*  Receive clock Rising-Edge      */
+#define SDCR0_RcFlEdg	(SDCR0_RCE*1)	/*  Receive clock Falling-Edge     */
+#define SDCR0_TCE	0x00000080	/* Transmit Clock Edge select      */
+#define SDCR0_TrRsEdg	(SDCR0_TCE*0)	/*  Transmit clock Rising-Edge     */
+#define SDCR0_TrFlEdg	(SDCR0_TCE*1)	/*  Transmit clock Falling-Edge    */
+
+#define SDCR1_AAF	0x00000001	/* Abort After Frame enable        */
+					/* (GPIO [17])                     */
+#define SDCR1_TXE	0x00000002	/* Transmit Enable                 */
+#define SDCR1_RXE	0x00000004	/* Receive Enable                  */
+#define SDCR1_RIE	0x00000008	/* Receive FIFO 1/3-to-2/3-full or */
+					/* more Interrupt Enable           */
+#define SDCR1_TIE	0x00000010	/* Transmit FIFO 1/2-full or less  */
+					/* Interrupt Enable                */
+#define SDCR1_AME	0x00000020	/* Address Match Enable            */
+#define SDCR1_TUS	0x00000040	/* Transmit FIFO Under-run Select  */
+#define SDCR1_EFrmURn	(SDCR1_TUS*0)	/*  End Frame on Under-Run         */
+#define SDCR1_AbortURn	(SDCR1_TUS*1)	/*  Abort on Under-Run             */
+#define SDCR1_RAE	0x00000080	/* Receive Abort interrupt Enable  */
+
+#define SDCR2_AMV	Fld (8, 0)	/* Address Match Value             */
+
+#define SDCR3_BRD	Fld (4, 0)	/* Baud Rate Divisor/16 - 1 [11:8] */
+#define SDCR4_BRD	Fld (8, 0)	/* Baud Rate Divisor/16 - 1  [7:0] */
+					/* fsd = fxtl/(16*(BRD[11:0] + 1)) */
+					/* Tsd = 16*(BRD[11:0] + 1)*Txtl   */
+#define SDCR3_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \
+			(((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
+			 FShft (SDCR3_BRD))
+#define SDCR4_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \
+			(((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
+			 FShft (SDCR4_BRD))
+					/*  fsd = fxtl/(16*Floor (Div/16)) */
+					/*  Tsd = 16*Floor (Div/16)*Txtl   */
+#define SDCR3_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \
+			(((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
+			 FShft (SDCR3_BRD))
+#define SDCR4_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \
+			(((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
+			 FShft (SDCR4_BRD))
+					/*  fsd = fxtl/(16*Ceil (Div/16))  */
+					/*  Tsd = 16*Ceil (Div/16)*Txtl    */
+
+#define SDDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
+#if 0           	        	/* Hidden receive FIFO bits        */
+#define SDDR_EOF	0x00000100	/*  receive End-Of-Frame (read)    */
+#define SDDR_CRE	0x00000200	/*  receive CRC Error (read)       */
+#define SDDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
+#endif /* 0 */
+
+#define SDSR0_EIF	0x00000001	/* Error In FIFO (read)            */
+#define SDSR0_TUR	0x00000002	/* Transmit FIFO Under-Run         */
+#define SDSR0_RAB	0x00000004	/* Receive ABort                   */
+#define SDSR0_TFS	0x00000008	/* Transmit FIFO 1/2-full or less  */
+					/* Service request (read)          */
+#define SDSR0_RFS	0x00000010	/* Receive FIFO 1/3-to-2/3-full or */
+					/* more Service request (read)     */
+
+#define SDSR1_RSY	0x00000001	/* Receiver SYnchronized (read)    */
+#define SDSR1_TBY	0x00000002	/* Transmitter BusY (read)         */
+#define SDSR1_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
+#define SDSR1_TNF	0x00000008	/* Transmit FIFO Not Full (read)   */
+#define SDSR1_RTD	0x00000010	/* Receive Transition Detected     */
+#define SDSR1_EOF	0x00000020	/* receive End-Of-Frame (read)     */
+#define SDSR1_CRE	0x00000040	/* receive CRC Error (read)        */
+#define SDSR1_ROR	0x00000080	/* Receive FIFO Over-Run (read)    */
+
+
+/*
+ * High-Speed Serial to Parallel controller (HSSP) control registers
+ *
+ * Registers
+ *    Ser2HSCR0 	Serial port 2 High-Speed Serial to Parallel
+ *              	controller (HSSP) Control Register 0 (read/write).
+ *    Ser2HSCR1 	Serial port 2 High-Speed Serial to Parallel
+ *              	controller (HSSP) Control Register 1 (read/write).
+ *    Ser2HSDR  	Serial port 2 High-Speed Serial to Parallel
+ *              	controller (HSSP) Data Register (read/write).
+ *    Ser2HSSR0 	Serial port 2 High-Speed Serial to Parallel
+ *              	controller (HSSP) Status Register 0 (read/write).
+ *    Ser2HSSR1 	Serial port 2 High-Speed Serial to Parallel
+ *              	controller (HSSP) Status Register 1 (read).
+ *    Ser2HSCR2 	Serial port 2 High-Speed Serial to Parallel
+ *              	controller (HSSP) Control Register 2 (read/write).
+ *              	[The HSCR2 register is only implemented in
+ *              	versions 2.0 (rev. = 8) and higher of the StrongARM
+ *              	SA-1100.]
+ */
+
+#define _Ser2HSCR0	0x80040060	/* Ser. port 2 HSSP Control Reg. 0 */
+#define _Ser2HSCR1	0x80040064	/* Ser. port 2 HSSP Control Reg. 1 */
+#define _Ser2HSDR	0x8004006C	/* Ser. port 2 HSSP Data Reg.      */
+#define _Ser2HSSR0	0x80040074	/* Ser. port 2 HSSP Status Reg. 0  */
+#define _Ser2HSSR1	0x80040078	/* Ser. port 2 HSSP Status Reg. 1  */
+#define _Ser2HSCR2	0x90060028	/* Ser. port 2 HSSP Control Reg. 2 */
+
+#if LANGUAGE == C
+#define Ser2HSCR0	        	/* Ser. port 2 HSSP Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser2HSCR0)))
+#define Ser2HSCR1	        	/* Ser. port 2 HSSP Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser2HSCR1)))
+#define Ser2HSDR	        	/* Ser. port 2 HSSP Data Reg.      */ \
+			(*((volatile Word *) io_p2v (_Ser2HSDR)))
+#define Ser2HSSR0	        	/* Ser. port 2 HSSP Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser2HSSR0)))
+#define Ser2HSSR1	        	/* Ser. port 2 HSSP Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser2HSSR1)))
+#define Ser2HSCR2	        	/* Ser. port 2 HSSP Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser2HSCR2)))
+#endif /* LANGUAGE == C */
+
+#define HSCR0_ITR	0x00000001	/* IrDA Transmission Rate          */
+#define HSCR0_UART	(HSCR0_ITR*0)	/*  UART mode (115.2 kb/s if IrDA) */
+#define HSCR0_HSSP	(HSCR0_ITR*1)	/*  HSSP mode (4 Mb/s)             */
+#define HSCR0_LBM	0x00000002	/* Look-Back Mode                  */
+#define HSCR0_TUS	0x00000004	/* Transmit FIFO Under-run Select  */
+#define HSCR0_EFrmURn	(HSCR0_TUS*0)	/*  End Frame on Under-Run         */
+#define HSCR0_AbortURn	(HSCR0_TUS*1)	/*  Abort on Under-Run             */
+#define HSCR0_TXE	0x00000008	/* Transmit Enable                 */
+#define HSCR0_RXE	0x00000010	/* Receive Enable                  */
+#define HSCR0_RIE	0x00000020	/* Receive FIFO 2/5-to-3/5-full or */
+					/* more Interrupt Enable           */
+#define HSCR0_TIE	0x00000040	/* Transmit FIFO 1/2-full or less  */
+					/* Interrupt Enable                */
+#define HSCR0_AME	0x00000080	/* Address Match Enable            */
+
+#define HSCR1_AMV	Fld (8, 0)	/* Address Match Value             */
+
+#define HSDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
+#if 0           	        	/* Hidden receive FIFO bits        */
+#define HSDR_EOF	0x00000100	/*  receive End-Of-Frame (read)    */
+#define HSDR_CRE	0x00000200	/*  receive CRC Error (read)       */
+#define HSDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
+#endif /* 0 */
+
+#define HSSR0_EIF	0x00000001	/* Error In FIFO (read)            */
+#define HSSR0_TUR	0x00000002	/* Transmit FIFO Under-Run         */
+#define HSSR0_RAB	0x00000004	/* Receive ABort                   */
+#define HSSR0_TFS	0x00000008	/* Transmit FIFO 1/2-full or less  */
+					/* Service request (read)          */
+#define HSSR0_RFS	0x00000010	/* Receive FIFO 2/5-to-3/5-full or */
+					/* more Service request (read)     */
+#define HSSR0_FRE	0x00000020	/* receive FRaming Error           */
+
+#define HSSR1_RSY	0x00000001	/* Receiver SYnchronized (read)    */
+#define HSSR1_TBY	0x00000002	/* Transmitter BusY (read)         */
+#define HSSR1_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
+#define HSSR1_TNF	0x00000008	/* Transmit FIFO Not Full (read)   */
+#define HSSR1_EOF	0x00000010	/* receive End-Of-Frame (read)     */
+#define HSSR1_CRE	0x00000020	/* receive CRC Error (read)        */
+#define HSSR1_ROR	0x00000040	/* Receive FIFO Over-Run (read)    */
+
+#define HSCR2_TXP	0x00040000	/* Transmit data Polarity (TXD_2)  */
+#define HSCR2_TrDataL	(HSCR2_TXP*0)	/*  Transmit Data active Low       */
+					/*  (inverted)                     */
+#define HSCR2_TrDataH	(HSCR2_TXP*1)	/*  Transmit Data active High      */
+					/*  (non-inverted)                 */
+#define HSCR2_RXP	0x00080000	/* Receive data Polarity (RXD_2)   */
+#define HSCR2_RcDataL	(HSCR2_RXP*0)	/*  Receive Data active Low        */
+					/*  (inverted)                     */
+#define HSCR2_RcDataH	(HSCR2_RXP*1)	/*  Receive Data active High       */
+					/*  (non-inverted)                 */
+
+
+/*
+ * Multi-media Communications Port (MCP) control registers
+ *
+ * Registers
+ *    Ser4MCCR0 	Serial port 4 Multi-media Communications Port (MCP)
+ *              	Control Register 0 (read/write).
+ *    Ser4MCDR0 	Serial port 4 Multi-media Communications Port (MCP)
+ *              	Data Register 0 (audio, read/write).
+ *    Ser4MCDR1 	Serial port 4 Multi-media Communications Port (MCP)
+ *              	Data Register 1 (telecom, read/write).
+ *    Ser4MCDR2 	Serial port 4 Multi-media Communications Port (MCP)
+ *              	Data Register 2 (CODEC registers, read/write).
+ *    Ser4MCSR  	Serial port 4 Multi-media Communications Port (MCP)
+ *              	Status Register (read/write).
+ *    Ser4MCCR1 	Serial port 4 Multi-media Communications Port (MCP)
+ *              	Control Register 1 (read/write).
+ *              	[The MCCR1 register is only implemented in
+ *              	versions 2.0 (rev. = 8) and higher of the StrongARM
+ *              	SA-1100.]
+ *
+ * Clocks
+ *    fmc, Tmc  	Frequency, period of the MCP communication (10 MHz,
+ *              	12 MHz, or GPIO [21]).
+ *    faud, Taud	Frequency, period of the audio sampling.
+ *    ftcm, Ttcm	Frequency, period of the telecom sampling.
+ */
+
+#define _Ser4MCCR0	0x80060000	/* Ser. port 4 MCP Control Reg. 0  */
+#define _Ser4MCDR0	0x80060008	/* Ser. port 4 MCP Data Reg. 0     */
+					/* (audio)                         */
+#define _Ser4MCDR1	0x8006000C	/* Ser. port 4 MCP Data Reg. 1     */
+					/* (telecom)                       */
+#define _Ser4MCDR2	0x80060010	/* Ser. port 4 MCP Data Reg. 2     */
+					/* (CODEC reg.)                    */
+#define _Ser4MCSR	0x80060018	/* Ser. port 4 MCP Status Reg.     */
+#define _Ser4MCCR1	0x90060030	/* Ser. port 4 MCP Control Reg. 1  */
+
+#if LANGUAGE == C
+#define Ser4MCCR0	        	/* Ser. port 4 MCP Control Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser4MCCR0)))
+#define Ser4MCDR0	        	/* Ser. port 4 MCP Data Reg. 0     */ \
+					/* (audio)                         */ \
+			(*((volatile Word *) io_p2v (_Ser4MCDR0)))
+#define Ser4MCDR1	        	/* Ser. port 4 MCP Data Reg. 1     */ \
+					/* (telecom)                       */ \
+			(*((volatile Word *) io_p2v (_Ser4MCDR1)))
+#define Ser4MCDR2	        	/* Ser. port 4 MCP Data Reg. 2     */ \
+					/* (CODEC reg.)                    */ \
+			(*((volatile Word *) io_p2v (_Ser4MCDR2)))
+#define Ser4MCSR	        	/* Ser. port 4 MCP Status Reg.     */ \
+			(*((volatile Word *) io_p2v (_Ser4MCSR)))
+#define Ser4MCCR1	        	/* Ser. port 4 MCP Control Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser4MCCR1)))
+#endif /* LANGUAGE == C */
+
+#define MCCR0_ASD	Fld (7, 0)	/* Audio Sampling rate Divisor/32  */
+					/* [6..127]                        */
+					/* faud = fmc/(32*ASD)             */
+					/* Taud = 32*ASD*Tmc               */
+#define MCCR0_AudSmpDiv(Div)    	/*  Audio Sampling rate Divisor    */ \
+					/*  [192..4064]                    */ \
+			((Div)/32 << FShft (MCCR0_ASD))
+					/*  faud = fmc/(32*Floor (Div/32)) */
+					/*  Taud = 32*Floor (Div/32)*Tmc   */
+#define MCCR0_CeilAudSmpDiv(Div)	/*  Ceil. of AudSmpDiv [192..4064] */ \
+			(((Div) + 31)/32 << FShft (MCCR0_ASD))
+					/*  faud = fmc/(32*Ceil (Div/32))  */
+					/*  Taud = 32*Ceil (Div/32)*Tmc    */
+#define MCCR0_TSD	Fld (7, 8)	/* Telecom Sampling rate           */
+					/* Divisor/32 [16..127]            */
+					/* ftcm = fmc/(32*TSD)             */
+					/* Ttcm = 32*TSD*Tmc               */
+#define MCCR0_TcmSmpDiv(Div)    	/*  Telecom Sampling rate Divisor  */ \
+					/*  [512..4064]                    */ \
+			((Div)/32 << FShft (MCCR0_TSD))
+					/*  ftcm = fmc/(32*Floor (Div/32)) */
+					/*  Ttcm = 32*Floor (Div/32)*Tmc   */
+#define MCCR0_CeilTcmSmpDiv(Div)	/*  Ceil. of TcmSmpDiv [512..4064] */ \
+			(((Div) + 31)/32 << FShft (MCCR0_TSD))
+					/*  ftcm = fmc/(32*Ceil (Div/32))  */
+					/*  Ttcm = 32*Ceil (Div/32)*Tmc    */
+#define MCCR0_MCE	0x00010000	/* MCP Enable                      */
+#define MCCR0_ECS	0x00020000	/* External Clock Select           */
+#define MCCR0_IntClk	(MCCR0_ECS*0)	/*  Internal Clock (10 or 12 MHz)  */
+#define MCCR0_ExtClk	(MCCR0_ECS*1)	/*  External Clock (GPIO [21])     */
+#define MCCR0_ADM	0x00040000	/* A/D (audio/telecom) data        */
+					/* sampling/storing Mode           */
+#define MCCR0_VldBit	(MCCR0_ADM*0)	/*  Valid Bit storing mode         */
+#define MCCR0_SmpCnt	(MCCR0_ADM*1)	/*  Sampling Counter storing mode  */
+#define MCCR0_TTE	0x00080000	/* Telecom Transmit FIFO 1/2-full  */
+					/* or less interrupt Enable        */
+#define MCCR0_TRE	0x00100000	/* Telecom Receive FIFO 1/2-full   */
+					/* or more interrupt Enable        */
+#define MCCR0_ATE	0x00200000	/* Audio Transmit FIFO 1/2-full    */
+					/* or less interrupt Enable        */
+#define MCCR0_ARE	0x00400000	/* Audio Receive FIFO 1/2-full or  */
+					/* more interrupt Enable           */
+#define MCCR0_LBM	0x00800000	/* Look-Back Mode                  */
+#define MCCR0_ECP	Fld (2, 24)	/* External Clock Prescaler - 1    */
+#define MCCR0_ExtClkDiv(Div)    	/*  External Clock Divisor [1..4]  */ \
+			(((Div) - 1) << FShft (MCCR0_ECP))
+
+#define MCDR0_DATA	Fld (12, 4)	/* receive/transmit audio DATA     */
+					/* FIFOs                           */
+
+#define MCDR1_DATA	Fld (14, 2)	/* receive/transmit telecom DATA   */
+					/* FIFOs                           */
+
+					/* receive/transmit CODEC reg.     */
+					/* FIFOs:                          */
+#define MCDR2_DATA	Fld (16, 0)	/*  reg. DATA                      */
+#define MCDR2_RW	0x00010000	/*  reg. Read/Write (transmit)     */
+#define MCDR2_Rd	(MCDR2_RW*0)	/*   reg. Read                     */
+#define MCDR2_Wr	(MCDR2_RW*1)	/*   reg. Write                    */
+#define MCDR2_ADD	Fld (4, 17)	/*  reg. ADDress                   */
+
+#define MCSR_ATS	0x00000001	/* Audio Transmit FIFO 1/2-full    */
+					/* or less Service request (read)  */
+#define MCSR_ARS	0x00000002	/* Audio Receive FIFO 1/2-full or  */
+					/* more Service request (read)     */
+#define MCSR_TTS	0x00000004	/* Telecom Transmit FIFO 1/2-full  */
+					/* or less Service request (read)  */
+#define MCSR_TRS	0x00000008	/* Telecom Receive FIFO 1/2-full   */
+					/* or more Service request (read)  */
+#define MCSR_ATU	0x00000010	/* Audio Transmit FIFO Under-run   */
+#define MCSR_ARO	0x00000020	/* Audio Receive FIFO Over-run     */
+#define MCSR_TTU	0x00000040	/* Telecom Transmit FIFO Under-run */
+#define MCSR_TRO	0x00000080	/* Telecom Receive FIFO Over-run   */
+#define MCSR_ANF	0x00000100	/* Audio transmit FIFO Not Full    */
+					/* (read)                          */
+#define MCSR_ANE	0x00000200	/* Audio receive FIFO Not Empty    */
+					/* (read)                          */
+#define MCSR_TNF	0x00000400	/* Telecom transmit FIFO Not Full  */
+					/* (read)                          */
+#define MCSR_TNE	0x00000800	/* Telecom receive FIFO Not Empty  */
+					/* (read)                          */
+#define MCSR_CWC	0x00001000	/* CODEC register Write Completed  */
+					/* (read)                          */
+#define MCSR_CRC	0x00002000	/* CODEC register Read Completed   */
+					/* (read)                          */
+#define MCSR_ACE	0x00004000	/* Audio CODEC Enabled (read)      */
+#define MCSR_TCE	0x00008000	/* Telecom CODEC Enabled (read)    */
+
+#define MCCR1_CFS	0x00100000	/* Clock Freq. Select              */
+#define MCCR1_F12MHz	(MCCR1_CFS*0)	/*  Freq. (fmc) = ~ 12 MHz         */
+					/*  (11.981 MHz)                   */
+#define MCCR1_F10MHz	(MCCR1_CFS*1)	/*  Freq. (fmc) = ~ 10 MHz         */
+					/*  (9.585 MHz)                    */
+
+
+/*
+ * Synchronous Serial Port (SSP) control registers
+ *
+ * Registers
+ *    Ser4SSCR0 	Serial port 4 Synchronous Serial Port (SSP) Control
+ *              	Register 0 (read/write).
+ *    Ser4SSCR1 	Serial port 4 Synchronous Serial Port (SSP) Control
+ *              	Register 1 (read/write).
+ *              	[Bits SPO and SP are only implemented in versions 2.0
+ *              	(rev. = 8) and higher of the StrongARM SA-1100.]
+ *    Ser4SSDR  	Serial port 4 Synchronous Serial Port (SSP) Data
+ *              	Register (read/write).
+ *    Ser4SSSR  	Serial port 4 Synchronous Serial Port (SSP) Status
+ *              	Register (read/write).
+ *
+ * Clocks
+ *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
+ *              	or 3.5795 MHz).
+ *    fss, Tss  	Frequency, period of the SSP communication.
+ */
+
+#define _Ser4SSCR0	0x80070060	/* Ser. port 4 SSP Control Reg. 0  */
+#define _Ser4SSCR1	0x80070064	/* Ser. port 4 SSP Control Reg. 1  */
+#define _Ser4SSDR	0x8007006C	/* Ser. port 4 SSP Data Reg.       */
+#define _Ser4SSSR	0x80070074	/* Ser. port 4 SSP Status Reg.     */
+
+#if LANGUAGE == C
+#define Ser4SSCR0	        	/* Ser. port 4 SSP Control Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser4SSCR0)))
+#define Ser4SSCR1	        	/* Ser. port 4 SSP Control Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser4SSCR1)))
+#define Ser4SSDR	        	/* Ser. port 4 SSP Data Reg.       */ \
+			(*((volatile Word *) io_p2v (_Ser4SSDR)))
+#define Ser4SSSR	        	/* Ser. port 4 SSP Status Reg.     */ \
+			(*((volatile Word *) io_p2v (_Ser4SSSR)))
+#endif /* LANGUAGE == C */
+
+#define SSCR0_DSS	Fld (4, 0)	/* Data Size - 1 Select [3..15]    */
+#define SSCR0_DataSize(Size)    	/*  Data Size Select [4..16]       */ \
+			(((Size) - 1) << FShft (SSCR0_DSS))
+#define SSCR0_FRF	Fld (2, 4)	/* FRame Format                    */
+#define SSCR0_Motorola	        	/*  Motorola Serial Peripheral     */ \
+					/*  Interface (SPI) format         */ \
+			(0 << FShft (SSCR0_FRF))
+#define SSCR0_TI	        	/*  Texas Instruments Synchronous  */ \
+					/*  Serial format                  */ \
+			(1 << FShft (SSCR0_FRF))
+#define SSCR0_National	        	/*  National Microwire format      */ \
+			(2 << FShft (SSCR0_FRF))
+#define SSCR0_SSE	0x00000080	/* SSP Enable                      */
+#define SSCR0_SCR	Fld (8, 8)	/* Serial Clock Rate divisor/2 - 1 */
+					/* fss = fxtl/(2*(SCR + 1))        */
+					/* Tss = 2*(SCR + 1)*Txtl          */
+#define SSCR0_SerClkDiv(Div)    	/*  Serial Clock Divisor [2..512]  */ \
+			(((Div) - 2)/2 << FShft (SSCR0_SCR))
+					/*  fss = fxtl/(2*Floor (Div/2))   */
+					/*  Tss = 2*Floor (Div/2)*Txtl     */
+#define SSCR0_CeilSerClkDiv(Div)	/*  Ceil. of SerClkDiv [2..512]    */ \
+			(((Div) - 1)/2 << FShft (SSCR0_SCR))
+					/*  fss = fxtl/(2*Ceil (Div/2))    */
+					/*  Tss = 2*Ceil (Div/2)*Txtl      */
+
+#define SSCR1_RIE	0x00000001	/* Receive FIFO 1/2-full or more   */
+					/* Interrupt Enable                */
+#define SSCR1_TIE	0x00000002	/* Transmit FIFO 1/2-full or less  */
+					/* Interrupt Enable                */
+#define SSCR1_LBM	0x00000004	/* Look-Back Mode                  */
+#define SSCR1_SPO	0x00000008	/* Sample clock (SCLK) POlarity    */
+#define SSCR1_SClkIactL	(SSCR1_SPO*0)	/*  Sample Clock Inactive Low      */
+#define SSCR1_SClkIactH	(SSCR1_SPO*1)	/*  Sample Clock Inactive High     */
+#define SSCR1_SP	0x00000010	/* Sample clock (SCLK) Phase       */
+#define SSCR1_SClk1P	(SSCR1_SP*0)	/*  Sample Clock active 1 Period   */
+					/*  after frame (SFRM, 1st edge)   */
+#define SSCR1_SClk1_2P	(SSCR1_SP*1)	/*  Sample Clock active 1/2 Period */
+					/*  after frame (SFRM, 1st edge)   */
+#define SSCR1_ECS	0x00000020	/* External Clock Select           */
+#define SSCR1_IntClk	(SSCR1_ECS*0)	/*  Internal Clock                 */
+#define SSCR1_ExtClk	(SSCR1_ECS*1)	/*  External Clock (GPIO [19])     */
+
+#define SSDR_DATA	Fld (16, 0)	/* receive/transmit DATA FIFOs     */
+
+#define SSSR_TNF	0x00000002	/* Transmit FIFO Not Full (read)   */
+#define SSSR_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
+#define SSSR_BSY	0x00000008	/* SSP BuSY (read)                 */
+#define SSSR_TFS	0x00000010	/* Transmit FIFO 1/2-full or less  */
+					/* Service request (read)          */
+#define SSSR_RFS	0x00000020	/* Receive FIFO 1/2-full or more   */
+					/* Service request (read)          */
+#define SSSR_ROR	0x00000040	/* Receive FIFO Over-Run           */
+
+
+/*
+ * Operating System (OS) timer control registers
+ *
+ * Registers
+ *    OSMR0     	Operating System (OS) timer Match Register 0
+ *              	(read/write).
+ *    OSMR1     	Operating System (OS) timer Match Register 1
+ *              	(read/write).
+ *    OSMR2     	Operating System (OS) timer Match Register 2
+ *              	(read/write).
+ *    OSMR3     	Operating System (OS) timer Match Register 3
+ *              	(read/write).
+ *    OSCR      	Operating System (OS) timer Counter Register
+ *              	(read/write).
+ *    OSSR      	Operating System (OS) timer Status Register
+ *              	(read/write).
+ *    OWER      	Operating System (OS) timer Watch-dog Enable Register
+ *              	(read/write).
+ *    OIER      	Operating System (OS) timer Interrupt Enable Register
+ *              	(read/write).
+ */
+
+#define _OSMR(Nb)	        	/* OS timer Match Reg. [0..3]      */ \
+			(0x90000000 + (Nb)*4)
+#define _OSMR0  	_OSMR (0)	/* OS timer Match Reg. 0           */
+#define _OSMR1  	_OSMR (1)	/* OS timer Match Reg. 1           */
+#define _OSMR2  	_OSMR (2)	/* OS timer Match Reg. 2           */
+#define _OSMR3  	_OSMR (3)	/* OS timer Match Reg. 3           */
+#define _OSCR   	0x90000010	/* OS timer Counter Reg.           */
+#define _OSSR   	0x90000014	/* OS timer Status Reg.            */
+#define _OWER   	0x90000018	/* OS timer Watch-dog Enable Reg.  */
+#define _OIER   	0x9000001C	/* OS timer Interrupt Enable Reg.  */
+
+#if LANGUAGE == C
+#define OSMR    	        	/* OS timer Match Reg. [0..3]      */ \
+			((volatile Word *) io_p2v (_OSMR (0)))
+#define OSMR0   	(OSMR [0])	/* OS timer Match Reg. 0           */
+#define OSMR1   	(OSMR [1])	/* OS timer Match Reg. 1           */
+#define OSMR2   	(OSMR [2])	/* OS timer Match Reg. 2           */
+#define OSMR3   	(OSMR [3])	/* OS timer Match Reg. 3           */
+#define OSCR    	        	/* OS timer Counter Reg.           */ \
+			(*((volatile Word *) io_p2v (_OSCR)))
+#define OSSR    	        	/* OS timer Status Reg.            */ \
+			(*((volatile Word *) io_p2v (_OSSR)))
+#define OWER    	        	/* OS timer Watch-dog Enable Reg.  */ \
+			(*((volatile Word *) io_p2v (_OWER)))
+#define OIER    	        	/* OS timer Interrupt Enable Reg.  */ \
+			(*((volatile Word *) io_p2v (_OIER)))
+#endif /* LANGUAGE == C */
+
+#define OSSR_M(Nb)	        	/* Match detected [0..3]           */ \
+			(0x00000001 << (Nb))
+#define OSSR_M0 	OSSR_M (0)	/* Match detected 0                */
+#define OSSR_M1 	OSSR_M (1)	/* Match detected 1                */
+#define OSSR_M2 	OSSR_M (2)	/* Match detected 2                */
+#define OSSR_M3 	OSSR_M (3)	/* Match detected 3                */
+
+#define OWER_WME	0x00000001	/* Watch-dog Match Enable          */
+					/* (set only)                      */
+
+#define OIER_E(Nb)	        	/* match interrupt Enable [0..3]   */ \
+			(0x00000001 << (Nb))
+#define OIER_E0 	OIER_E (0)	/* match interrupt Enable 0        */
+#define OIER_E1 	OIER_E (1)	/* match interrupt Enable 1        */
+#define OIER_E2 	OIER_E (2)	/* match interrupt Enable 2        */
+#define OIER_E3 	OIER_E (3)	/* match interrupt Enable 3        */
+
+
+/*
+ * Real-Time Clock (RTC) control registers
+ *
+ * Registers
+ *    RTAR      	Real-Time Clock (RTC) Alarm Register (read/write).
+ *    RCNR      	Real-Time Clock (RTC) CouNt Register (read/write).
+ *    RTTR      	Real-Time Clock (RTC) Trim Register (read/write).
+ *    RTSR      	Real-Time Clock (RTC) Status Register (read/write).
+ *
+ * Clocks
+ *    frtx, Trtx	Frequency, period of the real-time clock crystal
+ *              	(32.768 kHz nominal).
+ *    frtc, Trtc	Frequency, period of the real-time clock counter
+ *              	(1 Hz nominal).
+ */
+
+#define _RTAR   	0x90010000	/* RTC Alarm Reg.                  */
+#define _RCNR   	0x90010004	/* RTC CouNt Reg.                  */
+#define _RTTR   	0x90010008	/* RTC Trim Reg.                   */
+#define _RTSR   	0x90010010	/* RTC Status Reg.                 */
+
+#if LANGUAGE == C
+#define RTAR    	        	/* RTC Alarm Reg.                  */ \
+			(*((volatile Word *) io_p2v (_RTAR)))
+#define RCNR    	        	/* RTC CouNt Reg.                  */ \
+			(*((volatile Word *) io_p2v (_RCNR)))
+#define RTTR    	        	/* RTC Trim Reg.                   */ \
+			(*((volatile Word *) io_p2v (_RTTR)))
+#define RTSR    	        	/* RTC Status Reg.                 */ \
+			(*((volatile Word *) io_p2v (_RTSR)))
+#endif /* LANGUAGE == C */
+
+#define RTTR_C  	Fld (16, 0)	/* clock divider Count - 1         */
+#define RTTR_D  	Fld (10, 16)	/* trim Delete count               */
+					/* frtc = (1023*(C + 1) - D)*frtx/ */
+					/*        (1023*(C + 1)^2)         */
+					/* Trtc = (1023*(C + 1)^2)*Trtx/   */
+					/*        (1023*(C + 1) - D)       */
+
+#define RTSR_AL 	0x00000001	/* ALarm detected                  */
+#define RTSR_HZ 	0x00000002	/* 1 Hz clock detected             */
+#define RTSR_ALE	0x00000004	/* ALarm interrupt Enable          */
+#define RTSR_HZE	0x00000008	/* 1 Hz clock interrupt Enable     */
+
+
+/*
+ * Power Manager (PM) control registers
+ *
+ * Registers
+ *    PMCR      	Power Manager (PM) Control Register (read/write).
+ *    PSSR      	Power Manager (PM) Sleep Status Register (read/write).
+ *    PSPR      	Power Manager (PM) Scratch-Pad Register (read/write).
+ *    PWER      	Power Manager (PM) Wake-up Enable Register
+ *              	(read/write).
+ *    PCFR      	Power Manager (PM) general ConFiguration Register
+ *              	(read/write).
+ *    PPCR      	Power Manager (PM) Phase-Locked Loop (PLL)
+ *              	Configuration Register (read/write).
+ *    PGSR      	Power Manager (PM) General-Purpose Input/Output (GPIO)
+ *              	Sleep state Register (read/write, see GPIO pins).
+ *    POSR      	Power Manager (PM) Oscillator Status Register (read).
+ *
+ * Clocks
+ *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
+ *              	or 3.5795 MHz).
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ */
+
+#define _PMCR   	0x90020000	/* PM Control Reg.                 */
+#define _PSSR   	0x90020004	/* PM Sleep Status Reg.            */
+#define _PSPR   	0x90020008	/* PM Scratch-Pad Reg.             */
+#define _PWER   	0x9002000C	/* PM Wake-up Enable Reg.          */
+#define _PCFR   	0x90020010	/* PM general ConFiguration Reg.   */
+#define _PPCR   	0x90020014	/* PM PLL Configuration Reg.       */
+#define _PGSR   	0x90020018	/* PM GPIO Sleep state Reg.        */
+#define _POSR   	0x9002001C	/* PM Oscillator Status Reg.       */
+
+#if LANGUAGE == C
+#define PMCR    	        	/* PM Control Reg.                 */ \
+			(*((volatile Word *) io_p2v (_PMCR)))
+#define PSSR    	        	/* PM Sleep Status Reg.            */ \
+			(*((volatile Word *) io_p2v (_PSSR)))
+#define PSPR    	        	/* PM Scratch-Pad Reg.             */ \
+			(*((volatile Word *) io_p2v (_PSPR)))
+#define PWER    	        	/* PM Wake-up Enable Reg.          */ \
+			(*((volatile Word *) io_p2v (_PWER)))
+#define PCFR    	        	/* PM general ConFiguration Reg.   */ \
+			(*((volatile Word *) io_p2v (_PCFR)))
+#define PPCR    	        	/* PM PLL Configuration Reg.       */ \
+			(*((volatile Word *) io_p2v (_PPCR)))
+#define PGSR    	        	/* PM GPIO Sleep state Reg.        */ \
+			(*((volatile Word *) io_p2v (_PGSR)))
+#define POSR    	        	/* PM Oscillator Status Reg.       */ \
+			(*((volatile Word *) io_p2v (_POSR)))
+
+#elif LANGUAGE == Assembly
+#define PMCR          	(io_p2v (_PMCR))
+#define PSSR          	(io_p2v (_PSSR))
+#define PSPR          	(io_p2v (_PSPR))
+#define PWER          	(io_p2v (_PWER))
+#define PCFR          	(io_p2v (_PCFR))
+#define PPCR          	(io_p2v (_PPCR))
+#define PGSR          	(io_p2v (_PGSR))
+#define POSR          	(io_p2v (_POSR))
+
+#endif /* LANGUAGE == C */
+
+#define PMCR_SF 	0x00000001	/* Sleep Force (set only)          */
+
+#define PSSR_SS 	0x00000001	/* Software Sleep                  */
+#define PSSR_BFS	0x00000002	/* Battery Fault Status            */
+					/* (BATT_FAULT)                    */
+#define PSSR_VFS	0x00000004	/* Vdd Fault Status (VDD_FAULT)    */
+#define PSSR_DH 	0x00000008	/* DRAM control Hold               */
+#define PSSR_PH 	0x00000010	/* Peripheral control Hold         */
+
+#define PWER_GPIO(Nb)	GPIO_GPIO (Nb)	/* GPIO [0..27] wake-up enable     */
+#define PWER_GPIO0	PWER_GPIO (0)	/* GPIO  [0] wake-up enable        */
+#define PWER_GPIO1	PWER_GPIO (1)	/* GPIO  [1] wake-up enable        */
+#define PWER_GPIO2	PWER_GPIO (2)	/* GPIO  [2] wake-up enable        */
+#define PWER_GPIO3	PWER_GPIO (3)	/* GPIO  [3] wake-up enable        */
+#define PWER_GPIO4	PWER_GPIO (4)	/* GPIO  [4] wake-up enable        */
+#define PWER_GPIO5	PWER_GPIO (5)	/* GPIO  [5] wake-up enable        */
+#define PWER_GPIO6	PWER_GPIO (6)	/* GPIO  [6] wake-up enable        */
+#define PWER_GPIO7	PWER_GPIO (7)	/* GPIO  [7] wake-up enable        */
+#define PWER_GPIO8	PWER_GPIO (8)	/* GPIO  [8] wake-up enable        */
+#define PWER_GPIO9	PWER_GPIO (9)	/* GPIO  [9] wake-up enable        */
+#define PWER_GPIO10	PWER_GPIO (10)	/* GPIO [10] wake-up enable        */
+#define PWER_GPIO11	PWER_GPIO (11)	/* GPIO [11] wake-up enable        */
+#define PWER_GPIO12	PWER_GPIO (12)	/* GPIO [12] wake-up enable        */
+#define PWER_GPIO13	PWER_GPIO (13)	/* GPIO [13] wake-up enable        */
+#define PWER_GPIO14	PWER_GPIO (14)	/* GPIO [14] wake-up enable        */
+#define PWER_GPIO15	PWER_GPIO (15)	/* GPIO [15] wake-up enable        */
+#define PWER_GPIO16	PWER_GPIO (16)	/* GPIO [16] wake-up enable        */
+#define PWER_GPIO17	PWER_GPIO (17)	/* GPIO [17] wake-up enable        */
+#define PWER_GPIO18	PWER_GPIO (18)	/* GPIO [18] wake-up enable        */
+#define PWER_GPIO19	PWER_GPIO (19)	/* GPIO [19] wake-up enable        */
+#define PWER_GPIO20	PWER_GPIO (20)	/* GPIO [20] wake-up enable        */
+#define PWER_GPIO21	PWER_GPIO (21)	/* GPIO [21] wake-up enable        */
+#define PWER_GPIO22	PWER_GPIO (22)	/* GPIO [22] wake-up enable        */
+#define PWER_GPIO23	PWER_GPIO (23)	/* GPIO [23] wake-up enable        */
+#define PWER_GPIO24	PWER_GPIO (24)	/* GPIO [24] wake-up enable        */
+#define PWER_GPIO25	PWER_GPIO (25)	/* GPIO [25] wake-up enable        */
+#define PWER_GPIO26	PWER_GPIO (26)	/* GPIO [26] wake-up enable        */
+#define PWER_GPIO27	PWER_GPIO (27)	/* GPIO [27] wake-up enable        */
+#define PWER_RTC	0x80000000	/* RTC alarm wake-up enable        */
+
+#define PCFR_OPDE	0x00000001	/* Oscillator Power-Down Enable    */
+#define PCFR_ClkRun	(PCFR_OPDE*0)	/*  Clock Running in sleep mode    */
+#define PCFR_ClkStp	(PCFR_OPDE*1)	/*  Clock Stopped in sleep mode    */
+#define PCFR_FP 	0x00000002	/* Float PCMCIA pins               */
+#define PCFR_PCMCIANeg	(PCFR_FP*0)	/*  PCMCIA pins Negated (1)        */
+#define PCFR_PCMCIAFlt	(PCFR_FP*1)	/*  PCMCIA pins Floating           */
+#define PCFR_FS 	0x00000004	/* Float Static memory pins        */
+#define PCFR_StMemNeg	(PCFR_FS*0)	/*  Static Memory pins Negated (1) */
+#define PCFR_StMemFlt	(PCFR_FS*1)	/*  Static Memory pins Floating    */
+#define PCFR_FO 	0x00000008	/* Force RTC oscillator            */
+					/* (32.768 kHz) enable On          */
+
+#define PPCR_CCF	Fld (5, 0)	/* CPU core Clock (CCLK) Freq.     */
+#define PPCR_Fx16	        	/*  Freq. x 16 (fcpu = 16*fxtl)    */ \
+			(0x00 << FShft (PPCR_CCF))
+#define PPCR_Fx20	        	/*  Freq. x 20 (fcpu = 20*fxtl)    */ \
+			(0x01 << FShft (PPCR_CCF))
+#define PPCR_Fx24	        	/*  Freq. x 24 (fcpu = 24*fxtl)    */ \
+			(0x02 << FShft (PPCR_CCF))
+#define PPCR_Fx28	        	/*  Freq. x 28 (fcpu = 28*fxtl)    */ \
+			(0x03 << FShft (PPCR_CCF))
+#define PPCR_Fx32	        	/*  Freq. x 32 (fcpu = 32*fxtl)    */ \
+			(0x04 << FShft (PPCR_CCF))
+#define PPCR_Fx36	        	/*  Freq. x 36 (fcpu = 36*fxtl)    */ \
+			(0x05 << FShft (PPCR_CCF))
+#define PPCR_Fx40	        	/*  Freq. x 40 (fcpu = 40*fxtl)    */ \
+			(0x06 << FShft (PPCR_CCF))
+#define PPCR_Fx44	        	/*  Freq. x 44 (fcpu = 44*fxtl)    */ \
+			(0x07 << FShft (PPCR_CCF))
+#define PPCR_Fx48	        	/*  Freq. x 48 (fcpu = 48*fxtl)    */ \
+			(0x08 << FShft (PPCR_CCF))
+#define PPCR_Fx52	        	/*  Freq. x 52 (fcpu = 52*fxtl)    */ \
+			(0x09 << FShft (PPCR_CCF))
+#define PPCR_Fx56	        	/*  Freq. x 56 (fcpu = 56*fxtl)    */ \
+			(0x0A << FShft (PPCR_CCF))
+#define PPCR_Fx60	        	/*  Freq. x 60 (fcpu = 60*fxtl)    */ \
+			(0x0B << FShft (PPCR_CCF))
+#define PPCR_Fx64	        	/*  Freq. x 64 (fcpu = 64*fxtl)    */ \
+			(0x0C << FShft (PPCR_CCF))
+#define PPCR_Fx68	        	/*  Freq. x 68 (fcpu = 68*fxtl)    */ \
+			(0x0D << FShft (PPCR_CCF))
+#define PPCR_Fx72	        	/*  Freq. x 72 (fcpu = 72*fxtl)    */ \
+			(0x0E << FShft (PPCR_CCF))
+#define PPCR_Fx76	        	/*  Freq. x 76 (fcpu = 76*fxtl)    */ \
+			(0x0F << FShft (PPCR_CCF))
+					/*  3.6864 MHz crystal (fxtl):     */
+#define PPCR_F59_0MHz	PPCR_Fx16	/*   Freq. (fcpu) =  59.0 MHz      */
+#define PPCR_F73_7MHz	PPCR_Fx20	/*   Freq. (fcpu) =  73.7 MHz      */
+#define PPCR_F88_5MHz	PPCR_Fx24	/*   Freq. (fcpu) =  88.5 MHz      */
+#define PPCR_F103_2MHz	PPCR_Fx28	/*   Freq. (fcpu) = 103.2 MHz      */
+#define PPCR_F118_0MHz	PPCR_Fx32	/*   Freq. (fcpu) = 118.0 MHz      */
+#define PPCR_F132_7MHz	PPCR_Fx36	/*   Freq. (fcpu) = 132.7 MHz      */
+#define PPCR_F147_5MHz	PPCR_Fx40	/*   Freq. (fcpu) = 147.5 MHz      */
+#define PPCR_F162_2MHz	PPCR_Fx44	/*   Freq. (fcpu) = 162.2 MHz      */
+#define PPCR_F176_9MHz	PPCR_Fx48	/*   Freq. (fcpu) = 176.9 MHz      */
+#define PPCR_F191_7MHz	PPCR_Fx52	/*   Freq. (fcpu) = 191.7 MHz      */
+#define PPCR_F206_4MHz	PPCR_Fx56	/*   Freq. (fcpu) = 206.4 MHz      */
+#define PPCR_F221_2MHz	PPCR_Fx60	/*   Freq. (fcpu) = 221.2 MHz      */
+#define PPCR_F239_6MHz	PPCR_Fx64	/*   Freq. (fcpu) = 239.6 MHz      */
+#define PPCR_F250_7MHz	PPCR_Fx68	/*   Freq. (fcpu) = 250.7 MHz      */
+#define PPCR_F265_4MHz	PPCR_Fx72	/*   Freq. (fcpu) = 265.4 MHz      */
+#define PPCR_F280_2MHz	PPCR_Fx76	/*   Freq. (fcpu) = 280.2 MHz      */
+					/*  3.5795 MHz crystal (fxtl):     */
+#define PPCR_F57_3MHz	PPCR_Fx16	/*   Freq. (fcpu) =  57.3 MHz      */
+#define PPCR_F71_6MHz	PPCR_Fx20	/*   Freq. (fcpu) =  71.6 MHz      */
+#define PPCR_F85_9MHz	PPCR_Fx24	/*   Freq. (fcpu) =  85.9 MHz      */
+#define PPCR_F100_2MHz	PPCR_Fx28	/*   Freq. (fcpu) = 100.2 MHz      */
+#define PPCR_F114_5MHz	PPCR_Fx32	/*   Freq. (fcpu) = 114.5 MHz      */
+#define PPCR_F128_9MHz	PPCR_Fx36	/*   Freq. (fcpu) = 128.9 MHz      */
+#define PPCR_F143_2MHz	PPCR_Fx40	/*   Freq. (fcpu) = 143.2 MHz      */
+#define PPCR_F157_5MHz	PPCR_Fx44	/*   Freq. (fcpu) = 157.5 MHz      */
+#define PPCR_F171_8MHz	PPCR_Fx48	/*   Freq. (fcpu) = 171.8 MHz      */
+#define PPCR_F186_1MHz	PPCR_Fx52	/*   Freq. (fcpu) = 186.1 MHz      */
+#define PPCR_F200_5MHz	PPCR_Fx56	/*   Freq. (fcpu) = 200.5 MHz      */
+#define PPCR_F214_8MHz	PPCR_Fx60	/*   Freq. (fcpu) = 214.8 MHz      */
+#define PPCR_F229_1MHz	PPCR_Fx64	/*   Freq. (fcpu) = 229.1 MHz      */
+#define PPCR_F243_4MHz	PPCR_Fx68	/*   Freq. (fcpu) = 243.4 MHz      */
+#define PPCR_F257_7MHz	PPCR_Fx72	/*   Freq. (fcpu) = 257.7 MHz      */
+#define PPCR_F272_0MHz	PPCR_Fx76	/*   Freq. (fcpu) = 272.0 MHz      */
+
+#define POSR_OOK	0x00000001	/* RTC Oscillator (32.768 kHz) OK  */
+
+
+/*
+ * Reset Controller (RC) control registers
+ *
+ * Registers
+ *    RSRR      	Reset Controller (RC) Software Reset Register
+ *              	(read/write).
+ *    RCSR      	Reset Controller (RC) Status Register (read/write).
+ */
+
+#define _RSRR   	0x90030000	/* RC Software Reset Reg.          */
+#define _RCSR   	0x90030004	/* RC Status Reg.                  */
+
+#if LANGUAGE == C
+#define RSRR    	        	/* RC Software Reset Reg.          */ \
+			(*((volatile Word *) io_p2v (_RSRR)))
+#define RCSR    	        	/* RC Status Reg.                  */ \
+			(*((volatile Word *) io_p2v (_RCSR)))
+#endif /* LANGUAGE == C */
+
+#define RSRR_SWR	0x00000001	/* SoftWare Reset (set only)       */
+
+#define RCSR_HWR	0x00000001	/* HardWare Reset                  */
+#define RCSR_SWR	0x00000002	/* SoftWare Reset                  */
+#define RCSR_WDR	0x00000004	/* Watch-Dog Reset                 */
+#define RCSR_SMR	0x00000008	/* Sleep-Mode Reset                */
+
+
+/*
+ * Test unit control registers
+ *
+ * Registers
+ *    TUCR      	Test Unit Control Register (read/write).
+ */
+
+#define _TUCR   	0x90030008	/* Test Unit Control Reg.          */
+
+#if LANGUAGE == C
+#define TUCR    	        	/* Test Unit Control Reg.          */ \
+			(*((volatile Word *) io_p2v (_TUCR)))
+#endif /* LANGUAGE == C */
+
+#define TUCR_TIC	0x00000040	/* TIC mode                        */
+#define TUCR_TTST	0x00000080	/* Trim TeST mode                  */
+#define TUCR_RCRC	0x00000100	/* Richard's Cyclic Redundancy     */
+					/* Check                           */
+#define TUCR_PMD	0x00000200	/* Power Management Disable        */
+#define TUCR_MR 	0x00000400	/* Memory Request mode             */
+#define TUCR_NoMB	(TUCR_MR*0)	/*  No Memory Bus request & grant  */
+#define TUCR_MBGPIO	(TUCR_MR*1)	/*  Memory Bus request (MBREQ) &   */
+					/*  grant (MBGNT) on GPIO [22:21]  */
+#define TUCR_CTB	Fld (3, 20)	/* Clock Test Bits                 */
+#define TUCR_FDC	0x00800000	/* RTC Force Delete Count          */
+#define TUCR_FMC	0x01000000	/* Force Michelle's Control mode   */
+#define TUCR_TMC	0x02000000	/* RTC Trimmer Multiplexer Control */
+#define TUCR_DPS	0x04000000	/* Disallow Pad Sleep              */
+#define TUCR_TSEL	Fld (3, 29)	/* clock Test SELect on GPIO [27]  */
+#define TUCR_32_768kHz	        	/*  32.768 kHz osc. on GPIO [27]   */ \
+			(0 << FShft (TUCR_TSEL))
+#define TUCR_3_6864MHz	        	/*  3.6864 MHz osc. on GPIO [27]   */ \
+			(1 << FShft (TUCR_TSEL))
+#define TUCR_VDD	        	/*  VDD ring osc./16 on GPIO [27]  */ \
+			(2 << FShft (TUCR_TSEL))
+#define TUCR_96MHzPLL	        	/*  96 MHz PLL/4 on GPIO [27]      */ \
+			(3 << FShft (TUCR_TSEL))
+#define TUCR_Clock	        	/*  internal (fcpu/2) & 32.768 kHz */ \
+					/*  Clocks on GPIO [26:27]         */ \
+			(4 << FShft (TUCR_TSEL))
+#define TUCR_3_6864MHzA	        	/*  3.6864 MHz osc. on GPIO [27]   */ \
+					/*  (Alternative)                  */ \
+			(5 << FShft (TUCR_TSEL))
+#define TUCR_MainPLL	        	/*  Main PLL/16 on GPIO [27]       */ \
+			(6 << FShft (TUCR_TSEL))
+#define TUCR_VDDL	        	/*  VDDL ring osc./4 on GPIO [27]  */ \
+			(7 << FShft (TUCR_TSEL))
+
+
+/*
+ * General-Purpose Input/Output (GPIO) control registers
+ *
+ * Registers
+ *    GPLR      	General-Purpose Input/Output (GPIO) Pin Level
+ *              	Register (read).
+ *    GPDR      	General-Purpose Input/Output (GPIO) Pin Direction
+ *              	Register (read/write).
+ *    GPSR      	General-Purpose Input/Output (GPIO) Pin output Set
+ *              	Register (write).
+ *    GPCR      	General-Purpose Input/Output (GPIO) Pin output Clear
+ *              	Register (write).
+ *    GRER      	General-Purpose Input/Output (GPIO) Rising-Edge
+ *              	detect Register (read/write).
+ *    GFER      	General-Purpose Input/Output (GPIO) Falling-Edge
+ *              	detect Register (read/write).
+ *    GEDR      	General-Purpose Input/Output (GPIO) Edge Detect
+ *              	status Register (read/write).
+ *    GAFR      	General-Purpose Input/Output (GPIO) Alternate
+ *              	Function Register (read/write).
+ *
+ * Clock
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ */
+
+#define _GPLR   	0x90040000	/* GPIO Pin Level Reg.             */
+#define _GPDR   	0x90040004	/* GPIO Pin Direction Reg.         */
+#define _GPSR   	0x90040008	/* GPIO Pin output Set Reg.        */
+#define _GPCR   	0x9004000C	/* GPIO Pin output Clear Reg.      */
+#define _GRER   	0x90040010	/* GPIO Rising-Edge detect Reg.    */
+#define _GFER   	0x90040014	/* GPIO Falling-Edge detect Reg.   */
+#define _GEDR   	0x90040018	/* GPIO Edge Detect status Reg.    */
+#define _GAFR   	0x9004001C	/* GPIO Alternate Function Reg.    */
+
+#if LANGUAGE == C
+#define GPLR    	        	/* GPIO Pin Level Reg.             */ \
+			(*((volatile Word *) io_p2v (_GPLR)))
+#define GPDR    	        	/* GPIO Pin Direction Reg.         */ \
+			(*((volatile Word *) io_p2v (_GPDR)))
+#define GPSR    	        	/* GPIO Pin output Set Reg.        */ \
+			(*((volatile Word *) io_p2v (_GPSR)))
+#define GPCR    	        	/* GPIO Pin output Clear Reg.      */ \
+			(*((volatile Word *) io_p2v (_GPCR)))
+#define GRER    	        	/* GPIO Rising-Edge detect Reg.    */ \
+			(*((volatile Word *) io_p2v (_GRER)))
+#define GFER    	        	/* GPIO Falling-Edge detect Reg.   */ \
+			(*((volatile Word *) io_p2v (_GFER)))
+#define GEDR    	        	/* GPIO Edge Detect status Reg.    */ \
+			(*((volatile Word *) io_p2v (_GEDR)))
+#define GAFR    	        	/* GPIO Alternate Function Reg.    */ \
+			(*((volatile Word *) io_p2v (_GAFR)))
+#elif LANGUAGE == Assembly
+
+#define GPLR  (io_p2v (_GPLR))
+#define GPDR  (io_p2v (_GPDR))
+#define GPSR  (io_p2v (_GPSR))
+#define GPCR  (io_p2v (_GPCR))
+#define GRER  (io_p2v (_GRER))
+#define GFER  (io_p2v (_GFER))
+#define GEDR  (io_p2v (_GEDR))
+#define GAFR  (io_p2v (_GAFR))
+
+#endif /* LANGUAGE == C */
+
+#define GPIO_MIN	(0)
+#define GPIO_MAX	(27)
+
+#define GPIO_GPIO(Nb)	        	/* GPIO [0..27]                    */ \
+			(0x00000001 << (Nb))
+#define GPIO_GPIO0	GPIO_GPIO (0)	/* GPIO  [0]                       */
+#define GPIO_GPIO1	GPIO_GPIO (1)	/* GPIO  [1]                       */
+#define GPIO_GPIO2	GPIO_GPIO (2)	/* GPIO  [2]                       */
+#define GPIO_GPIO3	GPIO_GPIO (3)	/* GPIO  [3]                       */
+#define GPIO_GPIO4	GPIO_GPIO (4)	/* GPIO  [4]                       */
+#define GPIO_GPIO5	GPIO_GPIO (5)	/* GPIO  [5]                       */
+#define GPIO_GPIO6	GPIO_GPIO (6)	/* GPIO  [6]                       */
+#define GPIO_GPIO7	GPIO_GPIO (7)	/* GPIO  [7]                       */
+#define GPIO_GPIO8	GPIO_GPIO (8)	/* GPIO  [8]                       */
+#define GPIO_GPIO9	GPIO_GPIO (9)	/* GPIO  [9]                       */
+#define GPIO_GPIO10	GPIO_GPIO (10)	/* GPIO [10]                       */
+#define GPIO_GPIO11	GPIO_GPIO (11)	/* GPIO [11]                       */
+#define GPIO_GPIO12	GPIO_GPIO (12)	/* GPIO [12]                       */
+#define GPIO_GPIO13	GPIO_GPIO (13)	/* GPIO [13]                       */
+#define GPIO_GPIO14	GPIO_GPIO (14)	/* GPIO [14]                       */
+#define GPIO_GPIO15	GPIO_GPIO (15)	/* GPIO [15]                       */
+#define GPIO_GPIO16	GPIO_GPIO (16)	/* GPIO [16]                       */
+#define GPIO_GPIO17	GPIO_GPIO (17)	/* GPIO [17]                       */
+#define GPIO_GPIO18	GPIO_GPIO (18)	/* GPIO [18]                       */
+#define GPIO_GPIO19	GPIO_GPIO (19)	/* GPIO [19]                       */
+#define GPIO_GPIO20	GPIO_GPIO (20)	/* GPIO [20]                       */
+#define GPIO_GPIO21	GPIO_GPIO (21)	/* GPIO [21]                       */
+#define GPIO_GPIO22	GPIO_GPIO (22)	/* GPIO [22]                       */
+#define GPIO_GPIO23	GPIO_GPIO (23)	/* GPIO [23]                       */
+#define GPIO_GPIO24	GPIO_GPIO (24)	/* GPIO [24]                       */
+#define GPIO_GPIO25	GPIO_GPIO (25)	/* GPIO [25]                       */
+#define GPIO_GPIO26	GPIO_GPIO (26)	/* GPIO [26]                       */
+#define GPIO_GPIO27	GPIO_GPIO (27)	/* GPIO [27]                       */
+
+#define GPIO_LDD(Nb)	        	/* LCD Data [8..15] (O)            */ \
+			GPIO_GPIO ((Nb) - 6)
+#define GPIO_LDD8	GPIO_LDD (8)	/* LCD Data  [8] (O)               */
+#define GPIO_LDD9	GPIO_LDD (9)	/* LCD Data  [9] (O)               */
+#define GPIO_LDD10	GPIO_LDD (10)	/* LCD Data [10] (O)               */
+#define GPIO_LDD11	GPIO_LDD (11)	/* LCD Data [11] (O)               */
+#define GPIO_LDD12	GPIO_LDD (12)	/* LCD Data [12] (O)               */
+#define GPIO_LDD13	GPIO_LDD (13)	/* LCD Data [13] (O)               */
+#define GPIO_LDD14	GPIO_LDD (14)	/* LCD Data [14] (O)               */
+#define GPIO_LDD15	GPIO_LDD (15)	/* LCD Data [15] (O)               */
+					/* ser. port 4:                    */
+#define GPIO_SSP_TXD	GPIO_GPIO (10)	/*  SSP Transmit Data (O)          */
+#define GPIO_SSP_RXD	GPIO_GPIO (11)	/*  SSP Receive Data (I)           */
+#define GPIO_SSP_SCLK	GPIO_GPIO (12)	/*  SSP Sample CLocK (O)           */
+#define GPIO_SSP_SFRM	GPIO_GPIO (13)	/*  SSP Sample FRaMe (O)           */
+					/* ser. port 1:                    */
+#define GPIO_UART_TXD	GPIO_GPIO (14)	/*  UART Transmit Data (O)         */
+#define GPIO_UART_RXD	GPIO_GPIO (15)	/*  UART Receive Data (I)          */
+#define GPIO_SDLC_SCLK	GPIO_GPIO (16)	/*  SDLC Sample CLocK (I/O)        */
+#define GPIO_SDLC_AAF	GPIO_GPIO (17)	/*  SDLC Abort After Frame (O)     */
+#define GPIO_UART_SCLK1	GPIO_GPIO (18)	/*  UART Sample CLocK 1 (I)        */
+					/* ser. port 4:                    */
+#define GPIO_SSP_CLK	GPIO_GPIO (19)	/*  SSP external CLocK (I)         */
+					/* ser. port 3:                    */
+#define GPIO_UART_SCLK3	GPIO_GPIO (20)	/*  UART Sample CLocK 3 (I)        */
+					/* ser. port 4:                    */
+#define GPIO_MCP_CLK	GPIO_GPIO (21)	/*  MCP CLocK (I)                  */
+					/* test controller:                */
+#define GPIO_TIC_ACK	GPIO_GPIO (21)	/*  TIC ACKnowledge (O)            */
+#define GPIO_MBGNT	GPIO_GPIO (21)	/*  Memory Bus GraNT (O)           */
+#define GPIO_TREQA	GPIO_GPIO (22)	/*  TIC REQuest A (I)              */
+#define GPIO_MBREQ	GPIO_GPIO (22)	/*  Memory Bus REQuest (I)         */
+#define GPIO_TREQB	GPIO_GPIO (23)	/*  TIC REQuest B (I)              */
+#define GPIO_1Hz	GPIO_GPIO (25)	/* 1 Hz clock (O)                  */
+#define GPIO_RCLK	GPIO_GPIO (26)	/* internal (R) CLocK (O, fcpu/2)  */
+#define GPIO_32_768kHz	GPIO_GPIO (27)	/* 32.768 kHz clock (O, RTC)       */
+
+#define GPDR_In 	0       	/* Input                           */
+#define GPDR_Out	1       	/* Output                          */
+
+
+/*
+ * Interrupt Controller (IC) control registers
+ *
+ * Registers
+ *    ICIP      	Interrupt Controller (IC) Interrupt ReQuest (IRQ)
+ *              	Pending register (read).
+ *    ICMR      	Interrupt Controller (IC) Mask Register (read/write).
+ *    ICLR      	Interrupt Controller (IC) Level Register (read/write).
+ *    ICCR      	Interrupt Controller (IC) Control Register
+ *              	(read/write).
+ *              	[The ICCR register is only implemented in versions 2.0
+ *              	(rev. = 8) and higher of the StrongARM SA-1100.]
+ *    ICFP      	Interrupt Controller (IC) Fast Interrupt reQuest
+ *              	(FIQ) Pending register (read).
+ *    ICPR      	Interrupt Controller (IC) Pending Register (read).
+ *              	[The ICPR register is active low (inverted) in
+ *              	versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *              	StrongARM SA-1100, it is active high (non-inverted) in
+ *              	versions 2.0 (rev. = 8) and higher.]
+ */
+
+#define _ICIP   	0x90050000	/* IC IRQ Pending reg.             */
+#define _ICMR   	0x90050004	/* IC Mask Reg.                    */
+#define _ICLR   	0x90050008	/* IC Level Reg.                   */
+#define _ICCR   	0x9005000C	/* IC Control Reg.                 */
+#define _ICFP   	0x90050010	/* IC FIQ Pending reg.             */
+#define _ICPR   	0x90050020	/* IC Pending Reg.                 */
+
+#if LANGUAGE == C
+#define ICIP    	        	/* IC IRQ Pending reg.             */ \
+			(*((volatile Word *) io_p2v (_ICIP)))
+#define ICMR    	        	/* IC Mask Reg.                    */ \
+			(*((volatile Word *) io_p2v (_ICMR)))
+#define ICLR    	        	/* IC Level Reg.                   */ \
+			(*((volatile Word *) io_p2v (_ICLR)))
+#define ICCR    	        	/* IC Control Reg.                 */ \
+			(*((volatile Word *) io_p2v (_ICCR)))
+#define ICFP    	        	/* IC FIQ Pending reg.             */ \
+			(*((volatile Word *) io_p2v (_ICFP)))
+#define ICPR    	        	/* IC Pending Reg.                 */ \
+			(*((volatile Word *) io_p2v (_ICPR)))
+#endif /* LANGUAGE == C */
+
+#define IC_GPIO(Nb)	        	/* GPIO [0..10]                    */ \
+			(0x00000001 << (Nb))
+#define IC_GPIO0	IC_GPIO (0)	/* GPIO  [0]                       */
+#define IC_GPIO1	IC_GPIO (1)	/* GPIO  [1]                       */
+#define IC_GPIO2	IC_GPIO (2)	/* GPIO  [2]                       */
+#define IC_GPIO3	IC_GPIO (3)	/* GPIO  [3]                       */
+#define IC_GPIO4	IC_GPIO (4)	/* GPIO  [4]                       */
+#define IC_GPIO5	IC_GPIO (5)	/* GPIO  [5]                       */
+#define IC_GPIO6	IC_GPIO (6)	/* GPIO  [6]                       */
+#define IC_GPIO7	IC_GPIO (7)	/* GPIO  [7]                       */
+#define IC_GPIO8	IC_GPIO (8)	/* GPIO  [8]                       */
+#define IC_GPIO9	IC_GPIO (9)	/* GPIO  [9]                       */
+#define IC_GPIO10	IC_GPIO (10)	/* GPIO [10]                       */
+#define IC_GPIO11_27	0x00000800	/* GPIO [11:27] (ORed)             */
+#define IC_LCD  	0x00001000	/* LCD controller                  */
+#define IC_Ser0UDC	0x00002000	/* Ser. port 0 UDC                 */
+#define IC_Ser1SDLC	0x00004000	/* Ser. port 1 SDLC                */
+#define IC_Ser1UART	0x00008000	/* Ser. port 1 UART                */
+#define IC_Ser2ICP	0x00010000	/* Ser. port 2 ICP                 */
+#define IC_Ser3UART	0x00020000	/* Ser. port 3 UART                */
+#define IC_Ser4MCP	0x00040000	/* Ser. port 4 MCP                 */
+#define IC_Ser4SSP	0x00080000	/* Ser. port 4 SSP                 */
+#define IC_DMA(Nb)	        	/* DMA controller channel [0..5]   */ \
+			(0x00100000 << (Nb))
+#define IC_DMA0 	IC_DMA (0)	/* DMA controller channel 0        */
+#define IC_DMA1 	IC_DMA (1)	/* DMA controller channel 1        */
+#define IC_DMA2 	IC_DMA (2)	/* DMA controller channel 2        */
+#define IC_DMA3 	IC_DMA (3)	/* DMA controller channel 3        */
+#define IC_DMA4 	IC_DMA (4)	/* DMA controller channel 4        */
+#define IC_DMA5 	IC_DMA (5)	/* DMA controller channel 5        */
+#define IC_OST(Nb)	        	/* OS Timer match [0..3]           */ \
+			(0x04000000 << (Nb))
+#define IC_OST0 	IC_OST (0)	/* OS Timer match 0                */
+#define IC_OST1 	IC_OST (1)	/* OS Timer match 1                */
+#define IC_OST2 	IC_OST (2)	/* OS Timer match 2                */
+#define IC_OST3 	IC_OST (3)	/* OS Timer match 3                */
+#define IC_RTC1Hz	0x40000000	/* RTC 1 Hz clock                  */
+#define IC_RTCAlrm	0x80000000	/* RTC Alarm                       */
+
+#define ICLR_IRQ	0       	/* Interrupt ReQuest               */
+#define ICLR_FIQ	1       	/* Fast Interrupt reQuest          */
+
+#define ICCR_DIM	0x00000001	/* Disable Idle-mode interrupt     */
+					/* Mask                            */
+#define ICCR_IdleAllInt	(ICCR_DIM*0)	/*  Idle-mode All Interrupt enable */
+					/*  (ICMR ignored)                 */
+#define ICCR_IdleMskInt	(ICCR_DIM*1)	/*  Idle-mode non-Masked Interrupt */
+					/*  enable (ICMR used)             */
+
+
+/*
+ * Peripheral Pin Controller (PPC) control registers
+ *
+ * Registers
+ *    PPDR      	Peripheral Pin Controller (PPC) Pin Direction
+ *              	Register (read/write).
+ *    PPSR      	Peripheral Pin Controller (PPC) Pin State Register
+ *              	(read/write).
+ *    PPAR      	Peripheral Pin Controller (PPC) Pin Assignment
+ *              	Register (read/write).
+ *    PSDR      	Peripheral Pin Controller (PPC) Sleep-mode pin
+ *              	Direction Register (read/write).
+ *    PPFR      	Peripheral Pin Controller (PPC) Pin Flag Register
+ *              	(read).
+ */
+
+#define _PPDR   	0x90060000	/* PPC Pin Direction Reg.          */
+#define _PPSR   	0x90060004	/* PPC Pin State Reg.              */
+#define _PPAR   	0x90060008	/* PPC Pin Assignment Reg.         */
+#define _PSDR   	0x9006000C	/* PPC Sleep-mode pin Direction    */
+					/* Reg.                            */
+#define _PPFR   	0x90060010	/* PPC Pin Flag Reg.               */
+
+#if LANGUAGE == C
+#define PPDR    	        	/* PPC Pin Direction Reg.          */ \
+			(*((volatile Word *) io_p2v (_PPDR)))
+#define PPSR    	        	/* PPC Pin State Reg.              */ \
+			(*((volatile Word *) io_p2v (_PPSR)))
+#define PPAR    	        	/* PPC Pin Assignment Reg.         */ \
+			(*((volatile Word *) io_p2v (_PPAR)))
+#define PSDR    	        	/* PPC Sleep-mode pin Direction    */ \
+					/* Reg.                            */ \
+			(*((volatile Word *) io_p2v (_PSDR)))
+#define PPFR    	        	/* PPC Pin Flag Reg.               */ \
+			(*((volatile Word *) io_p2v (_PPFR)))
+#endif /* LANGUAGE == C */
+
+#define PPC_LDD(Nb)	        	/* LCD Data [0..7]                 */ \
+			(0x00000001 << (Nb))
+#define PPC_LDD0	PPC_LDD (0)	/* LCD Data [0]                    */
+#define PPC_LDD1	PPC_LDD (1)	/* LCD Data [1]                    */
+#define PPC_LDD2	PPC_LDD (2)	/* LCD Data [2]                    */
+#define PPC_LDD3	PPC_LDD (3)	/* LCD Data [3]                    */
+#define PPC_LDD4	PPC_LDD (4)	/* LCD Data [4]                    */
+#define PPC_LDD5	PPC_LDD (5)	/* LCD Data [5]                    */
+#define PPC_LDD6	PPC_LDD (6)	/* LCD Data [6]                    */
+#define PPC_LDD7	PPC_LDD (7)	/* LCD Data [7]                    */
+#define PPC_L_PCLK	0x00000100	/* LCD Pixel CLocK                 */
+#define PPC_L_LCLK	0x00000200	/* LCD Line CLocK                  */
+#define PPC_L_FCLK	0x00000400	/* LCD Frame CLocK                 */
+#define PPC_L_BIAS	0x00000800	/* LCD AC BIAS                     */
+					/* ser. port 1:                    */
+#define PPC_TXD1	0x00001000	/*  SDLC/UART Transmit Data 1      */
+#define PPC_RXD1	0x00002000	/*  SDLC/UART Receive Data 1       */
+					/* ser. port 2:                    */
+#define PPC_TXD2	0x00004000	/*  IPC Transmit Data 2            */
+#define PPC_RXD2	0x00008000	/*  IPC Receive Data 2             */
+					/* ser. port 3:                    */
+#define PPC_TXD3	0x00010000	/*  UART Transmit Data 3           */
+#define PPC_RXD3	0x00020000	/*  UART Receive Data 3            */
+					/* ser. port 4:                    */
+#define PPC_TXD4	0x00040000	/*  MCP/SSP Transmit Data 4        */
+#define PPC_RXD4	0x00080000	/*  MCP/SSP Receive Data 4         */
+#define PPC_SCLK	0x00100000	/*  MCP/SSP Sample CLocK           */
+#define PPC_SFRM	0x00200000	/*  MCP/SSP Sample FRaMe           */
+
+#define PPDR_In 	0       	/* Input                           */
+#define PPDR_Out	1       	/* Output                          */
+
+					/* ser. port 1:                    */
+#define PPAR_UPR	0x00001000	/*  UART Pin Reassignment          */
+#define PPAR_UARTTR	(PPAR_UPR*0)	/*   UART on TXD_1 & RXD_1         */
+#define PPAR_UARTGPIO	(PPAR_UPR*1)	/*   UART on GPIO [14:15]          */
+					/* ser. port 4:                    */
+#define PPAR_SPR	0x00040000	/*  SSP Pin Reassignment           */
+#define PPAR_SSPTRSS	(PPAR_SPR*0)	/*   SSP on TXD_C, RXD_C, SCLK_C,  */
+					/*   & SFRM_C                      */
+#define PPAR_SSPGPIO	(PPAR_SPR*1)	/*   SSP on GPIO [10:13]           */
+
+#define PSDR_OutL	0       	/* Output Low in sleep mode        */
+#define PSDR_Flt	1       	/* Floating (input) in sleep mode  */
+
+#define PPFR_LCD	0x00000001	/* LCD controller                  */
+#define PPFR_SP1TX	0x00001000	/* Ser. Port 1 SDLC/UART Transmit  */
+#define PPFR_SP1RX	0x00002000	/* Ser. Port 1 SDLC/UART Receive   */
+#define PPFR_SP2TX	0x00004000	/* Ser. Port 2 ICP Transmit        */
+#define PPFR_SP2RX	0x00008000	/* Ser. Port 2 ICP Receive         */
+#define PPFR_SP3TX	0x00010000	/* Ser. Port 3 UART Transmit       */
+#define PPFR_SP3RX	0x00020000	/* Ser. Port 3 UART Receive        */
+#define PPFR_SP4	0x00040000	/* Ser. Port 4 MCP/SSP             */
+#define PPFR_PerEn	0       	/* Peripheral Enabled              */
+#define PPFR_PPCEn	1       	/* PPC Enabled                     */
+
+
+/*
+ * Dynamic Random-Access Memory (DRAM) control registers
+ *
+ * Registers
+ *    MDCNFG    	Memory system: Dynamic Random-Access Memory (DRAM)
+ *              	CoNFiGuration register (read/write).
+ *    MDCAS0    	Memory system: Dynamic Random-Access Memory (DRAM)
+ *              	Column Address Strobe (CAS) shift register 0
+ *              	(read/write).
+ *    MDCAS1    	Memory system: Dynamic Random-Access Memory (DRAM)
+ *              	Column Address Strobe (CAS) shift register 1
+ *              	(read/write).
+ *    MDCAS2    	Memory system: Dynamic Random-Access Memory (DRAM)
+ *              	Column Address Strobe (CAS) shift register 2
+ *              	(read/write).
+ *
+ * Clocks
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem	Frequency, period of the memory clock (fmem = fcpu/2).
+ *    fcas, Tcas	Frequency, period of the DRAM CAS shift registers.
+ */
+
+					/* Memory system:                  */
+#define _MDCNFG 	0xA0000000	/*  DRAM CoNFiGuration reg.        */
+#define _MDCAS(Nb)	        	/*  DRAM CAS shift reg. [0..3]     */ \
+			(0xA0000004 + (Nb)*4)
+#define _MDCAS0 	_MDCAS (0)	/*  DRAM CAS shift reg. 0          */
+#define _MDCAS1 	_MDCAS (1)	/*  DRAM CAS shift reg. 1          */
+#define _MDCAS2 	_MDCAS (2)	/*  DRAM CAS shift reg. 2          */
+
+#if LANGUAGE == C
+					/* Memory system:                  */
+#define MDCNFG  	        	/*  DRAM CoNFiGuration reg.        */ \
+			(*((volatile Word *) io_p2v (_MDCNFG)))
+#define MDCAS   	        	/*  DRAM CAS shift reg. [0..3]     */ \
+			((volatile Word *) io_p2v (_MDCAS (0)))
+#define MDCAS0  	(MDCAS [0])	/*  DRAM CAS shift reg. 0          */
+#define MDCAS1  	(MDCAS [1])	/*  DRAM CAS shift reg. 1          */
+#define MDCAS2  	(MDCAS [2])	/*  DRAM CAS shift reg. 2          */
+
+#elif LANGUAGE == Assembly
+
+#define MDCNFG		(io_p2v(_MDCNFG))
+
+#endif /* LANGUAGE == C */
+
+/* SA1100 MDCNFG values */
+#define MDCNFG_DE(Nb)	        	/* DRAM Enable bank [0..3]         */ \
+			(0x00000001 << (Nb))
+#define MDCNFG_DE0	MDCNFG_DE (0)	/* DRAM Enable bank 0              */
+#define MDCNFG_DE1	MDCNFG_DE (1)	/* DRAM Enable bank 1              */
+#define MDCNFG_DE2	MDCNFG_DE (2)	/* DRAM Enable bank 2              */
+#define MDCNFG_DE3	MDCNFG_DE (3)	/* DRAM Enable bank 3              */
+#define MDCNFG_DRAC	Fld (2, 4)	/* DRAM Row Address Count - 9      */
+#define MDCNFG_RowAdd(Add)      	/*  Row Address count [9..12]      */ \
+			(((Add) - 9) << FShft (MDCNFG_DRAC))
+#define MDCNFG_CDB2	0x00000040	/* shift reg. Clock Divide By 2    */
+					/* (fcas = fcpu/2)                 */
+#define MDCNFG_TRP	Fld (4, 7)	/* Time RAS Pre-charge - 1 [Tmem]  */
+#define MDCNFG_PrChrg(Tcpu)     	/*  Pre-Charge time [2..32 Tcpu]   */ \
+			(((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
+#define MDCNFG_CeilPrChrg(Tcpu) 	/*  Ceil. of PrChrg [2..32 Tcpu]   */ \
+			(((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
+#define MDCNFG_TRASR	Fld (4, 11)	/* Time RAS Refresh - 1 [Tmem]     */
+#define MDCNFG_Ref(Tcpu)        	/*  Refresh time [2..32 Tcpu]      */ \
+			(((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
+#define MDCNFG_CeilRef(Tcpu)    	/*  Ceil. of Ref [2..32 Tcpu]      */ \
+			(((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
+#define MDCNFG_TDL	Fld (2, 15)	/* Time Data Latch [Tcpu]          */
+#define MDCNFG_DataLtch(Tcpu)   	/*  Data Latch delay [0..3 Tcpu]   */ \
+			((Tcpu) << FShft (MDCNFG_TDL))
+#define MDCNFG_DRI	Fld (15, 17)	/* min. DRAM Refresh Interval/4    */
+					/* [Tmem]                          */
+#define MDCNFG_RefInt(Tcpu)     	/*  min. Refresh Interval          */ \
+					/*  [0..262136 Tcpu]               */ \
+			((Tcpu)/8 << FShft (MDCNFG_DRI))
+
+/* SA1110 MDCNFG values */
+#define MDCNFG_SA1110_DE0	0x00000001	/* DRAM Enable bank 0        */
+#define MDCNFG_SA1110_DE1	0x00000002 	/* DRAM Enable bank 1        */
+#define MDCNFG_SA1110_DTIM0	0x00000004	/* DRAM timing type 0/1      */
+#define MDCNFG_SA1110_DWID0	0x00000008	/* DRAM bus width 0/1        */
+#define MDCNFG_SA1110_DRAC0	Fld(3, 4)	/* DRAM row addr bit count   */
+						/* bank 0/1                  */
+#define MDCNFG_SA1110_CDB20	0x00000080	/* Mem Clock divide by 2 0/1 */
+#define MDCNFG_SA1110_TRP0	Fld(3, 8)	/* RAS precharge 0/1         */
+#define MDCNFG_SA1110_TDL0	Fld(2, 12)	/* Data input latch after CAS*/
+						/* deassertion 0/1           */
+#define MDCNFG_SA1110_TWR0	Fld(2, 14)	/* SDRAM write recovery 0/1  */
+#define MDCNFG_SA1110_DE2	0x00010000	/* DRAM Enable bank 0        */
+#define MDCNFG_SA1110_DE3	0x00020000 	/* DRAM Enable bank 1        */
+#define MDCNFG_SA1110_DTIM2	0x00040000	/* DRAM timing type 0/1      */
+#define MDCNFG_SA1110_DWID2	0x00080000	/* DRAM bus width 0/1        */
+#define MDCNFG_SA1110_DRAC2	Fld(3, 20)	/* DRAM row addr bit count   */
+						/* bank 0/1                  */
+#define MDCNFG_SA1110_CDB22	0x00800000	/* Mem Clock divide by 2 0/1 */
+#define MDCNFG_SA1110_TRP2	Fld(3, 24)	/* RAS precharge 0/1         */
+#define MDCNFG_SA1110_TDL2	Fld(2, 28)	/* Data input latch after CAS*/
+						/* deassertion 0/1           */
+#define MDCNFG_SA1110_TWR2	Fld(2, 30)	/* SDRAM write recovery 0/1  */
+
+
+/*
+ * Static memory control registers
+ *
+ * Registers
+ *    MSC0      	Memory system: Static memory Control register 0
+ *              	(read/write).
+ *    MSC1      	Memory system: Static memory Control register 1
+ *              	(read/write).
+ *
+ * Clocks
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem	Frequency, period of the memory clock (fmem = fcpu/2).
+ */
+
+					/* Memory system:                  */
+#define _MSC(Nb)	        	/*  Static memory Control reg.     */ \
+					/*  [0..1]                         */ \
+			(0xA0000010 + (Nb)*4)
+#define _MSC0   	_MSC (0)	/*  Static memory Control reg. 0   */
+#define _MSC1   	_MSC (1)	/*  Static memory Control reg. 1   */
+#define _MSC2		0xA000002C	/*  Static memory Control reg. 2, not contiguous   */
+
+#if LANGUAGE == C
+					/* Memory system:                  */
+#define MSC     	        	/*  Static memory Control reg.     */ \
+					/*  [0..1]                         */ \
+			((volatile Word *) io_p2v (_MSC (0)))
+#define MSC0    	(MSC [0])	/*  Static memory Control reg. 0   */
+#define MSC1    	(MSC [1])	/*  Static memory Control reg. 1   */
+#define MSC2    	(*(volatile Word *) io_p2v (_MSC2))	/*  Static memory Control reg. 2   */
+
+#elif LANGUAGE == Assembly
+
+#define MSC0		io_p2v(0xa0000010)
+#define MSC1		io_p2v(0xa0000014)
+#define MSC2		io_p2v(0xa000002c)
+
+#endif /* LANGUAGE == C */
+
+#define MSC_Bnk(Nb)	        	/* static memory Bank [0..3]       */ \
+			Fld (16, ((Nb) Modulo 2)*16)
+#define MSC0_Bnk0	MSC_Bnk (0)	/* static memory Bank 0            */
+#define MSC0_Bnk1	MSC_Bnk (1)	/* static memory Bank 1            */
+#define MSC1_Bnk2	MSC_Bnk (2)	/* static memory Bank 2            */
+#define MSC1_Bnk3	MSC_Bnk (3)	/* static memory Bank 3            */
+
+#define MSC_RT  	Fld (2, 0)	/* ROM/static memory Type          */
+#define MSC_NonBrst	        	/*  Non-Burst static memory        */ \
+			(0 << FShft (MSC_RT))
+#define MSC_SRAM	        	/*  32-bit byte-writable SRAM      */ \
+			(1 << FShft (MSC_RT))
+#define MSC_Brst4	        	/*  Burst-of-4 static memory       */ \
+			(2 << FShft (MSC_RT))
+#define MSC_Brst8	        	/*  Burst-of-8 static memory       */ \
+			(3 << FShft (MSC_RT))
+#define MSC_RBW 	0x0004  	/* ROM/static memory Bus Width     */
+#define MSC_32BitStMem	(MSC_RBW*0)	/*  32-Bit Static Memory           */
+#define MSC_16BitStMem	(MSC_RBW*1)	/*  16-Bit Static Memory           */
+#define MSC_RDF 	Fld (5, 3)	/* ROM/static memory read Delay    */
+					/* First access - 1(.5) [Tmem]     */
+#define MSC_1stRdAcc(Tcpu)      	/*  1st Read Access time (burst    */ \
+					/*  static memory) [3..65 Tcpu]    */ \
+			((((Tcpu) - 3)/2) << FShft (MSC_RDF))
+#define MSC_Ceil1stRdAcc(Tcpu)  	/*  Ceil. of 1stRdAcc [3..65 Tcpu] */ \
+			((((Tcpu) - 2)/2) << FShft (MSC_RDF))
+#define MSC_RdAcc(Tcpu)	        	/*  Read Access time (non-burst    */ \
+					/*  static memory) [2..64 Tcpu]    */ \
+			((((Tcpu) - 2)/2) << FShft (MSC_RDF))
+#define MSC_CeilRdAcc(Tcpu)     	/*  Ceil. of RdAcc [2..64 Tcpu]    */ \
+			((((Tcpu) - 1)/2) << FShft (MSC_RDF))
+#define MSC_RDN 	Fld (5, 8)	/* ROM/static memory read Delay    */
+					/* Next access - 1 [Tmem]          */
+#define MSC_NxtRdAcc(Tcpu)      	/*  Next Read Access time (burst   */ \
+					/*  static memory) [2..64 Tcpu]    */ \
+			((((Tcpu) - 2)/2) << FShft (MSC_RDN))
+#define MSC_CeilNxtRdAcc(Tcpu)  	/*  Ceil. of NxtRdAcc [2..64 Tcpu] */ \
+			((((Tcpu) - 1)/2) << FShft (MSC_RDN))
+#define MSC_WrAcc(Tcpu)	        	/*  Write Access time (non-burst   */ \
+					/*  static memory) [2..64 Tcpu]    */ \
+			((((Tcpu) - 2)/2) << FShft (MSC_RDN))
+#define MSC_CeilWrAcc(Tcpu)     	/*  Ceil. of WrAcc [2..64 Tcpu]    */ \
+			((((Tcpu) - 1)/2) << FShft (MSC_RDN))
+#define MSC_RRR 	Fld (3, 13)	/* ROM/static memory RecoveRy      */
+					/* time/2 [Tmem]                   */
+#define MSC_Rec(Tcpu)	        	/*  Recovery time [0..28 Tcpu]     */ \
+			(((Tcpu)/4) << FShft (MSC_RRR))
+#define MSC_CeilRec(Tcpu)       	/*  Ceil. of Rec [0..28 Tcpu]      */ \
+			((((Tcpu) + 3)/4) << FShft (MSC_RRR))
+
+
+/*
+ * Personal Computer Memory Card International Association (PCMCIA) control
+ * register
+ *
+ * Register
+ *    MECR      	Memory system: Expansion memory bus (PCMCIA)
+ *              	Configuration Register (read/write).
+ *
+ * Clocks
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem	Frequency, period of the memory clock (fmem = fcpu/2).
+ *    fbclk, Tbclk	Frequency, period of the PCMCIA clock (BCLK).
+ */
+
+					/* Memory system:                  */
+#define _MECR   	0xA0000018	/*  Expansion memory bus (PCMCIA)  */
+					/*  Configuration Reg.             */
+
+#if LANGUAGE == C
+					/* Memory system:                  */
+#define MECR    	        	/*  Expansion memory bus (PCMCIA)  */ \
+					/*  Configuration Reg.             */ \
+			(*((volatile Word *) io_p2v (_MECR)))
+#endif /* LANGUAGE == C */
+
+#define MECR_PCMCIA(Nb)	        	/* PCMCIA [0..1]                   */ \
+			Fld (15, (Nb)*16)
+#define MECR_PCMCIA0	MECR_PCMCIA (0)	/* PCMCIA 0                        */
+#define MECR_PCMCIA1	MECR_PCMCIA (1)	/* PCMCIA 1                        */
+
+#define MECR_BSIO	Fld (5, 0)	/* BCLK Select I/O - 1 [Tmem]      */
+#define MECR_IOClk(Tcpu)        	/*  I/O Clock [2..64 Tcpu]         */ \
+			((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
+#define MECR_CeilIOClk(Tcpu)    	/*  Ceil. of IOClk [2..64 Tcpu]    */ \
+			((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
+#define MECR_BSA	Fld (5, 5)	/* BCLK Select Attribute - 1       */
+					/* [Tmem]                          */
+#define MECR_AttrClk(Tcpu)      	/*  Attribute Clock [2..64 Tcpu]   */ \
+			((((Tcpu) - 2)/2) << FShft (MECR_BSA))
+#define MECR_CeilAttrClk(Tcpu)  	/*  Ceil. of AttrClk [2..64 Tcpu]  */ \
+			((((Tcpu) - 1)/2) << FShft (MECR_BSA))
+#define MECR_BSM	Fld (5, 10)	/* BCLK Select Memory - 1 [Tmem]   */
+#define MECR_MemClk(Tcpu)       	/*  Memory Clock [2..64 Tcpu]      */ \
+			((((Tcpu) - 2)/2) << FShft (MECR_BSM))
+#define MECR_CeilMemClk(Tcpu)   	/*  Ceil. of MemClk [2..64 Tcpu]   */ \
+			((((Tcpu) - 1)/2) << FShft (MECR_BSM))
+
+/*
+ * On SA1110 only
+ */
+
+#define _MDREFR		0xA000001C
+
+#if LANGUAGE == C
+					/* Memory system:                  */
+#define MDREFR \
+			(*((volatile Word *) io_p2v (_MDREFR)))
+
+#elif LANGUAGE == Assembly
+
+#define MDREFR		(io_p2v(_MDREFR))
+
+#endif /* LANGUAGE == C */
+
+#define MDREFR_TRASR		Fld (4, 0)
+#define MDREFR_DRI		Fld (12, 4)
+#define MDREFR_E0PIN		(1 << 16)
+#define MDREFR_K0RUN		(1 << 17)
+#define MDREFR_K0DB2		(1 << 18)
+#define MDREFR_E1PIN		(1 << 20)
+#define MDREFR_K1RUN		(1 << 21)
+#define MDREFR_K1DB2		(1 << 22)
+#define MDREFR_K2RUN		(1 << 25)
+#define MDREFR_K2DB2		(1 << 26)
+#define MDREFR_EAPD		(1 << 28)
+#define MDREFR_KAPD		(1 << 29)
+#define MDREFR_SLFRSH		(1 << 31)
+
+
+/*
+ * Direct Memory Access (DMA) control registers
+ *
+ * Registers
+ *    DDAR0     	Direct Memory Access (DMA) Device Address Register
+ *              	channel 0 (read/write).
+ *    DCSR0     	Direct Memory Access (DMA) Control and Status
+ *              	Register channel 0 (read/write).
+ *    DBSA0     	Direct Memory Access (DMA) Buffer Start address
+ *              	register A channel 0 (read/write).
+ *    DBTA0     	Direct Memory Access (DMA) Buffer Transfer count
+ *              	register A channel 0 (read/write).
+ *    DBSB0     	Direct Memory Access (DMA) Buffer Start address
+ *              	register B channel 0 (read/write).
+ *    DBTB0     	Direct Memory Access (DMA) Buffer Transfer count
+ *              	register B channel 0 (read/write).
+ *
+ *    DDAR1     	Direct Memory Access (DMA) Device Address Register
+ *              	channel 1 (read/write).
+ *    DCSR1     	Direct Memory Access (DMA) Control and Status
+ *              	Register channel 1 (read/write).
+ *    DBSA1     	Direct Memory Access (DMA) Buffer Start address
+ *              	register A channel 1 (read/write).
+ *    DBTA1     	Direct Memory Access (DMA) Buffer Transfer count
+ *              	register A channel 1 (read/write).
+ *    DBSB1     	Direct Memory Access (DMA) Buffer Start address
+ *              	register B channel 1 (read/write).
+ *    DBTB1     	Direct Memory Access (DMA) Buffer Transfer count
+ *              	register B channel 1 (read/write).
+ *
+ *    DDAR2     	Direct Memory Access (DMA) Device Address Register
+ *              	channel 2 (read/write).
+ *    DCSR2     	Direct Memory Access (DMA) Control and Status
+ *              	Register channel 2 (read/write).
+ *    DBSA2     	Direct Memory Access (DMA) Buffer Start address
+ *              	register A channel 2 (read/write).
+ *    DBTA2     	Direct Memory Access (DMA) Buffer Transfer count
+ *              	register A channel 2 (read/write).
+ *    DBSB2     	Direct Memory Access (DMA) Buffer Start address
+ *              	register B channel 2 (read/write).
+ *    DBTB2     	Direct Memory Access (DMA) Buffer Transfer count
+ *              	register B channel 2 (read/write).
+ *
+ *    DDAR3     	Direct Memory Access (DMA) Device Address Register
+ *              	channel 3 (read/write).
+ *    DCSR3     	Direct Memory Access (DMA) Control and Status
+ *              	Register channel 3 (read/write).
+ *    DBSA3     	Direct Memory Access (DMA) Buffer Start address
+ *              	register A channel 3 (read/write).
+ *    DBTA3     	Direct Memory Access (DMA) Buffer Transfer count
+ *              	register A channel 3 (read/write).
+ *    DBSB3     	Direct Memory Access (DMA) Buffer Start address
+ *              	register B channel 3 (read/write).
+ *    DBTB3     	Direct Memory Access (DMA) Buffer Transfer count
+ *              	register B channel 3 (read/write).
+ *
+ *    DDAR4     	Direct Memory Access (DMA) Device Address Register
+ *              	channel 4 (read/write).
+ *    DCSR4     	Direct Memory Access (DMA) Control and Status
+ *              	Register channel 4 (read/write).
+ *    DBSA4     	Direct Memory Access (DMA) Buffer Start address
+ *              	register A channel 4 (read/write).
+ *    DBTA4     	Direct Memory Access (DMA) Buffer Transfer count
+ *              	register A channel 4 (read/write).
+ *    DBSB4     	Direct Memory Access (DMA) Buffer Start address
+ *              	register B channel 4 (read/write).
+ *    DBTB4     	Direct Memory Access (DMA) Buffer Transfer count
+ *              	register B channel 4 (read/write).
+ *
+ *    DDAR5     	Direct Memory Access (DMA) Device Address Register
+ *              	channel 5 (read/write).
+ *    DCSR5     	Direct Memory Access (DMA) Control and Status
+ *              	Register channel 5 (read/write).
+ *    DBSA5     	Direct Memory Access (DMA) Buffer Start address
+ *              	register A channel 5 (read/write).
+ *    DBTA5     	Direct Memory Access (DMA) Buffer Transfer count
+ *              	register A channel 5 (read/write).
+ *    DBSB5     	Direct Memory Access (DMA) Buffer Start address
+ *              	register B channel 5 (read/write).
+ *    DBTB5     	Direct Memory Access (DMA) Buffer Transfer count
+ *              	register B channel 5 (read/write).
+ */
+
+#define DMASp   	0x00000020	/* DMA control reg. Space [byte]   */
+
+#define _DDAR(Nb)	        	/* DMA Device Address Reg.         */ \
+					/* channel [0..5]                  */ \
+			(0xB0000000 + (Nb)*DMASp)
+#define _SetDCSR(Nb)	        	/* Set DMA Control & Status Reg.   */ \
+					/* channel [0..5] (write)          */ \
+			(0xB0000004 + (Nb)*DMASp)
+#define _ClrDCSR(Nb)	        	/* Clear DMA Control & Status Reg. */ \
+					/* channel [0..5] (write)          */ \
+			(0xB0000008 + (Nb)*DMASp)
+#define _RdDCSR(Nb)	        	/* Read DMA Control & Status Reg.  */ \
+					/* channel [0..5] (read)           */ \
+			(0xB000000C + (Nb)*DMASp)
+#define _DBSA(Nb)	        	/* DMA Buffer Start address reg. A */ \
+					/* channel [0..5]                  */ \
+			(0xB0000010 + (Nb)*DMASp)
+#define _DBTA(Nb)	        	/* DMA Buffer Transfer count       */ \
+					/* reg. A channel [0..5]           */ \
+			(0xB0000014 + (Nb)*DMASp)
+#define _DBSB(Nb)	        	/* DMA Buffer Start address reg. B */ \
+					/* channel [0..5]                  */ \
+			(0xB0000018 + (Nb)*DMASp)
+#define _DBTB(Nb)	        	/* DMA Buffer Transfer count       */ \
+					/* reg. B channel [0..5]           */ \
+			(0xB000001C + (Nb)*DMASp)
+
+#define _DDAR0  	_DDAR (0)	/* DMA Device Address Reg.         */
+					/* channel 0                       */
+#define _SetDCSR0	_SetDCSR (0)	/* Set DMA Control & Status Reg.   */
+					/* channel 0 (write)               */
+#define _ClrDCSR0	_ClrDCSR (0)	/* Clear DMA Control & Status Reg. */
+					/* channel 0 (write)               */
+#define _RdDCSR0	_RdDCSR (0)	/* Read DMA Control & Status Reg.  */
+					/* channel 0 (read)                */
+#define _DBSA0  	_DBSA (0)	/* DMA Buffer Start address reg. A */
+					/* channel 0                       */
+#define _DBTA0  	_DBTA (0)	/* DMA Buffer Transfer count       */
+					/* reg. A channel 0                */
+#define _DBSB0  	_DBSB (0)	/* DMA Buffer Start address reg. B */
+					/* channel 0                       */
+#define _DBTB0  	_DBTB (0)	/* DMA Buffer Transfer count       */
+					/* reg. B channel 0                */
+
+#define _DDAR1  	_DDAR (1)	/* DMA Device Address Reg.         */
+					/* channel 1                       */
+#define _SetDCSR1	_SetDCSR (1)	/* Set DMA Control & Status Reg.   */
+					/* channel 1 (write)               */
+#define _ClrDCSR1	_ClrDCSR (1)	/* Clear DMA Control & Status Reg. */
+					/* channel 1 (write)               */
+#define _RdDCSR1	_RdDCSR (1)	/* Read DMA Control & Status Reg.  */
+					/* channel 1 (read)                */
+#define _DBSA1  	_DBSA (1)	/* DMA Buffer Start address reg. A */
+					/* channel 1                       */
+#define _DBTA1  	_DBTA (1)	/* DMA Buffer Transfer count       */
+					/* reg. A channel 1                */
+#define _DBSB1  	_DBSB (1)	/* DMA Buffer Start address reg. B */
+					/* channel 1                       */
+#define _DBTB1  	_DBTB (1)	/* DMA Buffer Transfer count       */
+					/* reg. B channel 1                */
+
+#define _DDAR2  	_DDAR (2)	/* DMA Device Address Reg.         */
+					/* channel 2                       */
+#define _SetDCSR2	_SetDCSR (2)	/* Set DMA Control & Status Reg.   */
+					/* channel 2 (write)               */
+#define _ClrDCSR2	_ClrDCSR (2)	/* Clear DMA Control & Status Reg. */
+					/* channel 2 (write)               */
+#define _RdDCSR2	_RdDCSR (2)	/* Read DMA Control & Status Reg.  */
+					/* channel 2 (read)                */
+#define _DBSA2  	_DBSA (2)	/* DMA Buffer Start address reg. A */
+					/* channel 2                       */
+#define _DBTA2  	_DBTA (2)	/* DMA Buffer Transfer count       */
+					/* reg. A channel 2                */
+#define _DBSB2  	_DBSB (2)	/* DMA Buffer Start address reg. B */
+					/* channel 2                       */
+#define _DBTB2  	_DBTB (2)	/* DMA Buffer Transfer count       */
+					/* reg. B channel 2                */
+
+#define _DDAR3  	_DDAR (3)	/* DMA Device Address Reg.         */
+					/* channel 3                       */
+#define _SetDCSR3	_SetDCSR (3)	/* Set DMA Control & Status Reg.   */
+					/* channel 3 (write)               */
+#define _ClrDCSR3	_ClrDCSR (3)	/* Clear DMA Control & Status Reg. */
+					/* channel 3 (write)               */
+#define _RdDCSR3	_RdDCSR (3)	/* Read DMA Control & Status Reg.  */
+					/* channel 3 (read)                */
+#define _DBSA3  	_DBSA (3)	/* DMA Buffer Start address reg. A */
+					/* channel 3                       */
+#define _DBTA3  	_DBTA (3)	/* DMA Buffer Transfer count       */
+					/* reg. A channel 3                */
+#define _DBSB3  	_DBSB (3)	/* DMA Buffer Start address reg. B */
+					/* channel 3                       */
+#define _DBTB3  	_DBTB (3)	/* DMA Buffer Transfer count       */
+					/* reg. B channel 3                */
+
+#define _DDAR4  	_DDAR (4)	/* DMA Device Address Reg.         */
+					/* channel 4                       */
+#define _SetDCSR4	_SetDCSR (4)	/* Set DMA Control & Status Reg.   */
+					/* channel 4 (write)               */
+#define _ClrDCSR4	_ClrDCSR (4)	/* Clear DMA Control & Status Reg. */
+					/* channel 4 (write)               */
+#define _RdDCSR4	_RdDCSR (4)	/* Read DMA Control & Status Reg.  */
+					/* channel 4 (read)                */
+#define _DBSA4  	_DBSA (4)	/* DMA Buffer Start address reg. A */
+					/* channel 4                       */
+#define _DBTA4  	_DBTA (4)	/* DMA Buffer Transfer count       */
+					/* reg. A channel 4                */
+#define _DBSB4  	_DBSB (4)	/* DMA Buffer Start address reg. B */
+					/* channel 4                       */
+#define _DBTB4  	_DBTB (4)	/* DMA Buffer Transfer count       */
+					/* reg. B channel 4                */
+
+#define _DDAR5  	_DDAR (5)	/* DMA Device Address Reg.         */
+					/* channel 5                       */
+#define _SetDCSR5	_SetDCSR (5)	/* Set DMA Control & Status Reg.   */
+					/* channel 5 (write)               */
+#define _ClrDCSR5	_ClrDCSR (5)	/* Clear DMA Control & Status Reg. */
+					/* channel 5 (write)               */
+#define _RdDCSR5	_RdDCSR (5)	/* Read DMA Control & Status Reg.  */
+					/* channel 5 (read)                */
+#define _DBSA5  	_DBSA (5)	/* DMA Buffer Start address reg. A */
+					/* channel 5                       */
+#define _DBTA5  	_DBTA (5)	/* DMA Buffer Transfer count       */
+					/* reg. A channel 5                */
+#define _DBSB5  	_DBSB (5)	/* DMA Buffer Start address reg. B */
+					/* channel 5                       */
+#define _DBTB5  	_DBTB (5)	/* DMA Buffer Transfer count       */
+					/* reg. B channel 5                */
+
+#if LANGUAGE == C
+
+#define DDAR0   	        	/* DMA Device Address Reg.         */ \
+					/* channel 0                       */ \
+			(*((volatile Word *) io_p2v (_DDAR0)))
+#define SetDCSR0	        	/* Set DMA Control & Status Reg.   */ \
+					/* channel 0 (write)               */ \
+			(*((volatile Word *) io_p2v (_SetDCSR0)))
+#define ClrDCSR0	        	/* Clear DMA Control & Status Reg. */ \
+					/* channel 0 (write)               */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR0)))
+#define RdDCSR0 	        	/* Read DMA Control & Status Reg.  */ \
+					/* channel 0 (read)                */ \
+			(*((volatile Word *) io_p2v (_RdDCSR0)))
+#define DBSA0   	        	/* DMA Buffer Start address reg. A */ \
+					/* channel 0                       */ \
+			(*((volatile Address *) io_p2v (_DBSA0)))
+#define DBTA0   	        	/* DMA Buffer Transfer count       */ \
+					/* reg. A channel 0                */ \
+			(*((volatile Word *) io_p2v (_DBTA0)))
+#define DBSB0   	        	/* DMA Buffer Start address reg. B */ \
+					/* channel 0                       */ \
+			(*((volatile Address *) io_p2v (_DBSB0)))
+#define DBTB0   	        	/* DMA Buffer Transfer count       */ \
+					/* reg. B channel 0                */ \
+			(*((volatile Word *) io_p2v (_DBTB0)))
+
+#define DDAR1   	        	/* DMA Device Address Reg.         */ \
+					/* channel 1                       */ \
+			(*((volatile Word *) io_p2v (_DDAR1)))
+#define SetDCSR1	        	/* Set DMA Control & Status Reg.   */ \
+					/* channel 1 (write)               */ \
+			(*((volatile Word *) io_p2v (_SetDCSR1)))
+#define ClrDCSR1	        	/* Clear DMA Control & Status Reg. */ \
+					/* channel 1 (write)               */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR1)))
+#define RdDCSR1 	        	/* Read DMA Control & Status Reg.  */ \
+					/* channel 1 (read)                */ \
+			(*((volatile Word *) io_p2v (_RdDCSR1)))
+#define DBSA1   	        	/* DMA Buffer Start address reg. A */ \
+					/* channel 1                       */ \
+			(*((volatile Address *) io_p2v (_DBSA1)))
+#define DBTA1   	        	/* DMA Buffer Transfer count       */ \
+					/* reg. A channel 1                */ \
+			(*((volatile Word *) io_p2v (_DBTA1)))
+#define DBSB1   	        	/* DMA Buffer Start address reg. B */ \
+					/* channel 1                       */ \
+			(*((volatile Address *) io_p2v (_DBSB1)))
+#define DBTB1   	        	/* DMA Buffer Transfer count       */ \
+					/* reg. B channel 1                */ \
+			(*((volatile Word *) io_p2v (_DBTB1)))
+
+#define DDAR2   	        	/* DMA Device Address Reg.         */ \
+					/* channel 2                       */ \
+			(*((volatile Word *) io_p2v (_DDAR2)))
+#define SetDCSR2	        	/* Set DMA Control & Status Reg.   */ \
+					/* channel 2 (write)               */ \
+			(*((volatile Word *) io_p2v (_SetDCSR2)))
+#define ClrDCSR2	        	/* Clear DMA Control & Status Reg. */ \
+					/* channel 2 (write)               */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR2)))
+#define RdDCSR2 	        	/* Read DMA Control & Status Reg.  */ \
+					/* channel 2 (read)                */ \
+			(*((volatile Word *) io_p2v (_RdDCSR2)))
+#define DBSA2   	        	/* DMA Buffer Start address reg. A */ \
+					/* channel 2                       */ \
+			(*((volatile Address *) io_p2v (_DBSA2)))
+#define DBTA2   	        	/* DMA Buffer Transfer count       */ \
+					/* reg. A channel 2                */ \
+			(*((volatile Word *) io_p2v (_DBTA2)))
+#define DBSB2   	        	/* DMA Buffer Start address reg. B */ \
+					/* channel 2                       */ \
+			(*((volatile Address *) io_p2v (_DBSB2)))
+#define DBTB2   	        	/* DMA Buffer Transfer count       */ \
+					/* reg. B channel 2                */ \
+			(*((volatile Word *) io_p2v (_DBTB2)))
+
+#define DDAR3   	        	/* DMA Device Address Reg.         */ \
+					/* channel 3                       */ \
+			(*((volatile Word *) io_p2v (_DDAR3)))
+#define SetDCSR3	        	/* Set DMA Control & Status Reg.   */ \
+					/* channel 3 (write)               */ \
+			(*((volatile Word *) io_p2v (_SetDCSR3)))
+#define ClrDCSR3	        	/* Clear DMA Control & Status Reg. */ \
+					/* channel 3 (write)               */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR3)))
+#define RdDCSR3 	        	/* Read DMA Control & Status Reg.  */ \
+					/* channel 3 (read)                */ \
+			(*((volatile Word *) io_p2v (_RdDCSR3)))
+#define DBSA3   	        	/* DMA Buffer Start address reg. A */ \
+					/* channel 3                       */ \
+			(*((volatile Address *) io_p2v (_DBSA3)))
+#define DBTA3   	        	/* DMA Buffer Transfer count       */ \
+					/* reg. A channel 3                */ \
+			(*((volatile Word *) io_p2v (_DBTA3)))
+#define DBSB3   	        	/* DMA Buffer Start address reg. B */ \
+					/* channel 3                       */ \
+			(*((volatile Address *) io_p2v (_DBSB3)))
+#define DBTB3   	        	/* DMA Buffer Transfer count       */ \
+					/* reg. B channel 3                */ \
+			(*((volatile Word *) io_p2v (_DBTB3)))
+
+#define DDAR4   	        	/* DMA Device Address Reg.         */ \
+					/* channel 4                       */ \
+			(*((volatile Word *) io_p2v (_DDAR4)))
+#define SetDCSR4	        	/* Set DMA Control & Status Reg.   */ \
+					/* channel 4 (write)               */ \
+			(*((volatile Word *) io_p2v (_SetDCSR4)))
+#define ClrDCSR4	        	/* Clear DMA Control & Status Reg. */ \
+					/* channel 4 (write)               */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR4)))
+#define RdDCSR4 	        	/* Read DMA Control & Status Reg.  */ \
+					/* channel 4 (read)                */ \
+			(*((volatile Word *) io_p2v (_RdDCSR4)))
+#define DBSA4   	        	/* DMA Buffer Start address reg. A */ \
+					/* channel 4                       */ \
+			(*((volatile Address *) io_p2v (_DBSA4)))
+#define DBTA4   	        	/* DMA Buffer Transfer count       */ \
+					/* reg. A channel 4                */ \
+			(*((volatile Word *) io_p2v (_DBTA4)))
+#define DBSB4   	        	/* DMA Buffer Start address reg. B */ \
+					/* channel 4                       */ \
+			(*((volatile Address *) io_p2v (_DBSB4)))
+#define DBTB4   	        	/* DMA Buffer Transfer count       */ \
+					/* reg. B channel 4                */ \
+			(*((volatile Word *) io_p2v (_DBTB4)))
+
+#define DDAR5   	        	/* DMA Device Address Reg.         */ \
+					/* channel 5                       */ \
+			(*((volatile Word *) io_p2v (_DDAR5)))
+#define SetDCSR5	        	/* Set DMA Control & Status Reg.   */ \
+					/* channel 5 (write)               */ \
+			(*((volatile Word *) io_p2v (_SetDCSR5)))
+#define ClrDCSR5	        	/* Clear DMA Control & Status Reg. */ \
+					/* channel 5 (write)               */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR5)))
+#define RdDCSR5 	        	/* Read DMA Control & Status Reg.  */ \
+					/* channel 5 (read)                */ \
+			(*((volatile Word *) io_p2v (_RdDCSR5)))
+#define DBSA5   	        	/* DMA Buffer Start address reg. A */ \
+					/* channel 5                       */ \
+			(*((volatile Address *) io_p2v (_DBSA5)))
+#define DBTA5   	        	/* DMA Buffer Transfer count       */ \
+					/* reg. A channel 5                */ \
+			(*((volatile Word *) io_p2v (_DBTA5)))
+#define DBSB5   	        	/* DMA Buffer Start address reg. B */ \
+					/* channel 5                       */ \
+			(*((volatile Address *) io_p2v (_DBSB5)))
+#define DBTB5   	        	/* DMA Buffer Transfer count       */ \
+					/* reg. B channel 5                */ \
+			(*((volatile Word *) io_p2v (_DBTB5)))
+
+#endif /* LANGUAGE == C */
+
+#define DDAR_RW 	0x00000001	/* device data Read/Write          */
+#define DDAR_DevWr	(DDAR_RW*0)	/*  Device data Write              */
+					/*  (memory -> device)             */
+#define DDAR_DevRd	(DDAR_RW*1)	/*  Device data Read               */
+					/*  (device -> memory)             */
+#define DDAR_E  	0x00000002	/* big/little Endian device        */
+#define DDAR_LtlEnd	(DDAR_E*0)	/*  Little Endian device           */
+#define DDAR_BigEnd	(DDAR_E*1)	/*  Big Endian device              */
+#define DDAR_BS 	0x00000004	/* device Burst Size               */
+#define DDAR_Brst4	(DDAR_BS*0)	/*  Burst-of-4 device              */
+#define DDAR_Brst8	(DDAR_BS*1)	/*  Burst-of-8 device              */
+#define DDAR_DW 	0x00000008	/* device Data Width               */
+#define DDAR_8BitDev	(DDAR_DW*0)	/*  8-Bit Device                   */
+#define DDAR_16BitDev	(DDAR_DW*1)	/*  16-Bit Device                  */
+#define DDAR_DS 	Fld (4, 4)	/* Device Select                   */
+#define DDAR_Ser0UDCTr	        	/*  Ser. port 0 UDC Transmit       */ \
+			(0x0 << FShft (DDAR_DS))
+#define DDAR_Ser0UDCRc	        	/*  Ser. port 0 UDC Receive        */ \
+			(0x1 << FShft (DDAR_DS))
+#define DDAR_Ser1SDLCTr	        	/*  Ser. port 1 SDLC Transmit      */ \
+			(0x2 << FShft (DDAR_DS))
+#define DDAR_Ser1SDLCRc	        	/*  Ser. port 1 SDLC Receive       */ \
+			(0x3 << FShft (DDAR_DS))
+#define DDAR_Ser1UARTTr	        	/*  Ser. port 1 UART Transmit      */ \
+			(0x4 << FShft (DDAR_DS))
+#define DDAR_Ser1UARTRc	        	/*  Ser. port 1 UART Receive       */ \
+			(0x5 << FShft (DDAR_DS))
+#define DDAR_Ser2ICPTr	        	/*  Ser. port 2 ICP Transmit       */ \
+			(0x6 << FShft (DDAR_DS))
+#define DDAR_Ser2ICPRc	        	/*  Ser. port 2 ICP Receive        */ \
+			(0x7 << FShft (DDAR_DS))
+#define DDAR_Ser3UARTTr	        	/*  Ser. port 3 UART Transmit      */ \
+			(0x8 << FShft (DDAR_DS))
+#define DDAR_Ser3UARTRc	        	/*  Ser. port 3 UART Receive       */ \
+			(0x9 << FShft (DDAR_DS))
+#define DDAR_Ser4MCP0Tr	        	/*  Ser. port 4 MCP 0 Transmit     */ \
+					/*  (audio)                        */ \
+			(0xA << FShft (DDAR_DS))
+#define DDAR_Ser4MCP0Rc	        	/*  Ser. port 4 MCP 0 Receive      */ \
+					/*  (audio)                        */ \
+			(0xB << FShft (DDAR_DS))
+#define DDAR_Ser4MCP1Tr	        	/*  Ser. port 4 MCP 1 Transmit     */ \
+					/*  (telecom)                      */ \
+			(0xC << FShft (DDAR_DS))
+#define DDAR_Ser4MCP1Rc	        	/*  Ser. port 4 MCP 1 Receive      */ \
+					/*  (telecom)                      */ \
+			(0xD << FShft (DDAR_DS))
+#define DDAR_Ser4SSPTr	        	/*  Ser. port 4 SSP Transmit       */ \
+			(0xE << FShft (DDAR_DS))
+#define DDAR_Ser4SSPRc	        	/*  Ser. port 4 SSP Receive        */ \
+			(0xF << FShft (DDAR_DS))
+#define DDAR_DA 	Fld (24, 8)	/* Device Address                  */
+#define DDAR_DevAdd(Add)        	/*  Device Address                 */ \
+			(((Add) & 0xF0000000) | \
+			 (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
+#define DDAR_Ser0UDCWr	        	/* Ser. port 0 UDC Write           */ \
+			(DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
+			 DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR))
+#define DDAR_Ser0UDCRd	        	/* Ser. port 0 UDC Read            */ \
+			(DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
+			 DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR))
+#define DDAR_Ser1UARTWr	        	/* Ser. port 1 UART Write          */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR))
+#define DDAR_Ser1UARTRd	        	/* Ser. port 1 UART Read           */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR))
+#define DDAR_Ser1SDLCWr	        	/* Ser. port 1 SDLC Write          */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR))
+#define DDAR_Ser1SDLCRd	        	/* Ser. port 1 SDLC Read           */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR))
+#define DDAR_Ser2UARTWr	        	/* Ser. port 2 UART Write          */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR))
+#define DDAR_Ser2UARTRd	        	/* Ser. port 2 UART Read           */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR))
+#define DDAR_Ser2HSSPWr	        	/* Ser. port 2 HSSP Write          */ \
+			(DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
+			 DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR))
+#define DDAR_Ser2HSSPRd	        	/* Ser. port 2 HSSP Read           */ \
+			(DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
+			 DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR))
+#define DDAR_Ser3UARTWr	        	/* Ser. port 3 UART Write          */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR))
+#define DDAR_Ser3UARTRd	        	/* Ser. port 3 UART Read           */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR))
+#define DDAR_Ser4MCP0Wr	        	/* Ser. port 4 MCP 0 Write (audio) */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0))
+#define DDAR_Ser4MCP0Rd	        	/* Ser. port 4 MCP 0 Read (audio)  */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0))
+#define DDAR_Ser4MCP1Wr	        	/* Ser. port 4 MCP 1 Write         */ \
+					/* (telecom)                       */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1))
+#define DDAR_Ser4MCP1Rd	        	/* Ser. port 4 MCP 1 Read          */ \
+					/* (telecom)                       */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1))
+#define DDAR_Ser4SSPWr	        	/* Ser. port 4 SSP Write (16 bits) */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR))
+#define DDAR_Ser4SSPRd	        	/* Ser. port 4 SSP Read (16 bits)  */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR))
+
+#define DCSR_RUN	0x00000001	/* DMA RUNing                      */
+#define DCSR_IE 	0x00000002	/* DMA Interrupt Enable            */
+#define DCSR_ERROR	0x00000004	/* DMA ERROR                       */
+#define DCSR_DONEA	0x00000008	/* DONE DMA transfer buffer A      */
+#define DCSR_STRTA	0x00000010	/* STaRTed DMA transfer buffer A   */
+#define DCSR_DONEB	0x00000020	/* DONE DMA transfer buffer B      */
+#define DCSR_STRTB	0x00000040	/* STaRTed DMA transfer buffer B   */
+#define DCSR_BIU	0x00000080	/* DMA Buffer In Use               */
+#define DCSR_BufA	(DCSR_BIU*0)	/*  DMA Buffer A in use            */
+#define DCSR_BufB	(DCSR_BIU*1)	/*  DMA Buffer B in use            */
+
+#define DBT_TC  	Fld (13, 0)	/* Transfer Count                  */
+#define DBTA_TCA	DBT_TC  	/* Transfer Count buffer A         */
+#define DBTB_TCB	DBT_TC  	/* Transfer Count buffer B         */
+
+
+/*
+ * Liquid Crystal Display (LCD) control registers
+ *
+ * Registers
+ *    LCCR0     	Liquid Crystal Display (LCD) Control Register 0
+ *              	(read/write).
+ *              	[Bits LDM, BAM, and ERM are only implemented in
+ *              	versions 2.0 (rev. = 8) and higher of the StrongARM
+ *              	SA-1100.]
+ *    LCSR      	Liquid Crystal Display (LCD) Status Register
+ *              	(read/write).
+ *              	[Bit LDD can be only read in versions 1.0 (rev. = 1)
+ *              	and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
+ *              	read and written (cleared) in versions 2.0 (rev. = 8)
+ *              	and higher.]
+ *    DBAR1     	Liquid Crystal Display (LCD) Direct Memory Access
+ *              	(DMA) Base Address Register channel 1 (read/write).
+ *    DCAR1     	Liquid Crystal Display (LCD) Direct Memory Access
+ *              	(DMA) Current Address Register channel 1 (read).
+ *    DBAR2     	Liquid Crystal Display (LCD) Direct Memory Access
+ *              	(DMA) Base Address Register channel 2 (read/write).
+ *    DCAR2     	Liquid Crystal Display (LCD) Direct Memory Access
+ *              	(DMA) Current Address Register channel 2 (read).
+ *    LCCR1     	Liquid Crystal Display (LCD) Control Register 1
+ *              	(read/write).
+ *              	[The LCCR1 register can be only written in
+ *              	versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *              	StrongARM SA-1100, it can be written and read in
+ *              	versions 2.0 (rev. = 8) and higher.]
+ *    LCCR2     	Liquid Crystal Display (LCD) Control Register 2
+ *              	(read/write).
+ *              	[The LCCR1 register can be only written in
+ *              	versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *              	StrongARM SA-1100, it can be written and read in
+ *              	versions 2.0 (rev. = 8) and higher.]
+ *    LCCR3     	Liquid Crystal Display (LCD) Control Register 3
+ *              	(read/write).
+ *              	[The LCCR1 register can be only written in
+ *              	versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *              	StrongARM SA-1100, it can be written and read in
+ *              	versions 2.0 (rev. = 8) and higher. Bit PCP is only
+ *              	implemented in versions 2.0 (rev. = 8) and higher of
+ *              	the StrongARM SA-1100.]
+ *
+ * Clocks
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem	Frequency, period of the memory clock (fmem = fcpu/2).
+ *    fpix, Tpix	Frequency, period of the pixel clock.
+ *    fln, Tln  	Frequency, period of the line clock.
+ *    fac, Tac  	Frequency, period of the AC bias clock.
+ */
+
+#define LCD_PEntrySp	2       	/* LCD Palette Entry Space [byte]  */
+#define LCD_4BitPSp	        	/* LCD 4-Bit pixel Palette Space   */ \
+					/* [byte]                          */ \
+			(16*LCD_PEntrySp)
+#define LCD_8BitPSp	        	/* LCD 8-Bit pixel Palette Space   */ \
+					/* [byte]                          */ \
+			(256*LCD_PEntrySp)
+#define LCD_12_16BitPSp	        	/* LCD 12/16-Bit pixel             */ \
+					/* dummy-Palette Space [byte]      */ \
+			(16*LCD_PEntrySp)
+
+#define LCD_PGrey	Fld (4, 0)	/* LCD Palette entry Grey value    */
+#define LCD_PBlue	Fld (4, 0)	/* LCD Palette entry Blue value    */
+#define LCD_PGreen	Fld (4, 4)	/* LCD Palette entry Green value   */
+#define LCD_PRed	Fld (4, 8)	/* LCD Palette entry Red value     */
+#define LCD_PBS 	Fld (2, 12)	/* LCD Pixel Bit Size              */
+#define LCD_4Bit	        	/*  LCD 4-Bit pixel mode           */ \
+			(0 << FShft (LCD_PBS))
+#define LCD_8Bit	        	/*  LCD 8-Bit pixel mode           */ \
+			(1 << FShft (LCD_PBS))
+#define LCD_12_16Bit	        	/*  LCD 12/16-Bit pixel mode       */ \
+			(2 << FShft (LCD_PBS))
+
+#define LCD_Int0_0	0x0     	/* LCD Intensity =   0.0% =  0     */
+#define LCD_Int11_1	0x1     	/* LCD Intensity =  11.1% =  1/9   */
+#define LCD_Int20_0	0x2     	/* LCD Intensity =  20.0% =  1/5   */
+#define LCD_Int26_7	0x3     	/* LCD Intensity =  26.7% =  4/15  */
+#define LCD_Int33_3	0x4     	/* LCD Intensity =  33.3% =  3/9   */
+#define LCD_Int40_0	0x5     	/* LCD Intensity =  40.0% =  2/5   */
+#define LCD_Int44_4	0x6     	/* LCD Intensity =  44.4% =  4/9   */
+#define LCD_Int50_0	0x7     	/* LCD Intensity =  50.0% =  1/2   */
+#define LCD_Int55_6	0x8     	/* LCD Intensity =  55.6% =  5/9   */
+#define LCD_Int60_0	0x9     	/* LCD Intensity =  60.0% =  3/5   */
+#define LCD_Int66_7	0xA     	/* LCD Intensity =  66.7% =  6/9   */
+#define LCD_Int73_3	0xB     	/* LCD Intensity =  73.3% = 11/15  */
+#define LCD_Int80_0	0xC     	/* LCD Intensity =  80.0% =  4/5   */
+#define LCD_Int88_9	0xD     	/* LCD Intensity =  88.9% =  8/9   */
+#define LCD_Int100_0	0xE     	/* LCD Intensity = 100.0% =  1     */
+#define LCD_Int100_0A	0xF     	/* LCD Intensity = 100.0% =  1     */
+					/* (Alternative)                   */
+
+#define _LCCR0  	0xB0100000	/* LCD Control Reg. 0              */
+#define _LCSR   	0xB0100004	/* LCD Status Reg.                 */
+#define _DBAR1  	0xB0100010	/* LCD DMA Base Address Reg.       */
+					/* channel 1                       */
+#define _DCAR1  	0xB0100014	/* LCD DMA Current Address Reg.    */
+					/* channel 1                       */
+#define _DBAR2  	0xB0100018	/* LCD DMA Base Address Reg.       */
+					/* channel 2                       */
+#define _DCAR2  	0xB010001C	/* LCD DMA Current Address Reg.    */
+					/* channel 2                       */
+#define _LCCR1  	0xB0100020	/* LCD Control Reg. 1              */
+#define _LCCR2  	0xB0100024	/* LCD Control Reg. 2              */
+#define _LCCR3  	0xB0100028	/* LCD Control Reg. 3              */
+
+#if LANGUAGE == C
+#define LCCR0   	        	/* LCD Control Reg. 0              */ \
+			(*((volatile Word *) io_p2v (_LCCR0)))
+#define LCSR    	        	/* LCD Status Reg.                 */ \
+			(*((volatile Word *) io_p2v (_LCSR)))
+#define DBAR1   	        	/* LCD DMA Base Address Reg.       */ \
+					/* channel 1                       */ \
+			(*((volatile Address *) io_p2v (_DBAR1)))
+#define DCAR1   	        	/* LCD DMA Current Address Reg.    */ \
+					/* channel 1                       */ \
+			(*((volatile Address *) io_p2v (_DCAR1)))
+#define DBAR2   	        	/* LCD DMA Base Address Reg.       */ \
+					/* channel 2                       */ \
+			(*((volatile Address *) io_p2v (_DBAR2)))
+#define DCAR2   	        	/* LCD DMA Current Address Reg.    */ \
+					/* channel 2                       */ \
+			(*((volatile Address *) io_p2v (_DCAR2)))
+#define LCCR1   	        	/* LCD Control Reg. 1              */ \
+			(*((volatile Word *) io_p2v (_LCCR1)))
+#define LCCR2   	        	/* LCD Control Reg. 2              */ \
+			(*((volatile Word *) io_p2v (_LCCR2)))
+#define LCCR3   	        	/* LCD Control Reg. 3              */ \
+			(*((volatile Word *) io_p2v (_LCCR3)))
+#endif /* LANGUAGE == C */
+
+#define LCCR0_LEN	0x00000001	/* LCD ENable                      */
+#define LCCR0_CMS	0x00000002	/* Color/Monochrome display Select */
+#define LCCR0_Color	(LCCR0_CMS*0)	/*  Color display                  */
+#define LCCR0_Mono	(LCCR0_CMS*1)	/*  Monochrome display             */
+#define LCCR0_SDS	0x00000004	/* Single/Dual panel display       */
+					/* Select                          */
+#define LCCR0_Sngl	(LCCR0_SDS*0)	/*  Single panel display           */
+#define LCCR0_Dual	(LCCR0_SDS*1)	/*  Dual panel display             */
+#define LCCR0_LDM	0x00000008	/* LCD Disable done (LDD)          */
+					/* interrupt Mask (disable)        */
+#define LCCR0_BAM	0x00000010	/* Base Address update (BAU)       */
+					/* interrupt Mask (disable)        */
+#define LCCR0_ERM	0x00000020	/* LCD ERror (BER, IOL, IUL, IOU,  */
+					/* IUU, OOL, OUL, OOU, and OUU)    */
+					/* interrupt Mask (disable)        */
+#define LCCR0_PAS	0x00000080	/* Passive/Active display Select   */
+#define LCCR0_Pas	(LCCR0_PAS*0)	/*  Passive display (STN)          */
+#define LCCR0_Act	(LCCR0_PAS*1)	/*  Active display (TFT)           */
+#define LCCR0_BLE	0x00000100	/* Big/Little Endian select        */
+#define LCCR0_LtlEnd	(LCCR0_BLE*0)	/*  Little Endian frame buffer     */
+#define LCCR0_BigEnd	(LCCR0_BLE*1)	/*  Big Endian frame buffer        */
+#define LCCR0_DPD	0x00000200	/* Double Pixel Data (monochrome   */
+					/* display mode)                   */
+#define LCCR0_4PixMono	(LCCR0_DPD*0)	/*  4-Pixel/clock Monochrome       */
+					/*  display                        */
+#define LCCR0_8PixMono	(LCCR0_DPD*1)	/*  8-Pixel/clock Monochrome       */
+					/*  display                        */
+#define LCCR0_PDD	Fld (8, 12)	/* Palette DMA request Delay       */
+					/* [Tmem]                          */
+#define LCCR0_DMADel(Tcpu)      	/*  palette DMA request Delay      */ \
+					/*  [0..510 Tcpu]                  */ \
+			((Tcpu)/2 << FShft (LCCR0_PDD))
+
+#define LCSR_LDD	0x00000001	/* LCD Disable Done                */
+#define LCSR_BAU	0x00000002	/* Base Address Update (read)      */
+#define LCSR_BER	0x00000004	/* Bus ERror                       */
+#define LCSR_ABC	0x00000008	/* AC Bias clock Count             */
+#define LCSR_IOL	0x00000010	/* Input FIFO Over-run Lower       */
+					/* panel                           */
+#define LCSR_IUL	0x00000020	/* Input FIFO Under-run Lower      */
+					/* panel                           */
+#define LCSR_IOU	0x00000040	/* Input FIFO Over-run Upper       */
+					/* panel                           */
+#define LCSR_IUU	0x00000080	/* Input FIFO Under-run Upper      */
+					/* panel                           */
+#define LCSR_OOL	0x00000100	/* Output FIFO Over-run Lower      */
+					/* panel                           */
+#define LCSR_OUL	0x00000200	/* Output FIFO Under-run Lower     */
+					/* panel                           */
+#define LCSR_OOU	0x00000400	/* Output FIFO Over-run Upper      */
+					/* panel                           */
+#define LCSR_OUU	0x00000800	/* Output FIFO Under-run Upper     */
+					/* panel                           */
+
+#define LCCR1_PPL	Fld (6, 4)	/* Pixels Per Line/16 - 1          */
+#define LCCR1_DisWdth(Pixel)    	/*  Display Width [16..1024 pix.]  */ \
+			(((Pixel) - 16)/16 << FShft (LCCR1_PPL))
+#define LCCR1_HSW	Fld (6, 10)	/* Horizontal Synchronization      */
+					/* pulse Width - 2 [Tpix] (L_LCLK) */
+#define LCCR1_HorSnchWdth(Tpix) 	/*  Horizontal Synchronization     */ \
+					/*  pulse Width [2..65 Tpix]       */ \
+			(((Tpix) - 2) << FShft (LCCR1_HSW))
+#define LCCR1_ELW	Fld (8, 16)	/* End-of-Line pixel clock Wait    */
+					/* count - 1 [Tpix]                */
+#define LCCR1_EndLnDel(Tpix)    	/*  End-of-Line Delay              */ \
+					/*  [1..256 Tpix]                  */ \
+			(((Tpix) - 1) << FShft (LCCR1_ELW))
+#define LCCR1_BLW	Fld (8, 24)	/* Beginning-of-Line pixel clock   */
+					/* Wait count - 1 [Tpix]           */
+#define LCCR1_BegLnDel(Tpix)    	/*  Beginning-of-Line Delay        */ \
+					/*  [1..256 Tpix]                  */ \
+			(((Tpix) - 1) << FShft (LCCR1_BLW))
+
+#define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1              */
+#define LCCR2_DisHght(Line)     	/*  Display Height [1..1024 lines] */ \
+			(((Line) - 1) << FShft (LCCR2_LPP))
+#define LCCR2_VSW	Fld (6, 10)	/* Vertical Synchronization pulse  */
+					/* Width - 1 [Tln] (L_FCLK)        */
+#define LCCR2_VrtSnchWdth(Tln)  	/*  Vertical Synchronization pulse */ \
+					/*  Width [1..64 Tln]              */ \
+			(((Tln) - 1) << FShft (LCCR2_VSW))
+#define LCCR2_EFW	Fld (8, 16)	/* End-of-Frame line clock Wait    */
+					/* count [Tln]                     */
+#define LCCR2_EndFrmDel(Tln)    	/*  End-of-Frame Delay             */ \
+					/*  [0..255 Tln]                   */ \
+			((Tln) << FShft (LCCR2_EFW))
+#define LCCR2_BFW	Fld (8, 24)	/* Beginning-of-Frame line clock   */
+					/* Wait count [Tln]                */
+#define LCCR2_BegFrmDel(Tln)    	/*  Beginning-of-Frame Delay       */ \
+					/*  [0..255 Tln]                   */ \
+			((Tln) << FShft (LCCR2_BFW))
+
+#define LCCR3_PCD	Fld (8, 0)	/* Pixel Clock Divisor/2 - 2       */
+					/* [1..255] (L_PCLK)               */
+					/* fpix = fcpu/(2*(PCD + 2))       */
+					/* Tpix = 2*(PCD + 2)*Tcpu         */
+#define LCCR3_PixClkDiv(Div)    	/*  Pixel Clock Divisor [6..514]   */ \
+			(((Div) - 4)/2 << FShft (LCCR3_PCD))
+					/*  fpix = fcpu/(2*Floor (Div/2))  */
+					/*  Tpix = 2*Floor (Div/2)*Tcpu    */
+#define LCCR3_CeilPixClkDiv(Div)	/*  Ceil. of PixClkDiv [6..514]    */ \
+			(((Div) - 3)/2 << FShft (LCCR3_PCD))
+					/*  fpix = fcpu/(2*Ceil (Div/2))   */
+					/*  Tpix = 2*Ceil (Div/2)*Tcpu     */
+#define LCCR3_ACB	Fld (8, 8)	/* AC Bias clock half period - 1   */
+					/* [Tln] (L_BIAS)                  */
+#define LCCR3_ACBsDiv(Div)      	/*  AC Bias clock Divisor [2..512] */ \
+			(((Div) - 2)/2 << FShft (LCCR3_ACB))
+					/*  fac = fln/(2*Floor (Div/2))    */
+					/*  Tac = 2*Floor (Div/2)*Tln      */
+#define LCCR3_CeilACBsDiv(Div)  	/*  Ceil. of ACBsDiv [2..512]      */ \
+			(((Div) - 1)/2 << FShft (LCCR3_ACB))
+					/*  fac = fln/(2*Ceil (Div/2))     */
+					/*  Tac = 2*Ceil (Div/2)*Tln       */
+#define LCCR3_API	Fld (4, 16)	/* AC bias Pin transitions per     */
+					/* Interrupt                       */
+#define LCCR3_ACBsCntOff        	/*  AC Bias clock transition Count */ \
+					/*  Off                            */ \
+			(0 << FShft (LCCR3_API))
+#define LCCR3_ACBsCnt(Trans)    	/*  AC Bias clock transition Count */ \
+					/*  [1..15]                        */ \
+			((Trans) << FShft (LCCR3_API))
+#define LCCR3_VSP	0x00100000	/* Vertical Synchronization pulse  */
+					/* Polarity (L_FCLK)               */
+#define LCCR3_VrtSnchH	(LCCR3_VSP*0)	/*  Vertical Synchronization pulse */
+					/*  active High                    */
+#define LCCR3_VrtSnchL	(LCCR3_VSP*1)	/*  Vertical Synchronization pulse */
+					/*  active Low                     */
+#define LCCR3_HSP	0x00200000	/* Horizontal Synchronization      */
+					/* pulse Polarity (L_LCLK)         */
+#define LCCR3_HorSnchH	(LCCR3_HSP*0)	/*  Horizontal Synchronization     */
+					/*  pulse active High              */
+#define LCCR3_HorSnchL	(LCCR3_HSP*1)	/*  Horizontal Synchronization     */
+					/*  pulse active Low               */
+#define LCCR3_PCP	0x00400000	/* Pixel Clock Polarity (L_PCLK)   */
+#define LCCR3_PixRsEdg	(LCCR3_PCP*0)	/*  Pixel clock Rising-Edge        */
+#define LCCR3_PixFlEdg	(LCCR3_PCP*1)	/*  Pixel clock Falling-Edge       */
+#define LCCR3_OEP	0x00800000	/* Output Enable Polarity (L_BIAS, */
+					/* active display mode)            */
+#define LCCR3_OutEnH	(LCCR3_OEP*0)	/*  Output Enable active High      */
+#define LCCR3_OutEnL	(LCCR3_OEP*1)	/*  Output Enable active Low       */
+
+
+#undef C
+#undef Assembly
diff --git a/include/_exports.h b/include/_exports.h
new file mode 100755
index 0000000..61dcaaf
--- /dev/null
+++ b/include/_exports.h
@@ -0,0 +1,18 @@
+EXPORT_FUNC(get_version)
+EXPORT_FUNC(getc)
+EXPORT_FUNC(tstc)
+EXPORT_FUNC(putc)
+EXPORT_FUNC(puts)
+EXPORT_FUNC(printf)
+EXPORT_FUNC(install_hdlr)
+EXPORT_FUNC(free_hdlr)
+EXPORT_FUNC(malloc)
+EXPORT_FUNC(free)
+EXPORT_FUNC(udelay)
+EXPORT_FUNC(get_timer)
+EXPORT_FUNC(vprintf)
+EXPORT_FUNC(do_reset)
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+EXPORT_FUNC(i2c_write)
+EXPORT_FUNC(i2c_read)
+#endif	/* CFG_CMD_I2C */
diff --git a/include/altera.h b/include/altera.h
new file mode 100755
index 0000000..74b6729
--- /dev/null
+++ b/include/altera.h
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <fpga.h>
+
+#ifndef _ALTERA_H_
+#define _ALTERA_H_
+
+/*
+ * See include/xilinx.h for another working example.
+ */
+
+/* Altera Model definitions
+ *********************************************************************/
+#define CFG_ACEX1K		CFG_FPGA_DEV( 0x1 )
+
+#define CFG_ALTERA_ACEX1K	(CFG_FPGA_ALTERA | CFG_ACEX1K)
+/* Add new models here */
+
+/* Altera Interface definitions
+ *********************************************************************/
+#define CFG_ALTERA_IF_PS	CFG_FPGA_IF( 0x1 )	/* passive serial */
+/* Add new interfaces here */
+
+typedef enum {				/* typedef Altera_iface */
+	min_altera_iface_type,		/* insert all new types after this */
+	passive_serial,			/* serial data and external clock */
+	passive_parallel_synchronous,	/* parallel data */
+	passive_parallel_asynchronous,	/* parallel data */
+	passive_serial_asynchronous,	/* serial data w/ internal clock (not used)	*/
+	altera_jtag_mode,		/* jtag/tap serial (not used ) */
+	max_altera_iface_type		/* insert all new types before this */
+} Altera_iface;				/* end, typedef Altera_iface */
+
+typedef enum {			/* typedef Altera_Family */
+    min_altera_type,		/* insert all new types after this */
+    Altera_ACEX1K,		/* ACEX1K Family */
+/* Add new models here */
+    max_altera_type		/* insert all new types before this */
+} Altera_Family;		/* end, typedef Altera_Family */
+
+typedef struct {		/* typedef Altera_desc */
+	Altera_Family	family;	/* part type */
+	Altera_iface	iface;	/* interface type */
+	size_t		size;	/* bytes of data part can accept */
+	void *		iface_fns;/* interface function table */
+	void *		base;	/* base interface address */
+	int		cookie;	/* implementation specific cookie */
+} Altera_desc;			/* end, typedef Altera_desc */
+
+/* Generic Altera Functions
+ *********************************************************************/
+extern int altera_load( Altera_desc *desc, void *image, size_t size );
+extern int altera_dump( Altera_desc *desc, void *buf, size_t bsize );
+extern int altera_info( Altera_desc *desc );
+extern int altera_reloc( Altera_desc *desc, ulong reloc_offset );
+
+/* Board specific implementation specific function types
+ *********************************************************************/
+typedef int (*Altera_pre_fn)( int cookie );
+typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie );
+typedef int (*Altera_status_fn)( int cookie );
+typedef int (*Altera_done_fn)( int cookie );
+typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
+typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
+typedef int (*Altera_abort_fn)( int cookie );
+typedef int (*Altera_post_fn)( int cookie );
+
+#endif /* _ALTERA_H_ */
diff --git a/include/api_loader.h b/include/api_loader.h
new file mode 100755
index 0000000..44796b6
--- /dev/null
+++ b/include/api_loader.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+/*
+ * Definitions for Configuring the monitor commands
+ */
+#ifndef _API_LOADER_H
+#define _API_LOADER_H
+
+int dvo_pll_set (unsigned int multi, unsigned char divisor, unsigned short resx, unsigned short resy);
+
+
+#endif	/* _API_LOADER_H */
diff --git a/include/arm920t.h b/include/arm920t.h
new file mode 100755
index 0000000..95f3323
--- /dev/null
+++ b/include/arm920t.h
@@ -0,0 +1,12 @@
+/************************************************
+ * NAME	    : arm920t.h
+ * Version  : 30 April 2002			*
+ *
+ * empty for now
+ ************************************************/
+
+#ifndef __ARM920T_H__
+#define __ARM920T_H__
+
+
+#endif /*__ARM920T_H__*/
diff --git a/include/arm925t.h b/include/arm925t.h
new file mode 100755
index 0000000..ab343ea
--- /dev/null
+++ b/include/arm925t.h
@@ -0,0 +1,15 @@
+/************************************************
+ * NAME	    : arm925t.h
+ * Version  : 23 June 2003			*
+ ************************************************/
+
+#ifndef __ARM925T_H__
+#define __ARM925T_H__
+
+void gpioreserve(ushort mask);
+void gpiosetdir(ushort mask, ushort in);
+void gpiosetout(ushort mask, ushort out);
+void gpioinit(void);
+void archflashwp(void *archdata, int wp);
+
+#endif /*__ARM925T_H__*/
diff --git a/include/arm926ejs.h b/include/arm926ejs.h
new file mode 100755
index 0000000..c660265
--- /dev/null
+++ b/include/arm926ejs.h
@@ -0,0 +1,8 @@
+/************************************************
+ * NAME                 arm926ejs.h             *
+ * Version      :       23 June 2003            *
+ ************************************************/
+/* Currently empty */
+#ifndef __ARM926EJS_H__
+#define __ARM926EJS_H__
+#endif /*__ARM926EJS_H__*/
diff --git a/include/arm946es.h b/include/arm946es.h
new file mode 100755
index 0000000..c23f3e7
--- /dev/null
+++ b/include/arm946es.h
@@ -0,0 +1,8 @@
+/************************************************
+ * NAME                 arm946es.h              *
+ * $Version$                                    *
+ ************************************************/
+/* Currently empty */
+#ifndef __ARM946ES_H__
+#define __ARM946ES_H__
+#endif /*__ARM946ES_H__*/
diff --git a/include/armcoremodule.h b/include/armcoremodule.h
new file mode 100755
index 0000000..7dac6f8
--- /dev/null
+++ b/include/armcoremodule.h
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2005
+ * ARM Ltd.
+ * Peter Pearse, <Peter.Pearse@arm.com>
+ * Configuration for ARM Core Modules.
+ * No standalonw port yet available
+ * - this file is included by both integratorap.h & integratorcp.h
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARMCOREMODULE_H
+#define __ARMCOREMODULE_H
+
+#define CM_BASE		0x10000000
+
+/* CM registers common to all CMs */
+/* Note that observed values after reboot into the ARM Boot Monitor
+   have been used as defaults, rather than the POR values */
+#define OS_CTRL     		0x0000000C
+#define CMMASK_REMAP		0x00000005	/* set remap & led           */
+#define CMMASK_RESET		0x00000008
+#define OS_LOCK             	0x00000014
+#define CMVAL_LOCK1	     	0x0000A000	/* locking value             */
+#define CMVAL_LOCK2		0x0000005F	/* locking value             */
+#define CMVAL_UNLOCK		0x00000000	/* any value != CM_LOCKVAL   */
+#define OS_SDRAM		0x00000020
+#define OS_INIT     		0x00000024
+#define CMMASK_MAP_SIMPLE	0xFFFDFFFF	/* simple mapping */
+#define CMMASK_TCRAM_DISABLE	0xFFFEFFFF	/* TCRAM disabled */
+#define CMMASK_LOWVEC		0x00000000	/* vectors @ 0x00000000 */
+#define CMMASK_LE		0xFFFFFFF7	/* little endian */
+#define CMMASK_CMxx6_COMMON	0x00000013      /* Common value for CMxx6 */
+						/* - observed reset value of */
+						/*   CM926EJ-S */
+						/*   CM1136-EJ-S */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+#define CMMASK_INIT_102	0x00000300		/* see CM102xx ref manual */
+						/* - PLL test clock bypassed */
+						/* - bus clock ratio 2 */
+						/* - little endian */
+						/* - vectors at zero */
+#endif /* CM1022xx */
+
+/* Determine CM characteristics */
+
+#undef	CONFIG_CM_MULTIPLE_SSRAM
+#undef	CONFIG_CM_SPD_DETECT
+#undef	CONFIG_CM_REMAP
+#undef	CONFIG_CM_INIT
+#undef	CONFIG_CM_TCRAM
+
+#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
+#define	CONFIG_CM_MULTIPLE_SSRAM	/* CM has multiple SSRAM mapping */
+#endif
+
+/* Excalibur core module has reduced functionality */
+#ifndef	CONFIG_CM922T_XA10
+#define CONFIG_CM_SPD_DETECT			/* CM supports SPD query      */
+#define OS_SPD			0x00000100	/* Address of SPD data        */
+#define CONFIG_CM_REMAP				/* CM supports remapping      */
+#define CONFIG_CM_INIT				/* CM has initialization reg  */
+#endif	/* NOT EXCALIBUR */
+
+#if defined(CONFIG_CM926EJ_S)   || defined (CONFIG_CM946E_S)	|| \
+    defined(CONFIG_CM966E_S)    || defined (CONFIG_CM1026EJ_S)	|| \
+    defined(CONFIG_CM1136JF_S)
+#define CONFIG_CM_TCRAM				/* CM has TCRAM  */
+#endif
+
+#ifdef CONFIG_CM_SPD_DETECT
+#define OS_SPD		0x00000100	/* The SDRAM SPD data is copied here */
+#endif
+
+#endif /* __ARMCOREMODULE_H */
diff --git a/include/asm-arm/arch-arm1136/bits.h b/include/asm-arm/arch-arm1136/bits.h
new file mode 100755
index 0000000..8522335
--- /dev/null
+++ b/include/asm-arm/arch-arm1136/bits.h
@@ -0,0 +1,48 @@
+/* bits.h
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * This package is free software;  you can redistribute it and/or
+ * modify it under the terms of the license found in the file
+ * named COPYING that should have accompanied this file.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#ifndef __bits_h
+#define __bits_h 1
+
+#define BIT0  (1<<0)
+#define BIT1  (1<<1)
+#define BIT2  (1<<2)
+#define BIT3  (1<<3)
+#define BIT4  (1<<4)
+#define BIT5  (1<<5)
+#define BIT6  (1<<6)
+#define BIT7  (1<<7)
+#define BIT8  (1<<8)
+#define BIT9  (1<<9)
+#define BIT10 (1<<10)
+#define BIT11 (1<<11)
+#define BIT12 (1<<12)
+#define BIT13 (1<<13)
+#define BIT14 (1<<14)
+#define BIT15 (1<<15)
+#define BIT16 (1<<16)
+#define BIT17 (1<<17)
+#define BIT18 (1<<18)
+#define BIT19 (1<<19)
+#define BIT20 (1<<20)
+#define BIT21 (1<<21)
+#define BIT22 (1<<22)
+#define BIT23 (1<<23)
+#define BIT24 (1<<24)
+#define BIT25 (1<<25)
+#define BIT26 (1<<26)
+#define BIT27 (1<<27)
+#define BIT28 (1<<28)
+#define BIT29 (1<<29)
+#define BIT30 (1<<30)
+#define BIT31 (1<<31)
+
+#endif
diff --git a/include/asm-arm/arch-arm1136/clocks.h b/include/asm-arm/arch-arm1136/clocks.h
new file mode 100755
index 0000000..2a95af1
--- /dev/null
+++ b/include/asm-arm/arch-arm1136/clocks.h
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+  */
+#ifndef _OMAP24XX_CLOCKS_H_
+#define _OMAP24XX_CLOCKS_H_
+
+#define COMMIT_DIVIDERS  0x1
+
+#define MODE_BYPASS_FAST 0x2
+#define APLL_LOCK        0xc
+#ifdef CONFIG_APTIX
+#define DPLL_LOCK        0x1   /* stay in bypass mode */
+#else
+#define DPLL_LOCK        0x3   /* DPLL lock */
+#endif
+
+/****************************************************************************;
+; PRCM Scheme II
+;
+; Enable clocks and DPLL for:
+;  DPLL=300, 	DPLLout=600   	M=1,N=50   CM_CLKSEL1_PLL[21:8]  12/2*50
+;  Core=600  	(core domain)   DPLLx2     CM_CLKSEL2_PLL[1:0]
+;  MPUF=300   	(mpu domain)    2          CM_CLKSEL_MPU[4:0]
+;  DSPF=200    (dsp domain)    3          CM_CLKSEL_DSP[4:0]
+;  DSPI=100                    6          CM_CLKSEL_DSP[6:5]
+;  DSP_S          bypass	               CM_CLKSEL_DSP[7]
+;  IVAF=200    (dsp domain)    3          CM_CLKSEL_DSP[12:8]
+;  IVAF=100        auto
+;  IVAI            auto
+;  IVA_MPU         auto
+;  IVA_S          bypass                  CM_CLKSEL_DSP[13]
+;  GFXF=50      (gfx domain)	12         CM_CLKSEL_FGX[2:0]
+;  SSI_SSRF=200                 3         CM_CLKSEL1_CORE[24:20]
+;  SSI_SSTF=100     auto
+;  L3=100Mhz (sdram)            6         CM_CLKSEL1_CORE[4:0]
+;  L4=100Mhz                    6
+;  C_L4_USB=50                 12         CM_CLKSEL1_CORE[6:5]
+***************************************************************************/
+#define II_DPLL_OUT_X2   0x2    /* x2 core out */
+#define II_MPU_DIV       0x2    /* mpu = core/2 */
+#define II_DSP_DIV       0x343  /* dsp & iva divider */
+#define II_GFX_DIV       0x2
+#define II_BUS_DIV       0x04601026
+#define II_DPLL_300      0x01832100
+
+/****************************************************************************;
+; PRCM Scheme III
+;
+; Enable clocks and DPLL for:
+;  DPLL=266, 	DPLLout=532   	M=5+1,N=133 CM_CLKSEL1_PLL[21:8]  12/6*133=266
+;  Core=532  	(core domain)   DPLLx2      CM_CLKSEL2_PLL[1:0]
+;  MPUF=266   	(mpu domain)    /2          CM_CLKSEL_MPU[4:0]
+;  DSPF=177.3     (dsp domain)  /3          CM_CLKSEL_DSP[4:0]
+;  DSPI=88.67                   /6          CM_CLKSEL_DSP[6:5]
+;  DSP_S         ACTIVATED	            CM_CLKSEL_DSP[7]
+;  IVAF=88.67    (dsp domain)   /3          CM_CLKSEL_DSP[12:8]
+;  IVAF=88.67        auto
+;  IVAI            auto
+;  IVA_MPU         auto
+;  IVA_S         ACTIVATED                  CM_CLKSEL_DSP[13]
+;  GFXF=66.5      (gfx domain)	/8          CM_CLKSEL_FGX[2:0]:
+;  SSI_SSRF=177.3               /3          CM_CLKSEL1_CORE[24:20]
+;  SSI_SSTF=88.67     auto
+;  L3=133Mhz (sdram)            /4          CM_CLKSEL1_CORE[4:0]
+;  L4=66.5Mhz                   /8
+;  C_L4_USB=33.25               /16         CM_CLKSEL1_CORE[6:5]
+***************************************************************************/
+#define III_DPLL_OUT_X2   0x2    /* x2 core out */
+#define III_MPU_DIV       0x2    /* mpu = core/2 */
+#define III_DSP_DIV       0x23C3 /* dsp & iva divider sych enabled*/
+#define III_GFX_DIV       0x2
+#define III_BUS_DIV       0x08301044
+#define III_DPLL_266      0x01885500
+
+/* set defaults for boot up */
+#ifdef PRCM_CONFIG_II
+# define DPLL_OUT         II_DPLL_OUT_X2
+# define MPU_DIV          II_MPU_DIV
+# define DSP_DIV          II_DSP_DIV
+# define GFX_DIV          II_GFX_DIV
+# define BUS_DIV          II_BUS_DIV
+# define DPLL_VAL         II_DPLL_300
+#elif PRCM_CONFIG_III
+# define DPLL_OUT         III_DPLL_OUT_X2
+# define MPU_DIV          III_MPU_DIV
+# define DSP_DIV          III_DSP_DIV
+# define GFX_DIV          III_GFX_DIV
+# define BUS_DIV          III_BUS_DIV
+# define DPLL_VAL         III_DPLL_266
+#endif
+
+/* lock delay time out */
+#define LDELAY           12000000
+
+#endif
diff --git a/include/asm-arm/arch-arm1136/i2c.h b/include/asm-arm/arch-arm1136/i2c.h
new file mode 100755
index 0000000..7248950
--- /dev/null
+++ b/include/asm-arm/arch-arm1136/i2c.h
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP24XX_I2C_H_
+#define _OMAP24XX_I2C_H_
+
+#define I2C_BASE                0x48070000
+#define I2C_BASE2               0x48072000 /* nothing hooked up on h4 */
+
+#define I2C_REV                 (I2C_BASE + 0x00)
+#define I2C_IE                  (I2C_BASE + 0x04)
+#define I2C_STAT                (I2C_BASE + 0x08)
+#define I2C_IV                  (I2C_BASE + 0x0c)
+#define I2C_BUF                 (I2C_BASE + 0x14)
+#define I2C_CNT                 (I2C_BASE + 0x18)
+#define I2C_DATA                (I2C_BASE + 0x1c)
+#define I2C_SYSC                (I2C_BASE + 0x20)
+#define I2C_CON                 (I2C_BASE + 0x24)
+#define I2C_OA                  (I2C_BASE + 0x28)
+#define I2C_SA                  (I2C_BASE + 0x2c)
+#define I2C_PSC                 (I2C_BASE + 0x30)
+#define I2C_SCLL                (I2C_BASE + 0x34)
+#define I2C_SCLH                (I2C_BASE + 0x38)
+#define I2C_SYSTEST             (I2C_BASE + 0x3c)
+
+/* I2C masks */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+#define I2C_IE_GC_IE    (1 << 5)
+#define I2C_IE_XRDY_IE  (1 << 4)        /* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE  (1 << 3)        /* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE  (1 << 2)        /* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE  (1 << 1)        /* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE    (1 << 0)        /* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_SBD    (1 << 15)       /* Single byte data */
+#define I2C_STAT_BB     (1 << 12)       /* Bus busy */
+#define I2C_STAT_ROVR   (1 << 11)       /* Receive overrun */
+#define I2C_STAT_XUDF   (1 << 10)       /* Transmit underflow */
+#define I2C_STAT_AAS    (1 << 9)        /* Address as slave */
+#define I2C_STAT_GC     (1 << 5)
+#define I2C_STAT_XRDY   (1 << 4)        /* Transmit data ready */
+#define I2C_STAT_RRDY   (1 << 3)        /* Receive data ready */
+#define I2C_STAT_ARDY   (1 << 2)        /* Register access ready */
+#define I2C_STAT_NACK   (1 << 1)        /* No acknowledgment interrupt enable */
+#define I2C_STAT_AL     (1 << 0)        /* Arbitration lost interrupt enable */
+
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+#define I2C_INTCODE_MASK        7
+#define I2C_INTCODE_NONE        0
+#define I2C_INTCODE_AL          1       /* Arbitration lost */
+#define I2C_INTCODE_NAK         2       /* No acknowledgement/general call */
+#define I2C_INTCODE_ARDY        3       /* Register access ready */
+#define I2C_INTCODE_RRDY        4       /* Rcv data ready */
+#define I2C_INTCODE_XRDY        5       /* Xmit data ready */
+
+/* I2C Buffer Configuration Register (I2C_BUF): */
+
+#define I2C_BUF_RDMA_EN         (1 << 15)       /* Receive DMA channel enable */
+#define I2C_BUF_XDMA_EN         (1 << 7)        /* Transmit DMA channel enable */
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN      (1 << 15)       /* I2C module enable */
+#define I2C_CON_BE      (1 << 14)       /* Big endian mode */
+#define I2C_CON_STB     (1 << 11)       /* Start byte mode (master mode only) */
+#define I2C_CON_MST     (1 << 10)       /* Master/slave mode */
+#define I2C_CON_TRX     (1 << 9)        /* Transmitter/receiver mode (master mode only) */
+#define I2C_CON_XA      (1 << 8)        /* Expand address */
+#define I2C_CON_STP     (1 << 1)        /* Stop condition (master mode only) */
+#define I2C_CON_STT     (1 << 0)        /* Start condition (master mode only) */
+
+/* I2C System Test Register (I2C_SYSTEST): */
+
+#define I2C_SYSTEST_ST_EN       (1 << 15)       /* System test enable */
+#define I2C_SYSTEST_FREE        (1 << 14)       /* Free running mode (on breakpoint) */
+#define I2C_SYSTEST_TMODE_MASK  (3 << 12)       /* Test mode select */
+#define I2C_SYSTEST_TMODE_SHIFT (12)            /* Test mode select */
+#define I2C_SYSTEST_SCL_I       (1 << 3)        /* SCL line sense input value */
+#define I2C_SYSTEST_SCL_O       (1 << 2)        /* SCL line drive output value */
+#define I2C_SYSTEST_SDA_I       (1 << 1)        /* SDA line sense input value */
+#define I2C_SYSTEST_SDA_O       (1 << 0)        /* SDA line drive output value */
+
+#endif
diff --git a/include/asm-arm/arch-arm1136/mem.h b/include/asm-arm/arch-arm1136/mem.h
new file mode 100755
index 0000000..c81f1c4
--- /dev/null
+++ b/include/asm-arm/arch-arm1136/mem.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP24XX_MEM_H_
+#define _OMAP24XX_MEM_H_
+
+#define SDRC_CS0_OSET	 0x0
+#define SDRC_CS1_OSET	 0x30  /* mirror CS1 regs appear offset 0x30 from CS0 */
+
+#ifndef __ASSEMBLY__
+/* struct's for holding data tables for current boards, they are getting used
+   early in init when NO global access are there */
+struct sdrc_data_s {
+	u32    sdrc_sharing;
+	u32    sdrc_mdcfg_0_ddr;
+	u32    sdrc_mdcfg_0_sdr;
+	u32    sdrc_actim_ctrla_0;
+	u32    sdrc_actim_ctrlb_0;
+	u32    sdrc_rfr_ctrl;
+	u32    sdrc_mr_0_ddr;
+	u32    sdrc_mr_0_sdr;
+	u32    sdrc_dllab_ctrl;
+} /*__attribute__ ((packed))*/;
+typedef struct sdrc_data_s sdrc_data_t;
+
+typedef enum {
+	STACKED		= 0,
+	IP_DDR		= 1,
+	COMBO_DDR	= 2,
+	IP_SDR		= 3,
+} mem_t;
+
+#endif
+
+/* Slower full frequency range default timings for x32 operation*/
+#define H4_2420_SDRC_SHARING		0x00000100
+#define H4_2420_SDRC_MDCFG_0_SDR	0x00D04010 /* discrete sdr module */
+#define H4_2420_SDRC_MR_0_SDR		0x00000031
+#define H4_2420_SDRC_MDCFG_0_DDR	0x01702011 /* descrite ddr module */
+#define H4_2420_COMBO_MDCFG_0_DDR	0x00801011 /* combo module */
+#define H4_2420_SDRC_MR_0_DDR		0x00000032
+
+#define H4_2422_SDRC_SHARING		0x00004b00
+#define H4_2422_SDRC_MDCFG_0_DDR	0x00801011 /* stacked ddr on 2422 */
+#define H4_2422_SDRC_MR_0_DDR		0x00000032
+
+/* ES1 work around timings */
+#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1	0x9bead909  /* 165Mhz for use with 100/133 */
+#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1	0x00000020
+#define H4_242x_SDRC_RFR_CTRL_ES1	    0x00002401	/* use over refresh for ES1 */
+
+/* optimized timings good for current shipping parts */
+#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz  0x5A59B485
+#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz  0x0000000e
+#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz  0x8BA6E6C8 /* temp warn 0 settings */
+#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz  0x00000010 /* temp warn 0 settings */
+#define H4_242X_SDRC_RFR_CTRL_100MHz	   0x0002da01
+#define H4_242X_SDRC_RFR_CTRL_133MHz	   0x0003de01
+#define H4_242x_SDRC_DLLAB_CTRL_100MHz	   0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/
+#define H4_242x_SDRC_DLLAB_CTRL_133MHz	   0x0000690E /* 72deg, for ES2 */
+
+#ifdef PRCM_CONFIG_II
+# define H4_2420_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2420_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2420_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2420_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2422_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2422_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_100MHz
+#elif PRCM_CONFIG_III
+# define H4_2420_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
+# define H4_2420_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
+# define H4_2420_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_133MHz
+# define H4_2420_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_133MHz
+# define H4_2422_SDRC_ACTIM_CTRLA_0	H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLB_0	H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2422_SDRC_RFR_CTRL		H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2422_SDRC_DLLAB_CTRL    H4_242x_SDRC_DLLAB_CTRL_100MHz
+#endif
+
+
+/* GPMC settings */
+#ifdef PRCM_CONFIG_II	     /* L3 at 100MHz */
+# ifdef CFG_NAND_BOOT
+#  define H4_24XX_GPMC_CONFIG1_0   0x0
+#  define H4_24XX_GPMC_CONFIG2_0   0x00141400
+#  define H4_24XX_GPMC_CONFIG3_0   0x00141400
+#  define H4_24XX_GPMC_CONFIG4_0   0x0F010F01
+#  define H4_24XX_GPMC_CONFIG5_0   0x010C1414
+#  define H4_24XX_GPMC_CONFIG6_0   0x00000A80
+# else	/* else NOR */
+#  define H4_24XX_GPMC_CONFIG1_0   0x3
+#  define H4_24XX_GPMC_CONFIG2_0   0x000f0f01
+#  define H4_24XX_GPMC_CONFIG3_0   0x00050502
+#  define H4_24XX_GPMC_CONFIG4_0   0x0C060C06
+#  define H4_24XX_GPMC_CONFIG5_0   0x01131F1F
+# endif /* endif CFG_NAND_BOOT */
+# define H4_24XX_GPMC_CONFIG7_0	  (0x00000C40|(H4_CS0_BASE >> 24))
+# define H4_24XX_GPMC_CONFIG1_1	  0x00011000
+# define H4_24XX_GPMC_CONFIG2_1	  0x001F1F00
+# define H4_24XX_GPMC_CONFIG3_1	  0x00080802
+# define H4_24XX_GPMC_CONFIG4_1	  0x1C091C09
+# define H4_24XX_GPMC_CONFIG5_1	  0x031A1F1F
+# define H4_24XX_GPMC_CONFIG6_1	  0x000003C2
+# define H4_24XX_GPMC_CONFIG7_1	  (0x00000F40|(H4_CS1_BASE >> 24))
+#endif /* endif PRCM_CONFIG_II */
+
+#ifdef PRCM_CONFIG_III	/* L3 at 133MHz */
+# ifdef CFG_NAND_BOOT
+#  define H4_24XX_GPMC_CONFIG1_0   0x0
+#  define H4_24XX_GPMC_CONFIG2_0   0x00141400
+#  define H4_24XX_GPMC_CONFIG3_0   0x00141400
+#  define H4_24XX_GPMC_CONFIG4_0   0x0F010F01
+#  define H4_24XX_GPMC_CONFIG5_0   0x010C1414
+#  define H4_24XX_GPMC_CONFIG6_0   0x00000A80
+# else	/* NOR boot */
+#  define H4_24XX_GPMC_CONFIG1_0   0x3
+#  define H4_24XX_GPMC_CONFIG2_0   0x00151501
+#  define H4_24XX_GPMC_CONFIG3_0   0x00060602
+#  define H4_24XX_GPMC_CONFIG4_0   0x10081008
+#  define H4_24XX_GPMC_CONFIG5_0   0x01131F1F
+#  define H4_24XX_GPMC_CONFIG6_0   0x000004c4
+# endif /* endif CFG_NAND_BOOT */
+# define H4_24XX_GPMC_CONFIG7_0	  (0x00000C40|(H4_CS0_BASE >> 24))
+# define H4_24XX_GPMC_CONFIG1_1	  0x00011000
+# define H4_24XX_GPMC_CONFIG2_1	  0x001f1f01
+# define H4_24XX_GPMC_CONFIG3_1	  0x00080803
+# define H4_24XX_GPMC_CONFIG4_1	  0x1C091C09
+# define H4_24XX_GPMC_CONFIG5_1	  0x041f1F1F
+# define H4_24XX_GPMC_CONFIG6_1	  0x000004C4
+# define H4_24XX_GPMC_CONFIG7_1	  (0x00000F40|(H4_CS1_BASE >> 24))
+#endif /* endif CFG_PRCM_III */
+
+#endif /* endif _OMAP24XX_MEM_H_ */
diff --git a/include/asm-arm/arch-arm1136/mux.h b/include/asm-arm/arch-arm1136/mux.h
new file mode 100755
index 0000000..67c8419
--- /dev/null
+++ b/include/asm-arm/arch-arm1136/mux.h
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP2420_MUX_H_
+#define _OMAP2420_MUX_H_
+
+#ifndef __ASSEMBLY__
+typedef  unsigned char uint8;
+typedef  unsigned int uint32;
+
+void muxSetupSDRC(void);
+void muxSetupGPMC(void);
+void muxSetupUsb0(void);
+void muxSetupUart3(void);
+void muxSetupI2C1(void);
+void muxSetupUART1(void);
+void muxSetupLCD(void);
+void muxSetupCamera(void);
+void muxSetupMMCSD(void) ;
+void muxSetupTouchScreen(void) ;
+void muxSetupHDQ(void);
+#endif
+
+#define USB_OTG_CTRL			        ((volatile uint32 *)0x4805E30C)
+
+/* Pin Muxing registers used for HDQ (Smart battery) */
+#define CONTROL_PADCONF_HDQ_SIO         ((volatile unsigned char *)0x48000115)
+
+/* Pin Muxing registers used for GPMC */
+#define CONTROL_PADCONF_GPMC_D2_BYTE0	((volatile unsigned char *)0x48000088)
+#define CONTROL_PADCONF_GPMC_D2_BYTE1	((volatile unsigned char *)0x48000089)
+#define CONTROL_PADCONF_GPMC_D2_BYTE2	((volatile unsigned char *)0x4800008A)
+#define CONTROL_PADCONF_GPMC_D2_BYTE3	((volatile unsigned char *)0x4800008B)
+
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE0	((volatile unsigned char *)0x4800008C)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE1	((volatile unsigned char *)0x4800008D)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE2	((volatile unsigned char *)0x4800008E)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE3	((volatile unsigned char *)0x4800008F)
+
+/* Pin Muxing registers used for SDRC */
+#define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0)
+#define CONTROL_PADCONF_SDRC_NCS0_BYTE1 ((volatile unsigned char *)0x480000A1)
+#define CONTROL_PADCONF_SDRC_NCS0_BYTE2 ((volatile unsigned char *)0x480000A2)
+#define CONTROL_PADCONF_SDRC_NCS0_BYTE3 ((volatile unsigned char *)0x480000A3)
+
+#define CONTROL_PADCONF_SDRC_A14_BYTE0	((volatile unsigned char *)0x48000030)
+#define CONTROL_PADCONF_SDRC_A14_BYTE1	((volatile unsigned char *)0x48000031)
+#define CONTROL_PADCONF_SDRC_A14_BYTE2	((volatile unsigned char *)0x48000032)
+#define CONTROL_PADCONF_SDRC_A14_BYTE3	((volatile unsigned char *)0x48000033)
+
+/* Pin Muxing registers used for Touch Screen (SPI) */
+#define CONTROL_PADCONF_SPI1_CLK        ((volatile unsigned char *)0x480000FF)
+#define CONTROL_PADCONF_SPI1_SIMO       ((volatile unsigned char *)0x48000100)
+#define CONTROL_PADCONF_SPI1_SOMI       ((volatile unsigned char *)0x48000101)
+#define CONTROL_PADCONF_SPI1_NCS0       ((volatile unsigned char *)0x48000102)
+
+#define CONTROL_PADCONF_MCBSP1_FSR      ((volatile unsigned char *)0x4800010B)
+
+/* Pin Muxing registers used for MMCSD */
+#define CONTROL_PADCONF_MMC_CLKI        ((volatile unsigned char *)0x480000FE)
+#define CONTROL_PADCONF_MMC_CLKO        ((volatile unsigned char *)0x480000F3)
+#define CONTROL_PADCONF_MMC_CMD         ((volatile unsigned char *)0x480000F4)
+#define CONTROL_PADCONF_MMC_DAT0        ((volatile unsigned char *)0x480000F5)
+#define CONTROL_PADCONF_MMC_DAT1        ((volatile unsigned char *)0x480000F6)
+#define CONTROL_PADCONF_MMC_DAT2        ((volatile unsigned char *)0x480000F7)
+#define CONTROL_PADCONF_MMC_DAT3        ((volatile unsigned char *)0x480000F8)
+#define CONTROL_PADCONF_MMC_DAT_DIR0    ((volatile unsigned char *)0x480000F9)
+#define CONTROL_PADCONF_MMC_DAT_DIR1    ((volatile unsigned char *)0x480000FA)
+#define CONTROL_PADCONF_MMC_DAT_DIR2    ((volatile unsigned char *)0x480000FB)
+#define CONTROL_PADCONF_MMC_DAT_DIR3    ((volatile unsigned char *)0x480000FC)
+#define CONTROL_PADCONF_MMC_CMD_DIR     ((volatile unsigned char *)0x480000FD)
+
+#define CONTROL_PADCONF_SDRC_A14        ((volatile unsigned char *)0x48000030)
+#define CONTROL_PADCONF_SDRC_A13        ((volatile unsigned char *)0x48000031)
+
+/* Pin Muxing registers used for CAMERA */
+#define CONTROL_PADCONF_SYS_NRESWARM    ((volatile unsigned char *)0x4800012B)
+
+#define CONTROL_PADCONF_CAM_XCLK        ((volatile unsigned char *)0x480000DC)
+#define CONTROL_PADCONF_CAM_LCLK        ((volatile unsigned char *)0x480000DB)
+#define CONTROL_PADCONF_CAM_VS          ((volatile unsigned char *)0x480000DA)
+#define CONTROL_PADCONF_CAM_HS          ((volatile unsigned char *)0x480000D9)
+#define CONTROL_PADCONF_CAM_D0          ((volatile unsigned char *)0x480000D8)
+#define CONTROL_PADCONF_CAM_D1          ((volatile unsigned char *)0x480000D7)
+#define CONTROL_PADCONF_CAM_D2          ((volatile unsigned char *)0x480000D6)
+#define CONTROL_PADCONF_CAM_D3          ((volatile unsigned char *)0x480000D5)
+#define CONTROL_PADCONF_CAM_D4          ((volatile unsigned char *)0x480000D4)
+#define CONTROL_PADCONF_CAM_D5          ((volatile unsigned char *)0x480000D3)
+#define CONTROL_PADCONF_CAM_D6          ((volatile unsigned char *)0x480000D2)
+#define CONTROL_PADCONF_CAM_D7          ((volatile unsigned char *)0x480000D1)
+#define CONTROL_PADCONF_CAM_D8          ((volatile unsigned char *)0x480000D0)
+#define CONTROL_PADCONF_CAM_D9          ((volatile unsigned char *)0x480000CF)
+
+/* Pin Muxing registers used for LCD */
+#define CONTROL_PADCONF_DSS_D0          ((volatile unsigned char *)0x480000B3)
+#define CONTROL_PADCONF_DSS_D1          ((volatile unsigned char *)0x480000B4)
+#define CONTROL_PADCONF_DSS_D2          ((volatile unsigned char *)0x480000B5)
+#define CONTROL_PADCONF_DSS_D3          ((volatile unsigned char *)0x480000B6)
+#define CONTROL_PADCONF_DSS_D4          ((volatile unsigned char *)0x480000B7)
+#define CONTROL_PADCONF_DSS_D5          ((volatile unsigned char *)0x480000B8)
+#define CONTROL_PADCONF_DSS_D6          ((volatile unsigned char *)0x480000B9)
+#define CONTROL_PADCONF_DSS_D7          ((volatile unsigned char *)0x480000BA)
+#define CONTROL_PADCONF_DSS_D8          ((volatile unsigned char *)0x480000BB)
+#define CONTROL_PADCONF_DSS_D9          ((volatile unsigned char *)0x480000BC)
+#define CONTROL_PADCONF_DSS_D10         ((volatile unsigned char *)0x480000BD)
+#define CONTROL_PADCONF_DSS_D11         ((volatile unsigned char *)0x480000BE)
+#define CONTROL_PADCONF_DSS_D12         ((volatile unsigned char *)0x480000BF)
+#define CONTROL_PADCONF_DSS_D13         ((volatile unsigned char *)0x480000C0)
+#define CONTROL_PADCONF_DSS_D14         ((volatile unsigned char *)0x480000C1)
+#define CONTROL_PADCONF_DSS_D15         ((volatile unsigned char *)0x480000C2)
+#define CONTROL_PADCONF_DSS_D16         ((volatile unsigned char *)0x480000C3)
+#define CONTROL_PADCONF_DSS_D17         ((volatile unsigned char *)0x480000C4)
+#define CONTROL_PADCONF_DSS_PCLK        ((volatile unsigned char *)0x480000CB)
+#define CONTROL_PADCONF_DSS_VSYNC       ((volatile unsigned char *)0x480000CC)
+#define CONTROL_PADCONF_DSS_HSYNC       ((volatile unsigned char *)0x480000CD)
+#define CONTROL_PADCONF_DSS_ACBIAS      ((volatile unsigned char *)0x480000CE)
+
+/* Pin Muxing registers used for UART1 */
+#define CONTROL_PADCONF_UART1_CTS       ((volatile unsigned char *)0x480000C5)
+#define CONTROL_PADCONF_UART1_RTS       ((volatile unsigned char *)0x480000C6)
+#define CONTROL_PADCONF_UART1_TX        ((volatile unsigned char *)0x480000C7)
+#define CONTROL_PADCONF_UART1_RX        ((volatile unsigned char *)0x480000C8)
+
+/* Pin Muxing registers used for I2C1 */
+#define CONTROL_PADCONF_I2C1_SCL        ((volatile unsigned char *)0x48000111)
+#define CONTROL_PADCONF_I2C1_SDA        ((volatile unsigned char *)0x48000112)
+
+/* Pin Muxing registres used for USB0. */
+#define CONTROL_PADCONF_USB0_PUEN		((volatile uint8 *)0x4800011D)
+#define CONTROL_PADCONF_USB0_VP			((volatile uint8 *)0x4800011E)
+#define CONTROL_PADCONF_USB0_VM			((volatile uint8 *)0x4800011F)
+#define CONTROL_PADCONF_USB0_RCV		((volatile uint8 *)0x48000120)
+#define CONTROL_PADCONF_USB0_TXEN		((volatile uint8 *)0x48000121)
+#define CONTROL_PADCONF_USB0_SE0		((volatile uint8 *)0x48000122)
+#define CONTROL_PADCONF_USB0_DAT		((volatile uint8 *)0x48000123)
+
+/* Pin Muxing registers used for UART3/IRDA */
+#define CONTROL_PADCONF_UART3_TX_IRTX	((volatile uint8 *)0x48000118)
+#define CONTROL_PADCONF_UART3_RX_IRRX	((volatile uint8 *)0x48000119)
+
+#endif
diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h
new file mode 100755
index 0000000..d833035
--- /dev/null
+++ b/include/asm-arm/arch-arm1136/omap2420.h
@@ -0,0 +1,221 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP2420_SYS_H_
+#define _OMAP2420_SYS_H_
+
+#include <asm/arch/sizes.h>
+
+/*
+ * 2420 specific Section
+ */
+
+/* L3 Firewall */
+#define A_REQINFOPERM0        0x68005048
+#define A_READPERM0           0x68005050
+#define A_WRITEPERM0          0x68005058
+/* #define GP_DEVICE	(BIT8|BIT9)  FIXME -- commented out to make compile -- FIXME */
+
+/* L3 Firewall */
+#define A_REQINFOPERM0        0x68005048
+#define A_READPERM0           0x68005050
+#define A_WRITEPERM0          0x68005058
+
+/* CONTROL */
+#define OMAP2420_CTRL_BASE    (0x48000000)
+#define CONTROL_STATUS        (OMAP2420_CTRL_BASE + 0x2F8)
+
+/* device type */
+#define TST_DEVICE	0x0
+#define EMU_DEVICE	0x1
+#define HS_DEVICE	0x2
+#define GP_DEVICE	0x3
+
+/* TAP information */
+#define OMAP2420_TAP_BASE     (0x48014000)
+#define TAP_IDCODE_REG        (OMAP2420_TAP_BASE+0x204)
+#define PRODUCTION_ID         (OMAP2420_TAP_BASE+0x208)
+
+/* GPMC */
+#define OMAP2420_GPMC_BASE    (0x6800A000)
+#define GPMC_SYSCONFIG        (OMAP2420_GPMC_BASE+0x10)
+#define GPMC_IRQENABLE        (OMAP2420_GPMC_BASE+0x1C)
+#define GPMC_TIMEOUT_CONTROL  (OMAP2420_GPMC_BASE+0x40)
+#define GPMC_CONFIG           (OMAP2420_GPMC_BASE+0x50)
+#define GPMC_CONFIG1_0        (OMAP2420_GPMC_BASE+0x60)
+#define GPMC_CONFIG2_0        (OMAP2420_GPMC_BASE+0x64)
+#define GPMC_CONFIG3_0        (OMAP2420_GPMC_BASE+0x68)
+#define GPMC_CONFIG4_0        (OMAP2420_GPMC_BASE+0x6C)
+#define GPMC_CONFIG5_0        (OMAP2420_GPMC_BASE+0x70)
+#define GPMC_CONFIG6_0        (OMAP2420_GPMC_BASE+0x74)
+#define GPMC_CONFIG7_0	      (OMAP2420_GPMC_BASE+0x78)
+#define GPMC_CONFIG1_1        (OMAP2420_GPMC_BASE+0x90)
+#define GPMC_CONFIG2_1        (OMAP2420_GPMC_BASE+0x94)
+#define GPMC_CONFIG3_1        (OMAP2420_GPMC_BASE+0x98)
+#define GPMC_CONFIG4_1        (OMAP2420_GPMC_BASE+0x9C)
+#define GPMC_CONFIG5_1        (OMAP2420_GPMC_BASE+0xA0)
+#define GPMC_CONFIG6_1        (OMAP2420_GPMC_BASE+0xA4)
+#define GPMC_CONFIG7_1	      (OMAP2420_GPMC_BASE+0xA8)
+
+/* SMS */
+#define OMAP2420_SMS_BASE 0x68008000
+#define SMS_SYSCONFIG     (OMAP2420_SMS_BASE+0x10)
+#define SMS_CLASS_ARB0    (OMAP2420_SMS_BASE+0xD0)
+# define BURSTCOMPLETE_GROUP7    BIT31
+
+/* SDRC */
+#define OMAP2420_SDRC_BASE 0x68009000
+#define SDRC_SYSCONFIG     (OMAP2420_SDRC_BASE+0x10)
+#define SDRC_STATUS        (OMAP2420_SDRC_BASE+0x14)
+#define SDRC_CS_CFG        (OMAP2420_SDRC_BASE+0x40)
+#define SDRC_SHARING       (OMAP2420_SDRC_BASE+0x44)
+#define SDRC_DLLA_CTRL     (OMAP2420_SDRC_BASE+0x60)
+#define SDRC_DLLB_CTRL     (OMAP2420_SDRC_BASE+0x68)
+#define SDRC_POWER         (OMAP2420_SDRC_BASE+0x70)
+#define SDRC_MCFG_0        (OMAP2420_SDRC_BASE+0x80)
+#define SDRC_MR_0          (OMAP2420_SDRC_BASE+0x84)
+#define SDRC_ACTIM_CTRLA_0 (OMAP2420_SDRC_BASE+0x9C)
+#define SDRC_ACTIM_CTRLB_0 (OMAP2420_SDRC_BASE+0xA0)
+#define SDRC_ACTIM_CTRLA_1 (OMAP2420_SDRC_BASE+0xC4)
+#define SDRC_ACTIM_CTRLB_1 (OMAP2420_SDRC_BASE+0xC8)
+#define SDRC_RFR_CTRL      (OMAP2420_SDRC_BASE+0xA4)
+#define SDRC_MANUAL_0      (OMAP2420_SDRC_BASE+0xA8)
+#define OMAP2420_SDRC_CS0  0x80000000
+#define OMAP2420_SDRC_CS1  0xA0000000
+#define CMD_NOP            0x0
+#define CMD_PRECHARGE      0x1
+#define CMD_AUTOREFRESH    0x2
+#define CMD_ENTR_PWRDOWN   0x3
+#define CMD_EXIT_PWRDOWN   0x4
+#define CMD_ENTR_SRFRSH    0x5
+#define CMD_CKE_HIGH       0x6
+#define CMD_CKE_LOW        0x7
+#define SOFTRESET          BIT1
+#define SMART_IDLE         (0x2 << 3)
+#define REF_ON_IDLE        (0x1 << 6)
+
+
+/* UART */
+#define OMAP2420_UART1	      0x4806A000
+#define OMAP2420_UART2	      0x4806C000
+#define OMAP2420_UART3        0x4806E000
+
+/* General Purpose Timers */
+#define OMAP2420_GPT1         0x48028000
+#define OMAP2420_GPT2         0x4802A000
+#define OMAP2420_GPT3         0x48078000
+#define OMAP2420_GPT4         0x4807A000
+#define OMAP2420_GPT5         0x4807C000
+#define OMAP2420_GPT6         0x4807E000
+#define OMAP2420_GPT7         0x48080000
+#define OMAP2420_GPT8         0x48082000
+#define OMAP2420_GPT9         0x48084000
+#define OMAP2420_GPT10        0x48086000
+#define OMAP2420_GPT11        0x48088000
+#define OMAP2420_GPT12        0x4808A000
+
+/* timer regs offsets (32 bit regs) */
+#define TIDR       0x0      /* r */
+#define TIOCP_CFG  0x10     /* rw */
+#define TISTAT     0x14     /* r */
+#define TISR       0x18     /* rw */
+#define TIER       0x1C     /* rw */
+#define TWER       0x20     /* rw */
+#define TCLR       0x24     /* rw */
+#define TCRR       0x28     /* rw */
+#define TLDR       0x2C     /* rw */
+#define TTGR       0x30     /* rw */
+#define TWPS       0x34     /* r */
+#define TMAR       0x38     /* rw */
+#define TCAR1      0x3c     /* r */
+#define TSICR      0x40     /* rw */
+#define TCAR2      0x44     /* r */
+
+/* WatchDog Timers (1 secure, 3 GP) */
+#define WD1_BASE              0x48020000
+#define WD2_BASE              0x48022000
+#define WD3_BASE              0x48024000
+#define WD4_BASE              0x48026000
+#define WWPS       0x34     /* r */
+#define WSPR       0x48     /* rw */
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+/* PRCM */
+#define OMAP2420_CM_BASE 0x48008000
+#define PRCM_CLKCFG_CTRL (OMAP2420_CM_BASE+0x080)
+#define CM_CLKSEL_MPU    (OMAP2420_CM_BASE+0x140)
+#define CM_FCLKEN1_CORE  (OMAP2420_CM_BASE+0x200)
+#define CM_FCLKEN2_CORE  (OMAP2420_CM_BASE+0x204)
+#define CM_ICLKEN1_CORE  (OMAP2420_CM_BASE+0x210)
+#define CM_ICLKEN2_CORE  (OMAP2420_CM_BASE+0x214)
+#define CM_CLKSEL1_CORE  (OMAP2420_CM_BASE+0x240)
+#define CM_CLKSEL_WKUP   (OMAP2420_CM_BASE+0x440)
+#define CM_CLKSEL2_CORE  (OMAP2420_CM_BASE+0x244)
+#define CM_CLKSEL_GFX    (OMAP2420_CM_BASE+0x340)
+#define PM_RSTCTRL_WKUP  (OMAP2420_CM_BASE+0x450)
+#define CM_CLKEN_PLL     (OMAP2420_CM_BASE+0x500)
+#define CM_IDLEST_CKGEN  (OMAP2420_CM_BASE+0x520)
+#define CM_CLKSEL1_PLL   (OMAP2420_CM_BASE+0x540)
+#define CM_CLKSEL2_PLL   (OMAP2420_CM_BASE+0x544)
+#define CM_CLKSEL_DSP    (OMAP2420_CM_BASE+0x840)
+
+/*
+ * H4 specific Section
+ */
+
+/*
+ *  The 2420's chip selects are programmable.  The mask ROM
+ *  does configure CS0 to 0x08000000 before dispatch.  So, if
+ *  you want your code to live below that address, you have to
+ *  be prepared to jump though hoops, to reset the base address.
+ */
+#if defined(CONFIG_OMAP2420H4)
+/* GPMC */
+#ifdef CONFIG_VIRTIO_A        /* Pre version B */
+# define H4_CS0_BASE           0x08000000  /* flash (64 Meg aligned) */
+# define H4_CS1_BASE           0x04000000  /* debug board */
+# define H4_CS2_BASE           0x0A000000  /* wifi board */
+#else
+# define H4_CS0_BASE           0x04000000  /* flash (64 Meg aligned) */
+# define H4_CS1_BASE           0x08000000  /* debug board */
+# define H4_CS2_BASE           0x0A000000  /* wifi board */
+#endif
+
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_OFFSET0          0x40000000
+#define SRAM_OFFSET1          0x00200000
+#define SRAM_OFFSET2          0x0000F800
+#define SRAM_VECT_CODE       (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
+
+#define LOW_LEVEL_SRAM_STACK  0x4020FFFC
+
+#define PERIFERAL_PORT_BASE   0x480FE003
+
+/* FPGA on Debug board.*/
+#define ETH_CONTROL_REG       (H4_CS1_BASE+0x30b)
+#define LAN_RESET_REGISTER    (H4_CS1_BASE+0x1c)
+#endif  /* endif CONFIG_2420H4 */
+
+#endif
diff --git a/include/asm-arm/arch-arm1136/sizes.h b/include/asm-arm/arch-arm1136/sizes.h
new file mode 100755
index 0000000..aaba18f
--- /dev/null
+++ b/include/asm-arm/arch-arm1136/sizes.h
@@ -0,0 +1,49 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ */
+/*  Size defintions
+ *  Copyright (C) ARM Limited 1998. All rights reserved.
+ */
+
+#ifndef __sizes_h
+#define __sizes_h			1
+
+/* handy sizes */
+#define SZ_1K				0x00000400
+#define SZ_4K				0x00001000
+#define SZ_8K				0x00002000
+#define SZ_16K				0x00004000
+#define SZ_32K				0x00008000
+#define SZ_64K				0x00010000
+#define SZ_128K				0x00020000
+#define SZ_256K				0x00040000
+#define SZ_512K				0x00080000
+
+#define SZ_1M				0x00100000
+#define SZ_2M				0x00200000
+#define SZ_4M				0x00400000
+#define SZ_8M				0x00800000
+#define SZ_16M				0x01000000
+#define SZ_31M				0x01F00000
+#define SZ_32M				0x02000000
+#define SZ_64M				0x04000000
+#define SZ_128M				0x08000000
+#define SZ_256M				0x10000000
+#define SZ_512M				0x20000000
+
+#define SZ_1G				0x40000000
+#define SZ_2G				0x80000000
+
+#endif	/* __sizes_h */
diff --git a/include/asm-arm/arch-arm1136/sys_info.h b/include/asm-arm/arch-arm1136/sys_info.h
new file mode 100755
index 0000000..53c231a
--- /dev/null
+++ b/include/asm-arm/arch-arm1136/sys_info.h
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP24XX_SYS_INFO_H_
+#define _OMAP24XX_SYS_INFO_H_
+
+typedef struct  h4_system_data {
+	/* base board info */
+	u32 base_b_rev;		/* rev from base board i2c */
+	/* cpu board info */
+	u32 cpu_b_rev;		/* rev from cpu board i2c */
+	u32 cpu_b_mux;		/* mux type on daughter board */
+	u32 cpu_b_ddr_type;	/* mem type */
+	u32 cpu_b_ddr_speed;	/* ddr speed rating */
+	u32 cpu_b_switches;	/* boot ctrl switch settings */
+	/* cpu info */
+	u32 cpu_type;		/* type of cpu; 2420, 2422, 2430,...*/
+	u32 cpu_rev;		/* rev of given cpu; ES1, ES2,...*/
+} h4_sys_data;
+
+#define XDR_POP           5      /* package on package part */
+#define SDR_DISCRETE      4      /* 128M memory SDR module*/
+#define DDR_STACKED       3      /* stacked part on 2422 */
+#define DDR_COMBO         2      /* combo part on cpu daughter card (menalaeus) */
+#define DDR_DISCRETE      1      /* 2x16 parts on daughter card */
+
+#define DDR_100           100    /* type found on most mem d-boards */
+#define DDR_111           111    /* some combo parts */
+#define DDR_133           133    /* most combo, some mem d-boards */
+#define DDR_165           165    /* future parts */
+
+#define CPU_2420          0x2420
+#define CPU_2422          0x2422 /* 2420 + 64M stacked */
+#define CPU_2423          0x2423 /* 2420 + 96M stacked */
+
+#define CPU_2422_ES1      1
+#define CPU_2422_ES2      2
+#define CPU_2420_ES1      1
+#define CPU_2420_ES2      2
+#define CPU_2420_2422_ES1 1
+
+#define CPU_2420_CHIPID   0x0B5D9000
+#define CPU_24XX_ID_MASK  0x0FFFF000
+#define CPU_242X_REV_MASK 0xF0000000
+#define CPU_242X_PID_MASK 0x000F0000
+
+#define BOARD_H4_MENELAUS 1
+#define BOARD_H4_SDP      2
+
+#define GPMC_MUXED        1
+#define GPMC_NONMUXED     0
+
+#define TYPE_NAND         0x800   /* bit pos for nand in gpmc reg */
+#define TYPE_NOR          0x000
+
+#define WIDTH_8BIT        0x0000
+#define WIDTH_16BIT       0x1000  /* bit pos for 16 bit in gpmc */
+
+#define I2C_MENELAUS 0x72	/* i2c id for companion chip */
+
+#endif
diff --git a/include/asm-arm/arch-arm1136/sys_proto.h b/include/asm-arm/arch-arm1136/sys_proto.h
new file mode 100755
index 0000000..9d8e5b2
--- /dev/null
+++ b/include/asm-arm/arch-arm1136/sys_proto.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+  */
+#ifndef _OMAP24XX_SYS_PROTO_H_
+#define _OMAP24XX_SYS_PROTO_H_
+
+void prcm_init(void);
+void memif_init(void);
+void sdrc_init(void);
+void do_sdrc_init(u32,u32);
+void gpmc_init(void);
+
+void ether_init(void);
+void watchdog_init(void);
+void set_muxconf_regs(void);
+void peripheral_enable(void);
+
+u32 get_cpu_type(void);
+u32 get_cpu_rev(void);
+u32 get_mem_type(void);
+u32 get_sysboot_value(void);
+u32 get_gpmc0_base(void);
+u32 is_gpmc_muxed(void);
+u32 get_gpmc0_type(void);
+u32 get_gpmc0_width(void);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound);
+u32 get_board_type(void);
+void display_board_info(u32);
+void update_mux(u32,u32);
+u32 get_sdr_cs_size(u32 offset);
+
+u32 running_in_sdram(void);
+u32 running_in_sram(void);
+u32 running_in_flash(void);
+u32 running_from_internal_boot(void);
+u32 get_device_type(void);
+#endif
diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h
new file mode 100755
index 0000000..3056ca7
--- /dev/null
+++ b/include/asm-arm/arch-arm720t/hardware.h
@@ -0,0 +1,43 @@
+#ifndef __ARM7_HW_H
+#define __ARM7_HW_H
+
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if defined(CONFIG_S3C4510B)
+#include <asm-arm/arch-arm720t/s3c4510b.h>
+#elif defined(CONFIG_NETARM)
+#include <asm-arm/arch-arm720t/netarm_registers.h>
+#elif defined(CONFIG_IMPA7)
+/* include IMPA7 specific hardware file if there was one */
+#elif defined(CONFIG_EP7312)
+/* include EP7312 specific hardware file if there was one */
+#elif defined(CONFIG_ARMADILLO)
+/* include armadillo specific hardware file if there was one */
+#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+/* include IntegratorCP/CM720T specific hardware file if there was one */
+#else
+#error No hardware file defined for this configuration
+#endif
+
+#endif /* __ARM7_HW_H */
diff --git a/include/asm-arm/arch-arm720t/netarm_dma_module.h b/include/asm-arm/arch-arm720t/netarm_dma_module.h
new file mode 100755
index 0000000..328eaf0
--- /dev/null
+++ b/include/asm-arm/arch-arm720t/netarm_dma_module.h
@@ -0,0 +1,182 @@
+/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h
+ *
+ * Copyright (C) 2000 NETsilicon, Inc.
+ * Copyright (C) 2000 WireSpeed Communications Corporation
+ *
+ * This software is copyrighted by WireSpeed. LICENSEE agrees that
+ * it will not delete this copyright notice, trademarks or protective
+ * notices from any copy made by LICENSEE.
+ *
+ * This software is provided "AS-IS" and any express or implied
+ * warranties or conditions, including but not limited to any
+ * implied warranties of merchantability and fitness for a particular
+ * purpose regarding this software. In no event shall WireSpeed
+ * be liable for any indirect, consequential, or incidental damages,
+ * loss of profits or revenue, loss of use or data, or interruption
+ * of business, whether the alleged damages are labeled in contract,
+ * tort, or indemnity.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * author(s) : Joe deBlaquiere
+ *             David Smith
+ */
+
+#ifndef __NETARM_DMA_MODULE_REGISTERS_H
+#define __NETARM_DMA_MODULE_REGISTERS_H
+
+/* GEN unit register offsets */
+
+#define	NETARM_DMA_MODULE_BASE		(0xFF900000)
+
+#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c)))
+
+#define	NETARM_DMA1A_BFR_DESCRPTOR_PTR	(0x00)
+#define	NETARM_DMA1A_CONTROL		(0x10)
+#define	NETARM_DMA1A_STATUS		(0x14)
+#define	NETARM_DMA1B_BFR_DESCRPTOR_PTR	(0x20)
+#define	NETARM_DMA1B_CONTROL		(0x30)
+#define	NETARM_DMA1B_STATUS		(0x34)
+#define	NETARM_DMA1C_BFR_DESCRPTOR_PTR	(0x40)
+#define	NETARM_DMA1C_CONTROL		(0x50)
+#define	NETARM_DMA1C_STATUS		(0x54)
+#define	NETARM_DMA1D_BFR_DESCRPTOR_PTR	(0x60)
+#define	NETARM_DMA1D_CONTROL		(0x70)
+#define	NETARM_DMA1D_STATUS		(0x74)
+
+#define	NETARM_DMA2_BFR_DESCRPTOR_PTR	(0x80)
+#define	NETARM_DMA2_CONTROL		(0x90)
+#define	NETARM_DMA2_STATUS		(0x94)
+
+#define	NETARM_DMA3_BFR_DESCRPTOR_PTR	(0xA0)
+#define	NETARM_DMA3_CONTROL		(0xB0)
+#define	NETARM_DMA3_STATUS		(0xB4)
+
+#define	NETARM_DMA4_BFR_DESCRPTOR_PTR	(0xC0)
+#define	NETARM_DMA4_CONTROL		(0xD0)
+#define	NETARM_DMA4_STATUS		(0xD4)
+
+#define	NETARM_DMA5_BFR_DESCRPTOR_PTR	(0xE0)
+#define	NETARM_DMA5_CONTROL		(0xF0)
+#define	NETARM_DMA5_STATUS		(0xF4)
+
+#define	NETARM_DMA6_BFR_DESCRPTOR_PTR	(0x100)
+#define	NETARM_DMA6_CONTROL		(0x110)
+#define	NETARM_DMA6_STATUS		(0x114)
+
+#define	NETARM_DMA7_BFR_DESCRPTOR_PTR	(0x120)
+#define	NETARM_DMA7_CONTROL		(0x130)
+#define	NETARM_DMA7_STATUS		(0x134)
+
+#define	NETARM_DMA8_BFR_DESCRPTOR_PTR	(0x140)
+#define	NETARM_DMA8_CONTROL		(0x150)
+#define	NETARM_DMA8_STATUS		(0x154)
+
+#define	NETARM_DMA9_BFR_DESCRPTOR_PTR	(0x160)
+#define	NETARM_DMA9_CONTROL		(0x170)
+#define	NETARM_DMA9_STATUS		(0x174)
+
+#define	NETARM_DMA10_BFR_DESCRPTOR_PTR	(0x180)
+#define	NETARM_DMA10_CONTROL		(0x190)
+#define	NETARM_DMA10_STATUS		(0x194)
+
+/* select bitfield defintions */
+
+/* DMA Control Register ( 0xFF90_0XX0 ) */
+
+#define NETARM_DMA_CTL_ENABLE		(0x80000000)
+
+#define NETARM_DMA_CTL_ABORT		(0x40000000)
+
+#define NETARM_DMA_CTL_BUS_100_PERCENT	(0x00000000)
+#define NETARM_DMA_CTL_BUS_75_PERCENT	(0x10000000)
+#define NETARM_DMA_CTL_BUS_50_PERCENT	(0x20000000)
+#define NETARM_DMA_CTL_BUS_25_PERCENT	(0x30000000)
+
+#define NETARM_DMA_CTL_BUS_MASK		(0x30000000)
+
+#define NETARM_DMA_CTL_MODE_FB_TO_MEM	(0x00000000)
+#define NETARM_DMA_CTL_MODE_FB_FROM_MEM	(0x04000000)
+#define NETARM_DMA_CTL_MODE_MEM_TO_MEM	(0x08000000)
+
+#define NETARM_DMA_CTL_BURST_NONE	(0x00000000)
+#define NETARM_DMA_CTL_BURST_8_BYTE	(0x01000000)
+#define NETARM_DMA_CTL_BURST_16_BYTE	(0x02000000)
+
+#define NETARM_DMA_CTL_BURST_MASK	(0x03000000)
+
+#define NETARM_DMA_CTL_SRC_INCREMENT	(0x00200000)
+
+#define NETARM_DMA_CTL_DST_INCREMENT	(0x00100000)
+
+/* these apply only to ext xfers on DMA 3 or 4 */
+
+#define NETARM_DMA_CTL_CH_3_4_REQ_EXT	(0x00800000)
+
+#define NETARM_DMA_CTL_CH_3_4_DATA_32	(0x00000000)
+#define NETARM_DMA_CTL_CH_3_4_DATA_16	(0x00010000)
+#define NETARM_DMA_CTL_CH_3_4_DATA_8	(0x00020000)
+
+#define NETARM_DMA_CTL_STATE(X)	((X) & 0xFC00)
+#define NETARM_DMA_CTL_INDEX(X)	((X) & 0x03FF)
+
+/* DMA Status Register ( 0xFF90_0XX4 ) */
+
+#define NETARM_DMA_STAT_NC_INTPEN	(0x80000000)
+#define NETARM_DMA_STAT_EC_INTPEN	(0x40000000)
+#define NETARM_DMA_STAT_NR_INTPEN	(0x20000000)
+#define NETARM_DMA_STAT_CA_INTPEN	(0x10000000)
+#define NETARM_DMA_STAT_INTPEN_MASK	(0xF0000000)
+
+#define NETARM_DMA_STAT_NC_INT_EN	(0x00800000)
+#define NETARM_DMA_STAT_EC_INT_EN	(0x00400000)
+#define NETARM_DMA_STAT_NR_INT_EN	(0x00200000)
+#define NETARM_DMA_STAT_CA_INT_EN	(0x00100000)
+#define NETARM_DMA_STAT_INT_EN_MASK	(0x00F00000)
+
+#define NETARM_DMA_STAT_WRAP		(0x00080000)
+#define NETARM_DMA_STAT_IDONE		(0x00040000)
+#define NETARM_DMA_STAT_LAST		(0x00020000)
+#define NETARM_DMA_STAT_FULL		(0x00010000)
+
+#define	NETARM_DMA_STAT_BUFLEN(X)	((X) & 0x7FFF)
+
+/* DMA Buffer Descriptor Word 0 bitfields. */
+
+#define NETARM_DMA_BD0_WRAP		(0x80000000)
+#define NETARM_DMA_BD0_IDONE		(0x40000000)
+#define NETARM_DMA_BD0_LAST		(0x20000000)
+#define NETARM_DMA_BD0_BUFPTR_MASK	(0x1FFFFFFF)
+
+/* DMA Buffer Descriptor Word 1 bitfields. */
+
+#define NETARM_DMA_BD1_STATUS_MASK	(0xFFFF0000)
+#define NETARM_DMA_BD1_FULL		(0x00008000)
+#define NETARM_DMA_BD1_BUFLEN_MASK	(0x00007FFF)
+
+#ifndef	__ASSEMBLER__
+
+typedef	struct __NETARM_DMA_Buff_Desc_FlyBy
+{
+	unsigned int word0;
+	unsigned int word1;
+} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ;
+
+typedef	struct __NETARM_DMA_Buff_Desc_M_to_M
+{
+	unsigned int word0;
+	unsigned int word1;
+	unsigned int word2;
+	unsigned int word3;
+} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ;
+
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-arm720t/netarm_eni_module.h b/include/asm-arm/arch-arm720t/netarm_eni_module.h
new file mode 100755
index 0000000..317b354
--- /dev/null
+++ b/include/asm-arm/arch-arm720t/netarm_eni_module.h
@@ -0,0 +1,121 @@
+/*
+ * include/asm-armnommu/arch-netarm/netarm_eni_module.h
+ *
+ * Copyright (C) 2000 NETsilicon, Inc.
+ * Copyright (C) 2000 WireSpeed Communications Corporation
+ *
+ * This software is copyrighted by WireSpeed. LICENSEE agrees that
+ * it will not delete this copyright notice, trademarks or protective
+ * notices from any copy made by LICENSEE.
+ *
+ * This software is provided "AS-IS" and any express or implied
+ * warranties or conditions, including but not limited to any
+ * implied warranties of merchantability and fitness for a particular
+ * purpose regarding this software. In no event shall WireSpeed
+ * be liable for any indirect, consequential, or incidental damages,
+ * loss of profits or revenue, loss of use or data, or interruption
+ * of business, whether the alleged damages are labeled in contract,
+ * tort, or indemnity.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * author(s) : David Smith
+ */
+
+#ifndef __NETARM_ENI_MODULE_REGISTERS_H
+#define __NETARM_ENI_MODULE_REGISTERS_H
+
+/* ENI unit register offsets */
+
+/* #ifdef CONFIG_ARCH_NETARM */
+#define	NETARM_ENI_MODULE_BASE		(0xFFA00000)
+/* #endif / * CONFIG_ARCH_NETARM */
+
+#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c)))
+#define get_eni_ctl_reg_addr(minor) \
+	(get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor))
+
+#define	NETARM_ENI_GENERAL_CONTROL	(0x00)
+#define	NETARM_ENI_STATUS_CONTROL	(0x04)
+#define	NETARM_ENI_FIFO_MODE_DATA	(0x08)
+
+#define	NETARM_ENI_1284_PORT1_CONTROL	(0x10)
+#define	NETARM_ENI_1284_PORT2_CONTROL	(0x14)
+#define	NETARM_ENI_1284_PORT3_CONTROL	(0x18)
+#define	NETARM_ENI_1284_PORT4_CONTROL	(0x1c)
+
+#define	NETARM_ENI_1284_CHANNEL1_DATA	(0x20)
+#define	NETARM_ENI_1284_CHANNEL2_DATA	(0x24)
+#define	NETARM_ENI_1284_CHANNEL3_DATA	(0x28)
+#define	NETARM_ENI_1284_CHANNEL4_DATA	(0x2c)
+
+#define	NETARM_ENI_ENI_CONTROL		(0x30)
+#define	NETARM_ENI_ENI_PULSED_INTR	(0x34)
+#define	NETARM_ENI_ENI_SHARED_RAM_ADDR	(0x38)
+#define	NETARM_ENI_ENI_SHARED		(0x3c)
+
+/* select bitfield defintions */
+
+/* General Control Register (0xFFA0_0000) */
+
+#define NETARM_ENI_GCR_ENIMODE_IEEE1284	(0x00000001)
+#define NETARM_ENI_GCR_ENIMODE_SHRAM16	(0x00000004)
+#define NETARM_ENI_GCR_ENIMODE_SHRAM8	(0x00000005)
+#define NETARM_ENI_GCR_ENIMODE_FIFO16	(0x00000006)
+#define NETARM_ENI_GCR_ENIMODE_FIFO8	(0x00000007)
+
+#define NETARM_ENI_GCR_ENIMODE_MASK	(0x00000007)
+
+/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014,
+   0xFFA0_0018, 0xFFA0_001c) */
+
+#define NETARM_ENI_1284PC_PORT_ENABLE	(0x80000000)
+#define NETARM_ENI_1284PC_DMA_ENABLE	(0x40000000)
+#define NETARM_ENI_1284PC_OBE_INT_EN	(0x20000000)
+#define NETARM_ENI_1284PC_ACK_INT_EN	(0x10000000)
+#define NETARM_ENI_1284PC_ECP_MODE	(0x08000000)
+#define NETARM_ENI_1284PC_LOOPBACK_MODE	(0x04000000)
+
+#define NETARM_ENI_1284PC_STROBE_TIME0	(0x00000000) /* 0.5 uS */
+#define NETARM_ENI_1284PC_STROBE_TIME1	(0x01000000) /* 1.0 uS */
+#define NETARM_ENI_1284PC_STROBE_TIME2	(0x02000000) /* 5.0 uS */
+#define NETARM_ENI_1284PC_STROBE_TIME3	(0x03000000) /* 10.0 uS */
+#define NETARM_ENI_1284PC_STROBE_MASK	(0x03000000)
+
+#define NETARM_ENI_1284PC_MAN_STROBE_EN	(0x00800000)
+#define NETARM_ENI_1284PC_FAST_MODE	(0x00400000)
+#define NETARM_ENI_1284PC_BIDIR_MODE	(0x00200000)
+
+#define NETARM_ENI_1284PC_MAN_STROBE	(0x00080000)
+#define NETARM_ENI_1284PC_AUTO_FEED	(0x00040000)
+#define NETARM_ENI_1284PC_INIT		(0x00020000)
+#define NETARM_ENI_1284PC_HSELECT	(0x00010000)
+#define NETARM_ENI_1284PC_FE_INT_EN	(0x00008000)
+#define NETARM_ENI_1284PC_EPP_MODE	(0x00004000)
+#define NETARM_ENI_1284PC_IBR_INT_EN	(0x00002000)
+#define NETARM_ENI_1284PC_IBR		(0x00001000)
+
+#define NETARM_ENI_1284PC_RXFDB_1BYTE	(0x00000400)
+#define NETARM_ENI_1284PC_RXFDB_2BYTE	(0x00000800)
+#define NETARM_ENI_1284PC_RXFDB_3BYTE	(0x00000c00)
+#define NETARM_ENI_1284PC_RXFDB_4BYTE	(0x00000000)
+
+#define NETARM_ENI_1284PC_RBCC		(0x00000200)
+#define NETARM_ENI_1284PC_RBCT		(0x00000100)
+#define NETARM_ENI_1284PC_ACK		(0x00000080)
+#define NETARM_ENI_1284PC_FIFO_E	(0x00000040)
+#define NETARM_ENI_1284PC_OBE		(0x00000020)
+#define NETARM_ENI_1284PC_ACK_INT	(0x00000010)
+#define NETARM_ENI_1284PC_BUSY		(0x00000008)
+#define NETARM_ENI_1284PC_PE		(0x00000004)
+#define NETARM_ENI_1284PC_PSELECT	(0x00000002)
+#define NETARM_ENI_1284PC_FAULT		(0x00000001)
+
+#endif /* __NETARM_ENI_MODULE_REGISTERS_H */
diff --git a/include/asm-arm/arch-arm720t/netarm_eth_module.h b/include/asm-arm/arch-arm720t/netarm_eth_module.h
new file mode 100755
index 0000000..8f2f369
--- /dev/null
+++ b/include/asm-arm/arch-arm720t/netarm_eth_module.h
@@ -0,0 +1,160 @@
+/*
+ * include/asm-armnommu/arch-netarm/netarm_eth_module.h
+ *
+ * Copyright (C) 2000 NETsilicon, Inc.
+ * Copyright (C) 2000 WireSpeed Communications Corporation
+ *
+ * This software is copyrighted by WireSpeed. LICENSEE agrees that
+ * it will not delete this copyright notice, trademarks or protective
+ * notices from any copy made by LICENSEE.
+ *
+ * This software is provided "AS-IS" and any express or implied
+ * warranties or conditions, including but not limited to any
+ * implied warranties of merchantability and fitness for a particular
+ * purpose regarding this software. In no event shall WireSpeed
+ * be liable for any indirect, consequential, or incidental damages,
+ * loss of profits or revenue, loss of use or data, or interruption
+ * of business, whether the alleged damages are labeled in contract,
+ * tort, or indemnity.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * author(s) : Jackie Smith Cashion
+ *             David Smith
+ */
+
+#ifndef __NETARM_ETH_MODULE_REGISTERS_H
+#define __NETARM_ETH_MODULE_REGISTERS_H
+
+/* ETH unit register offsets */
+
+#define	NETARM_ETH_MODULE_BASE		(0xFF800000)
+
+#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c)))
+
+#define NETARM_ETH_GEN_CTRL		(0x000) /* Ethernet Gen Control Reg */
+#define NETARM_ETH_GEN_STAT		(0x004) /* Ethernet Gen Status Reg */
+#define NETARM_ETH_FIFO_DAT1            (0x008) /* Fifo Data Reg 1 */
+#define NETARM_ETH_FIFO_DAT2            (0x00C) /* Fifo Data Reg 2 */
+#define NETARM_ETH_TX_STAT              (0x010) /* Transmit Status Reg */
+#define NETARM_ETH_RX_STAT              (0x014) /* Receive Status Reg */
+
+#define NETARM_ETH_MAC_CFG		(0x400) /* MAC Configuration Reg */
+#define NETARM_ETH_PCS_CFG		(0x408) /* PCS Configuration Reg */
+#define NETARM_ETH_STL_CFG		(0x410) /* STL Configuration Reg */
+#define NETARM_ETH_B2B_IPG_GAP_TMR	(0x440) /* Back-to-back IPG
+						   Gap Timer Reg */
+#define NETARM_ETH_NB2B_IPG_GAP_TMR	(0x444) /* Non Back-to-back
+						   IPG Gap Timer Reg */
+#define NETARM_ETH_MII_CMD		(0x540) /* MII (PHY) Command Reg */
+#define NETARM_ETH_MII_ADDR		(0x544) /* MII Address Reg */
+#define NETARM_ETH_MII_WRITE		(0x548) /* MII Write Data Reg */
+#define NETARM_ETH_MII_READ		(0x54C) /* MII Read Data Reg */
+#define NETARM_ETH_MII_IND		(0x550) /* MII Indicators Reg */
+#define NETARM_ETH_MIB_CRCEC		(0x580) /* (MIB) CRC Error Counter */
+#define NETARM_ETH_MIB_AEC		(0x584) /* Alignment Error Counter */
+#define NETARM_ETH_MIB_CEC		(0x588) /* Code Error Counter */
+#define NETARM_ETH_MIB_LFC		(0x58C) /* Long Frame Counter */
+#define NETARM_ETH_MIB_SFC		(0x590) /* Short Frame Counter */
+#define NETARM_ETH_MIB_LCC		(0x594) /* Late Collision Counter */
+#define NETARM_ETH_MIB_EDC		(0x598) /* Excessive Deferral
+						   Counter */
+#define NETARM_ETH_MIB_MCC		(0x59C) /* Maximum Collision Counter */
+#define NETARM_ETH_SAL_FILTER		(0x5C0) /* SAL Station Address
+						   Filter Reg */
+#define NETARM_ETH_SAL_STATION_ADDR_1	(0x5C4) /* SAL Station Address
+						   Reg */
+#define NETARM_ETH_SAL_STATION_ADDR_2	(0x5C8)
+#define NETARM_ETH_SAL_STATION_ADDR_3	(0x5CC)
+#define NETARM_ETH_SAL_HASH_TBL_1	(0x5D0) /* SAL Multicast Hash Table*/
+#define NETARM_ETH_SAL_HASH_TBL_2	(0x5D4)
+#define NETARM_ETH_SAL_HASH_TBL_3	(0x5D8)
+#define NETARM_ETH_SAL_HASH_TBL_4	(0x5DC)
+
+/* select bitfield defintions */
+
+/* Ethernet General Control Register (0xFF80_0000) */
+
+#define NETARM_ETH_GCR_ERX		(0x80000000) /* Enable Receive FIFO */
+#define NETARM_ETH_GCR_ERXDMA		(0x40000000) /* Enable Receive DMA */
+#define NETARM_ETH_GCR_ETX		(0x00800000) /* Enable Transmit FIFO */
+#define NETARM_ETH_GCR_ETXDMA		(0x00400000) /* Enable Transmit DMA */
+#define NETARM_ETH_GCR_ETXWM_50		(0x00100000) /* Transmit FIFO Water
+							Mark.  Start transmit
+							when FIFO is 50%
+							full. */
+#define NETARM_ETH_GCR_PNA		(0x00000400) /* pSOS pNA Buffer
+							Descriptor Format */
+
+/* Ethernet General Status Register (0xFF80_0004) */
+
+#define NETARM_ETH_GST_RXFDB            (0x30000000)
+#define NETARM_ETH_GST_RXREGR		(0x08000000) /* Receive Register
+							Ready */
+#define NETARM_ETH_GST_RXFIFOH		(0x04000000)
+#define NETARM_ETH_GST_RXBR		(0x02000000)
+#define NETARM_ETH_GST_RXSKIP		(0x01000000)
+
+#define NETARM_ETH_GST_TXBC             (0x00020000)
+
+
+/* Ethernet Transmit Status Register (0xFF80_0010) */
+
+#define NETARM_ETH_TXSTAT_TXOK          (0x00008000)
+
+
+/* Ethernet Receive Status Register (0xFF80_0014) */
+
+#define NETARM_ETH_RXSTAT_SIZE          (0xFFFF0000)
+#define NETARM_ETH_RXSTAT_RXOK          (0x00002000)
+
+
+/* PCS Configuration Register (0xFF80_0408) */
+
+#define NETARM_ETH_PCSC_NOCFR		(0x1) /* Disable Ciphering */
+#define NETARM_ETH_PCSC_ENJAB		(0x2) /* Enable Jabber Protection */
+#define NETARM_ETH_PCSC_CLKS_25M	(0x0) /* 25 MHz Clock Speed Select */
+#define NETARM_ETH_PCSC_CLKS_33M	(0x4) /* 33 MHz Clock Speed Select */
+
+/* STL Configuration Register (0xFF80_0410) */
+
+#define NETARM_ETH_STLC_RXEN		(0x2) /* Enable Packet Receiver */
+#define NETARM_ETH_STLC_AUTOZ		(0x4) /* Auto Zero Statistics */
+
+/* MAC Configuration Register (0xFF80_0400) */
+
+#define NETARM_ETH_MACC_HUGEN		(0x1) /* Enable Unlimited Transmit
+						 Frame Sizes */
+#define NETARM_ETH_MACC_PADEN		(0x4) /* Automatic Pad Fill Frames
+						 to 64 Bytes */
+#define NETARM_ETH_MACC_CRCEN		(0x8) /* Append CRC to Transmit
+						 Frames */
+
+/* MII (PHY) Command Register (0xFF80_0540) */
+
+#define NETARM_ETH_MIIC_RSTAT		(0x1) /* Single Scan for Read Data */
+
+/* MII Indicators Register (0xFF80_0550) */
+
+#define NETARM_ETH_MIII_BUSY		(0x1) /* MII I/F Busy with
+						 Read/Write */
+
+/* SAL Station Address Filter Register (0xFF80_05C0) */
+
+#define NETARM_ETH_SALF_PRO		(0x8) /* Enable Promiscuous Mode */
+#define NETARM_ETH_SALF_PRM		(0x4) /* Accept All Multicast
+						 Packets */
+#define NETARM_ETH_SALF_PRA		(0x2) /* Accept Mulitcast Packets
+						 using Hash Table */
+#define NETARM_ETH_SALF_BROAD		(0x1) /* Accept All Broadcast
+						 Packets */
+
+
+#endif /* __NETARM_GEN_MODULE_REGISTERS_H */
diff --git a/include/asm-arm/arch-arm720t/netarm_gen_module.h b/include/asm-arm/arch-arm720t/netarm_gen_module.h
new file mode 100755
index 0000000..13656a3
--- /dev/null
+++ b/include/asm-arm/arch-arm720t/netarm_gen_module.h
@@ -0,0 +1,186 @@
+/*
+ * include/asm-armnommu/arch-netarm/netarm_gen_module.h
+ *
+ * Copyright (C) 2005
+ * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
+ *
+ * Copyright (C) 2000, 2001 NETsilicon, Inc.
+ * Copyright (C) 2000, 2001 Red Hat, Inc.
+ *
+ * This software is copyrighted by Red Hat. LICENSEE agrees that
+ * it will not delete this copyright notice, trademarks or protective
+ * notices from any copy made by LICENSEE.
+ *
+ * This software is provided "AS-IS" and any express or implied
+ * warranties or conditions, including but not limited to any
+ * implied warranties of merchantability and fitness for a particular
+ * purpose regarding this software. In no event shall Red Hat
+ * be liable for any indirect, consequential, or incidental damages,
+ * loss of profits or revenue, loss of use or data, or interruption
+ * of business, whether the alleged damages are labeled in contract,
+ * tort, or indemnity.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * author(s) : Joe deBlaquiere
+ *
+ * Modified to support NS7520 by Art Shipkowski.
+ */
+
+#ifndef __NETARM_GEN_MODULE_REGISTERS_H
+#define __NETARM_GEN_MODULE_REGISTERS_H
+
+/* GEN unit register offsets */
+
+#define NETARM_GEN_MODULE_BASE		(0xFFB00000)
+
+#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c)))
+
+#define NETARM_GEN_SYSTEM_CONTROL	(0x00)
+#define NETARM_GEN_STATUS_CONTROL	(0x04)
+#define NETARM_GEN_PLL_CONTROL		(0x08)
+#define NETARM_GEN_SOFTWARE_SERVICE	(0x0c)
+
+#define NETARM_GEN_TIMER1_CONTROL	(0x10)
+#define NETARM_GEN_TIMER1_STATUS	(0x14)
+#define NETARM_GEN_TIMER2_CONTROL	(0x18)
+#define NETARM_GEN_TIMER2_STATUS	(0x1c)
+
+#define NETARM_GEN_PORTA		(0x20)
+#ifndef CONFIG_NETARM_NS7520
+#define NETARM_GEN_PORTB		(0x24)
+#endif
+#define NETARM_GEN_PORTC		(0x28)
+
+#define NETARM_GEN_INTR_ENABLE		(0x30)
+#define NETARM_GEN_INTR_ENABLE_SET	(0x34)
+#define NETARM_GEN_INTR_ENABLE_CLR	(0x38)
+#define NETARM_GEN_INTR_STATUS_EN	(0x34)
+#define NETARM_GEN_INTR_STATUS_RAW	(0x38)
+
+#define NETARM_GEN_CACHE_CONTROL1	(0x40)
+#define NETARM_GEN_CACHE_CONTROL2	(0x44)
+
+/* select bitfield definitions */
+
+/* System Control Register ( 0xFFB0_0000 ) */
+
+#define NETARM_GEN_SYS_CFG_LENDIAN	(0x80000000)
+#define NETARM_GEN_SYS_CFG_BENDIAN	(0x00000000)
+
+#define NETARM_GEN_SYS_CFG_BUSQRTR	(0x00000000)
+#define NETARM_GEN_SYS_CFG_BUSHALF	(0x20000000)
+#define NETARM_GEN_SYS_CFG_BUSFULL	(0x40000000)
+
+#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000)
+
+#define NETARM_GEN_SYS_CFG_WDOG_EN	(0x01000000)
+#define NETARM_GEN_SYS_CFG_WDOG_IRQ	(0x00000000)
+#define NETARM_GEN_SYS_CFG_WDOG_FIQ	(0x00400000)
+#define NETARM_GEN_SYS_CFG_WDOG_RST	(0x00800000)
+#define NETARM_GEN_SYS_CFG_WDOG_24	(0x00000000)
+#define NETARM_GEN_SYS_CFG_WDOG_26	(0x00100000)
+#define NETARM_GEN_SYS_CFG_WDOG_28	(0x00200000)
+#define NETARM_GEN_SYS_CFG_WDOG_29	(0x00300000)
+
+#define NETARM_GEN_SYS_CFG_BUSMON_EN	(0x00040000)
+#define NETARM_GEN_SYS_CFG_BUSMON_128	(0x00000000)
+#define NETARM_GEN_SYS_CFG_BUSMON_64	(0x00010000)
+#define NETARM_GEN_SYS_CFG_BUSMON_32	(0x00020000)
+#define NETARM_GEN_SYS_CFG_BUSMON_16	(0x00030000)
+
+#define NETARM_GEN_SYS_CFG_USER_EN	(0x00008000)
+#define NETARM_GEN_SYS_CFG_BUSER_EN	(0x00004000)
+
+#define NETARM_GEN_SYS_CFG_BUSARB_INT	(0x00002000)
+#define NETARM_GEN_SYS_CFG_BUSARB_EXT	(0x00000000)
+
+#define NETARM_GEN_SYS_CFG_DMATST	(0x00001000)
+
+#define NETARM_GEN_SYS_CFG_TEALAST	(0x00000800)
+
+#define NETARM_GEN_SYS_CFG_ALIGN_ABORT	(0x00000400)
+
+#define NETARM_GEN_SYS_CFG_CACHE_EN	(0x00000200)
+
+#define NETARM_GEN_SYS_CFG_WRI_BUF_EN	(0x00000100)
+
+#define NETARM_GEN_SYS_CFG_CACHE_INIT	(0x00000080)
+
+/* PLL Control Register ( 0xFFB0_0008 ) */
+
+#define NETARM_GEN_PLL_CTL_PLLCNT_MASK	(0x0F000000)
+
+#define NETARM_GEN_PLL_CTL_PLLCNT(x)	(((x)<<24) & \
+					 NETARM_GEN_PLL_CTL_PLLCNT_MASK)
+
+/* Defaults for POLTST and ICP Fields in PLL CTL */
+#define NETARM_GEN_PLL_CTL_OUTDIV(x)	(x)
+#define NETARM_GEN_PLL_CTL_INDIV(x)	((x)<<6)
+#define NETARM_GEN_PLL_CTL_POLTST_DEF	(0x00000E00)
+#define NETARM_GEN_PLL_CTL_ICP_DEF	(0x0000003C)
+
+
+/* Software Service Register ( 0xFFB0_000C ) */
+
+#define NETARM_GEN_SW_SVC_RESETA	(0x123)
+#define NETARM_GEN_SW_SVC_RESETB	(0x321)
+
+/* PORT C Register ( 0xFFB0_0028 ) */
+
+#ifndef CONFIG_NETARM_NS7520
+#define NETARM_GEN_PORT_MODE(x)		(((x)<<24) + (0xFF00))
+#define NETARM_GEN_PORT_DIR(x)		(((x)<<16) + (0xFF00))
+#else
+#define NETARM_GEN_PORT_MODE(x)		((x)<<24)
+#define NETARM_GEN_PORT_DIR(x)		((x)<<16)
+#define NETARM_GEN_PORT_CSF(x)		((x)<<8)
+#endif
+
+/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */
+
+#define NETARM_GEN_TCTL_ENABLE		(0x80000000)
+#define NETARM_GEN_TCTL_INT_ENABLE	(0x40000000)
+
+#define NETARM_GEN_TCTL_USE_IRQ		(0x00000000)
+#define NETARM_GEN_TCTL_USE_FIQ		(0x20000000)
+
+#define NETARM_GEN_TCTL_USE_PRESCALE	(0x10000000)
+#define NETARM_GEN_TCTL_INIT_COUNT(x)	((x) & 0x1FF)
+
+#define NETARM_GEN_TSTAT_INTPEN		(0x40000000)
+#if ~defined(CONFIG_NETARM_NS7520)
+#define NETARM_GEN_TSTAT_CTC_MASK	(0x000001FF)
+#else
+#define NETARM_GEN_TSTAT_CTC_MASK	(0x0FFFFFFF)
+#endif
+
+/* prescale to msecs conversion */
+
+#if !defined(CONFIG_NETARM_PLL_BYPASS)
+#define NETARM_GEN_TIMER_MSEC_P(x)	( ( ( 20480 ) * ( 0x1FF - ( (x) &	    \
+					    NETARM_GEN_TSTAT_CTC_MASK ) +   \
+					    1 ) ) / (NETARM_XTAL_FREQ/1000) )
+
+#define NETARM_GEN_TIMER_SET_HZ(x)	( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \
+					  NETARM_GEN_TSTAT_CTC_MASK ) | \
+					  NETARM_GEN_TCTL_USE_PRESCALE )
+
+#else
+#define NETARM_GEN_TIMER_MSEC_P(x)	( ( ( 4096 ) * ( 0x1FF - ( (x) &    \
+					    NETARM_GEN_TSTAT_CTC_MASK ) +   \
+					    1 ) ) / (NETARM_XTAL_FREQ/1000) )
+
+#define NETARM_GEN_TIMER_SET_HZ(x)	( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \
+					  NETARM_GEN_TSTAT_CTC_MASK ) | \
+					  NETARM_GEN_TCTL_USE_PRESCALE )
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-arm720t/netarm_mem_module.h b/include/asm-arm/arch-arm720t/netarm_mem_module.h
new file mode 100755
index 0000000..f0529fd
--- /dev/null
+++ b/include/asm-arm/arch-arm720t/netarm_mem_module.h
@@ -0,0 +1,184 @@
+/*
+ * include/asm-armnommu/arch-netarm/netarm_mem_module.h
+ *
+ * Copyright (C) 2005
+ * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
+ *
+ * Copyright (C) 2000, 2001 NETsilicon, Inc.
+ * Copyright (C) 2000, 2001 Red Hat, Inc.
+ *
+ * This software is copyrighted by Red Hat. LICENSEE agrees that
+ * it will not delete this copyright notice, trademarks or protective
+ * notices from any copy made by LICENSEE.
+ *
+ * This software is provided "AS-IS" and any express or implied
+ * warranties or conditions, including but not limited to any
+ * implied warranties of merchantability and fitness for a particular
+ * purpose regarding this software. In no event shall Red Hat
+ * be liable for any indirect, consequential, or incidental damages,
+ * loss of profits or revenue, loss of use or data, or interruption
+ * of business, whether the alleged damages are labeled in contract,
+ * tort, or indemnity.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * author(s) : Joe deBlaquiere
+ *
+ * Modified to support NS7520 by Art Shipkowski.
+ */
+
+#ifndef __NETARM_MEM_MODULE_REGISTERS_H
+#define __NETARM_MEM_MODULE_REGISTERS_H
+
+/* GEN unit register offsets */
+
+#define	NETARM_MEM_MODULE_BASE		(0xFFC00000)
+
+#define	NETARM_MEM_MODULE_CONFIG	(0x00)
+#define	NETARM_MEM_CS0_BASE_ADDR	(0x10)
+#define	NETARM_MEM_CS0_OPTIONS		(0x14)
+#define	NETARM_MEM_CS1_BASE_ADDR	(0x20)
+#define	NETARM_MEM_CS1_OPTIONS		(0x24)
+#define	NETARM_MEM_CS2_BASE_ADDR	(0x30)
+#define	NETARM_MEM_CS2_OPTIONS		(0x34)
+#define	NETARM_MEM_CS3_BASE_ADDR	(0x40)
+#define	NETARM_MEM_CS3_OPTIONS		(0x44)
+#define	NETARM_MEM_CS4_BASE_ADDR	(0x50)
+#define	NETARM_MEM_CS4_OPTIONS		(0x54)
+
+/* select bitfield defintions */
+
+/* Module Configuration Register ( 0xFFC0_0000 ) */
+
+#define NETARM_MEM_CFG_REFR_COUNT_MASK	(0xFF000000)
+#define NETARM_MEM_CFG_REFRESH_EN	(0x00800000)
+
+#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS	(0x00000000)
+#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS	(0x00200000)
+#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS	(0x00400000)
+#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS	(0x00600000)
+
+#define NETARM_MEM_CFG_PORTC_AMUX	(0x00100000)
+
+#define NETARM_MEM_CFG_A27_ADDR		(0x00080000)
+#define NETARM_MEM_CFG_A27_CS0OE	(0x00000000)
+
+#define NETARM_MEM_CFG_A26_ADDR		(0x00040000)
+#define NETARM_MEM_CFG_A26_CS0WE	(0x00000000)
+
+#define NETARM_MEM_CFG_A25_ADDR		(0x00020000)
+#define NETARM_MEM_CFG_A25_BLAST	(0x00000000)
+
+#define NETARM_MEM_CFG_PORTC_AMUX2	(0x00010000)
+
+
+/* range on this period is about 1 to 275 usec (with 18.432MHz clock)   */
+/* the expression will round down, so make sure to reverse it to verify */
+/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal        */
+/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */
+
+#define	NETARM_MEM_REFR_PERIOD_USEC(p)	(NETARM_MEM_CFG_REFR_COUNT_MASK & \
+					 (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \
+					    ) - (1) ) << (24)))
+
+#if 0
+/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
+/* the expression will round down, so make sure to reverse it toverify */
+/* it is what you want. period = [( count + 1 ) * 4] / Fxtal          */
+
+#define	NETARM_MEM_REFR_PERIOD_USEC(p)	(NETARM_MEM_CFG_REFR_COUNT_MASK & \
+					 (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \
+					    ) - (1) ) << (24)))
+#endif
+
+/* Base Address Registers (0xFFC0_00X0) */
+
+#define NETARM_MEM_BAR_BASE_MASK	(0xFFFFF000)
+
+/* macro to define base */
+
+#define NETARM_MEM_BAR_BASE(x)		((x) & NETARM_MEM_BAR_BASE_MASK)
+
+#define NETARM_MEM_BAR_DRAM_FP		(0x00000000)
+#define NETARM_MEM_BAR_DRAM_EDO		(0x00000100)
+#define NETARM_MEM_BAR_DRAM_SYNC	(0x00000200)
+
+#define NETARM_MEM_BAR_DRAM_MUX_INT	(0x00000000)
+#define NETARM_MEM_BAR_DRAM_MUX_EXT	(0x00000080)
+
+#define NETARM_MEM_BAR_DRAM_MUX_BAL	(0x00000000)
+#define NETARM_MEM_BAR_DRAM_MUX_UNBAL	(0x00000020)
+
+#define NETARM_MEM_BAR_1BCLK_IDLE	(0x00000010)
+
+#define NETARM_MEM_BAR_DRAM_SEL		(0x00000008)
+
+#define NETARM_MEM_BAR_BURST_EN		(0x00000004)
+
+#define NETARM_MEM_BAR_WRT_PROT		(0x00000002)
+
+#define NETARM_MEM_BAR_VALID		(0x00000001)
+
+/* Option Registers (0xFFC0_00X4) */
+
+/* macro to define which bits of the base are significant */
+
+#define NETARM_MEM_OPT_BASE_USE(x)	((x) & NETARM_MEM_BAR_BASE_MASK)
+
+#define NETARM_MEM_OPT_WAIT_MASK	(0x00000F00)
+
+#define	NETARM_MEM_OPT_WAIT_STATES(x)	(((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK )
+
+#define NETARM_MEM_OPT_BCYC_1		(0x00000000)
+#define NETARM_MEM_OPT_BCYC_2		(0x00000040)
+#define NETARM_MEM_OPT_BCYC_3		(0x00000080)
+#define NETARM_MEM_OPT_BCYC_4		(0x000000C0)
+
+#define NETARM_MEM_OPT_BSIZE_2		(0x00000000)
+#define NETARM_MEM_OPT_BSIZE_4		(0x00000010)
+#define NETARM_MEM_OPT_BSIZE_8		(0x00000020)
+#define NETARM_MEM_OPT_BSIZE_16		(0x00000030)
+
+#define NETARM_MEM_OPT_32BIT		(0x00000000)
+#define NETARM_MEM_OPT_16BIT		(0x00000004)
+#define NETARM_MEM_OPT_8BIT		(0x00000008)
+#define NETARM_MEM_OPT_32BIT_EXT_ACK	(0x0000000C)
+
+#define NETARM_MEM_OPT_BUS_SIZE_MASK	(0x0000000C)
+
+#define NETARM_MEM_OPT_READ_ASYNC	(0x00000000)
+#define NETARM_MEM_OPT_READ_SYNC	(0x00000002)
+
+#define NETARM_MEM_OPT_WRITE_ASYNC	(0x00000000)
+#define NETARM_MEM_OPT_WRITE_SYNC	(0x00000001)
+
+#ifdef CONFIG_NETARM_NS7520
+/* The NS7520 has a second options register for each chip select */
+#define	NETARM_MEM_CS0_OPTIONS_B  (0x18)
+#define	NETARM_MEM_CS1_OPTIONS_B  (0x28)
+#define	NETARM_MEM_CS2_OPTIONS_B  (0x38)
+#define	NETARM_MEM_CS3_OPTIONS_B  (0x48)
+#define	NETARM_MEM_CS4_OPTIONS_B  (0x58)
+
+/* Option B Registers (0xFFC0_00x8) */
+#define NETARM_MEM_OPTB_SYNC_1_STAGE	(0x00000001)
+#define NETARM_MEM_OPTB_SYNC_2_STAGE	(0x00000002)
+#define NETARM_MEM_OPTB_BCYC_PLUS0   	(0x00000000)
+#define NETARM_MEM_OPTB_BCYC_PLUS4   	(0x00000004)
+#define NETARM_MEM_OPTB_BCYC_PLUS8   	(0x00000008)
+#define NETARM_MEM_OPTB_BCYC_PLUS12  	(0x0000000C)
+
+#define NETARM_MEM_OPTB_WAIT_PLUS0   	(0x00000000)
+#define NETARM_MEM_OPTB_WAIT_PLUS16   	(0x00000010)
+#define NETARM_MEM_OPTB_WAIT_PLUS32   	(0x00000020)
+#define NETARM_MEM_OPTB_WAIT_PLUS48   	(0x00000030)
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-arm720t/netarm_registers.h b/include/asm-arm/arch-arm720t/netarm_registers.h
new file mode 100755
index 0000000..fa88128
--- /dev/null
+++ b/include/asm-arm/arch-arm720t/netarm_registers.h
@@ -0,0 +1,96 @@
+/*
+ * linux/include/asm-arm/arch-netarm/netarm_registers.h
+ *
+ * Copyright (C) 2005
+ * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
+ *
+ * Copyright (C) 2000, 2001 NETsilicon, Inc.
+ * Copyright (C) 2000, 2001 WireSpeed Communications Corporation
+ *
+ * This software is copyrighted by WireSpeed. LICENSEE agrees that
+ * it will not delete this copyright notice, trademarks or protective
+ * notices from any copy made by LICENSEE.
+ *
+ * This software is provided "AS-IS" and any express or implied
+ * warranties or conditions, including but not limited to any
+ * implied warranties of merchantability and fitness for a particular
+ * purpose regarding this software. In no event shall WireSpeed
+ * be liable for any indirect, consequential, or incidental damages,
+ * loss of profits or revenue, loss of use or data, or interruption
+ * of business, whether the alleged damages are labeled in contract,
+ * tort, or indemnity.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * author(s) : Joe deBlaquiere
+ *
+ * Modified to support NS7520 by Art Shipkowski.
+ */
+
+#ifndef __NET_ARM_REGISTERS_H
+#define __NET_ARM_REGISTERS_H
+
+#include <config.h>
+
+/* fundamental constants : */
+/* the input crystal/clock frequency ( in Hz ) */
+#define	NETARM_XTAL_FREQ_25MHz		(18432000)
+#define	NETARM_XTAL_FREQ_33MHz		(23698000)
+#define	NETARM_XTAL_FREQ_48MHz		(48000000)
+#define	NETARM_XTAL_FREQ_55MHz		(55000000)
+#define NETARM_XTAL_FREQ_EMLIN1		(20000000)
+
+/* the frequency of SYS_CLK */
+#if defined(CONFIG_NETARM_EMLIN)
+
+/* EMLIN board:  33 MHz (exp.) */
+#define	NETARM_PLL_COUNT_VAL		6
+#define NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
+
+#elif defined(CONFIG_NETARM_NET40_REV2)
+
+/* NET+40 Rev2 boards:  33 MHz (with NETARM_XTAL_FREQ_25MHz) */
+#define	NETARM_PLL_COUNT_VAL		6
+#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
+
+#elif defined(CONFIG_NETARM_NET40_REV4)
+
+/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with
+   NETARM_XTAL_FREQ_25MHz) 4 */
+#define	NETARM_PLL_COUNT_VAL		4
+#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
+
+#elif defined(CONFIG_NETARM_NET50)
+
+/* NET+50 boards:  40 MHz (with NETARM_XTAL_FREQ_25MHz) */
+#define NETARM_PLL_COUNT_VAL		8
+#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
+
+#else	/* CONFIG_NETARM_NS7520 */
+
+#define	NETARM_PLL_COUNT_VAL		0
+
+#if defined(CONFIG_BOARD_UNC20)
+#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_48MHz
+#else
+#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_55MHz
+#endif
+
+#endif
+
+/* #include "arm_registers.h" */
+#include <asm/arch/netarm_gen_module.h>
+#include <asm/arch/netarm_mem_module.h>
+#include <asm/arch/netarm_ser_module.h>
+#include <asm/arch/netarm_eni_module.h>
+#include <asm/arch/netarm_dma_module.h>
+#include <asm/arch/netarm_eth_module.h>
+
+#endif
diff --git a/include/asm-arm/arch-arm720t/netarm_ser_module.h b/include/asm-arm/arch-arm720t/netarm_ser_module.h
new file mode 100755
index 0000000..fceabd1
--- /dev/null
+++ b/include/asm-arm/arch-arm720t/netarm_ser_module.h
@@ -0,0 +1,347 @@
+/*
+ * linux/include/asm-arm/arch-netarm/netarm_ser_module.h
+ *
+ * Copyright (C) 2000 NETsilicon, Inc.
+ * Copyright (C) 2000 Red Hat, Inc.
+ *
+ * This software is copyrighted by Red Hat. LICENSEE agrees that
+ * it will not delete this copyright notice, trademarks or protective
+ * notices from any copy made by LICENSEE.
+ *
+ * This software is provided "AS-IS" and any express or implied
+ * warranties or conditions, including but not limited to any
+ * implied warranties of merchantability and fitness for a particular
+ * purpose regarding this software. In no event shall Red Hat
+ * be liable for any indirect, consequential, or incidental damages,
+ * loss of profits or revenue, loss of use or data, or interruption
+ * of business, whether the alleged damages are labeled in contract,
+ * tort, or indemnity.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * author(s) : Joe deBlaquiere
+ *             Clark Williams
+ */
+
+#ifndef __NETARM_SER_MODULE_REGISTERS_H
+#define __NETARM_SER_MODULE_REGISTERS_H
+
+#ifndef	__ASSEMBLER__
+
+/* (--sub)#include "types.h" */
+
+/* serial channel control structure */
+typedef struct {
+  u32	ctrl_a;
+  u32	ctrl_b;
+  u32	status_a;
+  u32	bitrate;
+  u32	fifo;
+  u32	rx_buf_timer;
+  u32	rx_char_timer;
+  u32	rx_match;
+  u32	rx_match_mask;
+  u32	ctrl_c;
+  u32	status_b;
+  u32	status_c;
+  u32	fifo_last;
+  u32	unused[3];
+} netarm_serial_channel_t;
+
+#endif
+
+/* SER unit register offsets */
+
+/* #ifdef CONFIG_ARCH_NETARM */
+#define	NETARM_SER_MODULE_BASE		(0xFFD00000)
+/* #else */
+/* extern serial_channel_t netarm_dummy_registers[]; */
+/* #define NETARM_SER_MODULE_BASE		(netarm_dummy_registers) */
+/* #ifndef NETARM_XTAL_FREQ */
+/* #define NETARM_XTAL_FREQ                18432000 */
+/* #endif */
+/* #endif */
+
+/* calculate the sysclk value from the pll setting */
+#define	NETARM_PLLED_SYSCLK_FREQ	(( NETARM_XTAL_FREQ / 5 ) * \
+					 ( NETARM_PLL_COUNT_VAL + 3 ))
+
+#define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c]))
+
+#define	NETARM_SER_CH1_CTRL_A		(0x00)
+#define	NETARM_SER_CH1_CTRL_B		(0x04)
+#define	NETARM_SER_CH1_STATUS_A		(0x08)
+#define	NETARM_SER_CH1_BITRATE		(0x0C)
+#define	NETARM_SER_CH1_FIFO		(0x10)
+#define	NETARM_SER_CH1_RX_BUF_TMR	(0x14)
+#define	NETARM_SER_CH1_RX_CHAR_TMR	(0x18)
+#define	NETARM_SER_CH1_RX_MATCH		(0x1c)
+#define	NETARM_SER_CH1_RX_MATCH_MASK	(0x20)
+#define	NETARM_SER_CH1_CTRL_C		(0x24)
+#define	NETARM_SER_CH1_STATUS_B		(0x28)
+#define	NETARM_SER_CH1_STATUS_C		(0x2c)
+#define	NETARM_SER_CH1_FIFO_LAST	(0x30)
+
+#define	NETARM_SER_CH2_CTRL_A		(0x40)
+#define	NETARM_SER_CH2_CTRL_B		(0x44)
+#define	NETARM_SER_CH2_STATUS_A		(0x48)
+#define	NETARM_SER_CH2_BITRATE		(0x4C)
+#define	NETARM_SER_CH2_FIFO		(0x50)
+#define	NETARM_SER_CH2_RX_BUF_TMR	(0x54)
+#define	NETARM_SER_CH2_RX_CHAR_TMR	(0x58)
+#define	NETARM_SER_CH2_RX_MATCH		(0x5c)
+#define	NETARM_SER_CH2_RX_MATCH_MASK	(0x60)
+#define	NETARM_SER_CH2_CTRL_C		(0x64)
+#define	NETARM_SER_CH2_STATUS_B		(0x68)
+#define	NETARM_SER_CH2_STATUS_C		(0x6c)
+#define	NETARM_SER_CH2_FIFO_LAST	(0x70)
+
+/* select bitfield defintions */
+
+/* Control Register A */
+
+#define	NETARM_SER_CTLA_ENABLE		(0x80000000)
+#define	NETARM_SER_CTLA_BRK		(0x40000000)
+
+#define	NETARM_SER_CTLA_STICKP		(0x20000000)
+
+#define	NETARM_SER_CTLA_P_EVEN		(0x18000000)
+#define	NETARM_SER_CTLA_P_ODD		(0x08000000)
+#define	NETARM_SER_CTLA_P_NONE		(0x00000000)
+
+/* if you read the errata, you will find that the STOP bits don't work right */
+#define	NETARM_SER_CTLA_2STOP		(0x00000000)
+#define	NETARM_SER_CTLA_3STOP		(0x04000000)
+
+#define	NETARM_SER_CTLA_5BITS		(0x00000000)
+#define	NETARM_SER_CTLA_6BITS		(0x01000000)
+#define	NETARM_SER_CTLA_7BITS		(0x02000000)
+#define	NETARM_SER_CTLA_8BITS		(0x03000000)
+
+#define	NETARM_SER_CTLA_CTSTX		(0x00800000)
+#define	NETARM_SER_CTLA_RTSRX		(0x00400000)
+
+#define	NETARM_SER_CTLA_LOOP_REM	(0x00200000)
+#define	NETARM_SER_CTLA_LOOP_LOC	(0x00100000)
+
+#define	NETARM_SER_CTLA_GPIO2		(0x00080000)
+#define	NETARM_SER_CTLA_GPIO1		(0x00040000)
+
+#define	NETARM_SER_CTLA_DTR_EN		(0x00020000)
+#define	NETARM_SER_CTLA_RTS_EN		(0x00010000)
+
+#define	NETARM_SER_CTLA_IE_RX_BRK	(0x00008000)
+#define	NETARM_SER_CTLA_IE_RX_FRMERR	(0x00004000)
+#define	NETARM_SER_CTLA_IE_RX_PARERR	(0x00002000)
+#define	NETARM_SER_CTLA_IE_RX_OVERRUN	(0x00001000)
+#define	NETARM_SER_CTLA_IE_RX_RDY	(0x00000800)
+#define	NETARM_SER_CTLA_IE_RX_HALF	(0x00000400)
+#define	NETARM_SER_CTLA_IE_RX_FULL	(0x00000200)
+#define	NETARM_SER_CTLA_IE_RX_DMAEN	(0x00000100)
+#define	NETARM_SER_CTLA_IE_RX_DCD	(0x00000080)
+#define	NETARM_SER_CTLA_IE_RX_RI	(0x00000040)
+#define	NETARM_SER_CTLA_IE_RX_DSR	(0x00000020)
+
+#define NETARM_SER_CTLA_IE_RX_ALL	(NETARM_SER_CTLA_IE_RX_BRK \
+					|NETARM_SER_CTLA_IE_RX_FRMERR \
+					|NETARM_SER_CTLA_IE_RX_PARERR \
+					|NETARM_SER_CTLA_IE_RX_OVERRUN \
+					|NETARM_SER_CTLA_IE_RX_RDY \
+					|NETARM_SER_CTLA_IE_RX_HALF \
+					|NETARM_SER_CTLA_IE_RX_FULL \
+					|NETARM_SER_CTLA_IE_RX_DMAEN \
+					|NETARM_SER_CTLA_IE_RX_DCD \
+					|NETARM_SER_CTLA_IE_RX_RI \
+					|NETARM_SER_CTLA_IE_RX_DSR)
+
+#define	NETARM_SER_CTLA_IE_TX_CTS	(0x00000010)
+#define	NETARM_SER_CTLA_IE_TX_EMPTY	(0x00000008)
+#define	NETARM_SER_CTLA_IE_TX_HALF	(0x00000004)
+#define	NETARM_SER_CTLA_IE_TX_FULL	(0x00000002)
+#define	NETARM_SER_CTLA_IE_TX_DMAEN	(0x00000001)
+
+#define NETARM_SER_CTLA_IE_TX_ALL	(NETARM_SER_CTLA_IE_TX_CTS \
+					|NETARM_SER_CTLA_IE_TX_EMPTY \
+					|NETARM_SER_CTLA_IE_TX_HALF \
+					|NETARM_SER_CTLA_IE_TX_FULL \
+					|NETARM_SER_CTLA_IE_TX_DMAEN)
+
+/* Control Register B */
+
+#define	NETARM_SER_CTLB_MATCH1_EN	(0x80000000)
+#define	NETARM_SER_CTLB_MATCH2_EN	(0x40000000)
+#define	NETARM_SER_CTLB_MATCH3_EN	(0x20000000)
+#define	NETARM_SER_CTLB_MATCH4_EN	(0x10000000)
+
+#define	NETARM_SER_CTLB_RBGT_EN		(0x08000000)
+#define	NETARM_SER_CTLB_RCGT_EN		(0x04000000)
+
+#define	NETARM_SER_CTLB_UART_MODE	(0x00000000)
+#define	NETARM_SER_CTLB_HDLC_MODE	(0x00100000)
+#define	NETARM_SER_CTLB_SPI_MAS_MODE	(0x00200000)
+#define	NETARM_SER_CTLB_SPI_SLV_MODE	(0x00300000)
+
+#define	NETARM_SER_CTLB_REV_BIT_ORDER	(0x00080000)
+
+#define	NETARM_SER_CTLB_MAM1		(0x00040000)
+#define	NETARM_SER_CTLB_MAM2		(0x00020000)
+
+/* Status Register A */
+
+#define	NETARM_SER_STATA_MATCH1		(0x80000000)
+#define	NETARM_SER_STATA_MATCH2		(0x40000000)
+#define	NETARM_SER_STATA_MATCH3		(0x20000000)
+#define	NETARM_SER_STATA_MATCH4		(0x10000000)
+
+#define	NETARM_SER_STATA_BGAP		(0x80000000)
+#define	NETARM_SER_STATA_CGAP		(0x40000000)
+
+#define	NETARM_SER_STATA_RX_1B		(0x00100000)
+#define	NETARM_SER_STATA_RX_2B		(0x00200000)
+#define	NETARM_SER_STATA_RX_3B		(0x00300000)
+#define	NETARM_SER_STATA_RX_4B		(0x00000000)
+
+/* downshifted values */
+
+#define	NETARM_SER_STATA_RXFDB_1BYTES	(0x001)
+#define	NETARM_SER_STATA_RXFDB_2BYTES	(0x002)
+#define	NETARM_SER_STATA_RXFDB_3BYTES	(0x003)
+#define	NETARM_SER_STATA_RXFDB_4BYTES	(0x000)
+
+#define	NETARM_SER_STATA_RXFDB_MASK	(0x00300000)
+#define	NETARM_SER_STATA_RXFDB(x)	(((x) & NETARM_SER_STATA_RXFDB_MASK) \
+					 >> 20)
+
+#define	NETARM_SER_STATA_DCD		(0x00080000)
+#define	NETARM_SER_STATA_RI		(0x00040000)
+#define	NETARM_SER_STATA_DSR		(0x00020000)
+#define	NETARM_SER_STATA_CTS		(0x00010000)
+
+#define	NETARM_SER_STATA_RX_BRK		(0x00008000)
+#define	NETARM_SER_STATA_RX_FRMERR	(0x00004000)
+#define	NETARM_SER_STATA_RX_PARERR	(0x00002000)
+#define	NETARM_SER_STATA_RX_OVERRUN	(0x00001000)
+#define	NETARM_SER_STATA_RX_RDY		(0x00000800)
+#define	NETARM_SER_STATA_RX_HALF	(0x00000400)
+#define	NETARM_SER_STATA_RX_CLOSED	(0x00000200)
+#define	NETARM_SER_STATA_RX_FULL	(0x00000100)
+#define	NETARM_SER_STATA_RX_DCD		(0x00000080)
+#define	NETARM_SER_STATA_RX_RI		(0x00000040)
+#define	NETARM_SER_STATA_RX_DSR		(0x00000020)
+
+#define	NETARM_SER_STATA_TX_CTS		(0x00000010)
+#define	NETARM_SER_STATA_TX_RDY		(0x00000008)
+#define	NETARM_SER_STATA_TX_HALF	(0x00000004)
+#define	NETARM_SER_STATA_TX_FULL	(0x00000002)
+#define	NETARM_SER_STATA_TX_DMAEN	(0x00000001)
+
+/* you have to clear all receive signals to get the fifo to move forward */
+#define NETARM_SER_STATA_CLR_ALL	(NETARM_SER_STATA_RX_BRK | \
+					 NETARM_SER_STATA_RX_FRMERR | \
+					 NETARM_SER_STATA_RX_PARERR | \
+					 NETARM_SER_STATA_RX_OVERRUN | \
+					 NETARM_SER_STATA_RX_HALF | \
+					 NETARM_SER_STATA_RX_CLOSED | \
+					 NETARM_SER_STATA_RX_FULL | \
+					 NETARM_SER_STATA_RX_DCD | \
+					 NETARM_SER_STATA_RX_RI | \
+					 NETARM_SER_STATA_RX_DSR | \
+					 NETARM_SER_STATA_TX_CTS )
+
+/* Bit Rate Registers */
+
+#define	NETARM_SER_BR_EN		(0x80000000)
+#define	NETARM_SER_BR_TMODE		(0x40000000)
+
+#define	NETARM_SER_BR_RX_CLK_INT	(0x00000000)
+#define	NETARM_SER_BR_RX_CLK_EXT	(0x20000000)
+#define	NETARM_SER_BR_TX_CLK_INT	(0x00000000)
+#define	NETARM_SER_BR_TX_CLK_EXT	(0x10000000)
+
+#define	NETARM_SER_BR_RX_CLK_DRV	(0x08000000)
+#define	NETARM_SER_BR_TX_CLK_DRV	(0x04000000)
+
+#define	NETARM_SER_BR_CLK_EXT_5		(0x00000000)
+#define	NETARM_SER_BR_CLK_SYSTEM	(0x01000000)
+#define	NETARM_SER_BR_CLK_OUT1A		(0x02000000)
+#define	NETARM_SER_BR_CLK_OUT2A		(0x03000000)
+
+#define	NETARM_SER_BR_TX_CLK_INV	(0x00800000)
+#define	NETARM_SER_BR_RX_CLK_INV	(0x00400000)
+
+/* complete settings assuming system clock input is 18MHz */
+
+#define	NETARM_SER_BR_MASK		(0x000007FF)
+
+/* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */
+/* from section 7.5.4 of HW Ref Guide */
+
+/* #ifdef CONFIG_NETARM_PLL_BYPASS */
+#define	NETARM_SER_BR_X16(x)	( NETARM_SER_BR_EN | 			\
+				  NETARM_SER_BR_RX_CLK_INT | 		\
+				  NETARM_SER_BR_TX_CLK_INT | 		\
+				  NETARM_SER_BR_CLK_EXT_5 | 		\
+				  ( ( ( ( NETARM_XTAL_FREQ / 		\
+				          ( x * 10 ) ) - 1 ) /	16 ) & 	\
+				    NETARM_SER_BR_MASK ) )
+/*
+#else
+#define	NETARM_SER_BR_X16(x)	( NETARM_SER_BR_EN | 			\
+				  NETARM_SER_BR_RX_CLK_INT | 		\
+				  NETARM_SER_BR_TX_CLK_INT | 		\
+				  NETARM_SER_BR_CLK_SYSTEM | 		\
+				  ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / 		\
+				          ( x * 2 ) ) - 1 ) /	16 ) & 	\
+				    NETARM_SER_BR_MASK ) )
+#endif
+*/
+
+/* Receive Buffer Gap Timer */
+
+#define	NETARM_SER_RX_GAP_TIMER_EN	(0x80000000)
+#define	NETARM_SER_RX_GAP_MASK		(0x00003FFF)
+
+/* rx gap is a function of bit rate x */
+
+/* #ifdef CONFIG_NETARM_PLL_BYPASS */
+#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
+				  ( ( ( ( 10 * NETARM_XTAL_FREQ ) /	\
+				        ( x * 5 * 512 ) ) - 1 ) & 	\
+			              NETARM_SER_RX_GAP_MASK ) )
+/*
+#else
+#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |			\
+				  ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) /	\
+				        ( x * 512 ) ) - 1 ) & 			\
+			              NETARM_SER_RX_GAP_MASK ) )
+#endif
+*/
+
+#if 0
+#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
+				  ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) /	\
+				        ( x * 5 * 512 ) ) - 1 ) & 	\
+			              NETARM_SER_RX_GAP_MASK ) )
+#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
+				  ( ( ( ( 10 * NETARM_XTAL_FREQ ) /	\
+				        ( x * 512 ) ) - 1 ) & 	\
+			              NETARM_SER_RX_GAP_MASK ) )
+#endif
+
+#define MIN_BAUD_RATE        600
+#define MAX_BAUD_RATE     115200
+
+/* the default BAUD rate for the BOOTLOADER, there is a separate */
+/* setting in the serial driver <arch/armnommu/drivers/char/serial-netarm.h> */
+#define DEFAULT_BAUD_RATE 9600
+#define NETARM_SER_FIFO_SIZE 32
+#define MIN_GAP 0
+
+#endif
diff --git a/include/asm-arm/arch-arm720t/s3c4510b.h b/include/asm-arm/arch-arm720t/s3c4510b.h
new file mode 100755
index 0000000..517b1ad
--- /dev/null
+++ b/include/asm-arm/arch-arm720t/s3c4510b.h
@@ -0,0 +1,274 @@
+#ifndef __HW_S3C4510_H
+#define __HW_S3C4510_H
+
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:   Samsung S3C4510B register layout
+ */
+
+/*------------------------------------------------------------------------
+ *	  ASIC Address Definition
+ *----------------------------------------------------------------------*/
+
+/* L1 8KB on chip SRAM base address */
+#define SRAM_BASE       (0x03fe0000)
+
+/* Special Register Start Address After System Reset */
+#define REG_BASE	(0x03ff0000)
+#define SPSTR      	(REG_BASE)
+
+/* *********************** */
+/* System Manager Register */
+/* *********************** */
+#define REG_SYSCFG	(REG_BASE+0x0000)
+
+#define REG_CLKCON      (REG_BASE+0x3000)
+#define REG_EXTACON0	(REG_BASE+0x3008)
+#define REG_EXTACON1	(REG_BASE+0x300c)
+#define REG_EXTDBWTH	(REG_BASE+0x3010)
+#define REG_ROMCON0	(REG_BASE+0x3014)
+#define REG_ROMCON1	(REG_BASE+0x3018)
+#define REG_ROMCON2	(REG_BASE+0x301c)
+#define REG_ROMCON3	(REG_BASE+0x3020)
+#define REG_ROMCON4	(REG_BASE+0x3024)
+#define REG_ROMCON5	(REG_BASE+0x3028)
+#define REG_DRAMCON0	(REG_BASE+0x302c)
+#define REG_DRAMCON1	(REG_BASE+0x3030)
+#define REG_DRAMCON2	(REG_BASE+0x3034)
+#define REG_DRAMCON3	(REG_BASE+0x3038)
+#define REG_REFEXTCON	(REG_BASE+0x303c)
+
+/* *********************** */
+/* Ethernet BDMA Register  */
+/* *********************** */
+#define REG_BDMATXCON	(REG_BASE+0x9000)
+#define REG_BDMARXCON	(REG_BASE+0x9004)
+#define REG_BDMATXPTR	(REG_BASE+0x9008)
+#define REG_BDMARXPTR	(REG_BASE+0x900c)
+#define REG_BDMARXLSZ	(REG_BASE+0x9010)
+#define REG_BDMASTAT	(REG_BASE+0x9014)
+
+/* Content Address Memory */
+#define REG_CAM_BASE	(REG_BASE+0x9100)
+
+#define REG_BDMATXBUF	(REG_BASE+0x9200)
+#define REG_BDMARXBUF	(REG_BASE+0x9800)
+
+/* *********************** */
+/* Ethernet MAC Register   */
+/* *********************** */
+#define REG_MACCON	(REG_BASE+0xa000)
+#define REG_CAMCON	(REG_BASE+0xa004)
+#define REG_MACTXCON	(REG_BASE+0xa008)
+#define REG_MACTXSTAT	(REG_BASE+0xa00c)
+#define REG_MACRXCON	(REG_BASE+0xa010)
+#define REG_MACRXSTAT	(REG_BASE+0xa014)
+#define REG_STADATA	(REG_BASE+0xa018)
+#define REG_STACON	(REG_BASE+0xa01c)
+#define REG_CAMEN	(REG_BASE+0xa028)
+#define REG_EMISSCNT	(REG_BASE+0xa03c)
+#define REG_EPZCNT	(REG_BASE+0xa040)
+#define REG_ERMPZCNT	(REG_BASE+0xa044)
+#define REG_ETXSTAT	(REG_BASE+0x9040)
+#define REG_MACRXDESTR	(REG_BASE+0xa064)
+#define REG_MACRXSTATEM	(REG_BASE+0xa090)
+#define REG_MACRXFIFO	(REG_BASE+0xa200)
+
+/********************/
+/* I2C Bus Register */
+/********************/
+#define REG_I2C_CON	(REG_BASE+0xf000)
+#define REG_I2C_BUF	(REG_BASE+0xf004)
+#define REG_I2C_PS	(REG_BASE+0xf008)
+#define REG_I2C_COUNT 	(REG_BASE+0xf00c)
+
+/********************/
+/*    GDMA 0        */
+/********************/
+#define REG_GDMACON0	(REG_BASE+0xb000)
+#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020)
+#define REG_GDMASRC0	(REG_BASE+0xb004)
+#define REG_GDMADST0	(REG_BASE+0xb008)
+#define REG_GDMACNT0	(REG_BASE+0xb00c)
+
+/********************/
+/*    GDMA 1        */
+/********************/
+#define REG_GDMACON1	(REG_BASE+0xc000)
+#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020)
+#define REG_GDMASRC1	(REG_BASE+0xc004)
+#define REG_GDMADST1	(REG_BASE+0xc008)
+#define REG_GDMACNT1	(REG_BASE+0xc00c)
+
+/********************/
+/*      UART 0      */
+/********************/
+#define UART0_BASE       (REG_BASE+0xd000)
+#define REG_UART0_LCON   (REG_BASE+0xd000)
+#define REG_UART0_CTRL   (REG_BASE+0xd004)
+#define REG_UART0_STAT   (REG_BASE+0xd008)
+#define REG_UART0_TXB    (REG_BASE+0xd00c)
+#define REG_UART0_RXB    (REG_BASE+0xd010)
+#define REG_UART0_BAUD_DIV    (REG_BASE+0xd014)
+#define REG_UART0_BAUD_CNT    (REG_BASE+0xd018)
+#define REG_UART0_BAUD_CLK    (REG_BASE+0xd01C)
+
+/********************/
+/*     UART 1       */
+/********************/
+#define UART1_BASE       (REG_BASE+0xe000)
+#define REG_UART1_LCON   (REG_BASE+0xe000)
+#define REG_UART1_CTRL   (REG_BASE+0xe004)
+#define REG_UART1_STAT   (REG_BASE+0xe008)
+#define REG_UART1_TXB    (REG_BASE+0xe00c)
+#define REG_UART1_RXB    (REG_BASE+0xe010)
+#define REG_UART1_BAUD_DIV    (REG_BASE+0xe014)
+#define REG_UART1_BAUD_CNT    (REG_BASE+0xe018)
+#define REG_UART1_BAUD_CLK    (REG_BASE+0xe01C)
+
+/********************/
+/*  Timer Register  */
+/********************/
+#define REG_TMOD  	(REG_BASE+0x6000)
+#define REG_TDATA0	(REG_BASE+0x6004)
+#define REG_TDATA1	(REG_BASE+0x6008)
+#define REG_TCNT0	(REG_BASE+0x600c)
+#define REG_TCNT1	(REG_BASE+0x6010)
+
+/**********************/
+/* I/O Port Interface */
+/**********************/
+#define REG_IOPMODE	(REG_BASE+0x5000)
+#define REG_IOPCON  	(REG_BASE+0x5004)
+#define REG_IOPDATA 	(REG_BASE+0x5008)
+
+/*********************************/
+/* Interrupt Controller Register */
+/*********************************/
+#define REG_INTMODE     (REG_BASE+0x4000)
+#define REG_INTPEND     (REG_BASE+0x4004)
+#define REG_INTMASK     (REG_BASE+0x4008)
+
+#define REG_INTPRI0     (REG_BASE+0x400c)
+#define REG_INTPRI1	(REG_BASE+0x4010)
+#define REG_INTPRI2	(REG_BASE+0x4014)
+#define REG_INTPRI3	(REG_BASE+0x4018)
+#define REG_INTPRI4	(REG_BASE+0x401c)
+#define REG_INTPRI5	(REG_BASE+0x4020)
+#define REG_INTOFFSET	(REG_BASE+0x4024)
+#define REG_INTPNDPRI	(REG_BASE+0x4028)
+#define REG_INTPNDTST	(REG_BASE+0x402C)
+
+/*********************************/
+/* CACHE CONTROL MASKS           */
+/*********************************/
+#define CACHE_STALL      (0x00000001)
+#define CACHE_ENABLE     (0x00000002)
+#define CACHE_WRITE_BUFF (0x00000004)
+#define CACHE_MODE       (0x00000030)
+#define CACHE_MODE_00    (0x00000000)
+#define CACHE_MODE_01    (0x00000010)
+#define CACHE_MODE_10    (0x00000020)
+
+/*********************************/
+/* CACHE RAM BASE ADDRESSES      */
+/*********************************/
+#define CACHE_SET0_RAM   (0x10000000)
+#define CACHE_SET1_RAM   (0x10800000)
+#define CACHE_TAG_RAM    (0x11000000)
+
+/*********************************/
+/* CACHE_DISABLE MASK            */
+/*********************************/
+#define CACHE_DISABLE_MASK (0x04000000)
+
+#define GET_REG(reg)       (*((volatile u32 *)(reg)))
+#define PUT_REG(reg, val)  (*((volatile u32 *)(reg)) = ((u32)(val)))
+#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) |  mask))
+#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask))
+#define PUT_U16(reg, val)  (*((volatile u16 *)(reg)) = ((u16)(val)))
+#define PUT__U8(reg, val)  (*((volatile u8  *)(reg)) = (( u8)((val)&0xFF)))
+#define GET__U8(reg)       (*((volatile u8  *)(reg)))
+
+#define PUT_LED(val)       (PUT_REG(REG_IOPDATA, (~val)&0xFF))
+#define GET_LED()          ((~GET_REG( REG_IOPDATA)) & 0xFF)
+#define SET_LED(val)       { u32 led = GET_LED(); led |= 1 << (val);  PUT_LED( led); }
+#define CLR_LED(val)       { u32 led = GET_LED(); led &= ~(1 << (val));  PUT_LED( led); }
+
+/***********************************/
+/* CLOCK CONSTANTS -- 50 MHz Clock */
+/***********************************/
+
+#define CLK_FREQ_MHZ       (50)
+#define t_data_us(t)       ((t)*CLK_FREQ_MHZ-1)   /* t is time tick,unit[us] */
+#define t_data_ms(t)       (t_data_us((t)*1000))  /* t is time tick,unit[ms] */
+
+/*********************************************************/
+/*	       TIMER MODE REGISTER                       */
+/*********************************************************/
+#define  TM0_RUN      0x01  /* Timer 0 enable */
+#define  TM0_TOGGLE   0x02  /* 0, interval mode */
+#define  TM0_OUT_1    0x04  /* Timer 0 Initial TOUT0 value */
+#define  TM1_RUN      0x08  /* Timer 1 enable */
+#define  TM1_TOGGLE   0x10  /* 0, interval mode */
+#define  TM1_OUT_1    0x20  /* Timer 0 Initial TOUT0 value */
+
+
+/*********************************/
+/* INTERRUPT SOURCES             */
+/*********************************/
+#define INT_EXTINT0	0
+#define INT_EXTINT1	1
+#define INT_EXTINT2	2
+#define INT_EXTINT3	3
+#define INT_UARTTX0	4
+#define INT_UARTRX0	5
+#define INT_UARTTX1	6
+#define INT_UARTRX1	7
+#define INT_GDMA0	8
+#define INT_GDMA1	9
+#define INT_TIMER0	10
+#define INT_TIMER1	11
+#define INT_HDLCTXA	12
+#define INT_HDLCRXA	13
+#define INT_HDLCTXB	14
+#define INT_HDLCRXB	15
+#define INT_BDMATX	16
+#define INT_BDMARX	17
+#define INT_MACTX	18
+#define INT_MACRX	19
+#define INT_IIC		20
+#define INT_GLOBAL	21
+#define N_IRQS         (21)
+
+#ifndef __ASSEMBLER__
+struct _irq_handler {
+	void                *m_data;
+	void (*m_func)( void *data);
+};
+
+extern struct _irq_handler IRQ_HANDLER[];
+
+#endif
+
+#endif /* __S3C4510_h */
diff --git a/include/asm-arm/arch-arm925t/sizes.h b/include/asm-arm/arch-arm925t/sizes.h
new file mode 100755
index 0000000..7319bd9
--- /dev/null
+++ b/include/asm-arm/arch-arm925t/sizes.h
@@ -0,0 +1,50 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ */
+/* DO NOT EDIT!! - this file automatically generated
+ *		   from .s file by awk -f s2h.awk
+ */
+/*  Size defintions
+ *  Copyright (C) ARM Limited 1998. All rights reserved.
+ */
+
+#ifndef __sizes_h
+#define __sizes_h			1
+
+/* handy sizes */
+#define SZ_1K				0x00000400
+#define SZ_4K				0x00001000
+#define SZ_8K				0x00002000
+#define SZ_16K				0x00004000
+#define SZ_64K				0x00010000
+#define SZ_128K				0x00020000
+#define SZ_256K				0x00040000
+#define SZ_512K				0x00080000
+
+#define SZ_1M				0x00100000
+#define SZ_2M				0x00200000
+#define SZ_4M				0x00400000
+#define SZ_8M				0x00800000
+#define SZ_16M				0x01000000
+#define SZ_32M				0x02000000
+#define SZ_64M				0x04000000
+#define SZ_128M				0x08000000
+#define SZ_256M				0x10000000
+#define SZ_512M				0x20000000
+
+#define SZ_1G				0x40000000
+#define SZ_2G				0x80000000
+
+#endif	/* __sizes_h */
diff --git a/include/asm-arm/arch-arm926ejs/sizes.h b/include/asm-arm/arch-arm926ejs/sizes.h
new file mode 100755
index 0000000..ef0b99b
--- /dev/null
+++ b/include/asm-arm/arch-arm926ejs/sizes.h
@@ -0,0 +1,51 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA0 2111-1307
+ * USA
+ */
+/* DO NOT EDIT!! - this file automatically generated
+ *		   from .s file by awk -f s2h.awk
+ */
+/*  Size defintions
+ *  Copyright (C) ARM Limited 1998. All rights reserved.
+ */
+
+#ifndef __sizes_h
+#define __sizes_h			1
+
+/* handy sizes */
+#define SZ_1K		0x00000400
+#define SZ_4K		0x00001000
+#define SZ_8K		0x00002000
+#define SZ_16K		0x00004000
+#define SZ_64K		0x00010000
+#define SZ_128K	0x00020000
+#define SZ_256K	0x00040000
+#define SZ_512K	0x00080000
+
+#define SZ_1M		0x00100000
+#define SZ_2M		0x00200000
+#define SZ_4M		0x00400000
+#define SZ_8M		0x00800000
+#define SZ_16M		0x01000000
+#define SZ_32M		0x02000000
+#define SZ_64M		0x04000000
+#define SZ_128M	0x08000000
+#define SZ_256M	0x10000000
+#define SZ_512M	0x20000000
+
+#define SZ_1G		0x40000000
+#define SZ_2G		0x80000000
+
+#endif	/* __sizes_h */
diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
new file mode 100755
index 0000000..97d4704
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
@@ -0,0 +1,762 @@
+/*
+ * (C) Copyright 2003
+ * AT91RM9200 definitions
+ * Author : ATMEL AT91 application group
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91RM9200_H
+#define AT91RM9200_H
+
+typedef volatile unsigned int AT91_REG;		/* Hardware register definition */
+
+/******************************************************************************/
+/*        SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface        */
+/******************************************************************************/
+typedef struct _AT91S_TC
+{
+	AT91_REG	 TC_CCR; 	/* Channel Control Register */
+	AT91_REG	 TC_CMR; 	/* Channel Mode Register */
+	AT91_REG	 Reserved0[2]; 	/*  */
+	AT91_REG	 TC_CV; 	/* Counter Value */
+	AT91_REG	 TC_RA; 	/* Register A */
+	AT91_REG	 TC_RB; 	/* Register B */
+	AT91_REG	 TC_RC; 	/* Register C */
+	AT91_REG	 TC_SR; 	/* Status Register */
+	AT91_REG	 TC_IER; 	/* Interrupt Enable Register */
+	AT91_REG	 TC_IDR; 	/* Interrupt Disable Register */
+	AT91_REG	 TC_IMR; 	/* Interrupt Mask Register */
+} AT91S_TC, *AT91PS_TC;
+
+#define AT91C_TC_TIMER_DIV1_CLOCK	((unsigned int) 0x0 <<  0) /* (TC) MCK/2 */
+#define AT91C_TC_TIMER_DIV2_CLOCK	((unsigned int) 0x1 <<  0) /* (TC) MCK/8 */
+#define AT91C_TC_TIMER_DIV3_CLOCK	((unsigned int) 0x2 <<  0) /* (TC) MCK/32 */
+#define AT91C_TC_TIMER_DIV4_CLOCK	((unsigned int) 0x3 <<  0) /* (TC) MCK/128 */
+#define AT91C_TC_SLOW_CLOCK		((unsigned int) 0x4 <<  0) /* (TC) SLOW CLK */
+#define AT91C_TC_XC0_CLOCK		((unsigned int) 0x5 <<  0) /* (TC) XC0 */
+#define AT91C_TC_XC1_CLOCK		((unsigned int) 0x6 <<  0) /* (TC) XC1 */
+#define AT91C_TC_XC2_CLOCK		((unsigned int) 0x7 <<  0) /* (TC) XC2 */
+#define AT91C_TCB_TC0XC0S_NONE		((unsigned int) 0x1)       /* (TCB) None signal connected to XC0 */
+#define AT91C_TCB_TC1XC1S_NONE		((unsigned int) 0x1 <<  2) /* (TCB) None signal connected to XC1 */
+#define AT91C_TCB_TC2XC2S_NONE		((unsigned int) 0x1 <<  4) /* (TCB) None signal connected to XC2 */
+#define AT91C_TC_CLKDIS			((unsigned int) 0x1 <<  1) /* (TC) Counter Clock Disable Command */
+#define AT91C_TC_SWTRG			((unsigned int) 0x1 <<  2) /* (TC) Software Trigger Command */
+#define AT91C_TC_CLKEN			((unsigned int) 0x1 <<  0) /* (TC) Counter Clock Enable Command */
+
+/******************************************************************************/
+/*                  SOFTWARE API DEFINITION  FOR Usart                        */
+/******************************************************************************/
+typedef struct _AT91S_USART
+{
+	AT91_REG	 US_CR; 	/* Control Register */
+	AT91_REG	 US_MR; 	/* Mode Register */
+	AT91_REG	 US_IER; 	/* Interrupt Enable Register */
+	AT91_REG	 US_IDR; 	/* Interrupt Disable Register */
+	AT91_REG	 US_IMR; 	/* Interrupt Mask Register */
+	AT91_REG	 US_CSR; 	/* Channel Status Register */
+	AT91_REG	 US_RHR; 	/* Receiver Holding Register */
+	AT91_REG	 US_THR; 	/* Transmitter Holding Register */
+	AT91_REG	 US_BRGR; 	/* Baud Rate Generator Register */
+	AT91_REG	 US_RTOR; 	/* Receiver Time-out Register */
+	AT91_REG	 US_TTGR; 	/* Transmitter Time-guard Register */
+	AT91_REG	 Reserved0[5]; 	/*  */
+	AT91_REG	 US_FIDI; 	/* FI_DI_Ratio Register */
+	AT91_REG	 US_NER; 	/* Nb Errors Register */
+	AT91_REG	 US_XXR; 	/* XON_XOFF Register */
+	AT91_REG	 US_IF; 	/* IRDA_FILTER Register */
+	AT91_REG	 Reserved1[44];	/*  */
+	AT91_REG	 US_RPR; 	/* Receive Pointer Register */
+	AT91_REG	 US_RCR; 	/* Receive Counter Register */
+	AT91_REG	 US_TPR; 	/* Transmit Pointer Register */
+	AT91_REG	 US_TCR; 	/* Transmit Counter Register */
+	AT91_REG	 US_RNPR; 	/* Receive Next Pointer Register */
+	AT91_REG	 US_RNCR; 	/* Receive Next Counter Register */
+	AT91_REG	 US_TNPR; 	/* Transmit Next Pointer Register */
+	AT91_REG	 US_TNCR; 	/* Transmit Next Counter Register */
+	AT91_REG	 US_PTCR; 	/* PDC Transfer Control Register */
+	AT91_REG	 US_PTSR; 	/* PDC Transfer Status Register */
+} AT91S_USART, *AT91PS_USART;
+
+/******************************************************************************/
+/*          SOFTWARE API DEFINITION  FOR Clock Generator Controler            */
+/******************************************************************************/
+typedef struct _AT91S_CKGR
+{
+	AT91_REG	 CKGR_MOR; 	/* Main Oscillator Register */
+	AT91_REG	 CKGR_MCFR; 	/* Main Clock  Frequency Register */
+	AT91_REG	 CKGR_PLLAR; 	/* PLL A Register */
+	AT91_REG	 CKGR_PLLBR; 	/* PLL B Register */
+} AT91S_CKGR, *AT91PS_CKGR;
+
+/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
+#define AT91C_CKGR_MOSCEN	((unsigned int) 0x1  <<  0)	/* (CKGR) Main Oscillator Enable */
+#define AT91C_CKGR_OSCTEST	((unsigned int) 0x1  <<  1)	/* (CKGR) Oscillator Test */
+#define AT91C_CKGR_OSCOUNT	((unsigned int) 0xFF <<  8)	/* (CKGR) Main Oscillator Start-up Time */
+
+/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
+#define AT91C_CKGR_MAINF	((unsigned int) 0xFFFF <<  0)	/* (CKGR) Main Clock Frequency */
+#define AT91C_CKGR_MAINRDY	((unsigned int) 0x1 << 16)	/* (CKGR) Main Clock Ready */
+
+/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */
+#define AT91C_CKGR_DIVA		((unsigned int) 0xFF  <<  0)	/* (CKGR) Divider Selected */
+#define AT91C_CKGR_DIVA_0	((unsigned int) 0x0)		/* (CKGR) Divider output is 0 */
+#define AT91C_CKGR_DIVA_BYPASS	((unsigned int) 0x1)		/* (CKGR) Divider is bypassed */
+#define AT91C_CKGR_PLLACOUNT	((unsigned int) 0x3F  <<  8)	/* (CKGR) PLL A Counter */
+#define AT91C_CKGR_OUTA		((unsigned int) 0x3   << 14)	/* (CKGR) PLL A Output Frequency Range */
+#define AT91C_CKGR_OUTA_0	((unsigned int) 0x0   << 14)	/* (CKGR) Please refer to the PLLA datasheet */
+#define AT91C_CKGR_OUTA_1	((unsigned int) 0x1   << 14)	/* (CKGR) Please refer to the PLLA datasheet */
+#define AT91C_CKGR_OUTA_2	((unsigned int) 0x2   << 14)	/* (CKGR) Please refer to the PLLA datasheet */
+#define AT91C_CKGR_OUTA_3	((unsigned int) 0x3   << 14)	/* (CKGR) Please refer to the PLLA datasheet */
+#define AT91C_CKGR_MULA		((unsigned int) 0x7FF << 16)	/* (CKGR) PLL A Multiplier */
+#define AT91C_CKGR_SRCA		((unsigned int) 0x1   << 29)	/* (CKGR) PLL A Source */
+
+/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */
+#define AT91C_CKGR_DIVB		((unsigned int) 0xFF  <<  0)	/* (CKGR) Divider Selected */
+#define AT91C_CKGR_DIVB_0	((unsigned int) 0x0)		/* (CKGR) Divider output is 0 */
+#define AT91C_CKGR_DIVB_BYPASS	((unsigned int) 0x1)		/* (CKGR) Divider is bypassed */
+#define AT91C_CKGR_PLLBCOUNT	((unsigned int) 0x3F  <<  8)	/* (CKGR) PLL B Counter */
+#define AT91C_CKGR_OUTB		((unsigned int) 0x3   << 14)	/* (CKGR) PLL B Output Frequency Range */
+#define AT91C_CKGR_OUTB_0	((unsigned int) 0x0   << 14)	/* (CKGR) Please refer to the PLLB datasheet */
+#define AT91C_CKGR_OUTB_1	((unsigned int) 0x1   << 14)	/* (CKGR) Please refer to the PLLB datasheet */
+#define AT91C_CKGR_OUTB_2	((unsigned int) 0x2   << 14)	/* (CKGR) Please refer to the PLLB datasheet */
+#define AT91C_CKGR_OUTB_3	((unsigned int) 0x3   << 14)	/* (CKGR) Please refer to the PLLB datasheet */
+#define AT91C_CKGR_MULB		((unsigned int) 0x7FF << 16)	/* (CKGR) PLL B Multiplier */
+#define AT91C_CKGR_USB_96M	((unsigned int) 0x1   << 28)	/* (CKGR) Divider for USB Ports */
+#define AT91C_CKGR_USB_PLL	((unsigned int) 0x1   << 29)	/* (CKGR) PLL Use */
+
+/******************************************************************************/
+/*        SOFTWARE API DEFINITION  FOR Parallel Input Output Controler        */
+/******************************************************************************/
+typedef struct _AT91S_PIO
+{
+	AT91_REG	 PIO_PER; 	/* PIO Enable Register */
+	AT91_REG	 PIO_PDR; 	/* PIO Disable Register */
+	AT91_REG	 PIO_PSR; 	/* PIO Status Register */
+	AT91_REG	 Reserved0[1]; 	/*  */
+	AT91_REG	 PIO_OER; 	/* Output Enable Register */
+	AT91_REG	 PIO_ODR; 	/* Output Disable Registerr */
+	AT91_REG	 PIO_OSR; 	/* Output Status Register */
+	AT91_REG	 Reserved1[1]; 	/*  */
+	AT91_REG	 PIO_IFER; 	/* Input Filter Enable Register */
+	AT91_REG	 PIO_IFDR; 	/* Input Filter Disable Register */
+	AT91_REG	 PIO_IFSR; 	/* Input Filter Status Register */
+	AT91_REG	 Reserved2[1]; 	/*  */
+	AT91_REG	 PIO_SODR; 	/* Set Output Data Register */
+	AT91_REG	 PIO_CODR; 	/* Clear Output Data Register */
+	AT91_REG	 PIO_ODSR; 	/* Output Data Status Register */
+	AT91_REG	 PIO_PDSR; 	/* Pin Data Status Register */
+	AT91_REG	 PIO_IER; 	/* Interrupt Enable Register */
+	AT91_REG	 PIO_IDR; 	/* Interrupt Disable Register */
+	AT91_REG	 PIO_IMR; 	/* Interrupt Mask Register */
+	AT91_REG	 PIO_ISR; 	/* Interrupt Status Register */
+	AT91_REG	 PIO_MDER; 	/* Multi-driver Enable Register */
+	AT91_REG	 PIO_MDDR; 	/* Multi-driver Disable Register */
+	AT91_REG	 PIO_MDSR; 	/* Multi-driver Status Register */
+	AT91_REG	 Reserved3[1]; 	/*  */
+	AT91_REG	 PIO_PPUDR; 	/* Pull-up Disable Register */
+	AT91_REG	 PIO_PPUER; 	/* Pull-up Enable Register */
+	AT91_REG	 PIO_PPUSR; 	/* Pad Pull-up Status Register */
+	AT91_REG	 Reserved4[1]; 	/*  */
+	AT91_REG	 PIO_ASR; 	/* Select A Register */
+	AT91_REG	 PIO_BSR; 	/* Select B Register */
+	AT91_REG	 PIO_ABSR; 	/* AB Select Status Register */
+	AT91_REG	 Reserved5[9]; 	/*  */
+	AT91_REG	 PIO_OWER; 	/* Output Write Enable Register */
+	AT91_REG	 PIO_OWDR; 	/* Output Write Disable Register */
+	AT91_REG	 PIO_OWSR; 	/* Output Write Status Register */
+} AT91S_PIO, *AT91PS_PIO;
+
+
+/******************************************************************************/
+/*              SOFTWARE API DEFINITION  FOR Debug Unit                       */
+/******************************************************************************/
+typedef struct _AT91S_DBGU
+{
+	AT91_REG	 DBGU_CR; 	/* Control Register */
+	AT91_REG	 DBGU_MR; 	/* Mode Register */
+	AT91_REG	 DBGU_IER; 	/* Interrupt Enable Register */
+	AT91_REG	 DBGU_IDR; 	/* Interrupt Disable Register */
+	AT91_REG	 DBGU_IMR; 	/* Interrupt Mask Register */
+	AT91_REG	 DBGU_CSR; 	/* Channel Status Register */
+	AT91_REG	 DBGU_RHR; 	/* Receiver Holding Register */
+	AT91_REG	 DBGU_THR; 	/* Transmitter Holding Register */
+	AT91_REG	 DBGU_BRGR; 	/* Baud Rate Generator Register */
+	AT91_REG	 Reserved0[7]; 	/*  */
+	AT91_REG	 DBGU_C1R; 	/* Chip ID1 Register */
+	AT91_REG	 DBGU_C2R; 	/* Chip ID2 Register */
+	AT91_REG	 DBGU_FNTR; 	/* Force NTRST Register */
+	AT91_REG	 Reserved1[45]; 	/*  */
+	AT91_REG	 DBGU_RPR; 	/* Receive Pointer Register */
+	AT91_REG	 DBGU_RCR; 	/* Receive Counter Register */
+	AT91_REG	 DBGU_TPR; 	/* Transmit Pointer Register */
+	AT91_REG	 DBGU_TCR; 	/* Transmit Counter Register */
+	AT91_REG	 DBGU_RNPR; 	/* Receive Next Pointer Register */
+	AT91_REG	 DBGU_RNCR; 	/* Receive Next Counter Register */
+	AT91_REG	 DBGU_TNPR; 	/* Transmit Next Pointer Register */
+	AT91_REG	 DBGU_TNCR; 	/* Transmit Next Counter Register */
+	AT91_REG	 DBGU_PTCR; 	/* PDC Transfer Control Register */
+	AT91_REG	 DBGU_PTSR; 	/* PDC Transfer Status Register */
+} AT91S_DBGU, *AT91PS_DBGU;
+
+/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------  */
+#define AT91C_US_RXRDY		((unsigned int) 0x1 <<  0) /* (DBGU) RXRDY Interrupt */
+#define AT91C_US_TXRDY		((unsigned int) 0x1 <<  1) /* (DBGU) TXRDY Interrupt */
+#define AT91C_US_ENDRX		((unsigned int) 0x1 <<  3) /* (DBGU) End of Receive Transfer Interrupt */
+#define AT91C_US_ENDTX		((unsigned int) 0x1 <<  4) /* (DBGU) End of Transmit Interrupt */
+#define AT91C_US_OVRE		((unsigned int) 0x1 <<  5) /* (DBGU) Overrun Interrupt */
+#define AT91C_US_FRAME		((unsigned int) 0x1 <<  6) /* (DBGU) Framing Error Interrupt */
+#define AT91C_US_PARE		((unsigned int) 0x1 <<  7) /* (DBGU) Parity Error Interrupt */
+#define AT91C_US_TXEMPTY	((unsigned int) 0x1 <<  9) /* (DBGU) TXEMPTY Interrupt */
+#define AT91C_US_TXBUFE		((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
+#define AT91C_US_RXBUFF		((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
+#define AT91C_US_COMM_TX	((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
+#define AT91C_US_COMM_RX	((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
+
+/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------  */
+#define AT91C_US_RSTRX		((unsigned int) 0x1 <<  2) /* (DBGU) Reset Receiver */
+#define AT91C_US_RSTTX		((unsigned int) 0x1 <<  3) /* (DBGU) Reset Transmitter */
+#define AT91C_US_RXEN		((unsigned int) 0x1 <<  4) /* (DBGU) Receiver Enable */
+#define AT91C_US_RXDIS		((unsigned int) 0x1 <<  5) /* (DBGU) Receiver Disable */
+#define AT91C_US_TXEN		((unsigned int) 0x1 <<  6) /* (DBGU) Transmitter Enable */
+#define AT91C_US_TXDIS		((unsigned int) 0x1 <<  7) /* (DBGU) Transmitter Disable */
+
+#define AT91C_US_CLKS_CLOCK	((unsigned int) 0x0 <<  4) /* (USART) Clock */
+#define AT91C_US_CHRL_8_BITS	((unsigned int) 0x3 <<  6) /* (USART) Character Length: 8 bits */
+#define AT91C_US_PAR_NONE	((unsigned int) 0x4 <<  9) /* (DBGU) No Parity */
+#define AT91C_US_NBSTOP_1_BIT	((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
+
+/******************************************************************************/
+/*      SOFTWARE API DEFINITION  FOR Static Memory Controller 2 Interface     */
+/******************************************************************************/
+typedef struct _AT91S_SMC2
+{
+	AT91_REG	 SMC2_CSR[8]; 	/* SMC2 Chip Select Register */
+} AT91S_SMC2, *AT91PS_SMC2;
+
+/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register --------  */
+#define AT91C_SMC2_NWS			((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */
+#define AT91C_SMC2_WSEN			((unsigned int) 0x1 <<  7) /* (SMC2) Wait State Enable */
+#define AT91C_SMC2_TDF			((unsigned int) 0xF <<  8) /* (SMC2) Data Float Time */
+#define AT91C_SMC2_BAT			((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */
+#define AT91C_SMC2_DBW			((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */
+#define AT91C_SMC2_DBW_16		((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */
+#define AT91C_SMC2_DBW_8		((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
+#define AT91C_SMC2_DRP			((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */
+#define AT91C_SMC2_ACSS			((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */
+#define AT91C_SMC2_ACSS_STANDARD	((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
+#define AT91C_SMC2_ACSS_1_CYCLE		((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */
+#define AT91C_SMC2_ACSS_2_CYCLES	((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */
+#define AT91C_SMC2_ACSS_3_CYCLES	((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */
+#define AT91C_SMC2_RWSETUP		((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
+#define AT91C_SMC2_RWHOLD		((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
+
+/******************************************************************************/
+/*           SOFTWARE API DEFINITION  FOR Power Management Controler          */
+/******************************************************************************/
+typedef struct _AT91S_PMC
+{
+	AT91_REG	 PMC_SCER; 	/* System Clock Enable Register */
+	AT91_REG	 PMC_SCDR; 	/* System Clock Disable Register */
+	AT91_REG	 PMC_SCSR; 	/* System Clock Status Register */
+	AT91_REG	 Reserved0[1]; 	/* */
+	AT91_REG	 PMC_PCER; 	/* Peripheral Clock Enable Register */
+	AT91_REG	 PMC_PCDR; 	/* Peripheral Clock Disable Register */
+	AT91_REG	 PMC_PCSR; 	/* Peripheral Clock Status Register */
+	AT91_REG	 Reserved1[5]; 	/* */
+	AT91_REG	 PMC_MCKR; 	/* Master Clock Register */
+	AT91_REG	 Reserved2[3]; 	/* */
+	AT91_REG	 PMC_PCKR[8]; 	/* Programmable Clock Register */
+	AT91_REG	 PMC_IER; 	/* Interrupt Enable Register */
+	AT91_REG	 PMC_IDR; 	/* Interrupt Disable Register */
+	AT91_REG	 PMC_SR; 	/* Status Register */
+	AT91_REG	 PMC_IMR; 	/* Interrupt Mask Register */
+} AT91S_PMC, *AT91PS_PMC;
+
+/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/
+#define AT91C_PMC_PCK		((unsigned int) 0x1 <<  0) /* (PMC) Processor Clock */
+#define AT91C_PMC_UDP		((unsigned int) 0x1 <<  1) /* (PMC) USB Device Port Clock */
+#define AT91C_PMC_MCKUDP	((unsigned int) 0x1 <<  2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */
+#define AT91C_PMC_UHP		((unsigned int) 0x1 <<  4) /* (PMC) USB Host Port Clock */
+#define AT91C_PMC_PCK0		((unsigned int) 0x1 <<  8) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK1		((unsigned int) 0x1 <<  9) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK2		((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK3		((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK4		((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK5		((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK6		((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */
+#define AT91C_PMC_PCK7		((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */
+/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/
+/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/
+/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/
+#define AT91C_PMC_CSS		((unsigned int) 0x3 <<  0) /* (PMC) Programmable Clock Selection */
+#define AT91C_PMC_CSS_SLOW_CLK	((unsigned int) 0x0)       /* (PMC) Slow Clock is selected */
+#define AT91C_PMC_CSS_MAIN_CLK	((unsigned int) 0x1)       /* (PMC) Main Clock is selected */
+#define AT91C_PMC_CSS_PLLA_CLK	((unsigned int) 0x2)       /* (PMC) Clock from PLL A is selected */
+#define AT91C_PMC_CSS_PLLB_CLK	((unsigned int) 0x3)       /* (PMC) Clock from PLL B is selected */
+#define AT91C_PMC_PRES		((unsigned int) 0x7 <<  2) /* (PMC) Programmable Clock Prescaler */
+#define AT91C_PMC_PRES_CLK	((unsigned int) 0x0 <<  2) /* (PMC) Selected clock */
+#define AT91C_PMC_PRES_CLK_2	((unsigned int) 0x1 <<  2) /* (PMC) Selected clock divided by 2 */
+#define AT91C_PMC_PRES_CLK_4	((unsigned int) 0x2 <<  2) /* (PMC) Selected clock divided by 4 */
+#define AT91C_PMC_PRES_CLK_8	((unsigned int) 0x3 <<  2) /* (PMC) Selected clock divided by 8 */
+#define AT91C_PMC_PRES_CLK_16	((unsigned int) 0x4 <<  2) /* (PMC) Selected clock divided by 16 */
+#define AT91C_PMC_PRES_CLK_32	((unsigned int) 0x5 <<  2) /* (PMC) Selected clock divided by 32 */
+#define AT91C_PMC_PRES_CLK_64	((unsigned int) 0x6 <<  2) /* (PMC) Selected clock divided by 64 */
+#define AT91C_PMC_MDIV		((unsigned int) 0x3 <<  8) /* (PMC) Master Clock Division */
+#define AT91C_PMC_MDIV_1	((unsigned int) 0x0 <<  8) /* (PMC) The master clock and the processor clock are the same */
+#define AT91C_PMC_MDIV_2	((unsigned int) 0x1 <<  8) /* (PMC) The processor clock is twice as fast as the master clock */
+#define AT91C_PMC_MDIV_3	((unsigned int) 0x2 <<  8) /* (PMC) The processor clock is three times faster than the master clock */
+#define AT91C_PMC_MDIV_4	((unsigned int) 0x3 <<  8) /* (PMC) The processor clock is four times faster than the master clock */
+/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/
+/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/
+#define AT91C_PMC_MOSCS		((unsigned int) 0x1 <<  0) /* (PMC) MOSC Status/Enable/Disable/Mask */
+#define AT91C_PMC_LOCKA		((unsigned int) 0x1 <<  1) /* (PMC) PLL A Status/Enable/Disable/Mask */
+#define AT91C_PMC_LOCKB		((unsigned int) 0x1 <<  2) /* (PMC) PLL B Status/Enable/Disable/Mask */
+#define AT91C_PMC_MCKRDY	((unsigned int) 0x1 <<  3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK0RDY	((unsigned int) 0x1 <<  8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK1RDY	((unsigned int) 0x1 <<  9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK2RDY	((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK3RDY	((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK4RDY	((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK5RDY	((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK6RDY	((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */
+#define AT91C_PMC_PCK7RDY	((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */
+/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/
+/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
+/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/
+
+/******************************************************************************/
+/*              SOFTWARE API DEFINITION  FOR Ethernet MAC                     */
+/******************************************************************************/
+typedef struct _AT91S_EMAC
+{
+	AT91_REG	 EMAC_CTL; 	/* Network Control Register */
+	AT91_REG	 EMAC_CFG; 	/* Network Configuration Register */
+	AT91_REG	 EMAC_SR; 	/* Network Status Register */
+	AT91_REG	 EMAC_TAR; 	/* Transmit Address Register */
+	AT91_REG	 EMAC_TCR; 	/* Transmit Control Register */
+	AT91_REG	 EMAC_TSR; 	/* Transmit Status Register */
+	AT91_REG	 EMAC_RBQP; 	/* Receive Buffer Queue Pointer */
+	AT91_REG	 Reserved0[1]; 	/*  */
+	AT91_REG	 EMAC_RSR; 	/* Receive Status Register */
+	AT91_REG	 EMAC_ISR; 	/* Interrupt Status Register */
+	AT91_REG	 EMAC_IER; 	/* Interrupt Enable Register */
+	AT91_REG	 EMAC_IDR; 	/* Interrupt Disable Register */
+	AT91_REG	 EMAC_IMR; 	/* Interrupt Mask Register */
+	AT91_REG	 EMAC_MAN; 	/* PHY Maintenance Register */
+	AT91_REG	 Reserved1[2]; 	/*  */
+	AT91_REG	 EMAC_FRA; 	/* Frames Transmitted OK Register */
+	AT91_REG	 EMAC_SCOL; 	/* Single Collision Frame Register */
+	AT91_REG	 EMAC_MCOL; 	/* Multiple Collision Frame Register */
+	AT91_REG	 EMAC_OK; 	/* Frames Received OK Register */
+	AT91_REG	 EMAC_SEQE; 	/* Frame Check Sequence Error Register */
+	AT91_REG	 EMAC_ALE; 	/* Alignment Error Register */
+	AT91_REG	 EMAC_DTE; 	/* Deferred Transmission Frame Register */
+	AT91_REG	 EMAC_LCOL; 	/* Late Collision Register */
+	AT91_REG	 EMAC_ECOL; 	/* Excessive Collision Register */
+	AT91_REG	 EMAC_CSE; 	/* Carrier Sense Error Register */
+	AT91_REG	 EMAC_TUE; 	/* Transmit Underrun Error Register */
+	AT91_REG	 EMAC_CDE; 	/* Code Error Register */
+	AT91_REG	 EMAC_ELR; 	/* Excessive Length Error Register */
+	AT91_REG	 EMAC_RJB; 	/* Receive Jabber Register */
+	AT91_REG	 EMAC_USF; 	/* Undersize Frame Register */
+	AT91_REG	 EMAC_SQEE; 	/* SQE Test Error Register */
+	AT91_REG	 EMAC_DRFC; 	/* Discarded RX Frame Register */
+	AT91_REG	 Reserved2[3]; 	/*  */
+	AT91_REG	 EMAC_HSH; 	/* Hash Address High[63:32] */
+	AT91_REG	 EMAC_HSL; 	/* Hash Address Low[31:0] */
+	AT91_REG	 EMAC_SA1L; 	/* Specific Address 1 Low, First 4 bytes */
+	AT91_REG	 EMAC_SA1H; 	/* Specific Address 1 High, Last 2 bytes */
+	AT91_REG	 EMAC_SA2L; 	/* Specific Address 2 Low, First 4 bytes */
+	AT91_REG	 EMAC_SA2H; 	/* Specific Address 2 High, Last 2 bytes */
+	AT91_REG	 EMAC_SA3L; 	/* Specific Address 3 Low, First 4 bytes */
+	AT91_REG	 EMAC_SA3H; 	/* Specific Address 3 High, Last 2 bytes */
+	AT91_REG	 EMAC_SA4L; 	/* Specific Address 4 Low, First 4 bytes */
+	AT91_REG	 EMAC_SA4H; 	/* Specific Address 4 High, Last 2 bytesr */
+} AT91S_EMAC, *AT91PS_EMAC;
+
+/* -------- EMAC_CTL : (EMAC Offset: 0x0)  --------  */
+#define AT91C_EMAC_LB		((unsigned int) 0x1 <<  0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
+#define AT91C_EMAC_LBL		((unsigned int) 0x1 <<  1) /* (EMAC) Loopback local. */
+#define AT91C_EMAC_RE		((unsigned int) 0x1 <<  2) /* (EMAC) Receive enable. */
+#define AT91C_EMAC_TE		((unsigned int) 0x1 <<  3) /* (EMAC) Transmit enable. */
+#define AT91C_EMAC_MPE		((unsigned int) 0x1 <<  4) /* (EMAC) Management port enable. */
+#define AT91C_EMAC_CSR		((unsigned int) 0x1 <<  5) /* (EMAC) Clear statistics registers. */
+#define AT91C_EMAC_ISR		((unsigned int) 0x1 <<  6) /* (EMAC) Increment statistics registers. */
+#define AT91C_EMAC_WES		((unsigned int) 0x1 <<  7) /* (EMAC) Write enable for statistics registers. */
+#define AT91C_EMAC_BP		((unsigned int) 0x1 <<  8) /* (EMAC) Back pressure. */
+
+/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register --------  */
+#define AT91C_EMAC_SPD		((unsigned int) 0x1 <<  0) /* (EMAC) Speed. */
+#define AT91C_EMAC_FD		((unsigned int) 0x1 <<  1) /* (EMAC) Full duplex. */
+#define AT91C_EMAC_BR		((unsigned int) 0x1 <<  2) /* (EMAC) Bit rate. */
+#define AT91C_EMAC_CAF		((unsigned int) 0x1 <<  4) /* (EMAC) Copy all frames. */
+#define AT91C_EMAC_NBC		((unsigned int) 0x1 <<  5) /* (EMAC) No broadcast. */
+#define AT91C_EMAC_MTI		((unsigned int) 0x1 <<  6) /* (EMAC) Multicast hash enable */
+#define AT91C_EMAC_UNI		((unsigned int) 0x1 <<  7) /* (EMAC) Unicast hash enable. */
+#define AT91C_EMAC_BIG		((unsigned int) 0x1 <<  8) /* (EMAC) Receive 1522 bytes. */
+#define AT91C_EMAC_EAE		((unsigned int) 0x1 <<  9) /* (EMAC) External address match enable. */
+#define AT91C_EMAC_CLK		((unsigned int) 0x3 << 10) /* (EMAC) */
+#define AT91C_EMAC_CLK_HCLK_8	((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */
+#define AT91C_EMAC_CLK_HCLK_16	((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */
+#define AT91C_EMAC_CLK_HCLK_32	((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */
+#define AT91C_EMAC_CLK_HCLK_64	((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */
+#define AT91C_EMAC_RTY		((unsigned int) 0x1 << 12) /* (EMAC) */
+#define AT91C_EMAC_RMII		((unsigned int) 0x1 << 13) /* (EMAC) */
+
+/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register --------  */
+#define AT91C_EMAC_MDIO		((unsigned int) 0x1 <<  1) /* (EMAC) */
+#define AT91C_EMAC_IDLE		((unsigned int) 0x1 <<  2) /* (EMAC) */
+
+/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */
+#define AT91C_EMAC_LEN		((unsigned int) 0x7FF <<  0) /* (EMAC) */
+#define AT91C_EMAC_NCRC		((unsigned int) 0x1 << 15) /* (EMAC) */
+
+/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */
+#define AT91C_EMAC_OVR		((unsigned int) 0x1 <<  0) /* (EMAC) */
+#define AT91C_EMAC_COL		((unsigned int) 0x1 <<  1) /* (EMAC) */
+#define AT91C_EMAC_RLE		((unsigned int) 0x1 <<  2) /* (EMAC) */
+#define AT91C_EMAC_TXIDLE	((unsigned int) 0x1 <<  3) /* (EMAC) */
+#define AT91C_EMAC_BNQ		((unsigned int) 0x1 <<  4) /* (EMAC) */
+#define AT91C_EMAC_COMP		((unsigned int) 0x1 <<  5) /* (EMAC) */
+#define AT91C_EMAC_UND		((unsigned int) 0x1 <<  6) /* (EMAC) */
+
+/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
+#define AT91C_EMAC_BNA		((unsigned int) 0x1 <<  0) /* (EMAC) */
+#define AT91C_EMAC_REC		((unsigned int) 0x1 <<  1) /* (EMAC) */
+#define AT91C_EMAC_RSR_OVR	((unsigned int) 0x1 <<  2) /* (EMAC) */
+
+/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
+#define AT91C_EMAC_DONE		((unsigned int) 0x1 <<  0) /* (EMAC) */
+#define AT91C_EMAC_RCOM		((unsigned int) 0x1 <<  1) /* (EMAC) */
+#define AT91C_EMAC_RBNA		((unsigned int) 0x1 <<  2) /* (EMAC) */
+#define AT91C_EMAC_TOVR		((unsigned int) 0x1 <<  3) /* (EMAC) */
+#define AT91C_EMAC_TUND		((unsigned int) 0x1 <<  4) /* (EMAC) */
+#define AT91C_EMAC_RTRY		((unsigned int) 0x1 <<  5) /* (EMAC) */
+#define AT91C_EMAC_TBRE		((unsigned int) 0x1 <<  6) /* (EMAC) */
+#define AT91C_EMAC_TCOM		((unsigned int) 0x1 <<  7) /* (EMAC) */
+#define AT91C_EMAC_TIDLE	((unsigned int) 0x1 <<  8) /* (EMAC) */
+#define AT91C_EMAC_LINK		((unsigned int) 0x1 <<  9) /* (EMAC) */
+#define AT91C_EMAC_ROVR		((unsigned int) 0x1 << 10) /* (EMAC) */
+#define AT91C_EMAC_HRESP	((unsigned int) 0x1 << 11) /* (EMAC) */
+
+/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
+/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
+/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
+/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
+#define AT91C_EMAC_DATA		((unsigned int) 0xFFFF <<  0) /* (EMAC) */
+#define AT91C_EMAC_CODE		((unsigned int) 0x3  << 16) /* (EMAC) */
+#define AT91C_EMAC_CODE_802_3	((unsigned int) 0x2  << 16) /* (EMAC) Write Operation */
+#define AT91C_EMAC_REGA		((unsigned int) 0x1F << 18) /* (EMAC) */
+#define AT91C_EMAC_PHYA		((unsigned int) 0x1F << 23) /* (EMAC) */
+#define AT91C_EMAC_RW		((unsigned int) 0x3  << 28) /* (EMAC) */
+#define AT91C_EMAC_RW_R		((unsigned int) 0x2  << 28) /* (EMAC) Read Operation */
+#define AT91C_EMAC_RW_W		((unsigned int) 0x1  << 28) /* (EMAC) Write Operation */
+#define AT91C_EMAC_HIGH		((unsigned int) 0x1  << 30) /* (EMAC) */
+#define AT91C_EMAC_LOW		((unsigned int) 0x1  << 31) /* (EMAC) */
+
+/******************************************************************************/
+/*           SOFTWARE API DEFINITION  FOR Serial Parallel Interface           */
+/******************************************************************************/
+typedef struct _AT91S_SPI
+{
+	AT91_REG	 SPI_CR; 	/* Control Register */
+	AT91_REG	 SPI_MR; 	/* Mode Register */
+	AT91_REG	 SPI_RDR; 	/* Receive Data Register */
+	AT91_REG	 SPI_TDR; 	/* Transmit Data Register */
+	AT91_REG	 SPI_SR; 	/* Status Register */
+	AT91_REG	 SPI_IER; 	/* Interrupt Enable Register */
+	AT91_REG	 SPI_IDR; 	/* Interrupt Disable Register */
+	AT91_REG	 SPI_IMR; 	/* Interrupt Mask Register */
+	AT91_REG	 Reserved0[4]; 	/* */
+	AT91_REG	 SPI_CSR[4]; 	/* Chip Select Register */
+	AT91_REG	 Reserved1[48]; /* */
+	AT91_REG	 SPI_RPR; 	/* Receive Pointer Register */
+	AT91_REG	 SPI_RCR; 	/* Receive Counter Register */
+	AT91_REG	 SPI_TPR; 	/* Transmit Pointer Register */
+	AT91_REG	 SPI_TCR; 	/* Transmit Counter Register */
+	AT91_REG	 SPI_RNPR; 	/* Receive Next Pointer Register */
+	AT91_REG	 SPI_RNCR; 	/* Receive Next Counter Register */
+	AT91_REG	 SPI_TNPR; 	/* Transmit Next Pointer Register */
+	AT91_REG	 SPI_TNCR; 	/* Transmit Next Counter Register */
+	AT91_REG	 SPI_PTCR; 	/* PDC Transfer Control Register */
+	AT91_REG	 SPI_PTSR; 	/* PDC Transfer Status Register */
+} AT91S_SPI, *AT91PS_SPI;
+
+/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
+#define AT91C_SPI_SPIEN		((unsigned int) 0x1 <<  0) /* (SPI) SPI Enable */
+#define AT91C_SPI_SPIDIS	((unsigned int) 0x1 <<  1) /* (SPI) SPI Disable */
+#define AT91C_SPI_SWRST		((unsigned int) 0x1 <<  7) /* (SPI) SPI Software reset */
+
+/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
+#define AT91C_SPI_MSTR		((unsigned int) 0x1 <<  0) /* (SPI) Master/Slave Mode */
+#define AT91C_SPI_PS		((unsigned int) 0x1 <<  1) /* (SPI) Peripheral Select */
+#define AT91C_SPI_PS_FIXED	((unsigned int) 0x0 <<  1) /* (SPI) Fixed Peripheral Select */
+#define AT91C_SPI_PS_VARIABLE	((unsigned int) 0x1 <<  1) /* (SPI) Variable Peripheral Select */
+#define AT91C_SPI_PCSDEC	((unsigned int) 0x1 <<  2) /* (SPI) Chip Select Decode */
+#define AT91C_SPI_DIV32		((unsigned int) 0x1 <<  3) /* (SPI) Clock Selection */
+#define AT91C_SPI_MODFDIS	((unsigned int) 0x1 <<  4) /* (SPI) Mode Fault Detection */
+#define AT91C_SPI_LLB		((unsigned int) 0x1 <<  7) /* (SPI) Clock Selection */
+#define AT91C_SPI_PCS		((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */
+#define AT91C_SPI_DLYBCS	((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */
+
+/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
+#define AT91C_SPI_RD		((unsigned int) 0xFFFF <<  0) /* (SPI) Receive Data */
+#define AT91C_SPI_RPCS		((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
+
+/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
+#define AT91C_SPI_TD		((unsigned int) 0xFFFF <<  0) /* (SPI) Transmit Data */
+#define AT91C_SPI_TPCS		((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
+
+/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
+#define AT91C_SPI_RDRF		((unsigned int) 0x1 <<  0) /* (SPI) Receive Data Register Full */
+#define AT91C_SPI_TDRE		((unsigned int) 0x1 <<  1) /* (SPI) Transmit Data Register Empty */
+#define AT91C_SPI_MODF		((unsigned int) 0x1 <<  2) /* (SPI) Mode Fault Error */
+#define AT91C_SPI_OVRES		((unsigned int) 0x1 <<  3) /* (SPI) Overrun Error Status */
+#define AT91C_SPI_SPENDRX	((unsigned int) 0x1 <<  4) /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_SPENDTX	((unsigned int) 0x1 <<  5) /* (SPI) End of Receiver Transfer */
+#define AT91C_SPI_RXBUFF	((unsigned int) 0x1 <<  6) /* (SPI) RXBUFF Interrupt */
+#define AT91C_SPI_TXBUFE	((unsigned int) 0x1 <<  7) /* (SPI) TXBUFE Interrupt */
+#define AT91C_SPI_SPIENS	((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
+
+/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
+/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
+/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
+/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
+#define AT91C_SPI_CPOL		((unsigned int) 0x1  <<  0) /* (SPI) Clock Polarity */
+#define AT91C_SPI_NCPHA		((unsigned int) 0x1  <<  1) /* (SPI) Clock Phase */
+#define AT91C_SPI_BITS		((unsigned int) 0xF  <<  4) /* (SPI) Bits Per Transfer */
+#define AT91C_SPI_BITS_8	((unsigned int) 0x0  <<  4) /* (SPI) 8 Bits Per transfer */
+#define AT91C_SPI_BITS_9	((unsigned int) 0x1  <<  4) /* (SPI) 9 Bits Per transfer */
+#define AT91C_SPI_BITS_10	((unsigned int) 0x2  <<  4) /* (SPI) 10 Bits Per transfer */
+#define AT91C_SPI_BITS_11	((unsigned int) 0x3  <<  4) /* (SPI) 11 Bits Per transfer */
+#define AT91C_SPI_BITS_12	((unsigned int) 0x4  <<  4) /* (SPI) 12 Bits Per transfer */
+#define AT91C_SPI_BITS_13	((unsigned int) 0x5  <<  4) /* (SPI) 13 Bits Per transfer */
+#define AT91C_SPI_BITS_14	((unsigned int) 0x6  <<  4) /* (SPI) 14 Bits Per transfer */
+#define AT91C_SPI_BITS_15	((unsigned int) 0x7  <<  4) /* (SPI) 15 Bits Per transfer */
+#define AT91C_SPI_BITS_16	((unsigned int) 0x8  <<  4) /* (SPI) 16 Bits Per transfer */
+#define AT91C_SPI_SCBR		((unsigned int) 0xFF <<  8) /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBS		((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
+#define AT91C_SPI_DLYBCT	((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
+
+/******************************************************************************/
+/*           SOFTWARE API DEFINITION  FOR Peripheral Data Controller          */
+/******************************************************************************/
+typedef struct _AT91S_PDC
+{
+	AT91_REG	 PDC_RPR; 	/* Receive Pointer Register */
+	AT91_REG	 PDC_RCR; 	/* Receive Counter Register */
+	AT91_REG	 PDC_TPR; 	/* Transmit Pointer Register */
+	AT91_REG	 PDC_TCR; 	/* Transmit Counter Register */
+	AT91_REG	 PDC_RNPR; 	/* Receive Next Pointer Register */
+	AT91_REG	 PDC_RNCR; 	/* Receive Next Counter Register */
+	AT91_REG	 PDC_TNPR; 	/* Transmit Next Pointer Register */
+	AT91_REG	 PDC_TNCR; 	/* Transmit Next Counter Register */
+	AT91_REG	 PDC_PTCR; 	/* PDC Transfer Control Register */
+	AT91_REG	 PDC_PTSR; 	/* PDC Transfer Status Register */
+} AT91S_PDC, *AT91PS_PDC;
+
+/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
+#define AT91C_PDC_RXTEN		((unsigned int) 0x1 <<  0) /* (PDC) Receiver Transfer Enable */
+#define AT91C_PDC_RXTDIS	((unsigned int) 0x1 <<  1) /* (PDC) Receiver Transfer Disable */
+#define AT91C_PDC_TXTEN		((unsigned int) 0x1 <<  8) /* (PDC) Transmitter Transfer Enable */
+#define AT91C_PDC_TXTDIS	((unsigned int) 0x1 <<  9) /* (PDC) Transmitter Transfer Disable */
+/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------  */
+
+/* ========== Register definition ==================================== */
+#define AT91C_SPI_CSR		((AT91_REG *)	0xFFFE0030) /* (SPI) Chip Select Register */
+#define AT91C_PMC_PCER		((AT91_REG *)	0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PMC_PCDR		((AT91_REG *)	0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PMC_SCER		((AT91_REG *)	0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PMC_SCDR		((AT91_REG *)	0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */
+#define AT91C_PIOA_PER		((AT91_REG *)	0xFFFFF400) /* (PIOA) PIO Enable Register */
+#define AT91C_PIOA_PDR		((AT91_REG *)	0xFFFFF404) /* (PIOA) PIO Disable Register */
+#define AT91C_PIOA_PSR		((AT91_REG *)	0xFFFFF408) /* (PIOA) PIO Status Register */
+#define AT91C_PIOA_OER		((AT91_REG *)	0xFFFFF410) /* (PIOA) PIO Output Enable Register */
+#define AT91C_PIOA_ODR		((AT91_REG *)	0xFFFFF414) /* (PIOA) PIO Output Disable Register */
+#define AT91C_PIOA_OSR		((AT91_REG *)	0xFFFFF418) /* (PIOA) PIO Output Status Register */
+#define AT91C_PIOA_IFER		((AT91_REG *)	0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */
+#define AT91C_PIOA_IFDR		((AT91_REG *)	0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */
+#define AT91C_PIOA_IFSR		((AT91_REG *)	0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */
+#define AT91C_PIOA_SODR		((AT91_REG *)	0xFFFFF430) /* (PIOA) PIO Set Output Data Register */
+#define AT91C_PIOA_CODR		((AT91_REG *)	0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */
+#define AT91C_PIOA_ODSR		((AT91_REG *)	0xFFFFF438) /* (PIOA) PIO Output Data Status Register */
+#define AT91C_PIOA_PDSR		((AT91_REG *)	0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */
+#define AT91C_PIOA_IER		((AT91_REG *)	0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */
+#define AT91C_PIOA_IDR		((AT91_REG *)	0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */
+#define AT91C_PIOA_IMR		((AT91_REG *)	0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */
+#define AT91C_PIOA_ISR		((AT91_REG *)	0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */
+#define AT91C_PIOA_MDER		((AT91_REG *)	0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */
+#define AT91C_PIOA_MDDR		((AT91_REG *)	0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */
+#define AT91C_PIOA_MDSR		((AT91_REG *)	0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */
+#define AT91C_PIOA_PUDR		((AT91_REG *)	0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */
+#define AT91C_PIOA_PUER		((AT91_REG *)	0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */
+#define AT91C_PIOA_PUSR		((AT91_REG *)	0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */
+#define AT91C_PIOA_ASR		((AT91_REG *)	0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */
+#define AT91C_PIOA_BSR		((AT91_REG *)	0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */
+#define AT91C_PIOA_ABSR		((AT91_REG *)	0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */
+#define AT91C_PIOA_OWER		((AT91_REG *)	0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */
+#define AT91C_PIOA_OWDR		((AT91_REG *)	0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */
+#define AT91C_PIOA_OWSR		((AT91_REG *)	0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */
+#define AT91C_PIOB_PDR		((AT91_REG *)	0xFFFFF604) /* (PIOB) PIO Disable Register */
+
+#define AT91C_PIO_PA30		((unsigned int) 1 << 30)	/* Pin Controlled by PA30 */
+#define AT91C_PIO_PC0		((unsigned int) 1 <<  0)	/* Pin Controlled by PC0 */
+#define AT91C_PC0_BFCK		((unsigned int) AT91C_PIO_PC0)	/* Burst Flash Clock */
+#define AT91C_PA30_DRXD		((unsigned int) AT91C_PIO_PA30)	/* DBGU Debug Receive Data */
+#define AT91C_PIO_PA31		((unsigned int) 1 << 31)	/* Pin Controlled by PA31 */
+#define AT91C_PA25_TWD		((unsigned int) 1 << 25)
+#define AT91C_PA26_TWCK		((unsigned int) 1 << 26)
+#define AT91C_PA31_DTXD		((unsigned int) AT91C_PIO_PA31)	/* DBGU Debug Transmit Data */
+#define AT91C_PIO_PA17		((unsigned int) 1 << 17)	/* Pin Controlled by PA17 */
+#define AT91C_PA17_TXD0		AT91C_PIO_PA17			/* USART0 Transmit Data */
+#define AT91C_PIO_PA18		((unsigned int) 1 << 18)	/* Pin Controlled by PA18 */
+#define AT91C_PA18_RXD0		AT91C_PIO_PA18			/* USART0 Receive Data */
+#define AT91C_PIO_PB20		((unsigned int) 1 << 20)	/* Pin Controlled by PB20 */
+#define AT91C_PB20_RXD1		AT91C_PIO_PB20			/* USART1 Receive Data */
+#define AT91C_PIO_PB21		((unsigned int) 1 << 21)	/* Pin Controlled by PB21 */
+#define AT91C_PB21_TXD1		AT91C_PIO_PB21			/* USART1 Transmit Data */
+
+#define AT91C_ID_SYS		((unsigned int)  1) /* System Peripheral */
+#define AT91C_ID_PIOA		((unsigned int)  2) /* PIO port A */
+#define AT91C_ID_PIOB		((unsigned int)  3) /* PIO port B */
+#define AT91C_ID_PIOC		((unsigned int)  4) /* PIO port C */
+#define AT91C_ID_USART0		((unsigned int)  6) /* USART 0 */
+#define AT91C_ID_USART1		((unsigned int)  7) /* USART 1 */
+#define AT91C_ID_TWI		((unsigned int) 12) /* Two Wire Interface */
+#define AT91C_ID_SPI		((unsigned int) 13) /* Serial Peripheral Interface */
+#define AT91C_ID_TC0		((unsigned int) 17) /* Timer Counter 0 */
+#define AT91C_ID_UHP		((unsigned int) 23) /* OHCI USB Host Port */
+#define AT91C_ID_EMAC		((unsigned int) 24) /* Ethernet MAC */
+
+#define AT91C_PIO_PC1		((unsigned int) 1 <<  1)	/* Pin Controlled by PC1 */
+#define AT91C_PC1_BFRDY_SMOE	((unsigned int) AT91C_PIO_PC1)	/*  Burst Flash Ready */
+#define AT91C_PIO_PC3		((unsigned int) 1 <<  3)	/* Pin Controlled by PC3 */
+#define AT91C_PC3_BFBAA_SMWE	((unsigned int) AT91C_PIO_PC3)	/*  Burst Flash Address Advance / SmartMedia Write Enable */
+#define AT91C_PIO_PC2		((unsigned int) 1 <<  2)	/* Pin Controlled by PC2 */
+#define AT91C_PC2_BFAVD		((unsigned int) AT91C_PIO_PC2)	/*  Burst Flash Address Valid */
+#define AT91C_PIO_PB1		((unsigned int) 1 <<  1)	/* Pin Controlled by PB1 */
+
+#define AT91C_PIO_PA23		((unsigned int) 1 << 23)	/* Pin Controlled by PA23 */
+#define AT91C_PA23_TXD2		((unsigned int) AT91C_PIO_PA23)	/* USART 2 Transmit Data */
+
+#define AT91C_PIO_PA0		((unsigned int) 1 <<  0)	/* Pin Controlled by PA0 */
+#define AT91C_PA0_MISO		((unsigned int) AT91C_PIO_PA0)	/* SPI Master In Slave */
+#define AT91C_PIO_PA1		((unsigned int) 1 <<  1)	/* Pin Controlled by PA1 */
+#define AT91C_PA1_MOSI		((unsigned int) AT91C_PIO_PA1)	/* SPI Master Out Slave */
+#define AT91C_PIO_PA2		((unsigned int) 1 <<  2)	/* Pin Controlled by PA2 */
+#define AT91C_PA2_SPCK		((unsigned int) AT91C_PIO_PA2)	/* SPI Serial Clock */
+#define AT91C_PIO_PA3		((unsigned int) 1 <<  3)	/* Pin Controlled by PA3 */
+#define AT91C_PA3_NPCS0		((unsigned int) AT91C_PIO_PA3)	/* SPI Peripheral Chip Select 0 */
+#define AT91C_PIO_PA4		((unsigned int) 1 <<  4)	/* Pin Controlled by PA4 */
+#define AT91C_PA4_NPCS1		((unsigned int) AT91C_PIO_PA4)	/* SPI Peripheral Chip Select 1 */
+#define AT91C_PIO_PA5		((unsigned int) 1 <<  5)	/* Pin Controlled by PA5 */
+#define AT91C_PA5_NPCS2		((unsigned int) AT91C_PIO_PA5)	/* SPI Peripheral Chip Select 2 */
+#define AT91C_PIO_PA6		((unsigned int) 1 <<  6)	/* Pin Controlled by PA6 */
+#define AT91C_PA6_NPCS3		((unsigned int) AT91C_PIO_PA6)	/* SPI Peripheral Chip Select 3 */
+
+#define AT91C_PIO_PA16		((unsigned int) 1 << 16)	/* Pin Controlled by PA16 */
+#define AT91C_PA16_EMDIO	((unsigned int) AT91C_PIO_PA16)	/* Ethernet MAC Management Data Input/Output */
+#define AT91C_PIO_PA15		((unsigned int) 1 << 15)	/* Pin Controlled by PA15 */
+#define AT91C_PA15_EMDC		((unsigned int) AT91C_PIO_PA15)	/* Ethernet MAC Management Data Clock */
+#define AT91C_PIO_PA14		((unsigned int) 1 << 14)	/* Pin Controlled by PA14 */
+#define AT91C_PA14_ERXER	((unsigned int) AT91C_PIO_PA14)	/* Ethernet MAC Receive Error */
+#define AT91C_PIO_PA13		((unsigned int) 1 << 13)	/* Pin Controlled by PA13 */
+#define AT91C_PA13_ERX1		((unsigned int) AT91C_PIO_PA13)	/* Ethernet MAC Receive Data 1 */
+#define AT91C_PIO_PA12		((unsigned int) 1 << 12)	/* Pin Controlled by PA12 */
+#define AT91C_PA12_ERX0		((unsigned int) AT91C_PIO_PA12)	/* Ethernet MAC Receive Data 0 */
+#define AT91C_PIO_PA11		((unsigned int) 1 << 11)	/* Pin Controlled by PA11 */
+#define AT91C_PA11_ECRS_ECRSDV	((unsigned int) AT91C_PIO_PA11)	/* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
+#define AT91C_PIO_PA10		((unsigned int) 1 << 10)	/* Pin Controlled by PA10 */
+#define AT91C_PA10_ETX1		((unsigned int) AT91C_PIO_PA10)	/* Ethernet MAC Transmit Data 1 */
+#define AT91C_PIO_PA9		((unsigned int) 1 <<  9)	/* Pin Controlled by PA9 */
+#define AT91C_PA9_ETX0		((unsigned int) AT91C_PIO_PA9)	/* Ethernet MAC Transmit Data 0 */
+#define AT91C_PIO_PA8		((unsigned int) 1 <<  8)	/* Pin Controlled by PA8 */
+#define AT91C_PA8_ETXEN		((unsigned int) AT91C_PIO_PA8)	/* Ethernet MAC Transmit Enable */
+#define AT91C_PIO_PA7		((unsigned int) 1 <<  7)	/* Pin Controlled by PA7 */
+#define AT91C_PA7_ETXCK_EREFCK	((unsigned int) AT91C_PIO_PA7)	/* Ethernet MAC Transmit Clock/Reference Clock */
+
+#define AT91C_PIO_PB3		((unsigned int) 1 <<  3)	/* Pin Controlled by PB3 */
+#define AT91C_PIO_PB4		((unsigned int) 1 <<  4)	/* Pin Controlled by PB4 */
+#define AT91C_PIO_PB5		((unsigned int) 1 <<  5)	/* Pin Controlled by PB5 */
+#define AT91C_PIO_PB6		((unsigned int) 1 <<  6)	/* Pin Controlled by PB6 */
+#define AT91C_PIO_PB7		((unsigned int) 1 <<  7)	/* Pin Controlled by PB7 */
+#define AT91C_PIO_PB25		((unsigned int) 1 << 25)	/* Pin Controlled by PB25 */
+#define AT91C_PB25_DSR1		((unsigned int) AT91C_PIO_PB25)	/* USART 1 Data Set ready */
+#define AT91C_PB25_EF100	((unsigned int) AT91C_PIO_PB25)	/* Ethernet MAC Force 100 Mbits */
+#define AT91C_PIO_PB19		((unsigned int) 1 << 19)	/* Pin Controlled by PB19 */
+#define AT91C_PB19_DTR1		((unsigned int) AT91C_PIO_PB19)	/* USART 1 Data Terminal ready */
+#define AT91C_PB19_ERXCK	((unsigned int) AT91C_PIO_PB19)	/* Ethernet MAC Receive Clock */
+#define AT91C_PIO_PB18		((unsigned int) 1 << 18)	/* Pin Controlled by PB18 */
+#define AT91C_PB18_RI1		((unsigned int) AT91C_PIO_PB18)	/* USART 1 Ring Indicator */
+#define AT91C_PB18_ECOL		((unsigned int) AT91C_PIO_PB18)	/* Ethernet MAC Collision Detected */
+#define AT91C_PIO_PB17		((unsigned int) 1 << 17)	/* Pin Controlled by PB17 */
+#define AT91C_PB17_RF2		((unsigned int) AT91C_PIO_PB17)	/* SSC Receive Frame Sync 2 */
+#define AT91C_PB17_ERXDV	((unsigned int) AT91C_PIO_PB17)	/* Ethernet MAC Receive Data Valid */
+#define AT91C_PIO_PB16		((unsigned int) 1 << 16)	/* Pin Controlled by PB16 */
+#define AT91C_PB16_RK2		((unsigned int) AT91C_PIO_PB16)	/* SSC Receive Clock 2 */
+#define AT91C_PB16_ERX3		((unsigned int) AT91C_PIO_PB16)	/* Ethernet MAC Receive Data 3 */
+#define AT91C_PIO_PB15		((unsigned int) 1 << 15)	/* Pin Controlled by PB15 */
+#define AT91C_PB15_RD2		((unsigned int) AT91C_PIO_PB15)	/* SSC Receive Data 2 */
+#define AT91C_PB15_ERX2		((unsigned int) AT91C_PIO_PB15)	/* Ethernet MAC Receive Data 2 */
+#define AT91C_PIO_PB14		((unsigned int) 1 << 14)	/* Pin Controlled by PB14 */
+#define AT91C_PB14_TD2		((unsigned int) AT91C_PIO_PB14)	/* SSC Transmit Data 2 */
+#define AT91C_PB14_ETXER	((unsigned int) AT91C_PIO_PB14)	/* Ethernet MAC Transmikt Coding Error */
+#define AT91C_PIO_PB13		((unsigned int) 1 << 13)	/* Pin Controlled by PB13 */
+#define AT91C_PB13_TK2		((unsigned int) AT91C_PIO_PB13)	/* SSC Transmit Clock 2 */
+#define AT91C_PB13_ETX3		((unsigned int) AT91C_PIO_PB13)	/* Ethernet MAC Transmit Data 3 */
+#define AT91C_PIO_PB12		((unsigned int) 1 << 12)	/* Pin Controlled by PB12 */
+#define AT91C_PB12_TF2		((unsigned int) AT91C_PIO_PB12)	/* SSC Transmit Frame Sync 2 */
+#define AT91C_PB12_ETX2		((unsigned int) AT91C_PIO_PB12)	/* Ethernet MAC Transmit Data 2 */
+
+#define AT91C_PIOB_BSR		((AT91_REG *)	0xFFFFF674)	/* (PIOB) Select B Register */
+#define AT91C_PIOB_PDR		((AT91_REG *)	0xFFFFF604)	/* (PIOB) PIO Disable Register */
+
+#define AT91C_EBI_CS3A_SMC_SmartMedia	((unsigned int) 0x1 <<  3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
+#define AT91C_SMC2_ACSS_STANDARD	((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
+#define AT91C_SMC2_DBW_8	((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
+#define AT91C_SMC2_WSEN		((unsigned int) 0x1 <<  7) /* (SMC2) Wait State Enable */
+#define AT91C_PIOC_ASR		((AT91_REG *)	0xFFFFF870) /* (PIOC) Select A Register */
+#define AT91C_PIOC_SODR		((AT91_REG *)	0xFFFFF830) /* (PIOC) Set Output Data Register */
+#define AT91C_PIOC_CODR		((AT91_REG *)	0xFFFFF834) /* (PIOC) Clear Output Data Register */
+#define AT91C_PIOC_PDSR		((AT91_REG *)	0xFFFFF83C) /* (PIOC) Pin Data Status Register */
+
+#define AT91C_BASE_SPI		((AT91PS_SPI)	0xFFFE0000) /* (SPI) Base Address */
+#define AT91C_BASE_EMAC		((AT91PS_EMAC)	0xFFFBC000) /* (EMAC) Base Address */
+#define AT91C_BASE_PMC		((AT91PS_PMC)	0xFFFFFC00) /* (PMC) Base Address */
+#define AT91C_BASE_TC0		((AT91PS_TC)	0xFFFA0000) /* (TC0) Base Address */
+#define AT91C_BASE_DBGU		((AT91PS_DBGU)	0xFFFFF200) /* (DBGU) Base Address */
+#define AT91C_BASE_CKGR		((AT91PS_CKGR)	0xFFFFFC20) /* (CKGR) Base Address */
+#define AT91C_BASE_PIOC		((AT91PS_PIO)	0xFFFFF800) /* (PIOC) Base Address */
+#define AT91C_BASE_PIOB		((AT91PS_PIO)	0xFFFFF600) /* (PIOB) Base Address */
+#define AT91C_BASE_PIOA		((AT91PS_PIO)	0xFFFFF400) /* (PIOA) Base Address */
+#define AT91C_EBI_CSA		((AT91_REG *)	0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
+#define AT91C_BASE_SMC2		((AT91PS_SMC2)	0xFFFFFF70) /* (SMC2) Base Address */
+#define AT91C_BASE_US0		((AT91PS_USART)	0xFFFC0000) /* (US0) Base Address */
+#define AT91C_BASE_US1		((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
+#define AT91C_TCB0_BMR		((AT91_REG *)	0xFFFA00C4) /* (TCB0) TC Block Mode Register */
+#define AT91C_TCB0_BCR		((AT91_REG *)	0xFFFA00C0) /* (TCB0) TC Block Control Register */
+#define AT91C_PIOC_PDR		((AT91_REG *)	0xFFFFF804) /* (PIOC) PIO Disable Register */
+#define AT91C_PIOC_PER		((AT91_REG *)	0xFFFFF800) /* (PIOC) PIO Enable Register */
+#define AT91C_PIOC_ODR  	((AT91_REG *)	0xFFFFF814) /* (PIOC) Output Disable Registerr */
+#define AT91C_PIOB_PER		((AT91_REG *)	0xFFFFF600) /* (PIOB) PIO Enable Register */
+#define AT91C_PIOB_ODR		((AT91_REG *)	0xFFFFF614) /* (PIOB) Output Disable Registerr */
+#define AT91C_PIOB_PDSR		((AT91_REG *)	0xFFFFF63C) /* (PIOB) Pin Data Status Register */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
new file mode 100755
index 0000000..8bb0c47
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -0,0 +1,77 @@
+/*
+ * linux/include/asm-arm/arch-at91/hardware.h
+ *
+ *  Copyright (C) 2003 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+
+#ifndef __ASSEMBLY__
+#include "AT91RM9200.h"
+#else
+#include "AT91RM9200_inc.h"
+#endif
+
+/* Virtual and Physical base address for system peripherals */
+#define AT91_SYS_BASE		0xFFFFF000 /*4K */
+
+/* Virtual and Physical base addresses of user peripherals */
+#define AT91_SPI_BASE		0xFFFE0000 /*16K */
+#define AT91_SSC2_BASE		0xFFFD8000 /*16K */
+#define AT91_SSC1_BASE		0xFFFD4000 /*16K */
+#define AT91_SSC0_BASE		0xFFFD0000 /*16K */
+#define AT91_USART3_BASE	0xFFFCC000 /*16K */
+#define AT91_USART2_BASE	0xFFFC8000 /*16K */
+#define AT91_USART1_BASE	0xFFFC4000 /*16K */
+#define AT91_USART0_BASE	0xFFFC0000 /*16K */
+#define AT91_EMAC_BASE		0xFFFBC000 /*16K */
+#define AT91_TWI_BASE		0xFFFB8000 /*16K */
+#define AT91_MCI_BASE		0xFFFB4000 /*16K */
+#define AT91_UDP_BASE		0xFFFB0000 /*16K */
+#define AT91_TCB1_BASE		0xFFFA4000 /*16K */
+#define AT91_TCB0_BASE		0xFFFA0000 /*16K */
+
+#define AT91_USB_HOST_BASE	0x00300000
+
+/*
+ * Where in virtual memory the IO devices (timers, system controllers
+ * and so on)
+ */
+#define AT91_IO_BASE		0xF0000000	/* Virt/Phys Address of IO */
+
+/* FLASH */
+#define AT91_FLASH_BASE		0x10000000	/* NCS0 */
+
+/* SDRAM */
+#define AT91_SDRAM_BASE		0x20000000	/* NCS1 */
+
+/* SmartMedia */
+#define AT91_SMARTMEDIA_BASE	0x40000000	/* NCS3 */
+
+/* Definition of interrupt priority levels */
+#define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST
+#define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1)
+#define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2)
+#define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3)
+#define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4)
+#define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5)
+#define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6)
+#define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGEST
+
+#endif
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
new file mode 100755
index 0000000..318de22
--- /dev/null
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -0,0 +1,577 @@
+#ifndef _IMX_REGS_H
+#define _IMX_REGS_H
+/* ------------------------------------------------------------------------
+ *  Motorola IMX system registers
+ * ------------------------------------------------------------------------
+ *
+ */
+
+# ifndef __ASSEMBLY__
+#  define __REG(x)	(*((volatile u32 *)(x)))
+# define __REG2(x,y)	\
+	( __builtin_constant_p(y) ? (__REG((x) + (y))) \
+			  : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
+# else
+#  define __REG(x) (x)
+#  define __REG2(x,y) ((x)+(y))
+#endif
+
+#define IMX_IO_BASE		0x00200000
+
+/*
+ *  Register BASEs, based on OFFSETs
+ *
+ */
+#define IMX_AIPI1_BASE             (0x00000 + IMX_IO_BASE)
+#define IMX_WDT_BASE               (0x01000 + IMX_IO_BASE)
+#define IMX_TIM1_BASE              (0x02000 + IMX_IO_BASE)
+#define IMX_TIM2_BASE              (0x03000 + IMX_IO_BASE)
+#define IMX_RTC_BASE               (0x04000 + IMX_IO_BASE)
+#define IMX_LCDC_BASE              (0x05000 + IMX_IO_BASE)
+#define IMX_UART1_BASE             (0x06000 + IMX_IO_BASE)
+#define IMX_UART2_BASE             (0x07000 + IMX_IO_BASE)
+#define IMX_PWM_BASE               (0x08000 + IMX_IO_BASE)
+#define IMX_DMAC_BASE              (0x09000 + IMX_IO_BASE)
+#define IMX_AIPI2_BASE             (0x10000 + IMX_IO_BASE)
+#define IMX_SIM_BASE               (0x11000 + IMX_IO_BASE)
+#define IMX_USBD_BASE              (0x12000 + IMX_IO_BASE)
+#define IMX_SPI1_BASE              (0x13000 + IMX_IO_BASE)
+#define IMX_MMC_BASE               (0x14000 + IMX_IO_BASE)
+#define IMX_ASP_BASE               (0x15000 + IMX_IO_BASE)
+#define IMX_BTA_BASE               (0x16000 + IMX_IO_BASE)
+#define IMX_I2C_BASE               (0x17000 + IMX_IO_BASE)
+#define IMX_SSI_BASE               (0x18000 + IMX_IO_BASE)
+#define IMX_SPI2_BASE              (0x19000 + IMX_IO_BASE)
+#define IMX_MSHC_BASE              (0x1A000 + IMX_IO_BASE)
+#define IMX_PLL_BASE               (0x1B000 + IMX_IO_BASE)
+#define IMX_SYSCTRL_BASE           (0x1B800 + IMX_IO_BASE)
+#define IMX_GPIO_BASE              (0x1C000 + IMX_IO_BASE)
+#define IMX_EIM_BASE               (0x20000 + IMX_IO_BASE)
+#define IMX_SDRAMC_BASE            (0x21000 + IMX_IO_BASE)
+#define IMX_MMA_BASE               (0x22000 + IMX_IO_BASE)
+#define IMX_AITC_BASE              (0x23000 + IMX_IO_BASE)
+#define IMX_CSI_BASE               (0x24000 + IMX_IO_BASE)
+
+/* Watchdog Registers*/
+
+#define WCR  __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
+#define WSR  __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */
+#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register  */
+
+/* SYSCTRL Registers */
+#define SIDR   __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register		    */
+#define FMCR   __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
+#define GPCR   __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */
+
+/* Chip Select Registers */
+#define CS0U __REG(IMX_EIM_BASE)        /* Chip Select 0 Upper Register */
+#define CS0L __REG(IMX_EIM_BASE + 0x4)  /* Chip Select 0 Lower Register */
+#define CS1U __REG(IMX_EIM_BASE + 0x8)  /* Chip Select 1 Upper Register */
+#define CS1L __REG(IMX_EIM_BASE + 0xc)  /* Chip Select 1 Lower Register */
+#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
+#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
+#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
+#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
+#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
+#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
+#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
+#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
+#define EIM  __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
+
+/* SDRAM controller registers */
+
+#define SDCTL0 __REG(IMX_SDRAMC_BASE)        /* SDRAM 0 Control Register */
+#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4)  /* SDRAM 1 Control Register */
+#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */
+#define SDRST  __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */
+
+/* PLL registers */
+#define CSCR   __REG(IMX_PLL_BASE)        /* Clock Source Control Register */
+#define MPCTL0 __REG(IMX_PLL_BASE + 0x4)  /* MCU PLL Control Register 0 */
+#define MPCTL1 __REG(IMX_PLL_BASE + 0x8)  /* MCU PLL and System Clock Register 1 */
+#define SPCTL0 __REG(IMX_PLL_BASE + 0xc)  /* System PLL Control Register 0 */
+#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
+#define PCDR   __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
+
+#define CSCR_MPLL_RESTART (1<<21)
+
+/*
+ *  GPIO Module and I/O Multiplexer
+ *  x = 0..3 for reg_A, reg_B, reg_C, reg_D
+ */
+#define DDIR(x)    __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
+#define OCR1(x)    __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
+#define OCR2(x)    __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
+#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
+#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
+#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
+#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
+#define DR(x)      __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
+#define GIUS(x)    __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
+#define SSR(x)     __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
+#define ICR1(x)    __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
+#define ICR2(x)    __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
+#define IMR(x)     __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
+#define ISR(x)     __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
+#define GPR(x)     __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
+#define SWR(x)     __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
+#define PUEN(x)    __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
+
+#define GPIO_PIN_MASK 0x1f
+#define GPIO_PORT_MASK (0x3 << 5)
+
+#define GPIO_PORTA (0<<5)
+#define GPIO_PORTB (1<<5)
+#define GPIO_PORTC (2<<5)
+#define GPIO_PORTD (3<<5)
+
+#define GPIO_OUT   (1<<7)
+#define GPIO_IN    (0<<7)
+#define GPIO_PUEN  (1<<8)
+
+#define GPIO_PF    (0<<9)
+#define GPIO_AF    (1<<9)
+
+#define GPIO_OCR_MASK (3<<10)
+#define GPIO_AIN   (0<<10)
+#define GPIO_BIN   (1<<10)
+#define GPIO_CIN   (2<<10)
+#define GPIO_GPIO  (3<<10)
+
+#define GPIO_AOUT  (1<<12)
+#define GPIO_BOUT  (1<<13)
+
+/* assignements for GPIO alternate/primary functions */
+
+/* FIXME: This list is not completed. The correct directions are
+ * missing on some (many) pins
+ */
+#define PA0_PF_A24           ( GPIO_PORTA | GPIO_PF | 0 )
+#define PA0_AIN_SPI2_CLK     ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
+#define PA0_AF_ETMTRACESYNC  ( GPIO_PORTA | GPIO_AF | 0 )
+#define PA1_AOUT_SPI2_RXD    ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
+#define PA1_PF_TIN           ( GPIO_PORTA | GPIO_PF | 1 )
+#define PA2_PF_PWM0          ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
+#define PA3_PF_CSI_MCLK      ( GPIO_PORTA | GPIO_PF | 3 )
+#define PA4_PF_CSI_D0        ( GPIO_PORTA | GPIO_PF | 4 )
+#define PA5_PF_CSI_D1        ( GPIO_PORTA | GPIO_PF | 5 )
+#define PA6_PF_CSI_D2        ( GPIO_PORTA | GPIO_PF | 6 )
+#define PA7_PF_CSI_D3        ( GPIO_PORTA | GPIO_PF | 7 )
+#define PA8_PF_CSI_D4        ( GPIO_PORTA | GPIO_PF | 8 )
+#define PA9_PF_CSI_D5        ( GPIO_PORTA | GPIO_PF | 9 )
+#define PA10_PF_CSI_D6       ( GPIO_PORTA | GPIO_PF | 10 )
+#define PA11_PF_CSI_D7       ( GPIO_PORTA | GPIO_PF | 11 )
+#define PA12_PF_CSI_VSYNC    ( GPIO_PORTA | GPIO_PF | 12 )
+#define PA13_PF_CSI_HSYNC    ( GPIO_PORTA | GPIO_PF | 13 )
+#define PA14_PF_CSI_PIXCLK   ( GPIO_PORTA | GPIO_PF | 14 )
+#define PA15_PF_I2C_SDA      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
+#define PA16_PF_I2C_SCL      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
+#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
+#define PA17_AIN_SPI2_SS     ( GPIO_PORTA | GPIO_AIN | 17 )
+#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
+#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
+#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
+#define PA21_PF_A0           ( GPIO_PORTA | GPIO_PF | 21 )
+#define PA22_PF_CS4          ( GPIO_PORTA | GPIO_PF | 22 )
+#define PA23_PF_CS5          ( GPIO_PORTA | GPIO_PF | 23 )
+#define PA24_PF_A16          ( GPIO_PORTA | GPIO_PF | 24 )
+#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
+#define PA25_PF_A17          ( GPIO_PORTA | GPIO_PF | 25 )
+#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
+#define PA26_PF_A18          ( GPIO_PORTA | GPIO_PF | 26 )
+#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
+#define PA27_PF_A19          ( GPIO_PORTA | GPIO_PF | 27 )
+#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
+#define PA28_PF_A20          ( GPIO_PORTA | GPIO_PF | 28 )
+#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
+#define PA29_PF_A21          ( GPIO_PORTA | GPIO_PF | 29 )
+#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
+#define PA30_PF_A22          ( GPIO_PORTA | GPIO_PF | 30 )
+#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
+#define PA31_PF_A23          ( GPIO_PORTA | GPIO_PF | 31 )
+#define PA31_AF_ETMTRACECLK  ( GPIO_PORTA | GPIO_AF | 31 )
+#define PB8_PF_SD_DAT0       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
+#define PB8_AF_MS_PIO        ( GPIO_PORTB | GPIO_AF | 8 )
+#define PB9_PF_SD_DAT1       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 9 )
+#define PB9_AF_MS_PI1        ( GPIO_PORTB | GPIO_AF | 9 )
+#define PB10_PF_SD_DAT2      ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 10 )
+#define PB10_AF_MS_SCLKI     ( GPIO_PORTB | GPIO_AF | 10 )
+#define PB11_PF_SD_DAT3      ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 11 )
+#define PB11_AF_MS_SDIO      ( GPIO_PORTB | GPIO_AF | 11 )
+#define PB12_PF_SD_CLK       ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 )
+#define PB12_AF_MS_SCLK0     ( GPIO_PORTB | GPIO_AF | 12 )
+#define PB13_PF_SD_CMD       ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 )
+#define PB13_AF_MS_BS        ( GPIO_PORTB | GPIO_AF | 13 )
+#define PB14_AF_SSI_RXFS     ( GPIO_PORTB | GPIO_AF | 14 )
+#define PB15_AF_SSI_RXCLK    ( GPIO_PORTB | GPIO_AF | 15 )
+#define PB16_AF_SSI_RXDAT    ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
+#define PB17_AF_SSI_TXDAT    ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
+#define PB18_AF_SSI_TXFS     ( GPIO_PORTB | GPIO_AF | 18 )
+#define PB19_AF_SSI_TXCLK    ( GPIO_PORTB | GPIO_AF | 19 )
+#define PB20_PF_USBD_AFE     ( GPIO_PORTB | GPIO_PF | 20 )
+#define PB21_PF_USBD_OE      ( GPIO_PORTB | GPIO_PF | 21 )
+#define PB22_PFUSBD_RCV      ( GPIO_PORTB | GPIO_PF | 22 )
+#define PB23_PF_USBD_SUSPND  ( GPIO_PORTB | GPIO_PF | 23 )
+#define PB24_PF_USBD_VP      ( GPIO_PORTB | GPIO_PF | 24 )
+#define PB25_PF_USBD_VM      ( GPIO_PORTB | GPIO_PF | 25 )
+#define PB26_PF_USBD_VPO     ( GPIO_PORTB | GPIO_PF | 26 )
+#define PB27_PF_USBD_VMO     ( GPIO_PORTB | GPIO_PF | 27 )
+#define PB28_PF_UART2_CTS    ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
+#define PB29_PF_UART2_RTS    ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
+#define PB30_PF_UART2_TXD    ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
+#define PB31_PF_UART2_RXD    ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
+#define PC3_PF_SSI_RXFS      ( GPIO_PORTC | GPIO_PF | 3 )
+#define PC4_PF_SSI_RXCLK     ( GPIO_PORTC | GPIO_PF | 4 )
+#define PC5_PF_SSI_RXDAT     ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
+#define PC6_PF_SSI_TXDAT     ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
+#define PC7_PF_SSI_TXFS      ( GPIO_PORTC | GPIO_PF | 7 )
+#define PC8_PF_SSI_TXCLK     ( GPIO_PORTC | GPIO_PF | 8 )
+#define PC9_PF_UART1_CTS     ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
+#define PC10_PF_UART1_RTS    ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
+#define PC11_PF_UART1_TXD    ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
+#define PC12_PF_UART1_RXD    ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
+#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
+#define PC14_PF_SPI1_SCLK    ( GPIO_PORTC | GPIO_PF | 14 )
+#define PC15_PF_SPI1_SS      ( GPIO_PORTC | GPIO_PF | 15 )
+#define PC16_PF_SPI1_MISO    ( GPIO_PORTC | GPIO_PF | 16 )
+#define PC17_PF_SPI1_MOSI    ( GPIO_PORTC | GPIO_PF | 17 )
+#define PD6_PF_LSCLK         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
+#define PD7_PF_REV           ( GPIO_PORTD | GPIO_PF | 7 )
+#define PD7_AF_UART2_DTR     ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
+#define PD7_AIN_SPI2_SCLK    ( GPIO_PORTD | GPIO_AIN | 7 )
+#define PD8_PF_CLS           ( GPIO_PORTD | GPIO_PF | 8 )
+#define PD8_AF_UART2_DCD     ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
+#define PD8_AIN_SPI2_SS      ( GPIO_PORTD | GPIO_AIN | 8 )
+#define PD9_PF_PS            ( GPIO_PORTD | GPIO_PF | 9 )
+#define PD9_AF_UART2_RI      ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
+#define PD9_AOUT_SPI2_RXD    ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
+#define PD10_PF_SPL_SPR      ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
+#define PD10_AF_UART2_DSR    ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
+#define PD10_AIN_SPI2_TXD    ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
+#define PD11_PF_CONTRAST     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
+#define PD12_PF_ACD_OE       ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
+#define PD13_PF_LP_HSYNC     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
+#define PD14_PF_FLM_VSYNC    ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
+#define PD15_PF_LD0          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
+#define PD16_PF_LD1          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
+#define PD17_PF_LD2          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
+#define PD18_PF_LD3          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
+#define PD19_PF_LD4          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
+#define PD20_PF_LD5          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
+#define PD21_PF_LD6          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
+#define PD22_PF_LD7          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
+#define PD23_PF_LD8          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
+#define PD24_PF_LD9          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
+#define PD25_PF_LD10         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
+#define PD26_PF_LD11         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
+#define PD27_PF_LD12         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
+#define PD28_PF_LD13         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
+#define PD29_PF_LD14         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
+#define PD30_PF_LD15         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
+#define PD31_PF_TMR2OUT      ( GPIO_PORTD | GPIO_PF | 31 )
+#define PD31_BIN_SPI2_TXD    ( GPIO_PORTD | GPIO_BIN | 31 )
+
+/*
+ *  DMA Controller
+ */
+#define DCR     __REG(IMX_DMAC_BASE +0x00)	/* DMA Control Register */
+#define DISR    __REG(IMX_DMAC_BASE +0x04)	/* DMA Interrupt status Register */
+#define DIMR    __REG(IMX_DMAC_BASE +0x08)	/* DMA Interrupt mask Register */
+#define DBTOSR  __REG(IMX_DMAC_BASE +0x0c)	/* DMA Burst timeout status Register */
+#define DRTOSR  __REG(IMX_DMAC_BASE +0x10)	/* DMA Request timeout Register */
+#define DSESR   __REG(IMX_DMAC_BASE +0x14)	/* DMA Transfer Error Status Register */
+#define DBOSR   __REG(IMX_DMAC_BASE +0x18)	/* DMA Buffer overflow status Register */
+#define DBTOCR  __REG(IMX_DMAC_BASE +0x1c)	/* DMA Burst timeout control Register */
+#define WSRA    __REG(IMX_DMAC_BASE +0x40)	/* W-Size Register A */
+#define XSRA    __REG(IMX_DMAC_BASE +0x44)	/* X-Size Register A */
+#define YSRA    __REG(IMX_DMAC_BASE +0x48)	/* Y-Size Register A */
+#define WSRB    __REG(IMX_DMAC_BASE +0x4c)	/* W-Size Register B */
+#define XSRB    __REG(IMX_DMAC_BASE +0x50)	/* X-Size Register B */
+#define YSRB    __REG(IMX_DMAC_BASE +0x54)	/* Y-Size Register B */
+#define SAR(x)  __REG2( IMX_DMAC_BASE + 0x80, (x) << 6)	/* Source Address Registers */
+#define DAR(x)  __REG2( IMX_DMAC_BASE + 0x84, (x) << 6)	/* Destination Address Registers */
+#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6)	/* Count Registers */
+#define CCR(x)  __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6)	/* Control Registers */
+#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6)	/* Request source select Registers */
+#define BLR(x)  __REG2( IMX_DMAC_BASE + 0x94, (x) << 6)	/* Burst length Registers */
+#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6)	/* Request timeout Registers */
+#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6)	/* Bus Utilization Registers */
+
+/* TODO: define DMA_REQ lines */
+
+#define DCR_DRST           (1<<1)
+#define DCR_DEN            (1<<0)
+#define DBTOCR_EN          (1<<15)
+#define DBTOCR_CNT(x)      ((x) & 0x7fff )
+#define CNTR_CNT(x)        ((x) & 0xffffff )
+#define CCR_DMOD_LINEAR    ( 0x0 << 12 )
+#define CCR_DMOD_2D        ( 0x1 << 12 )
+#define CCR_DMOD_FIFO      ( 0x2 << 12 )
+#define CCR_DMOD_EOBFIFO   ( 0x3 << 12 )
+#define CCR_SMOD_LINEAR    ( 0x0 << 10 )
+#define CCR_SMOD_2D        ( 0x1 << 10 )
+#define CCR_SMOD_FIFO      ( 0x2 << 10 )
+#define CCR_SMOD_EOBFIFO   ( 0x3 << 10 )
+#define CCR_MDIR_DEC       (1<<9)
+#define CCR_MSEL_B         (1<<8)
+#define CCR_DSIZ_32        ( 0x0 << 6 )
+#define CCR_DSIZ_8         ( 0x1 << 6 )
+#define CCR_DSIZ_16        ( 0x2 << 6 )
+#define CCR_SSIZ_32        ( 0x0 << 4 )
+#define CCR_SSIZ_8         ( 0x1 << 4 )
+#define CCR_SSIZ_16        ( 0x2 << 4 )
+#define CCR_REN            (1<<3)
+#define CCR_RPT            (1<<2)
+#define CCR_FRC            (1<<1)
+#define CCR_CEN            (1<<0)
+#define RTOR_EN            (1<<15)
+#define RTOR_CLK           (1<<14)
+#define RTOR_PSC           (1<<13)
+
+/*
+ * LCD Controller
+ */
+
+#define LCDC_SSA	__REG(IMX_LCDC_BASE+0x00)
+
+#define LCDC_SIZE	__REG(IMX_LCDC_BASE+0x04)
+#define SIZE_XMAX(x)	((((x) >> 4) & 0x3f) << 20)
+#define SIZE_YMAX(y)    ( (y) & 0x1ff )
+
+#define LCDC_VPW	__REG(IMX_LCDC_BASE+0x08)
+#define VPW_VPW(x)	( (x) & 0x3ff )
+
+#define LCDC_CPOS	__REG(IMX_LCDC_BASE+0x0C)
+#define CPOS_CC1        (1<<31)
+#define CPOS_CC0        (1<<30)
+#define CPOS_OP         (1<<28)
+#define CPOS_CXP(x)     (((x) & 3ff) << 16)
+#define CPOS_CYP(y)     ((y) & 0x1ff)
+
+#define LCDC_LCWHB	__REG(IMX_LCDC_BASE+0x10)
+#define LCWHB_BK_EN     (1<<31)
+#define LCWHB_CW(w)     (((w) & 0x1f) << 24)
+#define LCWHB_CH(h)     (((h) & 0x1f) << 16)
+#define LCWHB_BD(x)     ((x) & 0xff)
+
+#define LCDC_LCHCC	__REG(IMX_LCDC_BASE+0x14)
+#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
+#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
+#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
+
+#define LCDC_PCR	__REG(IMX_LCDC_BASE+0x18)
+#define PCR_TFT         (1<<31)
+#define PCR_COLOR       (1<<30)
+#define PCR_PBSIZ_1     (0<<28)
+#define PCR_PBSIZ_2     (1<<28)
+#define PCR_PBSIZ_4     (2<<28)
+#define PCR_PBSIZ_8     (3<<28)
+#define PCR_BPIX_1      (0<<25)
+#define PCR_BPIX_2      (1<<25)
+#define PCR_BPIX_4      (2<<25)
+#define PCR_BPIX_8      (3<<25)
+#define PCR_BPIX_12     (4<<25)
+#define PCR_BPIX_16     (4<<25)
+#define PCR_PIXPOL      (1<<24)
+#define PCR_FLMPOL      (1<<23)
+#define PCR_LPPOL       (1<<22)
+#define PCR_CLKPOL      (1<<21)
+#define PCR_OEPOL       (1<<20)
+#define PCR_SCLKIDLE    (1<<19)
+#define PCR_END_SEL     (1<<18)
+#define PCR_END_BYTE_SWAP (1<<17)
+#define PCR_REV_VS      (1<<16)
+#define PCR_ACD_SEL     (1<<15)
+#define PCR_ACD(x)      (((x) & 0x7f) << 8)
+#define PCR_SCLK_SEL    (1<<7)
+#define PCR_SHARP       (1<<6)
+#define PCR_PCD(x)      ((x) & 0x3f)
+
+#define LCDC_HCR	__REG(IMX_LCDC_BASE+0x1C)
+#define HCR_H_WIDTH(x)  (((x) & 0x3f) << 26)
+#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
+#define HCR_H_WAIT_2(x) ((x) & 0xff)
+
+#define LCDC_VCR	__REG(IMX_LCDC_BASE+0x20)
+#define VCR_V_WIDTH(x)  (((x) & 0x3f) << 26)
+#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
+#define VCR_V_WAIT_2(x) ((x) & 0xff)
+
+#define LCDC_POS	__REG(IMX_LCDC_BASE+0x24)
+#define POS_POS(x)      ((x) & 1f)
+
+#define LCDC_LSCR1	__REG(IMX_LCDC_BASE+0x28)
+#define LSCR1_GRAY1(x)  (((x) & 0xf) << 4)
+#define LSCR1_GRAY2(x)  ((x) & 0xf)
+
+#define LCDC_PWMR	__REG(IMX_LCDC_BASE+0x2C)
+#define PWMR_CLS(x)     (((x) & 0x1ff) << 16)
+#define PWMR_LDMSK      (1<<15)
+#define PWMR_SCR1       (1<<10)
+#define PWMR_SCR0       (1<<9)
+#define PWMR_CC_EN      (1<<8)
+#define PWMR_PW(x)      ((x) & 0xff)
+
+#define LCDC_DMACR	__REG(IMX_LCDC_BASE+0x30)
+#define DMACR_BURST     (1<<31)
+#define DMACR_HM(x)     (((x) & 0xf) << 16)
+#define DMACR_TM(x)     ((x) &0xf)
+
+#define LCDC_RMCR	__REG(IMX_LCDC_BASE+0x34)
+#define RMCR_LCDC_EN		(1<<1)
+#define RMCR_SELF_REF		(1<<0)
+
+#define LCDC_LCDICR	__REG(IMX_LCDC_BASE+0x38)
+#define LCDICR_INT_SYN  (1<<2)
+#define LCDICR_INT_CON  (1)
+
+#define LCDC_LCDISR	__REG(IMX_LCDC_BASE+0x40)
+#define LCDISR_UDR_ERR (1<<3)
+#define LCDISR_ERR_RES (1<<2)
+#define LCDISR_EOF     (1<<1)
+#define LCDISR_BOF     (1<<0)
+/*
+ *  UART Module
+ */
+#define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12)	/* Receiver Register */
+#define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12)	/* Transmitter Register */
+#define UCR1(x)  __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12)	/* Control Register 1 */
+#define UCR2(x)  __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12)	/* Control Register 2 */
+#define UCR3(x)  __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12)	/* Control Register 3 */
+#define UCR4(x)  __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12)	/* Control Register 4 */
+#define UFCR(x)  __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12)	/* FIFO Control Register */
+#define USR1(x)  __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12)	/* Status Register 1 */
+#define USR2(x)  __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12)	/* Status Register 2 */
+#define UESC(x)  __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12)	/* Escape Character Register */
+#define UTIM(x)  __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12)	/* Escape Timer Register */
+#define UBIR(x)  __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12)	/* BRM Incremental Register */
+#define UBMR(x)  __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12)	/* BRM Modulator Register */
+#define UBRC(x)  __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12)	/* Baud Rate Count Register */
+#define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12)	/* Incremental Preset Register 1 */
+#define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12)	/* Incremental Preset Register 2 */
+#define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12)	/* Incremental Preset Register 3 */
+#define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12)	/* Incremental Preset Register 4 */
+#define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12)	/* BRM Modulator Register 1 */
+#define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12)	/* BRM Modulator Register 2 */
+#define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12)	/* BRM Modulator Register 3 */
+#define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12)	/* BRM Modulator Register 4 */
+#define UTS(x)   __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12)	/* UART Test Register */
+
+/* UART Control Register Bit Fields.*/
+#define  URXD_CHARRDY    (1<<15)
+#define  URXD_ERR        (1<<14)
+#define  URXD_OVRRUN     (1<<13)
+#define  URXD_FRMERR     (1<<12)
+#define  URXD_BRK        (1<<11)
+#define  URXD_PRERR      (1<<10)
+#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
+#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
+#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
+#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
+#define  UCR1_RRDYEN     (1<<9)	 /* Recv ready interrupt enable */
+#define  UCR1_RDMAEN     (1<<8)	 /* Recv ready DMA enable */
+#define  UCR1_IREN       (1<<7)	 /* Infrared interface enable */
+#define  UCR1_TXMPTYEN   (1<<6)	 /* Transimitter empty interrupt enable */
+#define  UCR1_RTSDEN     (1<<5)	 /* RTS delta interrupt enable */
+#define  UCR1_SNDBRK     (1<<4)	 /* Send break */
+#define  UCR1_TDMAEN     (1<<3)	 /* Transmitter ready DMA enable */
+#define  UCR1_UARTCLKEN  (1<<2)	 /* UART clock enabled */
+#define  UCR1_DOZE       (1<<1)	 /* Doze */
+#define  UCR1_UARTEN     (1<<0)	 /* UART enabled */
+#define  UCR2_ESCI     	 (1<<15) /* Escape seq interrupt enable */
+#define  UCR2_IRTS  	 (1<<14) /* Ignore RTS pin */
+#define  UCR2_CTSC  	 (1<<13) /* CTS pin control */
+#define  UCR2_CTS        (1<<12) /* Clear to send */
+#define  UCR2_ESCEN      (1<<11) /* Escape enable */
+#define  UCR2_PREN       (1<<8) /* Parity enable */
+#define  UCR2_PROE       (1<<7) /* Parity odd/even */
+#define  UCR2_STPB       (1<<6)	/* Stop */
+#define  UCR2_WS         (1<<5)	/* Word size */
+#define  UCR2_RTSEN      (1<<4)	/* Request to send interrupt enable */
+#define  UCR2_TXEN       (1<<2)	/* Transmitter enabled */
+#define  UCR2_RXEN       (1<<1)	/* Receiver enabled */
+#define  UCR2_SRST 	 (1<<0)	/* SW reset */
+#define  UCR3_DTREN 	 (1<<13) /* DTR interrupt enable */
+#define  UCR3_PARERREN   (1<<12) /* Parity enable */
+#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
+#define  UCR3_DSR        (1<<10) /* Data set ready */
+#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
+#define  UCR3_RI         (1<<8)  /* Ring indicator */
+#define  UCR3_TIMEOUTEN  (1<<7)  /* Timeout interrupt enable */
+#define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
+#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
+#define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
+#define  UCR3_REF25 	 (1<<3)  /* Ref freq 25 MHz */
+#define  UCR3_REF30 	 (1<<2)  /* Ref Freq 30 MHz */
+#define  UCR3_INVT  	 (1<<1)  /* Inverted Infrared transmission */
+#define  UCR3_BPEN  	 (1<<0)  /* Preset registers enable */
+#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
+#define  UCR4_INVR  	 (1<<9)  /* Inverted infrared reception */
+#define  UCR4_ENIRI 	 (1<<8)  /* Serial infrared interrupt enable */
+#define  UCR4_WKEN  	 (1<<7)  /* Wake interrupt enable */
+#define  UCR4_REF16 	 (1<<6)  /* Ref freq 16 MHz */
+#define  UCR4_IRSC  	 (1<<5) /* IR special case */
+#define  UCR4_TCEN  	 (1<<3) /* Transmit complete interrupt enable */
+#define  UCR4_BKEN  	 (1<<2) /* Break condition interrupt enable */
+#define  UCR4_OREN  	 (1<<1) /* Receiver overrun interrupt enable */
+#define  UCR4_DREN  	 (1<<0) /* Recv data ready interrupt enable */
+#define  UFCR_RXTL_SHF   0      /* Receiver trigger level shift */
+#define  UFCR_RFDIV      (7<<7) /* Reference freq divider mask */
+#define  UFCR_TXTL_SHF   10     /* Transmitter trigger level shift */
+#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
+#define  USR1_RTSS  	 (1<<14) /* RTS pin status */
+#define  USR1_TRDY  	 (1<<13) /* Transmitter ready interrupt/dma flag */
+#define  USR1_RTSD  	 (1<<12) /* RTS delta */
+#define  USR1_ESCF  	 (1<<11) /* Escape seq interrupt flag */
+#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
+#define  USR1_RRDY       (1<<9)	/* Receiver ready interrupt/dma flag */
+#define  USR1_TIMEOUT    (1<<7)	/* Receive timeout interrupt status */
+#define  USR1_RXDS  	 (1<<6)	/* Receiver idle interrupt flag */
+#define  USR1_AIRINT	 (1<<5)	/* Async IR wake interrupt flag */
+#define  USR1_AWAKE 	 (1<<4)	/* Aysnc wake interrupt flag */
+#define  USR2_ADET  	 (1<<15) /* Auto baud rate detect complete */
+#define  USR2_TXFE  	 (1<<14) /* Transmit buffer FIFO empty */
+#define  USR2_DTRF  	 (1<<13) /* DTR edge interrupt flag */
+#define  USR2_IDLE  	 (1<<12) /* Idle condition */
+#define  USR2_IRINT 	 (1<<8)	/* Serial infrared interrupt flag */
+#define  USR2_WAKE  	 (1<<7)	/* Wake */
+#define  USR2_RTSF  	 (1<<4)	/* RTS edge interrupt flag */
+#define  USR2_TXDC  	 (1<<3)	/* Transmitter complete */
+#define  USR2_BRCD  	 (1<<2)	/* Break condition */
+#define  USR2_ORE        (1<<1)	/* Overrun error */
+#define  USR2_RDR        (1<<0)	/* Recv data ready */
+#define  UTS_FRCPERR	 (1<<13) /* Force parity error */
+#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
+#define  UTS_TXEMPTY	 (1<<6)	/* TxFIFO empty */
+#define  UTS_RXEMPTY	 (1<<5)	/* RxFIFO empty */
+#define  UTS_TXFULL 	 (1<<4)	/* TxFIFO full */
+#define  UTS_RXFULL 	 (1<<3)	/* RxFIFO full */
+#define  UTS_SOFTRST	 (1<<0)	/* Software reset */
+
+/* General purpose timers registers */
+#define TCTL1   __REG(IMX_TIM1_BASE)
+#define TPRER1  __REG(IMX_TIM1_BASE + 0x4)
+#define TCMP1   __REG(IMX_TIM1_BASE + 0x8)
+#define TCR1    __REG(IMX_TIM1_BASE + 0xc)
+#define TCN1    __REG(IMX_TIM1_BASE + 0x10)
+#define TSTAT1  __REG(IMX_TIM1_BASE + 0x14)
+#define TCTL2   __REG(IMX_TIM2_BASE)
+#define TPRER2  __REG(IMX_TIM2_BASE + 0x4)
+#define TCMP2   __REG(IMX_TIM2_BASE + 0x8)
+#define TCR2    __REG(IMX_TIM2_BASE + 0xc)
+#define TCN2    __REG(IMX_TIM2_BASE + 0x10)
+#define TSTAT2  __REG(IMX_TIM2_BASE + 0x14)
+
+/* General purpose timers bitfields */
+#define TCTL_SWR       (1<<15) /* Software reset */
+#define TCTL_FRR       (1<<8)  /* Freerun / restart */
+#define TCTL_CAP       (3<<6)  /* Capture Edge */
+#define TCTL_OM        (1<<5)  /* output mode */
+#define TCTL_IRQEN     (1<<4)  /* interrupt enable */
+#define TCTL_CLKSOURCE (7<<1)  /* Clock source */
+#define TCTL_TEN       (1)     /* Timer enable */
+#define TPRER_PRES     (0xff)  /* Prescale */
+#define TSTAT_CAPT     (1<<1)  /* Capture event */
+#define TSTAT_COMP     (1)     /* Compare event */
+
+#endif				/* _IMX_REGS_H */
diff --git a/include/asm-arm/arch-ixp/ixp425.h b/include/asm-arm/arch-ixp/ixp425.h
new file mode 100755
index 0000000..fbe6858
--- /dev/null
+++ b/include/asm-arm/arch-ixp/ixp425.h
@@ -0,0 +1,559 @@
+/*
+ * include/asm-arm/arch-ixp425/ixp425.h
+ *
+ * Register definitions for IXP425
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ASM_ARM_IXP425_H_
+#define _ASM_ARM_IXP425_H_
+
+#define BIT(x)	(1<<(x))
+
+/* FIXME: Only this does work for u-boot... find out why... [RS] */
+#define UBOOT_REG_FIX 1
+#ifdef UBOOT_REG_FIX
+# undef	io_p2v
+# undef __REG
+# ifndef __ASSEMBLY__
+#  define io_p2v(PhAdd)    (PhAdd)
+#  define __REG(x)	(*((volatile u32 *)io_p2v(x)))
+#  define __REG2(x,y)	(*(volatile u32 *)((u32)&__REG(x) + (y)))
+# else
+#  define __REG(x) (x)
+# endif
+#endif /* UBOOT_REG_FIX */
+
+/*
+ *
+ * IXP425 Memory map:
+ *
+ * Phy		Phy Size	Map Size	Virt		Description
+ * =========================================================================
+ *
+ * 0x00000000	0x10000000					SDRAM 1
+ *
+ * 0x10000000	0x10000000					SDRAM 2
+ *
+ * 0x20000000	0x10000000					SDRAM 3
+ *
+ * 0x30000000	0x10000000					SDRAM 4
+ *
+ * The above four are aliases to the same memory location  (0x00000000)
+ *
+ * 0x48000000	 0x4000000					PCI Memory
+ *
+ * 0x50000000	0x10000000			Not Mapped	EXP BUS
+ *
+ * 0x6000000	0x00004000	    0x4000	0xFFFEB000	QMgr
+ *
+ * 0xC0000000	     0x100   	    0x1000	0xFFFDD000	PCI CFG
+ *
+ * 0xC4000000	     0x100          0x1000	0xFFFDE000	EXP CFG
+ *
+ * 0xC8000000	    0xC000          0xC000	0xFFFDF000	PERIPHERAL
+ *
+ * 0xCC000000	     0x100   	    0x1000	Not Mapped	SDRAM CFG
+ */
+
+/*
+ * SDRAM
+ */
+#define IXP425_SDRAM_BASE		(0x00000000)
+#define IXP425_SDRAM_BASE_ALT		(0x10000000)
+
+
+/*
+ * PCI Configuration space
+ */
+#define IXP425_PCI_CFG_BASE_PHYS	(0xC0000000)
+#define IXP425_PCI_CFG_BASE_VIRT	(0xFFFD0000)
+#define IXP425_PCI_CFG_REGION_SIZE	(0x00001000)
+
+/*
+ * Expansion BUS Configuration registers
+ */
+#define IXP425_EXP_CFG_BASE_PHYS	(0xC4000000)
+#define IXP425_EXP_CFG_BASE_VIRT	(0xFFFD1000)
+#define IXP425_EXP_CFG_REGION_SIZE	(0x00001000)
+
+/*
+ * Peripheral space
+ */
+#define IXP425_PERIPHERAL_BASE_PHYS	(0xC8000000)
+#define IXP425_PERIPHERAL_BASE_VIRT	(0xFFFD2000)
+#define IXP425_PERIPHERAL_REGION_SIZE	(0x0000C000)
+
+/*
+ * SDRAM configuration registers
+ */
+#define IXP425_SDRAM_CFG_BASE_PHYS	(0xCC000000)
+
+/*
+ * Q Manager space .. not static mapped
+ */
+#define IXP425_QMGR_BASE_PHYS		(0x60000000)
+#define IXP425_QMGR_BASE_VIRT		(0xFFFDE000)
+#define IXP425_QMGR_REGION_SIZE		(0x00004000)
+
+/*
+ * Expansion BUS
+ *
+ * Expansion Bus 'lives' at either base1 or base 2 depending on the value of
+ * Exp Bus config registers:
+ *
+ * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero,
+ * and The expansion bus to IXP425_EXP_BUS_BASE2
+ */
+#define IXP425_EXP_BUS_BASE1_PHYS	(0x00000000)
+#define IXP425_EXP_BUS_BASE2_PHYS	(0x50000000)
+#define IXP425_EXP_BUS_BASE2_VIRT	(0xF0000000)
+
+#define IXP425_EXP_BUS_BASE_PHYS	IXP425_EXP_BUS_BASE2_PHYS
+#define IXP425_EXP_BUS_BASE_VIRT	IXP425_EXP_BUS_BASE2_VIRT
+
+#define IXP425_EXP_BUS_REGION_SIZE	(0x08000000)
+#define IXP425_EXP_BUS_CSX_REGION_SIZE	(0x01000000)
+
+#define IXP425_EXP_BUS_CS0_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x00000000)
+#define IXP425_EXP_BUS_CS1_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x01000000)
+#define IXP425_EXP_BUS_CS2_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x02000000)
+#define IXP425_EXP_BUS_CS3_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x03000000)
+#define IXP425_EXP_BUS_CS4_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x04000000)
+#define IXP425_EXP_BUS_CS5_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x05000000)
+#define IXP425_EXP_BUS_CS6_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
+#define IXP425_EXP_BUS_CS7_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
+
+#define IXP425_EXP_BUS_CS0_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x00000000)
+#define IXP425_EXP_BUS_CS1_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x01000000)
+#define IXP425_EXP_BUS_CS2_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x02000000)
+#define IXP425_EXP_BUS_CS3_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x03000000)
+#define IXP425_EXP_BUS_CS4_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x04000000)
+#define IXP425_EXP_BUS_CS5_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x05000000)
+#define IXP425_EXP_BUS_CS6_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x06000000)
+#define IXP425_EXP_BUS_CS7_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x07000000)
+
+#define IXP425_FLASH_WRITABLE	(0x2)
+#define IXP425_FLASH_DEFAULT	(0xbcd23c40)
+#define IXP425_FLASH_WRITE	(0xbcd23c42)
+
+
+#define IXP425_EXP_CS0_OFFSET	0x00
+#define IXP425_EXP_CS1_OFFSET   0x04
+#define IXP425_EXP_CS2_OFFSET   0x08
+#define IXP425_EXP_CS3_OFFSET   0x0C
+#define IXP425_EXP_CS4_OFFSET   0x10
+#define IXP425_EXP_CS5_OFFSET   0x14
+#define IXP425_EXP_CS6_OFFSET   0x18
+#define IXP425_EXP_CS7_OFFSET   0x1C
+#define IXP425_EXP_CFG0_OFFSET	0x20
+#define IXP425_EXP_CFG1_OFFSET	0x24
+#define IXP425_EXP_CFG2_OFFSET	0x28
+#define IXP425_EXP_CFG3_OFFSET	0x2C
+
+/*
+ * Expansion Bus Controller registers.
+ */
+#ifndef __ASSEMBLY__
+#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_VIRT+(x)))
+#else
+#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
+#endif
+
+#define IXP425_EXP_CS0      IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
+#define IXP425_EXP_CS1      IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
+#define IXP425_EXP_CS2      IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
+#define IXP425_EXP_CS3      IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET)
+#define IXP425_EXP_CS4      IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET)
+#define IXP425_EXP_CS5      IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET)
+#define IXP425_EXP_CS6      IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
+#define IXP425_EXP_CS7      IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET)
+
+#define IXP425_EXP_CFG0     IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
+#define IXP425_EXP_CFG1     IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
+#define IXP425_EXP_CFG2     IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
+#define IXP425_EXP_CFG3     IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
+
+/*
+ * SDRAM Controller registers.
+ */
+#define IXP425_SDR_CONFIG_OFFSET	0x00
+#define IXP425_SDR_REFRESH_OFFSET	0x04
+#define IXP425_SDR_IR_OFFSET		0x08
+
+#define IXP425_SDRAM_REG(x) 	(IXP425_SDRAM_CFG_BASE_PHYS+(x))
+
+#define IXP425_SDR_CONFIG	IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET)
+#define IXP425_SDR_REFRESH     	IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
+#define IXP425_SDR_IR     	IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
+
+/*
+ * UART registers
+ */
+#define IXP425_UART1	0
+#define IXP425_UART2	0x1000
+
+#define IXP425_UART_RBR_OFFSET	0x00
+#define IXP425_UART_THR_OFFSET	0x00
+#define IXP425_UART_DLL_OFFSET	0x00
+#define IXP425_UART_IER_OFFSET	0x04
+#define IXP425_UART_DLH_OFFSET	0x04
+#define IXP425_UART_IIR_OFFSET	0x08
+#define IXP425_UART_FCR_OFFSET	0x00
+#define IXP425_UART_LCR_OFFSET	0x0c
+#define IXP425_UART_MCR_OFFSET	0x10
+#define IXP425_UART_LSR_OFFSET	0x14
+#define IXP425_UART_MSR_OFFSET	0x18
+#define IXP425_UART_SPR_OFFSET	0x1c
+#define IXP425_UART_ISR_OFFSET	0x20
+
+#define IXP425_UART_CFG_BASE_PHYS	(0xc8000000)
+
+#define RBR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET)
+#define THR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET)
+#define DLL(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET)
+#define IER(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET)
+#define DLH(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET)
+#define IIR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET)
+#define FCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET)
+#define LCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET)
+#define MCR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET)
+#define LSR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET)
+#define MSR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET)
+#define SPR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET)
+#define ISR(x)		__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET)
+
+#define IER_DMAE	(1 << 7)	/* DMA Requests Enable */
+#define IER_UUE		(1 << 6)	/* UART Unit Enable */
+#define IER_NRZE	(1 << 5)	/* NRZ coding Enable */
+#define IER_RTIOE	(1 << 4)	/* Receiver Time Out Interrupt Enable */
+#define IER_MIE		(1 << 3)	/* Modem Interrupt Enable */
+#define IER_RLSE	(1 << 2)	/* Receiver Line Status Interrupt Enable */
+#define IER_TIE		(1 << 1)	/* Transmit Data request Interrupt Enable */
+#define IER_RAVIE	(1 << 0)	/* Receiver Data Available Interrupt Enable */
+
+#define IIR_FIFOES1	(1 << 7)	/* FIFO Mode Enable Status */
+#define IIR_FIFOES0	(1 << 6)	/* FIFO Mode Enable Status */
+#define IIR_TOD		(1 << 3)	/* Time Out Detected */
+#define IIR_IID2	(1 << 2)	/* Interrupt Source Encoded */
+#define IIR_IID1	(1 << 1)	/* Interrupt Source Encoded */
+#define IIR_IP		(1 << 0)	/* Interrupt Pending (active low) */
+
+#define FCR_ITL2	(1 << 7)	/* Interrupt Trigger Level */
+#define FCR_ITL1	(1 << 6)	/* Interrupt Trigger Level */
+#define FCR_RESETTF	(1 << 2)	/* Reset Transmitter FIFO */
+#define FCR_RESETRF	(1 << 1)	/* Reset Receiver FIFO */
+#define FCR_TRFIFOE	(1 << 0)	/* Transmit and Receive FIFO Enable */
+#define FCR_ITL_1	(0)
+#define FCR_ITL_8	(FCR_ITL1)
+#define FCR_ITL_16	(FCR_ITL2)
+#define FCR_ITL_32	(FCR_ITL2|FCR_ITL1)
+
+#define LCR_DLAB	(1 << 7)	/* Divisor Latch Access Bit */
+#define LCR_SB		(1 << 6)	/* Set Break */
+#define LCR_STKYP	(1 << 5)	/* Sticky Parity */
+#define LCR_EPS		(1 << 4)	/* Even Parity Select */
+#define LCR_PEN		(1 << 3)	/* Parity Enable */
+#define LCR_STB		(1 << 2)	/* Stop Bit */
+#define LCR_WLS1	(1 << 1)	/* Word Length Select */
+#define LCR_WLS0	(1 << 0)	/* Word Length Select */
+
+#define LSR_FIFOE	(1 << 7)	/* FIFO Error Status */
+#define LSR_TEMT	(1 << 6)	/* Transmitter Empty */
+#define LSR_TDRQ	(1 << 5)	/* Transmit Data Request */
+#define LSR_BI		(1 << 4)	/* Break Interrupt */
+#define LSR_FE		(1 << 3)	/* Framing Error */
+#define LSR_PE		(1 << 2)	/* Parity Error */
+#define LSR_OE		(1 << 1)	/* Overrun Error */
+#define LSR_DR		(1 << 0)	/* Data Ready */
+
+#define MCR_LOOP	(1 << 4)	*/
+#define MCR_OUT2	(1 << 3)	/* force MSR_DCD in loopback mode */
+#define MCR_OUT1	(1 << 2)	/* force MSR_RI in loopback mode */
+#define MCR_RTS		(1 << 1)	/* Request to Send */
+#define MCR_DTR		(1 << 0)	/* Data Terminal Ready */
+
+#define MSR_DCD		(1 << 7)	/* Data Carrier Detect */
+#define MSR_RI		(1 << 6)	/* Ring Indicator */
+#define MSR_DSR		(1 << 5)	/* Data Set Ready */
+#define MSR_CTS		(1 << 4)	/* Clear To Send */
+#define MSR_DDCD	(1 << 3)	/* Delta Data Carrier Detect */
+#define MSR_TERI	(1 << 2)	/* Trailing Edge Ring Indicator */
+#define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */
+#define MSR_DCTS	(1 << 0)	/* Delta Clear To Send */
+
+#define IXP425_CONSOLE_UART_BASE_VIRT IXP425_UART1_BASE_VIRT
+#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
+/*
+ * Peripheral Space Registers
+ */
+#define IXP425_UART1_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x0000)
+#define IXP425_UART2_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x1000)
+#define IXP425_PMU_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x2000)
+#define IXP425_INTC_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x3000)
+#define IXP425_GPIO_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x4000)
+#define IXP425_TIMER_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x5000)
+#define IXP425_NPEA_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x6000)
+#define IXP425_NPEB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x7000)
+#define IXP425_NPEC_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x8000)
+#define IXP425_EthA_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x9000)
+#define IXP425_EthB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0xA000)
+#define IXP425_USB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0xB000)
+
+#define IXP425_UART1_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x0000)
+#define IXP425_UART2_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x1000)
+#define IXP425_PMU_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x2000)
+#define IXP425_INTC_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x3000)
+#define IXP425_GPIO_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x4000)
+#define IXP425_TIMER_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x5000)
+#define IXP425_NPEA_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x6000)
+#define IXP425_NPEB_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x7000)
+#define IXP425_NPEC_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x8000)
+#define IXP425_EthA_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x9000)
+#define IXP425_EthB_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0xA000)
+#define IXP425_USB_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0xB000)
+
+
+/*
+ * UART Register Definitions , Offsets only as there are 2 UARTS.
+ *   IXP425_UART1_BASE , IXP425_UART2_BASE.
+ */
+
+#undef  UART_NO_RX_INTERRUPT
+
+#define IXP425_UART_XTAL        14745600
+
+/*
+ * Constants to make it easy to access  Interrupt Controller registers
+ */
+#define IXP425_ICPR_OFFSET	0x00 /* Interrupt Status */
+#define IXP425_ICMR_OFFSET	0x04 /* Interrupt Enable */
+#define IXP425_ICLR_OFFSET	0x08 /* Interrupt IRQ/FIQ Select */
+#define IXP425_ICIP_OFFSET      0x0C /* IRQ Status */
+#define IXP425_ICFP_OFFSET	0x10 /* FIQ Status */
+#define IXP425_ICHR_OFFSET	0x14 /* Interrupt Priority */
+#define IXP425_ICIH_OFFSET	0x18 /* IRQ Highest Pri Int */
+#define IXP425_ICFH_OFFSET	0x1C /* FIQ Highest Pri Int */
+
+/*
+ * Interrupt Controller Register Definitions.
+ */
+#ifndef __ASSEMBLY__
+#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_VIRT+(x)))
+#else
+#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x))
+#endif
+
+#define IXP425_ICPR     IXP425_INTC_REG(IXP425_ICPR_OFFSET)
+#define IXP425_ICMR     IXP425_INTC_REG(IXP425_ICMR_OFFSET)
+#define IXP425_ICLR     IXP425_INTC_REG(IXP425_ICLR_OFFSET)
+#define IXP425_ICIP     IXP425_INTC_REG(IXP425_ICIP_OFFSET)
+#define IXP425_ICFP     IXP425_INTC_REG(IXP425_ICFP_OFFSET)
+#define IXP425_ICHR     IXP425_INTC_REG(IXP425_ICHR_OFFSET)
+#define IXP425_ICIH     IXP425_INTC_REG(IXP425_ICIH_OFFSET)
+#define IXP425_ICFH     IXP425_INTC_REG(IXP425_ICFH_OFFSET)
+
+/*
+ * Constants to make it easy to access GPIO registers
+ */
+#define IXP425_GPIO_GPOUTR_OFFSET       0x00
+#define IXP425_GPIO_GPOER_OFFSET        0x04
+#define IXP425_GPIO_GPINR_OFFSET        0x08
+#define IXP425_GPIO_GPISR_OFFSET        0x0C
+#define IXP425_GPIO_GPIT1R_OFFSET	0x10
+#define IXP425_GPIO_GPIT2R_OFFSET	0x14
+#define IXP425_GPIO_GPCLKR_OFFSET	0x18
+#define IXP425_GPIO_GPDBSELR_OFFSET	0x1C
+
+/*
+ * GPIO Register Definitions.
+ * [Only perform 32bit reads/writes]
+ */
+#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_VIRT+(x)))
+
+#define IXP425_GPIO_GPOUTR	IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET)
+#define IXP425_GPIO_GPOER       IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET)
+#define IXP425_GPIO_GPINR       IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET)
+#define IXP425_GPIO_GPISR       IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET)
+#define IXP425_GPIO_GPIT1R      IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET)
+#define IXP425_GPIO_GPIT2R      IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET)
+#define IXP425_GPIO_GPCLKR      IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET)
+#define IXP425_GPIO_GPDBSELR    IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET)
+
+/*
+ * Constants to make it easy to access Timer Control/Status registers
+ */
+#define IXP425_OSTS_OFFSET	0x00  /* Continious TimeStamp */
+#define IXP425_OST1_OFFSET	0x04  /* Timer 1 Timestamp */
+#define IXP425_OSRT1_OFFSET	0x08  /* Timer 1 Reload */
+#define IXP425_OST2_OFFSET	0x0C  /* Timer 2 Timestamp */
+#define IXP425_OSRT2_OFFSET	0x10  /* Timer 2 Reload */
+#define IXP425_OSWT_OFFSET	0x14  /* Watchdog Timer */
+#define IXP425_OSWE_OFFSET	0x18  /* Watchdog Enable */
+#define IXP425_OSWK_OFFSET	0x1C  /* Watchdog Key */
+#define IXP425_OSST_OFFSET	0x20  /* Timer Status */
+
+/*
+ * Operating System Timer Register Definitions.
+ */
+
+#ifndef __ASSEMBLY__
+#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x)))
+#else
+#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
+#endif
+
+#define IXP425_OSTS	IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
+#define IXP425_OST1	IXP425_TIMER_REG(IXP425_OST1_OFFSET)
+#define IXP425_OSRT1	IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
+#define IXP425_OST2	IXP425_TIMER_REG(IXP425_OST2_OFFSET)
+#define IXP425_OSRT2	IXP425_TIMER_REG(IXP425_OSRT2_OFFSET)
+#define IXP425_OSWT	IXP425_TIMER_REG(IXP425_OSWT_OFFSET)
+#define IXP425_OSWE	IXP425_TIMER_REG(IXP425_OSWE_OFFSET)
+#define IXP425_OSWK	IXP425_TIMER_REG(IXP425_OSWK_OFFSET)
+#define IXP425_OSST	IXP425_TIMER_REG(IXP425_OSST_OFFSET)
+
+/*
+ * Timer register values and bit definitions
+ */
+#define IXP425_OST_ENABLE              BIT(0)
+#define IXP425_OST_ONE_SHOT            BIT(1)
+/* Low order bits of reload value ignored */
+#define IXP425_OST_RELOAD_MASK         (0x3)
+#define IXP425_OST_DISABLED            (0x0)
+#define IXP425_OSST_TIMER_1_PEND       BIT(0)
+#define IXP425_OSST_TIMER_2_PEND       BIT(1)
+#define IXP425_OSST_TIMER_TS_PEND      BIT(2)
+#define IXP425_OSST_TIMER_WDOG_PEND    BIT(3)
+#define IXP425_OSST_TIMER_WARM_RESET   BIT(4)
+
+/*
+ * Constants to make it easy to access PCI Control/Status registers
+ */
+#define PCI_NP_AD_OFFSET            0x00
+#define PCI_NP_CBE_OFFSET           0x04
+#define PCI_NP_WDATA_OFFSET         0x08
+#define PCI_NP_RDATA_OFFSET         0x0c
+#define PCI_CRP_AD_CBE_OFFSET       0x10
+#define PCI_CRP_WDATA_OFFSET        0x14
+#define PCI_CRP_RDATA_OFFSET        0x18
+#define PCI_CSR_OFFSET              0x1c
+#define PCI_ISR_OFFSET              0x20
+#define PCI_INTEN_OFFSET            0x24
+#define PCI_DMACTRL_OFFSET          0x28
+#define PCI_AHBMEMBASE_OFFSET       0x2c
+#define PCI_AHBIOBASE_OFFSET        0x30
+#define PCI_PCIMEMBASE_OFFSET       0x34
+#define PCI_AHBDOORBELL_OFFSET      0x38
+#define PCI_PCIDOORBELL_OFFSET      0x3C
+#define PCI_ATPDMA0_AHBADDR_OFFSET  0x40
+#define PCI_ATPDMA0_PCIADDR_OFFSET  0x44
+#define PCI_ATPDMA0_LENADDR_OFFSET  0x48
+#define PCI_ATPDMA1_AHBADDR_OFFSET  0x4C
+#define PCI_ATPDMA1_PCIADDR_OFFSET  0x50
+#define PCI_ATPDMA1_LENADDR_OFFSET	0x54
+
+/*
+ * PCI Control/Status Registers
+ */
+#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_VIRT+(x)))
+
+#define PCI_NP_AD               IXP425_PCI_CSR(PCI_NP_AD_OFFSET)
+#define PCI_NP_CBE              IXP425_PCI_CSR(PCI_NP_CBE_OFFSET)
+#define PCI_NP_WDATA            IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET)
+#define PCI_NP_RDATA            IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET)
+#define PCI_CRP_AD_CBE          IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
+#define PCI_CRP_WDATA           IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET)
+#define PCI_CRP_RDATA           IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET)
+#define PCI_CSR                 IXP425_PCI_CSR(PCI_CSR_OFFSET)
+#define PCI_ISR                 IXP425_PCI_CSR(PCI_ISR_OFFSET)
+#define PCI_INTEN               IXP425_PCI_CSR(PCI_INTEN_OFFSET)
+#define PCI_DMACTRL             IXP425_PCI_CSR(PCI_DMACTRL_OFFSET)
+#define PCI_AHBMEMBASE          IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
+#define PCI_AHBIOBASE           IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET)
+#define PCI_PCIMEMBASE          IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
+#define PCI_AHBDOORBELL         IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
+#define PCI_PCIDOORBELL         IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
+#define PCI_ATPDMA0_AHBADDR     IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
+#define PCI_ATPDMA0_PCIADDR     IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
+#define PCI_ATPDMA0_LENADDR     IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
+#define PCI_ATPDMA1_AHBADDR     IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
+#define PCI_ATPDMA1_PCIADDR     IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
+#define PCI_ATPDMA1_LENADDR     IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
+
+/*
+ * PCI register values and bit definitions
+ */
+
+/* CSR bit definitions */
+#define PCI_CSR_HOST    	BIT(0)
+#define PCI_CSR_ARBEN   	BIT(1)
+#define PCI_CSR_ADS     	BIT(2)
+#define PCI_CSR_PDS     	BIT(3)
+#define PCI_CSR_ABE     	BIT(4)
+#define PCI_CSR_DBT     	BIT(5)
+#define PCI_CSR_ASE     	BIT(8)
+#define PCI_CSR_IC      	BIT(15)
+
+/* ISR (Interrupt status) Register bit definitions */
+#define PCI_ISR_PSE     	BIT(0)
+#define PCI_ISR_PFE     	BIT(1)
+#define PCI_ISR_PPE     	BIT(2)
+#define PCI_ISR_AHBE    	BIT(3)
+#define PCI_ISR_APDC    	BIT(4)
+#define PCI_ISR_PADC    	BIT(5)
+#define PCI_ISR_ADB     	BIT(6)
+#define PCI_ISR_PDB     	BIT(7)
+
+/* INTEN (Interrupt Enable) Register bit definitions */
+#define PCI_INTEN_PSE   	BIT(0)
+#define PCI_INTEN_PFE   	BIT(1)
+#define PCI_INTEN_PPE   	BIT(2)
+#define PCI_INTEN_AHBE  	BIT(3)
+#define PCI_INTEN_APDC  	BIT(4)
+#define PCI_INTEN_PADC  	BIT(5)
+#define PCI_INTEN_ADB   	BIT(6)
+#define PCI_INTEN_PDB   	BIT(7)
+
+/*
+ * Shift value for byte enable on NP cmd/byte enable register
+ */
+#define IXP425_PCI_NP_CBE_BESL		4
+
+/*
+ * PCI commands supported by NP access unit
+ */
+#define NP_CMD_IOREAD			0x2
+#define NP_CMD_IOWRITE			0x3
+#define NP_CMD_CONFIGREAD		0xa
+#define NP_CMD_CONFIGWRITE		0xb
+#define NP_CMD_MEMREAD			0x6
+#define	NP_CMD_MEMWRITE			0x7
+
+#if 0
+#ifndef __ASSEMBLY__
+extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data);
+extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data);
+extern void ixp425_pci_init(void *);
+#endif
+#endif
+
+/*
+ * Constants for CRP access into local config space
+ */
+#define CRP_AD_CBE_BESL         20
+#define CRP_AD_CBE_WRITE        BIT(16)
+
+/*
+ * Clock Speed Definitions.
+ */
+#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS   */
+
+
+#endif
diff --git a/include/asm-arm/arch-ixp/ixp425pci.h b/include/asm-arm/arch-ixp/ixp425pci.h
new file mode 100755
index 0000000..9ea3319
--- /dev/null
+++ b/include/asm-arm/arch-ixp/ixp425pci.h
@@ -0,0 +1,312 @@
+/*
+ * IXP PCI Init
+ * (C) Copyright 2004 eslab.whut.edu.cn
+ * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _IXP425PCI_H_
+#define _IXP425PCI_H_
+
+#define TRUE	1
+#define FALSE	0
+#define OK	0
+#define ERROR	-1
+#define BOOL	int
+
+#define IXP425_PCI_MAX_BAR_PER_FUNC  6
+#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \
+			    IXP425_PCI_MAX_FUNC_ON_BUS)
+
+enum PciBarId
+{
+	CSR_BAR=0,
+	IO_BAR,
+	SD_BAR,
+	NO_BAR
+};
+
+/*Base address register descriptor*/
+typedef struct
+{
+	unsigned int size;
+	unsigned int address;
+} PciBar;
+
+typedef struct
+{
+	unsigned int bus;
+	unsigned int device;
+	unsigned int func;
+	unsigned int irq;
+	BOOL error;
+	unsigned short vendor_id;
+	unsigned short device_id;
+	/*We need an extra entry in this array for dummy placeholder*/
+	PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1];
+} PciDevice;
+
+/* Mask definitions*/
+#define IXP425_PCI_TOP_WORD_OF_LONG_MASK	0xffff0000
+#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK	0xff000000
+#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK	0x0000ffff
+#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff
+#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK	0x0000000f
+#define IXP425_PCI_MAX_UINT32			0xffffffff
+
+
+#define IXP425_PCI_BAR_QUERY			0xffffffff
+
+#define IXP425_PCI_BAR_MEM_BASE 0x100000
+#define IXP425_PCI_BAR_IO_BASE	0x000000
+
+/*define the maximum number of bus segments - we support a single segment*/
+#define IXP425_PCI_MAX_BUS  1
+/*define the maximum number of cards per bus segment*/
+#define IXP425_PCI_MAX_DEV  4
+/*define the maximum number of functions per device*/
+#define IXP425_PCI_MAX_FUNC 8
+/* define the maximum number of separate functions that we can
+   potentially have on the bus*/
+#define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC *	\
+				    IXP425_PCI_MAX_DEV *	\
+				    IXP425_PCI_MAX_BUS)
+/*define the maximum number of BARs per function*/
+#define IXP425_PCI_MAX_BAR_PER_FUNC  6
+#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC *	\
+			    IXP425_PCI_MAX_FUNC_ON_BUS)
+
+#define PCI_NP_CBE_BESL	 (4)
+#define PCI_NP_AD_FUNCSL (8)
+
+#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v))
+#define REG_READ(b,o,v)	 ((v)=(*(volatile unsigned int*)((b+o))))
+
+#define PCI_DELAY	500
+#define USEC_LOOP_COUNT 533
+#define PCI_SETTLE_USEC 200
+#define PCI_MIN_RESET_ASSERT_USEC 2000
+
+/*Register addressing definitions for PCI controller configuration
+  and status registers*/
+
+#define PCI_CSR_BASE (0xC0000000)
+/*
+#define PCI_NP_AD_OFFSET       (0x00)
+#define PCI_NP_CBE_OFFSET      (0x04)
+#define PCI_NP_WDATA_OFFSET    (0x08)
+#define PCI_NP_RDATA_OFFSET    (0x0C)
+#define PCI_CRP_OFFSET	       (0x10)
+#define PCI_CRP_WDATA_OFFSET   (0x14)
+#define PCI_CRP_RDATA_OFFSET   (0x18)
+#define PCI_CSR_OFFSET	       (0x1C)
+#define PCI_ISR_OFFSET	       (0x20)
+#define PCI_INTEN_OFFSET       (0x24)
+#define PCI_DMACTRL_OFFSET     (0x28)
+#define PCI_AHBMEMBASE_OFFSET  (0x2C)
+#define PCI_AHBIOBASE_OFFSET   (0x30)
+#define PCI_PCIMEMBASE_OFFSET  (0x34)
+#define PCI_AHBDOORBELL_OFFSET (0x38)
+#define PCI_PCIDOORBELL_OFFSET (0x3C)
+#define PCI_ATPDMA0_AHBADDR    (0x40)
+#define PCI_ATPDMA0_PCIADDR    (0x44)
+#define PCI_ATPDMA0_LENADDR    (0x48)
+#define PCI_ATPDMA1_AHBADDR    (0x4C)
+#define PCI_ATPDMA1_PCIADDR    (0x50)
+#define PCI_ATPDMA1_LENADDR    (0x54)
+#define PCI_PTADMA0_AHBADDR    (0x58)
+#define PCI_PTADMA0_PCIADDR    (0x5C)
+#define PCI_PTADMA0_LENADDR    (0x60)
+#define PCI_PTADMA1_AHBADDR    (0x64)
+#define PCI_PTADMA1_PCIADDR    (0x68)
+#define PCI_PTADMA1_LENADDR    (0x6C)
+*/
+/*Non prefetch registers bit definitions*/
+/*
+#define NP_CMD_INTACK	   (0x0)
+#define NP_CMD_SPECIAL	   (0x1)
+#define NP_CMD_IOREAD	   (0x2)
+#define NP_CMD_IOWRITE	   (0x3)
+#define NP_CMD_MEMREAD	   (0x6)
+#define NP_CMD_MEMWRITE	   (0x7)
+#define NP_CMD_CONFIGREAD  (0xa)
+#define NP_CMD_CONFIGWRITE (0xb)
+*/
+
+/*define the default setting of the AHB memory base reg*/
+#define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203
+#define IXP425_PCI_AHBIOBASE_DEFAULT  0x0
+#define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0
+
+/*define the default settings for the controller's BARs*/
+#ifdef IXP425_PCI_SIMPLE_MAPPING
+#define IXP425_PCI_BAR_0_DEFAULT 0x00000000
+#define IXP425_PCI_BAR_1_DEFAULT 0x01000000
+#define IXP425_PCI_BAR_2_DEFAULT 0x02000000
+#define IXP425_PCI_BAR_3_DEFAULT 0x03000000
+#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
+#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
+#else
+#define IXP425_PCI_BAR_0_DEFAULT 0x40000000
+#define IXP425_PCI_BAR_1_DEFAULT 0x41000000
+#define IXP425_PCI_BAR_2_DEFAULT 0x42000000
+#define IXP425_PCI_BAR_3_DEFAULT 0x43000000
+#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
+#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
+#endif
+
+/*Configuration Port register bit definitions*/
+#define PCI_CRP_WRITE BIT(16)
+
+/*ISR (Interrupt status) Register bit definitions*/
+#define PCI_ISR_PSE   BIT(0)
+#define PCI_ISR_PFE   BIT(1)
+#define PCI_ISR_PPE   BIT(2)
+#define PCI_ISR_AHBE  BIT(3)
+#define PCI_ISR_APDC  BIT(4)
+#define PCI_ISR_PADC  BIT(5)
+#define PCI_ISR_ADB   BIT(6)
+#define PCI_ISR_PDB   BIT(7)
+
+/*INTEN (Interrupt Enable) Register bit definitions*/
+#define PCI_INTEN_PSE	BIT(0)
+#define PCI_INTEN_PFE	BIT(1)
+#define PCI_INTEN_PPE	BIT(2)
+#define PCI_INTEN_AHBE	BIT(3)
+#define PCI_INTEN_APDC	BIT(4)
+#define PCI_INTEN_PADC	BIT(5)
+#define PCI_INTEN_ADB	BIT(6)
+#define PCI_INTEN_PDB	BIT(7)
+
+/*PCI configuration regs.*/
+
+#define PCI_CFG_VENDOR_ID	0x00
+#define PCI_CFG_DEVICE_ID	0x02
+#define PCI_CFG_COMMAND		0x04
+#define PCI_CFG_STATUS		0x06
+#define PCI_CFG_REVISION	0x08
+#define PCI_CFG_PROGRAMMING_IF	0x09
+#define PCI_CFG_SUBCLASS	0x0a
+#define PCI_CFG_CLASS		0x0b
+#define PCI_CFG_CACHE_LINE_SIZE 0x0c
+#define PCI_CFG_LATENCY_TIMER	0x0d
+#define PCI_CFG_HEADER_TYPE	0x0e
+#define PCI_CFG_BIST		0x0f
+#define PCI_CFG_BASE_ADDRESS_0	0x10
+#define PCI_CFG_BASE_ADDRESS_1	0x14
+#define PCI_CFG_BASE_ADDRESS_2	0x18
+#define PCI_CFG_BASE_ADDRESS_3	0x1c
+#define PCI_CFG_BASE_ADDRESS_4	0x20
+#define PCI_CFG_BASE_ADDRESS_5	0x24
+#define PCI_CFG_CIS		0x28
+#define PCI_CFG_SUB_VENDOR_ID	0x2c
+#define PCI_CFG_SUB_SYSTEM_ID	0x2e
+#define PCI_CFG_EXPANSION_ROM	0x30
+#define PCI_CFG_RESERVED_0	0x34
+#define PCI_CFG_RESERVED_1	0x38
+#define PCI_CFG_DEV_INT_LINE	0x3c
+#define PCI_CFG_DEV_INT_PIN	0x3d
+#define PCI_CFG_MIN_GRANT	0x3e
+#define PCI_CFG_MAX_LATENCY	0x3f
+#define PCI_CFG_SPECIAL_USE	0x41
+#define PCI_CFG_MODE		0x43
+
+/*Specify the initial command we send to PCI devices*/
+#define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE	   \
+			 | PCI_CMD_MEM_ENABLE	   \
+			 | PCI_CMD_MASTER_ENABLE   \
+			 | PCI_CMD_WI_ENABLE)
+
+/*define the sub vendor and subsystem to be used */
+#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
+
+#define PCI_IRQ_LINES		4
+
+#define PCI_CMD_IO_ENABLE	0x0001	/* IO access enable */
+#define PCI_CMD_MEM_ENABLE	0x0002	/* memory access enable */
+#define PCI_CMD_MASTER_ENABLE	0x0004	/* bus master enable */
+#define PCI_CMD_MON_ENABLE	0x0008	/* monitor special cycles enable */
+#define PCI_CMD_WI_ENABLE	0x0010	/* write and invalidate enable */
+#define PCI_CMD_SNOOP_ENABLE	0x0020	/* palette snoop enable */
+#define PCI_CMD_PERR_ENABLE	0x0040	/* parity error enable */
+#define PCI_CMD_WC_ENABLE	0x0080	/* wait cycle enable */
+#define PCI_CMD_SERR_ENABLE	0x0100	/* system error enable */
+#define PCI_CMD_FBTB_ENABLE	0x0200	/* fast back to back enable */
+
+
+/*CSR Register bit definitions*/
+#define PCI_CSR_HOST  BIT(0)
+#define PCI_CSR_ARBEN BIT(1)
+#define PCI_CSR_ADS   BIT(2)
+#define PCI_CSR_PDS   BIT(3)
+#define PCI_CSR_ABE   BIT(4)
+#define PCI_CSR_DBT   BIT(5)
+#define PCI_CSR_ASE   BIT(8)
+#define PCI_CSR_IC    BIT(15)
+
+/*Configuration command bit definitions*/
+#define PCI_CFG_CMD_IOAE BIT(0)
+#define PCI_CFG_CMD_MAE	 BIT(1)
+#define PCI_CFG_CMD_BME	 BIT(2)
+#define PCI_CFG_CMD_MWIE BIT(4)
+#define PCI_CFG_CMD_SER	 BIT(8)
+#define PCI_CFG_CMD_FBBE BIT(9)
+#define PCI_CFG_CMD_MDPE BIT(24)
+#define PCI_CFG_CMD_STA	 BIT(27)
+#define PCI_CFG_CMD_RTA	 BIT(28)
+#define PCI_CFG_CMD_RMA	 BIT(29)
+#define PCI_CFG_CMD_SSE	 BIT(30)
+#define PCI_CFG_CMD_DPE	 BIT(31)
+
+/*DMACTRL DMA Control and status Register*/
+#define PCI_DMACTRL_APDCEN  BIT(0)
+#define PCI_DMACTRL_APDC0   BIT(4)
+#define PCI_DMACTRL_APDE0   BIT(5)
+#define PCI_DMACTRL_APDC1   BIT(6)
+#define PCI_DMACTRL_APDE1   BIT(7)
+#define PCI_DMACTRL_PADCEN  BIT(8)
+#define PCI_DMACTRL_PADC0   BIT(12)
+#define PCI_DMACTRL_PADE0   BIT(13)
+#define PCI_DMACTRL_PADC1   BIT(14)
+#define PCI_DMACTRL_PADE1   BIT(15)
+
+/* GPIO related register */
+#undef IXP425_GPIO_GPOUTR
+#undef IXP425_GPIO_GPOER
+#undef IXP425_GPIO_GPINR
+#undef IXP425_GPIO_GPISR
+#undef IXP425_GPIO_GPIT1R
+#undef IXP425_GPIO_GPIT2R
+#undef IXP425_GPIO_GPCLKR
+
+#define IXP425_GPIO_GPOUTR	0xC8004000
+#define IXP425_GPIO_GPOER	0xC8004004
+#define IXP425_GPIO_GPINR	0xC8004008
+#define IXP425_GPIO_GPISR	0xC800400C
+#define IXP425_GPIO_GPIT1R	0xC8004010
+#define IXP425_GPIO_GPIT2R	0xC8004014
+#define IXP425_GPIO_GPCLKR	0xC8004018
+
+#define READ_GPIO_REG(addr,val) \
+		(val) = *((volatile int *)(addr));
+#define WRITE_GPIO_REG(addr,val) \
+		*((volatile int *)(addr)) = (val);
+
+#endif
diff --git a/include/asm-arm/arch-ks8695/platform.h b/include/asm-arm/arch-ks8695/platform.h
new file mode 100755
index 0000000..de20015
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/platform.h
@@ -0,0 +1,306 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ */
+#ifndef __address_h
+#define __address_h			1
+
+#define KS8695_SDRAM_START	    0x00000000
+#define KS8695_SDRAM_SIZE	    0x01000000
+#define KS8695_MEM_SIZE		    KS8695_SDRAM_SIZE
+#define KS8695_MEM_START	    KS8695_SDRAM_START
+
+#define KS8695_PCMCIA_IO_BASE	    0x03800000
+#define KS8695_PCMCIA_IO_SIZE	    0x00040000
+
+#define KS8695_IO_BASE		    0x03FF0000
+#define KS8695_IO_SIZE		    0x00010000
+
+#define KS8695_SYSTEN_CONFIG	    0x00
+#define KS8695_SYSTEN_BUS_CLOCK	    0x04
+
+#define KS8695_FLASH_START	    0x02800000
+#define KS8695_FLASH_SIZE	    0x00400000
+
+/*i/o control registers offset difinitions*/
+#define KS8695_IO_CTRL0		    0x4000
+#define KS8695_IO_CTRL1		    0x4004
+#define KS8695_IO_CTRL2		    0x4008
+#define KS8695_IO_CTRL3		    0x400C
+
+/*memory control registers offset difinitions*/
+#define KS8695_MEM_CTRL0	    0x4010
+#define KS8695_MEM_CTRL1	    0x4014
+#define KS8695_MEM_CTRL2	    0x4018
+#define KS8695_MEM_CTRL3	    0x401C
+#define KS8695_MEM_GENERAL	    0x4020
+#define KS8695_SDRAM_CTRL0	    0x4030
+#define KS8695_SDRAM_CTRL1	    0x4034
+#define KS8695_SDRAM_GENERAL	    0x4038
+#define KS8695_SDRAM_BUFFER	    0x403C
+#define KS8695_SDRAM_REFRESH	    0x4040
+
+/*WAN control registers offset difinitions*/
+#define KS8695_WAN_DMA_TX	    0x6000
+#define KS8695_WAN_DMA_RX	    0x6004
+#define KS8695_WAN_DMA_TX_START	    0x6008
+#define KS8695_WAN_DMA_RX_START	    0x600C
+#define KS8695_WAN_TX_LIST	    0x6010
+#define KS8695_WAN_RX_LIST	    0x6014
+#define KS8695_WAN_MAC_LOW	    0x6018
+#define KS8695_WAN_MAC_HIGH	    0x601C
+#define KS8695_WAN_MAC_ELOW	    0x6080
+#define KS8695_WAN_MAC_EHIGH	    0x6084
+
+/*LAN control registers offset difinitions*/
+#define KS8695_LAN_DMA_TX	    0x8000
+#define KS8695_LAN_DMA_RX	    0x8004
+#define KS8695_LAN_DMA_TX_START	    0x8008
+#define KS8695_LAN_DMA_RX_START	    0x800C
+#define KS8695_LAN_TX_LIST	    0x8010
+#define KS8695_LAN_RX_LIST	    0x8014
+#define KS8695_LAN_MAC_LOW	    0x8018
+#define KS8695_LAN_MAC_HIGH	    0x801C
+#define KS8695_LAN_MAC_ELOW	    0X8080
+#define KS8695_LAN_MAC_EHIGH	    0X8084
+
+/*HPNA control registers offset difinitions*/
+#define KS8695_HPNA_DMA_TX	    0xA000
+#define KS8695_HPNA_DMA_RX	    0xA004
+#define KS8695_HPNA_DMA_TX_START    0xA008
+#define KS8695_HPNA_DMA_RX_START    0xA00C
+#define KS8695_HPNA_TX_LIST	    0xA010
+#define KS8695_HPNA_RX_LIST	    0xA014
+#define KS8695_HPNA_MAC_LOW	    0xA018
+#define KS8695_HPNA_MAC_HIGH	    0xA01C
+#define KS8695_HPNA_MAC_ELOW	    0xA080
+#define KS8695_HPNA_MAC_EHIGH	    0xA084
+
+/*UART control registers offset difinitions*/
+#define KS8695_UART_RX_BUFFER	    0xE000
+#define KS8695_UART_TX_HOLDING	    0xE004
+
+#define KS8695_UART_FIFO_CTRL	    0xE008
+#define KS8695_UART_FIFO_TRIG01	    0x00
+#define KS8695_UART_FIFO_TRIG04	    0x80
+#define KS8695_UART_FIFO_TXRST	    0x03
+#define KS8695_UART_FIFO_RXRST	    0x02
+#define KS8695_UART_FIFO_FEN	    0x01
+
+#define KS8695_UART_LINE_CTRL	    0xE00C
+#define KS8695_UART_LINEC_BRK	    0x40
+#define KS8695_UART_LINEC_EPS	    0x10
+#define KS8695_UART_LINEC_PEN	    0x08
+#define KS8695_UART_LINEC_STP2	    0x04
+#define KS8695_UART_LINEC_WLEN8	    0x03
+#define KS8695_UART_LINEC_WLEN7	    0x02
+#define KS8695_UART_LINEC_WLEN6	    0x01
+#define KS8695_UART_LINEC_WLEN5	    0x00
+
+#define KS8695_UART_MODEM_CTRL	    0xE010
+#define KS8695_UART_MODEMC_RTS	    0x02
+#define KS8695_UART_MODEMC_DTR	    0x01
+
+#define KS8695_UART_LINE_STATUS	    0xE014
+#define KS8695_UART_LINES_TXFE	    0x20
+#define KS8695_UART_LINES_BE	    0x10
+#define KS8695_UART_LINES_FE	    0x08
+#define KS8695_UART_LINES_PE	    0x04
+#define KS8695_UART_LINES_OE	    0x02
+#define KS8695_UART_LINES_RXFE	    0x01
+#define KS8695_UART_LINES_ANY	    (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
+
+#define KS8695_UART_MODEM_STATUS    0xE018
+#define KS8695_UART_MODEM_DCD	    0x80
+#define KS8695_UART_MODEM_DSR	    0x20
+#define KS8695_UART_MODEM_CTS	    0x10
+#define KS8695_UART_MODEM_DDCD	    0x08
+#define KS8695_UART_MODEM_DDSR	    0x02
+#define KS8695_UART_MODEM_DCTS	    0x01
+#define UART8695_MODEM_ANY	    0xFF
+
+#define KS8695_UART_DIVISOR	    0xE01C
+#define KS8695_UART_STATUS	    0xE020
+
+/*Interrupt controlller registers offset difinitions*/
+#define KS8695_INT_CONTL	    0xE200
+#define KS8695_INT_ENABLE	    0xE204
+#define KS8695_INT_ENABLE_MODEM	    0x0800
+#define KS8695_INT_ENABLE_ERR	    0x0400
+#define KS8695_INT_ENABLE_RX	    0x0200
+#define KS8695_INT_ENABLE_TX	    0x0100
+
+#define KS8695_INT_STATUS	    0xE208
+#define KS8695_INT_WAN_PRIORITY	    0xE20C
+#define KS8695_INT_HPNA_PRIORITY    0xE210
+#define KS8695_INT_LAN_PRIORITY	    0xE214
+#define KS8695_INT_TIMER_PRIORITY   0xE218
+#define KS8695_INT_UART_PRIORITY    0xE21C
+#define KS8695_INT_EXT_PRIORITY	    0xE220
+#define KS8695_INT_CHAN_PRIORITY    0xE224
+#define KS8695_INT_BUSERROR_PRO	    0xE228
+#define KS8695_INT_MASK_STATUS	    0xE22C
+#define KS8695_FIQ_PEND_PRIORITY    0xE230
+#define KS8695_IRQ_PEND_PRIORITY    0xE234
+
+/*timer registers offset difinitions*/
+#define KS8695_TIMER_CTRL	    0xE400
+#define KS8695_TIMER1		    0xE404
+#define KS8695_TIMER0		    0xE408
+#define KS8695_TIMER1_PCOUNT	    0xE40C
+#define KS8695_TIMER0_PCOUNT	    0xE410
+
+/*GPIO registers offset difinitions*/
+#define KS8695_GPIO_MODE	    0xE600
+#define KS8695_GPIO_CTRL	    0xE604
+#define KS8695_GPIO_DATA	    0xE608
+
+/*SWITCH registers offset difinitions*/
+#define KS8695_SWITCH_CTRL0	    0xE800
+#define KS8695_SWITCH_CTRL1	    0xE804
+#define KS8695_SWITCH_PORT1	    0xE808
+#define KS8695_SWITCH_PORT2	    0xE80C
+#define KS8695_SWITCH_PORT3	    0xE810
+#define KS8695_SWITCH_PORT4	    0xE814
+#define KS8695_SWITCH_PORT5	    0xE818
+#define KS8695_SWITCH_AUTO0	    0xE81C
+#define KS8695_SWITCH_AUTO1	    0xE820
+#define KS8695_SWITCH_LUE_CTRL	    0xE824
+#define KS8695_SWITCH_LUE_HIGH	    0xE828
+#define KS8695_SWITCH_LUE_LOW	    0xE82C
+#define KS8695_SWITCH_ADVANCED	    0xE830
+
+#define KS8695_SWITCH_LPPM12	    0xE874
+#define KS8695_SWITCH_LPPM34	    0xE878
+
+/*host communication registers difinitions*/
+#define KS8695_DSCP_HIGH	    0xE834
+#define KS8695_DSCP_LOW		    0xE838
+#define KS8695_SWITCH_MAC_HIGH	    0xE83C
+#define KS8695_SWITCH_MAC_LOW	    0xE840
+
+/*miscellaneours registers difinitions*/
+#define KS8695_MANAGE_COUNTER	    0xE844
+#define KS8695_MANAGE_DATA	    0xE848
+#define KS8695_LAN12_POWERMAGR	    0xE84C
+#define KS8695_LAN34_POWERMAGR	    0xE850
+
+#define KS8695_DEVICE_ID	    0xEA00
+#define KS8695_REVISION_ID	    0xEA04
+
+#define KS8695_MISC_CONTROL	    0xEA08
+#define KS8695_WAN_CONTROL	    0xEA0C
+#define KS8695_WAN_POWERMAGR	    0xEA10
+#define KS8695_WAN_PHY_CONTROL	    0xEA14
+#define KS8695_WAN_PHY_STATUS	    0xEA18
+
+/* bus clock definitions*/
+#define KS8695_BUS_CLOCK_125MHZ	    0x0
+#define KS8695_BUS_CLOCK_100MHZ	    0x1
+#define KS8695_BUS_CLOCK_62MHZ	    0x2
+#define KS8695_BUS_CLOCK_50MHZ	    0x3
+#define KS8695_BUS_CLOCK_41MHZ	    0x4
+#define KS8695_BUS_CLOCK_33MHZ	    0x5
+#define KS8695_BUS_CLOCK_31MHZ	    0x6
+#define KS8695_BUS_CLOCK_25MHZ	    0x7
+
+/* -------------------------------------------------------------------------------
+ *  definations for IRQ
+ * -------------------------------------------------------------------------------*/
+
+#define KS8695_INT_EXT_INT0		       2
+#define KS8695_INT_EXT_INT1		       3
+#define KS8695_INT_EXT_INT2		       4
+#define KS8695_INT_EXT_INT3		       5
+#define KS8695_INT_TIMERINT0		       6
+#define KS8695_INT_TIMERINT1		       7
+#define KS8695_INT_UART_TX		       8
+#define KS8695_INT_UART_RX		       9
+#define KS8695_INT_UART_LINE_ERR	       10
+#define KS8695_INT_UART_MODEMS		       11
+#define KS8695_INT_LAN_STOP_RX		       12
+#define KS8695_INT_LAN_STOP_TX		       13
+#define KS8695_INT_LAN_BUF_RX_STATUS	       14
+#define KS8695_INT_LAN_BUF_TX_STATUS	       15
+#define KS8695_INT_LAN_RX_STATUS	       16
+#define KS8695_INT_LAN_TX_STATUS	       17
+#define KS8695_INT_HPAN_STOP_RX		       18
+#define KS8695_INT_HPNA_STOP_TX		       19
+#define KS8695_INT_HPNA_BUF_RX_STATUS	       20
+#define KS8695_INT_HPNA_BUF_TX_STATUS	       21
+#define KS8695_INT_HPNA_RX_STATUS	       22
+#define KS8695_INT_HPNA_TX_STATUS	       23
+#define KS8695_INT_BUS_ERROR		       24
+#define KS8695_INT_WAN_STOP_RX		       25
+#define KS8695_INT_WAN_STOP_TX		       26
+#define KS8695_INT_WAN_BUF_RX_STATUS	       27
+#define KS8695_INT_WAN_BUF_TX_STATUS	       28
+#define KS8695_INT_WAN_RX_STATUS	       29
+#define KS8695_INT_WAN_TX_STATUS	       30
+
+#define KS8695_INT_UART			       KS8695_INT_UART_TX
+
+/* -------------------------------------------------------------------------------
+ *  Interrupt bit positions
+ *
+ * -------------------------------------------------------------------------------
+ */
+
+#define KS8695_INTMASK_EXT_INT0		       ( 1 << KS8695_INT_EXT_INT0 )
+#define KS8695_INTMASK_EXT_INT1		       ( 1 << KS8695_INT_EXT_INT1 )
+#define KS8695_INTMASK_EXT_INT2		       ( 1 << KS8695_INT_EXT_INT2 )
+#define KS8695_INTMASK_EXT_INT3		       ( 1 << KS8695_INT_EXT_INT3 )
+#define KS8695_INTMASK_TIMERINT0	       ( 1 << KS8695_INT_TIMERINT0 )
+#define KS8695_INTMASK_TIMERINT1	       ( 1 << KS8695_INT_TIMERINT1 )
+#define KS8695_INTMASK_UART_TX		       ( 1 << KS8695_INT_UART_TX  )
+#define KS8695_INTMASK_UART_RX		       ( 1 << KS8695_INT_UART_RX  )
+#define KS8695_INTMASK_UART_LINE_ERR	       ( 1 << KS8695_INT_UART_LINE_ERR )
+#define KS8695_INTMASK_UART_MODEMS	       ( 1 << KS8695_INT_UART_MODEMS )
+#define KS8695_INTMASK_LAN_STOP_RX	       ( 1 << KS8695_INT_LAN_STOP_RX )
+#define KS8695_INTMASK_LAN_STOP_TX	       ( 1 << KS8695_INT_LAN_STOP_TX )
+#define KS8695_INTMASK_LAN_BUF_RX_STATUS       ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
+#define KS8695_INTMASK_LAN_BUF_TX_STATUS       ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
+#define KS8695_INTMASK_LAN_RX_STATUS	       ( 1 << KS8695_INT_LAN_RX_STATUS )
+#define KS8695_INTMASK_LAN_TX_STATUS	       ( 1 << KS8695_INT_LAN_RX_STATUS )
+#define KS8695_INTMASK_HPAN_STOP_RX	       ( 1 << KS8695_INT_HPAN_STOP_RX )
+#define KS8695_INTMASK_HPNA_STOP_TX	       ( 1 << KS8695_INT_HPNA_STOP_TX )
+#define KS8695_INTMASK_HPNA_BUF_RX_STATUS      ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
+#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS      ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
+#define KS8695_INTMASK_HPNA_RX_STATUS	       ( 1 << KS8695_INT_HPNA_RX_STATUS )
+#define KS8695_INTMASK_HPNA_TX_STATUS	       ( 1 << KS8695_INT_HPNA_TX_STATUS )
+#define KS8695_INTMASK_BUS_ERROR	       ( 1 << KS8695_INT_BUS_ERROR )
+#define KS8695_INTMASK_WAN_STOP_RX	       ( 1 << KS8695_INT_WAN_STOP_RX )
+#define KS8695_INTMASK_WAN_STOP_TX	       ( 1 << KS8695_INT_WAN_STOP_TX )
+#define KS8695_INTMASK_WAN_BUF_RX_STATUS       ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
+#define KS8695_INTMASK_WAN_BUF_TX_STATUS       ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
+#define KS8695_INTMASK_WAN_RX_STATUS	       ( 1 << KS8695_INT_WAN_RX_STATUS )
+#define KS8695_INTMASK_WAN_TX_STATUS	       ( 1 << KS8695_INT_WAN_TX_STATUS )
+
+#define KS8695_SC_VALID_INT		       0xFFFFFFFF
+#define MAXIRQNUM			       31
+
+/*
+ *  Timer definitions
+ *
+ *  Use timer 1 & 2
+ *  (both run at 25MHz).
+ *
+ */
+#define TICKS_PER_uSEC			25
+#define mSEC_1				1000
+#define mSEC_10				(mSEC_1 * 10)
+
+#endif
+
+/*	END */
diff --git a/include/asm-arm/arch-pxa/bitfield.h b/include/asm-arm/arch-pxa/bitfield.h
new file mode 100755
index 0000000..2ac5ea2
--- /dev/null
+++ b/include/asm-arm/arch-pxa/bitfield.h
@@ -0,0 +1,112 @@
+/*
+ *	FILE    	bitfield.h
+ *
+ *	Version 	1.1
+ *	Author  	Copyright (c) Marc A. Viredaz, 1998
+ *	        	DEC Western Research Laboratory, Palo Alto, CA
+ *	Date    	April 1998 (April 1997)
+ *	System  	Advanced RISC Machine (ARM)
+ *	Language	C or ARM Assembly
+ *	Purpose 	Definition of macros to operate on bit fields.
+ */
+
+
+#ifndef __BITFIELD_H
+#define __BITFIELD_H
+
+#ifndef __ASSEMBLY__
+#define UData(Data)	((unsigned long) (Data))
+#else
+#define UData(Data)	(Data)
+#endif
+
+
+/*
+ * MACRO: Fld
+ *
+ * Purpose
+ *    The macro "Fld" encodes a bit field, given its size and its shift value
+ *    with respect to bit 0.
+ *
+ * Note
+ *    A more intuitive way to encode bit fields would have been to use their
+ *    mask. However, extracting size and shift value information from a bit
+ *    field's mask is cumbersome and might break the assembler (255-character
+ *    line-size limit).
+ *
+ * Input
+ *    Size      	Size of the bit field, in number of bits.
+ *    Shft      	Shift value of the bit field with respect to bit 0.
+ *
+ * Output
+ *    Fld       	Encoded bit field.
+ */
+
+#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
+
+
+/*
+ * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
+ *
+ * Purpose
+ *    The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
+ *    the size, shift value, mask, aligned mask, and first bit of a
+ *    bit field.
+ *
+ * Input
+ *    Field     	Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FSize     	Size of the bit field, in number of bits.
+ *    FShft     	Shift value of the bit field with respect to bit 0.
+ *    FMsk      	Mask for the bit field.
+ *    FAlnMsk   	Mask for the bit field, aligned on bit 0.
+ *    F1stBit   	First bit of the bit field.
+ */
+
+#define FSize(Field)	((Field) >> 16)
+#define FShft(Field)	((Field) & 0x0000FFFF)
+#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
+#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
+#define F1stBit(Field)	(UData (1) << FShft (Field))
+
+
+/*
+ * MACRO: FInsrt
+ *
+ * Purpose
+ *    The macro "FInsrt" inserts a value into a bit field by shifting the
+ *    former appropriately.
+ *
+ * Input
+ *    Value     	Bit-field value.
+ *    Field     	Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FInsrt    	Bit-field value positioned appropriately.
+ */
+
+#define FInsrt(Value, Field) \
+			(UData (Value) << FShft (Field))
+
+
+/*
+ * MACRO: FExtr
+ *
+ * Purpose
+ *    The macro "FExtr" extracts the value of a bit field by masking and
+ *    shifting it appropriately.
+ *
+ * Input
+ *    Data      	Data containing the bit-field to be extracted.
+ *    Field     	Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FExtr     	Bit-field value.
+ */
+
+#define FExtr(Data, Field) \
+			((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
+
+
+#endif /* __BITFIELD_H */
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
new file mode 100755
index 0000000..3ff1d26
--- /dev/null
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -0,0 +1,154 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/hardware.h
+ *
+ *  Author:	Nicolas Pitre
+ *  Created:	Jun 15, 2001
+ *  Copyright:	MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Note: This file was taken from linux-2.4.19-rmk4-pxa1
+ *
+ * - 2003/01/20 implementation specifics activated
+ *   Robert Schwebel <r.schwebel@pengutronix.de>
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/config.h>
+#include <asm/mach-types.h>
+
+
+/*
+ * These are statically mapped PCMCIA IO space for designs using it as a
+ * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
+ * The actual PCMCIA code is mapping required IO region at run time.
+ */
+#define PCMCIA_IO_0_BASE	0xf6000000
+#define PCMCIA_IO_1_BASE	0xf7000000
+
+
+/*
+ * We requires absolute addresses.
+ */
+#define PCIO_BASE		0
+
+/*
+ * Workarounds for at least 2 errata so far require this.
+ * The mapping is set in mach-pxa/generic.c.
+ */
+#define UNCACHED_PHYS_0		0xff000000
+#define UNCACHED_ADDR		UNCACHED_PHYS_0
+
+/*
+ * Intel PXA internal I/O mappings:
+ *
+ * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
+ * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
+ * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
+ */
+
+/* FIXME: Only this does work for u-boot... find out why... [RS] */
+#define UBOOT_REG_FIX 1
+
+#ifndef UBOOT_REG_FIX
+#ifndef __ASSEMBLY__
+
+#define io_p2v(x)	( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
+#define io_v2p( x )	( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
+
+/*
+ * This __REG() version gives the same results as the one above,  except
+ * that we are fooling gcc somehow so it generates far better and smaller
+ * assembly code for access to contigous registers.  It's a shame that gcc
+ * doesn't guess this by itself.
+ */
+#include <asm/types.h>
+typedef struct { volatile u32 offset[4096]; } __regbase;
+# define __REGP(x)	((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
+# define __REG(x)	__REGP(io_p2v(x))
+#endif
+
+/* Let's kick gcc's ass again... */
+# define __REG2(x,y)	\
+	( __builtin_constant_p(y) ? (__REG((x) + (y))) \
+				  : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
+
+# define __PREG(x)	(io_v2p((u32)&(x)))
+
+#else
+
+# define __REG(x)	io_p2v(x)
+# define __PREG(x)	io_v2p(x)
+
+# undef io_p2v
+# undef __REG
+# ifndef __ASSEMBLY__
+#  define io_p2v(PhAdd)	   (PhAdd)
+#  define __REG(x)	(*((volatile u32 *)io_p2v(x)))
+#  define __REG2(x,y)	(*(volatile u32 *)((u32)&__REG(x) + (y)))
+# else
+#  define __REG(x) (x)
+# endif
+#endif /* UBOOT_REG_FIX */
+
+#include "pxa-regs.h"
+
+#ifndef __ASSEMBLY__
+
+/*
+ * GPIO edge detection for IRQs:
+ * IRQs are generated on Falling-Edge, Rising-Edge, or both.
+ * This must be called *before* the corresponding IRQ is registered.
+ * Use this instead of directly setting GRER/GFER.
+ */
+#define GPIO_FALLING_EDGE	1
+#define GPIO_RISING_EDGE	2
+#define GPIO_BOTH_EDGES		3
+extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask );
+
+/*
+ * Handy routine to set GPIO alternate functions
+ */
+extern void set_GPIO_mode( int gpio_mode );
+
+/*
+ * return current lclk frequency in units of 10kHz
+ */
+extern unsigned int get_lclk_frequency_10khz(void);
+
+#endif
+
+
+/*
+ * Implementation specifics
+ */
+
+#ifdef CONFIG_ARCH_LUBBOCK
+#include "lubbock.h"
+#endif
+
+#ifdef CONFIG_ARCH_PXA_IDP
+#include "idp.h"
+#endif
+
+#ifdef CONFIG_ARCH_PXA_CERF
+#include "cerf.h"
+#endif
+
+#ifdef CONFIG_ARCH_CSB226
+#include "csb226.h"
+#endif
+
+#ifdef CONFIG_ARCH_INNOKOM
+#include "innokom.h"
+#endif
+
+#ifdef CONFIG_ARCH_PLEB
+#include "pleb.h"
+#endif
+
+#endif	/* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
new file mode 100755
index 0000000..a62679a
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mmc.h
@@ -0,0 +1,200 @@
+/*
+ *  linux/drivers/mmc/mmc_pxa.h
+ *
+ *  Author: Vladimir Shebordaev, Igor Oblakov
+ *  Copyright:  MontaVista Software Inc.
+ *
+ *  $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#ifndef __MMC_PXA_P_H__
+#define __MMC_PXA_P_H__
+
+/* PXA-250 MMC controller registers */
+
+/* MMC_STRPCL */
+#define MMC_STRPCL_STOP_CLK     	(0x0001UL)
+#define MMC_STRPCL_START_CLK		(0x0002UL)
+
+/* MMC_STAT */
+#define MMC_STAT_END_CMD_RES		(0x0001UL << 13)
+#define MMC_STAT_PRG_DONE       	(0x0001UL << 12)
+#define MMC_STAT_DATA_TRAN_DONE     	(0x0001UL << 11)
+#define MMC_STAT_CLK_EN	 		(0x0001UL << 8)
+#define MMC_STAT_RECV_FIFO_FULL     	(0x0001UL << 7)
+#define MMC_STAT_XMIT_FIFO_EMPTY    	(0x0001UL << 6)
+#define MMC_STAT_RES_CRC_ERROR      	(0x0001UL << 5)
+#define MMC_STAT_SPI_READ_ERROR_TOKEN   (0x0001UL << 4)
+#define MMC_STAT_CRC_READ_ERROR     	(0x0001UL << 3)
+#define MMC_STAT_CRC_WRITE_ERROR    	(0x0001UL << 2)
+#define MMC_STAT_TIME_OUT_RESPONSE  	(0x0001UL << 1)
+#define MMC_STAT_READ_TIME_OUT      	(0x0001UL)
+
+#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
+	|MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
+	|MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
+
+/* MMC_CLKRT */
+#define MMC_CLKRT_20MHZ	 		(0x0000UL)
+#define MMC_CLKRT_10MHZ	 		(0x0001UL)
+#define MMC_CLKRT_5MHZ	  		(0x0002UL)
+#define MMC_CLKRT_2_5MHZ		(0x0003UL)
+#define MMC_CLKRT_1_25MHZ       	(0x0004UL)
+#define MMC_CLKRT_0_625MHZ      	(0x0005UL)
+#define MMC_CLKRT_0_3125MHZ     	(0x0006UL)
+
+/* MMC_SPI */
+#define MMC_SPI_DISABLE	 		(0x00UL)
+#define MMC_SPI_EN	  		(0x01UL)
+#define MMC_SPI_CS_EN	   		(0x01UL << 2)
+#define MMC_SPI_CS_ADDRESS      	(0x01UL << 3)
+#define MMC_SPI_CRC_ON	  		(0x01UL << 1)
+
+/* MMC_CMDAT */
+#define MMC_CMDAT_MMC_DMA_EN		(0x0001UL << 7)
+#define MMC_CMDAT_INIT	  		(0x0001UL << 6)
+#define MMC_CMDAT_BUSY	  		(0x0001UL << 5)
+#define MMC_CMDAT_STREAM		(0x0001UL << 4)
+#define MMC_CMDAT_BLOCK	 		(0x0000UL << 4)
+#define MMC_CMDAT_WRITE	 		(0x0001UL << 3)
+#define MMC_CMDAT_READ	  		(0x0000UL << 3)
+#define MMC_CMDAT_DATA_EN       	(0x0001UL << 2)
+#define MMC_CMDAT_R1	    		(0x0001UL)
+#define MMC_CMDAT_R2	    		(0x0002UL)
+#define MMC_CMDAT_R3	    		(0x0003UL)
+
+/* MMC_RESTO */
+#define MMC_RES_TO_MAX	  		(0x007fUL) /* [6:0] */
+
+/* MMC_RDTO */
+#define MMC_READ_TO_MAX	 		(0x0ffffUL) /* [15:0] */
+
+/* MMC_BLKLEN */
+#define MMC_BLK_LEN_MAX	 		(0x03ffUL) /* [9:0] */
+
+/* MMC_PRTBUF */
+#define MMC_PRTBUF_BUF_PART_FULL       	(0x01UL)
+#define MMC_PRTBUF_BUF_FULL		(0x00UL    )
+
+/* MMC_I_MASK */
+#define MMC_I_MASK_TXFIFO_WR_REQ	(0x01UL << 6)
+#define MMC_I_MASK_RXFIFO_RD_REQ	(0x01UL << 5)
+#define MMC_I_MASK_CLK_IS_OFF	   	(0x01UL << 4)
+#define MMC_I_MASK_STOP_CMD	 	(0x01UL << 3)
+#define MMC_I_MASK_END_CMD_RES	  	(0x01UL << 2)
+#define MMC_I_MASK_PRG_DONE	 	(0x01UL << 1)
+#define MMC_I_MASK_DATA_TRAN_DONE       (0x01UL)
+#define MMC_I_MASK_ALL	      		(0x07fUL)
+
+
+/* MMC_I_REG */
+#define MMC_I_REG_TXFIFO_WR_REQ     	(0x01UL << 6)
+#define MMC_I_REG_RXFIFO_RD_REQ     	(0x01UL << 5)
+#define MMC_I_REG_CLK_IS_OFF		(0x01UL << 4)
+#define MMC_I_REG_STOP_CMD      	(0x01UL << 3)
+#define MMC_I_REG_END_CMD_RES       	(0x01UL << 2)
+#define MMC_I_REG_PRG_DONE      	(0x01UL << 1)
+#define MMC_I_REG_DATA_TRAN_DONE    	(0x01UL)
+#define MMC_I_REG_ALL	   		(0x007fUL)
+
+/* MMC_CMD */
+#define MMC_CMD_INDEX_MAX       	(0x006fUL)  /* [5:0] */
+#define CMD(x)  (x)
+
+#define MMC_DEFAULT_RCA			1
+
+#define MMC_BLOCK_SIZE			512
+#define MMC_CMD_RESET			0
+#define MMC_CMD_SEND_OP_COND		1
+#define MMC_CMD_ALL_SEND_CID 		2
+#define MMC_CMD_SET_RCA			3
+#define MMC_CMD_SEND_CSD 		9
+#define MMC_CMD_SEND_CID 		10
+#define MMC_CMD_SEND_STATUS		13
+#define MMC_CMD_SET_BLOCKLEN		16
+#define MMC_CMD_READ_BLOCK		17
+#define MMC_CMD_RD_BLK_MULTI		18
+#define MMC_CMD_WRITE_BLOCK		24
+
+#define MMC_MAX_BLOCK_SIZE		512
+
+#define MMC_R1_IDLE_STATE		0x01
+#define MMC_R1_ERASE_STATE		0x02
+#define MMC_R1_ILLEGAL_CMD		0x04
+#define MMC_R1_COM_CRC_ERR		0x08
+#define MMC_R1_ERASE_SEQ_ERR		0x01
+#define MMC_R1_ADDR_ERR			0x02
+#define MMC_R1_PARAM_ERR		0x04
+
+#define MMC_R1B_WP_ERASE_SKIP		0x0002
+#define MMC_R1B_ERR			0x0004
+#define MMC_R1B_CC_ERR			0x0008
+#define MMC_R1B_CARD_ECC_ERR		0x0010
+#define MMC_R1B_WP_VIOLATION		0x0020
+#define MMC_R1B_ERASE_PARAM		0x0040
+#define MMC_R1B_OOR			0x0080
+#define MMC_R1B_IDLE_STATE		0x0100
+#define MMC_R1B_ERASE_RESET		0x0200
+#define MMC_R1B_ILLEGAL_CMD		0x0400
+#define MMC_R1B_COM_CRC_ERR		0x0800
+#define MMC_R1B_ERASE_SEQ_ERR		0x1000
+#define MMC_R1B_ADDR_ERR		0x2000
+#define MMC_R1B_PARAM_ERR		0x4000
+
+typedef struct mmc_cid
+{
+/* FIXME: BYTE_ORDER */
+   uchar year:4,
+   month:4;
+   uchar sn[3];
+   uchar fwrev:4,
+   hwrev:4;
+   uchar name[6];
+   uchar id[3];
+} mmc_cid_t;
+
+typedef struct mmc_csd
+{
+	uchar	ecc:2,
+		file_format:2,
+		tmp_write_protect:1,
+		perm_write_protect:1,
+		copy:1,
+		file_format_grp:1;
+	uint64_t content_prot_app:1,
+		rsvd3:4,
+		write_bl_partial:1,
+		write_bl_len:4,
+		r2w_factor:3,
+		default_ecc:2,
+		wp_grp_enable:1,
+		wp_grp_size:5,
+		erase_grp_mult:5,
+		erase_grp_size:5,
+		c_size_mult1:3,
+		vdd_w_curr_max:3,
+		vdd_w_curr_min:3,
+		vdd_r_curr_max:3,
+		vdd_r_curr_min:3,
+		c_size:12,
+		rsvd2:2,
+		dsr_imp:1,
+		read_blk_misalign:1,
+		write_blk_misalign:1,
+		read_bl_partial:1;
+
+	ushort	read_bl_len:4,
+		ccc:12;
+	uchar	tran_speed;
+	uchar	nsac;
+	uchar	taac;
+	uchar	rsvd1:2,
+  		spec_vers:4,
+		csd_structure:2;
+} mmc_csd_t;
+
+
+#endif /* __MMC_PXA_P_H__ */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
new file mode 100755
index 0000000..41d37d7
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -0,0 +1,1749 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/pxa-regs.h
+ *
+ *  Author:	Nicolas Pitre
+ *  Created:	Jun 15, 2001
+ *  Copyright:	MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
+ *   Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
+ *   Added include for hardware.h (for __REG definition)
+ */
+#ifndef _PXA_REGS_H_
+#define _PXA_REGS_H_
+
+#include "bitfield.h"
+#include "hardware.h"
+
+/* FIXME hack so that SA-1111.h will work [cb] */
+
+#ifndef __ASSEMBLY__
+typedef unsigned short	Word16 ;
+typedef unsigned int	Word32 ;
+typedef Word32		Word ;
+typedef Word		Quad [4] ;
+typedef void		*Address ;
+typedef void		(*ExcpHndlr) (void) ;
+#endif
+
+/*
+ * PXA Chip selects
+ */
+#define PXA_CS0_PHYS	0x00000000
+#define PXA_CS1_PHYS	0x04000000
+#define PXA_CS2_PHYS	0x08000000
+#define PXA_CS3_PHYS	0x0C000000
+#define PXA_CS4_PHYS	0x10000000
+#define PXA_CS5_PHYS	0x14000000
+
+/*
+ * Personal Computer Memory Card International Association (PCMCIA) sockets
+ */
+#define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
+#define PCMCIASp	(4*PCMCIAPrtSp) /* PCMCIA Space [byte]		   */
+#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]	   */
+#define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
+#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]	   */
+
+#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]	   */
+#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]	   */
+#define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
+#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]	   */
+
+#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]	   */
+#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]	   */
+#define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
+#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]	   */
+
+#define _PCMCIA(Nb)			/* PCMCIA [0..1]		   */ \
+			(0x20000000 + (Nb)*PCMCIASp)
+#define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]		   */
+#define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]	   */ \
+			(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
+#define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]		   */ \
+			(_PCMCIA (Nb) + 3*PCMCIAPrtSp)
+
+#define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0			   */
+#define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O			   */
+#define _PCMCIA0Attr	_PCMCIAAttr (0) /* PCMCIA 0 Attribute		   */
+#define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory		   */
+
+#define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1			   */
+#define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O			   */
+#define _PCMCIA1Attr	_PCMCIAAttr (1) /* PCMCIA 1 Attribute		   */
+#define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory		   */
+
+/*
+ * DMA Controller
+ */
+#define DCSR0		__REG(0x40000000)  /* DMA Control / Status Register for Channel 0 */
+#define DCSR1		__REG(0x40000004)  /* DMA Control / Status Register for Channel 1 */
+#define DCSR2		__REG(0x40000008)  /* DMA Control / Status Register for Channel 2 */
+#define DCSR3		__REG(0x4000000c)  /* DMA Control / Status Register for Channel 3 */
+#define DCSR4		__REG(0x40000010)  /* DMA Control / Status Register for Channel 4 */
+#define DCSR5		__REG(0x40000014)  /* DMA Control / Status Register for Channel 5 */
+#define DCSR6		__REG(0x40000018)  /* DMA Control / Status Register for Channel 6 */
+#define DCSR7		__REG(0x4000001c)  /* DMA Control / Status Register for Channel 7 */
+#define DCSR8		__REG(0x40000020)  /* DMA Control / Status Register for Channel 8 */
+#define DCSR9		__REG(0x40000024)  /* DMA Control / Status Register for Channel 9 */
+#define DCSR10		__REG(0x40000028)  /* DMA Control / Status Register for Channel 10 */
+#define DCSR11		__REG(0x4000002c)  /* DMA Control / Status Register for Channel 11 */
+#define DCSR12		__REG(0x40000030)  /* DMA Control / Status Register for Channel 12 */
+#define DCSR13		__REG(0x40000034)  /* DMA Control / Status Register for Channel 13 */
+#define DCSR14		__REG(0x40000038)  /* DMA Control / Status Register for Channel 14 */
+#define DCSR15		__REG(0x4000003c)  /* DMA Control / Status Register for Channel 15 */
+
+#define DCSR(x)		__REG2(0x40000000, (x) << 2)
+
+#define DCSR_RUN	(1 << 31)	/* Run Bit (read / write) */
+#define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */
+#define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */
+
+#if defined(CONFIG_PXA27X)
+#define DCSR_EORIRQEN	(1 << 28)	/* End of Receive Interrupt Enable (R/W) */
+#define DCSR_EORJMPEN	(1 << 27)	/* Jump to next descriptor on EOR */
+#define DCSR_EORSTOPEN	(1 << 26)	/* STOP on an EOR */
+#define DCSR_SETCMPST	(1 << 25)	/* Set Descriptor Compare Status */
+#define DCSR_CLRCMPST	(1 << 24)	/* Clear Descriptor Compare Status */
+#define DCSR_CMPST	(1 << 10)	/* The Descriptor Compare Status */
+#define DCSR_ENRINTR	(1 << 9)	/* The end of Receive */
+#endif
+
+#define DCSR_REQPEND	(1 << 8)	/* Request Pending (read-only) */
+#define DCSR_STOPSTATE	(1 << 3)	/* Stop State (read-only) */
+#define DCSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write) */
+#define DCSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write) */
+#define DCSR_BUSERR	(1 << 0)	/* Bus Error Interrupt (read / write) */
+
+#define DINT		__REG(0x400000f0)  /* DMA Interrupt Register */
+
+#define DRCMR0		__REG(0x40000100)  /* Request to Channel Map Register for DREQ 0 */
+#define DRCMR1		__REG(0x40000104)  /* Request to Channel Map Register for DREQ 1 */
+#define DRCMR2		__REG(0x40000108)  /* Request to Channel Map Register for I2S receive Request */
+#define DRCMR3		__REG(0x4000010c)  /* Request to Channel Map Register for I2S transmit Request */
+#define DRCMR4		__REG(0x40000110)  /* Request to Channel Map Register for BTUART receive Request */
+#define DRCMR5		__REG(0x40000114)  /* Request to Channel Map Register for BTUART transmit Request. */
+#define DRCMR6		__REG(0x40000118)  /* Request to Channel Map Register for FFUART receive Request */
+#define DRCMR7		__REG(0x4000011c)  /* Request to Channel Map Register for FFUART transmit Request */
+#define DRCMR8		__REG(0x40000120)  /* Request to Channel Map Register for AC97 microphone Request */
+#define DRCMR9		__REG(0x40000124)  /* Request to Channel Map Register for AC97 modem receive Request */
+#define DRCMR10		__REG(0x40000128)  /* Request to Channel Map Register for AC97 modem transmit Request */
+#define DRCMR11		__REG(0x4000012c)  /* Request to Channel Map Register for AC97 audio receive Request */
+#define DRCMR12		__REG(0x40000130)  /* Request to Channel Map Register for AC97 audio transmit Request */
+#define DRCMR13		__REG(0x40000134)  /* Request to Channel Map Register for SSP receive Request */
+#define DRCMR14		__REG(0x40000138)  /* Request to Channel Map Register for SSP transmit Request */
+#define DRCMR15		__REG(0x4000013c)  /* Reserved */
+#define DRCMR16		__REG(0x40000140)  /* Reserved */
+#define DRCMR17		__REG(0x40000144)  /* Request to Channel Map Register for ICP receive Request */
+#define DRCMR18		__REG(0x40000148)  /* Request to Channel Map Register for ICP transmit Request */
+#define DRCMR19		__REG(0x4000014c)  /* Request to Channel Map Register for STUART receive Request */
+#define DRCMR20		__REG(0x40000150)  /* Request to Channel Map Register for STUART transmit Request */
+#define DRCMR21		__REG(0x40000154)  /* Request to Channel Map Register for MMC receive Request */
+#define DRCMR22		__REG(0x40000158)  /* Request to Channel Map Register for MMC transmit Request */
+#define DRCMR23		__REG(0x4000015c)  /* Reserved */
+#define DRCMR24		__REG(0x40000160)  /* Reserved */
+#define DRCMR25		__REG(0x40000164)  /* Request to Channel Map Register for USB endpoint 1 Request */
+#define DRCMR26		__REG(0x40000168)  /* Request to Channel Map Register for USB endpoint 2 Request */
+#define DRCMR27		__REG(0x4000016C)  /* Request to Channel Map Register for USB endpoint 3 Request */
+#define DRCMR28		__REG(0x40000170)  /* Request to Channel Map Register for USB endpoint 4 Request */
+#define DRCMR29		__REG(0x40000174)  /* Reserved */
+#define DRCMR30		__REG(0x40000178)  /* Request to Channel Map Register for USB endpoint 6 Request */
+#define DRCMR31		__REG(0x4000017C)  /* Request to Channel Map Register for USB endpoint 7 Request */
+#define DRCMR32		__REG(0x40000180)  /* Request to Channel Map Register for USB endpoint 8 Request */
+#define DRCMR33		__REG(0x40000184)  /* Request to Channel Map Register for USB endpoint 9 Request */
+#define DRCMR34		__REG(0x40000188)  /* Reserved */
+#define DRCMR35		__REG(0x4000018C)  /* Request to Channel Map Register for USB endpoint 11 Request */
+#define DRCMR36		__REG(0x40000190)  /* Request to Channel Map Register for USB endpoint 12 Request */
+#define DRCMR37		__REG(0x40000194)  /* Request to Channel Map Register for USB endpoint 13 Request */
+#define DRCMR38		__REG(0x40000198)  /* Request to Channel Map Register for USB endpoint 14 Request */
+#define DRCMR39		__REG(0x4000019C)  /* Reserved */
+
+#define DRCMR68		       __REG(0x40001110)  /* Request to Channel Map Register for Camera FIFO 0 Request */
+#define DRCMR69		       __REG(0x40001114)  /* Request to Channel Map Register for Camera FIFO 1 Request */
+#define DRCMR70		       __REG(0x40001118)  /* Request to Channel Map Register for Camera FIFO 2 Request */
+
+#define DRCMRRXSADR	DRCMR2
+#define DRCMRTXSADR	DRCMR3
+#define DRCMRRXBTRBR	DRCMR4
+#define DRCMRTXBTTHR	DRCMR5
+#define DRCMRRXFFRBR	DRCMR6
+#define DRCMRTXFFTHR	DRCMR7
+#define DRCMRRXMCDR	DRCMR8
+#define DRCMRRXMODR	DRCMR9
+#define DRCMRTXMODR	DRCMR10
+#define DRCMRRXPCDR	DRCMR11
+#define DRCMRTXPCDR	DRCMR12
+#define DRCMRRXSSDR	DRCMR13
+#define DRCMRTXSSDR	DRCMR14
+#define DRCMRRXICDR	DRCMR17
+#define DRCMRTXICDR	DRCMR18
+#define DRCMRRXSTRBR	DRCMR19
+#define DRCMRTXSTTHR	DRCMR20
+#define DRCMRRXMMC	DRCMR21
+#define DRCMRTXMMC	DRCMR22
+
+#define DRCMR_MAPVLD	(1 << 7)	/* Map Valid (read / write) */
+#define DRCMR_CHLNUM	0x0f		/* mask for Channel Number (read / write) */
+
+#define DDADR0		__REG(0x40000200)  /* DMA Descriptor Address Register Channel 0 */
+#define DSADR0		__REG(0x40000204)  /* DMA Source Address Register Channel 0 */
+#define DTADR0		__REG(0x40000208)  /* DMA Target Address Register Channel 0 */
+#define DCMD0		__REG(0x4000020c)  /* DMA Command Address Register Channel 0 */
+#define DDADR1		__REG(0x40000210)  /* DMA Descriptor Address Register Channel 1 */
+#define DSADR1		__REG(0x40000214)  /* DMA Source Address Register Channel 1 */
+#define DTADR1		__REG(0x40000218)  /* DMA Target Address Register Channel 1 */
+#define DCMD1		__REG(0x4000021c)  /* DMA Command Address Register Channel 1 */
+#define DDADR2		__REG(0x40000220)  /* DMA Descriptor Address Register Channel 2 */
+#define DSADR2		__REG(0x40000224)  /* DMA Source Address Register Channel 2 */
+#define DTADR2		__REG(0x40000228)  /* DMA Target Address Register Channel 2 */
+#define DCMD2		__REG(0x4000022c)  /* DMA Command Address Register Channel 2 */
+#define DDADR3		__REG(0x40000230)  /* DMA Descriptor Address Register Channel 3 */
+#define DSADR3		__REG(0x40000234)  /* DMA Source Address Register Channel 3 */
+#define DTADR3		__REG(0x40000238)  /* DMA Target Address Register Channel 3 */
+#define DCMD3		__REG(0x4000023c)  /* DMA Command Address Register Channel 3 */
+#define DDADR4		__REG(0x40000240)  /* DMA Descriptor Address Register Channel 4 */
+#define DSADR4		__REG(0x40000244)  /* DMA Source Address Register Channel 4 */
+#define DTADR4		__REG(0x40000248)  /* DMA Target Address Register Channel 4 */
+#define DCMD4		__REG(0x4000024c)  /* DMA Command Address Register Channel 4 */
+#define DDADR5		__REG(0x40000250)  /* DMA Descriptor Address Register Channel 5 */
+#define DSADR5		__REG(0x40000254)  /* DMA Source Address Register Channel 5 */
+#define DTADR5		__REG(0x40000258)  /* DMA Target Address Register Channel 5 */
+#define DCMD5		__REG(0x4000025c)  /* DMA Command Address Register Channel 5 */
+#define DDADR6		__REG(0x40000260)  /* DMA Descriptor Address Register Channel 6 */
+#define DSADR6		__REG(0x40000264)  /* DMA Source Address Register Channel 6 */
+#define DTADR6		__REG(0x40000268)  /* DMA Target Address Register Channel 6 */
+#define DCMD6		__REG(0x4000026c)  /* DMA Command Address Register Channel 6 */
+#define DDADR7		__REG(0x40000270)  /* DMA Descriptor Address Register Channel 7 */
+#define DSADR7		__REG(0x40000274)  /* DMA Source Address Register Channel 7 */
+#define DTADR7		__REG(0x40000278)  /* DMA Target Address Register Channel 7 */
+#define DCMD7		__REG(0x4000027c)  /* DMA Command Address Register Channel 7 */
+#define DDADR8		__REG(0x40000280)  /* DMA Descriptor Address Register Channel 8 */
+#define DSADR8		__REG(0x40000284)  /* DMA Source Address Register Channel 8 */
+#define DTADR8		__REG(0x40000288)  /* DMA Target Address Register Channel 8 */
+#define DCMD8		__REG(0x4000028c)  /* DMA Command Address Register Channel 8 */
+#define DDADR9		__REG(0x40000290)  /* DMA Descriptor Address Register Channel 9 */
+#define DSADR9		__REG(0x40000294)  /* DMA Source Address Register Channel 9 */
+#define DTADR9		__REG(0x40000298)  /* DMA Target Address Register Channel 9 */
+#define DCMD9		__REG(0x4000029c)  /* DMA Command Address Register Channel 9 */
+#define DDADR10		__REG(0x400002a0)  /* DMA Descriptor Address Register Channel 10 */
+#define DSADR10		__REG(0x400002a4)  /* DMA Source Address Register Channel 10 */
+#define DTADR10		__REG(0x400002a8)  /* DMA Target Address Register Channel 10 */
+#define DCMD10		__REG(0x400002ac)  /* DMA Command Address Register Channel 10 */
+#define DDADR11		__REG(0x400002b0)  /* DMA Descriptor Address Register Channel 11 */
+#define DSADR11		__REG(0x400002b4)  /* DMA Source Address Register Channel 11 */
+#define DTADR11		__REG(0x400002b8)  /* DMA Target Address Register Channel 11 */
+#define DCMD11		__REG(0x400002bc)  /* DMA Command Address Register Channel 11 */
+#define DDADR12		__REG(0x400002c0)  /* DMA Descriptor Address Register Channel 12 */
+#define DSADR12		__REG(0x400002c4)  /* DMA Source Address Register Channel 12 */
+#define DTADR12		__REG(0x400002c8)  /* DMA Target Address Register Channel 12 */
+#define DCMD12		__REG(0x400002cc)  /* DMA Command Address Register Channel 12 */
+#define DDADR13		__REG(0x400002d0)  /* DMA Descriptor Address Register Channel 13 */
+#define DSADR13		__REG(0x400002d4)  /* DMA Source Address Register Channel 13 */
+#define DTADR13		__REG(0x400002d8)  /* DMA Target Address Register Channel 13 */
+#define DCMD13		__REG(0x400002dc)  /* DMA Command Address Register Channel 13 */
+#define DDADR14		__REG(0x400002e0)  /* DMA Descriptor Address Register Channel 14 */
+#define DSADR14		__REG(0x400002e4)  /* DMA Source Address Register Channel 14 */
+#define DTADR14		__REG(0x400002e8)  /* DMA Target Address Register Channel 14 */
+#define DCMD14		__REG(0x400002ec)  /* DMA Command Address Register Channel 14 */
+#define DDADR15		__REG(0x400002f0)  /* DMA Descriptor Address Register Channel 15 */
+#define DSADR15		__REG(0x400002f4)  /* DMA Source Address Register Channel 15 */
+#define DTADR15		__REG(0x400002f8)  /* DMA Target Address Register Channel 15 */
+#define DCMD15		__REG(0x400002fc)  /* DMA Command Address Register Channel 15 */
+
+#define DDADR(x)	__REG2(0x40000200, (x) << 4)
+#define DSADR(x)	__REG2(0x40000204, (x) << 4)
+#define DTADR(x)	__REG2(0x40000208, (x) << 4)
+#define DCMD(x)		__REG2(0x4000020c, (x) << 4)
+
+#define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
+#define DDADR_STOP	(1 << 0)	/* Stop (read / write) */
+
+#define DCMD_INCSRCADDR (1 << 31)	/* Source Address Increment Setting. */
+#define DCMD_INCTRGADDR (1 << 30)	/* Target Address Increment Setting. */
+#define DCMD_FLOWSRC	(1 << 29)	/* Flow Control by the source. */
+#define DCMD_FLOWTRG	(1 << 28)	/* Flow Control by the target. */
+#define DCMD_STARTIRQEN (1 << 22)	/* Start Interrupt Enable */
+#define DCMD_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */
+#define DCMD_ENDIAN	(1 << 18)	/* Device Endian-ness. */
+#define DCMD_BURST8	(1 << 16)	/* 8 byte burst */
+#define DCMD_BURST16	(2 << 16)	/* 16 byte burst */
+#define DCMD_BURST32	(3 << 16)	/* 32 byte burst */
+#define DCMD_WIDTH1	(1 << 14)	/* 1 byte width */
+#define DCMD_WIDTH2	(2 << 14)	/* 2 byte width (HalfWord) */
+#define DCMD_WIDTH4	(3 << 14)	/* 4 byte width (Word) */
+#define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */
+
+/* default combinations */
+#define DCMD_RXPCDR	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
+#define DCMD_RXMCDR	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
+#define DCMD_TXPCDR	(DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
+
+/*
+ * UARTs
+ */
+/* Full Function UART (FFUART) */
+#define FFUART		FFRBR
+#define FFRBR		__REG(0x40100000)  /* Receive Buffer Register (read only) */
+#define FFTHR		__REG(0x40100000)  /* Transmit Holding Register (write only) */
+#define FFIER		__REG(0x40100004)  /* Interrupt Enable Register (read/write) */
+#define FFIIR		__REG(0x40100008)  /* Interrupt ID Register (read only) */
+#define FFFCR		__REG(0x40100008)  /* FIFO Control Register (write only) */
+#define FFLCR		__REG(0x4010000C)  /* Line Control Register (read/write) */
+#define FFMCR		__REG(0x40100010)  /* Modem Control Register (read/write) */
+#define FFLSR		__REG(0x40100014)  /* Line Status Register (read only) */
+#define FFMSR		__REG(0x40100018)  /* Modem Status Register (read only) */
+#define FFSPR		__REG(0x4010001C)  /* Scratch Pad Register (read/write) */
+#define FFISR		__REG(0x40100020)  /* Infrared Selection Register (read/write) */
+#define FFDLL		__REG(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define FFDLH		__REG(0x40100004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
+/* Bluetooth UART (BTUART) */
+#define BTUART		BTRBR
+#define BTRBR		__REG(0x40200000)  /* Receive Buffer Register (read only) */
+#define BTTHR		__REG(0x40200000)  /* Transmit Holding Register (write only) */
+#define BTIER		__REG(0x40200004)  /* Interrupt Enable Register (read/write) */
+#define BTIIR		__REG(0x40200008)  /* Interrupt ID Register (read only) */
+#define BTFCR		__REG(0x40200008)  /* FIFO Control Register (write only) */
+#define BTLCR		__REG(0x4020000C)  /* Line Control Register (read/write) */
+#define BTMCR		__REG(0x40200010)  /* Modem Control Register (read/write) */
+#define BTLSR		__REG(0x40200014)  /* Line Status Register (read only) */
+#define BTMSR		__REG(0x40200018)  /* Modem Status Register (read only) */
+#define BTSPR		__REG(0x4020001C)  /* Scratch Pad Register (read/write) */
+#define BTISR		__REG(0x40200020)  /* Infrared Selection Register (read/write) */
+#define BTDLL		__REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define BTDLH		__REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
+/* Standard UART (STUART) */
+#define STUART		STRBR
+#define STRBR		__REG(0x40700000)  /* Receive Buffer Register (read only) */
+#define STTHR		__REG(0x40700000)  /* Transmit Holding Register (write only) */
+#define STIER		__REG(0x40700004)  /* Interrupt Enable Register (read/write) */
+#define STIIR		__REG(0x40700008)  /* Interrupt ID Register (read only) */
+#define STFCR		__REG(0x40700008)  /* FIFO Control Register (write only) */
+#define STLCR		__REG(0x4070000C)  /* Line Control Register (read/write) */
+#define STMCR		__REG(0x40700010)  /* Modem Control Register (read/write) */
+#define STLSR		__REG(0x40700014)  /* Line Status Register (read only) */
+#define STMSR		__REG(0x40700018)  /* Reserved */
+#define STSPR		__REG(0x4070001C)  /* Scratch Pad Register (read/write) */
+#define STISR		__REG(0x40700020)  /* Infrared Selection Register (read/write) */
+#define STDLL		__REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define STDLH		__REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
+#define IER_DMAE	(1 << 7)	/* DMA Requests Enable */
+#define IER_UUE		(1 << 6)	/* UART Unit Enable */
+#define IER_NRZE	(1 << 5)	/* NRZ coding Enable */
+#define IER_RTIOE	(1 << 4)	/* Receiver Time Out Interrupt Enable */
+#define IER_MIE		(1 << 3)	/* Modem Interrupt Enable */
+#define IER_RLSE	(1 << 2)	/* Receiver Line Status Interrupt Enable */
+#define IER_TIE		(1 << 1)	/* Transmit Data request Interrupt Enable */
+#define IER_RAVIE	(1 << 0)	/* Receiver Data Available Interrupt Enable */
+
+#define IIR_FIFOES1	(1 << 7)	/* FIFO Mode Enable Status */
+#define IIR_FIFOES0	(1 << 6)	/* FIFO Mode Enable Status */
+#define IIR_TOD		(1 << 3)	/* Time Out Detected */
+#define IIR_IID2	(1 << 2)	/* Interrupt Source Encoded */
+#define IIR_IID1	(1 << 1)	/* Interrupt Source Encoded */
+#define IIR_IP		(1 << 0)	/* Interrupt Pending (active low) */
+
+#define FCR_ITL2	(1 << 7)	/* Interrupt Trigger Level */
+#define FCR_ITL1	(1 << 6)	/* Interrupt Trigger Level */
+#define FCR_RESETTF	(1 << 2)	/* Reset Transmitter FIFO */
+#define FCR_RESETRF	(1 << 1)	/* Reset Receiver FIFO */
+#define FCR_TRFIFOE	(1 << 0)	/* Transmit and Receive FIFO Enable */
+#define FCR_ITL_1	(0)
+#define FCR_ITL_8	(FCR_ITL1)
+#define FCR_ITL_16	(FCR_ITL2)
+#define FCR_ITL_32	(FCR_ITL2|FCR_ITL1)
+
+#define LCR_DLAB	(1 << 7)	/* Divisor Latch Access Bit */
+#define LCR_SB		(1 << 6)	/* Set Break */
+#define LCR_STKYP	(1 << 5)	/* Sticky Parity */
+#define LCR_EPS		(1 << 4)	/* Even Parity Select */
+#define LCR_PEN		(1 << 3)	/* Parity Enable */
+#define LCR_STB		(1 << 2)	/* Stop Bit */
+#define LCR_WLS1	(1 << 1)	/* Word Length Select */
+#define LCR_WLS0	(1 << 0)	/* Word Length Select */
+
+#define LSR_FIFOE	(1 << 7)	/* FIFO Error Status */
+#define LSR_TEMT	(1 << 6)	/* Transmitter Empty */
+#define LSR_TDRQ	(1 << 5)	/* Transmit Data Request */
+#define LSR_BI		(1 << 4)	/* Break Interrupt */
+#define LSR_FE		(1 << 3)	/* Framing Error */
+#define LSR_PE		(1 << 2)	/* Parity Error */
+#define LSR_OE		(1 << 1)	/* Overrun Error */
+#define LSR_DR		(1 << 0)	/* Data Ready */
+
+#define MCR_LOOP	(1 << 4)	*/
+#define MCR_OUT2	(1 << 3)	/* force MSR_DCD in loopback mode */
+#define MCR_OUT1	(1 << 2)	/* force MSR_RI in loopback mode */
+#define MCR_RTS		(1 << 1)	/* Request to Send */
+#define MCR_DTR		(1 << 0)	/* Data Terminal Ready */
+
+#define MSR_DCD		(1 << 7)	/* Data Carrier Detect */
+#define MSR_RI		(1 << 6)	/* Ring Indicator */
+#define MSR_DSR		(1 << 5)	/* Data Set Ready */
+#define MSR_CTS		(1 << 4)	/* Clear To Send */
+#define MSR_DDCD	(1 << 3)	/* Delta Data Carrier Detect */
+#define MSR_TERI	(1 << 2)	/* Trailing Edge Ring Indicator */
+#define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */
+#define MSR_DCTS	(1 << 0)	/* Delta Clear To Send */
+
+/*
+ * IrSR (Infrared Selection Register)
+ */
+#define IrSR_OFFSET 0x20
+
+#define IrSR_RXPL_NEG_IS_ZERO (1<<4)
+#define IrSR_RXPL_POS_IS_ZERO 0x0
+#define IrSR_TXPL_NEG_IS_ZERO (1<<3)
+#define IrSR_TXPL_POS_IS_ZERO 0x0
+#define IrSR_XMODE_PULSE_1_6  (1<<2)
+#define IrSR_XMODE_PULSE_3_16 0x0
+#define IrSR_RCVEIR_IR_MODE   (1<<1)
+#define IrSR_RCVEIR_UART_MODE 0x0
+#define IrSR_XMITIR_IR_MODE   (1<<0)
+#define IrSR_XMITIR_UART_MODE 0x0
+
+#define IrSR_IR_RECEIVE_ON (\
+		IrSR_RXPL_NEG_IS_ZERO | \
+		IrSR_TXPL_POS_IS_ZERO | \
+		IrSR_XMODE_PULSE_3_16 | \
+		IrSR_RCVEIR_IR_MODE   | \
+		IrSR_XMITIR_UART_MODE)
+
+#define IrSR_IR_TRANSMIT_ON (\
+		IrSR_RXPL_NEG_IS_ZERO | \
+		IrSR_TXPL_POS_IS_ZERO | \
+		IrSR_XMODE_PULSE_3_16 | \
+		IrSR_RCVEIR_UART_MODE | \
+		IrSR_XMITIR_IR_MODE)
+
+/*
+ * I2C registers
+ */
+#define IBMR		__REG(0x40301680)  /* I2C Bus Monitor Register - IBMR */
+#define IDBR		__REG(0x40301688)  /* I2C Data Buffer Register - IDBR */
+#define ICR		__REG(0x40301690)  /* I2C Control Register - ICR */
+#define ISR		__REG(0x40301698)  /* I2C Status Register - ISR */
+#define ISAR		__REG(0x403016A0)  /* I2C Slave Address Register - ISAR */
+
+#define PWRIBMR		__REG(0x40f00180)  /* Power I2C Bus Monitor Register-IBMR */
+#define PWRIDBR		__REG(0x40f00188)  /* Power I2C Data Buffer Register-IDBR */
+#define PWRICR		__REG(0x40f00190)  /* Power I2C Control Register - ICR */
+#define PWRISR		__REG(0x40f00198)  /* Power I2C Status Register - ISR */
+#define PWRISAR		__REG(0x40f001A0)  /* Power I2C Slave Address Register-ISAR */
+
+/* ----- Control register bits ---------------------------------------- */
+
+#define ICR_START	0x1		/* start bit */
+#define ICR_STOP	0x2		/* stop bit */
+#define ICR_ACKNAK	0x4		/* send ACK(0) or NAK(1) */
+#define ICR_TB		0x8		/* transfer byte bit */
+#define ICR_MA		0x10		/* master abort */
+#define ICR_SCLE	0x20		/* master clock enable */
+#define ICR_IUE		0x40		/* unit enable */
+#define ICR_GCD		0x80		/* general call disable */
+#define ICR_ITEIE	0x100		/* enable tx interrupts */
+#define ICR_IRFIE	0x200		/* enable rx interrupts */
+#define ICR_BEIE	0x400		/* enable bus error ints */
+#define ICR_SSDIE	0x800		/* slave STOP detected int enable */
+#define ICR_ALDIE	0x1000		/* enable arbitration interrupt */
+#define ICR_SADIE	0x2000		/* slave address detected int enable */
+#define ICR_UR		0x4000		/* unit reset */
+#define ICR_FM		0x8000		/* Fast Mode */
+
+/* ----- Status register bits ----------------------------------------- */
+
+#define ISR_RWM		0x1		/* read/write mode */
+#define ISR_ACKNAK	0x2		/* ack/nak status */
+#define ISR_UB		0x4		/* unit busy */
+#define ISR_IBB		0x8		/* bus busy */
+#define ISR_SSD		0x10		/* slave stop detected */
+#define ISR_ALD		0x20		/* arbitration loss detected */
+#define ISR_ITE		0x40		/* tx buffer empty */
+#define ISR_IRF		0x80		/* rx buffer full */
+#define ISR_GCAD	0x100		/* general call address detected */
+#define ISR_SAD		0x200		/* slave address detected */
+#define ISR_BED		0x400		/* bus error no ACK/NAK */
+
+/*
+ * Serial Audio Controller
+ */
+/* FIXME the audio defines collide w/ the SA1111 defines.  I don't like these
+ * short defines because there is too much chance of namespace collision
+ */
+/*#define SACR0		__REG(0x40400000)  /  Global Control Register */
+/*#define SACR1		__REG(0x40400004)  /  Serial Audio I 2 S/MSB-Justified Control Register */
+/*#define SASR0		__REG(0x4040000C)  /  Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
+/*#define SAIMR		__REG(0x40400014)  /  Serial Audio Interrupt Mask Register */
+/*#define SAICR		__REG(0x40400018)  /  Serial Audio Interrupt Clear Register */
+/*#define SADIV		__REG(0x40400060)  /  Audio Clock Divider Register. */
+/*#define SADR		__REG(0x40400080)  /  Serial Audio Data Register (TX and RX FIFO access Register). */
+
+
+/*
+ * AC97 Controller registers
+ */
+#define POCR		__REG(0x40500000)  /* PCM Out Control Register */
+#define POCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
+
+#define PICR		__REG(0x40500004)  /* PCM In Control Register */
+#define PICR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
+
+#define MCCR		__REG(0x40500008)  /* Mic In Control Register */
+#define MCCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
+
+#define GCR		__REG(0x4050000C)  /* Global Control Register */
+#define GCR_CDONE_IE	(1 << 19)	/* Command Done Interrupt Enable */
+#define GCR_SDONE_IE	(1 << 18)	/* Status Done Interrupt Enable */
+#define GCR_SECRDY_IEN	(1 << 9)	/* Secondary Ready Interrupt Enable */
+#define GCR_PRIRDY_IEN	(1 << 8)	/* Primary Ready Interrupt Enable */
+#define GCR_SECRES_IEN	(1 << 5)	/* Secondary Resume Interrupt Enable */
+#define GCR_PRIRES_IEN	(1 << 4)	/* Primary Resume Interrupt Enable */
+#define GCR_ACLINK_OFF	(1 << 3)	/* AC-link Shut Off */
+#define GCR_WARM_RST	(1 << 2)	/* AC97 Warm Reset */
+#define GCR_COLD_RST	(1 << 1)	/* AC'97 Cold Reset (0 = active) */
+#define GCR_GIE		(1 << 0)	/* Codec GPI Interrupt Enable */
+
+#define POSR		__REG(0x40500010)  /* PCM Out Status Register */
+#define POSR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define PISR		__REG(0x40500014)  /* PCM In Status Register */
+#define PISR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define MCSR		__REG(0x40500018)  /* Mic In Status Register */
+#define MCSR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define GSR		__REG(0x4050001C)  /* Global Status Register */
+#define GSR_CDONE	(1 << 19)	/* Command Done */
+#define GSR_SDONE	(1 << 18)	/* Status Done */
+#define GSR_RDCS	(1 << 15)	/* Read Completion Status */
+#define GSR_BIT3SLT12	(1 << 14)	/* Bit 3 of slot 12 */
+#define GSR_BIT2SLT12	(1 << 13)	/* Bit 2 of slot 12 */
+#define GSR_BIT1SLT12	(1 << 12)	/* Bit 1 of slot 12 */
+#define GSR_SECRES	(1 << 11)	/* Secondary Resume Interrupt */
+#define GSR_PRIRES	(1 << 10)	/* Primary Resume Interrupt */
+#define GSR_SCR		(1 << 9)	/* Secondary Codec Ready */
+#define GSR_PCR		(1 << 8)	/*  Primary Codec Ready */
+#define GSR_MINT	(1 << 7)	/* Mic In Interrupt */
+#define GSR_POINT	(1 << 6)	/* PCM Out Interrupt */
+#define GSR_PIINT	(1 << 5)	/* PCM In Interrupt */
+#define GSR_MOINT	(1 << 2)	/* Modem Out Interrupt */
+#define GSR_MIINT	(1 << 1)	/* Modem In Interrupt */
+#define GSR_GSCI	(1 << 0)	/* Codec GPI Status Change Interrupt */
+
+#define CAR		__REG(0x40500020)  /* CODEC Access Register */
+#define CAR_CAIP	(1 << 0)	/* Codec Access In Progress */
+
+#define PCDR		__REG(0x40500040)  /* PCM FIFO Data Register */
+#define MCDR		__REG(0x40500060)  /* Mic-in FIFO Data Register */
+
+#define MOCR		__REG(0x40500100)  /* Modem Out Control Register */
+#define MOCR_FEIE	(1 << 3)	/* FIFO Error */
+
+#define MICR		__REG(0x40500108)  /* Modem In Control Register */
+#define MICR_FEIE	(1 << 3)	/* FIFO Error */
+
+#define MOSR		__REG(0x40500110)  /* Modem Out Status Register */
+#define MOSR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define MISR		__REG(0x40500118)  /* Modem In Status Register */
+#define MISR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define MODR		__REG(0x40500140)  /* Modem FIFO Data Register */
+
+#define PAC_REG_BASE	__REG(0x40500200)  /* Primary Audio Codec */
+#define SAC_REG_BASE	__REG(0x40500300)  /* Secondary Audio Codec */
+#define PMC_REG_BASE	__REG(0x40500400)  /* Primary Modem Codec */
+#define SMC_REG_BASE	__REG(0x40500500)  /* Secondary Modem Codec */
+
+/*
+ * USB Device Controller
+ */
+#define UDC_RES1	__REG(0x40600004)  /* UDC Undocumented - Reserved1 */
+#define UDC_RES2	__REG(0x40600008)  /* UDC Undocumented - Reserved2 */
+#define UDC_RES3	__REG(0x4060000C)  /* UDC Undocumented - Reserved3 */
+
+#define UDCCR		__REG(0x40600000)  /* UDC Control Register */
+#define UDCCR_UDE	(1 << 0)	/* UDC enable */
+#define UDCCR_UDA	(1 << 1)	/* UDC active */
+#define UDCCR_RSM	(1 << 2)	/* Device resume */
+#define UDCCR_RESIR	(1 << 3)	/* Resume interrupt request */
+#define UDCCR_SUSIR	(1 << 4)	/* Suspend interrupt request */
+#define UDCCR_SRM	(1 << 5)	/* Suspend/resume interrupt mask */
+#define UDCCR_RSTIR	(1 << 6)	/* Reset interrupt request */
+#define UDCCR_REM	(1 << 7)	/* Reset interrupt mask */
+
+#define UDCCS0		__REG(0x40600010)  /* UDC Endpoint 0 Control/Status Register */
+#define UDCCS0_OPR	(1 << 0)	/* OUT packet ready */
+#define UDCCS0_IPR	(1 << 1)	/* IN packet ready */
+#define UDCCS0_FTF	(1 << 2)	/* Flush Tx FIFO */
+#define UDCCS0_DRWF	(1 << 3)	/* Device remote wakeup feature */
+#define UDCCS0_SST	(1 << 4)	/* Sent stall */
+#define UDCCS0_FST	(1 << 5)	/* Force stall */
+#define UDCCS0_RNE	(1 << 6)	/* Receive FIFO no empty */
+#define UDCCS0_SA	(1 << 7)	/* Setup active */
+
+/* Bulk IN - Endpoint 1,6,11 */
+#define UDCCS1		__REG(0x40600014)  /* UDC Endpoint 1 (IN) Control/Status Register */
+#define UDCCS6		__REG(0x40600028)  /* UDC Endpoint 6 (IN) Control/Status Register */
+#define UDCCS11		__REG(0x4060003C)  /* UDC Endpoint 11 (IN) Control/Status Register */
+
+#define UDCCS_BI_TFS	(1 << 0)	/* Transmit FIFO service */
+#define UDCCS_BI_TPC	(1 << 1)	/* Transmit packet complete */
+#define UDCCS_BI_FTF	(1 << 2)	/* Flush Tx FIFO */
+#define UDCCS_BI_TUR	(1 << 3)	/* Transmit FIFO underrun */
+#define UDCCS_BI_SST	(1 << 4)	/* Sent stall */
+#define UDCCS_BI_FST	(1 << 5)	/* Force stall */
+#define UDCCS_BI_TSP	(1 << 7)	/* Transmit short packet */
+
+/* Bulk OUT - Endpoint 2,7,12 */
+#define UDCCS2		__REG(0x40600018)  /* UDC Endpoint 2 (OUT) Control/Status Register */
+#define UDCCS7		__REG(0x4060002C)  /* UDC Endpoint 7 (OUT) Control/Status Register */
+#define UDCCS12		__REG(0x40600040)  /* UDC Endpoint 12 (OUT) Control/Status Register */
+
+#define UDCCS_BO_RFS	(1 << 0)	/* Receive FIFO service */
+#define UDCCS_BO_RPC	(1 << 1)	/* Receive packet complete */
+#define UDCCS_BO_DME	(1 << 3)	/* DMA enable */
+#define UDCCS_BO_SST	(1 << 4)	/* Sent stall */
+#define UDCCS_BO_FST	(1 << 5)	/* Force stall */
+#define UDCCS_BO_RNE	(1 << 6)	/* Receive FIFO not empty */
+#define UDCCS_BO_RSP	(1 << 7)	/* Receive short packet */
+
+/* Isochronous IN - Endpoint 3,8,13 */
+#define UDCCS3		__REG(0x4060001C)  /* UDC Endpoint 3 (IN) Control/Status Register */
+#define UDCCS8		__REG(0x40600030)  /* UDC Endpoint 8 (IN) Control/Status Register */
+#define UDCCS13		__REG(0x40600044)  /* UDC Endpoint 13 (IN) Control/Status Register */
+
+#define UDCCS_II_TFS	(1 << 0)	/* Transmit FIFO service */
+#define UDCCS_II_TPC	(1 << 1)	/* Transmit packet complete */
+#define UDCCS_II_FTF	(1 << 2)	/* Flush Tx FIFO */
+#define UDCCS_II_TUR	(1 << 3)	/* Transmit FIFO underrun */
+#define UDCCS_II_TSP	(1 << 7)	/* Transmit short packet */
+
+/* Isochronous OUT - Endpoint 4,9,14 */
+#define UDCCS4		__REG(0x40600020)  /* UDC Endpoint 4 (OUT) Control/Status Register */
+#define UDCCS9		__REG(0x40600034)  /* UDC Endpoint 9 (OUT) Control/Status Register */
+#define UDCCS14		__REG(0x40600048)  /* UDC Endpoint 14 (OUT) Control/Status Register */
+
+#define UDCCS_IO_RFS	(1 << 0)	/* Receive FIFO service */
+#define UDCCS_IO_RPC	(1 << 1)	/* Receive packet complete */
+#define UDCCS_IO_ROF	(1 << 3)	/* Receive overflow */
+#define UDCCS_IO_DME	(1 << 3)	/* DMA enable */
+#define UDCCS_IO_RNE	(1 << 6)	/* Receive FIFO not empty */
+#define UDCCS_IO_RSP	(1 << 7)	/* Receive short packet */
+
+/* Interrupt IN - Endpoint 5,10,15 */
+#define UDCCS5		__REG(0x40600024)  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
+#define UDCCS10		__REG(0x40600038)  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
+#define UDCCS15		__REG(0x4060004C)  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
+
+#define UDCCS_INT_TFS	(1 << 0)	/* Transmit FIFO service */
+#define UDCCS_INT_TPC	(1 << 1)	/* Transmit packet complete */
+#define UDCCS_INT_FTF	(1 << 2)	/* Flush Tx FIFO */
+#define UDCCS_INT_TUR	(1 << 3)	/* Transmit FIFO underrun */
+#define UDCCS_INT_SST	(1 << 4)	/* Sent stall */
+#define UDCCS_INT_FST	(1 << 5)	/* Force stall */
+#define UDCCS_INT_TSP	(1 << 7)	/* Transmit short packet */
+
+#define UFNRH		__REG(0x40600060)  /* UDC Frame Number Register High */
+#define UFNRL		__REG(0x40600064)  /* UDC Frame Number Register Low */
+#define UBCR2		__REG(0x40600068)  /* UDC Byte Count Reg 2 */
+#define UBCR4		__REG(0x4060006c)  /* UDC Byte Count Reg 4 */
+#define UBCR7		__REG(0x40600070)  /* UDC Byte Count Reg 7 */
+#define UBCR9		__REG(0x40600074)  /* UDC Byte Count Reg 9 */
+#define UBCR12		__REG(0x40600078)  /* UDC Byte Count Reg 12 */
+#define UBCR14		__REG(0x4060007c)  /* UDC Byte Count Reg 14 */
+#define UDDR0		__REG(0x40600080)  /* UDC Endpoint 0 Data Register */
+#define UDDR1		__REG(0x40600100)  /* UDC Endpoint 1 Data Register */
+#define UDDR2		__REG(0x40600180)  /* UDC Endpoint 2 Data Register */
+#define UDDR3		__REG(0x40600200)  /* UDC Endpoint 3 Data Register */
+#define UDDR4		__REG(0x40600400)  /* UDC Endpoint 4 Data Register */
+#define UDDR5		__REG(0x406000A0)  /* UDC Endpoint 5 Data Register */
+#define UDDR6		__REG(0x40600600)  /* UDC Endpoint 6 Data Register */
+#define UDDR7		__REG(0x40600680)  /* UDC Endpoint 7 Data Register */
+#define UDDR8		__REG(0x40600700)  /* UDC Endpoint 8 Data Register */
+#define UDDR9		__REG(0x40600900)  /* UDC Endpoint 9 Data Register */
+#define UDDR10		__REG(0x406000C0)  /* UDC Endpoint 10 Data Register */
+#define UDDR11		__REG(0x40600B00)  /* UDC Endpoint 11 Data Register */
+#define UDDR12		__REG(0x40600B80)  /* UDC Endpoint 12 Data Register */
+#define UDDR13		__REG(0x40600C00)  /* UDC Endpoint 13 Data Register */
+#define UDDR14		__REG(0x40600E00)  /* UDC Endpoint 14 Data Register */
+#define UDDR15		__REG(0x406000E0)  /* UDC Endpoint 15 Data Register */
+
+#define UICR0		__REG(0x40600050)  /* UDC Interrupt Control Register 0 */
+
+#define UICR0_IM0	(1 << 0)	/* Interrupt mask ep 0 */
+#define UICR0_IM1	(1 << 1)	/* Interrupt mask ep 1 */
+#define UICR0_IM2	(1 << 2)	/* Interrupt mask ep 2 */
+#define UICR0_IM3	(1 << 3)	/* Interrupt mask ep 3 */
+#define UICR0_IM4	(1 << 4)	/* Interrupt mask ep 4 */
+#define UICR0_IM5	(1 << 5)	/* Interrupt mask ep 5 */
+#define UICR0_IM6	(1 << 6)	/* Interrupt mask ep 6 */
+#define UICR0_IM7	(1 << 7)	/* Interrupt mask ep 7 */
+
+#define UICR1		__REG(0x40600054)  /* UDC Interrupt Control Register 1 */
+
+#define UICR1_IM8	(1 << 0)	/* Interrupt mask ep 8 */
+#define UICR1_IM9	(1 << 1)	/* Interrupt mask ep 9 */
+#define UICR1_IM10	(1 << 2)	/* Interrupt mask ep 10 */
+#define UICR1_IM11	(1 << 3)	/* Interrupt mask ep 11 */
+#define UICR1_IM12	(1 << 4)	/* Interrupt mask ep 12 */
+#define UICR1_IM13	(1 << 5)	/* Interrupt mask ep 13 */
+#define UICR1_IM14	(1 << 6)	/* Interrupt mask ep 14 */
+#define UICR1_IM15	(1 << 7)	/* Interrupt mask ep 15 */
+
+#define USIR0		__REG(0x40600058)  /* UDC Status Interrupt Register 0 */
+
+#define USIR0_IR0	(1 << 0)	/* Interrup request ep 0 */
+#define USIR0_IR1	(1 << 1)	/* Interrup request ep 1 */
+#define USIR0_IR2	(1 << 2)	/* Interrup request ep 2 */
+#define USIR0_IR3	(1 << 3)	/* Interrup request ep 3 */
+#define USIR0_IR4	(1 << 4)	/* Interrup request ep 4 */
+#define USIR0_IR5	(1 << 5)	/* Interrup request ep 5 */
+#define USIR0_IR6	(1 << 6)	/* Interrup request ep 6 */
+#define USIR0_IR7	(1 << 7)	/* Interrup request ep 7 */
+
+#define USIR1		__REG(0x4060005C)  /* UDC Status Interrupt Register 1 */
+
+#define USIR1_IR8	(1 << 0)	/* Interrup request ep 8 */
+#define USIR1_IR9	(1 << 1)	/* Interrup request ep 9 */
+#define USIR1_IR10	(1 << 2)	/* Interrup request ep 10 */
+#define USIR1_IR11	(1 << 3)	/* Interrup request ep 11 */
+#define USIR1_IR12	(1 << 4)	/* Interrup request ep 12 */
+#define USIR1_IR13	(1 << 5)	/* Interrup request ep 13 */
+#define USIR1_IR14	(1 << 6)	/* Interrup request ep 14 */
+#define USIR1_IR15	(1 << 7)	/* Interrup request ep 15 */
+
+#if defined(CONFIG_PXA27X)
+/*
+ * USB Host Controller
+ */
+#define UHCREV		__REG(0x4C000000)
+#define UHCHCON		__REG(0x4C000004)
+#define UHCCOMS		__REG(0x4C000008)
+#define UHCINTS		__REG(0x4C00000C)
+#define UHCINTE		__REG(0x4C000010)
+#define UHCINTD		__REG(0x4C000014)
+#define UHCHCCA		__REG(0x4C000018)
+#define UHCPCED		__REG(0x4C00001C)
+#define UHCCHED		__REG(0x4C000020)
+#define UHCCCED		__REG(0x4C000024)
+#define UHCBHED		__REG(0x4C000028)
+#define UHCBCED		__REG(0x4C00002C)
+#define UHCDHEAD	__REG(0x4C000030)
+#define UHCFMI		__REG(0x4C000034)
+#define UHCFMR		__REG(0x4C000038)
+#define UHCFMN		__REG(0x4C00003C)
+#define UHCPERS		__REG(0x4C000040)
+#define UHCLST		__REG(0x4C000044)
+#define UHCRHDA		__REG(0x4C000048)
+#define UHCRHDB		__REG(0x4C00004C)
+#define UHCRHS		__REG(0x4C000050)
+#define UHCRHPS1	__REG(0x4C000054)
+#define UHCRHPS2	__REG(0x4C000058)
+#define UHCRHPS3	__REG(0x4C00005C)
+#define UHCSTAT		__REG(0x4C000060)
+#define UHCHR		__REG(0x4C000064)
+#define UHCHIE		__REG(0x4C000068)
+#define UHCHIT		__REG(0x4C00006C)
+
+#define UHCHR_FSBIR	(1<<0)
+#define UHCHR_FHR	(1<<1)
+#define UHCHR_CGR	(1<<2)
+#define UHCHR_SSDC	(1<<3)
+#define UHCHR_UIT	(1<<4)
+#define UHCHR_SSE	(1<<5)
+#define UHCHR_PSPL	(1<<6)
+#define UHCHR_PCPL	(1<<7)
+#define UHCHR_SSEP0	(1<<9)
+#define UHCHR_SSEP1	(1<<10)
+#define UHCHR_SSEP2	(1<<11)
+
+#define UHCHIE_UPRIE	(1<<13)
+#define UHCHIE_UPS2IE	(1<<12)
+#define UHCHIE_UPS1IE	(1<<11)
+#define UHCHIE_TAIE	(1<<10)
+#define UHCHIE_HBAIE	(1<<8)
+#define UHCHIE_RWIE	(1<<7)
+
+#endif
+
+/*
+ * Fast Infrared Communication Port
+ */
+#define ICCR0		__REG(0x40800000)  /* ICP Control Register 0 */
+#define ICCR1		__REG(0x40800004)  /* ICP Control Register 1 */
+#define ICCR2		__REG(0x40800008)  /* ICP Control Register 2 */
+#define ICDR		__REG(0x4080000c)  /* ICP Data Register */
+#define ICSR0		__REG(0x40800014)  /* ICP Status Register 0 */
+#define ICSR1		__REG(0x40800018)  /* ICP Status Register 1 */
+
+/*
+ * Real Time Clock
+ */
+#define RCNR		__REG(0x40900000)  /* RTC Count Register */
+#define RTAR		__REG(0x40900004)  /* RTC Alarm Register */
+#define RTSR		__REG(0x40900008)  /* RTC Status Register */
+#define RTTR		__REG(0x4090000C)  /* RTC Timer Trim Register */
+#define RDAR1	   __REG(0x40900018)  /* Wristwatch Day Alarm Reg 1 */
+#define RDAR2	   __REG(0x40900020)  /* Wristwatch Day Alarm Reg 2 */
+#define RYAR1	   __REG(0x4090001C)  /* Wristwatch Year Alarm Reg 1 */
+#define RYAR2	   __REG(0x40900024)  /* Wristwatch Year Alarm Reg 2 */
+#define SWAR1	   __REG(0x4090002C)  /* Stopwatch Alarm Register 1 */
+#define SWAR2	   __REG(0x40900030)  /* Stopwatch Alarm Register 2 */
+#define PIAR	   __REG(0x40900038)  /* Periodic Interrupt Alarm Register */
+#define RDCR	   __REG(0x40900010)  /* RTC Day Count Register. */
+#define RYCR	   __REG(0x40900014)  /* RTC Year Count Register. */
+#define SWCR	   __REG(0x40900028)  /* Stopwatch Count Register */
+#define RTCPICR	   __REG(0x40900034)  /* Periodic Interrupt Counter Register */
+
+#define RTSR_PICE  (1 << 15)   /* Peridoc interrupt count enable */
+#define RTSR_PIALE (1 << 14)   /* Peridoc interrupt Alarm enable */
+#define RTSR_PIAL  (1 << 13)   /* Peridoc  interrupt Alarm status */
+#define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
+#define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
+#define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
+#define RTSR_AL		(1 << 0)	/* RTC alarm detected */
+
+/*
+ * OS Timer & Match Registers
+ */
+#define OSMR0		__REG(0x40A00000)  /* */
+#define OSMR1		__REG(0x40A00004)  /* */
+#define OSMR2		__REG(0x40A00008)  /* */
+#define OSMR3		__REG(0x40A0000C)  /* */
+#define OSCR		__REG(0x40A00010)  /* OS Timer Counter Register */
+#define OSSR		__REG(0x40A00014)  /* OS Timer Status Register */
+#define OWER		__REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
+#define OIER		__REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
+
+#define OSSR_M3		(1 << 3)	/* Match status channel 3 */
+#define OSSR_M2		(1 << 2)	/* Match status channel 2 */
+#define OSSR_M1		(1 << 1)	/* Match status channel 1 */
+#define OSSR_M0		(1 << 0)	/* Match status channel 0 */
+
+#define OWER_WME	(1 << 0)	/* Watchdog Match Enable */
+
+#define OIER_E3		(1 << 3)	/* Interrupt enable channel 3 */
+#define OIER_E2		(1 << 2)	/* Interrupt enable channel 2 */
+#define OIER_E1		(1 << 1)	/* Interrupt enable channel 1 */
+#define OIER_E0		(1 << 0)	/* Interrupt enable channel 0 */
+
+/*
+ * Pulse Width Modulator
+ */
+#define PWM_CTRL0	__REG(0x40B00000)  /* PWM 0 Control Register */
+#define PWM_PWDUTY0	__REG(0x40B00004)  /* PWM 0 Duty Cycle Register */
+#define PWM_PERVAL0	__REG(0x40B00008)  /* PWM 0 Period Control Register */
+
+#define PWM_CTRL1	__REG(0x40C00000)  /* PWM 1Control Register */
+#define PWM_PWDUTY1	__REG(0x40C00004)  /* PWM 1 Duty Cycle Register */
+#define PWM_PERVAL1	__REG(0x40C00008)  /* PWM 1 Period Control Register */
+
+/*
+ * Interrupt Controller
+ */
+#define ICIP		__REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
+#define ICMR		__REG(0x40D00004)  /* Interrupt Controller Mask Register */
+#define ICLR		__REG(0x40D00008)  /* Interrupt Controller Level Register */
+#define ICFP		__REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
+#define ICPR		__REG(0x40D00010)  /* Interrupt Controller Pending Register */
+#define ICCR		__REG(0x40D00014)  /* Interrupt Controller Control Register */
+
+/*
+ * General Purpose I/O
+ */
+#define GPLR0		__REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
+#define GPLR1		__REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
+#define GPLR2		__REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */
+
+#define GPDR0		__REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
+#define GPDR1		__REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
+#define GPDR2		__REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */
+
+#define GPSR0		__REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
+#define GPSR1		__REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
+#define GPSR2		__REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<80:64> */
+
+#define GPCR0		__REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
+#define GPCR1		__REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
+#define GPCR2		__REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <80:64> */
+
+#define GRER0		__REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
+#define GRER1		__REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
+#define GRER2		__REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<80:64> */
+
+#define GFER0		__REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
+#define GFER1		__REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
+#define GFER2		__REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<80:64> */
+
+#define GEDR0		__REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
+#define GEDR1		__REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
+#define GEDR2		__REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */
+
+#define GAFR0_L		__REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
+#define GAFR0_U		__REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
+#define GAFR1_L		__REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
+#define GAFR1_U		__REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
+#define GAFR2_L		__REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
+#define GAFR2_U		__REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO 80 */
+
+/* More handy macros.  The argument is a literal GPIO number. */
+
+#define GPIO_bit(x)	(1 << ((x) & 0x1f))
+
+#ifdef CONFIG_PXA27X
+
+/* Interrupt Controller */
+
+#define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
+#define ICLR2		__REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
+#define ICFP2		__REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2		__REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
+
+#define _GPLR(x)	__REG2(0x40E00000, ((x) & 0x60) >> 3)
+#define _GPDR(x)	__REG2(0x40E0000C, ((x) & 0x60) >> 3)
+#define _GPSR(x)	__REG2(0x40E00018, ((x) & 0x60) >> 3)
+#define _GPCR(x)	__REG2(0x40E00024, ((x) & 0x60) >> 3)
+#define _GRER(x)	__REG2(0x40E00030, ((x) & 0x60) >> 3)
+#define _GFER(x)	__REG2(0x40E0003C, ((x) & 0x60) >> 3)
+#define _GEDR(x)	__REG2(0x40E00048, ((x) & 0x60) >> 3)
+#define _GAFR(x)	__REG2(0x40E00054, ((x) & 0x70) >> 2)
+
+#define GPLR(x)		((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)
+#define GPDR(x)		((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)
+#define GPSR(x)		((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)
+#define GPCR(x)		((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)
+#define GRER(x)		((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)
+#define GFER(x)		((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)
+#define GEDR(x)		((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)
+#define GAFR(x)		((((x) & 0x7f) < 96) ? _GAFR(x) : \
+			 ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))
+#else
+
+#define GPLR(x)		__REG2(0x40E00000, ((x) & 0x60) >> 3)
+#define GPDR(x)		__REG2(0x40E0000C, ((x) & 0x60) >> 3)
+#define GPSR(x)		__REG2(0x40E00018, ((x) & 0x60) >> 3)
+#define GPCR(x)		__REG2(0x40E00024, ((x) & 0x60) >> 3)
+#define GRER(x)		__REG2(0x40E00030, ((x) & 0x60) >> 3)
+#define GFER(x)		__REG2(0x40E0003C, ((x) & 0x60) >> 3)
+#define GEDR(x)		__REG2(0x40E00048, ((x) & 0x60) >> 3)
+#define GAFR(x)		__REG2(0x40E00054, ((x) & 0x70) >> 2)
+
+#endif
+
+/* GPIO alternate function assignments */
+
+#define GPIO1_RST		1	/* reset */
+#define GPIO6_MMCCLK		6	/* MMC Clock */
+#define GPIO8_48MHz		7	/* 48 MHz clock output */
+#define GPIO8_MMCCS0		8	/* MMC Chip Select 0 */
+#define GPIO9_MMCCS1		9	/* MMC Chip Select 1 */
+#define GPIO10_RTCCLK		10	/* real time clock (1 Hz) */
+#define GPIO11_3_6MHz		11	/* 3.6 MHz oscillator out */
+#define GPIO12_32KHz		12	/* 32 kHz out */
+#define GPIO13_MBGNT		13	/* memory controller grant */
+#define GPIO14_MBREQ		14	/* alternate bus master request */
+#define GPIO15_nCS_1		15	/* chip select 1 */
+#define GPIO16_PWM0		16	/* PWM0 output */
+#define GPIO17_PWM1		17	/* PWM1 output */
+#define GPIO18_RDY		18	/* Ext. Bus Ready */
+#define GPIO19_DREQ1		19	/* External DMA Request */
+#define GPIO20_DREQ0		20	/* External DMA Request */
+#define GPIO23_SCLK		23	/* SSP clock */
+#define GPIO24_SFRM		24	/* SSP Frame */
+#define GPIO25_STXD		25	/* SSP transmit */
+#define GPIO26_SRXD		26	/* SSP receive */
+#define GPIO27_SEXTCLK		27	/* SSP ext_clk */
+#define GPIO28_BITCLK		28	/* AC97/I2S bit_clk */
+#define GPIO29_SDATA_IN		29	/* AC97 Sdata_in0 / I2S Sdata_in */
+#define GPIO30_SDATA_OUT	30	/* AC97/I2S Sdata_out */
+#define GPIO31_SYNC		31	/* AC97/I2S sync */
+#define GPIO32_SDATA_IN1	32	/* AC97 Sdata_in1 */
+#define GPIO33_nCS_5		33	/* chip select 5 */
+#define GPIO34_FFRXD		34	/* FFUART receive */
+#define GPIO34_MMCCS0		34	/* MMC Chip Select 0 */
+#define GPIO35_FFCTS		35	/* FFUART Clear to send */
+#define GPIO36_FFDCD		36	/* FFUART Data carrier detect */
+#define GPIO37_FFDSR		37	/* FFUART data set ready */
+#define GPIO38_FFRI		38	/* FFUART Ring Indicator */
+#define GPIO39_MMCCS1		39	/* MMC Chip Select 1 */
+#define GPIO39_FFTXD		39	/* FFUART transmit data */
+#define GPIO40_FFDTR		40	/* FFUART data terminal Ready */
+#define GPIO41_FFRTS		41	/* FFUART request to send */
+#define GPIO42_BTRXD		42	/* BTUART receive data */
+#define GPIO43_BTTXD		43	/* BTUART transmit data */
+#define GPIO44_BTCTS		44	/* BTUART clear to send */
+#define GPIO45_BTRTS		45	/* BTUART request to send */
+#define GPIO46_ICPRXD		46	/* ICP receive data */
+#define GPIO46_STRXD		46	/* STD_UART receive data */
+#define GPIO47_ICPTXD		47	/* ICP transmit data */
+#define GPIO47_STTXD		47	/* STD_UART transmit data */
+#define GPIO48_nPOE		48	/* Output Enable for Card Space */
+#define GPIO49_nPWE		49	/* Write Enable for Card Space */
+#define GPIO50_nPIOR		50	/* I/O Read for Card Space */
+#define GPIO51_nPIOW		51	/* I/O Write for Card Space */
+#define GPIO52_nPCE_1		52	/* Card Enable for Card Space */
+#define GPIO53_nPCE_2		53	/* Card Enable for Card Space */
+#define GPIO53_MMCCLK		53	/* MMC Clock */
+#define GPIO54_MMCCLK		54	/* MMC Clock */
+#define GPIO54_pSKTSEL		54	/* Socket Select for Card Space */
+#define GPIO55_nPREG		55	/* Card Address bit 26 */
+#define GPIO56_nPWAIT		56	/* Wait signal for Card Space */
+#define GPIO57_nIOIS16		57	/* Bus Width select for I/O Card Space */
+#define GPIO58_LDD_0		58	/* LCD data pin 0 */
+#define GPIO59_LDD_1		59	/* LCD data pin 1 */
+#define GPIO60_LDD_2		60	/* LCD data pin 2 */
+#define GPIO61_LDD_3		61	/* LCD data pin 3 */
+#define GPIO62_LDD_4		62	/* LCD data pin 4 */
+#define GPIO63_LDD_5		63	/* LCD data pin 5 */
+#define GPIO64_LDD_6		64	/* LCD data pin 6 */
+#define GPIO65_LDD_7		65	/* LCD data pin 7 */
+#define GPIO66_LDD_8		66	/* LCD data pin 8 */
+#define GPIO66_MBREQ		66	/* alternate bus master req */
+#define GPIO67_LDD_9		67	/* LCD data pin 9 */
+#define GPIO67_MMCCS0		67	/* MMC Chip Select 0 */
+#define GPIO68_LDD_10		68	/* LCD data pin 10 */
+#define GPIO68_MMCCS1		68	/* MMC Chip Select 1 */
+#define GPIO69_LDD_11		69	/* LCD data pin 11 */
+#define GPIO69_MMCCLK		69	/* MMC_CLK */
+#define GPIO70_LDD_12		70	/* LCD data pin 12 */
+#define GPIO70_RTCCLK		70	/* Real Time clock (1 Hz) */
+#define GPIO71_LDD_13		71	/* LCD data pin 13 */
+#define GPIO71_3_6MHz		71	/* 3.6 MHz Oscillator clock */
+#define GPIO72_LDD_14		72	/* LCD data pin 14 */
+#define GPIO72_32kHz		72	/* 32 kHz clock */
+#define GPIO73_LDD_15		73	/* LCD data pin 15 */
+#define GPIO73_MBGNT		73	/* Memory controller grant */
+#define GPIO74_LCD_FCLK		74	/* LCD Frame clock */
+#define GPIO75_LCD_LCLK		75	/* LCD line clock */
+#define GPIO76_LCD_PCLK		76	/* LCD Pixel clock */
+#define GPIO77_LCD_ACBIAS	77	/* LCD AC Bias */
+#define GPIO78_nCS_2		78	/* chip select 2 */
+#define GPIO79_nCS_3		79	/* chip select 3 */
+#define GPIO80_nCS_4		80	/* chip select 4 */
+
+/* GPIO alternate function mode & direction */
+
+#define GPIO_IN			0x000
+#define GPIO_OUT		0x080
+#define GPIO_ALT_FN_1_IN	0x100
+#define GPIO_ALT_FN_1_OUT	0x180
+#define GPIO_ALT_FN_2_IN	0x200
+#define GPIO_ALT_FN_2_OUT	0x280
+#define GPIO_ALT_FN_3_IN	0x300
+#define GPIO_ALT_FN_3_OUT	0x380
+#define GPIO_MD_MASK_NR		0x07f
+#define GPIO_MD_MASK_DIR	0x080
+#define GPIO_MD_MASK_FN		0x300
+
+#define GPIO1_RTS_MD		( 1 | GPIO_ALT_FN_1_IN)
+#define GPIO6_MMCCLK_MD		( 6 | GPIO_ALT_FN_1_OUT)
+#define GPIO8_48MHz_MD		( 8 | GPIO_ALT_FN_1_OUT)
+#define GPIO8_MMCCS0_MD		( 8 | GPIO_ALT_FN_1_OUT)
+#define GPIO9_MMCCS1_MD		( 9 | GPIO_ALT_FN_1_OUT)
+#define GPIO10_RTCCLK_MD	(10 | GPIO_ALT_FN_1_OUT)
+#define GPIO11_3_6MHz_MD	(11 | GPIO_ALT_FN_1_OUT)
+#define GPIO12_32KHz_MD		(12 | GPIO_ALT_FN_1_OUT)
+#define GPIO13_MBGNT_MD		(13 | GPIO_ALT_FN_2_OUT)
+#define GPIO14_MBREQ_MD		(14 | GPIO_ALT_FN_1_IN)
+#define GPIO15_nCS_1_MD		(15 | GPIO_ALT_FN_2_OUT)
+#define GPIO16_PWM0_MD		(16 | GPIO_ALT_FN_2_OUT)
+#define GPIO17_PWM1_MD		(17 | GPIO_ALT_FN_2_OUT)
+#define GPIO18_RDY_MD		(18 | GPIO_ALT_FN_1_IN)
+#define GPIO19_DREQ1_MD		(19 | GPIO_ALT_FN_1_IN)
+#define GPIO20_DREQ0_MD		(20 | GPIO_ALT_FN_1_IN)
+#define GPIO23_SCLK_md		(23 | GPIO_ALT_FN_2_OUT)
+#define GPIO24_SFRM_MD		(24 | GPIO_ALT_FN_2_OUT)
+#define GPIO25_STXD_MD		(25 | GPIO_ALT_FN_2_OUT)
+#define GPIO26_SRXD_MD		(26 | GPIO_ALT_FN_1_IN)
+#define GPIO27_SEXTCLK_MD	(27 | GPIO_ALT_FN_1_IN)
+#define GPIO28_BITCLK_AC97_MD	(28 | GPIO_ALT_FN_1_IN)
+#define GPIO28_BITCLK_I2S_MD	(28 | GPIO_ALT_FN_2_IN)
+#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
+#define GPIO29_SDATA_IN_I2S_MD	(29 | GPIO_ALT_FN_2_IN)
+#define GPIO30_SDATA_OUT_AC97_MD	(30 | GPIO_ALT_FN_2_OUT)
+#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_AC97_MD	(31 | GPIO_ALT_FN_2_OUT)
+#define GPIO31_SYNC_I2S_MD	(31 | GPIO_ALT_FN_1_OUT)
+#define GPIO32_SDATA_IN1_AC97_MD	(32 | GPIO_ALT_FN_1_IN)
+#define GPIO33_nCS_5_MD		(33 | GPIO_ALT_FN_2_OUT)
+#define GPIO34_FFRXD_MD		(34 | GPIO_ALT_FN_1_IN)
+#define GPIO34_MMCCS0_MD	(34 | GPIO_ALT_FN_2_OUT)
+#define GPIO35_FFCTS_MD		(35 | GPIO_ALT_FN_1_IN)
+#define GPIO36_FFDCD_MD		(36 | GPIO_ALT_FN_1_IN)
+#define GPIO37_FFDSR_MD		(37 | GPIO_ALT_FN_1_IN)
+#define GPIO38_FFRI_MD		(38 | GPIO_ALT_FN_1_IN)
+#define GPIO39_MMCCS1_MD	(39 | GPIO_ALT_FN_1_OUT)
+#define GPIO39_FFTXD_MD		(39 | GPIO_ALT_FN_2_OUT)
+#define GPIO40_FFDTR_MD		(40 | GPIO_ALT_FN_2_OUT)
+#define GPIO41_FFRTS_MD		(41 | GPIO_ALT_FN_2_OUT)
+#define GPIO42_BTRXD_MD		(42 | GPIO_ALT_FN_1_IN)
+#define GPIO43_BTTXD_MD		(43 | GPIO_ALT_FN_2_OUT)
+#define GPIO44_BTCTS_MD		(44 | GPIO_ALT_FN_1_IN)
+#define GPIO45_BTRTS_MD		(45 | GPIO_ALT_FN_2_OUT)
+#define GPIO46_ICPRXD_MD	(46 | GPIO_ALT_FN_1_IN)
+#define GPIO46_STRXD_MD		(46 | GPIO_ALT_FN_2_IN)
+#define GPIO47_ICPTXD_MD	(47 | GPIO_ALT_FN_2_OUT)
+#define GPIO47_STTXD_MD		(47 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_nPOE_MD		(48 | GPIO_ALT_FN_2_OUT)
+#define GPIO49_nPWE_MD		(49 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_nPIOR_MD		(50 | GPIO_ALT_FN_2_OUT)
+#define GPIO51_nPIOW_MD		(51 | GPIO_ALT_FN_2_OUT)
+#define GPIO52_nPCE_1_MD	(52 | GPIO_ALT_FN_2_OUT)
+#define GPIO53_nPCE_2_MD	(53 | GPIO_ALT_FN_2_OUT)
+#define GPIO53_MMCCLK_MD	(53 | GPIO_ALT_FN_1_OUT)
+#define GPIO54_MMCCLK_MD	(54 | GPIO_ALT_FN_1_OUT)
+#define GPIO54_pSKTSEL_MD	(54 | GPIO_ALT_FN_2_OUT)
+#define GPIO55_nPREG_MD		(55 | GPIO_ALT_FN_2_OUT)
+#define GPIO56_nPWAIT_MD	(56 | GPIO_ALT_FN_1_IN)
+#define GPIO57_nIOIS16_MD	(57 | GPIO_ALT_FN_1_IN)
+#define GPIO58_LDD_0_MD		(58 | GPIO_ALT_FN_2_OUT)
+#define GPIO59_LDD_1_MD		(59 | GPIO_ALT_FN_2_OUT)
+#define GPIO60_LDD_2_MD		(60 | GPIO_ALT_FN_2_OUT)
+#define GPIO61_LDD_3_MD		(61 | GPIO_ALT_FN_2_OUT)
+#define GPIO62_LDD_4_MD		(62 | GPIO_ALT_FN_2_OUT)
+#define GPIO63_LDD_5_MD		(63 | GPIO_ALT_FN_2_OUT)
+#define GPIO64_LDD_6_MD		(64 | GPIO_ALT_FN_2_OUT)
+#define GPIO65_LDD_7_MD		(65 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_LDD_8_MD		(66 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_MBREQ_MD		(66 | GPIO_ALT_FN_1_IN)
+#define GPIO67_LDD_9_MD		(67 | GPIO_ALT_FN_2_OUT)
+#define GPIO67_MMCCS0_MD	(67 | GPIO_ALT_FN_1_OUT)
+#define GPIO68_LDD_10_MD	(68 | GPIO_ALT_FN_2_OUT)
+#define GPIO68_MMCCS1_MD	(68 | GPIO_ALT_FN_1_OUT)
+#define GPIO69_LDD_11_MD	(69 | GPIO_ALT_FN_2_OUT)
+#define GPIO69_MMCCLK_MD	(69 | GPIO_ALT_FN_1_OUT)
+#define GPIO70_LDD_12_MD	(70 | GPIO_ALT_FN_2_OUT)
+#define GPIO70_RTCCLK_MD	(70 | GPIO_ALT_FN_1_OUT)
+#define GPIO71_LDD_13_MD	(71 | GPIO_ALT_FN_2_OUT)
+#define GPIO71_3_6MHz_MD	(71 | GPIO_ALT_FN_1_OUT)
+#define GPIO72_LDD_14_MD	(72 | GPIO_ALT_FN_2_OUT)
+#define GPIO72_32kHz_MD		(72 | GPIO_ALT_FN_1_OUT)
+#define GPIO73_LDD_15_MD	(73 | GPIO_ALT_FN_2_OUT)
+#define GPIO73_MBGNT_MD		(73 | GPIO_ALT_FN_1_OUT)
+#define GPIO74_LCD_FCLK_MD	(74 | GPIO_ALT_FN_2_OUT)
+#define GPIO75_LCD_LCLK_MD	(75 | GPIO_ALT_FN_2_OUT)
+#define GPIO76_LCD_PCLK_MD	(76 | GPIO_ALT_FN_2_OUT)
+#define GPIO77_LCD_ACBIAS_MD	(77 | GPIO_ALT_FN_2_OUT)
+#define GPIO78_nCS_2_MD		(78 | GPIO_ALT_FN_2_OUT)
+#define GPIO79_nCS_3_MD		(79 | GPIO_ALT_FN_2_OUT)
+#define GPIO80_nCS_4_MD		(80 | GPIO_ALT_FN_2_OUT)
+
+#define GPIO117_SCL	     (117 | GPIO_ALT_FN_1_OUT)
+#define GPIO118_SDA	     (118 | GPIO_ALT_FN_1_OUT)
+
+/*
+ * Power Manager
+ */
+#define PMCR		__REG(0x40F00000)  /* Power Manager Control Register */
+#define PSSR		__REG(0x40F00004)  /* Power Manager Sleep Status Register */
+#define PSPR		__REG(0x40F00008)  /* Power Manager Scratch Pad Register */
+#define PWER		__REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
+#define PRER		__REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
+#define PFER		__REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
+#define PEDR		__REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
+#define PCFR		__REG(0x40F0001C)  /* Power Manager General Configuration Register */
+#define PGSR0		__REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
+#define PGSR1		__REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
+#define PGSR2		__REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
+#define PGSR3		__REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
+#define RCSR		__REG(0x40F00030)  /* Reset Controller Status Register */
+
+#define	   PSLR	   __REG(0x40F00034)	/* Power Manager Sleep Config Register */
+#define	   PSTR	   __REG(0x40F00038)	/* Power Manager Standby Config Register */
+#define	   PSNR	   __REG(0x40F0003C)	/* Power Manager Sense Config Register */
+#define	   PVCR	   __REG(0x40F00040)	/* Power Manager VoltageControl Register */
+#define	   PKWR	   __REG(0x40F00050)	/* Power Manager KB Wake-up Enable Reg */
+#define	   PKSR	   __REG(0x40F00054)	/* Power Manager KB Level-Detect Register */
+#define	   PCMD(x) __REG(0x40F00080 + x*4)
+#define	   PCMD0   __REG(0x40F00080 + 0 * 4)
+#define	   PCMD1   __REG(0x40F00080 + 1 * 4)
+#define	   PCMD2   __REG(0x40F00080 + 2 * 4)
+#define	   PCMD3   __REG(0x40F00080 + 3 * 4)
+#define	   PCMD4   __REG(0x40F00080 + 4 * 4)
+#define	   PCMD5   __REG(0x40F00080 + 5 * 4)
+#define	   PCMD6   __REG(0x40F00080 + 6 * 4)
+#define	   PCMD7   __REG(0x40F00080 + 7 * 4)
+#define	   PCMD8   __REG(0x40F00080 + 8 * 4)
+#define	   PCMD9   __REG(0x40F00080 + 9 * 4)
+#define	   PCMD10  __REG(0x40F00080 + 10 * 4)
+#define	   PCMD11  __REG(0x40F00080 + 11 * 4)
+#define	   PCMD12  __REG(0x40F00080 + 12 * 4)
+#define	   PCMD13  __REG(0x40F00080 + 13 * 4)
+#define	   PCMD14  __REG(0x40F00080 + 14 * 4)
+#define	   PCMD15  __REG(0x40F00080 + 15 * 4)
+#define	   PCMD16  __REG(0x40F00080 + 16 * 4)
+#define	   PCMD17  __REG(0x40F00080 + 17 * 4)
+#define	   PCMD18  __REG(0x40F00080 + 18 * 4)
+#define	   PCMD19  __REG(0x40F00080 + 19 * 4)
+#define	   PCMD20  __REG(0x40F00080 + 20 * 4)
+#define	   PCMD21  __REG(0x40F00080 + 21 * 4)
+#define	   PCMD22  __REG(0x40F00080 + 22 * 4)
+#define	   PCMD23  __REG(0x40F00080 + 23 * 4)
+#define	   PCMD24  __REG(0x40F00080 + 24 * 4)
+#define	   PCMD25  __REG(0x40F00080 + 25 * 4)
+#define	   PCMD26  __REG(0x40F00080 + 26 * 4)
+#define	   PCMD27  __REG(0x40F00080 + 27 * 4)
+#define	   PCMD28  __REG(0x40F00080 + 28 * 4)
+#define	   PCMD29  __REG(0x40F00080 + 29 * 4)
+#define	   PCMD30  __REG(0x40F00080 + 30 * 4)
+#define	   PCMD31  __REG(0x40F00080 + 31 * 4)
+
+#define	   PCMD_MBC    (1<<12)
+#define	   PCMD_DCE    (1<<11)
+#define	   PCMD_LC     (1<<10)
+/* FIXME:  PCMD_SQC need be checked.   */
+#define	   PCMD_SQC    (3<<8)  /* currently only bit 8 is changerable, */
+				/* bit 9 should be 0 all day. */
+#define PVCR_VCSA		   (0x1<<14)
+#define PVCR_CommandDelay	   (0xf80)
+/* define MACRO for Power Manager General Configuration Register (PCFR) */
+#define PCFR_FVC		   (0x1 << 10)
+#define PCFR_PI2C_EN		   (0x1 << 6)
+
+#define PSSR_OTGPH	(1 << 6)	/* OTG Peripheral control Hold */
+#define PSSR_RDH	(1 << 5)	/* Read Disable Hold */
+#define PSSR_PH		(1 << 4)	/* Peripheral Control Hold */
+#define PSSR_VFS	(1 << 2)	/* VDD Fault Status */
+#define PSSR_BFS	(1 << 1)	/* Battery Fault Status */
+#define PSSR_SSS	(1 << 0)	/* Software Sleep Status */
+
+#define PCFR_DS		(1 << 3)	/* Deep Sleep Mode */
+#define PCFR_FS		(1 << 2)	/* Float Static Chip Selects */
+#define PCFR_FP		(1 << 1)	/* Float PCMCIA controls */
+#define PCFR_OPDE	(1 << 0)	/* 3.6864 MHz oscillator power-down enable */
+
+#define RCSR_GPR	(1 << 3)	/* GPIO Reset */
+#define RCSR_SMR	(1 << 2)	/* Sleep Mode */
+#define RCSR_WDR	(1 << 1)	/* Watchdog Reset */
+#define RCSR_HWR	(1 << 0)	/* Hardware Reset */
+
+/*
+ * SSP Serial Port Registers
+ */
+#define SSCR0		__REG(0x41000000)  /* SSP Control Register 0 */
+#define SSCR1		__REG(0x41000004)  /* SSP Control Register 1 */
+#define SSSR		__REG(0x41000008)  /* SSP Status Register */
+#define SSITR		__REG(0x4100000C)  /* SSP Interrupt Test Register */
+#define SSDR		__REG(0x41000010)  /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
+
+/*
+ * MultiMediaCard (MMC) controller
+ */
+#define MMC_STRPCL	__REG(0x41100000)  /* Control to start and stop MMC clock */
+#define MMC_STAT	__REG(0x41100004)  /* MMC Status Register (read only) */
+#define MMC_CLKRT	__REG(0x41100008)  /* MMC clock rate */
+#define MMC_SPI		__REG(0x4110000c)  /* SPI mode control bits */
+#define MMC_CMDAT	__REG(0x41100010)  /* Command/response/data sequence control */
+#define MMC_RESTO	__REG(0x41100014)  /* Expected response time out */
+#define MMC_RDTO	__REG(0x41100018)  /* Expected data read time out */
+#define MMC_BLKLEN	__REG(0x4110001c)  /* Block length of data transaction */
+#define MMC_NOB		__REG(0x41100020)  /* Number of blocks, for block mode */
+#define MMC_PRTBUF	__REG(0x41100024)  /* Partial MMC_TXFIFO FIFO written */
+#define MMC_I_MASK	__REG(0x41100028)  /* Interrupt Mask */
+#define MMC_I_REG	__REG(0x4110002c)  /* Interrupt Register (read only) */
+#define MMC_CMD		__REG(0x41100030)  /* Index of current command */
+#define MMC_ARGH	__REG(0x41100034)  /* MSW part of the current command argument */
+#define MMC_ARGL	__REG(0x41100038)  /* LSW part of the current command argument */
+#define MMC_RES		__REG(0x4110003c)  /* Response FIFO (read only) */
+#define MMC_RXFIFO	__REG(0x41100040)  /* Receive FIFO (read only) */
+#define MMC_TXFIFO	__REG(0x41100044)  /* Transmit FIFO (write only) */
+
+/*
+ * Core Clock
+ */
+#define CCCR		__REG(0x41300000)  /* Core Clock Configuration Register */
+#define CKEN		__REG(0x41300004)  /* Clock Enable Register */
+#define OSCC		__REG(0x41300008)  /* Oscillator Configuration Register */
+
+#define CCCR_N_MASK	0x0380		/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#if !defined(CONFIG_PXA27X)
+#define CCCR_M_MASK	0x0060		/* Memory Frequency to Run Mode Frequency Multiplier */
+#endif
+#define CCCR_L_MASK	0x001f		/* Crystal Frequency to Memory Frequency Multiplier */
+
+#define CKEN24_CAMERA	(1 << 24)	/* Camera Interface Clock Enable */
+#define CKEN23_SSP1	(1 << 23)	/* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC	(1 << 22)	/* Memory Controller Clock Enable */
+#define CKEN21_MEMSTK	(1 << 21)	/* Memory Stick Host Controller */
+#define CKEN20_IM	(1 << 20)	/* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD	(1 << 19)	/* Keypad Interface Clock Enable */
+#define CKEN18_USIM	(1 << 18)	/* USIM Unit Clock Enable */
+#define CKEN17_MSL	(1 << 17)	/* MSL Unit Clock Enable */
+#define CKEN16_LCD	(1 << 16)	/* LCD Unit Clock Enable */
+#define CKEN15_PWRI2C	(1 << 15)	/* PWR I2C Unit Clock Enable */
+#define CKEN14_I2C	(1 << 14)	/* I2C Unit Clock Enable */
+#define CKEN13_FICP	(1 << 13)	/* FICP Unit Clock Enable */
+#define CKEN12_MMC	(1 << 12)	/* MMC Unit Clock Enable */
+#define CKEN11_USB	(1 << 11)	/* USB Unit Clock Enable */
+#if defined(CONFIG_PXA27X)
+#define CKEN10_USBHOST	(1 << 10)	/* USB Host Unit Clock Enable */
+#define CKEN24_CAMERA	(1 << 24)	/* Camera Unit Clock Enable */
+#endif
+#define CKEN8_I2S	(1 << 8)	/* I2S Unit Clock Enable */
+#define CKEN7_BTUART	(1 << 7)	/* BTUART Unit Clock Enable */
+#define CKEN6_FFUART	(1 << 6)	/* FFUART Unit Clock Enable */
+#define CKEN5_STUART	(1 << 5)	/* STUART Unit Clock Enable */
+#define CKEN3_SSP	(1 << 3)	/* SSP Unit Clock Enable */
+#define CKEN2_AC97	(1 << 2)	/* AC97 Unit Clock Enable */
+#define CKEN1_PWM1	(1 << 1)	/* PWM1 Clock Enable */
+#define CKEN0_PWM0	(1 << 0)	/* PWM0 Clock Enable */
+
+#define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */
+#define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) */
+
+#if !defined(CONFIG_PXA27X)
+#define	 CCCR_L09      (0x1F)
+#define	 CCCR_L27      (0x1)
+#define	 CCCR_L32      (0x2)
+#define	 CCCR_L36      (0x3)
+#define	 CCCR_L40      (0x4)
+#define	 CCCR_L45      (0x5)
+
+#define	 CCCR_M1       (0x1 << 5)
+#define	 CCCR_M2       (0x2 << 5)
+#define	 CCCR_M4       (0x3 << 5)
+
+#define	 CCCR_N10      (0x2 << 7)
+#define	 CCCR_N15      (0x3 << 7)
+#define	 CCCR_N20      (0x4 << 7)
+#define	 CCCR_N25      (0x5 << 7)
+#define	 CCCR_N30      (0x6 << 7)
+#endif
+
+/*
+ * LCD
+ */
+#define LCCR0		__REG(0x44000000)  /* LCD Controller Control Register 0 */
+#define LCCR1		__REG(0x44000004)  /* LCD Controller Control Register 1 */
+#define LCCR2		__REG(0x44000008)  /* LCD Controller Control Register 2 */
+#define LCCR3		__REG(0x4400000C)  /* LCD Controller Control Register 3 */
+#define DFBR0		__REG(0x44000020)  /* DMA Channel 0 Frame Branch Register */
+#define DFBR1		__REG(0x44000024)  /* DMA Channel 1 Frame Branch Register */
+#define LCSR0		__REG(0x44000038)  /* LCD Controller Status Register */
+#define LCSR1		__REG(0x44000034)  /* LCD Controller Status Register */
+#define LIIDR		__REG(0x4400003C)  /* LCD Controller Interrupt ID Register */
+#define TMEDRGBR	__REG(0x44000040)  /* TMED RGB Seed Register */
+#define TMEDCR		__REG(0x44000044)  /* TMED Control Register */
+
+#define FDADR0		__REG(0x44000200)  /* DMA Channel 0 Frame Descriptor Address Register */
+#define FSADR0		__REG(0x44000204)  /* DMA Channel 0 Frame Source Address Register */
+#define FIDR0		__REG(0x44000208)  /* DMA Channel 0 Frame ID Register */
+#define LDCMD0		__REG(0x4400020C)  /* DMA Channel 0 Command Register */
+#define FDADR1		__REG(0x44000210)  /* DMA Channel 1 Frame Descriptor Address Register */
+#define FSADR1		__REG(0x44000214)  /* DMA Channel 1 Frame Source Address Register */
+#define FIDR1		__REG(0x44000218)  /* DMA Channel 1 Frame ID Register */
+#define LDCMD1		__REG(0x4400021C)  /* DMA Channel 1 Command Register */
+
+#define LCCR0_ENB	(1 << 0)	/* LCD Controller enable */
+#define LCCR0_CMS	(1 << 1)	/* Color = 0, Monochrome = 1 */
+#define LCCR0_SDS	(1 << 2)	/* Single Panel = 0, Dual Panel = 1 */
+#define LCCR0_LDM	(1 << 3)	/* LCD Disable Done Mask */
+#define LCCR0_SFM	(1 << 4)	/* Start of frame mask */
+#define LCCR0_IUM	(1 << 5)	/* Input FIFO underrun mask */
+#define LCCR0_EFM	(1 << 6)	/* End of Frame mask */
+#define LCCR0_PAS	(1 << 7)	/* Passive = 0, Active = 1 */
+#define LCCR0_BLE	(1 << 8)	/* Little Endian = 0, Big Endian = 1 */
+#define LCCR0_DPD	(1 << 9)	/* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */
+#define LCCR0_DIS	(1 << 10)	/* LCD Disable */
+#define LCCR0_QDM	(1 << 11)	/* LCD Quick Disable mask */
+#define LCCR0_PDD	(0xff << 12)	/* Palette DMA request delay */
+#define LCCR0_PDD_S	12
+#define LCCR0_BM	(1 << 20)	/* Branch mask */
+#define LCCR0_OUM	(1 << 21)	/* Output FIFO underrun mask */
+#if defined(CONFIG_PXA27X)
+#define LCCR0_LCDT	(1 << 22)	/* LCD Panel Type */
+#define LCCR0_RDSTM	(1 << 23)	/* Read Status Interrupt Mask */
+#define LCCR0_CMDIM	(1 << 24)	/* Command Interrupt Mask */
+#endif
+
+#define LCCR1_PPL	Fld (10, 0)	 /* Pixels Per Line - 1 */
+#define LCCR1_DisWdth(Pixel)		/* Display Width [1..800 pix.]	*/ \
+			(((Pixel) - 1) << FShft (LCCR1_PPL))
+
+#define LCCR1_HSW	Fld (6, 10)	/* Horizontal Synchronization	  */
+#define LCCR1_HorSnchWdth(Tpix)		/* Horizontal Synchronization	  */ \
+					/* pulse Width [1..64 Tpix]	  */ \
+			(((Tpix) - 1) << FShft (LCCR1_HSW))
+
+#define LCCR1_ELW	Fld (8, 16)	/* End-of-Line pixel clock Wait	   */
+					/* count - 1 [Tpix]		   */
+#define LCCR1_EndLnDel(Tpix)		/*  End-of-Line Delay		   */ \
+					/*  [1..256 Tpix]		   */ \
+			(((Tpix) - 1) << FShft (LCCR1_ELW))
+
+#define LCCR1_BLW	Fld (8, 24)	/* Beginning-of-Line pixel clock   */
+					/* Wait count - 1 [Tpix]	   */
+#define LCCR1_BegLnDel(Tpix)		/*  Beginning-of-Line Delay	   */ \
+					/*  [1..256 Tpix]		   */ \
+			(((Tpix) - 1) << FShft (LCCR1_BLW))
+
+
+#define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1		   */
+#define LCCR2_DisHght(Line)		/*  Display Height [1..1024 lines] */ \
+			(((Line) - 1) << FShft (LCCR2_LPP))
+
+#define LCCR2_VSW	Fld (6, 10)	/* Vertical Synchronization pulse  */
+					/* Width - 1 [Tln] (L_FCLK)	   */
+#define LCCR2_VrtSnchWdth(Tln)		/*  Vertical Synchronization pulse */ \
+					/*  Width [1..64 Tln]		   */ \
+			(((Tln) - 1) << FShft (LCCR2_VSW))
+
+#define LCCR2_EFW	Fld (8, 16)	/* End-of-Frame line clock Wait	   */
+					/* count [Tln]			   */
+#define LCCR2_EndFrmDel(Tln)		/*  End-of-Frame Delay		   */ \
+					/*  [0..255 Tln]		   */ \
+			((Tln) << FShft (LCCR2_EFW))
+
+#define LCCR2_BFW	Fld (8, 24)	/* Beginning-of-Frame line clock   */
+					/* Wait count [Tln]		   */
+#define LCCR2_BegFrmDel(Tln)		/*  Beginning-of-Frame Delay	   */ \
+					/*  [0..255 Tln]		   */ \
+			((Tln) << FShft (LCCR2_BFW))
+
+#if 0
+#define LCCR3_PCD	(0xff)		/* Pixel clock divisor */
+#define LCCR3_ACB	(0xff << 8)	/* AC Bias pin frequency */
+#define LCCR3_ACB_S	8
+#endif
+
+#define LCCR3_API	(0xf << 16)	/* AC Bias pin trasitions per interrupt */
+#define LCCR3_API_S	16
+#define LCCR3_VSP	(1 << 20)	/* vertical sync polarity */
+#define LCCR3_HSP	(1 << 21)	/* horizontal sync polarity */
+#define LCCR3_PCP	(1 << 22)	/* pixel clock polarity */
+#define LCCR3_OEP	(1 << 23)	/* output enable polarity */
+#if 0
+#define LCCR3_BPP	(7 << 24)	/* bits per pixel */
+#define LCCR3_BPP_S	24
+#endif
+#define LCCR3_DPC	(1 << 27)	/* double pixel clock mode */
+
+#define LCCR3_PDFOR_0	 (0 << 30)
+#define LCCR3_PDFOR_1	 (1 << 30)
+#define LCCR3_PDFOR_2	 (2 << 30)
+#define LCCR3_PDFOR_3	 (3 << 30)
+
+
+#define LCCR3_PCD	Fld (8, 0)	/* Pixel Clock Divisor */
+#define LCCR3_PixClkDiv(Div)		/* Pixel Clock Divisor */ \
+			(((Div) << FShft (LCCR3_PCD)))
+
+
+#define LCCR3_BPP	Fld (3, 24)	/* Bit Per Pixel */
+#define LCCR3_Bpp(Bpp)			/* Bit Per Pixel */ \
+			((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26)))
+
+#define LCCR3_ACB	Fld (8, 8)	/* AC Bias */
+#define LCCR3_Acb(Acb)			/* BAC Bias */ \
+			(((Acb) << FShft (LCCR3_ACB)))
+
+#define LCCR3_HorSnchH	(LCCR3_HSP*0)	/*  Horizontal Synchronization	   */
+					/*  pulse active High		   */
+#define LCCR3_HorSnchL	(LCCR3_HSP*1)	/*  Horizontal Synchronization	   */
+
+#define LCCR3_VrtSnchH	(LCCR3_VSP*0)	/*  Vertical Synchronization pulse */
+					/*  active High			   */
+#define LCCR3_VrtSnchL	(LCCR3_VSP*1)	/*  Vertical Synchronization pulse */
+					/*  active Low			   */
+
+#define LCSR0_LDD	(1 << 0)	/* LCD Disable Done */
+#define LCSR0_SOF	(1 << 1)	/* Start of frame */
+#define LCSR0_BER	(1 << 2)	/* Bus error */
+#define LCSR0_ABC	(1 << 3)	/* AC Bias count */
+#define LCSR0_IUL	(1 << 4)	/* input FIFO underrun Lower panel */
+#define LCSR0_IUU	(1 << 5)	/* input FIFO underrun Upper panel */
+#define LCSR0_OU	(1 << 6)	/* output FIFO underrun */
+#define LCSR0_QD	(1 << 7)	/* quick disable */
+#define LCSR0_EOF0	(1 << 8)	/* end of frame */
+#define LCSR0_BS	(1 << 9)	/* branch status */
+#define LCSR0_SINT	(1 << 10)	/* subsequent interrupt */
+
+#define LCSR1_SOF1	(1 << 0)
+#define LCSR1_SOF2	(1 << 1)
+#define LCSR1_SOF3	(1 << 2)
+#define LCSR1_SOF4	(1 << 3)
+#define LCSR1_SOF5	(1 << 4)
+#define LCSR1_SOF6	(1 << 5)
+
+#define LCSR1_EOF1	(1 << 8)
+#define LCSR1_EOF2	(1 << 9)
+#define LCSR1_EOF3	(1 << 10)
+#define LCSR1_EOF4	(1 << 11)
+#define LCSR1_EOF5	(1 << 12)
+#define LCSR1_EOF6	(1 << 13)
+
+#define LCSR1_BS1	(1 << 16)
+#define LCSR1_BS2	(1 << 17)
+#define LCSR1_BS3	(1 << 18)
+#define LCSR1_BS4	(1 << 19)
+#define LCSR1_BS5	(1 << 20)
+#define LCSR1_BS6	(1 << 21)
+
+#define LCSR1_IU2	(1 << 25)
+#define LCSR1_IU3	(1 << 26)
+#define LCSR1_IU4	(1 << 27)
+#define LCSR1_IU5	(1 << 28)
+#define LCSR1_IU6	(1 << 29)
+
+#define LDCMD_PAL	(1 << 26)	/* instructs DMA to load palette buffer */
+#if defined(CONFIG_PXA27X)
+#define LDCMD_SOFINT	(1 << 22)
+#define LDCMD_EOFINT	(1 << 21)
+#endif
+
+/*
+ * Memory controller
+ */
+#define MEMC_BASE	__REG(0x48000000)  /* Base of Memory Controller */
+#define MDCNFG_OFFSET	0x0
+#define MDREFR_OFFSET	0x4
+#define MSC0_OFFSET	0x8
+#define MSC1_OFFSET	0xC
+#define MSC2_OFFSET	0x10
+#define MECR_OFFSET	0x14
+#define SXLCR_OFFSET	0x18
+#define SXCNFG_OFFSET	0x1C
+#define FLYCNFG_OFFSET	0x20
+#define SXMRS_OFFSET	0x24
+#define MCMEM0_OFFSET	0x28
+#define MCMEM1_OFFSET	0x2C
+#define MCATT0_OFFSET	0x30
+#define MCATT1_OFFSET	0x34
+#define MCIO0_OFFSET	0x38
+#define MCIO1_OFFSET	0x3C
+#define MDMRS_OFFSET	0x40
+
+#define MDCNFG		__REG(0x48000000)  /* SDRAM Configuration Register 0 */
+#define MDCNFG_DE0	0x00000001
+#define MDCNFG_DE1	0x00000002
+#define MDCNFG_DE2	0x00010000
+#define MDCNFG_DE3	0x00020000
+#define MDCNFG_DWID0	0x00000004
+
+#define MDREFR		__REG(0x48000004)  /* SDRAM Refresh Control Register */
+#define MSC0		__REG(0x48000008)  /* Static Memory Control Register 0 */
+#define MSC1		__REG(0x4800000C)  /* Static Memory Control Register 1 */
+#define MSC2		__REG(0x48000010)  /* Static Memory Control Register 2 */
+#define MECR		__REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXLCR		__REG(0x48000018)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
+#define SXCNFG		__REG(0x4800001C)  /* Synchronous Static Memory Control Register */
+#define SXMRS		__REG(0x48000024)  /* MRS value to be written to Synchronous Flash or SMROM */
+#define MCMEM0		__REG(0x48000028)  /* Card interface Common Memory Space Socket 0 Timing */
+#define MCMEM1		__REG(0x4800002C)  /* Card interface Common Memory Space Socket 1 Timing */
+#define MCATT0		__REG(0x48000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCATT1		__REG(0x48000034)  /* Card interface Attribute Space Socket 1 Timing Configuration */
+#define MCIO0		__REG(0x48000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MCIO1		__REG(0x4800003C)  /* Card interface I/O Space Socket 1 Timing Configuration */
+#define MDMRS		__REG(0x48000040)  /* MRS value to be written to SDRAM */
+#define BOOT_DEF	__REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
+
+#define MDREFR_K2FREE	(1 << 25)	/* SDRAM Free-Running Control */
+#define MDREFR_K1FREE	(1 << 24)	/* SDRAM Free-Running Control */
+#define MDREFR_K0FREE	(1 << 23)	/* SDRAM Free-Running Control */
+#define MDREFR_SLFRSH	(1 << 22)	/* SDRAM Self-Refresh Control/Status */
+#define MDREFR_APD	(1 << 20)	/* SDRAM/SSRAM Auto-Power-Down Enable */
+#define MDREFR_K2DB2	(1 << 19)	/* SDCLK2 Divide by 2 Control/Status */
+#define MDREFR_K2RUN	(1 << 18)	/* SDCLK2 Run Control/Status */
+#define MDREFR_K1DB2	(1 << 17)	/* SDCLK1 Divide by 2 Control/Status */
+#define MDREFR_K1RUN	(1 << 16)	/* SDCLK1 Run Control/Status */
+#define MDREFR_E1PIN	(1 << 15)	/* SDCKE1 Level Control/Status */
+#define MDREFR_K0DB2	(1 << 14)	/* SDCLK0 Divide by 2 Control/Status */
+#define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
+#define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */
+
+#if defined(CONFIG_PXA27X)
+
+#define ARB_CNTRL	__REG(0x48000048)  /* Arbiter Control Register */
+
+#define ARB_DMA_SLV_PARK	(1<<31)	   /* Be parked with DMA slave when idle */
+#define ARB_CI_PARK		(1<<30)	   /* Be parked with Camera Interface when idle */
+#define ARB_EX_MEM_PARK		(1<<29)	   /* Be parked with external MEMC when idle */
+#define ARB_INT_MEM_PARK	(1<<28)	   /* Be parked with internal MEMC when idle */
+#define ARB_USB_PARK		(1<<27)	   /* Be parked with USB when idle */
+#define ARB_LCD_PARK		(1<<26)	   /* Be parked with LCD when idle */
+#define ARB_DMA_PARK		(1<<25)	   /* Be parked with DMA when idle */
+#define ARB_CORE_PARK		(1<<24)	   /* Be parked with core when idle */
+#define ARB_LOCK_FLAG		(1<<23)	   /* Only Locking masters gain access to the bus */
+
+/* Interrupt Controller */
+
+#define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
+#define ICLR2		__REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
+#define ICFP2		__REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2		__REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
+
+/* General Purpose I/O */
+
+#define GAFR3_L		__REG(0x40E0006C)  /* GPIO Alternate Function Select Register GPIO<111:96> */
+#define GAFR3_U		__REG(0x40E00070)  /* GPIO Alternate Function Select Register GPIO<127:112> */
+#define GPLR3		__REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<127:96> */
+#define GPDR3		__REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<127:96> */
+#define GPSR3		__REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<127:96> */
+#define GPCR3		__REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO <127:96> */
+#define GRER3		__REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
+#define GFER3		__REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
+#define GEDR3		__REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<127:96> */
+
+/* Core Clock */
+
+#define CCSR		__REG(0x4130000C) /* Core Clock Status Register */
+
+#define CKEN23_SSP1	(1 << 23) /* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC	(1 << 22) /* Memory Controler */
+#define CKEN21_MSHC	(1 << 21) /* Memery Stick Host Controller */
+#define CKEN20_IM	(1 << 20) /* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD	(1 << 19) /* Keypad Interface Clock Enable */
+#define CKEN18_USIM	(1 << 18) /* USIM Unit Clock Enable */
+#define CKEN17_MSL	(1 << 17) /* MSL Interface Unit Clock Enable */
+#define CKEN15_PWR_I2C	(1 << 15) /* PWR_I2C Unit Clock Enable */
+#define CKEN9_OST	(1 << 9)  /* OS Timer Unit Clock Enable */
+#define CKEN4_SSP3	(1 << 4)  /* SSP3 Unit Clock Enable */
+
+/* Memory controller */
+
+#define MDREFR_K0DB4	(1 << 29)	  /* SDCLK[0] divide by 4 */
+
+/* LCD registers */
+#define LCCR4		__REG(0x44000010)  /* LCD Controller Control Register 4 */
+#define LCCR5		__REG(0x44000014)  /* LCD Controller Control Register 5 */
+#define FBR0		__REG(0x44000020)  /* DMA Channel 0 Frame Branch Register */
+#define FBR1		__REG(0x44000024)  /* DMA Channel 1 Frame Branch Register */
+#define FBR2		__REG(0x44000028)  /* DMA Channel 2 Frame Branch Register */
+#define FBR3		__REG(0x4400002C)  /* DMA Channel 3 Frame Branch Register */
+#define FBR4		__REG(0x44000030)  /* DMA Channel 4 Frame Branch Register */
+#define FDADR2		__REG(0x44000220)  /* DMA Channel 2 Frame Descriptor Address Register */
+#define FSADR2		__REG(0x44000224)  /* DMA Channel 2 Frame Source Address Register */
+#define FIDR2		__REG(0x44000228)  /* DMA Channel 2 Frame ID Register */
+#define LDCMD2		__REG(0x4400022C)  /* DMA Channel 2 Command Register */
+#define FDADR3		__REG(0x44000230)  /* DMA Channel 3 Frame Descriptor Address Register */
+#define FSADR3		__REG(0x44000234)  /* DMA Channel 3 Frame Source Address Register */
+#define FIDR3		__REG(0x44000238)  /* DMA Channel 3 Frame ID Register */
+#define LDCMD3		__REG(0x4400023C)  /* DMA Channel 3 Command Register */
+#define FDADR4		__REG(0x44000240)  /* DMA Channel 4 Frame Descriptor Address Register */
+#define FSADR4		__REG(0x44000244)  /* DMA Channel 4 Frame Source Address Register */
+#define FIDR4		__REG(0x44000248)  /* DMA Channel 4 Frame ID Register */
+#define LDCMD4		__REG(0x4400024C)  /* DMA Channel 4 Command Register */
+#define FDADR5		__REG(0x44000250)  /* DMA Channel 5 Frame Descriptor Address Register */
+#define FSADR5		__REG(0x44000254)  /* DMA Channel 5 Frame Source Address Register */
+#define FIDR5		__REG(0x44000258)  /* DMA Channel 5 Frame ID Register */
+#define LDCMD5		__REG(0x4400025C)  /* DMA Channel 5 Command Register */
+
+#define OVL1C1		__REG(0x44000050)  /* Overlay 1 Control Register 1 */
+#define OVL1C2		__REG(0x44000060)  /* Overlay 1 Control Register 2 */
+#define OVL2C1		__REG(0x44000070)  /* Overlay 2 Control Register 1 */
+#define OVL2C2		__REG(0x44000080)  /* Overlay 2 Control Register 2 */
+#define CCR		__REG(0x44000090)  /* Cursor Control Register */
+
+#define FBR5		__REG(0x44000110)  /* DMA Channel 5 Frame Branch Register */
+#define FBR6		__REG(0x44000114)  /* DMA Channel 6 Frame Branch Register */
+
+#define LCCR0_LDDALT	(1<<26)		/* LDD Alternate mapping bit when base pixel is RGBT16 */
+#define LCCR0_OUC	(1<<25)		/* Overlay Underlay Control Bit */
+
+#define LCCR5_SOFM1	(1<<0)		/* Start Of Frame Mask for Overlay 1 (channel 1) */
+#define LCCR5_SOFM2	(1<<1)		/* Start Of Frame Mask for Overlay 2 (channel 2) */
+#define LCCR5_SOFM3	(1<<2)		/* Start Of Frame Mask for Overlay 2 (channel 3) */
+#define LCCR5_SOFM4	(1<<3)		/* Start Of Frame Mask for Overlay 2 (channel 4) */
+#define LCCR5_SOFM5	(1<<4)		/* Start Of Frame Mask for cursor (channel 5) */
+#define LCCR5_SOFM6	(1<<5)		/* Start Of Frame Mask for command data (channel 6) */
+
+#define LCCR5_EOFM1	(1<<8)		/* End Of Frame Mask for Overlay 1 (channel 1) */
+#define LCCR5_EOFM2	(1<<9)		/* End Of Frame Mask for Overlay 2 (channel 2) */
+#define LCCR5_EOFM3	(1<<10)		/* End Of Frame Mask for Overlay 2 (channel 3) */
+#define LCCR5_EOFM4	(1<<11)		/* End Of Frame Mask for Overlay 2 (channel 4) */
+#define LCCR5_EOFM5	(1<<12)		/* End Of Frame Mask for cursor (channel 5) */
+#define LCCR5_EOFM6	(1<<13)		/* End Of Frame Mask for command data (channel 6) */
+
+#define LCCR5_BSM1	(1<<16)		/* Branch mask for Overlay 1 (channel 1) */
+#define LCCR5_BSM2	(1<<17)		/* Branch mask for Overlay 2 (channel 2) */
+#define LCCR5_BSM3	(1<<18)		/* Branch mask for Overlay 2 (channel 3) */
+#define LCCR5_BSM4	(1<<19)		/* Branch mask for Overlay 2 (channel 4) */
+#define LCCR5_BSM5	(1<<20)		/* Branch mask for cursor (channel 5) */
+#define LCCR5_BSM6	(1<<21)		/* Branch mask for data command	 (channel 6) */
+
+#define LCCR5_IUM1	(1<<24)		/* Input FIFO Underrun Mask for Overlay 1  */
+#define LCCR5_IUM2	(1<<25)		/* Input FIFO Underrun Mask for Overlay 2  */
+#define LCCR5_IUM3	(1<<26)		/* Input FIFO Underrun Mask for Overlay 2  */
+#define LCCR5_IUM4	(1<<27)		/* Input FIFO Underrun Mask for Overlay 2  */
+#define LCCR5_IUM5	(1<<28)		/* Input FIFO Underrun Mask for cursor */
+#define LCCR5_IUM6	(1<<29)		/* Input FIFO Underrun Mask for data command */
+
+#define OVL1C1_O1EN	(1<<31)		/* Enable bit for Overlay 1 */
+#define OVL2C1_O2EN	(1<<31)		/* Enable bit for Overlay 2 */
+#define CCR_CEN		(1<<31)		/* Enable bit for Cursor */
+
+/* Keypad controller */
+
+#define KPC		__REG(0x41500000) /* Keypad Interface Control register */
+#define KPDK		__REG(0x41500008) /* Keypad Interface Direct Key register */
+#define KPREC		__REG(0x41500010) /* Keypad Intefcace Rotary Encoder register */
+#define KPMK		__REG(0x41500018) /* Keypad Intefcace Matrix Key register */
+#define KPAS		__REG(0x41500020) /* Keypad Interface Automatic Scan register */
+#define KPASMKP0	__REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
+#define KPASMKP1	__REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
+#define KPASMKP2	__REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
+#define KPASMKP3	__REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
+#define KPKDI		__REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
+
+#define KPC_AS		(0x1 << 30)  /* Automatic Scan bit */
+#define KPC_ASACT	(0x1 << 29)  /* Automatic Scan on Activity */
+#define KPC_MI		(0x1 << 22)  /* Matrix interrupt bit */
+#define KPC_IMKP	(0x1 << 21)  /* Ignore Multiple Key Press */
+#define KPC_MS7		(0x1 << 20)  /* Matrix scan line 7 */
+#define KPC_MS6		(0x1 << 19)  /* Matrix scan line 6 */
+#define KPC_MS5		(0x1 << 18)  /* Matrix scan line 5 */
+#define KPC_MS4		(0x1 << 17)  /* Matrix scan line 4 */
+#define KPC_MS3		(0x1 << 16)  /* Matrix scan line 3 */
+#define KPC_MS2		(0x1 << 15)  /* Matrix scan line 2 */
+#define KPC_MS1		(0x1 << 14)  /* Matrix scan line 1 */
+#define KPC_MS0		(0x1 << 13)  /* Matrix scan line 0 */
+#define KPC_ME		(0x1 << 12)  /* Matrix Keypad Enable */
+#define KPC_MIE		(0x1 << 11)  /* Matrix Interrupt Enable */
+#define KPC_DK_DEB_SEL	(0x1 <<	 9)  /* Direct Key Debounce select */
+#define KPC_DI		(0x1 <<	 5)  /* Direct key interrupt bit */
+#define KPC_DEE0	(0x1 <<	 2)  /* Rotary Encoder 0 Enable */
+#define KPC_DE		(0x1 <<	 1)  /* Direct Keypad Enable */
+#define KPC_DIE		(0x1 <<	 0)  /* Direct Keypad interrupt Enable */
+
+#define KPDK_DKP	(0x1 << 31)
+#define KPDK_DK7	(0x1 <<	 7)
+#define KPDK_DK6	(0x1 <<	 6)
+#define KPDK_DK5	(0x1 <<	 5)
+#define KPDK_DK4	(0x1 <<	 4)
+#define KPDK_DK3	(0x1 <<	 3)
+#define KPDK_DK2	(0x1 <<	 2)
+#define KPDK_DK1	(0x1 <<	 1)
+#define KPDK_DK0	(0x1 <<	 0)
+
+#define KPREC_OF1	(0x1 << 31)
+#define kPREC_UF1	(0x1 << 30)
+#define KPREC_OF0	(0x1 << 15)
+#define KPREC_UF0	(0x1 << 14)
+
+#define KPMK_MKP	(0x1 << 31)
+#define KPAS_SO		(0x1 << 31)
+#define KPASMKPx_SO	(0x1 << 31)
+
+#define GPIO113_BIT	   (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
+#define PSLR	   __REG(0x40F00034)
+#define PSTR	   __REG(0x40F00038)  /* Power Manager Standby Configuration Reg */
+#define PSNR	   __REG(0x40F0003C)  /* Power Manager Sense Configuration Reg */
+#define PVCR	   __REG(0x40F00040)  /* Power Manager Voltage Change Control Reg */
+#define PKWR	   __REG(0x40F00050)  /* Power Manager KB Wake-Up Enable Reg */
+#define PKSR	   __REG(0x40F00054)  /* Power Manager KB Level-Detect Status Reg */
+#define OSMR4	    __REG(0x40A00080)  /* */
+#define OSCR4	    __REG(0x40A00040)  /* OS Timer Counter Register */
+#define OMCR4	    __REG(0x40A000C0)  /* */
+
+#endif	/* CONFIG_PXA27X */
+
+#endif	/* _PXA_REGS_H_ */
diff --git a/include/asm-arm/arch-s3c24x0/memory.h b/include/asm-arm/arch-s3c24x0/memory.h
new file mode 100755
index 0000000..333f218
--- /dev/null
+++ b/include/asm-arm/arch-s3c24x0/memory.h
@@ -0,0 +1,162 @@
+/*
+ * linux/include/asm-arm/arch-s3c2400/memory.h by gj@denx.de
+ * based on
+ * linux/include/asm-arm/arch-sa1100/memory.h
+ *
+ * Copyright (c) 1999 Nicolas Pitre <nico@visuaide.com>
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+
+/*
+ * Task size: 3GB
+ */
+#define TASK_SIZE       (0xc0000000UL)
+#define TASK_SIZE_26	(0x04000000UL)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
+
+/*
+ * Page offset: 3GB
+ */
+#define PAGE_OFFSET     (0xc0000000UL)
+
+/*
+ * Physical DRAM offset is 0x0c000000 on the S3C2400
+ */
+#define PHYS_OFFSET	(0x0c000000UL)
+
+#include <linux/config.h>
+
+
+/* Modified for S3C2400, by chc, 20010509 */
+#define RAM_IN_BANK_0  32*1024*1024
+#define RAM_IN_BANK_1  0
+#define RAM_IN_BANK_2  0
+#define RAM_IN_BANK_3  0
+
+#define MEM_SIZE  (RAM_IN_BANK_0+RAM_IN_BANK_1+RAM_IN_BANK_2+RAM_IN_BANK_3)
+
+
+/* translation macros */
+#define __virt_to_phys__is_a_macro
+#define __phys_to_virt__is_a_macro
+
+#if (RAM_IN_BANK_1 + RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0)
+
+#define __virt_to_phys(x) ( (x) - PAGE_OFFSET + 0x0c000000 )
+#define __phys_to_virt(x) ( (x) - 0x0c000000 + PAGE_OFFSET )
+
+#elif (RAM_IN_BANK_0 == RAM_IN_BANK_1) && \
+      (RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0)
+
+/* Two identical banks */
+#define __virt_to_phys(x) \
+	  ( ((x) < PAGE_OFFSET+RAM_IN_BANK_0) ? \
+	    ((x) - PAGE_OFFSET + _DRAMBnk0) : \
+	    ((x) - PAGE_OFFSET - RAM_IN_BANK_0 + _DRAMBnk1) )
+#define __phys_to_virt(x) \
+	  ( ((x)&0x07ffffff) + \
+	    (((x)&0x08000000) ? PAGE_OFFSET+RAM_IN_BANK_0 : PAGE_OFFSET) )
+#else
+
+/* It's more efficient for all other cases to use the function call */
+#undef __virt_to_phys__is_a_macro
+#undef __phys_to_virt__is_a_macro
+extern unsigned long __virt_to_phys(unsigned long vpage);
+extern unsigned long __phys_to_virt(unsigned long ppage);
+
+#endif
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ *
+ * On the SA1100, bus addresses are equivalent to physical addresses.
+ */
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+
+#ifdef CONFIG_DISCONTIGMEM
+#error "CONFIG_DISCONTIGMEM will not work on S3C2400"
+/*
+ * Because of the wide memory address space between physical RAM banks on the
+ * SA1100, it's much more convenient to use Linux's NUMA support to implement
+ * our memory map representation.  Assuming all memory nodes have equal access
+ * characteristics, we then have generic discontiguous memory support.
+ *
+ * Of course, all this isn't mandatory for SA1100 implementations with only
+ * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.
+ *
+ * The nodes are matched with the physical memory bank addresses which are
+ * incidentally the same as virtual addresses.
+ *
+ * 	node 0:  0xc0000000 - 0xc7ffffff
+ * 	node 1:  0xc8000000 - 0xcfffffff
+ * 	node 2:  0xd0000000 - 0xd7ffffff
+ * 	node 3:  0xd8000000 - 0xdfffffff
+ */
+
+#define NR_NODES	4
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+#define KVADDR_TO_NID(addr) \
+		(((unsigned long)(addr) - 0xc0000000) >> 27)
+
+/*
+ * Given a physical address, convert it to a node id.
+ */
+#define PHYS_TO_NID(addr) KVADDR_TO_NID(__phys_to_virt(addr))
+
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define ADDR_TO_MAPBASE(kaddr) \
+			NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
+
+/*
+ * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
+ * and returns the index corresponding to the appropriate page in the
+ * node's mem_map.
+ */
+#define LOCAL_MAP_NR(kvaddr) \
+	(((unsigned long)(kvaddr) & 0x07ffffff) >> PAGE_SHIFT)
+
+/*
+ * Given a kaddr, virt_to_page returns a pointer to the corresponding
+ * mem_map entry.
+ */
+#define virt_to_page(kaddr) \
+	(ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
+
+/*
+ * VALID_PAGE returns a non-zero value if given page pointer is valid.
+ * This assumes all node's mem_maps are stored within the node they refer to.
+ */
+#define VALID_PAGE(page) \
+({ unsigned int node = KVADDR_TO_NID(page); \
+   ( (node < NR_NODES) && \
+     ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size) ); \
+})
+
+#else
+
+#define PHYS_TO_NID(addr)	(0)
+
+#endif
+#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/include/asm-arm/arch-s3c44b0/hardware.h b/include/asm-arm/arch-s3c44b0/hardware.h
new file mode 100755
index 0000000..146e265
--- /dev/null
+++ b/include/asm-arm/arch-s3c44b0/hardware.h
@@ -0,0 +1,281 @@
+/********************************************************/
+/*							*/
+/* Samsung S3C44B0					*/
+/* tpu <tapu@371.net>					*/
+/*							*/
+/********************************************************/
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#define REGBASE		0x01c00000
+#define REGL(addr)	(*(volatile unsigned int *)(REGBASE+addr))
+#define REGW(addr)	(*(volatile unsigned short *)(REGBASE+addr))
+#define REGB(addr)	(*(volatile unsigned char *)(REGBASE+addr))
+
+
+/*****************************/
+/* CPU Wrapper Registers     */
+/*****************************/
+
+#define SYSCFG		REGL(0x000000)
+#define NCACHBE0	REGL(0x000004)
+#define NCACHBE1	REGL(0x000008)
+#define SBUSCON		REGL(0x040000)
+
+/************************************/
+/* Memory Controller Registers      */
+/************************************/
+
+#define BWSCON		REGL(0x080000)
+#define BANKCON0	REGL(0x080004)
+#define BANKCON1	REGL(0x080008)
+#define BANKCON2	REGL(0x08000c)
+#define BANKCON3	REGL(0x080010)
+#define BANKCON4	REGL(0x080014)
+#define BANKCON5	REGL(0x080018)
+#define BANKCON6	REGL(0x08001c)
+#define BANKCON7	REGL(0x080020)
+#define REFRESH		REGL(0x080024)
+#define BANKSIZE	REGL(0x080028)
+#define MRSRB6		REGL(0x08002c)
+#define MRSRB7		REGL(0x080030)
+
+/*********************/
+/* UART Registers    */
+/*********************/
+
+#define ULCON0		REGL(0x100000)
+#define ULCON1		REGL(0x104000)
+#define UCON0		REGL(0x100004)
+#define UCON1		REGL(0x104004)
+#define UFCON0		REGL(0x100008)
+#define UFCON1		REGL(0x104008)
+#define UMCON0		REGL(0x10000c)
+#define UMCON1		REGL(0x10400c)
+#define UTRSTAT0	REGL(0x100010)
+#define UTRSTAT1	REGL(0x104010)
+#define UERSTAT0	REGL(0x100014)
+#define UERSTAT1	REGL(0x104014)
+#define UFSTAT0		REGL(0x100018)
+#define UFSTAT1		REGL(0x104018)
+#define UMSTAT0		REGL(0x10001c)
+#define UMSTAT1		REGL(0x10401c)
+#define UTXH0		REGB(0x100020)
+#define UTXH1		REGB(0x104020)
+#define URXH0		REGB(0x100024)
+#define URXH1		REGB(0x104024)
+#define UBRDIV0		REGL(0x100028)
+#define UBRDIV1		REGL(0x104028)
+
+/*******************/
+/* SIO Registers   */
+/*******************/
+
+#define SIOCON		REGL(0x114000)
+#define SIODAT		REGL(0x114004)
+#define SBRDR		REGL(0x114008)
+#define ITVCNT		REGL(0x11400c)
+#define DCNTZ		REGL(0x114010)
+
+/********************/
+/* IIS Registers    */
+/********************/
+
+#define IISCON		REGL(0x118000)
+#define IISMOD		REGL(0x118004)
+#define IISPSR		REGL(0x118008)
+#define IISFIFCON	REGL(0x11800c)
+#define IISFIF		REGW(0x118010)
+
+/**************************/
+/* I/O Ports Registers    */
+/**************************/
+
+#define PCONA		REGL(0x120000)
+#define PDATA		REGL(0x120004)
+#define PCONB		REGL(0x120008)
+#define PDATB		REGL(0x12000c)
+#define PCONC		REGL(0x120010)
+#define PDATC		REGL(0x120014)
+#define PUPC		REGL(0x120018)
+#define PCOND		REGL(0x12001c)
+#define PDATD		REGL(0x120020)
+#define PUPD		REGL(0x120024)
+#define PCONE		REGL(0x120028)
+#define PDATE		REGL(0x12002c)
+#define PUPE		REGL(0x120030)
+#define PCONF		REGL(0x120034)
+#define PDATF		REGL(0x120038)
+#define PUPF		REGL(0x12003c)
+#define PCONG		REGL(0x120040)
+#define PDATG		REGL(0x120044)
+#define PUPG		REGL(0x120048)
+#define SPUCR		REGL(0x12004c)
+#define EXTINT		REGL(0x120050)
+#define EXTINTPND	REGL(0x120054)
+
+/*********************************/
+/* WatchDog Timers Registers     */
+/*********************************/
+
+#define WTCON		REGL(0x130000)
+#define WTDAT		REGL(0x130004)
+#define WTCNT		REGL(0x130008)
+
+/*********************************/
+/* A/D Converter Registers       */
+/*********************************/
+
+#define ADCCON		REGL(0x140000)
+#define ADCPSR		REGL(0x140004)
+#define ADCDAT		REGL(0x140008)
+
+/***************************/
+/* PWM Timer Registers     */
+/***************************/
+
+#define TCFG0		REGL(0x150000)
+#define TCFG1		REGL(0x150004)
+#define TCON		REGL(0x150008)
+#define TCNTB0		REGL(0x15000c)
+#define TCMPB0		REGL(0x150010)
+#define TCNTO0		REGL(0x150014)
+#define TCNTB1		REGL(0x150018)
+#define TCMPB1		REGL(0x15001c)
+#define TCNTO1		REGL(0x150020)
+#define TCNTB2		REGL(0x150024)
+#define TCMPB2		REGL(0x150028)
+#define TCNTO2		REGL(0x15002c)
+#define TCNTB3		REGL(0x150030)
+#define TCMPB3		REGL(0x150034)
+#define TCNTO3		REGL(0x150038)
+#define TCNTB4		REGL(0x15003c)
+#define TCMPB4		REGL(0x150040)
+#define TCNTO4		REGL(0x150044)
+#define TCNTB5		REGL(0x150048)
+#define TCNTO5		REGL(0x15004c)
+
+/*********************/
+/* IIC Registers     */
+/*********************/
+
+#define IICCON		REGL(0x160000)
+#define IICSTAT		REGL(0x160004)
+#define IICADD		REGL(0x160008)
+#define IICDS		REGL(0x16000c)
+
+/*********************/
+/* RTC Registers     */
+/*********************/
+
+#define RTCCON		REGB(0x170040)
+#define RTCALM		REGB(0x170050)
+#define ALMSEC		REGB(0x170054)
+#define ALMMIN		REGB(0x170058)
+#define ALMHOUR		REGB(0x17005c)
+#define ALMDAY		REGB(0x170060)
+#define ALMMON		REGB(0x170064)
+#define ALMYEAR		REGB(0x170068)
+#define RTCRST		REGB(0x17006c)
+#define BCDSEC		REGB(0x170070)
+#define BCDMIN		REGB(0x170074)
+#define BCDHOUR		REGB(0x170078)
+#define BCDDAY		REGB(0x17007c)
+#define BCDDATE		REGB(0x170080)
+#define BCDMON		REGB(0x170084)
+#define BCDYEAR		REGB(0x170088)
+#define TICINT		REGB(0x17008c)
+
+/*********************************/
+/* Clock & Power Registers       */
+/*********************************/
+
+#define PLLCON		REGL(0x180000)
+#define CLKCON		REGL(0x180004)
+#define CLKSLOW		REGL(0x180008)
+#define LOCKTIME	REGL(0x18000c)
+
+/**************************************/
+/* Interrupt Controller Registers     */
+/**************************************/
+
+#define INTCON		REGL(0x200000)
+#define INTPND		REGL(0x200004)
+#define INTMOD		REGL(0x200008)
+#define INTMSK		REGL(0x20000c)
+#define I_PSLV		REGL(0x200010)
+#define I_PMST		REGL(0x200014)
+#define I_CSLV		REGL(0x200018)
+#define I_CMST		REGL(0x20001c)
+#define I_ISPR		REGL(0x200020)
+#define I_ISPC		REGL(0x200024)
+#define F_ISPR		REGL(0x200038)
+#define F_ISPC		REGL(0x20003c)
+
+/********************************/
+/* LCD Controller Registers     */
+/********************************/
+
+#define LCDCON1		REGL(0x300000)
+#define LCDCON2		REGL(0x300004)
+#define LCDSADDR1	REGL(0x300008)
+#define LCDSADDR2	REGL(0x30000c)
+#define LCDSADDR3	REGL(0x300010)
+#define REDLUT		REGL(0x300014)
+#define GREENLUT	REGL(0x300018)
+#define BLUELUT		REGL(0x30001c)
+#define DP1_2		REGL(0x300020)
+#define DP4_7		REGL(0x300024)
+#define DP3_5		REGL(0x300028)
+#define DP2_3		REGL(0x30002c)
+#define DP5_7		REGL(0x300030)
+#define DP3_4		REGL(0x300034)
+#define DP4_5		REGL(0x300038)
+#define DP6_7		REGL(0x30003c)
+#define LCDCON3		REGL(0x300040)
+#define DITHMODE	REGL(0x300044)
+
+/*********************/
+/* DMA Registers     */
+/*********************/
+
+#define ZDCON0		REGL(0x280000)
+#define ZDISRC0		REGL(0x280004)
+#define ZDIDES0		REGL(0x280008)
+#define ZDICNT0		REGL(0x28000c)
+#define ZDCSRC0		REGL(0x280010)
+#define ZDCDES0		REGL(0x280014)
+#define ZDCCNT0		REGL(0x280018)
+
+#define ZDCON1		REGL(0x280020)
+#define ZDISRC1		REGL(0x280024)
+#define ZDIDES1		REGL(0x280028)
+#define ZDICNT1		REGL(0x28002c)
+#define ZDCSRC1		REGL(0x280030)
+#define ZDCDES1		REGL(0x280034)
+#define ZDCCNT1		REGL(0x280038)
+
+#define BDCON0		REGL(0x380000)
+#define BDISRC0		REGL(0x380004)
+#define BDIDES0		REGL(0x380008)
+#define BDICNT0		REGL(0x38000c)
+#define BDCSRC0		REGL(0x380010)
+#define BDCDES0		REGL(0x380014)
+#define BDCCNT0		REGL(0x380018)
+
+#define BDCON1		REGL(0x380020)
+#define BDISRC1		REGL(0x380024)
+#define BDIDES1		REGL(0x380028)
+#define BDICNT1		REGL(0x38002c)
+#define BDCSRC1		REGL(0x380030)
+#define BDCDES1		REGL(0x380034)
+#define BDCCNT1		REGL(0x380038)
+
+
+#define CLEAR_PEND_INT(n)       I_ISPC = (1<<(n))
+#define INT_ENABLE(n)		INTMSK &= ~(1<<(n))
+#define INT_DISABLE(n)		INTMSK |= (1<<(n))
+
+#define HARD_RESET_NOW()
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/include/asm-arm/arch-sa1100/bitfield.h
new file mode 100755
index 0000000..2ac5ea2
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/bitfield.h
@@ -0,0 +1,112 @@
+/*
+ *	FILE    	bitfield.h
+ *
+ *	Version 	1.1
+ *	Author  	Copyright (c) Marc A. Viredaz, 1998
+ *	        	DEC Western Research Laboratory, Palo Alto, CA
+ *	Date    	April 1998 (April 1997)
+ *	System  	Advanced RISC Machine (ARM)
+ *	Language	C or ARM Assembly
+ *	Purpose 	Definition of macros to operate on bit fields.
+ */
+
+
+#ifndef __BITFIELD_H
+#define __BITFIELD_H
+
+#ifndef __ASSEMBLY__
+#define UData(Data)	((unsigned long) (Data))
+#else
+#define UData(Data)	(Data)
+#endif
+
+
+/*
+ * MACRO: Fld
+ *
+ * Purpose
+ *    The macro "Fld" encodes a bit field, given its size and its shift value
+ *    with respect to bit 0.
+ *
+ * Note
+ *    A more intuitive way to encode bit fields would have been to use their
+ *    mask. However, extracting size and shift value information from a bit
+ *    field's mask is cumbersome and might break the assembler (255-character
+ *    line-size limit).
+ *
+ * Input
+ *    Size      	Size of the bit field, in number of bits.
+ *    Shft      	Shift value of the bit field with respect to bit 0.
+ *
+ * Output
+ *    Fld       	Encoded bit field.
+ */
+
+#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
+
+
+/*
+ * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
+ *
+ * Purpose
+ *    The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
+ *    the size, shift value, mask, aligned mask, and first bit of a
+ *    bit field.
+ *
+ * Input
+ *    Field     	Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FSize     	Size of the bit field, in number of bits.
+ *    FShft     	Shift value of the bit field with respect to bit 0.
+ *    FMsk      	Mask for the bit field.
+ *    FAlnMsk   	Mask for the bit field, aligned on bit 0.
+ *    F1stBit   	First bit of the bit field.
+ */
+
+#define FSize(Field)	((Field) >> 16)
+#define FShft(Field)	((Field) & 0x0000FFFF)
+#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
+#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
+#define F1stBit(Field)	(UData (1) << FShft (Field))
+
+
+/*
+ * MACRO: FInsrt
+ *
+ * Purpose
+ *    The macro "FInsrt" inserts a value into a bit field by shifting the
+ *    former appropriately.
+ *
+ * Input
+ *    Value     	Bit-field value.
+ *    Field     	Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FInsrt    	Bit-field value positioned appropriately.
+ */
+
+#define FInsrt(Value, Field) \
+			(UData (Value) << FShft (Field))
+
+
+/*
+ * MACRO: FExtr
+ *
+ * Purpose
+ *    The macro "FExtr" extracts the value of a bit field by masking and
+ *    shifting it appropriately.
+ *
+ * Input
+ *    Data      	Data containing the bit-field to be extracted.
+ *    Field     	Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FExtr     	Bit-field value.
+ */
+
+#define FExtr(Data, Field) \
+			((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
+
+
+#endif /* __BITFIELD_H */
diff --git a/include/asm-arm/arch-wmt/common_def.h b/include/asm-arm/arch-wmt/common_def.h
new file mode 100755
index 0000000..ad40c67
--- /dev/null
+++ b/include/asm-arm/arch-wmt/common_def.h
@@ -0,0 +1,167 @@
+/*
+ * Common definitions for WMT SoC/EVB
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+#ifndef __COMMON_DEF_H
+#define __COMMON_DEF_H
+
+/*
+ *    Common Constant define
+ */
+
+/*
+ *      PTR and VAL
+ */
+
+#define REG32_VAL(addr) (*(volatile unsigned int *)(addr))
+#define REG16_VAL(addr) (*(volatile unsigned short *)(addr))
+#define REG8_VAL(addr)  (*(volatile unsigned char *)(addr))
+
+#define REG32_PTR(addr) ((volatile unsigned int *)(addr))
+#define REG16_PTR(addr) ((volatile unsigned short *)(addr))
+#define REG8_PTR(addr)  ((volatile unsigned char *)(addr))
+
+/*
+ *      PTR and VAL for Memory
+ */
+#define MEM32_VAL(addr) (*(volatile unsigned int *)(addr))
+#define MEM16_VAL(addr) (*(volatile unsigned short *)(addr))
+#define MEM8_VAL(addr)  (*(volatile unsigned char *)(addr))
+
+#define MEM32_PTR(addr) ((volatile unsigned int *)(addr))
+#define MEM16_PTR(addr) ((volatile unsigned short *)(addr))
+#define MEM8_PTR(addr)  ((volatile unsigned char *)(addr))
+
+
+#define U32 unsigned int
+#define U16 unsigned short
+#define S32 int
+#define S16 short int
+#define U8  unsigned char
+#define S8  char
+
+
+#define BIT0                0x00000001
+#define BIT1                0x00000002
+#define BIT2                0x00000004
+#define BIT3                0x00000008
+#define BIT4                0x00000010
+#define BIT5                0x00000020
+#define BIT6                0x00000040
+#define BIT7                0x00000080
+#define BIT8                0x00000100
+#define BIT9                0x00000200
+#define BIT10               0x00000400
+#define BIT11               0x00000800
+#define BIT12               0x00001000
+#define BIT13               0x00002000
+#define BIT14               0x00004000
+#define BIT15               0x00008000
+#define BIT16               0x00010000
+#define BIT17               0x00020000
+#define BIT18               0x00040000
+#define BIT19               0x00080000
+#define BIT20               0x00100000
+#define BIT21               0x00200000
+#define BIT22               0x00400000
+#define BIT23               0x00800000
+#define BIT24               0x01000000
+#define BIT25               0x02000000
+#define BIT26               0x04000000
+#define BIT27               0x08000000
+#define BIT28               0x10000000
+#define BIT29               0x20000000
+#define BIT30               0x40000000
+#define BIT31               0x80000000
+
+
+#define SIZE_1B             0x00000001
+#define SIZE_2B             0x00000002
+#define SIZE_4B             0x00000004
+#define SIZE_8B             0x00000008
+#define SIZE_16B            0x00000010
+#define SIZE_32B            0x00000020
+#define SIZE_64B            0x00000040
+#define SIZE_128B           0x00000080
+#define SIZE_256B           0x00000100
+#define SIZE_512B           0x00000200
+#define SIZE_1KB            0x00000400
+#define SIZE_2KB            0x00000800
+#define SIZE_4KB            0x00001000
+#define SIZE_8KB            0x00002000
+#define SIZE_16KB           0x00004000
+#define SIZE_32KB           0x00008000
+#define SIZE_64KB           0x00010000
+#define SIZE_128KB          0x00020000
+#define SIZE_256KB          0x00040000
+#define SIZE_512KB          0x00080000
+#define SIZE_1MB            0x00100000
+#define SIZE_2MB            0x00200000
+#define SIZE_4MB            0x00400000
+#define SIZE_8MB            0x00800000
+#define SIZE_16MB           0x01000000
+#define SIZE_32MB           0x02000000
+#define SIZE_64MB           0x04000000
+#define SIZE_128MB          0x08000000
+#define SIZE_256MB          0x10000000
+#define SIZE_512MB          0x20000000
+#define SIZE_1GB            0x40000000
+#define SIZE_2GB            0x80000000
+
+/*
+ * Get any byte from a word
+ */
+#define GET_LE_BYTE0(x)          ((unsigned char)((x) & 0xFF))
+#define GET_LE_BYTE1(x)          ((unsigned char)((x) >> 8 & 0xFF))
+#define GET_LE_BYTE2(x)          ((unsigned char)((x) >> 16 & 0xFF))
+#define GET_LE_BYTE3(x)          ((unsigned char)((x) >> 24 & 0xFF))
+
+/*
+ *  !!! Special Note !!! for packed
+ *
+ *  use packed that will treat all member as "char" type.
+ *  Please use "packed" very carefully.
+ *
+ *  We should take care to use "packed"
+ *  Make sure that each item in the structure will have the same align.
+ *
+ */
+#ifdef __GNUC__
+    #define MAKE_PACKED(X) X __attribute__((packed))
+
+#else
+   #define MAKE_PACKED(X) __packed X
+   #define __FUNCTION__ __func__
+
+#endif
+/*
+Example for packed structure:
+------------------------------
+typedef MAKE_PACKED( struct Test1_s
+{
+    unsigned short s1 ;
+    unsigned short s2 ;
+    unsigned int   i1 ;
+    unsigned int   i2 ;
+} ) Test1_t  ;
+
+*/
+#endif /* __COMMON_DEF_H */
diff --git a/include/asm-arm/arch-wmt/hardware.h b/include/asm-arm/arch-wmt/hardware.h
new file mode 100755
index 0000000..18cacf7
--- /dev/null
+++ b/include/asm-arm/arch-wmt/hardware.h
@@ -0,0 +1,55 @@
+/*
+ * Memory Map for WMT SoC
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+#ifndef __HARDWARE_H
+#define __HARDWARE_H
+
+/*
+ * Internal APB Slaves Memory Address Map
+ */
+#define BA_MC3      0xD8000000	/* DDR/DDR2 Memory Controller Configuration */
+#define BA_DMA      0xD8001800	/* System Dma Base Address */
+#define BA_SF       0xD8002000	/* Serial Flash Memory Controller Configuration */
+#define BA_LPC      0xD8003000	/* LPC Memory Controller Configuration */
+#define BA_ENET_0   0xD8004000	/* Ethernet MAC 0 Configuration */
+#define BA_ENET_1   0xD8005000	/* Ethernet MAC 1 Configuration */
+#define BA_CIPHER   0xD8006000	/* Security Acceleration Engine Configuration */
+#define BA_UHC      0xD8007000	/* USB 2.0 Host Controller Configuration */
+#define BA_PATA     0xD8008000	/* PATA Controller Configuration */
+#define BA_NFC      0xD8009000	/* NANAD Controller Configuration */
+#define BA_SDC      0xD800A000	/* SD/SDIO/MMC Controller Configuration */
+#define BA_MSC      0xD800B000	/* Memory Stick/PRO Configuration */
+#define BA_CFC      0xD800C000	/* Compact Flash Controller Configuration */
+#define BA_SATA     0xD800D000	/* SATA Controller Configuration */
+#define BA_XOR      0xD800E000	/* XOR Engine Configuration */
+#define BA_SUPERIO  0xD8040000	/* LPC(Super IO) */
+#define BA_RTC      0xD8100000	/* Real Time Clock (RTC) */
+#define BA_GPIO     0xD8110000	/* GPIO */
+#define BA_SCC      0xD8120000	/* System Configuration Control */
+#define BA_PMC      0xD8130000	/* Power Management Control */
+#define BA_IC       0xD8140000	/* Interrupt Controller */
+#define BA_UART0    0xD8200000	/* UART0 */
+#define BA_UART1    0xD8210000	/* UART1 */
+#define BA_SPI      0xD8240000	/* SPI */
+#define BA_I2C      0xD8280000	/* I2C */
+
+#endif	/* __HARDWARE_H */
diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h
new file mode 100755
index 0000000..ba9e4b7
--- /dev/null
+++ b/include/asm-arm/atomic.h
@@ -0,0 +1,113 @@
+/*
+ *  linux/include/asm-arm/atomic.h
+ *
+ *  Copyright (c) 1996 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   13-04-1997	RMK	Made functions atomic!
+ *   07-12-1997	RMK	Upgraded for v2.1.
+ *   26-08-1998	PJB	Added #ifdef __KERNEL__
+ */
+#ifndef __ASM_ARM_ATOMIC_H
+#define __ASM_ARM_ATOMIC_H
+
+#include <linux/config.h>
+
+#ifdef CONFIG_SMP
+#error SMP not supported
+#endif
+
+typedef struct { volatile int counter; } atomic_t;
+
+#define ATOMIC_INIT(i)	{ (i) }
+
+#ifdef __KERNEL__
+#include <asm/proc/system.h>
+
+#define atomic_read(v)	((v)->counter)
+#define atomic_set(v,i)	(((v)->counter) = (i))
+
+static inline void atomic_add(int i, volatile atomic_t *v)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	v->counter += i;
+	local_irq_restore(flags);
+}
+
+static inline void atomic_sub(int i, volatile atomic_t *v)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	v->counter -= i;
+	local_irq_restore(flags);
+}
+
+static inline void atomic_inc(volatile atomic_t *v)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	v->counter += 1;
+	local_irq_restore(flags);
+}
+
+static inline void atomic_dec(volatile atomic_t *v)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	v->counter -= 1;
+	local_irq_restore(flags);
+}
+
+static inline int atomic_dec_and_test(volatile atomic_t *v)
+{
+	unsigned long flags;
+	int val;
+
+	local_irq_save(flags);
+	val = v->counter;
+	v->counter = val -= 1;
+	local_irq_restore(flags);
+
+	return val == 0;
+}
+
+static inline int atomic_add_negative(int i, volatile atomic_t *v)
+{
+	unsigned long flags;
+	int val;
+
+	local_irq_save(flags);
+	val = v->counter;
+	v->counter = val += i;
+	local_irq_restore(flags);
+
+	return val < 0;
+}
+
+static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	*addr &= ~mask;
+	local_irq_restore(flags);
+}
+
+/* Atomic operations are already serializing on ARM */
+#define smp_mb__before_atomic_dec()	barrier()
+#define smp_mb__after_atomic_dec()	barrier()
+#define smp_mb__before_atomic_inc()	barrier()
+#define smp_mb__after_atomic_inc()	barrier()
+
+#endif
+#endif
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
new file mode 100755
index 0000000..80f6766
--- /dev/null
+++ b/include/asm-arm/bitops.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_ARM_BITOPS_H
+#define __ASM_ARM_BITOPS_H
+
+#ifdef __KERNEL__
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Save the current interrupt enable state & disable IRQs
+ */
+#define local_irq_save(x)                                       \
+        ({                                                      \
+                unsigned long temp;                             \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ local_irq_save\n"     \
+"       orr     %1, %0, #128\n"                                 \
+"       msr     cpsr_c, %1"                                     \
+        : "=r" (x), "=r" (temp)                                 \
+        :                                                       \
+        : "memory");                                            \
+        })
+
+/*
+ * restore saved IRQ & FIQ state
+ */
+#define local_irq_restore(x)                                    \
+        __asm__ __volatile__(                                   \
+        "msr    cpsr_c, %0              @ local_irq_restore\n"  \
+        :                                                       \
+        : "r" (x)                                               \
+        : "memory")
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, volatile void * addr);
+
+static inline void __set_bit(int nr, volatile void *addr)
+{
+	((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7));
+}
+
+extern void clear_bit(int nr, volatile void * addr);
+
+static inline void __clear_bit(int nr, volatile void *addr)
+{
+	((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7));
+}
+
+extern void change_bit(int nr, volatile void * addr);
+
+static inline void __change_bit(int nr, volatile void *addr)
+{
+	((unsigned char *) addr)[nr >> 3] ^= (1U << (nr & 7));
+}
+
+//extern int test_and_set_bit(int nr, volatile void * addr);
+
+static inline int __test_and_set_bit(int nr, volatile void *addr)
+{
+	unsigned int mask = 1 << (nr & 7);
+	unsigned int oldval;
+
+	oldval = ((unsigned char *) addr)[nr >> 3];
+	((unsigned char *) addr)[nr >> 3] = oldval | mask;
+	return oldval & mask;
+}
+
+static inline int test_and_set_bit(int nr, volatile void * addr)
+{
+        unsigned long flags;
+        int out;
+
+        local_irq_save(flags);
+        out = __test_and_set_bit(nr, addr);
+        local_irq_restore(flags);
+
+        return out;
+}
+
+extern int test_and_clear_bit(int nr, volatile void * addr);
+
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	unsigned int mask = 1 << (nr & 7);
+	unsigned int oldval;
+
+	oldval = ((unsigned char *) addr)[nr >> 3];
+	((unsigned char *) addr)[nr >> 3] = oldval & ~mask;
+	return oldval & mask;
+}
+
+extern int test_and_change_bit(int nr, volatile void * addr);
+
+static inline int __test_and_change_bit(int nr, volatile void *addr)
+{
+	unsigned int mask = 1 << (nr & 7);
+	unsigned int oldval;
+
+	oldval = ((unsigned char *) addr)[nr >> 3];
+	((unsigned char *) addr)[nr >> 3] = oldval ^ mask;
+	return oldval & mask;
+}
+
+extern int find_first_zero_bit(void * addr, unsigned size);
+extern int find_next_zero_bit(void * addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void * addr)
+{
+    return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) { k -= 16; word <<= 16; }
+	if (word & 0x00ff0000) { k -= 8;  word <<= 8;  }
+	if (word & 0x0f000000) { k -= 4;  word <<= 4;  }
+	if (word & 0x30000000) { k -= 2;  word <<= 2;  }
+	if (word & 0x40000000) { k -= 1; }
+	return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+#define ffs(x) generic_ffs(x)
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr,addr)	test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr)		set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr)	test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr)		test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size)	find_first_zero_bit(addr,size)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ARM_BITOPS_H */
diff --git a/include/asm-arm/byteorder.h b/include/asm-arm/byteorder.h
new file mode 100755
index 0000000..c3489f1
--- /dev/null
+++ b/include/asm-arm/byteorder.h
@@ -0,0 +1,32 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+#ifndef __ASM_ARM_BYTEORDER_H
+#define __ASM_ARM_BYTEORDER_H
+
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __ARMEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h
new file mode 100755
index 0000000..00e8e92
--- /dev/null
+++ b/include/asm-arm/cache.h
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+#include <asm/system.h>
+
+/*
+ * Invalidate L2 Cache using co-proc instruction
+ */
+#if 0
+static inline void invalidate_l2_cache(void)
+{
+	unsigned int val=0;
+
+	asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
+		: : "r" (val) : "cc");
+	isb();
+}
+#endif
+
+void l2_cache_enable(void);
+void l2_cache_disable(void);
+
+/*
+ * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
+ * use that value for aligning DMA buffers unless the board config has specified
+ * an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	64
+#endif
+
+#endif /* _ASM_CACHE_H */
diff --git a/include/asm-arm/errno.h b/include/asm-arm/errno.h
new file mode 100755
index 0000000..39dc515
--- /dev/null
+++ b/include/asm-arm/errno.h
@@ -0,0 +1,155 @@
+/*
+ * U-boot - errno.h Error number defines
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _GENERIC_ERRNO_H
+#define _GENERIC_ERRNO_H
+
+#define	EPERM		1	/* Operation not permitted */
+#define	ENOENT		2	/* No such file or directory */
+#define	ESRCH		3	/* No such process */
+#define	EINTR		4	/* Interrupted system call */
+#define	EIO		5	/* I/O error */
+#define	ENXIO		6	/* No such device or address */
+#define	E2BIG		7	/* Argument list too long */
+#define	ENOEXEC		8	/* Exec format error */
+#define	EBADF		9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+#define	ENOSYS		38	/* Function not implemented */
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+
+#define	EDEADLOCK	EDEADLK
+
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale NFS file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+
+#endif
diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h
new file mode 100755
index 0000000..cb4eca2
--- /dev/null
+++ b/include/asm-arm/global_data.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct	global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	have_console;	/* serial_init() was called */
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	unsigned long	fb_base;	/* base address of frame buffer */
+#ifdef CONFIG_VFD
+	unsigned char	vfd_type;	/* display type */
+#endif
+#if 0
+	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
+	unsigned long	bus_clk;
+	unsigned long	ram_size;	/* RAM size */
+	unsigned long	reset_status;	/* reset status register at boot */
+#endif
+	void		**jt;		/* jump table */
+	char		env_buf[32];	/* buffer for getenv() before reloc. */
+
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC	0x00001		/* Code was relocated to RAM		*/
+#define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
+#define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
+/*======rockpzhang======*/
+#define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
+/*============*/
+
+
+#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/include/asm-arm/hardware.h b/include/asm-arm/hardware.h
new file mode 100755
index 0000000..1fd1a5b
--- /dev/null
+++ b/include/asm-arm/hardware.h
@@ -0,0 +1,18 @@
+/*
+ *  linux/include/asm-arm/hardware.h
+ *
+ *  Copyright (C) 1996 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Common hardware definitions
+ */
+
+#ifndef __ASM_HARDWARE_H
+#define __ASM_HARDWARE_H
+
+#include <asm/arch/hardware.h>
+
+#endif
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
new file mode 100755
index 0000000..c2b69fb
--- /dev/null
+++ b/include/asm-arm/io.h
@@ -0,0 +1,299 @@
+/*
+ *  linux/include/asm-arm/io.h
+ *
+ *  Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_ARM_IO_H
+#define __ASM_ARM_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+#include <asm/memory.h>
+#if 0	/* XXX###XXX */
+#include <asm/arch/hardware.h>
+#endif	/* XXX###XXX */
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(volatile unsigned char *)(a))
+#define __arch_getw(a)			(*(volatile unsigned short *)(a))
+#define __arch_getl(a)			(*(volatile unsigned int *)(a))
+
+#define __arch_putb(v,a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v,a)		__arch_putb(v,a)
+#define __raw_writew(v,a)		__arch_putw(v,a)
+#define __raw_writel(v,a)		__arch_putl(v,a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val,base,off)	__arch_base_putb(val,base,off)
+#define __raw_base_writew(val,base,off)	__arch_base_putw(val,base,off)
+#define __raw_base_writel(val,base,off)	__arch_base_putl(val,base,off)
+
+#define __raw_base_readb(base,off)	__arch_base_getb(base,off)
+#define __raw_base_readw(base,off)	__arch_base_getw(base,off)
+#define __raw_base_readl(base,off)	__arch_base_getl(base,off)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ */
+#if 0	/* XXX###XXX */
+#include <asm/arch/io.h>
+#endif	/* XXX###XXX */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The ARM doesn't have special IO access instructions; all IO is memory
+ * mapped.  Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v,p)			__raw_writeb(v,__io(p))
+#define outw(v,p)			__raw_writew(cpu_to_le16(v),__io(p))
+#define outl(v,p)			__raw_writel(cpu_to_le32(v),__io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p,d,l)			__raw_writesb(__io(p),d,l)
+#define outsw(p,d,l)			__raw_writesw(__io(p),d,l)
+#define outsl(p,d,l)			__raw_writesl(__io(p),d,l)
+
+#define insb(p,d,l)			__raw_readsb(__io(p),d,l)
+#define insw(p,d,l)			__raw_readsw(__io(p),d,l)
+#define insl(p,d,l)			__raw_readsl(__io(p),d,l)
+#endif
+
+#define outb_p(val,port)		outb((val),(port))
+#define outw_p(val,port)		outw((val),(port))
+#define outl_p(val,port)		outl((val),(port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port,from,len)		outsb(port,from,len)
+#define outsw_p(port,from,len)		outsw(port,from,len)
+#define outsl_p(port,from,len)		outsl(port,from,len)
+#define insb_p(port,to,len)		insb(port,to,len)
+#define insw_p(port,to,len)		insw(port,to,len)
+#define insl_p(port,to,len)		insl(port,to,len)
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.  If you want a
+ * physical address, use __ioremap instead.
+ */
+extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
+extern void __iounmap(void *addr);
+
+/*
+ * Generic ioremap support.
+ *
+ * Define:
+ *  iomem_valid_addr(off,size)
+ *  iomem_to_phys(off)
+ */
+#ifdef iomem_valid_addr
+#define __arch_ioremap(off,sz,nocache)				\
+ ({								\
+	unsigned long _off = (off), _size = (sz);		\
+	void *_ret = (void *)0;					\
+	if (iomem_valid_addr(_off, _size))			\
+		_ret = __ioremap(iomem_to_phys(_off),_size,0);	\
+	_ret;							\
+ })
+
+#define __arch_iounmap __iounmap
+#endif
+
+#define ioremap(off,sz)			__arch_ioremap((off),(sz),0)
+#define ioremap_nocache(off,sz)		__arch_ioremap((off),(sz),1)
+#define iounmap(_addr)			__arch_iounmap(_addr)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v,c)		__raw_writeb(v,__mem_pci(c))
+#define writew(v,c)		__raw_writew(cpu_to_le16(v),__mem_pci(c))
+#define writel(v,c)		__raw_writel(cpu_to_le32(v),__mem_pci(c))
+
+#define memset_io(c,v,l)		_memset_io(__mem_pci(c),(v),(l))
+#define memcpy_fromio(a,c,l)		_memcpy_fromio((a),__mem_pci(c),(l))
+#define memcpy_toio(c,a,l)		_memcpy_toio(__mem_pci(c),(a),(l))
+
+#define eth_io_copy_and_sum(s,c,l,b) \
+				eth_copy_and_sum((s),__mem_pci(c),(l),(b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)			(__readwrite_bug("readb"),0)
+#define readw(addr)			(__readwrite_bug("readw"),0)
+#define readl(addr)			(__readwrite_bug("readl"),0)
+#define writeb(v,addr)			__readwrite_bug("writeb")
+#define writew(v,addr)			__readwrite_bug("writew")
+#define writel(v,addr)			__readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(a,b,c,d)	__readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io,sig,len)	(0)
+
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val,addr)		__raw_writeb(val,__mem_isa(addr))
+#define isa_writew(val,addr)		__raw_writew(val,__mem_isa(addr))
+#define isa_writel(val,addr)		__raw_writel(val,__mem_isa(addr))
+#define isa_memset_io(a,b,c)		_memset_io(__mem_isa(a),(b),(c))
+#define isa_memcpy_fromio(a,b,c)	_memcpy_fromio((a),__mem_isa(b),(c))
+#define isa_memcpy_toio(a,b,c)		_memcpy_toio(__mem_isa((a)),(b),(c))
+
+#define isa_eth_io_copy_and_sum(a,b,c,d) \
+				eth_copy_and_sum((a),__mem_isa(b),(c),(d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+		    int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"),0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"),0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"),0)
+#define isa_writeb(val,addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val,addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val,addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a,b,c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a,b,c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a,b,c)		__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a,b,c,d) \
+				__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io,sig,len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_ARM_IO_H */
diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
new file mode 100755
index 0000000..0468e3c
--- /dev/null
+++ b/include/asm-arm/mach-types.h
@@ -0,0 +1,9427 @@
+/*
+ * This was automagically generated from arch/arm/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_ARM_MACH_TYPE_H
+#define __ASM_ARM_MACH_TYPE_H
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_EBSA110              0
+#define MACH_TYPE_RISCPC               1
+#define MACH_TYPE_NEXUSPCI             3
+#define MACH_TYPE_EBSA285              4
+#define MACH_TYPE_NETWINDER            5
+#define MACH_TYPE_CATS                 6
+#define MACH_TYPE_TBOX                 7
+#define MACH_TYPE_CO285                8
+#define MACH_TYPE_CLPS7110             9
+#define MACH_TYPE_ARCHIMEDES           10
+#define MACH_TYPE_A5K                  11
+#define MACH_TYPE_ETOILE               12
+#define MACH_TYPE_LACIE_NAS            13
+#define MACH_TYPE_CLPS7500             14
+#define MACH_TYPE_SHARK                15
+#define MACH_TYPE_BRUTUS               16
+#define MACH_TYPE_PERSONAL_SERVER      17
+#define MACH_TYPE_ITSY                 18
+#define MACH_TYPE_L7200                19
+#define MACH_TYPE_PLEB                 20
+#define MACH_TYPE_INTEGRATOR           21
+#define MACH_TYPE_H3600                22
+#define MACH_TYPE_IXP1200              23
+#define MACH_TYPE_P720T                24
+#define MACH_TYPE_ASSABET              25
+#define MACH_TYPE_VICTOR               26
+#define MACH_TYPE_LART                 27
+#define MACH_TYPE_RANGER               28
+#define MACH_TYPE_GRAPHICSCLIENT       29
+#define MACH_TYPE_XP860                30
+#define MACH_TYPE_CERF                 31
+#define MACH_TYPE_NANOENGINE           32
+#define MACH_TYPE_FPIC                 33
+#define MACH_TYPE_EXTENEX1             34
+#define MACH_TYPE_SHERMAN              35
+#define MACH_TYPE_ACCELENT_SA          36
+#define MACH_TYPE_ACCELENT_L7200       37
+#define MACH_TYPE_NETPORT              38
+#define MACH_TYPE_PANGOLIN             39
+#define MACH_TYPE_YOPY                 40
+#define MACH_TYPE_COOLIDGE             41
+#define MACH_TYPE_HUW_WEBPANEL         42
+#define MACH_TYPE_SPOTME               43
+#define MACH_TYPE_FREEBIRD             44
+#define MACH_TYPE_TI925                45
+#define MACH_TYPE_RISCSTATION          46
+#define MACH_TYPE_CAVY                 47
+#define MACH_TYPE_JORNADA720           48
+#define MACH_TYPE_OMNIMETER            49
+#define MACH_TYPE_EDB7211              50
+#define MACH_TYPE_CITYGO               51
+#define MACH_TYPE_PFS168               52
+#define MACH_TYPE_SPOT                 53
+#define MACH_TYPE_FLEXANET             54
+#define MACH_TYPE_WEBPAL               55
+#define MACH_TYPE_LINPDA               56
+#define MACH_TYPE_ANAKIN               57
+#define MACH_TYPE_MVI                  58
+#define MACH_TYPE_JUPITER              59
+#define MACH_TYPE_PSIONW               60
+#define MACH_TYPE_ALN                  61
+#define MACH_TYPE_CAMELOT              62
+#define MACH_TYPE_GDS2200              63
+#define MACH_TYPE_PSION_SERIES7        64
+#define MACH_TYPE_XFILE                65
+#define MACH_TYPE_ACCELENT_EP9312      66
+#define MACH_TYPE_IC200                67
+#define MACH_TYPE_CREDITLART           68
+#define MACH_TYPE_HTM                  69
+#define MACH_TYPE_IQ80310              70
+#define MACH_TYPE_FREEBOT              71
+#define MACH_TYPE_ENTEL                72
+#define MACH_TYPE_ENP3510              73
+#define MACH_TYPE_TRIZEPS              74
+#define MACH_TYPE_NESA                 75
+#define MACH_TYPE_VENUS                76
+#define MACH_TYPE_TARDIS               77
+#define MACH_TYPE_MERCURY              78
+#define MACH_TYPE_EMPEG                79
+#define MACH_TYPE_I80200FCC            80
+#define MACH_TYPE_ITT_CPB              81
+#define MACH_TYPE_SVC                  82
+#define MACH_TYPE_ALPHA2               84
+#define MACH_TYPE_ALPHA1               85
+#define MACH_TYPE_NETARM               86
+#define MACH_TYPE_SIMPAD               87
+#define MACH_TYPE_PDA1                 88
+#define MACH_TYPE_LUBBOCK              89
+#define MACH_TYPE_ANIKO                90
+#define MACH_TYPE_CLEP7212             91
+#define MACH_TYPE_CS89712              92
+#define MACH_TYPE_WEARARM              93
+#define MACH_TYPE_POSSIO_PX            94
+#define MACH_TYPE_SIDEARM              95
+#define MACH_TYPE_STORK                96
+#define MACH_TYPE_SHANNON              97
+#define MACH_TYPE_ACE                  98
+#define MACH_TYPE_BALLYARM             99
+#define MACH_TYPE_SIMPUTER             100
+#define MACH_TYPE_NEXTERM              101
+#define MACH_TYPE_SA1100_ELF           102
+#define MACH_TYPE_GATOR                103
+#define MACH_TYPE_GRANITE              104
+#define MACH_TYPE_CONSUS               105
+#define MACH_TYPE_AAED2000             106
+#define MACH_TYPE_CDB89712             107
+#define MACH_TYPE_GRAPHICSMASTER       108
+#define MACH_TYPE_ADSBITSY             109
+#define MACH_TYPE_PXA_IDP              110
+#define MACH_TYPE_PLCE                 111
+#define MACH_TYPE_PT_SYSTEM3           112
+#define MACH_TYPE_MEDALB               113
+#define MACH_TYPE_EAGLE                114
+#define MACH_TYPE_DSC21                115
+#define MACH_TYPE_DSC24                116
+#define MACH_TYPE_TI5472               117
+#define MACH_TYPE_AUTCPU12             118
+#define MACH_TYPE_UENGINE              119
+#define MACH_TYPE_BLUESTEM             120
+#define MACH_TYPE_XINGU8               121
+#define MACH_TYPE_BUSHSTB              122
+#define MACH_TYPE_EPSILON1             123
+#define MACH_TYPE_BALLOON              124
+#define MACH_TYPE_PUPPY                125
+#define MACH_TYPE_ELROY                126
+#define MACH_TYPE_GMS720               127
+#define MACH_TYPE_S24X                 128
+#define MACH_TYPE_JTEL_CLEP7312        129
+#define MACH_TYPE_CX821XX              130
+#define MACH_TYPE_EDB7312              131
+#define MACH_TYPE_BSA1110              132
+#define MACH_TYPE_POWERPIN             133
+#define MACH_TYPE_OPENARM              134
+#define MACH_TYPE_WHITECHAPEL          135
+#define MACH_TYPE_H3100                136
+#define MACH_TYPE_H3800                137
+#define MACH_TYPE_BLUE_V1              138
+#define MACH_TYPE_PXA_CERF             139
+#define MACH_TYPE_ARM7TEVB             140
+#define MACH_TYPE_D7400                141
+#define MACH_TYPE_PIRANHA              142
+#define MACH_TYPE_SBCAMELOT            143
+#define MACH_TYPE_KINGS                144
+#define MACH_TYPE_SMDK2400             145
+#define MACH_TYPE_COLLIE               146
+#define MACH_TYPE_IDR                  147
+#define MACH_TYPE_BADGE4               148
+#define MACH_TYPE_WEBNET               149
+#define MACH_TYPE_D7300                150
+#define MACH_TYPE_CEP                  151
+#define MACH_TYPE_FORTUNET             152
+#define MACH_TYPE_VC547X               153
+#define MACH_TYPE_FILEWALKER           154
+#define MACH_TYPE_NETGATEWAY           155
+#define MACH_TYPE_SYMBOL2800           156
+#define MACH_TYPE_SUNS                 157
+#define MACH_TYPE_FRODO                158
+#define MACH_TYPE_MACH_TYTE_MS301      159
+#define MACH_TYPE_MX1ADS               160
+#define MACH_TYPE_H7201                161
+#define MACH_TYPE_H7202                162
+#define MACH_TYPE_AMICO                163
+#define MACH_TYPE_IAM                  164
+#define MACH_TYPE_TT530                165
+#define MACH_TYPE_SAM2400              166
+#define MACH_TYPE_JORNADA56X           167
+#define MACH_TYPE_ACTIVE               168
+#define MACH_TYPE_IQ80321              169
+#define MACH_TYPE_WID                  170
+#define MACH_TYPE_SABINAL              171
+#define MACH_TYPE_IXP425_MATACUMBE     172
+#define MACH_TYPE_MINIPRINT            173
+#define MACH_TYPE_ADM510X              174
+#define MACH_TYPE_SVS200               175
+#define MACH_TYPE_ATG_TCU              176
+#define MACH_TYPE_JORNADA820           177
+#define MACH_TYPE_S3C44B0              178
+#define MACH_TYPE_MARGIS2              179
+#define MACH_TYPE_KS8695               180
+#define MACH_TYPE_BRH                  181
+#define MACH_TYPE_S3C2410              182
+#define MACH_TYPE_POSSIO_PX30          183
+#define MACH_TYPE_S3C2800              184
+#define MACH_TYPE_FLEETWOOD            185
+#define MACH_TYPE_OMAHA                186
+#define MACH_TYPE_TA7                  187
+#define MACH_TYPE_NOVA                 188
+#define MACH_TYPE_HMK                  189
+#define MACH_TYPE_KARO                 190
+#define MACH_TYPE_FESTER               191
+#define MACH_TYPE_GPI                  192
+#define MACH_TYPE_SMDK2410             193
+#define MACH_TYPE_I519                 194
+#define MACH_TYPE_NEXIO                195
+#define MACH_TYPE_BITBOX               196
+#define MACH_TYPE_G200                 197
+#define MACH_TYPE_GILL                 198
+#define MACH_TYPE_PXA_MERCURY          199
+#define MACH_TYPE_CEIVA                200
+#define MACH_TYPE_FRET                 201
+#define MACH_TYPE_EMAILPHONE           202
+#define MACH_TYPE_H3900                203
+#define MACH_TYPE_PXA1                 204
+#define MACH_TYPE_KOAN369              205
+#define MACH_TYPE_COGENT               206
+#define MACH_TYPE_ESL_SIMPUTER         207
+#define MACH_TYPE_ESL_SIMPUTER_CLR     208
+#define MACH_TYPE_ESL_SIMPUTER_BW      209
+#define MACH_TYPE_HHP_CRADLE           210
+#define MACH_TYPE_HE500                211
+#define MACH_TYPE_INHANDELF2           212
+#define MACH_TYPE_INHANDFTIP           213
+#define MACH_TYPE_DNP1110              214
+#define MACH_TYPE_PNP1110              215
+#define MACH_TYPE_CSB226               216
+#define MACH_TYPE_ARNOLD               217
+#define MACH_TYPE_VOICEBLUE            218
+#define MACH_TYPE_JZ8028               219
+#define MACH_TYPE_H5400                220
+#define MACH_TYPE_FORTE                221
+#define MACH_TYPE_ACAM                 222
+#define MACH_TYPE_ABOX                 223
+#define MACH_TYPE_ATMEL                224
+#define MACH_TYPE_SITSANG              225
+#define MACH_TYPE_CPU1110LCDNET        226
+#define MACH_TYPE_MPL_VCMA9            227
+#define MACH_TYPE_OPUS_A1              228
+#define MACH_TYPE_DAYTONA              229
+#define MACH_TYPE_KILLBEAR             230
+#define MACH_TYPE_YOHO                 231
+#define MACH_TYPE_JASPER               232
+#define MACH_TYPE_DSC25                233
+#define MACH_TYPE_OMAP_INNOVATOR       234
+#define MACH_TYPE_RAMSES               235
+#define MACH_TYPE_S28X                 236
+#define MACH_TYPE_MPORT3               237
+#define MACH_TYPE_PXA_EAGLE250         238
+#define MACH_TYPE_PDB                  239
+#define MACH_TYPE_BLUE_2G              240
+#define MACH_TYPE_BLUEARCH             241
+#define MACH_TYPE_IXDP2400             242
+#define MACH_TYPE_IXDP2800             243
+#define MACH_TYPE_EXPLORER             244
+#define MACH_TYPE_IXDP425              245
+#define MACH_TYPE_CHIMP                246
+#define MACH_TYPE_STORK_NEST           247
+#define MACH_TYPE_STORK_EGG            248
+#define MACH_TYPE_WISMO                249
+#define MACH_TYPE_EZLINX               250
+#define MACH_TYPE_AT91RM9200           251
+#define MACH_TYPE_ORION                252
+#define MACH_TYPE_NEPTUNE              253
+#define MACH_TYPE_HACKKIT              254
+#define MACH_TYPE_PXA_WINS30           255
+#define MACH_TYPE_LAVINNA              256
+#define MACH_TYPE_PXA_UENGINE          257
+#define MACH_TYPE_INNOKOM              258
+#define MACH_TYPE_BMS                  259
+#define MACH_TYPE_IXCDP1100            260
+#define MACH_TYPE_PRPMC1100            261
+#define MACH_TYPE_AT91RM9200DK         262
+#define MACH_TYPE_ARMSTICK             263
+#define MACH_TYPE_ARMONIE              264
+#define MACH_TYPE_MPORT1               265
+#define MACH_TYPE_S3C5410              266
+#define MACH_TYPE_ZCP320A              267
+#define MACH_TYPE_I_BOX                268
+#define MACH_TYPE_STLC1502             269
+#define MACH_TYPE_SIREN                270
+#define MACH_TYPE_GREENLAKE            271
+#define MACH_TYPE_ARGUS                272
+#define MACH_TYPE_COMBADGE             273
+#define MACH_TYPE_ROKEPXA              274
+#define MACH_TYPE_CINTEGRATOR          275
+#define MACH_TYPE_GUIDEA07             276
+#define MACH_TYPE_TAT257               277
+#define MACH_TYPE_IGP2425              278
+#define MACH_TYPE_BLUEGRAMMA           279
+#define MACH_TYPE_IPOD                 280
+#define MACH_TYPE_ADSBITSYX            281
+#define MACH_TYPE_TRIZEPS2             282
+#define MACH_TYPE_VIPER                283
+#define MACH_TYPE_ADSBITSYPLUS         284
+#define MACH_TYPE_ADSAGC               285
+#define MACH_TYPE_STP7312              286
+#define MACH_TYPE_NX_PHNX              287
+#define MACH_TYPE_WEP_EP250            288
+#define MACH_TYPE_INHANDELF3           289
+#define MACH_TYPE_ADI_COYOTE           290
+#define MACH_TYPE_IYONIX               291
+#define MACH_TYPE_DAMICAM_SA1110       292
+#define MACH_TYPE_MEG03                293
+#define MACH_TYPE_PXA_WHITECHAPEL      294
+#define MACH_TYPE_NWSC                 295
+#define MACH_TYPE_NWLARM               296
+#define MACH_TYPE_IXP425_MGUARD        297
+#define MACH_TYPE_PXA_NETDCU4          298
+#define MACH_TYPE_IXDP2401             299
+#define MACH_TYPE_IXDP2801             300
+#define MACH_TYPE_ZODIAC               301
+#define MACH_TYPE_ARMMODUL             302
+#define MACH_TYPE_KETOP                303
+#define MACH_TYPE_AV7200               304
+#define MACH_TYPE_ARCH_TI925           305
+#define MACH_TYPE_ACQ200               306
+#define MACH_TYPE_PT_DAFIT             307
+#define MACH_TYPE_IHBA                 308
+#define MACH_TYPE_QUINQUE              309
+#define MACH_TYPE_NIMBRAONE            310
+#define MACH_TYPE_NIMBRA29X            311
+#define MACH_TYPE_NIMBRA210            312
+#define MACH_TYPE_HHP_D95XX            313
+#define MACH_TYPE_LABARM               314
+#define MACH_TYPE_M825XX               315
+#define MACH_TYPE_M7100                316
+#define MACH_TYPE_NIPC2                317
+#define MACH_TYPE_FU7202               318
+#define MACH_TYPE_ADSAGX               319
+#define MACH_TYPE_PXA_POOH             320
+#define MACH_TYPE_BANDON               321
+#define MACH_TYPE_PCM7210              322
+#define MACH_TYPE_NMS9200              323
+#define MACH_TYPE_LOGODL               324
+#define MACH_TYPE_M7140                325
+#define MACH_TYPE_KOREBOT              326
+#define MACH_TYPE_IQ31244              327
+#define MACH_TYPE_KOAN393              328
+#define MACH_TYPE_INHANDFTIP3          329
+#define MACH_TYPE_GONZO                330
+#define MACH_TYPE_BAST                 331
+#define MACH_TYPE_SCANPASS             332
+#define MACH_TYPE_EP7312_POOH          333
+#define MACH_TYPE_TA7S                 334
+#define MACH_TYPE_TA7V                 335
+#define MACH_TYPE_ICARUS               336
+#define MACH_TYPE_H1900                337
+#define MACH_TYPE_GEMINI               338
+#define MACH_TYPE_AXIM                 339
+#define MACH_TYPE_AUDIOTRON            340
+#define MACH_TYPE_H2200                341
+#define MACH_TYPE_LOOX600              342
+#define MACH_TYPE_NIOP                 343
+#define MACH_TYPE_DM310                344
+#define MACH_TYPE_SEEDPXA_C2           345
+#define MACH_TYPE_IXP4XX_MGUARD_PCI    346
+#define MACH_TYPE_H1940                347
+#define MACH_TYPE_SCORPIO              348
+#define MACH_TYPE_VIVA                 349
+#define MACH_TYPE_PXA_XCARD            350
+#define MACH_TYPE_CSB335               351
+#define MACH_TYPE_IXRD425              352
+#define MACH_TYPE_IQ80315              353
+#define MACH_TYPE_NMP7312              354
+#define MACH_TYPE_CX861XX              355
+#define MACH_TYPE_ENP2611              356
+#define MACH_TYPE_XDA                  357
+#define MACH_TYPE_CSIR_IMS             358
+#define MACH_TYPE_IXP421_DNAEETH       359
+#define MACH_TYPE_POCKETSERV9200       360
+#define MACH_TYPE_TOTO                 361
+#define MACH_TYPE_S3C2440              362
+#define MACH_TYPE_KS8695P              363
+#define MACH_TYPE_SE4000               364
+#define MACH_TYPE_QUADRICEPS           365
+#define MACH_TYPE_BRONCO               366
+#define MACH_TYPE_ESL_SOFCOMP          368
+#define MACH_TYPE_S5C7375              369
+#define MACH_TYPE_SPEARHEAD            370
+#define MACH_TYPE_PANTERA              371
+#define MACH_TYPE_PRAYOGLITE           372
+#define MACH_TYPE_GUMSTIK              373
+#define MACH_TYPE_RCUBE                374
+#define MACH_TYPE_REA_OLV              375
+#define MACH_TYPE_PXA_IPHONE           376
+#define MACH_TYPE_S3C3410              377
+#define MACH_TYPE_ESPD_4510B           378
+#define MACH_TYPE_MP1X                 379
+#define MACH_TYPE_AT91RM9200TB         380
+#define MACH_TYPE_ADSVGX               381
+#define MACH_TYPE_OMAP_H2              382
+#define MACH_TYPE_PELEE                383
+#define MACH_TYPE_E740                 384
+#define MACH_TYPE_IQ80331              385
+#define MACH_TYPE_VERSATILE_PB         387
+#define MACH_TYPE_KEV7A400             388
+#define MACH_TYPE_LPD7A400             389
+#define MACH_TYPE_LPD7A404             390
+#define MACH_TYPE_FUJITSU_CAMELOT      391
+#define MACH_TYPE_JANUS2M              392
+#define MACH_TYPE_EMBTF                393
+#define MACH_TYPE_HPM                  394
+#define MACH_TYPE_SMDK2410TK           395
+#define MACH_TYPE_SMDK2410AJ           396
+#define MACH_TYPE_STREETRACER          397
+#define MACH_TYPE_EFRAME               398
+#define MACH_TYPE_CSB337               399
+#define MACH_TYPE_PXA_LARK             400
+#define MACH_TYPE_PNP2110              401
+#define MACH_TYPE_TCC72X               402
+#define MACH_TYPE_ALTAIR               403
+#define MACH_TYPE_KC3                  404
+#define MACH_TYPE_SINTEFTD             405
+#define MACH_TYPE_MAINSTONE            406
+#define MACH_TYPE_ADAY4X               407
+#define MACH_TYPE_LITE300              408
+#define MACH_TYPE_S5C7376              409
+#define MACH_TYPE_MT02                 410
+#define MACH_TYPE_MPORT3S              411
+#define MACH_TYPE_RA_ALPHA             412
+#define MACH_TYPE_XCEP                 413
+#define MACH_TYPE_ARCOM_MERCURY        414
+#define MACH_TYPE_STARGATE             415
+#define MACH_TYPE_ARMADILLOJ           416
+#define MACH_TYPE_ELROY_JACK           417
+#define MACH_TYPE_BACKEND              418
+#define MACH_TYPE_S5LINBOX             419
+#define MACH_TYPE_NOMADIK              420
+#define MACH_TYPE_IA_CPU_9200          421
+#define MACH_TYPE_AT91_BJA1            422
+#define MACH_TYPE_CORGI                423
+#define MACH_TYPE_POODLE               424
+#define MACH_TYPE_TEN                  425
+#define MACH_TYPE_ROVERP5P             426
+#define MACH_TYPE_SC2700               427
+#define MACH_TYPE_EX_EAGLE             428
+#define MACH_TYPE_NX_PXA12             429
+#define MACH_TYPE_NX_PXA5              430
+#define MACH_TYPE_BLACKBOARD2          431
+#define MACH_TYPE_I819                 432
+#define MACH_TYPE_IXMB995E             433
+#define MACH_TYPE_SKYRIDER             434
+#define MACH_TYPE_SKYHAWK              435
+#define MACH_TYPE_ENTERPRISE           436
+#define MACH_TYPE_DEP2410              437
+#define MACH_TYPE_ARMCORE              438
+#define MACH_TYPE_HOBBIT               439
+#define MACH_TYPE_H7210                440
+#define MACH_TYPE_PXA_NETDCU5          441
+#define MACH_TYPE_ACC                  442
+#define MACH_TYPE_ESL_SARVA            443
+#define MACH_TYPE_XM250                444
+#define MACH_TYPE_T6TC1XB              445
+#define MACH_TYPE_ESS710               446
+#define MACH_TYPE_MX3ADS               447
+#define MACH_TYPE_HIMALAYA             448
+#define MACH_TYPE_BOLFENK              449
+#define MACH_TYPE_AT91RM9200KR         450
+#define MACH_TYPE_EDB9312              451
+#define MACH_TYPE_OMAP_GENERIC         452
+#define MACH_TYPE_AXIMX3               453
+#define MACH_TYPE_EB67XDIP             454
+#define MACH_TYPE_WEBTXS               455
+#define MACH_TYPE_HAWK                 456
+#define MACH_TYPE_CCAT91SBC001         457
+#define MACH_TYPE_EXPRESSO             458
+#define MACH_TYPE_H4000                459
+#define MACH_TYPE_DINO                 460
+#define MACH_TYPE_ML675K               461
+#define MACH_TYPE_EDB9301              462
+#define MACH_TYPE_EDB9315              463
+#define MACH_TYPE_RECIVA_TT            464
+#define MACH_TYPE_CSTCB01              465
+#define MACH_TYPE_CSTCB1               466
+#define MACH_TYPE_SHADWELL             467
+#define MACH_TYPE_GOEPEL263            468
+#define MACH_TYPE_ACQ100               469
+#define MACH_TYPE_MX1FS2               470
+#define MACH_TYPE_HIPTOP_G1            471
+#define MACH_TYPE_SPARKY               472
+#define MACH_TYPE_NS9750               473
+#define MACH_TYPE_PHOENIX              474
+#define MACH_TYPE_VR1000               475
+#define MACH_TYPE_DEISTERPXA           476
+#define MACH_TYPE_BCM1160              477
+#define MACH_TYPE_PCM022               478
+#define MACH_TYPE_ADSGCX               479
+#define MACH_TYPE_DREADNAUGHT          480
+#define MACH_TYPE_DM320                481
+#define MACH_TYPE_MARKOV               482
+#define MACH_TYPE_COS7A400             483
+#define MACH_TYPE_MILANO               484
+#define MACH_TYPE_UE9328               485
+#define MACH_TYPE_UEX255               486
+#define MACH_TYPE_UE2410               487
+#define MACH_TYPE_A620                 488
+#define MACH_TYPE_OCELOT               489
+#define MACH_TYPE_CHEETAH              490
+#define MACH_TYPE_OMAP_PERSEUS2        491
+#define MACH_TYPE_ZVUE                 492
+#define MACH_TYPE_ROVERP1              493
+#define MACH_TYPE_ASIDIAL2             494
+#define MACH_TYPE_S3C24A0              495
+#define MACH_TYPE_E800                 496
+#define MACH_TYPE_E750                 497
+#define MACH_TYPE_S3C5500              498
+#define MACH_TYPE_SMDK5500             499
+#define MACH_TYPE_SIGNALSYNC           500
+#define MACH_TYPE_NBC                  501
+#define MACH_TYPE_KODIAK               502
+#define MACH_TYPE_NETBOOKPRO           503
+#define MACH_TYPE_HW90200              504
+#define MACH_TYPE_CONDOR               505
+#define MACH_TYPE_CUP                  506
+#define MACH_TYPE_KITE                 507
+#define MACH_TYPE_SCB9328              508
+#define MACH_TYPE_OMAP_H3              509
+#define MACH_TYPE_OMAP_H4              510
+#define MACH_TYPE_N10                  511
+#define MACH_TYPE_MONTAJADE            512
+#define MACH_TYPE_SG560                513
+#define MACH_TYPE_DP1000               514
+#define MACH_TYPE_OMAP_OSK             515
+#define MACH_TYPE_RG100V3              516
+#define MACH_TYPE_MX2ADS               517
+#define MACH_TYPE_PXA_KILO             518
+#define MACH_TYPE_IXP4XX_EAGLE         519
+#define MACH_TYPE_TOSA                 520
+#define MACH_TYPE_MB2520F              521
+#define MACH_TYPE_EMC1000              522
+#define MACH_TYPE_TIDSC25              523
+#define MACH_TYPE_AKCPMXL              524
+#define MACH_TYPE_AV3XX                525
+#define MACH_TYPE_AVILA                526
+#define MACH_TYPE_PXA_MPM10            527
+#define MACH_TYPE_PXA_KYANITE          528
+#define MACH_TYPE_SGOLD                529
+#define MACH_TYPE_OSCAR                530
+#define MACH_TYPE_EPXA4USB2            531
+#define MACH_TYPE_XSENGINE             532
+#define MACH_TYPE_IP600                533
+#define MACH_TYPE_MCAN2                534
+#define MACH_TYPE_DDI_BLUERIDGE        535
+#define MACH_TYPE_SKYMINDER            536
+#define MACH_TYPE_LPD79520             537
+#define MACH_TYPE_EDB9302              538
+#define MACH_TYPE_HW90340              539
+#define MACH_TYPE_CIP_BOX              540
+#define MACH_TYPE_IVPN                 541
+#define MACH_TYPE_RSOC2                542
+#define MACH_TYPE_HUSKY                543
+#define MACH_TYPE_BOXER                544
+#define MACH_TYPE_SHEPHERD             545
+#define MACH_TYPE_AML42800AA           546
+#define MACH_TYPE_MACH_TYPE_ML674001   547
+#define MACH_TYPE_LPC2294              548
+#define MACH_TYPE_SWITCHGRASS          549
+#define MACH_TYPE_ENS_CMU              550
+#define MACH_TYPE_MM6_SDB              551
+#define MACH_TYPE_SATURN               552
+#define MACH_TYPE_ARGONPLUSEVB         553
+#define MACH_TYPE_SCMA11EVB            554
+#define MACH_TYPE_SMDK2800             555
+#define MACH_TYPE_MTWILSON             556
+#define MACH_TYPE_ZITI                 557
+#define MACH_TYPE_GRANDFATHER          558
+#define MACH_TYPE_TENGINE              559
+#define MACH_TYPE_S3C2460              560
+#define MACH_TYPE_PDM                  561
+#define MACH_TYPE_H4700                562
+#define MACH_TYPE_H6300                563
+#define MACH_TYPE_RZ1700               564
+#define MACH_TYPE_A716                 565
+#define MACH_TYPE_ESTK2440A            566
+#define MACH_TYPE_ATWIXP425            567
+#define MACH_TYPE_CSB336               568
+#define MACH_TYPE_RIRM2                569
+#define MACH_TYPE_CX23518              570
+#define MACH_TYPE_CX2351X              571
+#define MACH_TYPE_COMPUTIME            572
+#define MACH_TYPE_IZARUS               573
+#define MACH_TYPE_RTS                  574
+#define MACH_TYPE_SE5100               575
+#define MACH_TYPE_S3C2510              576
+#define MACH_TYPE_CSB437TL             577
+#define MACH_TYPE_SLAUSON              578
+#define MACH_TYPE_PEARLRIVER           579
+#define MACH_TYPE_TDC_P210             580
+#define MACH_TYPE_SG580                581
+#define MACH_TYPE_WRSBCARM7            582
+#define MACH_TYPE_IPD                  583
+#define MACH_TYPE_PXA_DNP2110          584
+#define MACH_TYPE_XAENIAX              585
+#define MACH_TYPE_SOMN4250             586
+#define MACH_TYPE_PLEB2                587
+#define MACH_TYPE_CORNWALLIS           588
+#define MACH_TYPE_GURNEY_DRV           589
+#define MACH_TYPE_CHAFFEE              590
+#define MACH_TYPE_RMS101               591
+#define MACH_TYPE_RX3715               592
+#define MACH_TYPE_SWIFT                593
+#define MACH_TYPE_ROVERP7              594
+#define MACH_TYPE_PR818S               595
+#define MACH_TYPE_TRXPRO               596
+#define MACH_TYPE_NSLU2                597
+#define MACH_TYPE_E400                 598
+#define MACH_TYPE_TRAB                 599
+#define MACH_TYPE_CMC_PU2              600
+#define MACH_TYPE_FULCRUM              601
+#define MACH_TYPE_NETGATE42X           602
+#define MACH_TYPE_STR710               603
+#define MACH_TYPE_IXDPG425             604
+#define MACH_TYPE_TOMTOMGO             605
+#define MACH_TYPE_VERSATILE_AB         606
+#define MACH_TYPE_EDB9307              607
+#define MACH_TYPE_SG565                608
+#define MACH_TYPE_LPD79524             609
+#define MACH_TYPE_LPD79525             610
+#define MACH_TYPE_RMS100               611
+#define MACH_TYPE_KB9200               612
+#define MACH_TYPE_SX1                  613
+#define MACH_TYPE_HMS39C7092           614
+#define MACH_TYPE_ARMADILLO            615
+#define MACH_TYPE_IPCU                 616
+#define MACH_TYPE_LOOX720              617
+#define MACH_TYPE_IXDP465              618
+#define MACH_TYPE_IXDP2351             619
+#define MACH_TYPE_ADSVIX               620
+#define MACH_TYPE_DM270                621
+#define MACH_TYPE_SOCLTPLUS            622
+#define MACH_TYPE_ECIA                 623
+#define MACH_TYPE_CM4008               624
+#define MACH_TYPE_P2001                625
+#define MACH_TYPE_TWISTER              626
+#define MACH_TYPE_MUDSHARK             627
+#define MACH_TYPE_HB2                  628
+#define MACH_TYPE_IQ80332              629
+#define MACH_TYPE_SENDT                630
+#define MACH_TYPE_MX2JAZZ              631
+#define MACH_TYPE_MULTIIO              632
+#define MACH_TYPE_HRDISPLAY            633
+#define MACH_TYPE_SCMA11BB             634
+#define MACH_TYPE_TRIZEPS3             635
+#define MACH_TYPE_ZEFEERDZA            636
+#define MACH_TYPE_ZEFEERDZB            637
+#define MACH_TYPE_ZEFEERDZG            638
+#define MACH_TYPE_ZEFEERDZN            639
+#define MACH_TYPE_ZEFEERDZQ            640
+#define MACH_TYPE_GTWX5715             641
+#define MACH_TYPE_ASTRO_JACK           643
+#define MACH_TYPE_TIP03                644
+#define MACH_TYPE_A9200EC              645
+#define MACH_TYPE_PNX0105              646
+#define MACH_TYPE_ADCPOECPU            647
+#define MACH_TYPE_CSB637               648
+#define MACH_TYPE_ML69Q6203            649
+#define MACH_TYPE_MB9200               650
+#define MACH_TYPE_KULUN                651
+#define MACH_TYPE_SNAPPER              652
+#define MACH_TYPE_OPTIMA               653
+#define MACH_TYPE_DLHSBC               654
+#define MACH_TYPE_X30                  655
+#define MACH_TYPE_N30                  656
+#define MACH_TYPE_MANGA_KS8695         657
+#define MACH_TYPE_AJAX                 658
+#define MACH_TYPE_NEC_MP900            659
+#define MACH_TYPE_VVTK1000             661
+#define MACH_TYPE_KAFA                 662
+#define MACH_TYPE_VVTK3000             663
+#define MACH_TYPE_PIMX1                664
+#define MACH_TYPE_OLLIE                665
+#define MACH_TYPE_SKYMAX               666
+#define MACH_TYPE_JAZZ                 667
+#define MACH_TYPE_TEL_T3               668
+#define MACH_TYPE_AISINO_FCR255        669
+#define MACH_TYPE_BTWEB                670
+#define MACH_TYPE_DBG_LH79520          671
+#define MACH_TYPE_CM41XX               672
+#define MACH_TYPE_TS72XX               673
+#define MACH_TYPE_NGGPXA               674
+#define MACH_TYPE_CSB535               675
+#define MACH_TYPE_CSB536               676
+#define MACH_TYPE_PXA_TRAKPOD          677
+#define MACH_TYPE_PRAXIS               678
+#define MACH_TYPE_LH75411              679
+#define MACH_TYPE_OTOM                 680
+#define MACH_TYPE_NEXCODER_2440        681
+#define MACH_TYPE_LOOX410              682
+#define MACH_TYPE_WESTLAKE             683
+#define MACH_TYPE_NSB                  684
+#define MACH_TYPE_ESL_SARVA_STN        685
+#define MACH_TYPE_ESL_SARVA_TFT        686
+#define MACH_TYPE_ESL_SARVA_IAD        687
+#define MACH_TYPE_ESL_SARVA_ACC        688
+#define MACH_TYPE_TYPHOON              689
+#define MACH_TYPE_CNAV                 690
+#define MACH_TYPE_A730                 691
+#define MACH_TYPE_NETSTAR              692
+#define MACH_TYPE_PHASEFALE_SUPERCON   693
+#define MACH_TYPE_SHIVA1100            694
+#define MACH_TYPE_ETEXSC               695
+#define MACH_TYPE_IXDPG465             696
+#define MACH_TYPE_A9M2410              697
+#define MACH_TYPE_A9M2440              698
+#define MACH_TYPE_A9M9750              699
+#define MACH_TYPE_A9M9360              700
+#define MACH_TYPE_UNC90                701
+#define MACH_TYPE_ECO920               702
+#define MACH_TYPE_SATVIEW              703
+#define MACH_TYPE_ROADRUNNER           704
+#define MACH_TYPE_AT91RM9200EK         705
+#define MACH_TYPE_GP32                 706
+#define MACH_TYPE_GEM                  707
+#define MACH_TYPE_I858                 708
+#define MACH_TYPE_HX2750               709
+#define MACH_TYPE_ZEUSEVB              710
+#define MACH_TYPE_P700                 711
+#define MACH_TYPE_CPE                  712
+#define MACH_TYPE_SPITZ                713
+#define MACH_TYPE_NIMBRA340            714
+#define MACH_TYPE_LPC22XX              715
+#define MACH_TYPE_COMET3               716
+#define MACH_TYPE_COMET4               717
+#define MACH_TYPE_CSB625               718
+#define MACH_TYPE_FORTUNET2            719
+#define MACH_TYPE_S5H2200              720
+#define MACH_TYPE_OPTORM920            721
+#define MACH_TYPE_ADSBITSYXB           722
+#define MACH_TYPE_ADSSPHERE            723
+#define MACH_TYPE_ADSPORTAL            724
+#define MACH_TYPE_LN2410SBC            725
+#define MACH_TYPE_CB3RUFC              726
+#define MACH_TYPE_MP2USB               727
+#define MACH_TYPE_WMT                  728
+
+#ifdef CONFIG_ARCH_EBSA110
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EBSA110
+# endif
+# define machine_is_ebsa110()	(machine_arch_type == MACH_TYPE_EBSA110)
+#else
+# define machine_is_ebsa110()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_RPC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RISCPC
+# endif
+# define machine_is_riscpc()	(machine_arch_type == MACH_TYPE_RISCPC)
+#else
+# define machine_is_riscpc()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_NEXUSPCI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEXUSPCI
+# endif
+# define machine_is_nexuspci()	(machine_arch_type == MACH_TYPE_NEXUSPCI)
+#else
+# define machine_is_nexuspci()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_EBSA285
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EBSA285
+# endif
+# define machine_is_ebsa285()	(machine_arch_type == MACH_TYPE_EBSA285)
+#else
+# define machine_is_ebsa285()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_NETWINDER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETWINDER
+# endif
+# define machine_is_netwinder()	(machine_arch_type == MACH_TYPE_NETWINDER)
+#else
+# define machine_is_netwinder()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CATS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CATS
+# endif
+# define machine_is_cats()	(machine_arch_type == MACH_TYPE_CATS)
+#else
+# define machine_is_cats()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_TBOX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TBOX
+# endif
+# define machine_is_tbox()	(machine_arch_type == MACH_TYPE_TBOX)
+#else
+# define machine_is_tbox()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CO285
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CO285
+# endif
+# define machine_is_co285()	(machine_arch_type == MACH_TYPE_CO285)
+#else
+# define machine_is_co285()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CLPS7110
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CLPS7110
+# endif
+# define machine_is_clps7110()	(machine_arch_type == MACH_TYPE_CLPS7110)
+#else
+# define machine_is_clps7110()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ARC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARCHIMEDES
+# endif
+# define machine_is_archimedes()	(machine_arch_type == MACH_TYPE_ARCHIMEDES)
+#else
+# define machine_is_archimedes()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_A5K
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_A5K
+# endif
+# define machine_is_a5k()	(machine_arch_type == MACH_TYPE_A5K)
+#else
+# define machine_is_a5k()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ETOILE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ETOILE
+# endif
+# define machine_is_etoile()	(machine_arch_type == MACH_TYPE_ETOILE)
+#else
+# define machine_is_etoile()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_LACIE_NAS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LACIE_NAS
+# endif
+# define machine_is_lacie_nas()	(machine_arch_type == MACH_TYPE_LACIE_NAS)
+#else
+# define machine_is_lacie_nas()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CLPS7500
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CLPS7500
+# endif
+# define machine_is_clps7500()	(machine_arch_type == MACH_TYPE_CLPS7500)
+#else
+# define machine_is_clps7500()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SHARK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHARK
+# endif
+# define machine_is_shark()	(machine_arch_type == MACH_TYPE_SHARK)
+#else
+# define machine_is_shark()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_BRUTUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BRUTUS
+# endif
+# define machine_is_brutus()	(machine_arch_type == MACH_TYPE_BRUTUS)
+#else
+# define machine_is_brutus()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PERSONAL_SERVER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PERSONAL_SERVER
+# endif
+# define machine_is_personal_server()	(machine_arch_type == MACH_TYPE_PERSONAL_SERVER)
+#else
+# define machine_is_personal_server()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ITSY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ITSY
+# endif
+# define machine_is_itsy()	(machine_arch_type == MACH_TYPE_ITSY)
+#else
+# define machine_is_itsy()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_L7200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_L7200
+# endif
+# define machine_is_l7200()	(machine_arch_type == MACH_TYPE_L7200)
+#else
+# define machine_is_l7200()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_PLEB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PLEB
+# endif
+# define machine_is_pleb()	(machine_arch_type == MACH_TYPE_PLEB)
+#else
+# define machine_is_pleb()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_INTEGRATOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INTEGRATOR
+# endif
+# define machine_is_integrator()	(machine_arch_type == MACH_TYPE_INTEGRATOR)
+#else
+# define machine_is_integrator()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_H3600
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H3600
+# endif
+# define machine_is_h3600()	(machine_arch_type == MACH_TYPE_H3600)
+#else
+# define machine_is_h3600()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXP1200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXP1200
+# endif
+# define machine_is_ixp1200()	(machine_arch_type == MACH_TYPE_IXP1200)
+#else
+# define machine_is_ixp1200()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_P720T
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_P720T
+# endif
+# define machine_is_p720t()	(machine_arch_type == MACH_TYPE_P720T)
+#else
+# define machine_is_p720t()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ASSABET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ASSABET
+# endif
+# define machine_is_assabet()	(machine_arch_type == MACH_TYPE_ASSABET)
+#else
+# define machine_is_assabet()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_VICTOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VICTOR
+# endif
+# define machine_is_victor()	(machine_arch_type == MACH_TYPE_VICTOR)
+#else
+# define machine_is_victor()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_LART
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LART
+# endif
+# define machine_is_lart()	(machine_arch_type == MACH_TYPE_LART)
+#else
+# define machine_is_lart()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_RANGER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RANGER
+# endif
+# define machine_is_ranger()	(machine_arch_type == MACH_TYPE_RANGER)
+#else
+# define machine_is_ranger()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_GRAPHICSCLIENT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GRAPHICSCLIENT
+# endif
+# define machine_is_graphicsclient()	(machine_arch_type == MACH_TYPE_GRAPHICSCLIENT)
+#else
+# define machine_is_graphicsclient()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_XP860
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XP860
+# endif
+# define machine_is_xp860()	(machine_arch_type == MACH_TYPE_XP860)
+#else
+# define machine_is_xp860()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_CERF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CERF
+# endif
+# define machine_is_cerf()	(machine_arch_type == MACH_TYPE_CERF)
+#else
+# define machine_is_cerf()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_NANOENGINE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NANOENGINE
+# endif
+# define machine_is_nanoengine()	(machine_arch_type == MACH_TYPE_NANOENGINE)
+#else
+# define machine_is_nanoengine()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_FPIC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FPIC
+# endif
+# define machine_is_fpic()	(machine_arch_type == MACH_TYPE_FPIC)
+#else
+# define machine_is_fpic()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_EXTENEX1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EXTENEX1
+# endif
+# define machine_is_extenex1()	(machine_arch_type == MACH_TYPE_EXTENEX1)
+#else
+# define machine_is_extenex1()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_SHERMAN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHERMAN
+# endif
+# define machine_is_sherman()	(machine_arch_type == MACH_TYPE_SHERMAN)
+#else
+# define machine_is_sherman()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ACCELENT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACCELENT_SA
+# endif
+# define machine_is_accelent_sa()	(machine_arch_type == MACH_TYPE_ACCELENT_SA)
+#else
+# define machine_is_accelent_sa()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_L7200_ACCELENT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACCELENT_L7200
+# endif
+# define machine_is_accelent_l7200()	(machine_arch_type == MACH_TYPE_ACCELENT_L7200)
+#else
+# define machine_is_accelent_l7200()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_NETPORT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETPORT
+# endif
+# define machine_is_netport()	(machine_arch_type == MACH_TYPE_NETPORT)
+#else
+# define machine_is_netport()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_PANGOLIN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PANGOLIN
+# endif
+# define machine_is_pangolin()	(machine_arch_type == MACH_TYPE_PANGOLIN)
+#else
+# define machine_is_pangolin()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_YOPY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_YOPY
+# endif
+# define machine_is_yopy()	(machine_arch_type == MACH_TYPE_YOPY)
+#else
+# define machine_is_yopy()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_COOLIDGE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COOLIDGE
+# endif
+# define machine_is_coolidge()	(machine_arch_type == MACH_TYPE_COOLIDGE)
+#else
+# define machine_is_coolidge()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_HUW_WEBPANEL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HUW_WEBPANEL
+# endif
+# define machine_is_huw_webpanel()	(machine_arch_type == MACH_TYPE_HUW_WEBPANEL)
+#else
+# define machine_is_huw_webpanel()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SPOTME
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPOTME
+# endif
+# define machine_is_spotme()	(machine_arch_type == MACH_TYPE_SPOTME)
+#else
+# define machine_is_spotme()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_FREEBIRD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FREEBIRD
+# endif
+# define machine_is_freebird()	(machine_arch_type == MACH_TYPE_FREEBIRD)
+#else
+# define machine_is_freebird()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_TI925
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TI925
+# endif
+# define machine_is_ti925()	(machine_arch_type == MACH_TYPE_TI925)
+#else
+# define machine_is_ti925()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_RISCSTATION
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RISCSTATION
+# endif
+# define machine_is_riscstation()	(machine_arch_type == MACH_TYPE_RISCSTATION)
+#else
+# define machine_is_riscstation()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_CAVY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CAVY
+# endif
+# define machine_is_cavy()	(machine_arch_type == MACH_TYPE_CAVY)
+#else
+# define machine_is_cavy()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_JORNADA720
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JORNADA720
+# endif
+# define machine_is_jornada720()	(machine_arch_type == MACH_TYPE_JORNADA720)
+#else
+# define machine_is_jornada720()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_OMNIMETER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMNIMETER
+# endif
+# define machine_is_omnimeter()	(machine_arch_type == MACH_TYPE_OMNIMETER)
+#else
+# define machine_is_omnimeter()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_EDB7211
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB7211
+# endif
+# define machine_is_edb7211()	(machine_arch_type == MACH_TYPE_EDB7211)
+#else
+# define machine_is_edb7211()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_CITYGO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CITYGO
+# endif
+# define machine_is_citygo()	(machine_arch_type == MACH_TYPE_CITYGO)
+#else
+# define machine_is_citygo()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_PFS168
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PFS168
+# endif
+# define machine_is_pfs168()	(machine_arch_type == MACH_TYPE_PFS168)
+#else
+# define machine_is_pfs168()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_SPOT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPOT
+# endif
+# define machine_is_spot()	(machine_arch_type == MACH_TYPE_SPOT)
+#else
+# define machine_is_spot()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_FLEXANET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FLEXANET
+# endif
+# define machine_is_flexanet()	(machine_arch_type == MACH_TYPE_FLEXANET)
+#else
+# define machine_is_flexanet()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_WEBPAL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WEBPAL
+# endif
+# define machine_is_webpal()	(machine_arch_type == MACH_TYPE_WEBPAL)
+#else
+# define machine_is_webpal()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_LINPDA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LINPDA
+# endif
+# define machine_is_linpda()	(machine_arch_type == MACH_TYPE_LINPDA)
+#else
+# define machine_is_linpda()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ANAKIN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ANAKIN
+# endif
+# define machine_is_anakin()	(machine_arch_type == MACH_TYPE_ANAKIN)
+#else
+# define machine_is_anakin()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_MVI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MVI
+# endif
+# define machine_is_mvi()	(machine_arch_type == MACH_TYPE_MVI)
+#else
+# define machine_is_mvi()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_JUPITER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JUPITER
+# endif
+# define machine_is_jupiter()	(machine_arch_type == MACH_TYPE_JUPITER)
+#else
+# define machine_is_jupiter()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PSIONW
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PSIONW
+# endif
+# define machine_is_psionw()	(machine_arch_type == MACH_TYPE_PSIONW)
+#else
+# define machine_is_psionw()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ALN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ALN
+# endif
+# define machine_is_aln()	(machine_arch_type == MACH_TYPE_ALN)
+#else
+# define machine_is_aln()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CAMELOT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CAMELOT
+# endif
+# define machine_is_epxa()	(machine_arch_type == MACH_TYPE_CAMELOT)
+#else
+# define machine_is_epxa()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_GDS2200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GDS2200
+# endif
+# define machine_is_gds2200()	(machine_arch_type == MACH_TYPE_GDS2200)
+#else
+# define machine_is_gds2200()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_PSION_SERIES7
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PSION_SERIES7
+# endif
+# define machine_is_psion_series7()	(machine_arch_type == MACH_TYPE_PSION_SERIES7)
+#else
+# define machine_is_psion_series7()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_XFILE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XFILE
+# endif
+# define machine_is_xfile()	(machine_arch_type == MACH_TYPE_XFILE)
+#else
+# define machine_is_xfile()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ACCELENT_EP9312
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACCELENT_EP9312
+# endif
+# define machine_is_accelent_ep9312()	(machine_arch_type == MACH_TYPE_ACCELENT_EP9312)
+#else
+# define machine_is_accelent_ep9312()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IC200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IC200
+# endif
+# define machine_is_ic200()	(machine_arch_type == MACH_TYPE_IC200)
+#else
+# define machine_is_ic200()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_CREDITLART
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CREDITLART
+# endif
+# define machine_is_creditlart()	(machine_arch_type == MACH_TYPE_CREDITLART)
+#else
+# define machine_is_creditlart()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_HTM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTM
+# endif
+# define machine_is_htm()	(machine_arch_type == MACH_TYPE_HTM)
+#else
+# define machine_is_htm()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IQ80310
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IQ80310
+# endif
+# define machine_is_iq80310()	(machine_arch_type == MACH_TYPE_IQ80310)
+#else
+# define machine_is_iq80310()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_FREEBOT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FREEBOT
+# endif
+# define machine_is_freebot()	(machine_arch_type == MACH_TYPE_FREEBOT)
+#else
+# define machine_is_freebot()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ENTEL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ENTEL
+# endif
+# define machine_is_entel()	(machine_arch_type == MACH_TYPE_ENTEL)
+#else
+# define machine_is_entel()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ENP3510
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ENP3510
+# endif
+# define machine_is_enp3510()	(machine_arch_type == MACH_TYPE_ENP3510)
+#else
+# define machine_is_enp3510()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_TRIZEPS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TRIZEPS
+# endif
+# define machine_is_trizeps()	(machine_arch_type == MACH_TYPE_TRIZEPS)
+#else
+# define machine_is_trizeps()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_NESA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NESA
+# endif
+# define machine_is_nesa()	(machine_arch_type == MACH_TYPE_NESA)
+#else
+# define machine_is_nesa()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_VENUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VENUS
+# endif
+# define machine_is_venus()	(machine_arch_type == MACH_TYPE_VENUS)
+#else
+# define machine_is_venus()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_TARDIS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TARDIS
+# endif
+# define machine_is_tardis()	(machine_arch_type == MACH_TYPE_TARDIS)
+#else
+# define machine_is_tardis()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_MERCURY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MERCURY
+# endif
+# define machine_is_mercury()	(machine_arch_type == MACH_TYPE_MERCURY)
+#else
+# define machine_is_mercury()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_EMPEG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EMPEG
+# endif
+# define machine_is_empeg()	(machine_arch_type == MACH_TYPE_EMPEG)
+#else
+# define machine_is_empeg()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_I80200FCC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_I80200FCC
+# endif
+# define machine_is_adi_evb()	(machine_arch_type == MACH_TYPE_I80200FCC)
+#else
+# define machine_is_adi_evb()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ITT_CPB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ITT_CPB
+# endif
+# define machine_is_itt_cpb()	(machine_arch_type == MACH_TYPE_ITT_CPB)
+#else
+# define machine_is_itt_cpb()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_SVC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SVC
+# endif
+# define machine_is_svc()	(machine_arch_type == MACH_TYPE_SVC)
+#else
+# define machine_is_svc()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ALPHA2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ALPHA2
+# endif
+# define machine_is_alpha2()	(machine_arch_type == MACH_TYPE_ALPHA2)
+#else
+# define machine_is_alpha2()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ALPHA1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ALPHA1
+# endif
+# define machine_is_alpha1()	(machine_arch_type == MACH_TYPE_ALPHA1)
+#else
+# define machine_is_alpha1()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_NETARM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETARM
+# endif
+# define machine_is_netarm()	(machine_arch_type == MACH_TYPE_NETARM)
+#else
+# define machine_is_netarm()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_SIMPAD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SIMPAD
+# endif
+# define machine_is_simpad()	(machine_arch_type == MACH_TYPE_SIMPAD)
+#else
+# define machine_is_simpad()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PDA1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PDA1
+# endif
+# define machine_is_pda1()	(machine_arch_type == MACH_TYPE_PDA1)
+#else
+# define machine_is_pda1()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_LUBBOCK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LUBBOCK
+# endif
+# define machine_is_lubbock()	(machine_arch_type == MACH_TYPE_LUBBOCK)
+#else
+# define machine_is_lubbock()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ANIKO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ANIKO
+# endif
+# define machine_is_aniko()	(machine_arch_type == MACH_TYPE_ANIKO)
+#else
+# define machine_is_aniko()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CLEP7212
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CLEP7212
+# endif
+# define machine_is_clep7212()	(machine_arch_type == MACH_TYPE_CLEP7212)
+#else
+# define machine_is_clep7212()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CS89712
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CS89712
+# endif
+# define machine_is_cs89712()	(machine_arch_type == MACH_TYPE_CS89712)
+#else
+# define machine_is_cs89712()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_WEARARM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WEARARM
+# endif
+# define machine_is_weararm()	(machine_arch_type == MACH_TYPE_WEARARM)
+#else
+# define machine_is_weararm()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_POSSIO_PX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_POSSIO_PX
+# endif
+# define machine_is_possio_px()	(machine_arch_type == MACH_TYPE_POSSIO_PX)
+#else
+# define machine_is_possio_px()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_SIDEARM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SIDEARM
+# endif
+# define machine_is_sidearm()	(machine_arch_type == MACH_TYPE_SIDEARM)
+#else
+# define machine_is_sidearm()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_STORK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STORK
+# endif
+# define machine_is_stork()	(machine_arch_type == MACH_TYPE_STORK)
+#else
+# define machine_is_stork()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_SHANNON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHANNON
+# endif
+# define machine_is_shannon()	(machine_arch_type == MACH_TYPE_SHANNON)
+#else
+# define machine_is_shannon()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ACE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACE
+# endif
+# define machine_is_ace()	(machine_arch_type == MACH_TYPE_ACE)
+#else
+# define machine_is_ace()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_BALLYARM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BALLYARM
+# endif
+# define machine_is_ballyarm()	(machine_arch_type == MACH_TYPE_BALLYARM)
+#else
+# define machine_is_ballyarm()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_SIMPUTER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SIMPUTER
+# endif
+# define machine_is_simputer()	(machine_arch_type == MACH_TYPE_SIMPUTER)
+#else
+# define machine_is_simputer()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_NEXTERM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEXTERM
+# endif
+# define machine_is_nexterm()	(machine_arch_type == MACH_TYPE_NEXTERM)
+#else
+# define machine_is_nexterm()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_SA1100_ELF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SA1100_ELF
+# endif
+# define machine_is_sa1100_elf()	(machine_arch_type == MACH_TYPE_SA1100_ELF)
+#else
+# define machine_is_sa1100_elf()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_GATOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GATOR
+# endif
+# define machine_is_gator()	(machine_arch_type == MACH_TYPE_GATOR)
+#else
+# define machine_is_gator()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_GRANITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GRANITE
+# endif
+# define machine_is_granite()	(machine_arch_type == MACH_TYPE_GRANITE)
+#else
+# define machine_is_granite()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_CONSUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CONSUS
+# endif
+# define machine_is_consus()	(machine_arch_type == MACH_TYPE_CONSUS)
+#else
+# define machine_is_consus()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_AAED2000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AAED2000
+# endif
+# define machine_is_aaed2000()	(machine_arch_type == MACH_TYPE_AAED2000)
+#else
+# define machine_is_aaed2000()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CDB89712
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CDB89712
+# endif
+# define machine_is_cdb89712()	(machine_arch_type == MACH_TYPE_CDB89712)
+#else
+# define machine_is_cdb89712()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_GRAPHICSMASTER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GRAPHICSMASTER
+# endif
+# define machine_is_graphicsmaster()	(machine_arch_type == MACH_TYPE_GRAPHICSMASTER)
+#else
+# define machine_is_graphicsmaster()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ADSBITSY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSBITSY
+# endif
+# define machine_is_adsbitsy()	(machine_arch_type == MACH_TYPE_ADSBITSY)
+#else
+# define machine_is_adsbitsy()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PXA_IDP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_IDP
+# endif
+# define machine_is_pxa_idp()	(machine_arch_type == MACH_TYPE_PXA_IDP)
+#else
+# define machine_is_pxa_idp()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PLCE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PLCE
+# endif
+# define machine_is_plce()	(machine_arch_type == MACH_TYPE_PLCE)
+#else
+# define machine_is_plce()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_PT_SYSTEM3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PT_SYSTEM3
+# endif
+# define machine_is_pt_system3()	(machine_arch_type == MACH_TYPE_PT_SYSTEM3)
+#else
+# define machine_is_pt_system3()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_MEDALB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MEDALB
+# endif
+# define machine_is_murphy()	(machine_arch_type == MACH_TYPE_MEDALB)
+#else
+# define machine_is_murphy()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_EAGLE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EAGLE
+# endif
+# define machine_is_eagle()	(machine_arch_type == MACH_TYPE_EAGLE)
+#else
+# define machine_is_eagle()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_DSC21
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DSC21
+# endif
+# define machine_is_dsc21()	(machine_arch_type == MACH_TYPE_DSC21)
+#else
+# define machine_is_dsc21()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_DSC24
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DSC24
+# endif
+# define machine_is_dsc24()	(machine_arch_type == MACH_TYPE_DSC24)
+#else
+# define machine_is_dsc24()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_TI5472
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TI5472
+# endif
+# define machine_is_ti5472()	(machine_arch_type == MACH_TYPE_TI5472)
+#else
+# define machine_is_ti5472()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_AUTCPU12
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AUTCPU12
+# endif
+# define machine_is_autcpu12()	(machine_arch_type == MACH_TYPE_AUTCPU12)
+#else
+# define machine_is_autcpu12()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_UENGINE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UENGINE
+# endif
+# define machine_is_uengine()	(machine_arch_type == MACH_TYPE_UENGINE)
+#else
+# define machine_is_uengine()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_BLUESTEM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BLUESTEM
+# endif
+# define machine_is_bluestem()	(machine_arch_type == MACH_TYPE_BLUESTEM)
+#else
+# define machine_is_bluestem()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_XINGU8
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XINGU8
+# endif
+# define machine_is_xingu8()	(machine_arch_type == MACH_TYPE_XINGU8)
+#else
+# define machine_is_xingu8()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_BUSHSTB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BUSHSTB
+# endif
+# define machine_is_bushstb()	(machine_arch_type == MACH_TYPE_BUSHSTB)
+#else
+# define machine_is_bushstb()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_EPSILON1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EPSILON1
+# endif
+# define machine_is_epsilon1()	(machine_arch_type == MACH_TYPE_EPSILON1)
+#else
+# define machine_is_epsilon1()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_BALLOON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BALLOON
+# endif
+# define machine_is_balloon()	(machine_arch_type == MACH_TYPE_BALLOON)
+#else
+# define machine_is_balloon()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PUPPY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PUPPY
+# endif
+# define machine_is_puppy()	(machine_arch_type == MACH_TYPE_PUPPY)
+#else
+# define machine_is_puppy()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ELROY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ELROY
+# endif
+# define machine_is_elroy()	(machine_arch_type == MACH_TYPE_ELROY)
+#else
+# define machine_is_elroy()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_GMS720
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GMS720
+# endif
+# define machine_is_gms720()	(machine_arch_type == MACH_TYPE_GMS720)
+#else
+# define machine_is_gms720()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_S24X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S24X
+# endif
+# define machine_is_s24x()	(machine_arch_type == MACH_TYPE_S24X)
+#else
+# define machine_is_s24x()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_JTEL_CLEP7312
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JTEL_CLEP7312
+# endif
+# define machine_is_jtel_clep7312()	(machine_arch_type == MACH_TYPE_JTEL_CLEP7312)
+#else
+# define machine_is_jtel_clep7312()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CX821XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CX821XX
+# endif
+# define machine_is_cx821xx()	(machine_arch_type == MACH_TYPE_CX821XX)
+#else
+# define machine_is_cx821xx()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_EDB7312
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB7312
+# endif
+# define machine_is_edb7312()	(machine_arch_type == MACH_TYPE_EDB7312)
+#else
+# define machine_is_edb7312()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_BSA1110
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BSA1110
+# endif
+# define machine_is_bsa1110()	(machine_arch_type == MACH_TYPE_BSA1110)
+#else
+# define machine_is_bsa1110()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_POWERPIN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_POWERPIN
+# endif
+# define machine_is_powerpin()	(machine_arch_type == MACH_TYPE_POWERPIN)
+#else
+# define machine_is_powerpin()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_OPENARM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OPENARM
+# endif
+# define machine_is_openarm()	(machine_arch_type == MACH_TYPE_OPENARM)
+#else
+# define machine_is_openarm()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_WHITECHAPEL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WHITECHAPEL
+# endif
+# define machine_is_whitechapel()	(machine_arch_type == MACH_TYPE_WHITECHAPEL)
+#else
+# define machine_is_whitechapel()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_H3100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H3100
+# endif
+# define machine_is_h3100()	(machine_arch_type == MACH_TYPE_H3100)
+#else
+# define machine_is_h3100()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_H3800
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H3800
+# endif
+# define machine_is_h3800()	(machine_arch_type == MACH_TYPE_H3800)
+#else
+# define machine_is_h3800()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_BLUE_V1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BLUE_V1
+# endif
+# define machine_is_blue_v1()	(machine_arch_type == MACH_TYPE_BLUE_V1)
+#else
+# define machine_is_blue_v1()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PXA_CERF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_CERF
+# endif
+# define machine_is_pxa_cerf()	(machine_arch_type == MACH_TYPE_PXA_CERF)
+#else
+# define machine_is_pxa_cerf()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ARM7TEVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARM7TEVB
+# endif
+# define machine_is_arm7tevb()	(machine_arch_type == MACH_TYPE_ARM7TEVB)
+#else
+# define machine_is_arm7tevb()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_D7400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_D7400
+# endif
+# define machine_is_d7400()	(machine_arch_type == MACH_TYPE_D7400)
+#else
+# define machine_is_d7400()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PIRANHA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PIRANHA
+# endif
+# define machine_is_piranha()	(machine_arch_type == MACH_TYPE_PIRANHA)
+#else
+# define machine_is_piranha()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_SBCAMELOT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SBCAMELOT
+# endif
+# define machine_is_sbcamelot()	(machine_arch_type == MACH_TYPE_SBCAMELOT)
+#else
+# define machine_is_sbcamelot()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_KINGS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KINGS
+# endif
+# define machine_is_kings()	(machine_arch_type == MACH_TYPE_KINGS)
+#else
+# define machine_is_kings()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SMDK2400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK2400
+# endif
+# define machine_is_smdk2400()	(machine_arch_type == MACH_TYPE_SMDK2400)
+#else
+# define machine_is_smdk2400()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_COLLIE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COLLIE
+# endif
+# define machine_is_collie()	(machine_arch_type == MACH_TYPE_COLLIE)
+#else
+# define machine_is_collie()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IDR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IDR
+# endif
+# define machine_is_idr()	(machine_arch_type == MACH_TYPE_IDR)
+#else
+# define machine_is_idr()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_BADGE4
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BADGE4
+# endif
+# define machine_is_badge4()	(machine_arch_type == MACH_TYPE_BADGE4)
+#else
+# define machine_is_badge4()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_WEBNET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WEBNET
+# endif
+# define machine_is_webnet()	(machine_arch_type == MACH_TYPE_WEBNET)
+#else
+# define machine_is_webnet()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_D7300
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_D7300
+# endif
+# define machine_is_d7300()	(machine_arch_type == MACH_TYPE_D7300)
+#else
+# define machine_is_d7300()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_CEP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CEP
+# endif
+# define machine_is_cep()	(machine_arch_type == MACH_TYPE_CEP)
+#else
+# define machine_is_cep()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_FORTUNET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FORTUNET
+# endif
+# define machine_is_fortunet()	(machine_arch_type == MACH_TYPE_FORTUNET)
+#else
+# define machine_is_fortunet()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_VC547X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VC547X
+# endif
+# define machine_is_vc547x()	(machine_arch_type == MACH_TYPE_VC547X)
+#else
+# define machine_is_vc547x()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_FILEWALKER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FILEWALKER
+# endif
+# define machine_is_filewalker()	(machine_arch_type == MACH_TYPE_FILEWALKER)
+#else
+# define machine_is_filewalker()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_NETGATEWAY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETGATEWAY
+# endif
+# define machine_is_netgateway()	(machine_arch_type == MACH_TYPE_NETGATEWAY)
+#else
+# define machine_is_netgateway()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_SYMBOL2800
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SYMBOL2800
+# endif
+# define machine_is_symbol2800()	(machine_arch_type == MACH_TYPE_SYMBOL2800)
+#else
+# define machine_is_symbol2800()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_SUNS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SUNS
+# endif
+# define machine_is_suns()	(machine_arch_type == MACH_TYPE_SUNS)
+#else
+# define machine_is_suns()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_FRODO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FRODO
+# endif
+# define machine_is_frodo()	(machine_arch_type == MACH_TYPE_FRODO)
+#else
+# define machine_is_frodo()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_MACH_TYTE_MS301
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MACH_TYTE_MS301
+# endif
+# define machine_is_ms301()	(machine_arch_type == MACH_TYPE_MACH_TYTE_MS301)
+#else
+# define machine_is_ms301()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_MX1ADS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX1ADS
+# endif
+# define machine_is_mx1ads()	(machine_arch_type == MACH_TYPE_MX1ADS)
+#else
+# define machine_is_mx1ads()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_H7201
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H7201
+# endif
+# define machine_is_h7201()	(machine_arch_type == MACH_TYPE_H7201)
+#else
+# define machine_is_h7201()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_H7202
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H7202
+# endif
+# define machine_is_h7202()	(machine_arch_type == MACH_TYPE_H7202)
+#else
+# define machine_is_h7202()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_AMICO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AMICO
+# endif
+# define machine_is_amico()	(machine_arch_type == MACH_TYPE_AMICO)
+#else
+# define machine_is_amico()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_IAM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IAM
+# endif
+# define machine_is_iam()	(machine_arch_type == MACH_TYPE_IAM)
+#else
+# define machine_is_iam()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_TT530
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TT530
+# endif
+# define machine_is_tt530()	(machine_arch_type == MACH_TYPE_TT530)
+#else
+# define machine_is_tt530()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SAM2400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SAM2400
+# endif
+# define machine_is_sam2400()	(machine_arch_type == MACH_TYPE_SAM2400)
+#else
+# define machine_is_sam2400()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_JORNADA56X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JORNADA56X
+# endif
+# define machine_is_jornada56x()	(machine_arch_type == MACH_TYPE_JORNADA56X)
+#else
+# define machine_is_jornada56x()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ACTIVE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACTIVE
+# endif
+# define machine_is_active()	(machine_arch_type == MACH_TYPE_ACTIVE)
+#else
+# define machine_is_active()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IQ80321
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IQ80321
+# endif
+# define machine_is_iq80321()	(machine_arch_type == MACH_TYPE_IQ80321)
+#else
+# define machine_is_iq80321()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_WID
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WID
+# endif
+# define machine_is_wid()	(machine_arch_type == MACH_TYPE_WID)
+#else
+# define machine_is_wid()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SABINAL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SABINAL
+# endif
+# define machine_is_sabinal()	(machine_arch_type == MACH_TYPE_SABINAL)
+#else
+# define machine_is_sabinal()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXP425_MATACUMBE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXP425_MATACUMBE
+# endif
+# define machine_is_ixp425_matacumbe()	(machine_arch_type == MACH_TYPE_IXP425_MATACUMBE)
+#else
+# define machine_is_ixp425_matacumbe()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_MINIPRINT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MINIPRINT
+# endif
+# define machine_is_miniprint()	(machine_arch_type == MACH_TYPE_MINIPRINT)
+#else
+# define machine_is_miniprint()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ADM510X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADM510X
+# endif
+# define machine_is_adm510x()	(machine_arch_type == MACH_TYPE_ADM510X)
+#else
+# define machine_is_adm510x()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_SVS200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SVS200
+# endif
+# define machine_is_svs200()	(machine_arch_type == MACH_TYPE_SVS200)
+#else
+# define machine_is_svs200()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ATG_TCU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ATG_TCU
+# endif
+# define machine_is_atg_tcu()	(machine_arch_type == MACH_TYPE_ATG_TCU)
+#else
+# define machine_is_atg_tcu()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_JORNADA820
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JORNADA820
+# endif
+# define machine_is_jornada820()	(machine_arch_type == MACH_TYPE_JORNADA820)
+#else
+# define machine_is_jornada820()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_S3C44B0
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S3C44B0
+# endif
+# define machine_is_s3c44b0()	(machine_arch_type == MACH_TYPE_S3C44B0)
+#else
+# define machine_is_s3c44b0()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_MARGIS2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MARGIS2
+# endif
+# define machine_is_margis2()	(machine_arch_type == MACH_TYPE_MARGIS2)
+#else
+# define machine_is_margis2()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_KS8695
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KS8695
+# endif
+# define machine_is_ks8695()	(machine_arch_type == MACH_TYPE_KS8695)
+#else
+# define machine_is_ks8695()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_BRH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BRH
+# endif
+# define machine_is_brh()	(machine_arch_type == MACH_TYPE_BRH)
+#else
+# define machine_is_brh()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_S3C2410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S3C2410
+# endif
+# define machine_is_s3c2410()	(machine_arch_type == MACH_TYPE_S3C2410)
+#else
+# define machine_is_s3c2410()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_POSSIO_PX30
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_POSSIO_PX30
+# endif
+# define machine_is_possio_px30()	(machine_arch_type == MACH_TYPE_POSSIO_PX30)
+#else
+# define machine_is_possio_px30()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_S3C2800
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S3C2800
+# endif
+# define machine_is_s3c2800()	(machine_arch_type == MACH_TYPE_S3C2800)
+#else
+# define machine_is_s3c2800()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_FLEETWOOD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FLEETWOOD
+# endif
+# define machine_is_fleetwood()	(machine_arch_type == MACH_TYPE_FLEETWOOD)
+#else
+# define machine_is_fleetwood()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_OMAHA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAHA
+# endif
+# define machine_is_omaha()	(machine_arch_type == MACH_TYPE_OMAHA)
+#else
+# define machine_is_omaha()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_TA7
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TA7
+# endif
+# define machine_is_ta7()	(machine_arch_type == MACH_TYPE_TA7)
+#else
+# define machine_is_ta7()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_NOVA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NOVA
+# endif
+# define machine_is_nova()	(machine_arch_type == MACH_TYPE_NOVA)
+#else
+# define machine_is_nova()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_HMK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HMK
+# endif
+# define machine_is_hmk()	(machine_arch_type == MACH_TYPE_HMK)
+#else
+# define machine_is_hmk()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_KARO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KARO
+# endif
+# define machine_is_karo()	(machine_arch_type == MACH_TYPE_KARO)
+#else
+# define machine_is_karo()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_FESTER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FESTER
+# endif
+# define machine_is_fester()	(machine_arch_type == MACH_TYPE_FESTER)
+#else
+# define machine_is_fester()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_GPI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GPI
+# endif
+# define machine_is_gpi()	(machine_arch_type == MACH_TYPE_GPI)
+#else
+# define machine_is_gpi()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SMDK2410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK2410
+# endif
+# define machine_is_smdk2410()	(machine_arch_type == MACH_TYPE_SMDK2410)
+#else
+# define machine_is_smdk2410()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_I519
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_I519
+# endif
+# define machine_is_i519()	(machine_arch_type == MACH_TYPE_I519)
+#else
+# define machine_is_i519()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_NEXIO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEXIO
+# endif
+# define machine_is_nexio()	(machine_arch_type == MACH_TYPE_NEXIO)
+#else
+# define machine_is_nexio()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_BITBOX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BITBOX
+# endif
+# define machine_is_bitbox()	(machine_arch_type == MACH_TYPE_BITBOX)
+#else
+# define machine_is_bitbox()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_G200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_G200
+# endif
+# define machine_is_g200()	(machine_arch_type == MACH_TYPE_G200)
+#else
+# define machine_is_g200()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_GILL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GILL
+# endif
+# define machine_is_gill()	(machine_arch_type == MACH_TYPE_GILL)
+#else
+# define machine_is_gill()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PXA_MERCURY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_MERCURY
+# endif
+# define machine_is_pxa_mercury()	(machine_arch_type == MACH_TYPE_PXA_MERCURY)
+#else
+# define machine_is_pxa_mercury()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CEIVA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CEIVA
+# endif
+# define machine_is_ceiva()	(machine_arch_type == MACH_TYPE_CEIVA)
+#else
+# define machine_is_ceiva()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_FRET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FRET
+# endif
+# define machine_is_fret()	(machine_arch_type == MACH_TYPE_FRET)
+#else
+# define machine_is_fret()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_EMAILPHONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EMAILPHONE
+# endif
+# define machine_is_emailphone()	(machine_arch_type == MACH_TYPE_EMAILPHONE)
+#else
+# define machine_is_emailphone()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_H3900
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H3900
+# endif
+# define machine_is_h3900()	(machine_arch_type == MACH_TYPE_H3900)
+#else
+# define machine_is_h3900()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PXA1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA1
+# endif
+# define machine_is_pxa1()	(machine_arch_type == MACH_TYPE_PXA1)
+#else
+# define machine_is_pxa1()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_KOAN369
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KOAN369
+# endif
+# define machine_is_koan369()	(machine_arch_type == MACH_TYPE_KOAN369)
+#else
+# define machine_is_koan369()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_COGENT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COGENT
+# endif
+# define machine_is_cogent()	(machine_arch_type == MACH_TYPE_COGENT)
+#else
+# define machine_is_cogent()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ESL_SIMPUTER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESL_SIMPUTER
+# endif
+# define machine_is_esl_simputer()	(machine_arch_type == MACH_TYPE_ESL_SIMPUTER)
+#else
+# define machine_is_esl_simputer()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ESL_SIMPUTER_CLR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESL_SIMPUTER_CLR
+# endif
+# define machine_is_esl_simputer_clr()	(machine_arch_type == MACH_TYPE_ESL_SIMPUTER_CLR)
+#else
+# define machine_is_esl_simputer_clr()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ESL_SIMPUTER_BW
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESL_SIMPUTER_BW
+# endif
+# define machine_is_esl_simputer_bw()	(machine_arch_type == MACH_TYPE_ESL_SIMPUTER_BW)
+#else
+# define machine_is_esl_simputer_bw()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_HHP_CRADLE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HHP_CRADLE
+# endif
+# define machine_is_hhp_cradle()	(machine_arch_type == MACH_TYPE_HHP_CRADLE)
+#else
+# define machine_is_hhp_cradle()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_HE500
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HE500
+# endif
+# define machine_is_he500()	(machine_arch_type == MACH_TYPE_HE500)
+#else
+# define machine_is_he500()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_INHANDELF2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INHANDELF2
+# endif
+# define machine_is_inhandelf2()	(machine_arch_type == MACH_TYPE_INHANDELF2)
+#else
+# define machine_is_inhandelf2()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_INHANDFTIP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INHANDFTIP
+# endif
+# define machine_is_inhandftip()	(machine_arch_type == MACH_TYPE_INHANDFTIP)
+#else
+# define machine_is_inhandftip()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_DNP1110
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DNP1110
+# endif
+# define machine_is_dnp1110()	(machine_arch_type == MACH_TYPE_DNP1110)
+#else
+# define machine_is_dnp1110()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_PNP1110
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PNP1110
+# endif
+# define machine_is_pnp1110()	(machine_arch_type == MACH_TYPE_PNP1110)
+#else
+# define machine_is_pnp1110()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CSB226
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB226
+# endif
+# define machine_is_csb226()	(machine_arch_type == MACH_TYPE_CSB226)
+#else
+# define machine_is_csb226()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ARNOLD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARNOLD
+# endif
+# define machine_is_arnold()	(machine_arch_type == MACH_TYPE_ARNOLD)
+#else
+# define machine_is_arnold()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VOICEBLUE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VOICEBLUE
+# endif
+# define machine_is_voiceblue()	(machine_arch_type == MACH_TYPE_VOICEBLUE)
+#else
+# define machine_is_voiceblue()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_JZ8028
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JZ8028
+# endif
+# define machine_is_jz8028()	(machine_arch_type == MACH_TYPE_JZ8028)
+#else
+# define machine_is_jz8028()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_H5400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H5400
+# endif
+# define machine_is_h5400()	(machine_arch_type == MACH_TYPE_H5400)
+#else
+# define machine_is_h5400()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_FORTE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FORTE
+# endif
+# define machine_is_forte()	(machine_arch_type == MACH_TYPE_FORTE)
+#else
+# define machine_is_forte()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ACAM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACAM
+# endif
+# define machine_is_acam()	(machine_arch_type == MACH_TYPE_ACAM)
+#else
+# define machine_is_acam()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ABOX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ABOX
+# endif
+# define machine_is_abox()	(machine_arch_type == MACH_TYPE_ABOX)
+#else
+# define machine_is_abox()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ATMEL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ATMEL
+# endif
+# define machine_is_atmel()	(machine_arch_type == MACH_TYPE_ATMEL)
+#else
+# define machine_is_atmel()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SITSANG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SITSANG
+# endif
+# define machine_is_sitsang()	(machine_arch_type == MACH_TYPE_SITSANG)
+#else
+# define machine_is_sitsang()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_CPU1110LCDNET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CPU1110LCDNET
+# endif
+# define machine_is_cpu1110lcdnet()	(machine_arch_type == MACH_TYPE_CPU1110LCDNET)
+#else
+# define machine_is_cpu1110lcdnet()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_MPL_VCMA9
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MPL_VCMA9
+# endif
+# define machine_is_mpl_vcma9()	(machine_arch_type == MACH_TYPE_MPL_VCMA9)
+#else
+# define machine_is_mpl_vcma9()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_OPUS_A1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OPUS_A1
+# endif
+# define machine_is_opus_a1()	(machine_arch_type == MACH_TYPE_OPUS_A1)
+#else
+# define machine_is_opus_a1()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_DAYTONA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAYTONA
+# endif
+# define machine_is_daytona()	(machine_arch_type == MACH_TYPE_DAYTONA)
+#else
+# define machine_is_daytona()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_KILLBEAR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KILLBEAR
+# endif
+# define machine_is_killbear()	(machine_arch_type == MACH_TYPE_KILLBEAR)
+#else
+# define machine_is_killbear()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_YOHO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_YOHO
+# endif
+# define machine_is_yoho()	(machine_arch_type == MACH_TYPE_YOHO)
+#else
+# define machine_is_yoho()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_JASPER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JASPER
+# endif
+# define machine_is_jasper()	(machine_arch_type == MACH_TYPE_JASPER)
+#else
+# define machine_is_jasper()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_DSC25
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DSC25
+# endif
+# define machine_is_dsc25()	(machine_arch_type == MACH_TYPE_DSC25)
+#else
+# define machine_is_dsc25()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_INNOVATOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_INNOVATOR
+# endif
+# define machine_is_omap_innovator()	(machine_arch_type == MACH_TYPE_OMAP_INNOVATOR)
+#else
+# define machine_is_omap_innovator()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_RAMSES
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RAMSES
+# endif
+# define machine_is_ramses()	(machine_arch_type == MACH_TYPE_RAMSES)
+#else
+# define machine_is_ramses()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_S28X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S28X
+# endif
+# define machine_is_s28x()	(machine_arch_type == MACH_TYPE_S28X)
+#else
+# define machine_is_s28x()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_MPORT3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MPORT3
+# endif
+# define machine_is_mport3()	(machine_arch_type == MACH_TYPE_MPORT3)
+#else
+# define machine_is_mport3()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PXA_EAGLE250
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_EAGLE250
+# endif
+# define machine_is_pxa_eagle250()	(machine_arch_type == MACH_TYPE_PXA_EAGLE250)
+#else
+# define machine_is_pxa_eagle250()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PDB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PDB
+# endif
+# define machine_is_pdb()	(machine_arch_type == MACH_TYPE_PDB)
+#else
+# define machine_is_pdb()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_BLUE_2G
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BLUE_2G
+# endif
+# define machine_is_blue_2g()	(machine_arch_type == MACH_TYPE_BLUE_2G)
+#else
+# define machine_is_blue_2g()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_BLUEARCH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BLUEARCH
+# endif
+# define machine_is_bluearch()	(machine_arch_type == MACH_TYPE_BLUEARCH)
+#else
+# define machine_is_bluearch()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXDP2400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP2400
+# endif
+# define machine_is_ixdp2400()	(machine_arch_type == MACH_TYPE_IXDP2400)
+#else
+# define machine_is_ixdp2400()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXDP2800
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP2800
+# endif
+# define machine_is_ixdp2800()	(machine_arch_type == MACH_TYPE_IXDP2800)
+#else
+# define machine_is_ixdp2800()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_EXPLORER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EXPLORER
+# endif
+# define machine_is_explorer()	(machine_arch_type == MACH_TYPE_EXPLORER)
+#else
+# define machine_is_explorer()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXDP425
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP425
+# endif
+# define machine_is_ixdp425()	(machine_arch_type == MACH_TYPE_IXDP425)
+#else
+# define machine_is_ixdp425()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CHIMP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CHIMP
+# endif
+# define machine_is_chimp()	(machine_arch_type == MACH_TYPE_CHIMP)
+#else
+# define machine_is_chimp()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_STORK_NEST
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STORK_NEST
+# endif
+# define machine_is_stork_nest()	(machine_arch_type == MACH_TYPE_STORK_NEST)
+#else
+# define machine_is_stork_nest()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_STORK_EGG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STORK_EGG
+# endif
+# define machine_is_stork_egg()	(machine_arch_type == MACH_TYPE_STORK_EGG)
+#else
+# define machine_is_stork_egg()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_WISMO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WISMO
+# endif
+# define machine_is_wismo()	(machine_arch_type == MACH_TYPE_WISMO)
+#else
+# define machine_is_wismo()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_EZLINX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EZLINX
+# endif
+# define machine_is_ezlinx()	(machine_arch_type == MACH_TYPE_EZLINX)
+#else
+# define machine_is_ezlinx()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_AT91RM9200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91RM9200
+# endif
+# define machine_is_at91rm9200()	(machine_arch_type == MACH_TYPE_AT91RM9200)
+#else
+# define machine_is_at91rm9200()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ORION
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ORION
+# endif
+# define machine_is_orion()	(machine_arch_type == MACH_TYPE_ORION)
+#else
+# define machine_is_orion()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_NEPTUNE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEPTUNE
+# endif
+# define machine_is_neptune()	(machine_arch_type == MACH_TYPE_NEPTUNE)
+#else
+# define machine_is_neptune()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_HACKKIT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HACKKIT
+# endif
+# define machine_is_hackkit()	(machine_arch_type == MACH_TYPE_HACKKIT)
+#else
+# define machine_is_hackkit()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PXA_WINS30
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_WINS30
+# endif
+# define machine_is_pxa_wins30()	(machine_arch_type == MACH_TYPE_PXA_WINS30)
+#else
+# define machine_is_pxa_wins30()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_LAVINNA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LAVINNA
+# endif
+# define machine_is_lavinna()	(machine_arch_type == MACH_TYPE_LAVINNA)
+#else
+# define machine_is_lavinna()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PXA_UENGINE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_UENGINE
+# endif
+# define machine_is_pxa_uengine()	(machine_arch_type == MACH_TYPE_PXA_UENGINE)
+#else
+# define machine_is_pxa_uengine()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_INNOKOM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INNOKOM
+# endif
+# define machine_is_innokom()	(machine_arch_type == MACH_TYPE_INNOKOM)
+#else
+# define machine_is_innokom()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_BMS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BMS
+# endif
+# define machine_is_bms()	(machine_arch_type == MACH_TYPE_BMS)
+#else
+# define machine_is_bms()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXCDP1100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXCDP1100
+# endif
+# define machine_is_ixcdp1100()	(machine_arch_type == MACH_TYPE_IXCDP1100)
+#else
+# define machine_is_ixcdp1100()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PRPMC1100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PRPMC1100
+# endif
+# define machine_is_prpmc1100()	(machine_arch_type == MACH_TYPE_PRPMC1100)
+#else
+# define machine_is_prpmc1100()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_AT91RM9200DK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91RM9200DK
+# endif
+# define machine_is_at91rm9200dk()	(machine_arch_type == MACH_TYPE_AT91RM9200DK)
+#else
+# define machine_is_at91rm9200dk()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ARMSTICK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMSTICK
+# endif
+# define machine_is_armstick()	(machine_arch_type == MACH_TYPE_ARMSTICK)
+#else
+# define machine_is_armstick()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ARMONIE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMONIE
+# endif
+# define machine_is_armonie()	(machine_arch_type == MACH_TYPE_ARMONIE)
+#else
+# define machine_is_armonie()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_MPORT1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MPORT1
+# endif
+# define machine_is_mport1()	(machine_arch_type == MACH_TYPE_MPORT1)
+#else
+# define machine_is_mport1()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_S3C5410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S3C5410
+# endif
+# define machine_is_s3c5410()	(machine_arch_type == MACH_TYPE_S3C5410)
+#else
+# define machine_is_s3c5410()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ZCP320A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZCP320A
+# endif
+# define machine_is_zcp320a()	(machine_arch_type == MACH_TYPE_ZCP320A)
+#else
+# define machine_is_zcp320a()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_I_BOX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_I_BOX
+# endif
+# define machine_is_i_box()	(machine_arch_type == MACH_TYPE_I_BOX)
+#else
+# define machine_is_i_box()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_STLC1502
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STLC1502
+# endif
+# define machine_is_stlc1502()	(machine_arch_type == MACH_TYPE_STLC1502)
+#else
+# define machine_is_stlc1502()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SIREN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SIREN
+# endif
+# define machine_is_siren()	(machine_arch_type == MACH_TYPE_SIREN)
+#else
+# define machine_is_siren()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_GREENLAKE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GREENLAKE
+# endif
+# define machine_is_greenlake()	(machine_arch_type == MACH_TYPE_GREENLAKE)
+#else
+# define machine_is_greenlake()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ARGUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARGUS
+# endif
+# define machine_is_argus()	(machine_arch_type == MACH_TYPE_ARGUS)
+#else
+# define machine_is_argus()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_COMBADGE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COMBADGE
+# endif
+# define machine_is_combadge()	(machine_arch_type == MACH_TYPE_COMBADGE)
+#else
+# define machine_is_combadge()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ROKEPXA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ROKEPXA
+# endif
+# define machine_is_rokepxa()	(machine_arch_type == MACH_TYPE_ROKEPXA)
+#else
+# define machine_is_rokepxa()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CINTEGRATOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CINTEGRATOR
+# endif
+# define machine_is_cintegrator()	(machine_arch_type == MACH_TYPE_CINTEGRATOR)
+#else
+# define machine_is_cintegrator()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_GUIDEA07
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GUIDEA07
+# endif
+# define machine_is_guidea07()	(machine_arch_type == MACH_TYPE_GUIDEA07)
+#else
+# define machine_is_guidea07()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_TAT257
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TAT257
+# endif
+# define machine_is_tat257()	(machine_arch_type == MACH_TYPE_TAT257)
+#else
+# define machine_is_tat257()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IGP2425
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IGP2425
+# endif
+# define machine_is_igp2425()	(machine_arch_type == MACH_TYPE_IGP2425)
+#else
+# define machine_is_igp2425()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_BLUEGRAMMA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BLUEGRAMMA
+# endif
+# define machine_is_bluegrama()	(machine_arch_type == MACH_TYPE_BLUEGRAMMA)
+#else
+# define machine_is_bluegrama()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IPOD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IPOD
+# endif
+# define machine_is_ipod()	(machine_arch_type == MACH_TYPE_IPOD)
+#else
+# define machine_is_ipod()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ADSBITSYX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSBITSYX
+# endif
+# define machine_is_adsbitsyx()	(machine_arch_type == MACH_TYPE_ADSBITSYX)
+#else
+# define machine_is_adsbitsyx()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_TRIZEPS2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TRIZEPS2
+# endif
+# define machine_is_trizeps2()	(machine_arch_type == MACH_TYPE_TRIZEPS2)
+#else
+# define machine_is_trizeps2()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_VIPER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VIPER
+# endif
+# define machine_is_viper()	(machine_arch_type == MACH_TYPE_VIPER)
+#else
+# define machine_is_viper()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ADSBITSYPLUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSBITSYPLUS
+# endif
+# define machine_is_adsbitsyplus()	(machine_arch_type == MACH_TYPE_ADSBITSYPLUS)
+#else
+# define machine_is_adsbitsyplus()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ADSAGC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSAGC
+# endif
+# define machine_is_adsagc()	(machine_arch_type == MACH_TYPE_ADSAGC)
+#else
+# define machine_is_adsagc()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_STP7312
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STP7312
+# endif
+# define machine_is_stp7312()	(machine_arch_type == MACH_TYPE_STP7312)
+#else
+# define machine_is_stp7312()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NX_PHNX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NX_PHNX
+# endif
+# define machine_is_nx_phnx()	(machine_arch_type == MACH_TYPE_NX_PHNX)
+#else
+# define machine_is_nx_phnx()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_WEP_EP250
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WEP_EP250
+# endif
+# define machine_is_wep_ep250()	(machine_arch_type == MACH_TYPE_WEP_EP250)
+#else
+# define machine_is_wep_ep250()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_INHANDELF3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INHANDELF3
+# endif
+# define machine_is_inhandelf3()	(machine_arch_type == MACH_TYPE_INHANDELF3)
+#else
+# define machine_is_inhandelf3()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ADI_COYOTE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADI_COYOTE
+# endif
+# define machine_is_adi_coyote()	(machine_arch_type == MACH_TYPE_ADI_COYOTE)
+#else
+# define machine_is_adi_coyote()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IYONIX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IYONIX
+# endif
+# define machine_is_iyonix()	(machine_arch_type == MACH_TYPE_IYONIX)
+#else
+# define machine_is_iyonix()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_DAMICAM_SA1110
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAMICAM_SA1110
+# endif
+# define machine_is_damicam1()	(machine_arch_type == MACH_TYPE_DAMICAM_SA1110)
+#else
+# define machine_is_damicam1()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_MEG03
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MEG03
+# endif
+# define machine_is_meg03()	(machine_arch_type == MACH_TYPE_MEG03)
+#else
+# define machine_is_meg03()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PXA_WHITECHAPEL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_WHITECHAPEL
+# endif
+# define machine_is_pxa_whitechapel()	(machine_arch_type == MACH_TYPE_PXA_WHITECHAPEL)
+#else
+# define machine_is_pxa_whitechapel()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_NWSC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NWSC
+# endif
+# define machine_is_nwsc()	(machine_arch_type == MACH_TYPE_NWSC)
+#else
+# define machine_is_nwsc()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_NWLARM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NWLARM
+# endif
+# define machine_is_nwlarm()	(machine_arch_type == MACH_TYPE_NWLARM)
+#else
+# define machine_is_nwlarm()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXP425_MGUARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXP425_MGUARD
+# endif
+# define machine_is_ixp425_mguard()	(machine_arch_type == MACH_TYPE_IXP425_MGUARD)
+#else
+# define machine_is_ixp425_mguard()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PXA_NETDCU4
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_NETDCU4
+# endif
+# define machine_is_pxa_netdcu4()	(machine_arch_type == MACH_TYPE_PXA_NETDCU4)
+#else
+# define machine_is_pxa_netdcu4()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXDP2401
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP2401
+# endif
+# define machine_is_ixdp2401()	(machine_arch_type == MACH_TYPE_IXDP2401)
+#else
+# define machine_is_ixdp2401()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXDP2801
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP2801
+# endif
+# define machine_is_ixdp2801()	(machine_arch_type == MACH_TYPE_IXDP2801)
+#else
+# define machine_is_ixdp2801()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ZODIAC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZODIAC
+# endif
+# define machine_is_zodiac()	(machine_arch_type == MACH_TYPE_ZODIAC)
+#else
+# define machine_is_zodiac()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ARMMODUL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMMODUL
+# endif
+# define machine_is_armmodul()	(machine_arch_type == MACH_TYPE_ARMMODUL)
+#else
+# define machine_is_armmodul()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_KETOP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KETOP
+# endif
+# define machine_is_ketop()	(machine_arch_type == MACH_TYPE_KETOP)
+#else
+# define machine_is_ketop()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_AV7200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AV7200
+# endif
+# define machine_is_av7200()	(machine_arch_type == MACH_TYPE_AV7200)
+#else
+# define machine_is_av7200()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ARCH_TI925
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARCH_TI925
+# endif
+# define machine_is_arch_ti925()	(machine_arch_type == MACH_TYPE_ARCH_TI925)
+#else
+# define machine_is_arch_ti925()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ACQ200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACQ200
+# endif
+# define machine_is_acq200()	(machine_arch_type == MACH_TYPE_ACQ200)
+#else
+# define machine_is_acq200()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_PT_DAFIT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PT_DAFIT
+# endif
+# define machine_is_pt_dafit()	(machine_arch_type == MACH_TYPE_PT_DAFIT)
+#else
+# define machine_is_pt_dafit()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IHBA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IHBA
+# endif
+# define machine_is_ihba()	(machine_arch_type == MACH_TYPE_IHBA)
+#else
+# define machine_is_ihba()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_QUINQUE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QUINQUE
+# endif
+# define machine_is_quinque()	(machine_arch_type == MACH_TYPE_QUINQUE)
+#else
+# define machine_is_quinque()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_NIMBRAONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NIMBRAONE
+# endif
+# define machine_is_nimbraone()	(machine_arch_type == MACH_TYPE_NIMBRAONE)
+#else
+# define machine_is_nimbraone()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_NIMBRA29X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NIMBRA29X
+# endif
+# define machine_is_nimbra29x()	(machine_arch_type == MACH_TYPE_NIMBRA29X)
+#else
+# define machine_is_nimbra29x()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_NIMBRA210
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NIMBRA210
+# endif
+# define machine_is_nimbra210()	(machine_arch_type == MACH_TYPE_NIMBRA210)
+#else
+# define machine_is_nimbra210()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_HHP_D95XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HHP_D95XX
+# endif
+# define machine_is_hhp_d95xx()	(machine_arch_type == MACH_TYPE_HHP_D95XX)
+#else
+# define machine_is_hhp_d95xx()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_LABARM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LABARM
+# endif
+# define machine_is_labarm()	(machine_arch_type == MACH_TYPE_LABARM)
+#else
+# define machine_is_labarm()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_M825XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_M825XX
+# endif
+# define machine_is_m825xx()	(machine_arch_type == MACH_TYPE_M825XX)
+#else
+# define machine_is_m825xx()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_M7100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_M7100
+# endif
+# define machine_is_m7100()	(machine_arch_type == MACH_TYPE_M7100)
+#else
+# define machine_is_m7100()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_NIPC2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NIPC2
+# endif
+# define machine_is_nipc2()	(machine_arch_type == MACH_TYPE_NIPC2)
+#else
+# define machine_is_nipc2()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_FU7202
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FU7202
+# endif
+# define machine_is_fu7202()	(machine_arch_type == MACH_TYPE_FU7202)
+#else
+# define machine_is_fu7202()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ADSAGX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSAGX
+# endif
+# define machine_is_adsagx()	(machine_arch_type == MACH_TYPE_ADSAGX)
+#else
+# define machine_is_adsagx()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PXA_POOH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_POOH
+# endif
+# define machine_is_pxa_pooh()	(machine_arch_type == MACH_TYPE_PXA_POOH)
+#else
+# define machine_is_pxa_pooh()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_BANDON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BANDON
+# endif
+# define machine_is_bandon()	(machine_arch_type == MACH_TYPE_BANDON)
+#else
+# define machine_is_bandon()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PCM7210
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCM7210
+# endif
+# define machine_is_pcm7210()	(machine_arch_type == MACH_TYPE_PCM7210)
+#else
+# define machine_is_pcm7210()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_NMS9200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NMS9200
+# endif
+# define machine_is_nms9200()	(machine_arch_type == MACH_TYPE_NMS9200)
+#else
+# define machine_is_nms9200()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_LOGODL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LOGODL
+# endif
+# define machine_is_logodl()	(machine_arch_type == MACH_TYPE_LOGODL)
+#else
+# define machine_is_logodl()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_M7140
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_M7140
+# endif
+# define machine_is_m7140()	(machine_arch_type == MACH_TYPE_M7140)
+#else
+# define machine_is_m7140()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_KOREBOT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KOREBOT
+# endif
+# define machine_is_korebot()	(machine_arch_type == MACH_TYPE_KOREBOT)
+#else
+# define machine_is_korebot()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IQ31244
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IQ31244
+# endif
+# define machine_is_iq31244()	(machine_arch_type == MACH_TYPE_IQ31244)
+#else
+# define machine_is_iq31244()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_KOAN393
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KOAN393
+# endif
+# define machine_is_koan393()	(machine_arch_type == MACH_TYPE_KOAN393)
+#else
+# define machine_is_koan393()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_INHANDFTIP3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INHANDFTIP3
+# endif
+# define machine_is_inhandftip3()	(machine_arch_type == MACH_TYPE_INHANDFTIP3)
+#else
+# define machine_is_inhandftip3()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_GONZO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GONZO
+# endif
+# define machine_is_gonzo()	(machine_arch_type == MACH_TYPE_GONZO)
+#else
+# define machine_is_gonzo()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_BAST
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BAST
+# endif
+# define machine_is_bast()	(machine_arch_type == MACH_TYPE_BAST)
+#else
+# define machine_is_bast()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SCANPASS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SCANPASS
+# endif
+# define machine_is_scanpass()	(machine_arch_type == MACH_TYPE_SCANPASS)
+#else
+# define machine_is_scanpass()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_EP7312_POOH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EP7312_POOH
+# endif
+# define machine_is_ep7312_pooh()	(machine_arch_type == MACH_TYPE_EP7312_POOH)
+#else
+# define machine_is_ep7312_pooh()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_TA7S
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TA7S
+# endif
+# define machine_is_ta7s()	(machine_arch_type == MACH_TYPE_TA7S)
+#else
+# define machine_is_ta7s()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_TA7V
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TA7V
+# endif
+# define machine_is_ta7v()	(machine_arch_type == MACH_TYPE_TA7V)
+#else
+# define machine_is_ta7v()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_ICARUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ICARUS
+# endif
+# define machine_is_icarus()	(machine_arch_type == MACH_TYPE_ICARUS)
+#else
+# define machine_is_icarus()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_H1900
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H1900
+# endif
+# define machine_is_h1900()	(machine_arch_type == MACH_TYPE_H1900)
+#else
+# define machine_is_h1900()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_GEMINI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GEMINI
+# endif
+# define machine_is_gemini()	(machine_arch_type == MACH_TYPE_GEMINI)
+#else
+# define machine_is_gemini()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_AXIM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AXIM
+# endif
+# define machine_is_axim()	(machine_arch_type == MACH_TYPE_AXIM)
+#else
+# define machine_is_axim()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_AUDIOTRON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AUDIOTRON
+# endif
+# define machine_is_audiotron()	(machine_arch_type == MACH_TYPE_AUDIOTRON)
+#else
+# define machine_is_audiotron()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_H2200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H2200
+# endif
+# define machine_is_h2200()	(machine_arch_type == MACH_TYPE_H2200)
+#else
+# define machine_is_h2200()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_LOOX600
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LOOX600
+# endif
+# define machine_is_loox600()	(machine_arch_type == MACH_TYPE_LOOX600)
+#else
+# define machine_is_loox600()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_NIOP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NIOP
+# endif
+# define machine_is_niop()	(machine_arch_type == MACH_TYPE_NIOP)
+#else
+# define machine_is_niop()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_DM310
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DM310
+# endif
+# define machine_is_dm310()	(machine_arch_type == MACH_TYPE_DM310)
+#else
+# define machine_is_dm310()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SEEDPXA_C2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SEEDPXA_C2
+# endif
+# define machine_is_seedpxa_c2()	(machine_arch_type == MACH_TYPE_SEEDPXA_C2)
+#else
+# define machine_is_seedpxa_c2()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXP4XX_MGUARD_PCI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXP4XX_MGUARD_PCI
+# endif
+# define machine_is_ixp4xx_mguardpci()	(machine_arch_type == MACH_TYPE_IXP4XX_MGUARD_PCI)
+#else
+# define machine_is_ixp4xx_mguardpci()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_H1940
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H1940
+# endif
+# define machine_is_h1940()	(machine_arch_type == MACH_TYPE_H1940)
+#else
+# define machine_is_h1940()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SCORPIO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SCORPIO
+# endif
+# define machine_is_scorpio()	(machine_arch_type == MACH_TYPE_SCORPIO)
+#else
+# define machine_is_scorpio()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_VIVA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VIVA
+# endif
+# define machine_is_viva()	(machine_arch_type == MACH_TYPE_VIVA)
+#else
+# define machine_is_viva()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PXA_XCARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_XCARD
+# endif
+# define machine_is_pxa_xcard()	(machine_arch_type == MACH_TYPE_PXA_XCARD)
+#else
+# define machine_is_pxa_xcard()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CSB335
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB335
+# endif
+# define machine_is_csb335()	(machine_arch_type == MACH_TYPE_CSB335)
+#else
+# define machine_is_csb335()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXRD425
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXRD425
+# endif
+# define machine_is_ixrd425()	(machine_arch_type == MACH_TYPE_IXRD425)
+#else
+# define machine_is_ixrd425()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IQ80315
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IQ80315
+# endif
+# define machine_is_iq80315()	(machine_arch_type == MACH_TYPE_IQ80315)
+#else
+# define machine_is_iq80315()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_NMP7312
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NMP7312
+# endif
+# define machine_is_nmp7312()	(machine_arch_type == MACH_TYPE_NMP7312)
+#else
+# define machine_is_nmp7312()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CX861XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CX861XX
+# endif
+# define machine_is_cx861xx()	(machine_arch_type == MACH_TYPE_CX861XX)
+#else
+# define machine_is_cx861xx()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ENP2611
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ENP2611
+# endif
+# define machine_is_enp2611()	(machine_arch_type == MACH_TYPE_ENP2611)
+#else
+# define machine_is_enp2611()	(0)
+#endif
+
+#ifdef CONFIG_SA1100_XDA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XDA
+# endif
+# define machine_is_xda()	(machine_arch_type == MACH_TYPE_XDA)
+#else
+# define machine_is_xda()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_CSIR_IMS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSIR_IMS
+# endif
+# define machine_is_csir_ims()	(machine_arch_type == MACH_TYPE_CSIR_IMS)
+#else
+# define machine_is_csir_ims()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IXP421_DNAEETH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXP421_DNAEETH
+# endif
+# define machine_is_ixp421_dnaeeth()	(machine_arch_type == MACH_TYPE_IXP421_DNAEETH)
+#else
+# define machine_is_ixp421_dnaeeth()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_POCKETSERV9200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_POCKETSERV9200
+# endif
+# define machine_is_pocketserv9200()	(machine_arch_type == MACH_TYPE_POCKETSERV9200)
+#else
+# define machine_is_pocketserv9200()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_TOTO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOTO
+# endif
+# define machine_is_toto()	(machine_arch_type == MACH_TYPE_TOTO)
+#else
+# define machine_is_toto()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_S3C2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S3C2440
+# endif
+# define machine_is_s3c2440()	(machine_arch_type == MACH_TYPE_S3C2440)
+#else
+# define machine_is_s3c2440()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_KS8695P
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KS8695P
+# endif
+# define machine_is_ks8695p()	(machine_arch_type == MACH_TYPE_KS8695P)
+#else
+# define machine_is_ks8695p()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SE4000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SE4000
+# endif
+# define machine_is_se4000()	(machine_arch_type == MACH_TYPE_SE4000)
+#else
+# define machine_is_se4000()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_QUADRICEPS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QUADRICEPS
+# endif
+# define machine_is_quadriceps()	(machine_arch_type == MACH_TYPE_QUADRICEPS)
+#else
+# define machine_is_quadriceps()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_BRONCO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BRONCO
+# endif
+# define machine_is_bronco()	(machine_arch_type == MACH_TYPE_BRONCO)
+#else
+# define machine_is_bronco()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ESL_SOFCOMP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESL_SOFCOMP
+# endif
+# define machine_is_esl_sofcomp()	(machine_arch_type == MACH_TYPE_ESL_SOFCOMP)
+#else
+# define machine_is_esl_sofcomp()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_S5C7375
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S5C7375
+# endif
+# define machine_is_s5c7375()	(machine_arch_type == MACH_TYPE_S5C7375)
+#else
+# define machine_is_s5c7375()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_SPEARHEAD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPEARHEAD
+# endif
+# define machine_is_spearhead()	(machine_arch_type == MACH_TYPE_SPEARHEAD)
+#else
+# define machine_is_spearhead()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PANTERA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PANTERA
+# endif
+# define machine_is_pantera()	(machine_arch_type == MACH_TYPE_PANTERA)
+#else
+# define machine_is_pantera()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PRAYOGLITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PRAYOGLITE
+# endif
+# define machine_is_prayoglite()	(machine_arch_type == MACH_TYPE_PRAYOGLITE)
+#else
+# define machine_is_prayoglite()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_GUMSTIK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GUMSTIK
+# endif
+# define machine_is_gumstix()	(machine_arch_type == MACH_TYPE_GUMSTIK)
+#else
+# define machine_is_gumstix()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_RCUBE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RCUBE
+# endif
+# define machine_is_rcube()	(machine_arch_type == MACH_TYPE_RCUBE)
+#else
+# define machine_is_rcube()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_REA_OLV
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_REA_OLV
+# endif
+# define machine_is_rea_olv()	(machine_arch_type == MACH_TYPE_REA_OLV)
+#else
+# define machine_is_rea_olv()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PXA_IPHONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_IPHONE
+# endif
+# define machine_is_pxa_iphone()	(machine_arch_type == MACH_TYPE_PXA_IPHONE)
+#else
+# define machine_is_pxa_iphone()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_S3C3410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S3C3410
+# endif
+# define machine_is_s3c3410()	(machine_arch_type == MACH_TYPE_S3C3410)
+#else
+# define machine_is_s3c3410()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ESPD_4510B
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESPD_4510B
+# endif
+# define machine_is_espd_4510b()	(machine_arch_type == MACH_TYPE_ESPD_4510B)
+#else
+# define machine_is_espd_4510b()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_MP1X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MP1X
+# endif
+# define machine_is_mp1x()	(machine_arch_type == MACH_TYPE_MP1X)
+#else
+# define machine_is_mp1x()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_AT91RM9200TB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91RM9200TB
+# endif
+# define machine_is_at91rm9200tb()	(machine_arch_type == MACH_TYPE_AT91RM9200TB)
+#else
+# define machine_is_at91rm9200tb()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_ADSVGX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSVGX
+# endif
+# define machine_is_adsvgx()	(machine_arch_type == MACH_TYPE_ADSVGX)
+#else
+# define machine_is_adsvgx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_H2
+# endif
+# define machine_is_omap_h2()	(machine_arch_type == MACH_TYPE_OMAP_H2)
+#else
+# define machine_is_omap_h2()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_PELEE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PELEE
+# endif
+# define machine_is_pelee()	(machine_arch_type == MACH_TYPE_PELEE)
+#else
+# define machine_is_pelee()	(0)
+#endif
+
+#ifdef CONFIG_MACH_E740
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_E740
+# endif
+# define machine_is_e740()	(machine_arch_type == MACH_TYPE_E740)
+#else
+# define machine_is_e740()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_IQ80331
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IQ80331
+# endif
+# define machine_is_iq80331()	(machine_arch_type == MACH_TYPE_IQ80331)
+#else
+# define machine_is_iq80331()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_VERSATILE_PB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VERSATILE_PB
+# endif
+# define machine_is_versatile_pb()	(machine_arch_type == MACH_TYPE_VERSATILE_PB)
+#else
+# define machine_is_versatile_pb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KEV7A400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KEV7A400
+# endif
+# define machine_is_kev7a400()	(machine_arch_type == MACH_TYPE_KEV7A400)
+#else
+# define machine_is_kev7a400()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LPD7A400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPD7A400
+# endif
+# define machine_is_lpd7a400()	(machine_arch_type == MACH_TYPE_LPD7A400)
+#else
+# define machine_is_lpd7a400()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LPD7A404
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPD7A404
+# endif
+# define machine_is_lpd7a404()	(machine_arch_type == MACH_TYPE_LPD7A404)
+#else
+# define machine_is_lpd7a404()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_FUJITSU_CAMELOT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FUJITSU_CAMELOT
+# endif
+# define machine_is_fujitsu_camelot()	(machine_arch_type == MACH_TYPE_FUJITSU_CAMELOT)
+#else
+# define machine_is_fujitsu_camelot()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_JANUS2M
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JANUS2M
+# endif
+# define machine_is_janus2m()	(machine_arch_type == MACH_TYPE_JANUS2M)
+#else
+# define machine_is_janus2m()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EMBTF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EMBTF
+# endif
+# define machine_is_embtf()	(machine_arch_type == MACH_TYPE_EMBTF)
+#else
+# define machine_is_embtf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HPM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HPM
+# endif
+# define machine_is_hpm()	(machine_arch_type == MACH_TYPE_HPM)
+#else
+# define machine_is_hpm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDK2410TK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK2410TK
+# endif
+# define machine_is_smdk2410tk()	(machine_arch_type == MACH_TYPE_SMDK2410TK)
+#else
+# define machine_is_smdk2410tk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDK2410AJ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK2410AJ
+# endif
+# define machine_is_smdk2410aj()	(machine_arch_type == MACH_TYPE_SMDK2410AJ)
+#else
+# define machine_is_smdk2410aj()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STREETRACER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STREETRACER
+# endif
+# define machine_is_streetracer()	(machine_arch_type == MACH_TYPE_STREETRACER)
+#else
+# define machine_is_streetracer()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EFRAME
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EFRAME
+# endif
+# define machine_is_eframe()	(machine_arch_type == MACH_TYPE_EFRAME)
+#else
+# define machine_is_eframe()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSB337
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB337
+# endif
+# define machine_is_csb337()	(machine_arch_type == MACH_TYPE_CSB337)
+#else
+# define machine_is_csb337()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PXA_LARK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_LARK
+# endif
+# define machine_is_pxa_lark()	(machine_arch_type == MACH_TYPE_PXA_LARK)
+#else
+# define machine_is_pxa_lark()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PNP2110
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PNP2110
+# endif
+# define machine_is_pxa_pnp2110()	(machine_arch_type == MACH_TYPE_PNP2110)
+#else
+# define machine_is_pxa_pnp2110()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TCC72X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TCC72X
+# endif
+# define machine_is_tcc72x()	(machine_arch_type == MACH_TYPE_TCC72X)
+#else
+# define machine_is_tcc72x()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ALTAIR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ALTAIR
+# endif
+# define machine_is_altair()	(machine_arch_type == MACH_TYPE_ALTAIR)
+#else
+# define machine_is_altair()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KC3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KC3
+# endif
+# define machine_is_kc3()	(machine_arch_type == MACH_TYPE_KC3)
+#else
+# define machine_is_kc3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SINTEFTD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SINTEFTD
+# endif
+# define machine_is_sinteftd()	(machine_arch_type == MACH_TYPE_SINTEFTD)
+#else
+# define machine_is_sinteftd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MAINSTONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MAINSTONE
+# endif
+# define machine_is_mainstone()	(machine_arch_type == MACH_TYPE_MAINSTONE)
+#else
+# define machine_is_mainstone()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ADAY4X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADAY4X
+# endif
+# define machine_is_aday4x()	(machine_arch_type == MACH_TYPE_ADAY4X)
+#else
+# define machine_is_aday4x()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LITE300
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LITE300
+# endif
+# define machine_is_lite300()	(machine_arch_type == MACH_TYPE_LITE300)
+#else
+# define machine_is_lite300()	(0)
+#endif
+
+#ifdef CONFIG_MACH_S5C7376
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S5C7376
+# endif
+# define machine_is_s5c7376()	(machine_arch_type == MACH_TYPE_S5C7376)
+#else
+# define machine_is_s5c7376()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MT02
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MT02
+# endif
+# define machine_is_mt02()	(machine_arch_type == MACH_TYPE_MT02)
+#else
+# define machine_is_mt02()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MPORT3S
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MPORT3S
+# endif
+# define machine_is_mport3s()	(machine_arch_type == MACH_TYPE_MPORT3S)
+#else
+# define machine_is_mport3s()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RA_ALPHA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RA_ALPHA
+# endif
+# define machine_is_ra_alpha()	(machine_arch_type == MACH_TYPE_RA_ALPHA)
+#else
+# define machine_is_ra_alpha()	(0)
+#endif
+
+#ifdef CONFIG_MACH_XCEP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XCEP
+# endif
+# define machine_is_xcep()	(machine_arch_type == MACH_TYPE_XCEP)
+#else
+# define machine_is_xcep()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARCOM_MERCURY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARCOM_MERCURY
+# endif
+# define machine_is_arcom_mercury()	(machine_arch_type == MACH_TYPE_ARCOM_MERCURY)
+#else
+# define machine_is_arcom_mercury()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STARGATE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STARGATE
+# endif
+# define machine_is_stargate()	(machine_arch_type == MACH_TYPE_STARGATE)
+#else
+# define machine_is_stargate()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMADILLOJ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMADILLOJ
+# endif
+# define machine_is_armadilloj()	(machine_arch_type == MACH_TYPE_ARMADILLOJ)
+#else
+# define machine_is_armadilloj()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ELROY_JACK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ELROY_JACK
+# endif
+# define machine_is_elroy_jack()	(machine_arch_type == MACH_TYPE_ELROY_JACK)
+#else
+# define machine_is_elroy_jack()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BACKEND
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BACKEND
+# endif
+# define machine_is_backend()	(machine_arch_type == MACH_TYPE_BACKEND)
+#else
+# define machine_is_backend()	(0)
+#endif
+
+#ifdef CONFIG_MACH_S5LINBOX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S5LINBOX
+# endif
+# define machine_is_s5linbox()	(machine_arch_type == MACH_TYPE_S5LINBOX)
+#else
+# define machine_is_s5linbox()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NOMADIK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NOMADIK
+# endif
+# define machine_is_nomadik()	(machine_arch_type == MACH_TYPE_NOMADIK)
+#else
+# define machine_is_nomadik()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IA_CPU_9200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IA_CPU_9200
+# endif
+# define machine_is_ia_cpu_9200()	(machine_arch_type == MACH_TYPE_IA_CPU_9200)
+#else
+# define machine_is_ia_cpu_9200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91_BJA1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91_BJA1
+# endif
+# define machine_is_at91_bja1()	(machine_arch_type == MACH_TYPE_AT91_BJA1)
+#else
+# define machine_is_at91_bja1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CORGI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CORGI
+# endif
+# define machine_is_corgi()	(machine_arch_type == MACH_TYPE_CORGI)
+#else
+# define machine_is_corgi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_POODLE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_POODLE
+# endif
+# define machine_is_poodle()	(machine_arch_type == MACH_TYPE_POODLE)
+#else
+# define machine_is_poodle()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TEN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TEN
+# endif
+# define machine_is_ten()	(machine_arch_type == MACH_TYPE_TEN)
+#else
+# define machine_is_ten()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ROVERP5P
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ROVERP5P
+# endif
+# define machine_is_roverp5p()	(machine_arch_type == MACH_TYPE_ROVERP5P)
+#else
+# define machine_is_roverp5p()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SC2700
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SC2700
+# endif
+# define machine_is_sc2700()	(machine_arch_type == MACH_TYPE_SC2700)
+#else
+# define machine_is_sc2700()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EX_EAGLE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EX_EAGLE
+# endif
+# define machine_is_ex_eagle()	(machine_arch_type == MACH_TYPE_EX_EAGLE)
+#else
+# define machine_is_ex_eagle()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NX_PXA12
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NX_PXA12
+# endif
+# define machine_is_nx_pxa12()	(machine_arch_type == MACH_TYPE_NX_PXA12)
+#else
+# define machine_is_nx_pxa12()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NX_PXA5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NX_PXA5
+# endif
+# define machine_is_nx_pxa5()	(machine_arch_type == MACH_TYPE_NX_PXA5)
+#else
+# define machine_is_nx_pxa5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BLACKBOARD2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BLACKBOARD2
+# endif
+# define machine_is_blackboard2()	(machine_arch_type == MACH_TYPE_BLACKBOARD2)
+#else
+# define machine_is_blackboard2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_I819
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_I819
+# endif
+# define machine_is_i819()	(machine_arch_type == MACH_TYPE_I819)
+#else
+# define machine_is_i819()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IXMB995E
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXMB995E
+# endif
+# define machine_is_ixmb995e()	(machine_arch_type == MACH_TYPE_IXMB995E)
+#else
+# define machine_is_ixmb995e()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SKYRIDER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SKYRIDER
+# endif
+# define machine_is_skyrider()	(machine_arch_type == MACH_TYPE_SKYRIDER)
+#else
+# define machine_is_skyrider()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SKYHAWK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SKYHAWK
+# endif
+# define machine_is_skyhawk()	(machine_arch_type == MACH_TYPE_SKYHAWK)
+#else
+# define machine_is_skyhawk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ENTERPRISE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ENTERPRISE
+# endif
+# define machine_is_enterprise()	(machine_arch_type == MACH_TYPE_ENTERPRISE)
+#else
+# define machine_is_enterprise()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DEP2410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DEP2410
+# endif
+# define machine_is_dep2410()	(machine_arch_type == MACH_TYPE_DEP2410)
+#else
+# define machine_is_dep2410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMCORE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMCORE
+# endif
+# define machine_is_armcore()	(machine_arch_type == MACH_TYPE_ARMCORE)
+#else
+# define machine_is_armcore()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HOBBIT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HOBBIT
+# endif
+# define machine_is_hobbit()	(machine_arch_type == MACH_TYPE_HOBBIT)
+#else
+# define machine_is_hobbit()	(0)
+#endif
+
+#ifdef CONFIG_MACH_H7210
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H7210
+# endif
+# define machine_is_h7210()	(machine_arch_type == MACH_TYPE_H7210)
+#else
+# define machine_is_h7210()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PXA_NETDCU5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_NETDCU5
+# endif
+# define machine_is_pxa_netdcu5()	(machine_arch_type == MACH_TYPE_PXA_NETDCU5)
+#else
+# define machine_is_pxa_netdcu5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACC
+# endif
+# define machine_is_acc()	(machine_arch_type == MACH_TYPE_ACC)
+#else
+# define machine_is_acc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESL_SARVA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESL_SARVA
+# endif
+# define machine_is_esl_sarva()	(machine_arch_type == MACH_TYPE_ESL_SARVA)
+#else
+# define machine_is_esl_sarva()	(0)
+#endif
+
+#ifdef CONFIG_MACH_XM250
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XM250
+# endif
+# define machine_is_xm250()	(machine_arch_type == MACH_TYPE_XM250)
+#else
+# define machine_is_xm250()	(0)
+#endif
+
+#ifdef CONFIG_MACH_T6TC1XB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_T6TC1XB
+# endif
+# define machine_is_t6tc1xb()	(machine_arch_type == MACH_TYPE_T6TC1XB)
+#else
+# define machine_is_t6tc1xb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESS710
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESS710
+# endif
+# define machine_is_ess710()	(machine_arch_type == MACH_TYPE_ESS710)
+#else
+# define machine_is_ess710()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX3ADS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX3ADS
+# endif
+# define machine_is_mx3ads()	(machine_arch_type == MACH_TYPE_MX3ADS)
+#else
+# define machine_is_mx3ads()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HIMALAYA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HIMALAYA
+# endif
+# define machine_is_himalaya()	(machine_arch_type == MACH_TYPE_HIMALAYA)
+#else
+# define machine_is_himalaya()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BOLFENK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BOLFENK
+# endif
+# define machine_is_bolfenk()	(machine_arch_type == MACH_TYPE_BOLFENK)
+#else
+# define machine_is_bolfenk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91RM9200KR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91RM9200KR
+# endif
+# define machine_is_at91rm9200kr()	(machine_arch_type == MACH_TYPE_AT91RM9200KR)
+#else
+# define machine_is_at91rm9200kr()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9312
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9312
+# endif
+# define machine_is_edb9312()	(machine_arch_type == MACH_TYPE_EDB9312)
+#else
+# define machine_is_edb9312()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_GENERIC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_GENERIC
+# endif
+# define machine_is_omap_generic()	(machine_arch_type == MACH_TYPE_OMAP_GENERIC)
+#else
+# define machine_is_omap_generic()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AXIMX3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AXIMX3
+# endif
+# define machine_is_aximx3()	(machine_arch_type == MACH_TYPE_AXIMX3)
+#else
+# define machine_is_aximx3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EB67XDIP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EB67XDIP
+# endif
+# define machine_is_eb67xdip()	(machine_arch_type == MACH_TYPE_EB67XDIP)
+#else
+# define machine_is_eb67xdip()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WEBTXS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WEBTXS
+# endif
+# define machine_is_webtxs()	(machine_arch_type == MACH_TYPE_WEBTXS)
+#else
+# define machine_is_webtxs()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HAWK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HAWK
+# endif
+# define machine_is_hawk()	(machine_arch_type == MACH_TYPE_HAWK)
+#else
+# define machine_is_hawk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CCAT91SBC001
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CCAT91SBC001
+# endif
+# define machine_is_ccat91sbc001()	(machine_arch_type == MACH_TYPE_CCAT91SBC001)
+#else
+# define machine_is_ccat91sbc001()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EXPRESSO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EXPRESSO
+# endif
+# define machine_is_expresso()	(machine_arch_type == MACH_TYPE_EXPRESSO)
+#else
+# define machine_is_expresso()	(0)
+#endif
+
+#ifdef CONFIG_MACH_H4000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H4000
+# endif
+# define machine_is_h4000()	(machine_arch_type == MACH_TYPE_H4000)
+#else
+# define machine_is_h4000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DINO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DINO
+# endif
+# define machine_is_dino()	(machine_arch_type == MACH_TYPE_DINO)
+#else
+# define machine_is_dino()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ML675K
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ML675K
+# endif
+# define machine_is_ml675k()	(machine_arch_type == MACH_TYPE_ML675K)
+#else
+# define machine_is_ml675k()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9301
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9301
+# endif
+# define machine_is_edb9301()	(machine_arch_type == MACH_TYPE_EDB9301)
+#else
+# define machine_is_edb9301()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9315
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9315
+# endif
+# define machine_is_edb9315()	(machine_arch_type == MACH_TYPE_EDB9315)
+#else
+# define machine_is_edb9315()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RECIVA_TT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RECIVA_TT
+# endif
+# define machine_is_reciva_tt()	(machine_arch_type == MACH_TYPE_RECIVA_TT)
+#else
+# define machine_is_reciva_tt()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSTCB01
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSTCB01
+# endif
+# define machine_is_cstcb01()	(machine_arch_type == MACH_TYPE_CSTCB01)
+#else
+# define machine_is_cstcb01()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSTCB1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSTCB1
+# endif
+# define machine_is_cstcb1()	(machine_arch_type == MACH_TYPE_CSTCB1)
+#else
+# define machine_is_cstcb1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SHADWELL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHADWELL
+# endif
+# define machine_is_shadwell()	(machine_arch_type == MACH_TYPE_SHADWELL)
+#else
+# define machine_is_shadwell()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GOEPEL263
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GOEPEL263
+# endif
+# define machine_is_goepel263()	(machine_arch_type == MACH_TYPE_GOEPEL263)
+#else
+# define machine_is_goepel263()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACQ100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACQ100
+# endif
+# define machine_is_acq100()	(machine_arch_type == MACH_TYPE_ACQ100)
+#else
+# define machine_is_acq100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX1FS2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX1FS2
+# endif
+# define machine_is_mx1fs2()	(machine_arch_type == MACH_TYPE_MX1FS2)
+#else
+# define machine_is_mx1fs2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HIPTOP_G1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HIPTOP_G1
+# endif
+# define machine_is_hiptop_g1()	(machine_arch_type == MACH_TYPE_HIPTOP_G1)
+#else
+# define machine_is_hiptop_g1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPARKY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPARKY
+# endif
+# define machine_is_sparky()	(machine_arch_type == MACH_TYPE_SPARKY)
+#else
+# define machine_is_sparky()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NS9750
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NS9750
+# endif
+# define machine_is_ns9750()	(machine_arch_type == MACH_TYPE_NS9750)
+#else
+# define machine_is_ns9750()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PHOENIX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PHOENIX
+# endif
+# define machine_is_phoenix()	(machine_arch_type == MACH_TYPE_PHOENIX)
+#else
+# define machine_is_phoenix()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VR1000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VR1000
+# endif
+# define machine_is_vr1000()	(machine_arch_type == MACH_TYPE_VR1000)
+#else
+# define machine_is_vr1000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DEISTERPXA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DEISTERPXA
+# endif
+# define machine_is_deisterpxa()	(machine_arch_type == MACH_TYPE_DEISTERPXA)
+#else
+# define machine_is_deisterpxa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BCM1160
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BCM1160
+# endif
+# define machine_is_bcm1160()	(machine_arch_type == MACH_TYPE_BCM1160)
+#else
+# define machine_is_bcm1160()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCM022
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCM022
+# endif
+# define machine_is_pcm022()	(machine_arch_type == MACH_TYPE_PCM022)
+#else
+# define machine_is_pcm022()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ADSGCX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSGCX
+# endif
+# define machine_is_adsgcx()	(machine_arch_type == MACH_TYPE_ADSGCX)
+#else
+# define machine_is_adsgcx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DREADNAUGHT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DREADNAUGHT
+# endif
+# define machine_is_dreadnaught()	(machine_arch_type == MACH_TYPE_DREADNAUGHT)
+#else
+# define machine_is_dreadnaught()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DM320
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DM320
+# endif
+# define machine_is_dm320()	(machine_arch_type == MACH_TYPE_DM320)
+#else
+# define machine_is_dm320()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MARKOV
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MARKOV
+# endif
+# define machine_is_markov()	(machine_arch_type == MACH_TYPE_MARKOV)
+#else
+# define machine_is_markov()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COS7A400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COS7A400
+# endif
+# define machine_is_cos7a400()	(machine_arch_type == MACH_TYPE_COS7A400)
+#else
+# define machine_is_cos7a400()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MILANO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MILANO
+# endif
+# define machine_is_milano()	(machine_arch_type == MACH_TYPE_MILANO)
+#else
+# define machine_is_milano()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UE9328
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UE9328
+# endif
+# define machine_is_ue9328()	(machine_arch_type == MACH_TYPE_UE9328)
+#else
+# define machine_is_ue9328()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UEX255
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UEX255
+# endif
+# define machine_is_uex255()	(machine_arch_type == MACH_TYPE_UEX255)
+#else
+# define machine_is_uex255()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UE2410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UE2410
+# endif
+# define machine_is_ue2410()	(machine_arch_type == MACH_TYPE_UE2410)
+#else
+# define machine_is_ue2410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_A620
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_A620
+# endif
+# define machine_is_a620()	(machine_arch_type == MACH_TYPE_A620)
+#else
+# define machine_is_a620()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OCELOT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OCELOT
+# endif
+# define machine_is_ocelot()	(machine_arch_type == MACH_TYPE_OCELOT)
+#else
+# define machine_is_ocelot()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CHEETAH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CHEETAH
+# endif
+# define machine_is_cheetah()	(machine_arch_type == MACH_TYPE_CHEETAH)
+#else
+# define machine_is_cheetah()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_PERSEUS2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_PERSEUS2
+# endif
+# define machine_is_omap_perseus2()	(machine_arch_type == MACH_TYPE_OMAP_PERSEUS2)
+#else
+# define machine_is_omap_perseus2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZVUE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZVUE
+# endif
+# define machine_is_zvue()	(machine_arch_type == MACH_TYPE_ZVUE)
+#else
+# define machine_is_zvue()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ROVERP1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ROVERP1
+# endif
+# define machine_is_roverp1()	(machine_arch_type == MACH_TYPE_ROVERP1)
+#else
+# define machine_is_roverp1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ASIDIAL2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ASIDIAL2
+# endif
+# define machine_is_asidial2()	(machine_arch_type == MACH_TYPE_ASIDIAL2)
+#else
+# define machine_is_asidial2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_S3C24A0
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S3C24A0
+# endif
+# define machine_is_s3c24a0()	(machine_arch_type == MACH_TYPE_S3C24A0)
+#else
+# define machine_is_s3c24a0()	(0)
+#endif
+
+#ifdef CONFIG_MACH_E800
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_E800
+# endif
+# define machine_is_e800()	(machine_arch_type == MACH_TYPE_E800)
+#else
+# define machine_is_e800()	(0)
+#endif
+
+#ifdef CONFIG_MACH_E750
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_E750
+# endif
+# define machine_is_e750()	(machine_arch_type == MACH_TYPE_E750)
+#else
+# define machine_is_e750()	(0)
+#endif
+
+#ifdef CONFIG_MACH_S3C5500
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S3C5500
+# endif
+# define machine_is_s3c5500()	(machine_arch_type == MACH_TYPE_S3C5500)
+#else
+# define machine_is_s3c5500()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDK5500
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK5500
+# endif
+# define machine_is_smdk5500()	(machine_arch_type == MACH_TYPE_SMDK5500)
+#else
+# define machine_is_smdk5500()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SIGNALSYNC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SIGNALSYNC
+# endif
+# define machine_is_signalsync()	(machine_arch_type == MACH_TYPE_SIGNALSYNC)
+#else
+# define machine_is_signalsync()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NBC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NBC
+# endif
+# define machine_is_nbc()	(machine_arch_type == MACH_TYPE_NBC)
+#else
+# define machine_is_nbc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KODIAK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KODIAK
+# endif
+# define machine_is_kodiak()	(machine_arch_type == MACH_TYPE_KODIAK)
+#else
+# define machine_is_kodiak()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NETBOOKPRO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETBOOKPRO
+# endif
+# define machine_is_netbookpro()	(machine_arch_type == MACH_TYPE_NETBOOKPRO)
+#else
+# define machine_is_netbookpro()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HW90200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HW90200
+# endif
+# define machine_is_hw90200()	(machine_arch_type == MACH_TYPE_HW90200)
+#else
+# define machine_is_hw90200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CONDOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CONDOR
+# endif
+# define machine_is_condor()	(machine_arch_type == MACH_TYPE_CONDOR)
+#else
+# define machine_is_condor()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CUP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CUP
+# endif
+# define machine_is_cup()	(machine_arch_type == MACH_TYPE_CUP)
+#else
+# define machine_is_cup()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KITE
+# endif
+# define machine_is_kite()	(machine_arch_type == MACH_TYPE_KITE)
+#else
+# define machine_is_kite()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SCB9328
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SCB9328
+# endif
+# define machine_is_scb9328()	(machine_arch_type == MACH_TYPE_SCB9328)
+#else
+# define machine_is_scb9328()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_H3
+# endif
+# define machine_is_omap_h3()	(machine_arch_type == MACH_TYPE_OMAP_H3)
+#else
+# define machine_is_omap_h3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H4
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_H4
+# endif
+# define machine_is_omap_h4()	(machine_arch_type == MACH_TYPE_OMAP_H4)
+#else
+# define machine_is_omap_h4()	(0)
+#endif
+
+#ifdef CONFIG_MACH_N10
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_N10
+# endif
+# define machine_is_n10()	(machine_arch_type == MACH_TYPE_N10)
+#else
+# define machine_is_n10()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MONTAJADE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MONTAJADE
+# endif
+# define machine_is_montejade()	(machine_arch_type == MACH_TYPE_MONTAJADE)
+#else
+# define machine_is_montejade()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SG560
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SG560
+# endif
+# define machine_is_sg560()	(machine_arch_type == MACH_TYPE_SG560)
+#else
+# define machine_is_sg560()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DP1000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DP1000
+# endif
+# define machine_is_dp1000()	(machine_arch_type == MACH_TYPE_DP1000)
+#else
+# define machine_is_dp1000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_OSK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_OSK
+# endif
+# define machine_is_omap_osk()	(machine_arch_type == MACH_TYPE_OMAP_OSK)
+#else
+# define machine_is_omap_osk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RG100V3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RG100V3
+# endif
+# define machine_is_rg100v3()	(machine_arch_type == MACH_TYPE_RG100V3)
+#else
+# define machine_is_rg100v3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX2ADS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX2ADS
+# endif
+# define machine_is_mx2ads()	(machine_arch_type == MACH_TYPE_MX2ADS)
+#else
+# define machine_is_mx2ads()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PXA_KILO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_KILO
+# endif
+# define machine_is_pxa_kilo()	(machine_arch_type == MACH_TYPE_PXA_KILO)
+#else
+# define machine_is_pxa_kilo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IXP4XX_EAGLE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXP4XX_EAGLE
+# endif
+# define machine_is_ixp4xx_eagle()	(machine_arch_type == MACH_TYPE_IXP4XX_EAGLE)
+#else
+# define machine_is_ixp4xx_eagle()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TOSA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOSA
+# endif
+# define machine_is_tosa()	(machine_arch_type == MACH_TYPE_TOSA)
+#else
+# define machine_is_tosa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MB2520F
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MB2520F
+# endif
+# define machine_is_mb2520f()	(machine_arch_type == MACH_TYPE_MB2520F)
+#else
+# define machine_is_mb2520f()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EMC1000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EMC1000
+# endif
+# define machine_is_emc1000()	(machine_arch_type == MACH_TYPE_EMC1000)
+#else
+# define machine_is_emc1000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TIDSC25
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TIDSC25
+# endif
+# define machine_is_tidsc25()	(machine_arch_type == MACH_TYPE_TIDSC25)
+#else
+# define machine_is_tidsc25()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AKCPMXL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AKCPMXL
+# endif
+# define machine_is_akcpmxl()	(machine_arch_type == MACH_TYPE_AKCPMXL)
+#else
+# define machine_is_akcpmxl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AV3XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AV3XX
+# endif
+# define machine_is_av3xx()	(machine_arch_type == MACH_TYPE_AV3XX)
+#else
+# define machine_is_av3xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AVILA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AVILA
+# endif
+# define machine_is_avila()	(machine_arch_type == MACH_TYPE_AVILA)
+#else
+# define machine_is_avila()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PXA_MPM10
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_MPM10
+# endif
+# define machine_is_pxa_mpm10()	(machine_arch_type == MACH_TYPE_PXA_MPM10)
+#else
+# define machine_is_pxa_mpm10()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PXA_KYANITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_KYANITE
+# endif
+# define machine_is_pxa_kyanite()	(machine_arch_type == MACH_TYPE_PXA_KYANITE)
+#else
+# define machine_is_pxa_kyanite()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SGOLD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SGOLD
+# endif
+# define machine_is_sgold()	(machine_arch_type == MACH_TYPE_SGOLD)
+#else
+# define machine_is_sgold()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OSCAR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OSCAR
+# endif
+# define machine_is_oscar()	(machine_arch_type == MACH_TYPE_OSCAR)
+#else
+# define machine_is_oscar()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EPXA4USB2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EPXA4USB2
+# endif
+# define machine_is_epxa4usb2()	(machine_arch_type == MACH_TYPE_EPXA4USB2)
+#else
+# define machine_is_epxa4usb2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_XSENGINE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XSENGINE
+# endif
+# define machine_is_xsengine()	(machine_arch_type == MACH_TYPE_XSENGINE)
+#else
+# define machine_is_xsengine()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IP600
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IP600
+# endif
+# define machine_is_ip600()	(machine_arch_type == MACH_TYPE_IP600)
+#else
+# define machine_is_ip600()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MCAN2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MCAN2
+# endif
+# define machine_is_mcan2()	(machine_arch_type == MACH_TYPE_MCAN2)
+#else
+# define machine_is_mcan2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DDI_BLUERIDGE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DDI_BLUERIDGE
+# endif
+# define machine_is_ddi_blueridge()	(machine_arch_type == MACH_TYPE_DDI_BLUERIDGE)
+#else
+# define machine_is_ddi_blueridge()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SKYMINDER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SKYMINDER
+# endif
+# define machine_is_skyminder()	(machine_arch_type == MACH_TYPE_SKYMINDER)
+#else
+# define machine_is_skyminder()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LPD79520
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPD79520
+# endif
+# define machine_is_lpd79520()	(machine_arch_type == MACH_TYPE_LPD79520)
+#else
+# define machine_is_lpd79520()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9302
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9302
+# endif
+# define machine_is_edb9302()	(machine_arch_type == MACH_TYPE_EDB9302)
+#else
+# define machine_is_edb9302()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HW90340
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HW90340
+# endif
+# define machine_is_hw90340()	(machine_arch_type == MACH_TYPE_HW90340)
+#else
+# define machine_is_hw90340()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CIP_BOX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CIP_BOX
+# endif
+# define machine_is_cip_box()	(machine_arch_type == MACH_TYPE_CIP_BOX)
+#else
+# define machine_is_cip_box()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IVPN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IVPN
+# endif
+# define machine_is_ivpn()	(machine_arch_type == MACH_TYPE_IVPN)
+#else
+# define machine_is_ivpn()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RSOC2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RSOC2
+# endif
+# define machine_is_rsoc2()	(machine_arch_type == MACH_TYPE_RSOC2)
+#else
+# define machine_is_rsoc2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HUSKY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HUSKY
+# endif
+# define machine_is_husky()	(machine_arch_type == MACH_TYPE_HUSKY)
+#else
+# define machine_is_husky()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BOXER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BOXER
+# endif
+# define machine_is_boxer()	(machine_arch_type == MACH_TYPE_BOXER)
+#else
+# define machine_is_boxer()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SHEPHERD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHEPHERD
+# endif
+# define machine_is_shepherd()	(machine_arch_type == MACH_TYPE_SHEPHERD)
+#else
+# define machine_is_shepherd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AML42800AA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AML42800AA
+# endif
+# define machine_is_aml42800aa()	(machine_arch_type == MACH_TYPE_AML42800AA)
+#else
+# define machine_is_aml42800aa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MACH_TYPE_ML674001
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MACH_TYPE_ML674001
+# endif
+# define machine_is_ml674001()	(machine_arch_type == MACH_TYPE_MACH_TYPE_ML674001)
+#else
+# define machine_is_ml674001()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LPC2294
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPC2294
+# endif
+# define machine_is_lpc2294()	(machine_arch_type == MACH_TYPE_LPC2294)
+#else
+# define machine_is_lpc2294()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SWITCHGRASS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SWITCHGRASS
+# endif
+# define machine_is_switchgrass()	(machine_arch_type == MACH_TYPE_SWITCHGRASS)
+#else
+# define machine_is_switchgrass()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ENS_CMU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ENS_CMU
+# endif
+# define machine_is_ens_cmu()	(machine_arch_type == MACH_TYPE_ENS_CMU)
+#else
+# define machine_is_ens_cmu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MM6_SDB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MM6_SDB
+# endif
+# define machine_is_mm6_sdb()	(machine_arch_type == MACH_TYPE_MM6_SDB)
+#else
+# define machine_is_mm6_sdb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SATURN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SATURN
+# endif
+# define machine_is_saturn()	(machine_arch_type == MACH_TYPE_SATURN)
+#else
+# define machine_is_saturn()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARGONPLUSEVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARGONPLUSEVB
+# endif
+# define machine_is_argonplusevb()	(machine_arch_type == MACH_TYPE_ARGONPLUSEVB)
+#else
+# define machine_is_argonplusevb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SCMA11EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SCMA11EVB
+# endif
+# define machine_is_scma11evb()	(machine_arch_type == MACH_TYPE_SCMA11EVB)
+#else
+# define machine_is_scma11evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDK2800
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK2800
+# endif
+# define machine_is_smdk2800()	(machine_arch_type == MACH_TYPE_SMDK2800)
+#else
+# define machine_is_smdk2800()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MTWILSON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MTWILSON
+# endif
+# define machine_is_mtwilson()	(machine_arch_type == MACH_TYPE_MTWILSON)
+#else
+# define machine_is_mtwilson()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZITI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZITI
+# endif
+# define machine_is_ziti()	(machine_arch_type == MACH_TYPE_ZITI)
+#else
+# define machine_is_ziti()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GRANDFATHER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GRANDFATHER
+# endif
+# define machine_is_grandfather()	(machine_arch_type == MACH_TYPE_GRANDFATHER)
+#else
+# define machine_is_grandfather()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TENGINE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TENGINE
+# endif
+# define machine_is_tengine()	(machine_arch_type == MACH_TYPE_TENGINE)
+#else
+# define machine_is_tengine()	(0)
+#endif
+
+#ifdef CONFIG_MACH_S3C2460
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S3C2460
+# endif
+# define machine_is_s3c2460()	(machine_arch_type == MACH_TYPE_S3C2460)
+#else
+# define machine_is_s3c2460()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PDM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PDM
+# endif
+# define machine_is_pdm()	(machine_arch_type == MACH_TYPE_PDM)
+#else
+# define machine_is_pdm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_H4700
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H4700
+# endif
+# define machine_is_h4700()	(machine_arch_type == MACH_TYPE_H4700)
+#else
+# define machine_is_h4700()	(0)
+#endif
+
+#ifdef CONFIG_MACH_H6300
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H6300
+# endif
+# define machine_is_h6300()	(machine_arch_type == MACH_TYPE_H6300)
+#else
+# define machine_is_h6300()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RZ1700
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RZ1700
+# endif
+# define machine_is_rz1700()	(machine_arch_type == MACH_TYPE_RZ1700)
+#else
+# define machine_is_rz1700()	(0)
+#endif
+
+#ifdef CONFIG_MACH_A716
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_A716
+# endif
+# define machine_is_a716()	(machine_arch_type == MACH_TYPE_A716)
+#else
+# define machine_is_a716()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESTK2440A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESTK2440A
+# endif
+# define machine_is_estk2440a()	(machine_arch_type == MACH_TYPE_ESTK2440A)
+#else
+# define machine_is_estk2440a()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ATWIXP425
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ATWIXP425
+# endif
+# define machine_is_atwixp425()	(machine_arch_type == MACH_TYPE_ATWIXP425)
+#else
+# define machine_is_atwixp425()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSB336
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB336
+# endif
+# define machine_is_csb336()	(machine_arch_type == MACH_TYPE_CSB336)
+#else
+# define machine_is_csb336()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RIRM2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RIRM2
+# endif
+# define machine_is_rirm2()	(machine_arch_type == MACH_TYPE_RIRM2)
+#else
+# define machine_is_rirm2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CX23518
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CX23518
+# endif
+# define machine_is_cx23518()	(machine_arch_type == MACH_TYPE_CX23518)
+#else
+# define machine_is_cx23518()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CX2351X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CX2351X
+# endif
+# define machine_is_cx2351x()	(machine_arch_type == MACH_TYPE_CX2351X)
+#else
+# define machine_is_cx2351x()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COMPUTIME
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COMPUTIME
+# endif
+# define machine_is_computime()	(machine_arch_type == MACH_TYPE_COMPUTIME)
+#else
+# define machine_is_computime()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IZARUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IZARUS
+# endif
+# define machine_is_izarus()	(machine_arch_type == MACH_TYPE_IZARUS)
+#else
+# define machine_is_izarus()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RTS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RTS
+# endif
+# define machine_is_pxa_rts()	(machine_arch_type == MACH_TYPE_RTS)
+#else
+# define machine_is_pxa_rts()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SE5100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SE5100
+# endif
+# define machine_is_se5100()	(machine_arch_type == MACH_TYPE_SE5100)
+#else
+# define machine_is_se5100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_S3C2510
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S3C2510
+# endif
+# define machine_is_s3c2510()	(machine_arch_type == MACH_TYPE_S3C2510)
+#else
+# define machine_is_s3c2510()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSB437TL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB437TL
+# endif
+# define machine_is_csb437tl()	(machine_arch_type == MACH_TYPE_CSB437TL)
+#else
+# define machine_is_csb437tl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SLAUSON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SLAUSON
+# endif
+# define machine_is_slauson()	(machine_arch_type == MACH_TYPE_SLAUSON)
+#else
+# define machine_is_slauson()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PEARLRIVER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PEARLRIVER
+# endif
+# define machine_is_pearlriver()	(machine_arch_type == MACH_TYPE_PEARLRIVER)
+#else
+# define machine_is_pearlriver()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TDC_P210
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TDC_P210
+# endif
+# define machine_is_tdc_p210()	(machine_arch_type == MACH_TYPE_TDC_P210)
+#else
+# define machine_is_tdc_p210()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SG580
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SG580
+# endif
+# define machine_is_sg580()	(machine_arch_type == MACH_TYPE_SG580)
+#else
+# define machine_is_sg580()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WRSBCARM7
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WRSBCARM7
+# endif
+# define machine_is_wrsbcarm7()	(machine_arch_type == MACH_TYPE_WRSBCARM7)
+#else
+# define machine_is_wrsbcarm7()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IPD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IPD
+# endif
+# define machine_is_ipd()	(machine_arch_type == MACH_TYPE_IPD)
+#else
+# define machine_is_ipd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PXA_DNP2110
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_DNP2110
+# endif
+# define machine_is_pxa_dnp2110()	(machine_arch_type == MACH_TYPE_PXA_DNP2110)
+#else
+# define machine_is_pxa_dnp2110()	(0)
+#endif
+
+#ifdef CONFIG_MACH_XAENIAX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XAENIAX
+# endif
+# define machine_is_xaeniax()	(machine_arch_type == MACH_TYPE_XAENIAX)
+#else
+# define machine_is_xaeniax()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SOMN4250
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SOMN4250
+# endif
+# define machine_is_somn4250()	(machine_arch_type == MACH_TYPE_SOMN4250)
+#else
+# define machine_is_somn4250()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PLEB2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PLEB2
+# endif
+# define machine_is_pleb2()	(machine_arch_type == MACH_TYPE_PLEB2)
+#else
+# define machine_is_pleb2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CORNWALLIS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CORNWALLIS
+# endif
+# define machine_is_cornwallis()	(machine_arch_type == MACH_TYPE_CORNWALLIS)
+#else
+# define machine_is_cornwallis()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GURNEY_DRV
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GURNEY_DRV
+# endif
+# define machine_is_gurney_drv()	(machine_arch_type == MACH_TYPE_GURNEY_DRV)
+#else
+# define machine_is_gurney_drv()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CHAFFEE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CHAFFEE
+# endif
+# define machine_is_chaffee()	(machine_arch_type == MACH_TYPE_CHAFFEE)
+#else
+# define machine_is_chaffee()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RMS101
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RMS101
+# endif
+# define machine_is_rms101()	(machine_arch_type == MACH_TYPE_RMS101)
+#else
+# define machine_is_rms101()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RX3715
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RX3715
+# endif
+# define machine_is_rx3715()	(machine_arch_type == MACH_TYPE_RX3715)
+#else
+# define machine_is_rx3715()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SWIFT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SWIFT
+# endif
+# define machine_is_swift()	(machine_arch_type == MACH_TYPE_SWIFT)
+#else
+# define machine_is_swift()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ROVERP7
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ROVERP7
+# endif
+# define machine_is_roverp7()	(machine_arch_type == MACH_TYPE_ROVERP7)
+#else
+# define machine_is_roverp7()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PR818S
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PR818S
+# endif
+# define machine_is_pr818s()	(machine_arch_type == MACH_TYPE_PR818S)
+#else
+# define machine_is_pr818s()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TRXPRO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TRXPRO
+# endif
+# define machine_is_trxpro()	(machine_arch_type == MACH_TYPE_TRXPRO)
+#else
+# define machine_is_trxpro()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NSLU2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NSLU2
+# endif
+# define machine_is_nslu2()	(machine_arch_type == MACH_TYPE_NSLU2)
+#else
+# define machine_is_nslu2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_E400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_E400
+# endif
+# define machine_is_e400()	(machine_arch_type == MACH_TYPE_E400)
+#else
+# define machine_is_e400()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TRAB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TRAB
+# endif
+# define machine_is_trab()	(machine_arch_type == MACH_TYPE_TRAB)
+#else
+# define machine_is_trab()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CMC_PU2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CMC_PU2
+# endif
+# define machine_is_cmc_pu2()	(machine_arch_type == MACH_TYPE_CMC_PU2)
+#else
+# define machine_is_cmc_pu2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FULCRUM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FULCRUM
+# endif
+# define machine_is_fulcrum()	(machine_arch_type == MACH_TYPE_FULCRUM)
+#else
+# define machine_is_fulcrum()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NETGATE42X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETGATE42X
+# endif
+# define machine_is_netgate42x()	(machine_arch_type == MACH_TYPE_NETGATE42X)
+#else
+# define machine_is_netgate42x()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STR710
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STR710
+# endif
+# define machine_is_str710()	(machine_arch_type == MACH_TYPE_STR710)
+#else
+# define machine_is_str710()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IXDPG425
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDPG425
+# endif
+# define machine_is_ixdpg425()	(machine_arch_type == MACH_TYPE_IXDPG425)
+#else
+# define machine_is_ixdpg425()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TOMTOMGO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOMTOMGO
+# endif
+# define machine_is_tomtomgo()	(machine_arch_type == MACH_TYPE_TOMTOMGO)
+#else
+# define machine_is_tomtomgo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VERSATILE_AB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VERSATILE_AB
+# endif
+# define machine_is_versatile_ab()	(machine_arch_type == MACH_TYPE_VERSATILE_AB)
+#else
+# define machine_is_versatile_ab()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EDB9307
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EDB9307
+# endif
+# define machine_is_edb9307()	(machine_arch_type == MACH_TYPE_EDB9307)
+#else
+# define machine_is_edb9307()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SG565
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SG565
+# endif
+# define machine_is_sg565()	(machine_arch_type == MACH_TYPE_SG565)
+#else
+# define machine_is_sg565()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LPD79524
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPD79524
+# endif
+# define machine_is_lpd79524()	(machine_arch_type == MACH_TYPE_LPD79524)
+#else
+# define machine_is_lpd79524()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LPD79525
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPD79525
+# endif
+# define machine_is_lpd79525()	(machine_arch_type == MACH_TYPE_LPD79525)
+#else
+# define machine_is_lpd79525()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RMS100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RMS100
+# endif
+# define machine_is_rms100()	(machine_arch_type == MACH_TYPE_RMS100)
+#else
+# define machine_is_rms100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KB9200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KB9200
+# endif
+# define machine_is_kb9200()	(machine_arch_type == MACH_TYPE_KB9200)
+#else
+# define machine_is_kb9200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SX1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SX1
+# endif
+# define machine_is_sx1()	(machine_arch_type == MACH_TYPE_SX1)
+#else
+# define machine_is_sx1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HMS39C7092
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HMS39C7092
+# endif
+# define machine_is_hms39c7092()	(machine_arch_type == MACH_TYPE_HMS39C7092)
+#else
+# define machine_is_hms39c7092()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMADILLO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMADILLO
+# endif
+# define machine_is_armadillo()	(machine_arch_type == MACH_TYPE_ARMADILLO)
+#else
+# define machine_is_armadillo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IPCU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IPCU
+# endif
+# define machine_is_ipcu()	(machine_arch_type == MACH_TYPE_IPCU)
+#else
+# define machine_is_ipcu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LOOX720
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LOOX720
+# endif
+# define machine_is_loox720()	(machine_arch_type == MACH_TYPE_LOOX720)
+#else
+# define machine_is_loox720()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IXDP465
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP465
+# endif
+# define machine_is_ixdp465()	(machine_arch_type == MACH_TYPE_IXDP465)
+#else
+# define machine_is_ixdp465()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IXDP2351
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDP2351
+# endif
+# define machine_is_ixdp2351()	(machine_arch_type == MACH_TYPE_IXDP2351)
+#else
+# define machine_is_ixdp2351()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ADSVIX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSVIX
+# endif
+# define machine_is_adsvix()	(machine_arch_type == MACH_TYPE_ADSVIX)
+#else
+# define machine_is_adsvix()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DM270
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DM270
+# endif
+# define machine_is_dm270()	(machine_arch_type == MACH_TYPE_DM270)
+#else
+# define machine_is_dm270()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SOCLTPLUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SOCLTPLUS
+# endif
+# define machine_is_socltplus()	(machine_arch_type == MACH_TYPE_SOCLTPLUS)
+#else
+# define machine_is_socltplus()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ECIA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ECIA
+# endif
+# define machine_is_ecia()	(machine_arch_type == MACH_TYPE_ECIA)
+#else
+# define machine_is_ecia()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CM4008
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CM4008
+# endif
+# define machine_is_cm4008()	(machine_arch_type == MACH_TYPE_CM4008)
+#else
+# define machine_is_cm4008()	(0)
+#endif
+
+#ifdef CONFIG_MACH_P2001
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_P2001
+# endif
+# define machine_is_p2001()	(machine_arch_type == MACH_TYPE_P2001)
+#else
+# define machine_is_p2001()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TWISTER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TWISTER
+# endif
+# define machine_is_twister()	(machine_arch_type == MACH_TYPE_TWISTER)
+#else
+# define machine_is_twister()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MUDSHARK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MUDSHARK
+# endif
+# define machine_is_mudshark()	(machine_arch_type == MACH_TYPE_MUDSHARK)
+#else
+# define machine_is_mudshark()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HB2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HB2
+# endif
+# define machine_is_hb2()	(machine_arch_type == MACH_TYPE_HB2)
+#else
+# define machine_is_hb2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IQ80332
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IQ80332
+# endif
+# define machine_is_iq80332()	(machine_arch_type == MACH_TYPE_IQ80332)
+#else
+# define machine_is_iq80332()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SENDT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SENDT
+# endif
+# define machine_is_sendt()	(machine_arch_type == MACH_TYPE_SENDT)
+#else
+# define machine_is_sendt()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX2JAZZ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX2JAZZ
+# endif
+# define machine_is_mx2jazz()	(machine_arch_type == MACH_TYPE_MX2JAZZ)
+#else
+# define machine_is_mx2jazz()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MULTIIO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MULTIIO
+# endif
+# define machine_is_multiio()	(machine_arch_type == MACH_TYPE_MULTIIO)
+#else
+# define machine_is_multiio()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HRDISPLAY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HRDISPLAY
+# endif
+# define machine_is_hrdisplay()	(machine_arch_type == MACH_TYPE_HRDISPLAY)
+#else
+# define machine_is_hrdisplay()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SCMA11BB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SCMA11BB
+# endif
+# define machine_is_scma11bb()	(machine_arch_type == MACH_TYPE_SCMA11BB)
+#else
+# define machine_is_scma11bb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TRIZEPS3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TRIZEPS3
+# endif
+# define machine_is_trizeps3()	(machine_arch_type == MACH_TYPE_TRIZEPS3)
+#else
+# define machine_is_trizeps3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZEFEERDZA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZEFEERDZA
+# endif
+# define machine_is_zefeerdza()	(machine_arch_type == MACH_TYPE_ZEFEERDZA)
+#else
+# define machine_is_zefeerdza()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZEFEERDZB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZEFEERDZB
+# endif
+# define machine_is_zefeerdzb()	(machine_arch_type == MACH_TYPE_ZEFEERDZB)
+#else
+# define machine_is_zefeerdzb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZEFEERDZG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZEFEERDZG
+# endif
+# define machine_is_zefeerdzg()	(machine_arch_type == MACH_TYPE_ZEFEERDZG)
+#else
+# define machine_is_zefeerdzg()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZEFEERDZN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZEFEERDZN
+# endif
+# define machine_is_zefeerdzn()	(machine_arch_type == MACH_TYPE_ZEFEERDZN)
+#else
+# define machine_is_zefeerdzn()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZEFEERDZQ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZEFEERDZQ
+# endif
+# define machine_is_zefeerdzq()	(machine_arch_type == MACH_TYPE_ZEFEERDZQ)
+#else
+# define machine_is_zefeerdzq()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GTWX5715
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GTWX5715
+# endif
+# define machine_is_gtwx5715()	(machine_arch_type == MACH_TYPE_GTWX5715)
+#else
+# define machine_is_gtwx5715()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ASTRO_JACK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ASTRO_JACK
+# endif
+# define machine_is_astro_jack()	(machine_arch_type == MACH_TYPE_ASTRO_JACK)
+#else
+# define machine_is_astro_jack()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TIP03
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TIP03
+# endif
+# define machine_is_tip03()	(machine_arch_type == MACH_TYPE_TIP03)
+#else
+# define machine_is_tip03()	(0)
+#endif
+
+#ifdef CONFIG_MACH_A9200EC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_A9200EC
+# endif
+# define machine_is_a9200ec()	(machine_arch_type == MACH_TYPE_A9200EC)
+#else
+# define machine_is_a9200ec()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PNX0105
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PNX0105
+# endif
+# define machine_is_pnx0105()	(machine_arch_type == MACH_TYPE_PNX0105)
+#else
+# define machine_is_pnx0105()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ADCPOECPU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADCPOECPU
+# endif
+# define machine_is_adcpoecpu()	(machine_arch_type == MACH_TYPE_ADCPOECPU)
+#else
+# define machine_is_adcpoecpu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSB637
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB637
+# endif
+# define machine_is_csb637()	(machine_arch_type == MACH_TYPE_CSB637)
+#else
+# define machine_is_csb637()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ML69Q6203
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ML69Q6203
+# endif
+# define machine_is_ml69q6203()	(machine_arch_type == MACH_TYPE_ML69Q6203)
+#else
+# define machine_is_ml69q6203()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MB9200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MB9200
+# endif
+# define machine_is_mb9200()	(machine_arch_type == MACH_TYPE_MB9200)
+#else
+# define machine_is_mb9200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KULUN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KULUN
+# endif
+# define machine_is_kulun()	(machine_arch_type == MACH_TYPE_KULUN)
+#else
+# define machine_is_kulun()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SNAPPER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SNAPPER
+# endif
+# define machine_is_snapper()	(machine_arch_type == MACH_TYPE_SNAPPER)
+#else
+# define machine_is_snapper()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OPTIMA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OPTIMA
+# endif
+# define machine_is_optima()	(machine_arch_type == MACH_TYPE_OPTIMA)
+#else
+# define machine_is_optima()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DLHSBC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DLHSBC
+# endif
+# define machine_is_dlhsbc()	(machine_arch_type == MACH_TYPE_DLHSBC)
+#else
+# define machine_is_dlhsbc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_X30
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_X30
+# endif
+# define machine_is_x30()	(machine_arch_type == MACH_TYPE_X30)
+#else
+# define machine_is_x30()	(0)
+#endif
+
+#ifdef CONFIG_MACH_N30
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_N30
+# endif
+# define machine_is_n30()	(machine_arch_type == MACH_TYPE_N30)
+#else
+# define machine_is_n30()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MANGA_KS8695
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MANGA_KS8695
+# endif
+# define machine_is_manga_ks8695()	(machine_arch_type == MACH_TYPE_MANGA_KS8695)
+#else
+# define machine_is_manga_ks8695()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AJAX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AJAX
+# endif
+# define machine_is_ajax()	(machine_arch_type == MACH_TYPE_AJAX)
+#else
+# define machine_is_ajax()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NEC_MP900
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEC_MP900
+# endif
+# define machine_is_nec_mp900()	(machine_arch_type == MACH_TYPE_NEC_MP900)
+#else
+# define machine_is_nec_mp900()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VVTK1000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VVTK1000
+# endif
+# define machine_is_vvtk1000()	(machine_arch_type == MACH_TYPE_VVTK1000)
+#else
+# define machine_is_vvtk1000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KAFA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KAFA
+# endif
+# define machine_is_kafa()	(machine_arch_type == MACH_TYPE_KAFA)
+#else
+# define machine_is_kafa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VVTK3000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VVTK3000
+# endif
+# define machine_is_vvtk3000()	(machine_arch_type == MACH_TYPE_VVTK3000)
+#else
+# define machine_is_vvtk3000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PIMX1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PIMX1
+# endif
+# define machine_is_pimx1()	(machine_arch_type == MACH_TYPE_PIMX1)
+#else
+# define machine_is_pimx1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OLLIE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OLLIE
+# endif
+# define machine_is_ollie()	(machine_arch_type == MACH_TYPE_OLLIE)
+#else
+# define machine_is_ollie()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SKYMAX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SKYMAX
+# endif
+# define machine_is_skymax()	(machine_arch_type == MACH_TYPE_SKYMAX)
+#else
+# define machine_is_skymax()	(0)
+#endif
+
+#ifdef CONFIG_MACH_JAZZ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_JAZZ
+# endif
+# define machine_is_jazz()	(machine_arch_type == MACH_TYPE_JAZZ)
+#else
+# define machine_is_jazz()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TEL_T3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TEL_T3
+# endif
+# define machine_is_tel_t3()	(machine_arch_type == MACH_TYPE_TEL_T3)
+#else
+# define machine_is_tel_t3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AISINO_FCR255
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AISINO_FCR255
+# endif
+# define machine_is_aisino_fcr255()	(machine_arch_type == MACH_TYPE_AISINO_FCR255)
+#else
+# define machine_is_aisino_fcr255()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BTWEB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BTWEB
+# endif
+# define machine_is_btweb()	(machine_arch_type == MACH_TYPE_BTWEB)
+#else
+# define machine_is_btweb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DBG_LH79520
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DBG_LH79520
+# endif
+# define machine_is_dbg_lh79520()	(machine_arch_type == MACH_TYPE_DBG_LH79520)
+#else
+# define machine_is_dbg_lh79520()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CM41XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CM41XX
+# endif
+# define machine_is_cm41xx()	(machine_arch_type == MACH_TYPE_CM41XX)
+#else
+# define machine_is_cm41xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TS72XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TS72XX
+# endif
+# define machine_is_ts72xx()	(machine_arch_type == MACH_TYPE_TS72XX)
+#else
+# define machine_is_ts72xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NGGPXA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NGGPXA
+# endif
+# define machine_is_nggpxa()	(machine_arch_type == MACH_TYPE_NGGPXA)
+#else
+# define machine_is_nggpxa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSB535
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB535
+# endif
+# define machine_is_csb535()	(machine_arch_type == MACH_TYPE_CSB535)
+#else
+# define machine_is_csb535()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSB536
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB536
+# endif
+# define machine_is_csb536()	(machine_arch_type == MACH_TYPE_CSB536)
+#else
+# define machine_is_csb536()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PXA_TRAKPOD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PXA_TRAKPOD
+# endif
+# define machine_is_pxa_trakpod()	(machine_arch_type == MACH_TYPE_PXA_TRAKPOD)
+#else
+# define machine_is_pxa_trakpod()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PRAXIS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PRAXIS
+# endif
+# define machine_is_praxis()	(machine_arch_type == MACH_TYPE_PRAXIS)
+#else
+# define machine_is_praxis()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LH75411
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LH75411
+# endif
+# define machine_is_lh75411()	(machine_arch_type == MACH_TYPE_LH75411)
+#else
+# define machine_is_lh75411()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OTOM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OTOM
+# endif
+# define machine_is_otom()	(machine_arch_type == MACH_TYPE_OTOM)
+#else
+# define machine_is_otom()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NEXCODER_2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NEXCODER_2440
+# endif
+# define machine_is_nexcoder_2440()	(machine_arch_type == MACH_TYPE_NEXCODER_2440)
+#else
+# define machine_is_nexcoder_2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LOOX410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LOOX410
+# endif
+# define machine_is_loox410()	(machine_arch_type == MACH_TYPE_LOOX410)
+#else
+# define machine_is_loox410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WESTLAKE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WESTLAKE
+# endif
+# define machine_is_westlake()	(machine_arch_type == MACH_TYPE_WESTLAKE)
+#else
+# define machine_is_westlake()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NSB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NSB
+# endif
+# define machine_is_nsb()	(machine_arch_type == MACH_TYPE_NSB)
+#else
+# define machine_is_nsb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESL_SARVA_STN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESL_SARVA_STN
+# endif
+# define machine_is_esl_sarva_stn()	(machine_arch_type == MACH_TYPE_ESL_SARVA_STN)
+#else
+# define machine_is_esl_sarva_stn()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESL_SARVA_TFT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESL_SARVA_TFT
+# endif
+# define machine_is_esl_sarva_tft()	(machine_arch_type == MACH_TYPE_ESL_SARVA_TFT)
+#else
+# define machine_is_esl_sarva_tft()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESL_SARVA_IAD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESL_SARVA_IAD
+# endif
+# define machine_is_esl_sarva_iad()	(machine_arch_type == MACH_TYPE_ESL_SARVA_IAD)
+#else
+# define machine_is_esl_sarva_iad()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ESL_SARVA_ACC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ESL_SARVA_ACC
+# endif
+# define machine_is_esl_sarva_acc()	(machine_arch_type == MACH_TYPE_ESL_SARVA_ACC)
+#else
+# define machine_is_esl_sarva_acc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TYPHOON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TYPHOON
+# endif
+# define machine_is_typhoon()	(machine_arch_type == MACH_TYPE_TYPHOON)
+#else
+# define machine_is_typhoon()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CNAV
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CNAV
+# endif
+# define machine_is_cnav()	(machine_arch_type == MACH_TYPE_CNAV)
+#else
+# define machine_is_cnav()	(0)
+#endif
+
+#ifdef CONFIG_MACH_A730
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_A730
+# endif
+# define machine_is_a730()	(machine_arch_type == MACH_TYPE_A730)
+#else
+# define machine_is_a730()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NETSTAR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NETSTAR
+# endif
+# define machine_is_netstar()	(machine_arch_type == MACH_TYPE_NETSTAR)
+#else
+# define machine_is_netstar()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PHASEFALE_SUPERCON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PHASEFALE_SUPERCON
+# endif
+# define machine_is_supercon()	(machine_arch_type == MACH_TYPE_PHASEFALE_SUPERCON)
+#else
+# define machine_is_supercon()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SHIVA1100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHIVA1100
+# endif
+# define machine_is_shiva1100()	(machine_arch_type == MACH_TYPE_SHIVA1100)
+#else
+# define machine_is_shiva1100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ETEXSC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ETEXSC
+# endif
+# define machine_is_etexsc()	(machine_arch_type == MACH_TYPE_ETEXSC)
+#else
+# define machine_is_etexsc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IXDPG465
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IXDPG465
+# endif
+# define machine_is_ixdpg465()	(machine_arch_type == MACH_TYPE_IXDPG465)
+#else
+# define machine_is_ixdpg465()	(0)
+#endif
+
+#ifdef CONFIG_MACH_A9M2410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_A9M2410
+# endif
+# define machine_is_a9m2410()	(machine_arch_type == MACH_TYPE_A9M2410)
+#else
+# define machine_is_a9m2410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_A9M2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_A9M2440
+# endif
+# define machine_is_a9m2440()	(machine_arch_type == MACH_TYPE_A9M2440)
+#else
+# define machine_is_a9m2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_A9M9750
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_A9M9750
+# endif
+# define machine_is_a9m9750()	(machine_arch_type == MACH_TYPE_A9M9750)
+#else
+# define machine_is_a9m9750()	(0)
+#endif
+
+#ifdef CONFIG_MACH_A9M9360
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_A9M9360
+# endif
+# define machine_is_a9m9360()	(machine_arch_type == MACH_TYPE_A9M9360)
+#else
+# define machine_is_a9m9360()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UNC90
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UNC90
+# endif
+# define machine_is_unc90()	(machine_arch_type == MACH_TYPE_UNC90)
+#else
+# define machine_is_unc90()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ECO920
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ECO920
+# endif
+# define machine_is_eco920()	(machine_arch_type == MACH_TYPE_ECO920)
+#else
+# define machine_is_eco920()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SATVIEW
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SATVIEW
+# endif
+# define machine_is_satview()	(machine_arch_type == MACH_TYPE_SATVIEW)
+#else
+# define machine_is_satview()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ROADRUNNER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ROADRUNNER
+# endif
+# define machine_is_roadrunner()	(machine_arch_type == MACH_TYPE_ROADRUNNER)
+#else
+# define machine_is_roadrunner()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91RM9200EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91RM9200EK
+# endif
+# define machine_is_at91rm9200ek()	(machine_arch_type == MACH_TYPE_AT91RM9200EK)
+#else
+# define machine_is_at91rm9200ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GP32
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GP32
+# endif
+# define machine_is_gp32()	(machine_arch_type == MACH_TYPE_GP32)
+#else
+# define machine_is_gp32()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GEM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GEM
+# endif
+# define machine_is_gem()	(machine_arch_type == MACH_TYPE_GEM)
+#else
+# define machine_is_gem()	(0)
+#endif
+
+#ifdef CONFIG_MACH_I858
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_I858
+# endif
+# define machine_is_i858()	(machine_arch_type == MACH_TYPE_I858)
+#else
+# define machine_is_i858()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HX2750
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HX2750
+# endif
+# define machine_is_hx2750()	(machine_arch_type == MACH_TYPE_HX2750)
+#else
+# define machine_is_hx2750()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZEUSEVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZEUSEVB
+# endif
+# define machine_is_zeusevb()	(machine_arch_type == MACH_TYPE_ZEUSEVB)
+#else
+# define machine_is_zeusevb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_P700
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_P700
+# endif
+# define machine_is_p700()	(machine_arch_type == MACH_TYPE_P700)
+#else
+# define machine_is_p700()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CPE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CPE
+# endif
+# define machine_is_cpe()	(machine_arch_type == MACH_TYPE_CPE)
+#else
+# define machine_is_cpe()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPITZ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPITZ
+# endif
+# define machine_is_spitz()	(machine_arch_type == MACH_TYPE_SPITZ)
+#else
+# define machine_is_spitz()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NIMBRA340
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NIMBRA340
+# endif
+# define machine_is_nimbra340()	(machine_arch_type == MACH_TYPE_NIMBRA340)
+#else
+# define machine_is_nimbra340()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LPC22XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPC22XX
+# endif
+# define machine_is_lpc22xx()	(machine_arch_type == MACH_TYPE_LPC22XX)
+#else
+# define machine_is_lpc22xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COMET3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COMET3
+# endif
+# define machine_is_omap_comet3()	(machine_arch_type == MACH_TYPE_COMET3)
+#else
+# define machine_is_omap_comet3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COMET4
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COMET4
+# endif
+# define machine_is_omap_comet4()	(machine_arch_type == MACH_TYPE_COMET4)
+#else
+# define machine_is_omap_comet4()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSB625
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB625
+# endif
+# define machine_is_csb625()	(machine_arch_type == MACH_TYPE_CSB625)
+#else
+# define machine_is_csb625()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FORTUNET2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FORTUNET2
+# endif
+# define machine_is_fortunet2()	(machine_arch_type == MACH_TYPE_FORTUNET2)
+#else
+# define machine_is_fortunet2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_S5H2200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S5H2200
+# endif
+# define machine_is_s5h2200()	(machine_arch_type == MACH_TYPE_S5H2200)
+#else
+# define machine_is_s5h2200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OPTORM920
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OPTORM920
+# endif
+# define machine_is_optorm920()	(machine_arch_type == MACH_TYPE_OPTORM920)
+#else
+# define machine_is_optorm920()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ADSBITSYXB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSBITSYXB
+# endif
+# define machine_is_adsbitsyxb()	(machine_arch_type == MACH_TYPE_ADSBITSYXB)
+#else
+# define machine_is_adsbitsyxb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ADSSPHERE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSSPHERE
+# endif
+# define machine_is_adssphere()	(machine_arch_type == MACH_TYPE_ADSSPHERE)
+#else
+# define machine_is_adssphere()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ADSPORTAL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSPORTAL
+# endif
+# define machine_is_adsportal()	(machine_arch_type == MACH_TYPE_ADSPORTAL)
+#else
+# define machine_is_adsportal()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LN2410SBC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LN2410SBC
+# endif
+# define machine_is_ln2410sbc()	(machine_arch_type == MACH_TYPE_LN2410SBC)
+#else
+# define machine_is_ln2410sbc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CB3RUFC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CB3RUFC
+# endif
+# define machine_is_cb3rufc()	(machine_arch_type == MACH_TYPE_CB3RUFC)
+#else
+# define machine_is_cb3rufc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MP2USB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MP2USB
+# endif
+# define machine_is_mp2usb()	(machine_arch_type == MACH_TYPE_MP2USB)
+#else
+# define machine_is_mp2usb()	(0)
+#endif
+
+/*
+ * These have not yet been registered
+ */
+/* #define MACH_TYPE_367                  <<not registered>> */
+#define machine_is_esl_wireless_tab()	(0)
+
+#ifndef machine_arch_type
+#define machine_arch_type	__machine_arch_type
+#endif
+
+#endif
+
+#ifdef CONFIG_MACH_WMT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WMT
+# endif
+# define machine_is_wmt()	(machine_arch_type == MACH_TYPE_WMT)
+#else
+# define machine_is_wmt()	(0)
+#endif
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
new file mode 100755
index 0000000..c3b2afd
--- /dev/null
+++ b/include/asm-arm/memory.h
@@ -0,0 +1,137 @@
+/*
+ *  linux/include/asm-arm/memory.h
+ *
+ *  Copyright (C) 2000-2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Note: this file should not be included by non-asm/.h files
+ */
+#ifndef __ASM_ARM_MEMORY_H
+#define __ASM_ARM_MEMORY_H
+
+#if 0	/* XXX###XXX */
+
+#include <linux/config.h>
+#include <asm/arch/memory.h>
+
+/*
+ * PFNs are used to describe any physical page; this means
+ * PFN 0 == physical address 0.
+ *
+ * This is the PFN of the first RAM page in the kernel
+ * direct-mapped view.  We assume this is the first page
+ * of RAM in the mem_map as well.
+ */
+#define PHYS_PFN_OFFSET	(PHYS_OFFSET >> PAGE_SHIFT)
+
+/*
+ * These are *only* valid on the kernel direct mapped RAM memory.
+ */
+static inline unsigned long virt_to_phys(void *x)
+{
+	return __virt_to_phys((unsigned long)(x));
+}
+
+static inline void *phys_to_virt(unsigned long x)
+{
+	return (void *)(__phys_to_virt((unsigned long)(x)));
+}
+
+#define __pa(x)			__virt_to_phys((unsigned long)(x))
+#define __va(x)			((void *)__phys_to_virt((unsigned long)(x)))
+
+/*
+ * Virtual <-> DMA view memory address translations
+ * Again, these are *only* valid on the kernel direct mapped RAM
+ * memory.  Use of these is *depreciated*.
+ */
+#define virt_to_bus(x)		(__virt_to_bus((unsigned long)(x)))
+#define bus_to_virt(x)		((void *)(__bus_to_virt((unsigned long)(x))))
+
+/*
+ * Conversion between a struct page and a physical address.
+ *
+ * Note: when converting an unknown physical address to a
+ * struct page, the resulting pointer must be validated
+ * using VALID_PAGE().  It must return an invalid struct page
+ * for any physical address not corresponding to a system
+ * RAM address.
+ *
+ *  page_to_pfn(page)	convert a struct page * to a PFN number
+ *  pfn_to_page(pfn)	convert a _valid_ PFN number to struct page *
+ *  pfn_valid(pfn)	indicates whether a PFN number is valid
+ *
+ *  virt_to_page(k)	convert a _valid_ virtual address to struct page *
+ *  virt_addr_valid(k)	indicates whether a virtual address is valid
+ */
+#ifndef CONFIG_DISCONTIGMEM
+
+#define page_to_pfn(page)	(((page) - mem_map) + PHYS_PFN_OFFSET)
+#define pfn_to_page(pfn)	((mem_map + (pfn)) - PHYS_PFN_OFFSET)
+#define pfn_valid(pfn)		((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
+
+#define virt_to_page(kaddr)	(pfn_to_page(__pa(kaddr) >> PAGE_SHIFT))
+#define virt_addr_valid(kaddr)	((kaddr) >= PAGE_OFFSET && (kaddr) < (unsigned long)high_memory)
+
+#define PHYS_TO_NID(addr)	(0)
+
+#define VALID_PAGE(page)	((page - mem_map) < max_mapnr)
+
+#else
+
+/*
+ * This is more complex.  We have a set of mem_map arrays spread
+ * around in memory.
+ */
+#define page_to_pfn(page)					\
+	(((page) - page_zone(page)->zone_mem_map)		\
+	  + (page_zone(page)->zone_start_paddr >> PAGE_SHIFT))
+
+#define pfn_to_page(pfn)					\
+	(PFN_TO_MAPBASE(pfn) + LOCAL_MAP_NR((pfn) << PAGE_SHIFT))
+
+#define pfn_valid(pfn)						\
+  ({								\
+	unsigned int node = PFN_TO_NID(pfn);			\
+	struct pglist_data *nd = NODE_DATA(node);		\
+	((node < NR_NODES) &&					\
+	 ((pfn - (nd->node_start_paddr >> PAGE_SHIFT)) < nd->node_size));\
+   })
+
+#define virt_to_page(kaddr)					\
+	(ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
+
+#define virt_addr_valid(kaddr)	(KVADDR_TO_NID(kaddr) < NR_NODES)
+
+/*
+ * Common discontigmem stuff.
+ *  PHYS_TO_NID is used by the ARM kernel/setup.c
+ */
+#define PHYS_TO_NID(addr)	PFN_TO_NID((addr) >> PAGE_SHIFT)
+
+/*
+ * 2.4 compatibility
+ *
+ * VALID_PAGE returns a non-zero value if given page pointer is valid.
+ * This assumes all node's mem_maps are stored within the node they
+ * refer to.  This is actually inherently buggy.
+ */
+#define VALID_PAGE(page) \
+({ unsigned int node = KVADDR_TO_NID(page); \
+   ((node < NR_NODES) && \
+     ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size)); \
+})
+
+#endif
+
+/*
+ * We should really eliminate virt_to_bus() here - it's depreciated.
+ */
+#define page_to_bus(page)	(virt_to_bus(page_address(page)))
+
+#endif	/* XXX###XXX */
+
+#endif	/* __ASM_ARM_MEMORY_H */
diff --git a/include/asm-arm/posix_types.h b/include/asm-arm/posix_types.h
new file mode 100755
index 0000000..c412486
--- /dev/null
+++ b/include/asm-arm/posix_types.h
@@ -0,0 +1,79 @@
+/*
+ *  linux/include/asm-arm/posix_types.h
+ *
+ *  Copyright (C) 1996-1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ */
+#ifndef __ARCH_ARM_POSIX_TYPES_H
+#define __ARCH_ARM_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char *			__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+		(memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp)))
+
+#endif
+
+#endif
diff --git a/include/asm-arm/proc-armv/domain.h b/include/asm-arm/proc-armv/domain.h
new file mode 100755
index 0000000..aadc831
--- /dev/null
+++ b/include/asm-arm/proc-armv/domain.h
@@ -0,0 +1,50 @@
+/*
+ *  linux/include/asm-arm/proc-armv/domain.h
+ *
+ *  Copyright (C) 1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PROC_DOMAIN_H
+#define __ASM_PROC_DOMAIN_H
+
+/*
+ * Domain numbers
+ *
+ *  DOMAIN_IO     - domain 2 includes all IO only
+ *  DOMAIN_KERNEL - domain 1 includes all kernel memory only
+ *  DOMAIN_USER   - domain 0 includes all user memory only
+ */
+#define DOMAIN_USER	0
+#define DOMAIN_KERNEL	1
+#define DOMAIN_TABLE	1
+#define DOMAIN_IO	2
+
+/*
+ * Domain types
+ */
+#define DOMAIN_NOACCESS	0
+#define DOMAIN_CLIENT	1
+#define DOMAIN_MANAGER	3
+
+#define domain_val(dom,type)	((type) << 2*(dom))
+
+#define set_domain(x)					\
+	do {						\
+	__asm__ __volatile__(				\
+	"mcr	p15, 0, %0, c3, c0	@ set domain"	\
+	  : : "r" (x));					\
+	} while (0)
+
+#define modify_domain(dom,type)				\
+	do {						\
+	unsigned int domain = current->thread.domain;	\
+	domain &= ~domain_val(dom, DOMAIN_MANAGER);	\
+	domain |= domain_val(dom, type);		\
+	current->thread.domain = domain;		\
+	set_domain(current->thread.domain);		\
+	} while (0)
+
+#endif
diff --git a/include/asm-arm/proc-armv/processor.h b/include/asm-arm/proc-armv/processor.h
new file mode 100755
index 0000000..5bfab7f
--- /dev/null
+++ b/include/asm-arm/proc-armv/processor.h
@@ -0,0 +1,74 @@
+/*
+ *  linux/include/asm-arm/proc-armv/processor.h
+ *
+ *  Copyright (C) 1996-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   20-09-1996	RMK	Created
+ *   26-09-1996	RMK	Added 'EXTRA_THREAD_STRUCT*'
+ *   28-09-1996	RMK	Moved start_thread into the processor dependencies
+ *   09-09-1998	PJB	Delete redundant `wp_works_ok'
+ *   30-05-1999	PJB	Save sl across context switches
+ *   31-07-1999	RMK	Added 'domain' stuff
+ */
+#ifndef __ASM_PROC_PROCESSOR_H
+#define __ASM_PROC_PROCESSOR_H
+
+#include <asm/proc/domain.h>
+
+#define KERNEL_STACK_SIZE	PAGE_SIZE
+
+struct context_save_struct {
+	unsigned long cpsr;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long sl;
+	unsigned long fp;
+	unsigned long pc;
+};
+
+#define INIT_CSS (struct context_save_struct){ SVC_MODE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+
+#define EXTRA_THREAD_STRUCT						\
+	unsigned int	domain;
+
+#define EXTRA_THREAD_STRUCT_INIT					\
+	domain:	  domain_val(DOMAIN_USER, DOMAIN_CLIENT) |		\
+		  domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) |		\
+		  domain_val(DOMAIN_IO, DOMAIN_CLIENT)
+
+#define start_thread(regs,pc,sp)					\
+({									\
+	unsigned long *stack = (unsigned long *)sp;			\
+	set_fs(USER_DS);						\
+	memzero(regs->uregs, sizeof(regs->uregs));			\
+	if (current->personality & ADDR_LIMIT_32BIT)			\
+		regs->ARM_cpsr = USR_MODE;				\
+	else								\
+		regs->ARM_cpsr = USR26_MODE;				\
+	regs->ARM_pc = pc;		/* pc */			\
+	regs->ARM_sp = sp;		/* sp */			\
+	regs->ARM_r2 = stack[2];	/* r2 (envp) */			\
+	regs->ARM_r1 = stack[1];	/* r1 (argv) */			\
+	regs->ARM_r0 = stack[0];	/* r0 (argc) */			\
+})
+
+#define KSTK_EIP(tsk)	(((unsigned long *)(4096+(unsigned long)(tsk)))[1019])
+#define KSTK_ESP(tsk)	(((unsigned long *)(4096+(unsigned long)(tsk)))[1017])
+
+/* Allocation and freeing of basic task resources. */
+/*
+ * NOTE! The task struct and the stack go together
+ */
+#define ll_alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
+#define ll_free_task_struct(p) free_pages((unsigned long)(p),1)
+
+#endif
diff --git a/include/asm-arm/proc-armv/ptrace.h b/include/asm-arm/proc-armv/ptrace.h
new file mode 100755
index 0000000..79cc644
--- /dev/null
+++ b/include/asm-arm/proc-armv/ptrace.h
@@ -0,0 +1,109 @@
+/*
+ *  linux/include/asm-arm/proc-armv/ptrace.h
+ *
+ *  Copyright (C) 1996-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PROC_PTRACE_H
+#define __ASM_PROC_PTRACE_H
+
+#include <linux/config.h>
+
+#define USR26_MODE	0x00
+#define FIQ26_MODE	0x01
+#define IRQ26_MODE	0x02
+#define SVC26_MODE	0x03
+#define USR_MODE	0x10
+#define FIQ_MODE	0x11
+#define IRQ_MODE	0x12
+#define SVC_MODE	0x13
+#define ABT_MODE	0x17
+#define UND_MODE	0x1b
+#define SYSTEM_MODE	0x1f
+#define MODE_MASK	0x1f
+#define T_BIT		0x20
+#define F_BIT		0x40
+#define I_BIT		0x80
+#define CC_V_BIT	(1 << 28)
+#define CC_C_BIT	(1 << 29)
+#define CC_Z_BIT	(1 << 30)
+#define CC_N_BIT	(1 << 31)
+#define PCMASK		0
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+struct pt_regs {
+	long uregs[18];
+};
+
+#define ARM_cpsr	uregs[16]
+#define ARM_pc		uregs[15]
+#define ARM_lr		uregs[14]
+#define ARM_sp		uregs[13]
+#define ARM_ip		uregs[12]
+#define ARM_fp		uregs[11]
+#define ARM_r10		uregs[10]
+#define ARM_r9		uregs[9]
+#define ARM_r8		uregs[8]
+#define ARM_r7		uregs[7]
+#define ARM_r6		uregs[6]
+#define ARM_r5		uregs[5]
+#define ARM_r4		uregs[4]
+#define ARM_r3		uregs[3]
+#define ARM_r2		uregs[2]
+#define ARM_r1		uregs[1]
+#define ARM_r0		uregs[0]
+#define ARM_ORIG_r0	uregs[17]
+
+#ifdef __KERNEL__
+
+#define user_mode(regs)	\
+	(((regs)->ARM_cpsr & 0xf) == 0)
+
+#ifdef CONFIG_ARM_THUMB
+#define thumb_mode(regs) \
+	(((regs)->ARM_cpsr & T_BIT))
+#else
+#define thumb_mode(regs) (0)
+#endif
+
+#define processor_mode(regs) \
+	((regs)->ARM_cpsr & MODE_MASK)
+
+#define interrupts_enabled(regs) \
+	(!((regs)->ARM_cpsr & I_BIT))
+
+#define fast_interrupts_enabled(regs) \
+	(!((regs)->ARM_cpsr & F_BIT))
+
+#define condition_codes(regs) \
+	((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT))
+
+/* Are the current registers suitable for user mode?
+ * (used to maintain security in signal handlers)
+ */
+static inline int valid_user_regs(struct pt_regs *regs)
+{
+	if ((regs->ARM_cpsr & 0xf) == 0 &&
+	    (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0)
+		return 1;
+
+	/*
+	 * Force CPSR to something logical...
+	 */
+	regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10);
+
+	return 0;
+}
+
+#endif	/* __KERNEL__ */
+
+#endif	/* __ASSEMBLY__ */
+
+#endif
diff --git a/include/asm-arm/proc-armv/system.h b/include/asm-arm/proc-armv/system.h
new file mode 100755
index 0000000..e7b0fe6
--- /dev/null
+++ b/include/asm-arm/proc-armv/system.h
@@ -0,0 +1,199 @@
+/*
+ *  linux/include/asm-arm/proc-armv/system.h
+ *
+ *  Copyright (C) 1996 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PROC_SYSTEM_H
+#define __ASM_PROC_SYSTEM_H
+
+#include <linux/config.h>
+
+#define set_cr(x)					\
+	__asm__ __volatile__(				\
+	"mcr	p15, 0, %0, c1, c0	@ set CR"	\
+	: : "r" (x))
+
+#define CR_M	(1 << 0)	/* MMU enable				*/
+#define CR_A	(1 << 1)	/* Alignment abort enable		*/
+#define CR_C	(1 << 2)	/* Dcache enable			*/
+#define CR_W	(1 << 3)	/* Write buffer enable			*/
+#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
+#define CR_D	(1 << 5)	/* 32-bit data address range		*/
+#define CR_L	(1 << 6)	/* Implementation defined		*/
+#define CD_B	(1 << 7)	/* Big endian				*/
+#define CR_S	(1 << 8)	/* System MMU protection		*/
+#define CD_R	(1 << 9)	/* ROM MMU protection			*/
+#define CR_F	(1 << 10)	/* Implementation defined		*/
+#define CR_Z	(1 << 11)	/* Implementation defined		*/
+#define CR_I	(1 << 12)	/* Icache enable			*/
+#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
+#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
+
+extern unsigned long cr_no_alignment;	/* defined in entry-armv.S */
+extern unsigned long cr_alignment;	/* defined in entry-armv.S */
+
+#if __LINUX_ARM_ARCH__ >= 4
+#define vectors_base()	((cr_alignment & CR_V) ? 0xffff0000 : 0)
+#else
+#define vectors_base()	(0)
+#endif
+
+/*
+ * Save the current interrupt enable state & disable IRQs
+ */
+#define local_irq_save(x)					\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ local_irq_save\n"	\
+"	orr	%1, %0, #128\n"					\
+"	msr	cpsr_c, %1"					\
+	: "=r" (x), "=r" (temp)					\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Enable IRQs
+ */
+#define local_irq_enable()					\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ local_irq_enable\n"	\
+"	bic	%0, %0, #128\n"					\
+"	msr	cpsr_c, %0"					\
+	: "=r" (temp)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Disable IRQs
+ */
+#define local_irq_disable()					\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ local_irq_disable\n"	\
+"	orr	%0, %0, #128\n"					\
+"	msr	cpsr_c, %0"					\
+	: "=r" (temp)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Enable FIQs
+ */
+#define __stf()							\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ stf\n"		\
+"	bic	%0, %0, #64\n"					\
+"	msr	cpsr_c, %0"					\
+	: "=r" (temp)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Disable FIQs
+ */
+#define __clf()							\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ clf\n"		\
+"	orr	%0, %0, #64\n"					\
+"	msr	cpsr_c, %0"					\
+	: "=r" (temp)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Save the current interrupt enable state.
+ */
+#define local_save_flags(x)					\
+	({							\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ local_save_flags\n"	\
+	  : "=r" (x)						\
+	  :							\
+	  : "memory");						\
+	})
+
+/*
+ * restore saved IRQ & FIQ state
+ */
+#define local_irq_restore(x)					\
+	__asm__ __volatile__(					\
+	"msr	cpsr_c, %0		@ local_irq_restore\n"	\
+	:							\
+	: "r" (x)						\
+	: "memory")
+
+#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
+/*
+ * On the StrongARM, "swp" is terminally broken since it bypasses the
+ * cache totally.  This means that the cache becomes inconsistent, and,
+ * since we use normal loads/stores as well, this is really bad.
+ * Typically, this causes oopsen in filp_close, but could have other,
+ * more disasterous effects.  There are two work-arounds:
+ *  1. Disable interrupts and emulate the atomic swap
+ *  2. Clean the cache, perform atomic swap, flush the cache
+ *
+ * We choose (1) since its the "easiest" to achieve here and is not
+ * dependent on the processor type.
+ */
+#define swp_is_buggy
+#endif
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
+{
+	extern void __bad_xchg(volatile void *, int);
+	unsigned long ret;
+#ifdef swp_is_buggy
+	unsigned long flags;
+#endif
+
+	switch (size) {
+#ifdef swp_is_buggy
+		case 1:
+			local_irq_save(flags);
+			ret = *(volatile unsigned char *)ptr;
+			*(volatile unsigned char *)ptr = x;
+			local_irq_restore(flags);
+			break;
+
+		case 4:
+			local_irq_save(flags);
+			ret = *(volatile unsigned long *)ptr;
+			*(volatile unsigned long *)ptr = x;
+			local_irq_restore(flags);
+			break;
+#else
+		case 1:	__asm__ __volatile__ ("swpb %0, %1, [%2]"
+					: "=&r" (ret)
+					: "r" (x), "r" (ptr)
+					: "memory");
+			break;
+		case 4:	__asm__ __volatile__ ("swp %0, %1, [%2]"
+					: "=&r" (ret)
+					: "r" (x), "r" (ptr)
+					: "memory");
+			break;
+#endif
+		default: __bad_xchg(ptr, size), ret = 0;
+	}
+
+	return ret;
+}
+
+#endif
diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h
new file mode 100755
index 0000000..445d449
--- /dev/null
+++ b/include/asm-arm/processor.h
@@ -0,0 +1,134 @@
+/*
+ *  linux/include/asm-arm/processor.h
+ *
+ *  Copyright (C) 1995-2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_PROCESSOR_H
+#define __ASM_ARM_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#define FP_SIZE 35
+
+struct fp_hard_struct {
+	unsigned int save[FP_SIZE];		/* as yet undefined */
+};
+
+struct fp_soft_struct {
+	unsigned int save[FP_SIZE];		/* undefined information */
+};
+
+union fp_state {
+	struct fp_hard_struct	hard;
+	struct fp_soft_struct	soft;
+};
+
+typedef unsigned long mm_segment_t;		/* domain register	*/
+
+#ifdef __KERNEL__
+
+#define EISA_bus 0
+#define MCA_bus 0
+#define MCA_bus__is_a_macro
+
+#include <asm/atomic.h>
+#include <asm/ptrace.h>
+#if 0	/* XXX###XXX */
+#include <asm/arch/memory.h>
+#endif	/* XXX###XXX */
+#include <asm/proc/processor.h>
+#include <asm/types.h>
+
+union debug_insn {
+	u32	arm;
+	u16	thumb;
+};
+
+struct debug_entry {
+	u32			address;
+	union debug_insn	insn;
+};
+
+struct debug_info {
+	int			nsaved;
+	struct debug_entry	bp[2];
+};
+
+struct thread_struct {
+	atomic_t			refcount;
+							/* fault info	  */
+	unsigned long			address;
+	unsigned long			trap_no;
+	unsigned long			error_code;
+							/* floating point */
+	union fp_state			fpstate;
+							/* debugging	  */
+	struct debug_info		debug;
+							/* context info	  */
+	struct context_save_struct	*save;
+	EXTRA_THREAD_STRUCT
+};
+
+#define INIT_THREAD  {					\
+	refcount:	ATOMIC_INIT(1),			\
+	EXTRA_THREAD_STRUCT_INIT			\
+}
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+static inline unsigned long thread_saved_pc(struct thread_struct *t)
+{
+	return t->save ? pc_pointer(t->save->pc) : 0;
+}
+
+static inline unsigned long thread_saved_fp(struct thread_struct *t)
+{
+	return t->save ? t->save->fp : 0;
+}
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+extern void release_thread(struct task_struct *);
+
+/* Copy and release all segment info associated with a VM */
+#define copy_segments(tsk, mm)		do { } while (0)
+#define release_segments(mm)		do { } while (0)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define THREAD_SIZE	(8192)
+
+extern struct task_struct *alloc_task_struct(void);
+extern void __free_task_struct(struct task_struct *);
+#define get_task_struct(p)	atomic_inc(&(p)->thread.refcount)
+#define free_task_struct(p)					\
+ do {								\
+	if (atomic_dec_and_test(&(p)->thread.refcount))		\
+		__free_task_struct((p));			\
+ } while (0)
+
+#define init_task	(init_task_union.task)
+#define init_stack	(init_task_union.stack)
+
+#define cpu_relax()	barrier()
+
+/*
+ * Create a new kernel thread
+ */
+extern int arch_kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+
+#endif
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h
new file mode 100755
index 0000000..73c9087
--- /dev/null
+++ b/include/asm-arm/ptrace.h
@@ -0,0 +1,33 @@
+#ifndef __ASM_ARM_PTRACE_H
+#define __ASM_ARM_PTRACE_H
+
+#define PTRACE_GETREGS		12
+#define PTRACE_SETREGS		13
+#define PTRACE_GETFPREGS	14
+#define PTRACE_SETFPREGS	15
+
+#define PTRACE_SETOPTIONS	21
+
+/* options set using PTRACE_SETOPTIONS */
+#define PTRACE_O_TRACESYSGOOD	0x00000001
+
+#include <asm/proc/ptrace.h>
+
+#ifndef __ASSEMBLY__
+#define pc_pointer(v) \
+	((v) & ~PCMASK)
+
+#define instruction_pointer(regs) \
+	(pc_pointer((regs)->ARM_pc))
+
+#ifdef __KERNEL__
+extern void show_regs(struct pt_regs *);
+
+#define predicate(x)	(x & 0xf0000000)
+#define PREDICATE_ALWAYS	0xe0000000
+
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/include/asm-arm/setup.h b/include/asm-arm/setup.h
new file mode 100755
index 0000000..89df4dc
--- /dev/null
+++ b/include/asm-arm/setup.h
@@ -0,0 +1,269 @@
+/*
+ *  linux/include/asm/setup.h
+ *
+ *  Copyright (C) 1997-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Structure passed to kernel to tell it about the
+ *  hardware it's running on.  See linux/Documentation/arm/Setup
+ *  for more info.
+ *
+ * NOTE:
+ *  This file contains two ways to pass information from the boot
+ *  loader to the kernel. The old struct param_struct is deprecated,
+ *  but it will be kept in the kernel for 5 years from now
+ *  (2001). This will allow boot loaders to convert to the new struct
+ *  tag way.
+ */
+#ifndef __ASMARM_SETUP_H
+#define __ASMARM_SETUP_H
+
+/*
+ * Usage:
+ *  - do not go blindly adding fields, add them at the end
+ *  - when adding fields, don't rely on the address until
+ *    a patch from me has been released
+ *  - unused fields should be zero (for future expansion)
+ *  - this structure is relatively short-lived - only
+ *    guaranteed to contain useful data in setup_arch()
+ */
+#define COMMAND_LINE_SIZE 1024
+
+/* This is the old deprecated way to pass parameters to the kernel */
+struct param_struct {
+    union {
+	struct {
+	    unsigned long page_size;		/*  0 */
+	    unsigned long nr_pages;		/*  4 */
+	    unsigned long ramdisk_size;		/*  8 */
+	    unsigned long flags;		/* 12 */
+#define FLAG_READONLY	1
+#define FLAG_RDLOAD	4
+#define FLAG_RDPROMPT	8
+	    unsigned long rootdev;		/* 16 */
+	    unsigned long video_num_cols;	/* 20 */
+	    unsigned long video_num_rows;	/* 24 */
+	    unsigned long video_x;		/* 28 */
+	    unsigned long video_y;		/* 32 */
+	    unsigned long memc_control_reg;	/* 36 */
+	    unsigned char sounddefault;		/* 40 */
+	    unsigned char adfsdrives;		/* 41 */
+	    unsigned char bytes_per_char_h;	/* 42 */
+	    unsigned char bytes_per_char_v;	/* 43 */
+	    unsigned long pages_in_bank[4];	/* 44 */
+	    unsigned long pages_in_vram;	/* 60 */
+	    unsigned long initrd_start;		/* 64 */
+	    unsigned long initrd_size;		/* 68 */
+	    unsigned long rd_start;		/* 72 */
+	    unsigned long system_rev;		/* 76 */
+	    unsigned long system_serial_low;	/* 80 */
+	    unsigned long system_serial_high;	/* 84 */
+	    unsigned long mem_fclk_21285;       /* 88 */
+	} s;
+	char unused[256];
+    } u1;
+    union {
+	char paths[8][128];
+	struct {
+	    unsigned long magic;
+	    char n[1024 - sizeof(unsigned long)];
+	} s;
+    } u2;
+    char commandline[COMMAND_LINE_SIZE];
+};
+
+
+/*
+ * The new way of passing information: a list of tagged entries
+ */
+
+/* The list ends with an ATAG_NONE node. */
+#define ATAG_NONE	0x00000000
+
+struct tag_header {
+	u32 size;
+	u32 tag;
+};
+
+/* The list must start with an ATAG_CORE node */
+#define ATAG_CORE	0x54410001
+
+struct tag_core {
+	u32 flags;		/* bit 0 = read-only */
+	u32 pagesize;
+	u32 rootdev;
+};
+
+/* it is allowed to have multiple ATAG_MEM nodes */
+#define ATAG_MEM	0x54410002
+
+struct tag_mem32 {
+	u32	size;
+	u32	start;	/* physical start address */
+};
+
+/* VGA text type displays */
+#define ATAG_VIDEOTEXT	0x54410003
+
+struct tag_videotext {
+	u8		x;
+	u8		y;
+	u16		video_page;
+	u8		video_mode;
+	u8		video_cols;
+	u16		video_ega_bx;
+	u8		video_lines;
+	u8		video_isvga;
+	u16		video_points;
+};
+
+/* describes how the ramdisk will be used in kernel */
+#define ATAG_RAMDISK	0x54410004
+
+struct tag_ramdisk {
+	u32 flags;	/* bit 0 = load, bit 1 = prompt */
+	u32 size;	/* decompressed ramdisk size in _kilo_ bytes */
+	u32 start;	/* starting block of floppy-based RAM disk image */
+};
+
+/* describes where the compressed ramdisk image lives (virtual address) */
+/*
+ * this one accidentally used virtual addresses - as such,
+ * its depreciated.
+ */
+#define ATAG_INITRD	0x54410005
+
+/* describes where the compressed ramdisk image lives (physical address) */
+#define ATAG_INITRD2	0x54420005
+
+struct tag_initrd {
+	u32 start;	/* physical start address */
+	u32 size;	/* size of compressed ramdisk image in bytes */
+};
+
+/* board serial number. "64 bits should be enough for everybody" */
+#define ATAG_SERIAL	0x54410006
+
+struct tag_serialnr {
+	u32 low;
+	u32 high;
+};
+
+/* board revision */
+#define ATAG_REVISION	0x54410007
+
+struct tag_revision {
+	u32 rev;
+};
+
+/* initial values for vesafb-type framebuffers. see struct screen_info
+ * in include/linux/tty.h
+ */
+#define ATAG_VIDEOLFB	0x54410008
+
+struct tag_videolfb {
+	u16		lfb_width;
+	u16		lfb_height;
+	u16		lfb_depth;
+	u16		lfb_linelength;
+	u32		lfb_base;
+	u32		lfb_size;
+	u8		red_size;
+	u8		red_pos;
+	u8		green_size;
+	u8		green_pos;
+	u8		blue_size;
+	u8		blue_pos;
+	u8		rsvd_size;
+	u8		rsvd_pos;
+};
+
+/* command line: \0 terminated string */
+#define ATAG_CMDLINE	0x54410009
+
+struct tag_cmdline {
+	char	cmdline[1];	/* this is the minimum size */
+};
+
+/* acorn RiscPC specific information */
+#define ATAG_ACORN	0x41000101
+
+struct tag_acorn {
+	u32 memc_control_reg;
+	u32 vram_pages;
+	u8 sounddefault;
+	u8 adfsdrives;
+};
+
+/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */
+#define ATAG_MEMCLK	0x41000402
+
+struct tag_memclk {
+	u32 fmemclk;
+};
+
+struct tag {
+	struct tag_header hdr;
+	union {
+		struct tag_core		core;
+		struct tag_mem32	mem;
+		struct tag_videotext	videotext;
+		struct tag_ramdisk	ramdisk;
+		struct tag_initrd	initrd;
+		struct tag_serialnr	serialnr;
+		struct tag_revision	revision;
+		struct tag_videolfb	videolfb;
+		struct tag_cmdline	cmdline;
+
+		/*
+		 * Acorn specific
+		 */
+		struct tag_acorn	acorn;
+
+		/*
+		 * DC21285 specific
+		 */
+		struct tag_memclk	memclk;
+	} u;
+};
+
+struct tagtable {
+	u32 tag;
+	int (*parse)(const struct tag *);
+};
+
+#define __tag __attribute__((unused, __section__(".taglist")))
+#define __tagtable(tag, fn) \
+static struct tagtable __tagtable_##fn __tag = { tag, fn }
+
+#define tag_member_present(tag,member)				\
+	((unsigned long)(&((struct tag *)0L)->member + 1)	\
+		<= (tag)->hdr.size * 4)
+
+#define tag_next(t)	((struct tag *)((u32 *)(t) + (t)->hdr.size))
+#define tag_size(type)	((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
+
+#define for_each_tag(t,base)		\
+	for (t = base; t->hdr.size; t = tag_next(t))
+
+/*
+ * Memory map description
+ */
+#define NR_BANKS 8
+
+struct meminfo {
+	int nr_banks;
+	unsigned long end;
+	struct {
+		unsigned long start;
+		unsigned long size;
+		int           node;
+	} bank[NR_BANKS];
+};
+
+extern struct meminfo meminfo;
+
+#endif
diff --git a/include/asm-arm/sizes.h b/include/asm-arm/sizes.h
new file mode 100755
index 0000000..f8d92ca
--- /dev/null
+++ b/include/asm-arm/sizes.h
@@ -0,0 +1,52 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/* DO NOT EDIT!! - this file automatically generated
+ *                 from .s file by awk -f s2h.awk
+ */
+/*  Size defintions
+ *  Copyright (C) ARM Limited 1998. All rights reserved.
+ */
+
+#ifndef __sizes_h
+#define __sizes_h                       1
+
+/* handy sizes */
+#define SZ_1K                           0x00000400
+#define SZ_4K                           0x00001000
+#define SZ_8K                           0x00002000
+#define SZ_16K                          0x00004000
+#define SZ_64K                          0x00010000
+#define SZ_128K                         0x00020000
+#define SZ_256K                         0x00040000
+#define SZ_512K                         0x00080000
+
+#define SZ_1M                           0x00100000
+#define SZ_2M                           0x00200000
+#define SZ_4M                           0x00400000
+#define SZ_8M                           0x00800000
+#define SZ_16M                          0x01000000
+#define SZ_32M                          0x02000000
+#define SZ_64M                          0x04000000
+#define SZ_128M                         0x08000000
+#define SZ_256M                         0x10000000
+#define SZ_512M                         0x20000000
+
+#define SZ_1G                           0x40000000
+#define SZ_2G                           0x80000000
+
+#endif
+
+/*         END */
diff --git a/include/asm-arm/string.h b/include/asm-arm/string.h
new file mode 100755
index 0000000..c3ea582
--- /dev/null
+++ b/include/asm-arm/string.h
@@ -0,0 +1,47 @@
+#ifndef __ASM_ARM_STRING_H
+#define __ASM_ARM_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char * strrchr(const char * s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char * strchr(const char * s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void * memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void * memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+extern void * memset(void *, int, __kernel_size_t);
+
+#if 0
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p,v,n)							\
+	({								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p),(n));			\
+			else						\
+				memset((p),(v),(n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
new file mode 100755
index 0000000..2b28a26
--- /dev/null
+++ b/include/asm-arm/system.h
@@ -0,0 +1,84 @@
+#ifndef __ASM_ARM_SYSTEM_H
+#define __ASM_ARM_SYSTEM_H
+
+#ifdef __KERNEL__
+
+#define CPU_ARCH_UNKNOWN	0
+#define CPU_ARCH_ARMv3		1
+#define CPU_ARCH_ARMv4		2
+#define CPU_ARCH_ARMv4T		3
+#define CPU_ARCH_ARMv5		4
+#define CPU_ARCH_ARMv5T		5
+#define CPU_ARCH_ARMv5TE	6
+#define CPU_ARCH_ARMv5TEJ	7
+#define CPU_ARCH_ARMv6		8
+#define CPU_ARCH_ARMv7		9
+
+/*
+ * CR1 bits (CP#15 CR1)
+ */
+#define CR_M	(1 << 0)	/* MMU enable				*/
+#define CR_A	(1 << 1)	/* Alignment abort enable		*/
+#define CR_C	(1 << 2)	/* Dcache enable			*/
+#define CR_W	(1 << 3)	/* Write buffer enable			*/
+#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
+#define CR_D	(1 << 5)	/* 32-bit data address range		*/
+#define CR_L	(1 << 6)	/* Implementation defined		*/
+#define CR_B	(1 << 7)	/* Big endian				*/
+#define CR_S	(1 << 8)	/* System MMU protection		*/
+#define CR_R	(1 << 9)	/* ROM MMU protection			*/
+#define CR_F	(1 << 10)	/* Implementation defined		*/
+#define CR_Z	(1 << 11)	/* Implementation defined		*/
+#define CR_I	(1 << 12)	/* Icache enable			*/
+#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
+#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
+#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
+#define CR_DT	(1 << 16)
+#define CR_IT	(1 << 18)
+#define CR_ST	(1 << 19)
+#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
+#define CR_U	(1 << 22)	/* Unaligned access operation		*/
+#define CR_XP	(1 << 23)	/* Extended page tables			*/
+#define CR_VE	(1 << 24)	/* Vectored interrupts			*/
+#define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/
+#define CR_TRE	(1 << 28)	/* TEX remap enable			*/
+#define CR_AFE	(1 << 29)	/* Access flag enable			*/
+#define CR_TE	(1 << 30)	/* Thumb exception enable		*/
+
+/*
+ * This is used to ensure the compiler did actually allocate the register we
+ * asked it for some inline assembly sequences.  Apparently we can't trust
+ * the compiler from one version to another so a bit of paranoia won't hurt.
+ * This string is meant to be concatenated with the inline asm string and
+ * will cause compilation to stop on mismatch.
+ * (for details, see gcc PR 15089)
+ */
+#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+#ifndef __ASSEMBLY__
+
+#define isb() __asm__ __volatile__ ("" : : : "memory")
+
+#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
+
+static inline unsigned int get_cr(void)
+{
+	unsigned int val;
+	asm("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val) : : "cc");
+	return val;
+}
+
+static inline void set_cr(unsigned int val)
+{
+	asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR"
+	  : : "r" (val) : "cc");
+	isb();
+}
+
+#endif /* __ASSEMBLY__ */
+
+#define arch_align_stack(x) (x)
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/include/asm-arm/types.h b/include/asm-arm/types.h
new file mode 100755
index 0000000..13e9806
--- /dev/null
+++ b/include/asm-arm/types.h
@@ -0,0 +1,50 @@
+#ifndef __ASM_ARM_TYPES_H
+#define __ASM_ARM_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h
new file mode 100755
index 0000000..4ee5a32
--- /dev/null
+++ b/include/asm-arm/u-boot-arm.h
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_ARM_H_
+#define _U_BOOT_ARM_H_	1
+
+/* for the following variables, see start.S */
+extern ulong _armboot_start;	/* code start */
+extern ulong _bss_start;	/* code + data end == BSS start */
+extern ulong _bss_end;		/* BSS end */
+extern ulong IRQ_STACK_START;	/* top of IRQ stack */
+extern ulong FIQ_STACK_START;	/* top of FIQ stack */
+
+/* cpu/.../cpu.c */
+int	cpu_init(void);
+int	cleanup_before_linux(void);
+
+/* board/.../... */
+int	board_init(void);
+int	dram_init (void);
+void	setup_serial_tag (struct tag **params);
+void	setup_revision_tag (struct tag **params);
+
+/* ------------------------------------------------------------ */
+/* Here is a list of some prototypes which are incompatible to	*/
+/* the U-Boot implementation					*/
+/* To be fixed!							*/
+/* ------------------------------------------------------------ */
+/* common/cmd_nvedit.c */
+int	setenv		(char *, char *);
+
+/* cpu/.../interrupt.c */
+void	reset_timer_masked	(void);
+ulong	get_timer_masked	(void);
+void	udelay_masked		(unsigned long usec);
+
+#endif	/* _U_BOOT_ARM_H_ */
diff --git a/include/asm-arm/u-boot.h b/include/asm-arm/u-boot.h
new file mode 100755
index 0000000..146934c
--- /dev/null
+++ b/include/asm-arm/u-boot.h
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+typedef struct bd_info {
+    int			bi_baudrate;	/* serial console baudrate */
+    unsigned long	bi_ip_addr;	/* IP Address */
+    unsigned char	bi_enetaddr[6]; /* Ethernet adress */
+    struct environment_s	       *bi_env;
+    ulong	        bi_arch_number;	/* unique id for this board */
+    ulong	        bi_boot_params;	/* where this board expects params */
+    struct				/* RAM configuration */
+    {
+	ulong start;
+	ulong size;
+    } 			bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+#define bi_env_data bi_env->data
+#define bi_env_crc  bi_env->crc
+
+#endif	/* _U_BOOT_H_ */
diff --git a/include/asm-i386/bitops.h b/include/asm-i386/bitops.h
new file mode 100755
index 0000000..b768e20
--- /dev/null
+++ b/include/asm-i386/bitops.h
@@ -0,0 +1,383 @@
+#ifndef _I386_BITOPS_H
+#define _I386_BITOPS_H
+
+/*
+ * Copyright 1992, Linus Torvalds.
+ */
+
+
+/*
+ * These have to be done with inline assembly: that way the bit-setting
+ * is guaranteed to be atomic. All bit operations return 0 if the bit
+ * was cleared before the operation and != 0 if it was not.
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ */
+
+#ifdef CONFIG_SMP
+#define LOCK_PREFIX "lock ; "
+#else
+#define LOCK_PREFIX ""
+#endif
+
+#define ADDR (*(volatile long *) addr)
+
+/**
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered.  See __set_bit()
+ * if you do not require the atomic guarantees.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static __inline__ void set_bit(int nr, volatile void * addr)
+{
+	__asm__ __volatile__( LOCK_PREFIX
+		"btsl %1,%0"
+		:"=m" (ADDR)
+		:"Ir" (nr));
+}
+
+/**
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static __inline__ void __set_bit(int nr, volatile void * addr)
+{
+	__asm__(
+		"btsl %1,%0"
+		:"=m" (ADDR)
+		:"Ir" (nr));
+}
+
+/**
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered.  However, it does
+ * not contain a memory barrier, so if it is used for locking purposes,
+ * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
+ * in order to ensure changes are visible on other processors.
+ */
+static __inline__ void clear_bit(int nr, volatile void * addr)
+{
+	__asm__ __volatile__( LOCK_PREFIX
+		"btrl %1,%0"
+		:"=m" (ADDR)
+		:"Ir" (nr));
+}
+#define smp_mb__before_clear_bit()	barrier()
+#define smp_mb__after_clear_bit()	barrier()
+
+/**
+ * __change_bit - Toggle a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike change_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static __inline__ void __change_bit(int nr, volatile void * addr)
+{
+	__asm__ __volatile__(
+		"btcl %1,%0"
+		:"=m" (ADDR)
+		:"Ir" (nr));
+}
+
+/**
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static __inline__ void change_bit(int nr, volatile void * addr)
+{
+	__asm__ __volatile__( LOCK_PREFIX
+		"btcl %1,%0"
+		:"=m" (ADDR)
+		:"Ir" (nr));
+}
+
+/**
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static __inline__ int test_and_set_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+
+	__asm__ __volatile__( LOCK_PREFIX
+		"btsl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit),"=m" (ADDR)
+		:"Ir" (nr) : "memory");
+	return oldbit;
+}
+
+/**
+ * __test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+
+	__asm__(
+		"btsl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit),"=m" (ADDR)
+		:"Ir" (nr));
+	return oldbit;
+}
+
+/**
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+
+	__asm__ __volatile__( LOCK_PREFIX
+		"btrl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit),"=m" (ADDR)
+		:"Ir" (nr) : "memory");
+	return oldbit;
+}
+
+/**
+ * __test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+
+	__asm__(
+		"btrl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit),"=m" (ADDR)
+		:"Ir" (nr));
+	return oldbit;
+}
+
+/* WARNING: non atomic and it can be reordered! */
+static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+
+	__asm__ __volatile__(
+		"btcl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit),"=m" (ADDR)
+		:"Ir" (nr) : "memory");
+	return oldbit;
+}
+
+/**
+ * test_and_change_bit - Change a bit and return its new value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static __inline__ int test_and_change_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+
+	__asm__ __volatile__( LOCK_PREFIX
+		"btcl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit),"=m" (ADDR)
+		:"Ir" (nr) : "memory");
+	return oldbit;
+}
+
+#if 0 /* Fool kernel-doc since it doesn't do macros yet */
+/**
+ * test_bit - Determine whether a bit is set
+ * @nr: bit number to test
+ * @addr: Address to start counting from
+ */
+static int test_bit(int nr, const volatile void * addr);
+#endif
+
+static __inline__ int constant_test_bit(int nr, const volatile void * addr)
+{
+	return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
+}
+
+static __inline__ int variable_test_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+
+	__asm__ __volatile__(
+		"btl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit)
+		:"m" (ADDR),"Ir" (nr));
+	return oldbit;
+}
+
+#define test_bit(nr,addr) \
+(__builtin_constant_p(nr) ? \
+ constant_test_bit((nr),(addr)) : \
+ variable_test_bit((nr),(addr)))
+
+/**
+ * find_first_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first zero bit, not the number of the byte
+ * containing a bit.
+ */
+static __inline__ int find_first_zero_bit(void * addr, unsigned size)
+{
+	int d0, d1, d2;
+	int res;
+
+	if (!size)
+		return 0;
+	/* This looks at memory. Mark it volatile to tell gcc not to move it around */
+	__asm__ __volatile__(
+		"movl $-1,%%eax\n\t"
+		"xorl %%edx,%%edx\n\t"
+		"repe; scasl\n\t"
+		"je 1f\n\t"
+		"xorl -4(%%edi),%%eax\n\t"
+		"subl $4,%%edi\n\t"
+		"bsfl %%eax,%%edx\n"
+		"1:\tsubl %%ebx,%%edi\n\t"
+		"shll $3,%%edi\n\t"
+		"addl %%edi,%%edx"
+		:"=d" (res), "=&c" (d0), "=&D" (d1), "=&a" (d2)
+		:"1" ((size + 31) >> 5), "2" (addr), "b" (addr));
+	return res;
+}
+
+/**
+ * find_next_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+static __inline__ int find_next_zero_bit (void * addr, int size, int offset)
+{
+	unsigned long * p = ((unsigned long *) addr) + (offset >> 5);
+	int set = 0, bit = offset & 31, res;
+
+	if (bit) {
+		/*
+		 * Look for zero in first byte
+		 */
+		__asm__("bsfl %1,%0\n\t"
+			"jne 1f\n\t"
+			"movl $32, %0\n"
+			"1:"
+			: "=r" (set)
+			: "r" (~(*p >> bit)));
+		if (set < (32 - bit))
+			return set + offset;
+		set = 32 - bit;
+		p++;
+	}
+	/*
+	 * No zero yet, search remaining full bytes for a zero
+	 */
+	res = find_first_zero_bit (p, size - 32 * (p - (unsigned long *) addr));
+	return (offset + set + res);
+}
+
+/**
+ * ffz - find first zero in word.
+ * @word: The word to search
+ *
+ * Undefined if no zero exists, so code should check against ~0UL first.
+ */
+static __inline__ unsigned long ffz(unsigned long word)
+{
+	__asm__("bsfl %1,%0"
+		:"=r" (word)
+		:"r" (~word));
+	return word;
+}
+
+#ifdef __KERNEL__
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static __inline__ int ffs(int x)
+{
+	int r;
+
+	__asm__("bsfl %1,%0\n\t"
+		"jnz 1f\n\t"
+		"movl $-1,%0\n"
+		"1:" : "=r" (r) : "g" (x));
+	return r+1;
+}
+
+/**
+ * hweightN - returns the hamming weight of a N-bit word
+ * @x: the word to weigh
+ *
+ * The Hamming Weight of a number is the total number of bits set in it.
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __KERNEL__ */
+
+#ifdef __KERNEL__
+
+#define ext2_set_bit                 __test_and_set_bit
+#define ext2_clear_bit               __test_and_clear_bit
+#define ext2_test_bit                test_bit
+#define ext2_find_first_zero_bit     find_first_zero_bit
+#define ext2_find_next_zero_bit      find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem.  */
+#define minix_test_and_set_bit(nr,addr) __test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr) __set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr) __test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr) test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
+
+#endif /* __KERNEL__ */
+
+#endif /* _I386_BITOPS_H */
diff --git a/include/asm-i386/byteorder.h b/include/asm-i386/byteorder.h
new file mode 100755
index 0000000..a9c69d5
--- /dev/null
+++ b/include/asm-i386/byteorder.h
@@ -0,0 +1,43 @@
+#ifndef _I386_BYTEORDER_H
+#define _I386_BYTEORDER_H
+
+#include <asm/types.h>
+
+#ifdef __GNUC__
+
+
+static __inline__ __const__ __u32 ___arch__swab32(__u32 x)
+{
+#ifdef CONFIG_X86_BSWAP
+	__asm__("bswap %0" : "=r" (x) : "0" (x));
+#else
+	__asm__("xchgb %b0,%h0\n\t"	/* swap lower bytes	*/
+		"rorl $16,%0\n\t"	/* swap words		*/
+		"xchgb %b0,%h0"		/* swap higher bytes	*/
+		:"=q" (x)
+		: "0" (x));
+#endif
+	return x;
+}
+
+static __inline__ __const__ __u16 ___arch__swab16(__u16 x)
+{
+	__asm__("xchgb %b0,%h0"		/* swap bytes		*/ \
+		: "=q" (x) \
+		:  "0" (x)); \
+		return x;
+}
+
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __GNUC__ */
+
+#include <linux/byteorder/little_endian.h>
+
+#endif /* _I386_BYTEORDER_H */
diff --git a/include/asm-i386/global_data.h b/include/asm-i386/global_data.h
new file mode 100755
index 0000000..1d309d5
--- /dev/null
+++ b/include/asm-i386/global_data.h
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	have_console;	/* serial_init() was called */
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
+	unsigned long	bus_clk;
+	unsigned long	ram_size;	/* RAM size */
+	unsigned long	reset_status;	/* reset status register at boot */
+	void		**jt;		/* jump table */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC	0x00001		/* Code was relocated to RAM		*/
+#define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
+#define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
+
+extern gd_t *global_data;
+
+#define DECLARE_GLOBAL_DATA_PTR     gd_t *gd = global_data
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/include/asm-i386/i8254.h b/include/asm-i386/i8254.h
new file mode 100755
index 0000000..aafdfb8
--- /dev/null
+++ b/include/asm-i386/i8254.h
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+/* i8254.h Intel 8254 PIT registers */
+
+
+#ifndef _ASMI386_I8254_H_
+#define _ASMI386_I8954_H_       1
+
+
+#define PIT_T0		0x00		/* PIT channel 0 count/status */
+#define PIT_T1		0x01		/* PIT channel 1 count/status */
+#define PIT_T2		0x02		/* PIT channel 2 count/status */
+#define PIT_COMMAND	0x03		/* PIT mode control, latch and read back */
+
+/* PIT Command Register Bit Definitions */
+
+#define PIT_CMD_CTR0	0x00		/* Select PIT counter 0 */
+#define PIT_CMD_CTR1	0x40		/* Select PIT counter 1 */
+#define PIT_CMD_CTR2	0x80		/* Select PIT counter 2 */
+
+#define PIT_CMD_LATCH	0x00		/* Counter Latch Command */
+#define PIT_CMD_LOW	0x10		/* Access counter bits 7-0 */
+#define PIT_CMD_HIGH	0x20		/* Access counter bits 15-8 */
+#define PIT_CMD_BOTH	0x30		/* Access counter bits 15-0 in two accesses */
+
+#define PIT_CMD_MODE0	0x00		/* Select mode 0 */
+#define PIT_CMD_MODE1	0x02		/* Select mode 1 */
+#define PIT_CMD_MODE2	0x04		/* Select mode 2 */
+#define PIT_CMD_MODE3	0x06		/* Select mode 3 */
+#define PIT_CMD_MODE4	0x08		/* Select mode 4 */
+#define PIT_CMD_MODE5	0x0A		/* Select mode 5 */
+
+#endif
diff --git a/include/asm-i386/i8259.h b/include/asm-i386/i8259.h
new file mode 100755
index 0000000..774d7a3
--- /dev/null
+++ b/include/asm-i386/i8259.h
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* i8259.h i8259 PIC Registers */
+
+#ifndef _ASMI386_I8259_H_
+#define _ASMI386_I8959_H_       1
+
+
+/* PIC I/O mapped registers */
+
+#define IRR		0x0	/* Interrupt Request Register */
+#define ISR		0x0	/* In-Service Register */
+#define ICW1		0x0	/* Initialization Control Word 1 */
+#define OCW2		0x0	/* Operation Control Word 2 */
+#define OCW3		0x0	/* Operation Control Word 3 */
+#define ICW2		0x1	/* Initialization Control Word 2 */
+#define ICW3		0x1	/* Initialization Control Word 3 */
+#define ICW4		0x1	/* Initialization Control Word 4 */
+#define IMR		0x1	/* Interrupt Mask Register */
+
+/* bits for IRR, IMR, ISR and ICW3 */
+#define	IR7		0x80	/* IR7 */
+#define	IR6		0x40	/* IR6 */
+#define	IR5		0x20	/* IR5 */
+#define	IR4		0x10	/* IR4 */
+#define	IR3		0x08	/* IR3 */
+#define	IR2		0x04	/* IR2 */
+#define	IR1		0x02	/* IR1 */
+#define	IR0		0x01	/* IR0 */
+
+/* bits for SEOI */
+#define	SEOI_IR7	0x07	/* IR7 */
+#define	SEOI_IR6	0x06	/* IR6 */
+#define	SEOI_IR5	0x05	/* IR5 */
+#define	SEOI_IR4	0x04	/* IR4 */
+#define	SEOI_IR3	0x03	/* IR3 */
+#define	SEOI_IR2	0x02	/* IR2 */
+#define	SEOI_IR1	0x01	/* IR1 */
+#define	SEOI_IR0	0x00	/* IR0 */
+
+/* OCW2 bits */
+#define OCW2_RCLR	0x00	/* Rotate/clear */
+#define OCW2_NEOI	0x20	/* Non specific EOI */
+#define OCW2_NOP	0x40	/* NOP */
+#define OCW2_SEOI	0x60	/* Specific EOI */
+#define OCW2_RSET	0x80	/* Rotate/set */
+#define OCW2_REOI	0xA0	/* Rotate on non specific EOI */
+#define OCW2_PSET	0xC0	/* Priority Set Command */
+#define OCW2_RSEOI	0xE0	/* Rotate on specific EOI */
+
+/* ICW1 bits */
+#define ICW1_SEL	0x10	/* Select ICW1 */
+#define ICW1_LTIM	0x08	/* Level-Triggered Interrupt Mode */
+#define ICW1_ADI	0x04	/* Address Interval */
+#define ICW1_SNGL	0x02	/* Single PIC */
+#define ICW1_EICW4	0x01	/* Expect initilization ICW4 */
+
+/* ICW2 is the starting vector number */
+
+/* ICW2 is bit-mask of present slaves for a master device,
+ * or the slave ID for a slave device */
+
+/* ICW4 bits */
+#define	ICW4_AEOI	0x02	/* Automatic EOI Mode */
+#define ICW4_PM		0x01	/* Microprocessor Mode */
+
+#endif
diff --git a/include/asm-i386/ibmpc.h b/include/asm-i386/ibmpc.h
new file mode 100755
index 0000000..e35cbd8
--- /dev/null
+++ b/include/asm-i386/ibmpc.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_IBMPC_H_
+#define __ASM_IBMPC_H_ 1
+
+/* misc ports in an ibm compatible pc */
+
+#define MASTER_PIC      0x20
+#define PIT_BASE	0x40
+#define KBDDATA         0x60
+#define SYSCTLB         0x62
+#define KBDCMD          0x64
+#define SYSCTLA         0x92
+#define SLAVE_PIC       0xa0
+
+#if 1
+#define UART0_BASE     0x3f8
+#define UART1_BASE     0x2f8
+#else
+/* FixMe: uarts swapped */
+#define UART0_BASE     0x2f8
+#define UART1_BASE     0x3f8
+#endif
+
+
+#endif
diff --git a/include/asm-i386/ic/ali512x.h b/include/asm-i386/ic/ali512x.h
new file mode 100755
index 0000000..5bc1bd7
--- /dev/null
+++ b/include/asm-i386/ic/ali512x.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_IC_ALI512X_H_
+#define __ASM_IC_ALI512X_H_
+
+# define ALI_INDEX    0x3f0
+# define ALI_DATA     0x3f1
+
+# define ALI_ENABLED  1
+# define ALI_DISABLED 0
+
+# define ALI_UART1    0
+# define ALI_UART2    1
+
+/* setup functions */
+void ali512x_init(void);
+void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel);
+void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel);
+void ali512x_set_uart(int enabled, int index, u16 io, u8 irq);
+void ali512x_set_rtc(int enabled, u16 io, u8 irq);
+void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq);
+void ali512x_set_cio(int enabled);
+
+
+/* common I/O functions */
+void ali512x_cio_function(int pin, int special, int inv, int input);
+void ali512x_cio_out(int pin, int value);
+int ali512x_cio_in(int pin);
+
+/* misc features */
+void ali512x_set_uart2_irda(int enabled);
+
+#endif
diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h
new file mode 100755
index 0000000..d5abbbe
--- /dev/null
+++ b/include/asm-i386/ic/sc520.h
@@ -0,0 +1,318 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_IC_SC520_H_
+#define _ASM_IC_SC520_H_ 1
+
+/* Memory mapped configuration registers, MMCR */
+#define SC520_REVID		0x0000		/* ElanSC520 Microcontroller Revision ID Register */
+#define SC520_CPUCTL		0x0002		/* Am5x86 CPU Control Register */
+#define SC520_DRCCTL            0x0010          /* SDRAM Control Register */
+#define SC520_DRCTMCTL		0x0012		/* SDRAM Timing Control Register */
+#define SC520_DRCCFG		0x0014		/* SDRAM Bank Configuration Register*/
+#define SC520_DRCBENDADR	0x0018		/* SDRAM Bank 0-3 Ending Address Register*/
+#define SC520_ECCCTL		0x0020		/* ECC Control Register */
+#define SC520_ECCSTA		0x0021		/* ECC Status Register */
+#define SC520_ECCCKBPOS		0x0022		/* ECC Check Bit Position Register */
+#define SC520_ECCSBADD		0x0024		/* ECC Single-Bit Error Address Register */
+#define SC520_DBCTL		0x0040		/* SDRAM Buffer Control Register */
+#define SC520_BOOTCSCTL		0x0050		/* /BOOTCS Control Register */
+#define SC520_ROMCS1CTL		0x0054		/* /ROMCS1 Control Register */
+#define SC520_ROMCS2CTL		0x0056		/* /ROMCS2 Control Register */
+#define SC520_HBCTL		0x0060 		/* Host Bridge Control Register */
+#define SC520_HBTGTIRQCTL	0x0062		/* Host Bridge Target Interrupt Control Register */
+#define SC520_HBTGTIRQSTA	0x0064		/* Host Bridge Target Interrupt Status Register */
+#define SC520_HBMSTIRQCTL	0x0066		/* Host Bridge Target Interrupt Control Register */
+#define SC520_HBMSTIRQSTA	0x0068		/* Host Bridge Master Interrupt Status Register */
+#define SC520_MSTINTADD		0x006c		/* Host Bridge Master Interrupt Address Register */
+#define SC520_SYSARBCTL		0x0070		/* System Arbiter Control Register */
+#define SC520_PCIARBSTA		0x0071		/* PCI Bus Arbiter Status Register */
+#define SC520_SYSARBMENB	0x0072		/* System Arbiter Master Enable Register */
+#define SC520_ARBPRICTL		0x0074		/* Arbiter Priority Control Register */
+#define SC520_ADDDECCTL     	0x0080 		/* Address Decode Control Register */
+#define SC520_WPVSTA        	0x0082		/* Write-Protect Violation Status Register */
+#define SC520_PAR0          	0x0088		/* Programmable Address Region 0 Register */
+#define SC520_PAR1          	0x008c       	/* Programmable Address Region 1 Register */
+#define SC520_PAR2          	0x0090       	/* Programmable Address Region 2 Register */
+#define SC520_PAR3          	0x0094      	/* Programmable Address Region 3 Register */
+#define SC520_PAR4          	0x0098       	/* Programmable Address Region 4 Register */
+#define SC520_PAR5          	0x009c       	/* Programmable Address Region 5 Register */
+#define SC520_PAR6         	0x00a0      	/* Programmable Address Region 6 Register */
+#define SC520_PAR7          	0x00a4       	/* Programmable Address Region 7 Register */
+#define SC520_PAR8          	0x00a8       	/* Programmable Address Region 8 Register */
+#define SC520_PAR9          	0x00ac       	/* Programmable Address Region 9 Register */
+#define SC520_PAR10         	0x00b0       	/* Programmable Address Region 10 Register */
+#define SC520_PAR11         	0x00b4       	/* Programmable Address Region 11 Register */
+#define SC520_PAR12         	0x00b8       	/* Programmable Address Region 12 Register */
+#define SC520_PAR13         	0x00bc       	/* Programmable Address Region 13 Register */
+#define SC520_PAR14         	0x00c0       	/* Programmable Address Region 14 Register */
+#define SC520_PAR15		0x00c4		/* Programmable Address Region 15 Register */
+#define SC520_GPECHO		0x0c00		/* GP Echo Mode Register */
+#define SC520_GPCSDW		0x0c01		/* GP Chip Select Data Width Register */
+#define SC520_GPCSQUAL		0x0c02		/* GP Chip Select Qualification Register */
+#define SC520_GPCSRT		0x0c08		/* GP Chip Select Recovery Time Register */
+#define SC520_GPCSPW		0x0c09		/* GP Chip Select Pulse Width Register */
+#define SC520_GPCSOFF		0x0c0a		/* GP Chip Select Offset Register */
+#define SC520_GPRDW		0x0c0b		/* GP Read Pulse Width Register */
+#define SC520_GPRDOFF		0x0c0c		/* GP Read Offset Register */
+#define SC520_GPWRW		0x0c0d		/* GP Write Pulse Width Register */
+#define SC520_GPWROFF		0x0c0e		/* GP Write Offset Register */
+#define SC520_GPALEW		0x0c0f		/* GP ALE Pulse Width Register */
+#define SC520_GPALEOFF		0x0c10		/* GP ALE Offset Register */
+#define SC520_PIOPFS15_0	0x0c20		/* PIO15-PIO0 Pin Function Select */
+#define SC520_PIOPFS31_16	0x0c22		/* PIO31-PIO16 Pin Function Select */
+#define SC520_CSPFS		0x0c24		/* Chip Select Pin Function Select */
+#define SC520_CLKSEL		0x0c26		/* Clock Select */
+#define SC520_DSCTL		0x0c28		/* Drive Strength Control */
+#define SC520_PIODIR15_0	0x0c2a		/* PIO15-PIO0 Direction */
+#define SC520_PIODIR31_16	0x0c2c		/* PIO31-PIO16 Direction */
+#define SC520_PIODATA15_0	0x0c30		/* PIO15-PIO0 Data */
+#define SC520_PIODATA31_16	0x0c32		/* PIO31-PIO16 Data */
+#define SC520_PIOSET15_0	0x0c34		/* PIO15-PIO0 Set */
+#define SC520_PIOSET31_16	0x0c36		/* PIO31-PIO16 Set */
+#define SC520_PIOCLR15_0	0x0c38		/* PIO15-PIO0 Clear */
+#define SC520_PIOCLR31_16	0x0c3a		/* PIO31-PIO16 Clear */
+#define SC520_SWTMRMILLI 	0x0c60		/* Software Timer Millisecond Count */
+#define SC520_SWTMRMICRO 	0x0c62		/* Software Timer Microsecond Count */
+#define SC520_SWTMRCFG   	0x0c64		/* Software Timer Configuration */
+#define SC520_GPTMRSTA		0x0c70		/* GP Timers Status Register */
+#define SC520_GPTMR0CTL		0x0c72		/* GP Timer 0 Mode/Control Register */
+#define SC520_GPTMR0CNT		0x0c74		/* GP Timer 0 Count Register */
+#define SC520_GPTMR0MAXCMPA	0x0c76		/* GP Timer 0 Maxcount Compare A Register */
+#define SC520_GPTMR0MAXCMPB	0x0c78		/* GP Timer 0 Maxcount Compare B Register */
+#define SC520_GPTMR1CTL		0x0c7a		/* GP Timer 1 Mode/Control Register */
+#define SC520_GPTMR1CNT		0x0c7c		/* GP Timer 1 Count Register */
+#define SC520_GPTMR1MAXCMPA	0x0c7e		/* GP Timer 1 Maxcount Compare Register A */
+#define SC520_GPTMR1MAXCMPB	0x0c80		/* GP Timer 1 Maxcount Compare B Register */
+#define SC520_GPTMR2CTL		0x0c82		/* GP Timer 2 Mode/Control Register */
+#define SC520_GPTMR2CNT		0x0c84		/* GP Timer 2 Count Register */
+#define SC520_GPTMR2MAXCMPA	0x0c8e		/* GP Timer 2 Maxcount Compare A Register */
+#define SC520_WDTMRCTL		0x0cb0		/* Watchdog Timer Control Register */
+#define SC520_WDTMRCNTL		0x0cb2		/* Watchdog Timer Count Low Register */
+#define SC520_WDTMRCNTH		0x0cb4		/* Watchdog Timer Count High Register */
+#define SC520_UART1CTL		0x0cc0	        /* UART 1 General Control Register */
+#define SC520_UART1STA		0x0cc1	        /* UART 1 General Status Register */
+#define SC520_UART1FCRSHAD	0x0cc2	        /* UART 1 FIFO Control Shadow Register */
+#define SC520_UART2CTL		0x0cc4	        /* UART 2 General Control Register */
+#define SC520_UART2STA		0x0cc5	        /* UART 2 General Status Register */
+#define SC520_UART2FCRSHAD	0x0cc6	        /* UART 2 FIFO Control Shadow Register */
+#define SC520_SSICTL            0x0cd0          /* SSI Control */
+#define SC520_SSIXMIT           0x0cd1          /* SSI Transmit */
+#define SC520_SSICMD            0x0cd2          /* SSI Command */
+#define SC520_SSISTA            0x0cd3          /* SSI Status */
+#define SC520_SSIRCV            0x0cd4          /* SSI Receive */
+#define SC520_PICICR		0x0d00		/* Interrupt Control Register */
+#define SC520_MPICMODE		0x0d02		/* Master PIC Interrupt Mode Register */
+#define SC520_SL1PICMODE	0x0d03		/* Slave 1 PIC Interrupt Mode Register */
+#define SC520_SL2PICMODE	0x0d04		/* Slave 2 PIC Interrupt Mode Register */
+#define SC520_SWINT16_1		0x0d08		/* Software Interrupt 16-1 Control Register */
+#define SC520_SWINT22_17	0x0d0a		/* Software Interrupt 22-17/NMI Control Register */
+#define SC520_INTPINPOL		0x0d10		/* Interrupt Pin Polarity Register */
+#define SC520_PCIHOSTMAP	0x0d14		/* PCI Host Bridge Interrupt Mappin Register */
+#define SC520_ECCMAP		0x0d18		/* ECC Interrupt Mapping Register */
+#define SC520_GPTMR0MAP		0x0d1a		/* GP Timer 0 Interrupt Mapping Register */
+#define SC520_GPTMR1MAP		0x0d1b		/* GP Timer 1 Interrupt Mapping Register */
+#define SC520_GPTMR2MAP		0x0d1c		/* GP Timer 2 Interrupt Mapping Register */
+#define SC520_PIT0MAP		0x0d20		/* PIT0 Interrupt Mapping Register */
+#define SC520_PIT1MAP		0x0d21		/* PIT1 Interrupt Mapping Register */
+#define SC520_PIT2MAP		0x0d22		/* PIT2 Interrupt Mapping Register */
+#define SC520_UART1MAP		0x0d28		/* UART 1 Interrupt Mapping Register */
+#define SC520_UART2MAP		0x0d29		/* UART 2 Interrupt Mapping Register */
+#define SC520_PCIINTAMAP	0x0d30		/* PCI Interrupt A Mapping Register */
+#define SC520_PCIINTBMAP	0x0d31		/* PCI Interrupt B Mapping Register */
+#define SC520_PCIINTCMAP	0x0d32		/* PCI Interrupt C Mapping Register */
+#define SC520_PCIINTDMAP	0x0d33		/* PCI Interrupt D Mapping Register */
+#define SC520_DMABCINTMAP	0x0d40		/* DMA Buffer Chaining Interrupt Mapping Register */
+#define SC520_SSIMAP		0x0d41		/* SSI Interrupt Mapping Register */
+#define SC520_WDTMAP		0x0d42		/* Watchdog Timer Interrupt Mapping Register */
+#define SC520_RTCMAP		0x0d43		/* RTC Interrupt Mapping Register */
+#define SC520_WPVMAP		0x0d44		/* Write-Protect Interrupt Mapping Register */
+#define SC520_ICEMAP		0x0d45		/* AMDebug JTAG RX/TX Interrupt Mapping Register */
+#define SC520_FERRMAP		0x0d46		/* Floating Point Error Interrupt Mapping Register */
+#define SC520_GP0IMAP		0x0d50		/* GPIRQ0 Interrupt Mapping Register */
+#define SC520_GP1IMAP		0x0d51		/* GPIRQ1 Interrupt Mapping Register */
+#define SC520_GP2IMAP		0x0d52		/* GPIRQ2 Interrupt Mapping Register */
+#define SC520_GP3IMAP		0x0d53		/* GPIRQ3 Interrupt Mapping Register */
+#define SC520_GP4IMAP		0x0d54		/* GPIRQ4 Interrupt Mapping Register */
+#define SC520_GP5IMAP		0x0d55		/* GPIRQ5 Interrupt Mapping Register */
+#define SC520_GP6IMAP		0x0d56		/* GPIRQ6 Interrupt Mapping Register */
+#define SC520_GP7IMAP		0x0d57		/* GPIRQ7 Interrupt Mapping Register */
+#define SC520_GP8IMAP		0x0d58		/* GPIRQ8 Interrupt Mapping Register */
+#define SC520_GP9IMAP		0x0d59		/* GPIRQ9 Interrupt Mapping Register */
+#define SC520_GP10IMAP		0x0d5a		/* GPIRQ10 Interrupt Mapping Register */
+#define SC520_SYSINFO		0x0d70		/* System Board Information Register */
+#define SC520_RESCFG		0x0d72		/* Reset Configuration Register */
+#define SC520_RESSTA		0x0d74		/* Reset Status Register */
+#define SC520_GPDMAMMIO		0x0d81		/* GP-DMA Memory-Mapped I/O Register */
+#define SC520_GPDMAEXTCHMAPA	0x0d82		/* GP-DMA Resource Channel Map A */
+#define SC520_GPDMAEXTCHMAPB	0x0d84		/* GP-DMA Resource Channel Map B */
+#define SC520_GPDMAEXTPG0	0x0d86		/* GP-DMA Channel 0 Extended Page */
+#define SC520_GPDMAEXTPG1	0x0d87		/* GP-DMA Channel 1 Extended Page */
+#define SC520_GPDMAEXTPG2	0x0d88		/* GP-DMA Channel 2 Extended Page */
+#define SC520_GPDMAEXTPG3	0x0d89		/* GP-DMA Channel 3 Extended Page */
+#define SC520_GPDMAEXTPG5	0x0d8a		/* GP-DMA Channel 5 Extended Page */
+#define SC520_GPDMAEXTPG6	0x0d8b		/* GP-DMA Channel 6 Extended Page */
+#define SC520_GPDMAEXTPG7	0x0d8c		/* GP-DMA Channel 7 Extended Page */
+#define SC520_GPDMAEXTTC3	0x0d90		/* GP-DMA Channel 3 Extender Transfer count */
+#define SC520_GPDMAEXTTC5	0x0d91		/* GP-DMA Channel 5 Extender Transfer count */
+#define SC520_GPDMAEXTTC6	0x0d92		/* GP-DMA Channel 6 Extender Transfer count */
+#define SC520_GPDMAEXTTC7	0x0d93		/* GP-DMA Channel 7 Extender Transfer count */
+#define SC520_GPDMABCCTL	0x0d98		/* Buffer Chaining Control */
+#define SC520_GPDMABCSTA	0x0d99		/* Buffer Chaining Status */
+#define SC520_GPDMABSINTENB	0x0d9a		/* Buffer Chaining Interrupt Enable */
+#define SC520_GPDMABCVAL	0x0d9b		/* Buffer Chaining Valid */
+#define SC520_GPDMANXTADDL3	0x0da0		/* GP-DMA Channel 3 Next Address Low */
+#define SC520_GPDMANXTADDH3	0x0da2		/* GP-DMA Channel 3 Next Address High */
+#define SC520_GPDMANXTADDL5	0x0da4		/* GP-DMA Channel 5 Next Address Low */
+#define SC520_GPDMANXTADDH5	0x0da6		/* GP-DMA Channel 5 Next Address High */
+#define SC520_GPDMANXTADDL6	0x0da8		/* GP-DMA Channel 6 Next Address Low */
+#define SC520_GPDMANXTADDH6	0x0daa		/* GP-DMA Channel 6 Next Address High */
+#define SC520_GPDMANXTADDL7	0x0dac		/* GP-DMA Channel 7 Next Address Low */
+#define SC520_GPDMANXTADDH7	0x0dae		/* GP-DMA Channel 7 Next Address High */
+#define SC520_GPDMANXTTCL3	0x0db0		/* GP-DMA Channel 3 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH3	0x0db2		/* GP-DMA Channel 3 Next Transfer Count High */
+#define SC520_GPDMANXTTCL5	0x0db4		/* GP-DMA Channel 5 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH5	0x0db6		/* GP-DMA Channel 5 Next Transfer Count High */
+#define SC520_GPDMANXTTCL6	0x0db8		/* GP-DMA Channel 6 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH6	0x0dba		/* GP-DMA Channel 6 Next Transfer Count High */
+#define SC520_GPDMANXTTCL7	0x0dbc		/* GP-DMA Channel 7 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH7	0x0dbe		/* GP-DMA Channel 7 Next Transfer Count High */
+
+/* MMCR Register bits (not all of them :) ) */
+
+/* SSI Stuff */
+#define CTL_CLK_SEL_4           0x00           /* Nominal Bit Rate = 8 MHz    */
+#define CTL_CLK_SEL_8           0x10           /* Nominal Bit Rate = 4 MHz    */
+#define CTL_CLK_SEL_16          0x20           /* Nominal Bit Rate = 2 MHz    */
+#define CTL_CLK_SEL_32          0x30           /* Nominal Bit Rate = 1 MHz    */
+#define CTL_CLK_SEL_64          0x40           /* Nominal Bit Rate = 512 KHz  */
+#define CTL_CLK_SEL_128         0x50           /* Nominal Bit Rate = 256 KHz  */
+#define CTL_CLK_SEL_256         0x60           /* Nominal Bit Rate = 128 KHz  */
+#define CTL_CLK_SEL_512         0x70           /* Nominal Bit Rate = 64 KHz   */
+
+#define TC_INT_ENB              0x08           /* Transaction Complete Interrupt Enable */
+#define PHS_INV_ENB             0x04           /* SSI Inverted Phase Mode Enable */
+#define CLK_INV_ENB    	        0x02           /* SSI Inverted Clock Mode Enable */
+#define MSBF_ENB      	        0x01           /* SSI Most Significant Bit First Mode Enable */
+
+#define SSICMD_CMD_SEL_XMITRCV  0x03           /* Simultaneous Transmit / Receive Transaction */
+#define SSICMD_CMD_SEL_RCV      0x02           /* Receive Transaction */
+#define SSICMD_CMD_SEL_XMIT     0x01           /* Transmit Transaction */
+#define SSISTA_BSY              0x02           /* SSI Busy */
+#define SSISTA_TC_INT           0x01           /* SSI Transaction Complete Interrupt */
+
+
+/* BITS for SC520_ADDDECCTL: */
+#define WPV_INT_ENB		0x80		/* Write-Protect Violation Interrupt Enable */
+#define IO_HOLE_DEST_PCI	0x10		/* I/O Hole Access Destination */
+#define RTC_DIS			0x04		/* RTC Disable */
+#define UART2_DIS		0x02		/* UART2 Disable */
+#define UART1_DIS		0x01		/* UART1 Disable */
+
+/* bus mapping constants (used for PCI core initialization) */																																																 /* bus mapping constants */
+#define SC520_REG_ADDR		0x00000cf8
+#define SC520_REG_DATA		0x00000cfc
+
+
+#define SC520_ISA_MEM_PHYS	0x00000000
+#define SC520_ISA_MEM_BUS	0x00000000
+#define SC520_ISA_MEM_SIZE	0x01000000
+
+#define SC520_ISA_IO_PHYS	0x00000000
+#define SC520_ISA_IO_BUS	0x00000000
+#define SC520_ISA_IO_SIZE	0x00001000
+
+/* PCI I/O space from 0x1000 to 0xdfff
+ * (make 0xe000-0xfdff available for stuff like PCCard boot) */
+#define SC520_PCI_IO_PHYS	0x00001000
+#define SC520_PCI_IO_BUS	0x00001000
+#define SC520_PCI_IO_SIZE	0x0000d000
+
+/* system memory from 0x00000000 to 0x0fffffff */
+#define	SC520_PCI_MEMORY_PHYS	0x00000000
+#define	SC520_PCI_MEMORY_BUS	0x00000000
+#define SC520_PCI_MEMORY_SIZE	0x10000000
+
+/* PCI bus memory from 0x10000000 to 0x26ffffff
+ * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */
+#define SC520_PCI_MEM_PHYS	0x10000000
+#define SC520_PCI_MEM_BUS       0x10000000
+#define SC520_PCI_MEM_SIZE	0x17000000
+
+/* 0x28000000 - 0x3fffffff is used by the flash banks */
+
+/* 0x40000000 - 0xffffffff is not adressable by the SC520 */
+
+/* priority numbers used for interrupt channel mappings */
+#define SC520_IRQ_DISABLED 0
+#define SC520_IRQ0  1
+#define SC520_IRQ1  2
+#define SC520_IRQ2  4  /* same as IRQ9 */
+#define SC520_IRQ3  11
+#define SC520_IRQ4  12
+#define SC520_IRQ5  13
+#define SC520_IRQ6  21
+#define SC520_IRQ7  22
+#define SC520_IRQ8  3
+#define SC520_IRQ9  4
+#define SC520_IRQ10 5
+#define SC520_IRQ11 6
+#define SC520_IRQ12 7
+#define SC520_IRQ13 8
+#define SC520_IRQ14 9
+#define SC520_IRQ15 10
+
+
+/* pin number used for PCI interrupt mappings */
+#define SC520_PCI_INTA 0
+#define SC520_PCI_INTB 1
+#define SC520_PCI_INTC 2
+#define SC520_PCI_INTD 3
+#define SC520_PCI_GPIRQ0 4
+#define SC520_PCI_GPIRQ1 5
+#define SC520_PCI_GPIRQ2 6
+#define SC520_PCI_GPIRQ3 7
+#define SC520_PCI_GPIRQ4 8
+#define SC520_PCI_GPIRQ5 9
+#define SC520_PCI_GPIRQ6 10
+#define SC520_PCI_GPIRQ7 11
+#define SC520_PCI_GPIRQ8 12
+#define SC520_PCI_GPIRQ9 13
+#define SC520_PCI_GPIRQ10 14
+
+/* utility functions */
+void write_mmcr_byte(u16 mmcr, u8 data);
+void write_mmcr_word(u16 mmcr, u16 data);
+void write_mmcr_long(u16 mmcr, u32 data);
+u8 read_mmcr_byte(u16 mmcr);
+u16 read_mmcr_word(u16 mmcr);
+u32 read_mmcr_long(u16 mmcr);
+
+extern int sc520_pci_ints[];
+
+void init_sc520(void);
+unsigned long init_sc520_dram(void);
+void pci_sc520_init(struct pci_controller *hose);
+int pci_sc520_set_irq(int pci_pin, int irq);
+
+#endif
diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h
new file mode 100755
index 0000000..85d44aa
--- /dev/null
+++ b/include/asm-i386/io.h
@@ -0,0 +1,204 @@
+#ifndef _ASM_IO_H
+#define _ASM_IO_H
+
+/*
+ * This file contains the definitions for the x86 IO instructions
+ * inb/inw/inl/outb/outw/outl and the "string versions" of the same
+ * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
+ * versions of the single-IO instructions (inb_p/inw_p/..).
+ *
+ * This file is not meant to be obfuscating: it's just complicated
+ * to (a) handle it all in a way that makes gcc able to optimize it
+ * as well as possible and (b) trying to avoid writing the same thing
+ * over and over again with slight variations and possibly making a
+ * mistake somewhere.
+ */
+
+/*
+ * Thanks to James van Artsdalen for a better timing-fix than
+ * the two short jumps: using outb's to a nonexistent port seems
+ * to guarantee better timings even on fast machines.
+ *
+ * On the other hand, I'd like to be sure of a non-existent port:
+ * I feel a bit unsafe about using 0x80 (should be safe, though)
+ *
+ *		Linus
+ */
+
+ /*
+  *  Bit simplified and optimized by Jan Hubicka
+  *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
+  *
+  *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
+  *  isa_read[wl] and isa_write[wl] fixed
+  *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
+  */
+
+#define IO_SPACE_LIMIT 0xffff
+
+
+#ifdef __KERNEL__
+
+
+/*
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the x86 architecture, we just read/write the
+ * memory location directly.
+ */
+
+#define readb(addr) (*(volatile unsigned char *) (addr))
+#define readw(addr) (*(volatile unsigned short *) (addr))
+#define readl(addr) (*(volatile unsigned int *) (addr))
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+
+#define writeb(b,addr) (*(volatile unsigned char *) (addr) = (b))
+#define writew(b,addr) (*(volatile unsigned short *) (addr) = (b))
+#define writel(b,addr) (*(volatile unsigned int *) (addr) = (b))
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+
+#define memset_io(a,b,c)	memset((a),(b),(c))
+#define memcpy_fromio(a,b,c)	memcpy((a),(b),(c))
+#define memcpy_toio(a,b,c)	memcpy((a),(b),(c))
+
+/*
+ * ISA space is 'always mapped' on a typical x86 system, no need to
+ * explicitly ioremap() it. The fact that the ISA IO space is mapped
+ * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
+ * are physical addresses. The following constant pointer can be
+ * used as the IO-area pointer (it can be iounmapped as well, so the
+ * analogy with PCI is quite large):
+ */
+#define isa_readb(a) readb((a))
+#define isa_readw(a) readw((a))
+#define isa_readl(a) readl((a))
+#define isa_writeb(b,a) writeb(b,(a))
+#define isa_writew(w,a) writew(w,(a))
+#define isa_writel(l,a) writel(l,(a))
+#define isa_memset_io(a,b,c)		memset_io((a),(b),(c))
+#define isa_memcpy_fromio(a,b,c)	memcpy_fromio((a),(b),(c))
+#define isa_memcpy_toio(a,b,c)		memcpy_toio((a),(b),(c))
+
+
+static inline int check_signature(unsigned long io_addr,
+	const unsigned char *signature, int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+/**
+ *	isa_check_signature		-	find BIOS signatures
+ *	@io_addr: mmio address to check
+ *	@signature:  signature block
+ *	@length: length of signature
+ *
+ *	Perform a signature comparison with the ISA mmio address io_addr.
+ *	Returns 1 on a match.
+ *
+ *	This function is deprecated. New drivers should use ioremap and
+ *	check_signature.
+ */
+
+
+static inline int isa_check_signature(unsigned long io_addr,
+	const unsigned char *signature, int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#endif /* __KERNEL__ */
+
+#ifdef SLOW_IO_BY_JUMPING
+#define __SLOW_DOWN_IO "\njmp 1f\n1:\tjmp 1f\n1:"
+#else
+#define __SLOW_DOWN_IO "\noutb %%al,$0x80"
+#endif
+
+#ifdef REALLY_SLOW_IO
+#define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO
+#else
+#define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO
+#endif
+
+
+/*
+ * Talk about misusing macros..
+ */
+#define __OUT1(s,x) \
+static inline void out##s(unsigned x value, unsigned short port) {
+
+#define __OUT2(s,s1,s2) \
+__asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1"
+
+
+#define __OUT(s,s1,x) \
+__OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "Nd" (port)); } \
+__OUT1(s##_p,x) __OUT2(s,s1,"w") __FULL_SLOW_DOWN_IO : : "a" (value), "Nd" (port));}
+
+#define __IN1(s) \
+static inline RETURN_TYPE in##s(unsigned short port) { RETURN_TYPE _v;
+
+#define __IN2(s,s1,s2) \
+__asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0"
+
+#define __IN(s,s1,i...) \
+__IN1(s) __IN2(s,s1,"w") : "=a" (_v) : "Nd" (port) ,##i ); return _v; } \
+__IN1(s##_p) __IN2(s,s1,"w") __FULL_SLOW_DOWN_IO : "=a" (_v) : "Nd" (port) ,##i ); return _v; }
+
+#define __INS(s) \
+static inline void ins##s(unsigned short port, void * addr, unsigned long count) \
+{ __asm__ __volatile__ ("rep ; ins" #s \
+: "=D" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
+
+#define __OUTS(s) \
+static inline void outs##s(unsigned short port, const void * addr, unsigned long count) \
+{ __asm__ __volatile__ ("rep ; outs" #s \
+: "=S" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
+
+#define RETURN_TYPE unsigned char
+__IN(b,"")
+#undef RETURN_TYPE
+#define RETURN_TYPE unsigned short
+__IN(w,"")
+#undef RETURN_TYPE
+#define RETURN_TYPE unsigned int
+__IN(l,"")
+#undef RETURN_TYPE
+
+__OUT(b,"b",char)
+__OUT(w,"w",short)
+__OUT(l,,int)
+
+__INS(b)
+__INS(w)
+__INS(l)
+
+__OUTS(b)
+__OUTS(w)
+__OUTS(l)
+
+#endif
diff --git a/include/asm-i386/pci.h b/include/asm-i386/pci.h
new file mode 100755
index 0000000..bde9550
--- /dev/null
+++ b/include/asm-i386/pci.h
@@ -0,0 +1,35 @@
+
+
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PCI_I386_H_
+#define _PCI_I386_H_	1
+
+void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
+int pci_enable_legacy_video_ports(struct pci_controller* hose);
+int pci_shadow_rom(pci_dev_t dev, unsigned char *dest);
+void pci_remove_rom_window(struct pci_controller* hose, u32 addr);
+u32 pci_get_rom_window(struct pci_controller* hose, int size);
+
+#endif
diff --git a/include/asm-i386/posix_types.h b/include/asm-i386/posix_types.h
new file mode 100755
index 0000000..5529f32
--- /dev/null
+++ b/include/asm-i386/posix_types.h
@@ -0,0 +1,80 @@
+#ifndef __ARCH_I386_POSIX_TYPES_H
+#define __ARCH_I386_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short	__kernel_dev_t;
+typedef unsigned long	__kernel_ino_t;
+typedef unsigned short	__kernel_mode_t;
+typedef unsigned short	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef unsigned short	__kernel_ipc_pid_t;
+typedef unsigned short	__kernel_uid_t;
+typedef unsigned short	__kernel_gid_t;
+typedef unsigned int	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef int		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned short	__kernel_old_uid_t;
+typedef unsigned short	__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long	__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd,fdsetp) \
+		__asm__ __volatile__("btsl %1,%0": \
+			"=m" (*(__kernel_fd_set *) (fdsetp)):"r" ((int) (fd)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd,fdsetp) \
+		__asm__ __volatile__("btrl %1,%0": \
+			"=m" (*(__kernel_fd_set *) (fdsetp)):"r" ((int) (fd)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd,fdsetp) (__extension__ ({ \
+		unsigned char __result; \
+		__asm__ __volatile__("btl %1,%2 ; setb %0" \
+			:"=q" (__result) :"r" ((int) (fd)), \
+			"m" (*(__kernel_fd_set *) (fdsetp))); \
+		__result; }))
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+do { \
+	int __d0, __d1; \
+	__asm__ __volatile__("cld ; rep ; stosl" \
+			:"=m" (*(__kernel_fd_set *) (fdsetp)), \
+			  "=&c" (__d0), "=&D" (__d1) \
+			:"a" (0), "1" (__FDSET_LONGS), \
+			"2" ((__kernel_fd_set *) (fdsetp)) : "memory"); \
+} while (0)
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif
diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h
new file mode 100755
index 0000000..5dedba8
--- /dev/null
+++ b/include/asm-i386/processor.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_PROCESSOR_H_
+#define __ASM_PROCESSOR_H_ 1
+/* Currently this header is unused in the i386 port
+ * but some generic files #include <asm/processor.h>
+ * so this file is a placeholder. */
+#endif
diff --git a/include/asm-i386/ptrace.h b/include/asm-i386/ptrace.h
new file mode 100755
index 0000000..750e40d
--- /dev/null
+++ b/include/asm-i386/ptrace.h
@@ -0,0 +1,66 @@
+#ifndef _I386_PTRACE_H
+#define _I386_PTRACE_H
+
+#define EBX 0
+#define ECX 1
+#define EDX 2
+#define ESI 3
+#define EDI 4
+#define EBP 5
+#define EAX 6
+#define DS 7
+#define ES 8
+#define FS 9
+#define GS 10
+#define ORIG_EAX 11
+#define EIP 12
+#define CS  13
+#define EFL 14
+#define UESP 15
+#define SS   16
+#define FRAME_SIZE 17
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+struct pt_regs {
+	long ebx;
+	long ecx;
+	long edx;
+	long esi;
+	long edi;
+	long ebp;
+	long eax;
+	int  xds;
+	int  xes;
+	int  xfs;
+	int  xgs;
+	long orig_eax;
+	long eip;
+	int  xcs;
+	long eflags;
+	long esp;
+	int  xss;
+}  __attribute__ ((packed));
+
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+#define PTRACE_GETREGS            12
+#define PTRACE_SETREGS            13
+#define PTRACE_GETFPREGS          14
+#define PTRACE_SETFPREGS          15
+#define PTRACE_GETFPXREGS         18
+#define PTRACE_SETFPXREGS         19
+
+#define PTRACE_SETOPTIONS         21
+
+/* options set using PTRACE_SETOPTIONS */
+#define PTRACE_O_TRACESYSGOOD     0x00000001
+
+#ifdef __KERNEL__
+#define user_mode(regs) ((VM_MASK & (regs)->eflags) || (3 & (regs)->xcs))
+#define instruction_pointer(regs) ((regs)->eip)
+extern void show_regs(struct pt_regs *);
+#endif
+
+#endif
diff --git a/include/asm-i386/realmode.h b/include/asm-i386/realmode.h
new file mode 100755
index 0000000..9177e4e
--- /dev/null
+++ b/include/asm-i386/realmode.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_REALMODE_H_
+#define __ASM_REALMODE_H_
+#include <asm/ptrace.h>
+
+int bios_setup(void);
+int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out);
+int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out);
+
+#endif
diff --git a/include/asm-i386/string.h b/include/asm-i386/string.h
new file mode 100755
index 0000000..91a23f9
--- /dev/null
+++ b/include/asm-i386/string.h
@@ -0,0 +1,30 @@
+#ifndef __ASM_I386_STRING_H
+#define __ASM_I386_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char * strrchr(const char * s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char * strchr(const char * s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void * memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void * memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMSET
+extern void * memset(void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+extern void memzero(void *ptr, __kernel_size_t n);
+
+#endif
diff --git a/include/asm-i386/types.h b/include/asm-i386/types.h
new file mode 100755
index 0000000..69f8a5a
--- /dev/null
+++ b/include/asm-i386/types.h
@@ -0,0 +1,50 @@
+#ifndef __ASM_I386_TYPES_H
+#define __ASM_I386_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/include/asm-i386/u-boot-i386.h b/include/asm-i386/u-boot-i386.h
new file mode 100755
index 0000000..12d10a7
--- /dev/null
+++ b/include/asm-i386/u-boot-i386.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _U_BOOT_I386_H_
+#define _U_BOOT_I386_H_	1
+
+/* for the following variables, see start.S */
+extern ulong i386boot_start;	    /* code start (in flash) */
+extern ulong i386boot_end;	    /* code end (in flash) */
+extern ulong i386boot_romdata_start;/* datasegment in flash (also code+rodata end) */
+extern ulong i386boot_romdata_dest; /* data location segment in ram */
+extern ulong i386boot_romdata_size; /* size of data segment */
+extern ulong i386boot_bss_start;    /* bss start */
+extern ulong i386boot_bss_size;     /* bss size */
+extern ulong i386boot_stack_end;    /* first usable RAM address after bss and stack */
+extern ulong i386boot_ram_end;      /* end of ram */
+
+extern ulong i386boot_realmode;     /* start of realmode entry code */
+extern ulong i386boot_realmode_size;/* size of realmode entry code */
+extern ulong i386boot_bios;         /* start of BIOS emulation code */
+extern ulong i386boot_bios_size;    /* size of BIOS emulation code */
+
+
+/* cpu/.../cpu.c */
+int cpu_init(void);
+int timer_init(void);
+
+/* board/.../... */
+int board_init(void);
+int dram_init(void);
+
+void isa_unmap_rom(u32 addr);
+u32 isa_map_rom(u32 bus_addr, int size);
+
+/* lib_i386/... */
+int video_bios_init(void);
+int video_init(void);
+
+
+#endif	/* _U_BOOT_I386_H_ */
diff --git a/include/asm-i386/u-boot.h b/include/asm-i386/u-boot.h
new file mode 100755
index 0000000..1e19f8f
--- /dev/null
+++ b/include/asm-i386/u-boot.h
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+typedef struct bd_info {
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+	unsigned long	bi_sramstart;	/* start of SRAM memory */
+	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
+	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6];	/* Ethernet adress */
+	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
+	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
+	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
+	unsigned int	bi_baudrate;	/* Console Baudrate */
+	unsigned long   bi_boot_params;	/* where this board expects params */
+	struct environment_s	       *bi_env;
+	struct				/* RAM configuration */
+	{
+		ulong start;
+		ulong size;
+	}bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+#define bi_env_data bi_env->data
+#define bi_env_crc  bi_env->crc
+
+#endif	/* _U_BOOT_H_ */
diff --git a/include/asm-i386/zimage.h b/include/asm-i386/zimage.h
new file mode 100755
index 0000000..c7103b1
--- /dev/null
+++ b/include/asm-i386/zimage.h
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ZIMAGE_H_
+#define _ASM_ZIMAGE_H_
+
+/* linux i386 zImage/bzImage header. Offsets relative to
+ * the start of the image */
+
+#define CMD_LINE_MAGIC_OFF  0x020 /* Magic 0xa33f if the offset below is valid */
+#define CMD_LINE_OFFSET_OFF 0x022 /* Offset to comandline */
+#define SETUP_SECTS_OFF     0x1F1 /* The size of the setup in sectors */
+#define ROOT_FLAGS_OFF      0x1F2 /* If set, the root is mounted readonly */
+#define VID_MODE_OFF        0x1FA /* Video mode control */
+#define ROOT_DEV_OFF        0x1FC /* Default root device number */
+#define BOOT_FLAG_OFF       0x1FE /* 0xAA55 magic number */
+#define HEADER_OFF          0x202 /* Magic signature "HdrS" */
+#define VERSION_OFF         0x206 /* Boot protocol version supported */
+#define REALMODE_SWTCH_OFF  0x208 /* Boot loader hook (see below) */
+#define START_SYS_OFF       0x20C /* Points to kernel version string */
+#define TYPE_OF_LOADER_OFF  0x210 /* Boot loader identifier */
+#define LOADFLAGS_OFF       0x211 /* Boot protocol option flags */
+#define SETUP_MOVE_SIZE_OFF 0x212 /* Move to high memory size (used with hooks) */
+#define CODE32_START_OFF    0x214 /* Boot loader hook (see below) */
+#define RAMDISK_IMAGE_OFF   0x218 /* initrd load address (set by boot loader) */
+#define RAMDISK_SIZE_OFF    0x21C /* initrd size (set by boot loader) */
+#define HEAP_END_PTR_OFF    0x224 /* Free memory after setup end */
+#define CMD_LINE_PTR_OFF    0x228 /* 32-bit pointer to the kernel command line */
+
+
+#define HEAP_FLAG           0x80
+#define BIG_KERNEL_FLAG     0x01
+
+/* magic numbers */
+#define KERNEL_MAGIC        0xaa55
+#define KERNEL_V2_MAGIC     0x53726448
+#define COMMAND_LINE_MAGIC  0xA33F
+
+/* limits */
+#define BZIMAGE_MAX_SIZE   15*1024*1024     /* 15MB */
+#define ZIMAGE_MAX_SIZE    512*1024         /* 512k */
+#define SETUP_MAX_SIZE     32768
+
+#define SETUP_START_OFFSET 0x200
+#define BZIMAGE_LOAD_ADDR  0x100000
+#define ZIMAGE_LOAD_ADDR   0x10000
+
+void *load_zimage(char *image, unsigned long kernel_size,
+		  unsigned long initrd_addr, unsigned long initrd_size,
+		  int auto_boot);
+
+void boot_zimage(void *setup_base);
+image_header_t *fake_zimage_header(image_header_t *hdr, void *ptr, int size);
+
+#endif
diff --git a/include/asm-m68k/bitops.h b/include/asm-m68k/bitops.h
new file mode 100755
index 0000000..3283714
--- /dev/null
+++ b/include/asm-m68k/bitops.h
@@ -0,0 +1,18 @@
+/*
+ * bitops.h: Bit string operations on the m68k
+ */
+
+#ifndef _M68K_BITOPS_H
+#define _M68K_BITOPS_H
+
+#include <linux/config.h>
+#include <asm/byteorder.h>
+
+extern void set_bit(int nr, volatile void *addr);
+extern void clear_bit(int nr, volatile void *addr);
+extern void change_bit(int nr, volatile void *addr);
+extern int test_and_set_bit(int nr, volatile void *addr);
+extern int test_and_clear_bit(int nr, volatile void *addr);
+extern int test_and_change_bit(int nr, volatile void *addr);
+
+#endif /* _M68K_BITOPS_H */
diff --git a/include/asm-m68k/byteorder.h b/include/asm-m68k/byteorder.h
new file mode 100755
index 0000000..ce613ac
--- /dev/null
+++ b/include/asm-m68k/byteorder.h
@@ -0,0 +1,7 @@
+#ifndef _M68K_BYTEORDER_H
+#define _M68K_BYTEORDER_H
+
+#include <asm/types.h>
+#include <linux/byteorder/big_endian.h>
+
+#endif /* _M68K_BYTEORDER_H */
diff --git a/include/asm-m68k/fec.h b/include/asm-m68k/fec.h
new file mode 100755
index 0000000..5bbbfb2
--- /dev/null
+++ b/include/asm-m68k/fec.h
@@ -0,0 +1,86 @@
+/*
+ * fec.h -- Fast Ethernet Controller definitions
+ *
+ * Some definitions copied from commproc.h for MPC8xx:
+ * MPC8xx Communication Processor Module.
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	fec_h
+#define	fec_h
+
+/* Buffer descriptors used FEC.
+*/
+typedef struct cpm_buf_desc {
+	ushort	cbd_sc;		/* Status and Control */
+	ushort	cbd_datlen;	/* Data length in buffer */
+	uint	cbd_bufaddr;	/* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
+#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
+#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
+#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
+#define BD_SC_TC	((ushort)0x0400)	/* Transmit CRC */
+#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
+#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
+#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
+#define BD_SC_BR	((ushort)0x0020)	/* Break received */
+#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
+#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
+#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
+#define BD_SC_CD	((ushort)0x0001)	/* Carrier Detect lost */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+*/
+#define BD_ENET_RX_EMPTY	((ushort)0x8000)
+#define BD_ENET_RX_WRAP		((ushort)0x2000)
+#define BD_ENET_RX_INTR		((ushort)0x1000)
+#define BD_ENET_RX_LAST		((ushort)0x0800)
+#define BD_ENET_RX_FIRST	((ushort)0x0400)
+#define BD_ENET_RX_MISS		((ushort)0x0100)
+#define BD_ENET_RX_LG		((ushort)0x0020)
+#define BD_ENET_RX_NO		((ushort)0x0010)
+#define BD_ENET_RX_SH		((ushort)0x0008)
+#define BD_ENET_RX_CR		((ushort)0x0004)
+#define BD_ENET_RX_OV		((ushort)0x0002)
+#define BD_ENET_RX_CL		((ushort)0x0001)
+#define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+*/
+#define BD_ENET_TX_READY	((ushort)0x8000)
+#define BD_ENET_TX_PAD		((ushort)0x4000)
+#define BD_ENET_TX_WRAP		((ushort)0x2000)
+#define BD_ENET_TX_INTR		((ushort)0x1000)
+#define BD_ENET_TX_LAST		((ushort)0x0800)
+#define BD_ENET_TX_TC		((ushort)0x0400)
+#define BD_ENET_TX_DEF		((ushort)0x0200)
+#define BD_ENET_TX_HB		((ushort)0x0100)
+#define BD_ENET_TX_LC		((ushort)0x0080)
+#define BD_ENET_TX_RL		((ushort)0x0040)
+#define BD_ENET_TX_RCMASK	((ushort)0x003c)
+#define BD_ENET_TX_UN		((ushort)0x0002)
+#define BD_ENET_TX_CSL		((ushort)0x0001)
+#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
+
+#endif	/* fec_h */
diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h
new file mode 100755
index 0000000..f68352f
--- /dev/null
+++ b/include/asm-m68k/global_data.h
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2002 - 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct	global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
+	unsigned long	bus_clk;
+	unsigned long	ram_size;	/* RAM size */
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	reset_status;	/* reset status register at boot	*/
+	unsigned long	env_addr;	/* Address  of Environment struct	*/
+	unsigned long	env_valid;	/* Checksum of Environment valid?	*/
+	unsigned long	have_console;	/* serial_init() was called		*/
+#ifdef CONFIG_BOARD_TYPES
+	unsigned long	board_type;
+#endif
+	void		**jt;		/* Standalone app jump table */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC	0x00001		/* Code was relocated to RAM		*/
+#define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
+#define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
+
+#if 0
+extern gd_t *global_data;
+#define DECLARE_GLOBAL_DATA_PTR     gd_t *gd = global_data
+#else
+#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("d7")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/include/asm-m68k/immap_5249.h b/include/asm-m68k/immap_5249.h
new file mode 100755
index 0000000..a2c1271
--- /dev/null
+++ b/include/asm-m68k/immap_5249.h
@@ -0,0 +1,43 @@
+/*
+ * MCF5249 Internal Memory Map
+ *
+ * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5249__
+#define __IMMAP_5249__
+
+/* Timer module registers
+ */
+typedef struct timer_ctrl {
+	ushort	timer_tmr;
+	ushort	res1;
+	ushort	timer_trr;
+	ushort	res2;
+	ushort	timer_tcap;
+	ushort	res3;
+	ushort	timer_tcn;
+	ushort	res4;
+	ushort	timer_ter;
+	uchar	res5[14];
+} timer_t;
+
+#endif /* __IMMAP_5249__ */
diff --git a/include/asm-m68k/immap_5272.h b/include/asm-m68k/immap_5272.h
new file mode 100755
index 0000000..ecb4906
--- /dev/null
+++ b/include/asm-m68k/immap_5272.h
@@ -0,0 +1,447 @@
+/*
+ * MCF5272 Internal Memory Map
+ *
+ * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5272__
+#define __IMMAP_5272__
+
+/* System configuration registers
+*/
+typedef	struct sys_ctrl {
+	uint	sc_mbar;
+	ushort	sc_scr;
+	ushort	sc_spr;
+	uint	sc_pmr;
+	char	res1[2];
+	ushort	sc_alpr;
+	uint	sc_dir;
+	char	res2[12];
+} sysctrl_t;
+
+/* Interrupt module registers
+*/
+typedef struct int_ctrl {
+	uint	int_icr1;
+	uint	int_icr2;
+	uint	int_icr3;
+	uint	int_icr4;
+	uint	int_isr;
+	uint	int_pitr;
+	uint	int_piwr;
+	uchar	res1[3];
+	uchar	int_pivr;
+} intctrl_t;
+
+/* Chip select module registers.
+*/
+typedef struct	cs_ctlr {
+	uint	cs_br0;
+	uint	cs_or0;
+	uint	cs_br1;
+	uint	cs_or1;
+	uint	cs_br2;
+	uint	cs_or2;
+	uint	cs_br3;
+	uint	cs_or3;
+	uint	cs_br4;
+	uint	cs_or4;
+	uint	cs_br5;
+	uint	cs_or5;
+	uint	cs_br6;
+	uint	cs_or6;
+	uint	cs_br7;
+	uint	cs_or7;
+} csctrl_t;
+
+/* GPIO port registers
+*/
+typedef struct	gpio_ctrl {
+	uint	gpio_pacnt;
+	ushort	gpio_paddr;
+	ushort	gpio_padat;
+	uint	gpio_pbcnt;
+	ushort	gpio_pbddr;
+	ushort	gpio_pbdat;
+	uchar	res1[4];
+	ushort	gpio_pcddr;
+	ushort	gpio_pcdat;
+	uint	gpio_pdcnt;
+	uchar	res2[4];
+} gpio_t;
+
+/* QSPI module registers
+ */
+typedef struct	qspi_ctrl {
+	ushort	qspi_qmr;
+	uchar	res1[2];
+	ushort	qspi_qdlyr;
+	uchar	res2[2];
+	ushort	qspi_qwr;
+	uchar	res3[2];
+	ushort	qspi_qir;
+	uchar	res4[2];
+	ushort	qspi_qar;
+	uchar	res5[2];
+	ushort	qspi_qdr;
+	uchar	res6[10];
+} qspi_t;
+
+/* PWM module registers
+ */
+typedef struct	pwm_ctrl {
+	uchar	pwm_pwcr0;
+	uchar	res1[3];
+	uchar	pwm_pwcr1;
+	uchar	res2[3];
+	uchar	pwm_pwcr2;
+	uchar	res3[7];
+	uchar	pwm_pwwd0;
+	uchar	res4[3];
+	uchar	pwm_pwwd1;
+	uchar	res5[3];
+	uchar	pwm_pwwd2;
+	uchar	res6[7];
+} pwm_t;
+
+/* DMA module registers
+ */
+typedef struct	dma_ctrl {
+	ulong	dma_dmr;
+	uchar	res1[2];
+	ushort	dma_dir;
+	ulong	dma_dbcr;
+	ulong	dma_dsar;
+	ulong	dma_ddar;
+	uchar	res2[12];
+} dma_t;
+
+/* UART module registers
+ */
+typedef struct uart_ctrl {
+	uchar	uart_umr;
+	uchar	res1[3];
+	uchar	uart_usr_ucsr;
+	uchar	res2[3];
+	uchar	uart_ucr;
+	uchar	res3[3];
+	uchar	uart_urb_utb;
+	uchar	res4[3];
+	uchar	uart_uipcr_uacr;
+	uchar	res5[3];
+	uchar	uart_uisr_uimr;
+	uchar	res6[3];
+	uchar	uart_udu;
+	uchar	res7[3];
+	uchar	uart_udl;
+	uchar	res8[3];
+	uchar	uart_uabu;
+	uchar	res9[3];
+	uchar	uart_uabl;
+	uchar	res10[3];
+	uchar	uart_utf;
+	uchar	res11[3];
+	uchar	uart_urf;
+	uchar	res12[3];
+	uchar	uart_ufpd;
+	uchar	res13[3];
+	uchar	uart_uip;
+	uchar	res14[3];
+	uchar	uart_uop1;
+	uchar	res15[3];
+	uchar	uart_uop0;
+	uchar	res16[3];
+} uart_t;
+
+/* SDRAM controller registers, offset: 0x180
+ */
+typedef struct sdram_ctrl {
+	uchar   res1[2];
+	ushort	sdram_sdcr;
+	uchar	res2[2];
+	ushort	sdram_sdtr;
+	uchar	res3[120];
+} sdramctrl_t;
+
+/* Timer module registers
+ */
+typedef struct timer_ctrl {
+	ushort	timer_tmr;
+	ushort	res1;
+	ushort	timer_trr;
+	ushort	res2;
+	ushort	timer_tcap;
+	ushort	res3;
+	ushort	timer_tcn;
+	ushort	res4;
+	ushort	timer_ter;
+	uchar	res5[14];
+} timer_t;
+
+/* Watchdog registers
+ */
+typedef struct wdog_ctrl {
+	ushort	wdog_wrrr;
+	ushort	res1;
+	ushort	wdog_wirr;
+	ushort	res2;
+	ushort	wdog_wcr;
+	ushort	res3;
+	ushort	wdog_wer;
+	uchar	res4[114];
+} wdog_t;
+
+/* PLIC module registers
+ */
+typedef struct plic_ctrl {
+	ulong	plic_p0b1rr;
+	ulong	plic_p1b1rr;
+	ulong	plic_p2b1rr;
+	ulong	plic_p3b1rr;
+	ulong	plic_p0b2rr;
+	ulong	plic_p1b2rr;
+	ulong	plic_p2b2rr;
+	ulong	plic_p3b2rr;
+	uchar	plic_p0drr;
+	uchar	plic_p1drr;
+	uchar	plic_p2drr;
+	uchar	plic_p3drr;
+	uchar	res1[4];
+	ulong	plic_p0b1tr;
+	ulong	plic_p1b1tr;
+	ulong	plic_p2b1tr;
+	ulong	plic_p3b1tr;
+	ulong	plic_p0b2tr;
+	ulong	plic_p1b2tr;
+	ulong	plic_p2b2tr;
+	ulong	plic_p3b2tr;
+	uchar	plic_p0dtr;
+	uchar	plic_p1dtr;
+	uchar	plic_p2dtr;
+	uchar	plic_p3dtr;
+	uchar	res2[4];
+	ushort	plic_p0cr;
+	ushort	plic_p1cr;
+	ushort	plic_p2cr;
+	ushort	plic_p3cr;
+	ushort	plic_p0icr;
+	ushort	plic_p1icr;
+	ushort	plic_p2icr;
+	ushort	plic_p3icr;
+	ushort	plic_p0gmr;
+	ushort	plic_p1gmr;
+	ushort	plic_p2gmr;
+	ushort	plic_p3gmr;
+	ushort	plic_p0gmt;
+	ushort	plic_p1gmt;
+	ushort	plic_p2gmt;
+	ushort	plic_p3gmt;
+	uchar	res3;
+	uchar	plic_pgmts;
+	uchar	plic_pgmta;
+	uchar	res4;
+	uchar	plic_p0gcir;
+	uchar	plic_p1gcir;
+	uchar	plic_p2gcir;
+	uchar	plic_p3gcir;
+	uchar	plic_p0gcit;
+	uchar	plic_p1gcit;
+	uchar	plic_p2gcit;
+	uchar	plic_p3gcit;
+	uchar	res5[3];
+	uchar	plic_pgcitsr;
+	uchar	res6[3];
+	uchar	plic_pdcsr;
+	ushort	plic_p0psr;
+	ushort	plic_p1psr;
+	ushort	plic_p2psr;
+	ushort	plic_p3psr;
+	ushort	plic_pasr;
+	uchar	res7;
+	uchar	plic_plcr;
+	ushort	res8;
+	ushort	plic_pdrqr;
+	ushort	plic_p0sdr;
+	ushort	plic_p1sdr;
+	ushort	plic_p2sdr;
+	ushort	plic_p3sdr;
+	ushort	res9;
+	ushort	plic_pcsr;
+	uchar	res10[1184];
+} plic_t;
+
+/* Fast ethernet controller registers
+ */
+typedef struct fec {
+	uint	fec_ecntrl;		/* ethernet control register		*/
+	uint	fec_ievent;		/* interrupt event register		*/
+	uint	fec_imask;		/* interrupt mask register		*/
+	uint	fec_ivec;		/* interrupt level and vector status	*/
+	uint	fec_r_des_active;	/* Rx ring updated flag			*/
+	uint	fec_x_des_active;	/* Tx ring updated flag			*/
+	uint	res3[10];		/* reserved				*/
+	uint	fec_mii_data;		/* MII data register			*/
+	uint	fec_mii_speed;		/* MII speed control register		*/
+	uint	res4[17];		/* reserved				*/
+	uint	fec_r_bound;		/* end of RAM (read-only)		*/
+	uint	fec_r_fstart;		/* Rx FIFO start address		*/
+	uint	res5[6];		/* reserved				*/
+	uint	fec_x_fstart;		/* Tx FIFO start address		*/
+	uint	res7[21];		/* reserved				*/
+	uint	fec_r_cntrl;		/* Rx control register			*/
+	uint	fec_r_hash;		/* Rx hash register			*/
+	uint	res8[14];		/* reserved				*/
+	uint	fec_x_cntrl;		/* Tx control register			*/
+	uint	res9[0x9e];		/* reserved				*/
+	uint	fec_addr_low;		/* lower 32 bits of station address	*/
+	uint	fec_addr_high;		/* upper 16 bits of station address	*/
+	uint	fec_hash_table_high;	/* upper 32-bits of hash table		*/
+	uint	fec_hash_table_low;	/* lower 32-bits of hash table		*/
+	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
+	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
+	uint	fec_r_buff_size;	/* Rx buffer size			*/
+	uint	res2[9];		/* reserved				*/
+	uchar	fec_fifo[960];		/* fifo RAM				*/
+} fec_t;
+
+/* USB module registers
+*/
+typedef struct usb {
+	ushort	res1;
+	ushort	usb_fnr;
+	ushort	res2;
+	ushort	usb_fnmr;
+	ushort	res3;
+	ushort	usb_rfmr;
+	ushort	res4;
+	ushort	usb_rfmmr;
+	uchar	res5[3];
+	uchar	usb_far;
+	ulong	usb_asr;
+	ulong	usb_drr1;
+	ulong	usb_drr2;
+	ushort	res6;
+	ushort	usb_specr;
+	ushort	res7;
+	ushort	usb_ep0sr;
+	ulong	usb_iep0cfg;
+	ulong	usb_oep0cfg;
+	ulong	usb_ep1cfg;
+	ulong	usb_ep2cfg;
+	ulong	usb_ep3cfg;
+	ulong	usb_ep4cfg;
+	ulong	usb_ep5cfg;
+	ulong	usb_ep6cfg;
+	ulong	usb_ep7cfg;
+	ulong	usb_ep0ctl;
+	ushort	res8;
+	ushort	usb_ep1ctl;
+	ushort	res9;
+	ushort	usb_ep2ctl;
+	ushort	res10;
+	ushort	usb_ep3ctl;
+	ushort	res11;
+	ushort	usb_ep4ctl;
+	ushort	res12;
+	ushort	usb_ep5ctl;
+	ushort	res13;
+	ushort	usb_ep6ctl;
+	ushort	res14;
+	ushort	usb_ep7ctl;
+	ulong	usb_ep0isr;
+	ushort	res15;
+	ushort	usb_ep1isr;
+	ushort	res16;
+	ushort	usb_ep2isr;
+	ushort	res17;
+	ushort	usb_ep3isr;
+	ushort	res18;
+	ushort	usb_ep4isr;
+	ushort	res19;
+	ushort	usb_ep5isr;
+	ushort	res20;
+	ushort	usb_ep6isr;
+	ushort	res21;
+	ushort	usb_ep7isr;
+	ulong	usb_ep0imr;
+	ushort	res22;
+	ushort	usb_ep1imr;
+	ushort	res23;
+	ushort	usb_ep2imr;
+	ushort	res24;
+	ushort	usb_ep3imr;
+	ushort	res25;
+	ushort	usb_ep4imr;
+	ushort	res26;
+	ushort	usb_ep5imr;
+	ushort	res27;
+	ushort	usb_ep6imr;
+	ushort	res28;
+	ushort	usb_ep7imr;
+	ulong	usb_ep0dr;
+	ulong	usb_ep1dr;
+	ulong	usb_ep2dr;
+	ulong	usb_ep3dr;
+	ulong	usb_ep4dr;
+	ulong	usb_ep5dr;
+	ulong	usb_ep6dr;
+	ulong	usb_ep7dr;
+	ushort	res29;
+	ushort	usb_ep0dpr;
+	ushort	res30;
+	ushort	usb_ep1dpr;
+	ushort	res31;
+	ushort	usb_ep2dpr;
+	ushort	res32;
+	ushort	usb_ep3dpr;
+	ushort	res33;
+	ushort	usb_ep4dpr;
+	ushort	res34;
+	ushort	usb_ep5dpr;
+	ushort	res35;
+	ushort	usb_ep6dpr;
+	ushort	res36;
+	ushort	usb_ep7dpr;
+	uchar	res37[788];
+	uchar	usb_cfgram[1024];
+} usb_t;
+
+/* Internal memory map.
+*/
+typedef struct immap {
+	sysctrl_t	sysctrl_reg;	/* System configuration registers */
+	intctrl_t	intctrl_reg;	/* Interrupt controller registers */
+	csctrl_t	csctrl_reg;	/* Chip select controller registers */
+	gpio_t		gpio_reg;	/* GPIO controller registers */
+	qspi_t		qspi_reg;	/* QSPI controller registers */
+	pwm_t		pwm_reg;	/* Pulse width modulation registers */
+	dma_t		dma_reg;	/* DMA registers */
+	uart_t		uart_reg[2];	/* UART registers */
+	sdramctrl_t	sdram_reg;	/* SDRAM controller registers */
+	timer_t		timer_reg[4];	/* Timer registers */
+	wdog_t		wdog_reg;	/* Watchdog registers */
+	plic_t		plic_reg;	/* Physical layer interface registers */
+	fec_t		fec_reg;	/* Fast ethernet controller registers */
+	usb_t		usb_reg;	/* USB controller registers */
+} immap_t;
+
+#endif /* __IMMAP_5272__ */
diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h
new file mode 100755
index 0000000..f2b77db
--- /dev/null
+++ b/include/asm-m68k/immap_5282.h
@@ -0,0 +1,63 @@
+/*
+ * MCF5282 Internal Memory Map
+ *
+ * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5282__
+#define __IMMAP_5282__
+
+
+/* Fast ethernet controller registers
+ */
+typedef struct fec {
+	uint	fec_ecntrl;		/* ethernet control register		*/
+	uint	fec_ievent;		/* interrupt event register		*/
+	uint	fec_imask;		/* interrupt mask register		*/
+	uint	fec_ivec;		/* interrupt level and vector status	*/
+	uint	fec_r_des_active;	/* Rx ring updated flag			*/
+	uint	fec_x_des_active;	/* Tx ring updated flag			*/
+	uint	res3[10];		/* reserved				*/
+	uint	fec_mii_data;		/* MII data register			*/
+	uint	fec_mii_speed;		/* MII speed control register		*/
+	uint	res4[17];		/* reserved				*/
+	uint	fec_r_bound;		/* end of RAM (read-only)		*/
+	uint	fec_r_fstart;		/* Rx FIFO start address		*/
+	uint	res5[6];		/* reserved				*/
+	uint	fec_x_fstart;		/* Tx FIFO start address		*/
+	uint	res7[21];		/* reserved				*/
+	uint	fec_r_cntrl;		/* Rx control register			*/
+	uint	fec_r_hash;		/* Rx hash register			*/
+	uint	res8[14];		/* reserved				*/
+	uint	fec_x_cntrl;		/* Tx control register			*/
+	uint	res9[0x9e];		/* reserved				*/
+	uint	fec_addr_low;		/* lower 32 bits of station address	*/
+	uint	fec_addr_high;		/* upper 16 bits of station address	*/
+	uint	fec_hash_table_high;	/* upper 32-bits of hash table		*/
+	uint	fec_hash_table_low;	/* lower 32-bits of hash table		*/
+	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
+	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
+	uint	fec_r_buff_size;	/* Rx buffer size			*/
+	uint	res2[9];		/* reserved				*/
+	uchar	fec_fifo[960];		/* fifo RAM				*/
+} fec_t;
+
+#endif /* __IMMAP_5282__ */
diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h
new file mode 100755
index 0000000..79a9626
--- /dev/null
+++ b/include/asm-m68k/io.h
@@ -0,0 +1 @@
+/* */
diff --git a/include/asm-m68k/m5249.h b/include/asm-m68k/m5249.h
new file mode 100755
index 0000000..8c1b077
--- /dev/null
+++ b/include/asm-m68k/m5249.h
@@ -0,0 +1,187 @@
+/*
+ * mcf5249.h -- Definitions for Motorola Coldfire 5249
+ *
+ * Based on mcf5272sim.h of uCLinux distribution:
+ *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
+ *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef	mcf5249_h
+#define	mcf5249_h
+/****************************************************************************/
+
+/*
+ * useful definitions for reading/writing MBAR offset memory
+ */
+#define mbar_readLong(x)      *((volatile unsigned long *) (CFG_MBAR + x))
+#define mbar_writeLong(x,y)   *((volatile unsigned long *) (CFG_MBAR + x)) = y
+#define mbar_writeShort(x,y)  *((volatile unsigned short *) (CFG_MBAR + x)) = y
+#define mbar_writeByte(x,y)   *((volatile unsigned char *) (CFG_MBAR + x)) = y
+#define mbar2_readLong(x)     *((volatile unsigned long *) (CFG_MBAR2 + x))
+#define mbar2_writeLong(x,y)  *((volatile unsigned long *) (CFG_MBAR2 + x)) = y
+#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y
+#define mbar2_writeByte(x,y)  *((volatile unsigned char *) (CFG_MBAR2 + x)) = y
+
+
+/*
+ * Size of internal RAM
+ */
+
+#define INT_RAM_SIZE 32768  /* RAMBAR0 - 32k */
+#define INT_RAM_SIZE2 65536  /* RAMBAR1 - 64k */
+
+/*
+ *	Define the 5249 SIM register set addresses.
+ */
+
+/*****************
+ ***** MBAR1 *****
+ *****************/
+#define	MCFSIM_RSR		0x00		/* Reset Status reg (r/w) */
+#define	MCFSIM_SYPCR		0x01		/* System Protection reg (r/w)*/
+#define	MCFSIM_SWIVR		0x02		/* SW Watchdog intr reg (r/w) */
+#define	MCFSIM_SWSR		0x03		/* SW Watchdog service (r/w) */
+#define MCFSIM_MPARK  		0x0c 		/* Bus master park register (r/w) */
+
+#define	MCFSIM_SIMR		0x00		/* SIM Config reg (r/w) */
+#define	MCFSIM_ICR0		0x4c		/* Intr Ctrl reg 0 (r/w) */
+#define	MCFSIM_ICR1		0x4d		/* Intr Ctrl reg 1 (r/w) */
+#define	MCFSIM_ICR2		0x4e		/* Intr Ctrl reg 2 (r/w) */
+#define	MCFSIM_ICR3		0x4f		/* Intr Ctrl reg 3 (r/w) */
+#define	MCFSIM_ICR4		0x50		/* Intr Ctrl reg 4 (r/w) */
+#define	MCFSIM_ICR5		0x51		/* Intr Ctrl reg 5 (r/w) */
+#define	MCFSIM_ICR6		0x52		/* Intr Ctrl reg 6 (r/w) */
+#define	MCFSIM_ICR7		0x53		/* Intr Ctrl reg 7 (r/w) */
+#define	MCFSIM_ICR8		0x54		/* Intr Ctrl reg 8 (r/w) */
+#define	MCFSIM_ICR9		0x55		/* Intr Ctrl reg 9 (r/w) */
+#define	MCFSIM_ICR10		0x56		/* Intr Ctrl reg 10 (r/w) */
+#define	MCFSIM_ICR11		0x57		/* Intr Ctrl reg 11 (r/w) */
+
+#define MCFSIM_IPR		0x40		/* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR		0x44		/* Interrupt Mask reg (r/w) */
+
+#define MCFSIM_CSAR0		0x80		/* CS 0 Address 0 reg (r/w) */
+#define MCFSIM_CSMR0		0x84		/* CS 0 Mask 0 reg (r/w) */
+#define MCFSIM_CSCR0		0x8a		/* CS 0 Control reg (r/w) */
+#define MCFSIM_CSAR1		0x8c		/* CS 1 Address reg (r/w) */
+#define MCFSIM_CSMR1		0x90		/* CS 1 Mask reg (r/w) */
+#define MCFSIM_CSCR1		0x96		/* CS 1 Control reg (r/w) */
+#define MCFSIM_CSAR2		0x98		/* CS 2 Address reg (r/w) */
+#define MCFSIM_CSMR2		0x9c		/* CS 2 Mask reg (r/w) */
+#define MCFSIM_CSCR2		0xa2		/* CS 2 Control reg (r/w) */
+#define MCFSIM_CSAR3		0xa4		/* CS 3 Address reg (r/w) */
+#define MCFSIM_CSMR3		0xa8		/* CS 3 Mask reg (r/w) */
+#define MCFSIM_CSCR3		0xae		/* CS 3 Control reg (r/w) */
+
+#define MCFSIM_DCR		0x100		/* DRAM Control reg (r/w) */
+#define MCFSIM_DACR0		0x108		/* DRAM 0 Addr and Ctrl (r/w) */
+#define MCFSIM_DMR0		0x10c		/* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DACR1		0x110		/* DRAM 1 Addr and Ctrl (r/w) */
+#define MCFSIM_DMR1		0x114		/* DRAM 1 Mask reg (r/w) */
+
+/** UART Bases **/
+#define MCFUART_BASE1		0x1c0           /* Base address of UART1 */
+#define MCFUART_BASE2		0x200           /* Base address of UART2 */
+
+/*****************
+ ***** MBAR2 *****
+ *****************/
+
+/*  GPIO Addresses
+ *  Note: These are offset from MBAR2!
+ */
+#define MCFSIM_GPIO_READ 	0x00 		/* Read-Only access to gpio 0-31 (MBAR2) (r) */
+#define MCFSIM_GPIO_OUT 	0x04    	/* Output register for gpio 0-31 (MBAR2) (r/w)*/
+#define MCFSIM_GPIO_EN 		0x08 		/* gpio 0-31 enable (r/w)*/
+#define MCFSIM_GPIO_FUNC 	0x0c 		/* gpio 0-31 function select (r/w) */
+#define MCFSIM_GPIO1_READ 	0xb0 		/* Read-Only access to gpio 32-63 (MBAR2) (r) */
+#define MCFSIM_GPIO1_OUT 	0xb4    	/* Output register for gpio 32-63 (MBAR2) (r/w) */
+#define MCFSIM_GPIO1_EN 	0xb8 		/* gpio 32-63 enable (r/w) */
+#define MCFSIM_GPIO1_FUNC 	0xbc 		/* gpio 32-63 function select (r/w) */
+
+#define MCFSIM_GPIO_INT_STAT 	0xc0  		/* Secondary Interrupt status (r) */
+#define MCFSIM_GPIO_INT_CLEAR 	0xc0  		/* Secondary Interrupt status (w) */
+#define MCFSIM_GPIO_INT_EN 	0xc4  		/* Secondary Interrupt status (r/w) */
+
+#define MCFSIM_INT_STAT3 	0xe0 		/* 3rd Interrupt ctrl status (r) */
+#define MCFSIM_INT_CLEAR3 	0xe0 		/* 3rd Interrupt ctrl clear (w) */
+#define MCFSIM_INT_EN3 		0xe4 		/* 3rd Interrupt ctrl enable (r/w) */
+
+#define MCFSIM_INTLEV1 		0x140 		/* Interrupts 0 - 7 (r/w) */
+#define MCFSIM_INTLEV2 		0x144 		/* Interrupts 8 -15 (r/w) */
+#define MCFSIM_INTLEV3 		0x148 		/* Interrupts 16-23 (r/w) */
+#define MCFSIM_INTLEV4 		0x14c 		/* Interrupts 24-31 (r/w) */
+#define MCFSIM_INTLEV5 		0x150 		/* Interrupts 32-39 (r/w) */
+#define MCFSIM_INTLEV6 		0x154 		/* Interrupts 40-47 (r/w) */
+#define MCFSIM_INTLEV7 		0x158 		/* Interrupts 48-55 (r/w) */
+#define MCFSIM_INTLEV8 		0x15c 		/* Interrupts 56-63 (r/w) */
+
+#define MCFSIM_SPURVEC 		0x167 		/* Spurious Vector Register (r/w) */
+#define MCFSIM_INTBASE 		0x16b 		/* Software interrupt base address (r/w) */
+
+#define MCFSIM_IDECONFIG1 	0x18c 		/* IDE config register 1 (r/w) */
+#define MCFSIM_IDECONFIG2 	0x190 		/* IDE config register 1 (r/w) */
+
+#define MCFSIM_PLLCR 		0x180 		/* PLL Control register */
+
+/*
+ *  Some symbol defines for the above...
+ */
+#define	MCFSIM_SWDICR		MCFSIM_ICR0	/* Watchdog timer ICR */
+#define	MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */
+#define	MCFSIM_TIMER2ICR	MCFSIM_ICR2	/* Timer 2 ICR */
+#define	MCFSIM_I2CICR		MCFSIM_ICR3	/* I2C ICR */
+#define	MCFSIM_UART1ICR		MCFSIM_ICR4	/* UART 1 ICR */
+#define	MCFSIM_UART2ICR		MCFSIM_ICR5	/* UART 2 ICR */
+/* XXX - If needed, DMA ICRs go here */
+#define	MCFSIM_QSPIICR		MCFSIM_ICR10	/* QSPI ICR */
+
+/*
+ *	Bit definitions for the ICR family of registers.
+ */
+#define	MCFSIM_ICR_AUTOVEC	0x80		/* Auto-vectored intr */
+#define	MCFSIM_ICR_LEVEL0	0x00		/* Level 0 intr */
+#define	MCFSIM_ICR_LEVEL1	0x04		/* Level 1 intr */
+#define	MCFSIM_ICR_LEVEL2	0x08		/* Level 2 intr */
+#define	MCFSIM_ICR_LEVEL3	0x0c		/* Level 3 intr */
+#define	MCFSIM_ICR_LEVEL4	0x10		/* Level 4 intr */
+#define	MCFSIM_ICR_LEVEL5	0x14		/* Level 5 intr */
+#define	MCFSIM_ICR_LEVEL6	0x18		/* Level 6 intr */
+#define	MCFSIM_ICR_LEVEL7	0x1c		/* Level 7 intr */
+
+#define	MCFSIM_ICR_PRI0		0x00		/* Priority 0 intr */
+#define	MCFSIM_ICR_PRI1		0x01		/* Priority 1 intr */
+#define	MCFSIM_ICR_PRI2		0x02		/* Priority 2 intr */
+#define	MCFSIM_ICR_PRI3		0x03		/* Priority 3 intr */
+
+
+/*
+ *  Macros to read/set IMR register. It is 32 bits on the 5249.
+ */
+
+#define	mcf_getimr()		\
+	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
+
+#define	mcf_setimr(imr)		\
+	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
+
+#endif	/* mcf5249_h */
diff --git a/include/asm-m68k/m5272.h b/include/asm-m68k/m5272.h
new file mode 100755
index 0000000..54d4a32
--- /dev/null
+++ b/include/asm-m68k/m5272.h
@@ -0,0 +1,99 @@
+/*
+ * mcf5272.h -- Definitions for Motorola Coldfire 5272
+ *
+ * Based on mcf5272sim.h of uCLinux distribution:
+ *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
+ *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef	mcf5272_h
+#define	mcf5272_h
+/****************************************************************************/
+
+/*
+ * Size of internal RAM
+ */
+
+#define INT_RAM_SIZE 4096
+
+
+/*
+ *	Define the 5272 SIM register set addresses.
+ */
+#define	MCFSIM_SCR		0x04		/* SIM Config reg (r/w) */
+#define	MCFSIM_SPR		0x06		/* System Protection reg (r/w)*/
+#define	MCFSIM_PMR		0x08		/* Power Management reg (r/w) */
+#define	MCFSIM_APMR		0x0e		/* Active Low Power reg (r/w) */
+#define	MCFSIM_DIR		0x10		/* Device Identity reg (r/w) */
+
+#define	MCFSIM_ICR1		0x20		/* Intr Ctrl reg 1 (r/w) */
+#define	MCFSIM_ICR2		0x24		/* Intr Ctrl reg 2 (r/w) */
+#define	MCFSIM_ICR3		0x28		/* Intr Ctrl reg 3 (r/w) */
+#define	MCFSIM_ICR4		0x2c		/* Intr Ctrl reg 4 (r/w) */
+
+#define MCFSIM_ISR		0x30		/* Interrupt Source reg (r/w) */
+#define MCFSIM_PITR		0x34		/* Interrupt Transition (r/w) */
+#define	MCFSIM_PIWR		0x38		/* Interrupt Wakeup reg (r/w) */
+#define	MCFSIM_PIVR		0x3f		/* Interrupt Vector reg (r/w( */
+
+#define	MCFSIM_WRRR		0x280		/* Watchdog reference (r/w) */
+#define	MCFSIM_WIRR		0x284		/* Watchdog interrupt (r/w) */
+#define	MCFSIM_WCR		0x288		/* Watchdog counter (r/w) */
+#define	MCFSIM_WER		0x28c		/* Watchdog event (r/w) */
+
+#define	MCFSIM_CSBR0		0x40		/* CS0 Base Address (r/w) */
+#define	MCFSIM_CSOR0		0x44		/* CS0 Option (r/w) */
+#define	MCFSIM_CSBR1		0x48		/* CS1 Base Address (r/w) */
+#define	MCFSIM_CSOR1		0x4c		/* CS1 Option (r/w) */
+#define	MCFSIM_CSBR2		0x50		/* CS2 Base Address (r/w) */
+#define	MCFSIM_CSOR2		0x54		/* CS2 Option (r/w) */
+#define	MCFSIM_CSBR3		0x58		/* CS3 Base Address (r/w) */
+#define	MCFSIM_CSOR3		0x5c		/* CS3 Option (r/w) */
+#define	MCFSIM_CSBR4		0x60		/* CS4 Base Address (r/w) */
+#define	MCFSIM_CSOR4		0x64		/* CS4 Option (r/w) */
+#define	MCFSIM_CSBR5		0x68		/* CS5 Base Address (r/w) */
+#define	MCFSIM_CSOR5		0x6c		/* CS5 Option (r/w) */
+#define	MCFSIM_CSBR6		0x70		/* CS6 Base Address (r/w) */
+#define	MCFSIM_CSOR6		0x74		/* CS6 Option (r/w) */
+#define	MCFSIM_CSBR7		0x78		/* CS7 Base Address (r/w) */
+#define	MCFSIM_CSOR7		0x7c		/* CS7 Option (r/w) */
+
+#define	MCFSIM_SDCR		0x180		/* SDRAM Configuration (r/w) */
+#define	MCFSIM_SDTR		0x184		/* SDRAM Timing (r/w) */
+#define	MCFSIM_DCAR0		0x4c		/* DRAM 0 Address reg(r/w) */
+#define	MCFSIM_DCMR0		0x50		/* DRAM 0 Mask reg (r/w) */
+#define	MCFSIM_DCCR0		0x57		/* DRAM 0 Control reg (r/w) */
+#define	MCFSIM_DCAR1		0x58		/* DRAM 1 Address reg (r/w) */
+#define	MCFSIM_DCMR1		0x5c		/* DRAM 1 Mask reg (r/w) */
+#define	MCFSIM_DCCR1		0x63		/* DRAM 1 Control reg (r/w) */
+
+#define	MCFSIM_PACNT		0x80		/* Port A Control (r/w) */
+#define	MCFSIM_PADDR		0x84		/* Port A Direction (r/w) */
+#define	MCFSIM_PADAT		0x86		/* Port A Data (r/w) */
+#define	MCFSIM_PBCNT		0x88		/* Port B Control (r/w) */
+#define	MCFSIM_PBDDR		0x8c		/* Port B Direction (r/w) */
+#define	MCFSIM_PBDAT		0x8e		/* Port B Data (r/w) */
+#define	MCFSIM_PCDDR		0x94		/* Port C Direction (r/w) */
+#define	MCFSIM_PCDAT		0x96		/* Port C Data (r/w) */
+#define	MCFSIM_PDCNT		0x98		/* Port D Control (r/w) */
+
+#endif	/* mcf5272_h */
diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h
new file mode 100755
index 0000000..073b0bc
--- /dev/null
+++ b/include/asm-m68k/m5282.h
@@ -0,0 +1,60 @@
+/*
+ * mcf5282.h -- Definitions for Motorola Coldfire 5282
+ *
+ * Based on mcf5282sim.h of uCLinux distribution:
+ *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************/
+#ifndef	m5282_h
+#define	m5282_h
+/****************************************************************************/
+
+/*
+ * Size of internal RAM
+ */
+
+#define INT_RAM_SIZE	65536
+
+
+/*
+ *	Define the 5282 SIM register set addresses.
+ */
+#define	MCFICM_INTC0		0x0c00		/* Base for Interrupt Ctrl 0 */
+#define	MCFICM_INTC1		0x0d00		/* Base for Interrupt Ctrl 0 */
+#define	MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
+#define	MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
+#define	MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
+#define	MCFINTC_IMRL		0x0c		/* Interrupt mask 1-31 */
+#define	MCFINTC_INTFRCH		0x10		/* Interrupt force 32-63 */
+#define	MCFINTC_INTFRCL		0x14		/* Interrupt force 1-31 */
+#define	MCFINTC_IRLR		0x18		/* */
+#define	MCFINTC_IACKL		0x19		/* */
+#define	MCFINTC_ICR0		0x40		/* Base ICR register */
+
+#define	MCFINT_UART0		13		/* Interrupt number for UART0 */
+#define	MCFINT_PIT1		55		/* Interrupt number for PIT1 */
+
+#define	MCF5282_GPIO_PUAPAR	0x10005C
+
+
+/****************************************************************************/
+#endif	/* m5282_h */
diff --git a/include/asm-m68k/mcftimer.h b/include/asm-m68k/mcftimer.h
new file mode 100755
index 0000000..047950b
--- /dev/null
+++ b/include/asm-m68k/mcftimer.h
@@ -0,0 +1,113 @@
+/*
+ * mcftimer.h -- ColdFire internal TIMER support defines.
+ *
+ * Based on mcftimer.h of uCLinux distribution:
+ *      (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
+ *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************/
+#ifndef	mcftimer_h
+#define	mcftimer_h
+/****************************************************************************/
+
+#include <linux/config.h>
+
+/*
+ *	Get address specific defines for this ColdFire member.
+ */
+#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
+#define	MCFTIMER_BASE1		0x100		/* Base address of TIMER1 */
+#define	MCFTIMER_BASE2		0x120		/* Base address of TIMER2 */
+#elif defined(CONFIG_M5272)
+#define MCFTIMER_BASE1		0x200           /* Base address of TIMER1 */
+#define MCFTIMER_BASE2		0x220           /* Base address of TIMER2 */
+#define MCFTIMER_BASE3		0x240           /* Base address of TIMER4 */
+#define MCFTIMER_BASE4		0x260           /* Base address of TIMER3 */
+#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
+#define MCFTIMER_BASE1		0x140           /* Base address of TIMER1 */
+#define MCFTIMER_BASE2		0x180           /* Base address of TIMER2 */
+#elif defined(CONFIG_M5282)
+#define MCFTIMER_BASE1		0x150000        /* Base address of TIMER1 */
+#define MCFTIMER_BASE2		0x160000        /* Base address of TIMER2 */
+#define MCFTIMER_BASE3		0x170000        /* Base address of TIMER4 */
+#define MCFTIMER_BASE4		0x180000	/* Base address of TIMER3 */
+#endif
+
+/*
+ *	Define the TIMER register set addresses.
+ */
+#define	MCFTIMER_TMR		0x00		/* Timer Mode reg (r/w) */
+#define	MCFTIMER_TRR		0x02		/* Timer Reference (r/w) */
+#define	MCFTIMER_TCR		0x04		/* Timer Capture reg (r/w) */
+#define	MCFTIMER_TCN		0x06		/* Timer Counter reg (r/w) */
+#define	MCFTIMER_TER		0x11		/* Timer Event reg (r/w) */
+
+
+/*
+ *	Define the TIMER register set addresses for 5282.
+ */
+#define MCFTIMER_PCSR		0
+#define MCFTIMER_PMR		1
+#define MCFTIMER_PCNTR		2
+
+/*
+ *	Bit definitions for the Timer Mode Register (TMR).
+ *	Register bit flags are common accross ColdFires.
+ */
+#define	MCFTIMER_TMR_PREMASK	0xff00		/* Prescalar mask */
+#define	MCFTIMER_TMR_DISCE	0x0000		/* Disable capture */
+#define	MCFTIMER_TMR_ANYCE	0x00c0		/* Capture any edge */
+#define	MCFTIMER_TMR_FALLCE	0x0080		/* Capture fallingedge */
+#define	MCFTIMER_TMR_RISECE	0x0040		/* Capture rising edge */
+#define	MCFTIMER_TMR_ENOM	0x0020		/* Enable output toggle */
+#define	MCFTIMER_TMR_DISOM	0x0000		/* Do single output pulse  */
+#define	MCFTIMER_TMR_ENORI	0x0010		/* Enable ref interrupt */
+#define	MCFTIMER_TMR_DISORI	0x0000		/* Disable ref interrupt */
+#define	MCFTIMER_TMR_RESTART	0x0008		/* Restart counter */
+#define	MCFTIMER_TMR_FREERUN	0x0000		/* Free running counter */
+#define	MCFTIMER_TMR_CLKTIN	0x0006		/* Input clock is TIN */
+#define	MCFTIMER_TMR_CLK16	0x0004		/* Input clock is /16 */
+#define	MCFTIMER_TMR_CLK1	0x0002		/* Input clock is /1 */
+#define	MCFTIMER_TMR_CLKSTOP	0x0000		/* Stop counter */
+#define	MCFTIMER_TMR_ENABLE	0x0001		/* Enable timer */
+#define	MCFTIMER_TMR_DISABLE	0x0000		/* Disable timer */
+
+/*
+ *	Bit definitions for the Timer Event Registers (TER).
+ */
+#define	MCFTIMER_TER_CAP	0x01		/* Capture event */
+#define	MCFTIMER_TER_REF	0x02		/* Refernece event */
+
+/*
+ *	Bit definitions for the 5282 PIT Control and Status Register (PCSR).
+ */
+#define MCFTIMER_PCSR_EN	0x0001
+#define MCFTIMER_PCSR_RLD	0x0002
+#define MCFTIMER_PCSR_PIF	0x0004
+#define MCFTIMER_PCSR_PIE	0x0008
+#define MCFTIMER_PCSR_OVW	0x0010
+#define MCFTIMER_PCSR_HALTED	0x0020
+#define MCFTIMER_PCSR_DOZE	0x0040
+
+
+/****************************************************************************/
+#endif	/* mcftimer_h */
diff --git a/include/asm-m68k/mcfuart.h b/include/asm-m68k/mcfuart.h
new file mode 100755
index 0000000..e5082a9
--- /dev/null
+++ b/include/asm-m68k/mcfuart.h
@@ -0,0 +1,221 @@
+/*
+ * mcfuart.h -- ColdFire internal UART support defines.
+ *
+ * File copied from mcfuart.h of uCLinux distribution:
+ *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
+ *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/****************************************************************************/
+#ifndef	mcfuart_h
+#define	mcfuart_h
+/****************************************************************************/
+
+#include <linux/config.h>
+
+/*
+ *	Define the base address of the UARTS within the MBAR address
+ *	space.
+ */
+#if defined(CONFIG_M5272)
+#define	MCFUART_BASE1		0x100		/* Base address of UART1 */
+#define	MCFUART_BASE2		0x140		/* Base address of UART2 */
+#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e)
+#if defined(CONFIG_NETtel)
+#define	MCFUART_BASE1		0x180		/* Base address of UART1 */
+#define	MCFUART_BASE2		0x140		/* Base address of UART2 */
+#else
+#define	MCFUART_BASE1		0x140		/* Base address of UART1 */
+#define	MCFUART_BASE2		0x180		/* Base address of UART2 */
+#endif
+#elif defined(CONFIG_M5282)
+#define MCFUART_BASE1		0x200           /* Base address of UART1 */
+#define MCFUART_BASE2		0x240           /* Base address of UART2 */
+#define MCFUART_BASE3		0x280           /* Base address of UART3 */
+#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407)
+#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3)
+#define MCFUART_BASE1		0x200           /* Base address of UART1 */
+#define MCFUART_BASE2		0x1c0           /* Base address of UART2 */
+#else
+#define MCFUART_BASE1		0x1c0           /* Base address of UART1 */
+#define MCFUART_BASE2		0x200           /* Base address of UART2 */
+#endif
+#endif
+
+
+/*
+ *	Define the ColdFire UART register set addresses.
+ */
+#define	MCFUART_UMR		0x00		/* Mode register (r/w) */
+#define	MCFUART_USR		0x04		/* Status register (r) */
+#define	MCFUART_UCSR		0x04		/* Clock Select (w) */
+#define	MCFUART_UCR		0x08		/* Command register (w) */
+#define	MCFUART_URB		0x0c		/* Receiver Buffer (r) */
+#define	MCFUART_UTB		0x0c		/* Transmit Buffer (w) */
+#define	MCFUART_UIPCR		0x10		/* Input Port Change (r) */
+#define	MCFUART_UACR		0x10		/* Auxiliary Control (w) */
+#define	MCFUART_UISR		0x14		/* Interrup Status (r) */
+#define	MCFUART_UIMR		0x14		/* Interrupt Mask (w) */
+#define	MCFUART_UBG1		0x18		/* Baud Rate MSB (r/w) */
+#define	MCFUART_UBG2		0x1c		/* Baud Rate LSB (r/w) */
+#ifdef	CONFIG_M5272
+#define	MCFUART_UTF		0x28		/* Transmitter FIFO (r/w) */
+#define	MCFUART_URF		0x2c		/* Receiver FIFO (r/w) */
+#define	MCFUART_UFPD		0x30		/* Frac Prec. Divider (r/w) */
+#else
+#define	MCFUART_UIVR		0x30		/* Interrupt Vector (r/w) */
+#endif
+#define	MCFUART_UIPR		0x34		/* Input Port (r) */
+#define	MCFUART_UOP1		0x38		/* Output Port Bit Set (w) */
+#define	MCFUART_UOP0		0x3c		/* Output Port Bit Reset (w) */
+
+#ifdef	CONFIG_M5249
+/* Note: This isn't in the 5249 docs */
+#define	MCFUART_UFPD		0x30		/* Frac Prec. Divider (r/w) */
+#endif
+
+/*
+ *	Define bit flags in Mode Register 1 (MR1).
+ */
+#define	MCFUART_MR1_RXRTS	0x80		/* Auto RTS flow control */
+#define	MCFUART_MR1_RXIRQFULL	0x40		/* RX IRQ type FULL */
+#define	MCFUART_MR1_RXIRQRDY	0x00		/* RX IRQ type RDY */
+#define	MCFUART_MR1_RXERRBLOCK	0x20		/* RX block error mode */
+#define	MCFUART_MR1_RXERRCHAR	0x00		/* RX char error mode */
+
+#define	MCFUART_MR1_PARITYNONE	0x10		/* No parity */
+#define	MCFUART_MR1_PARITYEVEN	0x00		/* Even parity */
+#define	MCFUART_MR1_PARITYODD	0x04		/* Odd parity */
+#define	MCFUART_MR1_PARITYSPACE	0x08		/* Space parity */
+#define	MCFUART_MR1_PARITYMARK	0x0c		/* Mark parity */
+
+#define	MCFUART_MR1_CS5		0x00		/* 5 bits per char */
+#define	MCFUART_MR1_CS6		0x01		/* 6 bits per char */
+#define	MCFUART_MR1_CS7		0x02		/* 7 bits per char */
+#define	MCFUART_MR1_CS8		0x03		/* 8 bits per char */
+
+/*
+ *	Define bit flags in Mode Register 2 (MR2).
+ */
+#define	MCFUART_MR2_LOOPBACK	0x80		/* Loopback mode */
+#define	MCFUART_MR2_REMOTELOOP	0xc0		/* Remote loopback mode */
+#define	MCFUART_MR2_AUTOECHO	0x40		/* Automatic echo */
+#define	MCFUART_MR2_TXRTS	0x20		/* Assert RTS on TX */
+#define	MCFUART_MR2_TXCTS	0x10		/* Auto CTS flow control */
+
+#define	MCFUART_MR2_STOP1	0x07		/* 1 stop bit */
+#define	MCFUART_MR2_STOP15	0x08		/* 1.5 stop bits */
+#define	MCFUART_MR2_STOP2	0x0f		/* 2 stop bits */
+
+/*
+ *	Define bit flags in Status Register (USR).
+ */
+#define	MCFUART_USR_RXBREAK	0x80		/* Received BREAK */
+#define	MCFUART_USR_RXFRAMING	0x40		/* Received framing error */
+#define	MCFUART_USR_RXPARITY	0x20		/* Received parity error */
+#define	MCFUART_USR_RXOVERRUN	0x10		/* Received overrun error */
+#define	MCFUART_USR_TXEMPTY	0x08		/* Transmitter empty */
+#define	MCFUART_USR_TXREADY	0x04		/* Transmitter ready */
+#define	MCFUART_USR_RXFULL	0x02		/* Receiver full */
+#define	MCFUART_USR_RXREADY	0x01		/* Receiver ready */
+
+#define	MCFUART_USR_RXERR	(MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \
+				MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN)
+
+/*
+ *	Define bit flags in Clock Select Register (UCSR).
+ */
+#define	MCFUART_UCSR_RXCLKTIMER	0xd0		/* RX clock is timer */
+#define	MCFUART_UCSR_RXCLKEXT16	0xe0		/* RX clock is external x16 */
+#define	MCFUART_UCSR_RXCLKEXT1	0xf0		/* RX clock is external x1 */
+
+#define	MCFUART_UCSR_TXCLKTIMER	0x0d		/* TX clock is timer */
+#define	MCFUART_UCSR_TXCLKEXT16	0x0e		/* TX clock is external x16 */
+#define	MCFUART_UCSR_TXCLKEXT1	0x0f		/* TX clock is external x1 */
+
+/*
+ *	Define bit flags in Command Register (UCR).
+ */
+#define	MCFUART_UCR_CMDNULL		0x00	/* No command */
+#define	MCFUART_UCR_CMDRESETMRPTR	0x10	/* Reset MR pointer */
+#define	MCFUART_UCR_CMDRESETRX		0x20	/* Reset receiver */
+#define	MCFUART_UCR_CMDRESETTX		0x30	/* Reset transmitter */
+#define	MCFUART_UCR_CMDRESETERR		0x40	/* Reset error status */
+#define	MCFUART_UCR_CMDRESETBREAK	0x50	/* Reset BREAK change */
+#define	MCFUART_UCR_CMDBREAKSTART	0x60	/* Start BREAK */
+#define	MCFUART_UCR_CMDBREAKSTOP	0x70	/* Stop BREAK */
+
+#define	MCFUART_UCR_TXNULL	0x00		/* No TX command */
+#define	MCFUART_UCR_TXENABLE	0x04		/* Enable TX */
+#define	MCFUART_UCR_TXDISABLE	0x08		/* Disable TX */
+#define	MCFUART_UCR_RXNULL	0x00		/* No RX command */
+#define	MCFUART_UCR_RXENABLE	0x01		/* Enable RX */
+#define	MCFUART_UCR_RXDISABLE	0x02		/* Disable RX */
+
+/*
+ *	Define bit flags in Input Port Change Register (UIPCR).
+ */
+#define	MCFUART_UIPCR_CTSCOS	0x10		/* CTS change of state */
+#define	MCFUART_UIPCR_CTS	0x01		/* CTS value */
+
+/*
+ *	Define bit flags in Input Port Register (UIP).
+ */
+#define	MCFUART_UIPR_CTS	0x01		/* CTS value */
+
+/*
+ *	Define bit flags in Output Port Registers (UOP).
+ *	Clear bit by writing to UOP0, set by writing to UOP1.
+ */
+#define	MCFUART_UOP_RTS		0x01		/* RTS set or clear */
+
+/*
+ *	Define bit flags in the Auxiliary Control Register (UACR).
+ */
+#define	MCFUART_UACR_IEC	0x01		/* Input enable control */
+
+/*
+ *	Define bit flags in Interrupt Status Register (UISR).
+ *	These same bits are used for the Interrupt Mask Register (UIMR).
+ */
+#define	MCFUART_UIR_COS		0x80		/* Change of state (CTS) */
+#define	MCFUART_UIR_DELTABREAK	0x04		/* Break start or stop */
+#define	MCFUART_UIR_RXREADY	0x02		/* Receiver ready */
+#define	MCFUART_UIR_TXREADY	0x01		/* Transmitter ready */
+
+#ifdef	CONFIG_M5272
+/*
+ *	Define bit flags in the Transmitter FIFO Register (UTF).
+ */
+#define	MCFUART_UTF_TXB		0x1f		/* transmitter data level */
+#define	MCFUART_UTF_FULL	0x20		/* transmitter fifo full */
+#define	MCFUART_UTF_TXS		0xc0		/* transmitter status */
+
+/*
+ *	Define bit flags in the Receiver FIFO Register (URF).
+ */
+#define	MCFUART_URF_RXB		0x1f		/* receiver data level */
+#define	MCFUART_URF_FULL	0x20		/* receiver fifo full */
+#define	MCFUART_URF_RXS		0xc0		/* receiver status */
+#endif
+
+/****************************************************************************/
+#endif	/* mcfuart_h */
diff --git a/include/asm-m68k/posix_types.h b/include/asm-m68k/posix_types.h
new file mode 100755
index 0000000..4fbc040
--- /dev/null
+++ b/include/asm-m68k/posix_types.h
@@ -0,0 +1,109 @@
+#ifndef _M68K_POSIX_TYPES_H
+#define _M68K_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned int	__kernel_dev_t;
+typedef unsigned int	__kernel_ino_t;
+typedef unsigned int	__kernel_mode_t;
+typedef unsigned short	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef unsigned int	__kernel_uid_t;
+typedef unsigned int	__kernel_gid_t;
+typedef unsigned int	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef long		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef short             __kernel_ipc_pid_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned int	__kernel_old_uid_t;
+typedef unsigned int	__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long	__kernel_loff_t;
+#endif
+
+typedef struct {
+	int	val[2];
+} __kernel_fsid_t;
+
+#ifndef __GNUC__
+
+#define	__FD_SET(d, set)	((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+#define	__FD_CLR(d, set)	((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+#define	__FD_ISSET(d, set)	((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+#define	__FD_ZERO(set)	\
+  ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
+
+#else /* __GNUC__ */
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
+    || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
+/* With GNU C, use inline functions instead so args are evaluated only once: */
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+	unsigned long _tmp = fd / __NFDBITS;
+	unsigned long _rem = fd % __NFDBITS;
+	fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+	unsigned long _tmp = fd / __NFDBITS;
+	unsigned long _rem = fd % __NFDBITS;
+	fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
+{
+	unsigned long _tmp = fd / __NFDBITS;
+	unsigned long _rem = fd % __NFDBITS;
+	return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *p)
+{
+	unsigned int *tmp = (unsigned int *)p->fds_bits;
+	int i;
+
+	if (__builtin_constant_p(__FDSET_LONGS)) {
+		switch (__FDSET_LONGS) {
+			case 8:
+				tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0;
+				tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0;
+				return;
+		}
+	}
+	i = __FDSET_LONGS;
+	while (i) {
+		i--;
+		*tmp = 0;
+		tmp++;
+	}
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* __GNUC__ */
+#endif /* _M68K_POSIX_TYPES_H */
diff --git a/include/asm-m68k/processor.h b/include/asm-m68k/processor.h
new file mode 100755
index 0000000..3fafa6f
--- /dev/null
+++ b/include/asm-m68k/processor.h
@@ -0,0 +1,18 @@
+#ifndef __ASM_M68K_PROCESSOR_H
+#define __ASM_M68K_PROCESSOR_H
+
+#include <asm/ptrace.h>
+#include <asm/types.h>
+
+#define _GLOBAL(n)\
+	.globl n;\
+n:
+
+/* Macros for setting and retrieving special purpose registers */
+#define setvbr(v)	asm volatile("movec %0,%%VBR" : : "r" (v))
+
+#ifndef __ASSEMBLY__
+
+#endif /* ifndef ASSEMBLY*/
+
+#endif /* __ASM_M68K_PROCESSOR_H */
diff --git a/include/asm-m68k/ptrace.h b/include/asm-m68k/ptrace.h
new file mode 100755
index 0000000..a6d3d74
--- /dev/null
+++ b/include/asm-m68k/ptrace.h
@@ -0,0 +1,59 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _M68K_PTRACE_H
+#define _M68K_PTRACE_H
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during an exception.
+ */
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+	ulong     d0;
+	ulong     d1;
+	ulong     d2;
+	ulong     d3;
+	ulong     d4;
+	ulong     d5;
+	ulong     d6;
+	ulong     d7;
+	ulong     a0;
+	ulong     a1;
+	ulong     a2;
+	ulong     a3;
+	ulong     a4;
+	ulong     a5;
+	ulong     a6;
+#if defined(CONFIG_M5272) || defined(CONFIG_M5282) || defined(CONFIG_M5249)
+	unsigned format :  4; /* frame format specifier */
+	unsigned vector : 12; /* vector offset */
+	unsigned short sr;
+	unsigned long  pc;
+#else
+	unsigned short sr;
+	unsigned long  pc;
+#endif
+};
+
+#endif	/* #ifndef __ASSEMBLY__ */
+
+#endif	/* #ifndef _M68K_PTRACE_H */
diff --git a/include/asm-m68k/string.h b/include/asm-m68k/string.h
new file mode 100755
index 0000000..e0773a8
--- /dev/null
+++ b/include/asm-m68k/string.h
@@ -0,0 +1,31 @@
+#ifndef _M68K_STRING_H_
+#define _M68K_STRING_H_
+
+#if 0
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRNCPY
+#define __HAVE_ARCH_STRLEN
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRCAT
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_BCOPY
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMMOVE
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_MEMCHR
+#endif
+
+extern int strcasecmp(const char *, const char *);
+extern int strncasecmp(const char *, const char *, int);
+extern char * strcpy(char *,const char *);
+extern char * strncpy(char *,const char *, __kernel_size_t);
+extern __kernel_size_t strlen(const char *);
+extern int strcmp(const char *,const char *);
+extern char * strcat(char *, const char *);
+extern void * memset(void *,int,__kernel_size_t);
+extern void * memcpy(void *,const void *,__kernel_size_t);
+extern void * memmove(void *,const void *,__kernel_size_t);
+extern int memcmp(const void *,const void *,__kernel_size_t);
+extern void * memchr(const void *,int,__kernel_size_t);
+
+#endif
diff --git a/include/asm-m68k/types.h b/include/asm-m68k/types.h
new file mode 100755
index 0000000..e673cb0
--- /dev/null
+++ b/include/asm-m68k/types.h
@@ -0,0 +1,50 @@
+#ifndef _M68K_TYPES_H
+#define _M68K_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+typedef struct {
+	__u32 u[4];
+} __attribute((aligned(16))) vector128;
+
+#ifdef __KERNEL__
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* DMA addresses are 32-bits wide */
+typedef u32 dma_addr_t;
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h
new file mode 100755
index 0000000..7a6a8c1
--- /dev/null
+++ b/include/asm-m68k/u-boot.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2000 - 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __U_BOOT_H__
+#define __U_BOOT_H__
+
+/*
+ * Board information passed to Linux kernel from U-Boot
+ *
+ * include/asm-ppc/u-boot.h
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef struct bd_info {
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+	unsigned long	bi_sramstart;	/* start of SRAM memory */
+	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
+	unsigned long	bi_mbar_base;	/* base of internal registers */
+	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
+	unsigned long   bi_boot_params; /* where this board expects params */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6];	/* Ethernet adress */
+	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
+	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
+	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
+	unsigned long	bi_baudrate;	/* Console Baudrate */
+} bd_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif	/* __U_BOOT_H__ */
diff --git a/include/asm-microblaze/arch-microblaze/xbasic_types.h b/include/asm-microblaze/arch-microblaze/xbasic_types.h
new file mode 100755
index 0000000..25012e6
--- /dev/null
+++ b/include/asm-microblaze/arch-microblaze/xbasic_types.h
@@ -0,0 +1,301 @@
+/******************************************************************************
+*
+*     Author: Xilinx, Inc.
+*
+*
+*     This program is free software; you can redistribute it and/or modify it
+*     under the terms of the GNU General Public License as published by the
+*     Free Software Foundation; either version 2 of the License, or (at your
+*     option) any later version.
+*
+*
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
+*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+*     FITNESS FOR A PARTICULAR PURPOSE.
+*
+*
+*     Xilinx hardware products are not intended for use in life support
+*     appliances, devices, or systems. Use in such applications is
+*     expressly prohibited.
+*
+*
+*     (c) Copyright 2002-2003 Xilinx Inc.
+*     All rights reserved.
+*
+*
+*     You should have received a copy of the GNU General Public License along
+*     with this program; if not, write to the Free Software Foundation, Inc.,
+*     675 Mass Ave, Cambridge, MA 02139, USA.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+* This file contains basic types for Xilinx software IP.  These types do not
+* follow the standard naming convention with respect to using the component
+* name in front of each name because they are considered to be primitives.
+*
+* @note
+*
+* This file contains items which are architecture dependent.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	 Who	Date	Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm  12/14/01 First release
+*	rmm  05/09/03 Added "xassert always" macros to rid ourselves of diab
+*		      compiler warnings
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H		/* prevent circular inclusions */
+#define XBASIC_TYPES_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+/** Null */
+
+#define XCOMPONENT_IS_READY	0x11111111	/* component has been initialized */
+#define XCOMPONENT_IS_STARTED	0x22222222	/* component has been started */
+
+/* the following constants and declarations are for unit test purposes and are
+ * designed to be used in test applications.
+ */
+#define XTEST_PASSED	0
+#define XTEST_FAILED	1
+
+#define XASSERT_NONE	 0
+#define XASSERT_OCCURRED 1
+
+extern unsigned int XAssertStatus;
+extern void XAssert(char *, int);
+
+/**************************** Type Definitions *******************************/
+
+/** @name Primitive types
+ * These primitive types are created for transportability.
+ * They are dependent upon the target architecture.
+ * @{
+ */
+#include <linux/types.h>
+
+typedef struct {
+	u32 Upper;
+	u32 Lower;
+} Xuint64;
+
+/* Xilinx's unsigned integer types */
+typedef u32 Xuint32;
+typedef u16 Xuint16;
+typedef u8 Xuint8;
+
+/* and signed integer types */
+typedef s32 Xint32;
+typedef s16 Xint16;
+typedef s8 Xint8;
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+typedef unsigned long Xboolean;
+#define XNULL	NULL
+
+#define XTRUE	1
+#define XFALSE	0
+
+/*@}*/
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return
+*
+* The upper 32 bits of the 64 bit word.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param x is the 64 bit word.
+*
+* @return
+*
+* The lower 32 bits of the 64 bit word.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do not return anything
+* (void). This in conjunction with the XWaitInAssert boolean can be used to
+* accomodate tests so that asserts which fail allow execution to continue.
+*
+* @param expression is the expression to evaluate. If it evaluates to false,
+*	 the assert occurs.
+*
+* @return
+*
+* Returns void unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XASSERT_VOID(expression)			\
+{							\
+	if (expression) {				\
+		XAssertStatus = XASSERT_NONE;		\
+	} else {					\
+		XAssert(__FILE__, __LINE__);		\
+		XAssertStatus = XASSERT_OCCURRED;	\
+		return;					\
+	}						\
+}
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do return a value. This in
+* conjunction with the XWaitInAssert boolean can be used to accomodate tests so
+* that asserts which fail allow execution to continue.
+*
+* @param expression is the expression to evaluate. If it evaluates to false,
+*	 the assert occurs.
+*
+* @return
+*
+* Returns 0 unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XASSERT_NONVOID(expression)			\
+{							\
+	if (expression) {				\
+		XAssertStatus = XASSERT_NONE;		\
+	} else {					\
+		XAssert(__FILE__, __LINE__);		\
+		XAssertStatus = XASSERT_OCCURRED;	\
+		return 0;				\
+	}						\
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do not
+* return anything (void). Use for instances where an assert should always
+* occur.
+*
+* @return
+*
+* Returns void unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XASSERT_VOID_ALWAYS()				\
+{							\
+	XAssert(__FILE__, __LINE__);			\
+	XAssertStatus = XASSERT_OCCURRED;		\
+	return;						\
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do return
+* a value. Use for instances where an assert should always occur.
+*
+* @return
+*
+* Returns void unless the XWaitInAssert variable is true, in which case
+* no return is made and an infinite loop is entered.
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#define XASSERT_NONVOID_ALWAYS()			\
+{							\
+	XAssert(__FILE__, __LINE__);			\
+	XAssertStatus = XASSERT_OCCURRED;		\
+	return 0;					\
+}
+
+#else
+
+#define XASSERT_VOID(expression)
+#define XASSERT_VOID_ALWAYS()
+#define XASSERT_NONVOID(expression)
+#define XASSERT_NONVOID_ALWAYS()
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void XAssertSetCallback(XAssertCallback Routine);
+
+#endif	/* end of protection macro */
diff --git a/include/asm-microblaze/arch-microblaze/xio.h b/include/asm-microblaze/arch-microblaze/xio.h
new file mode 100755
index 0000000..7eed327
--- /dev/null
+++ b/include/asm-microblaze/arch-microblaze/xio.h
@@ -0,0 +1,63 @@
+/*
+ * xio.h
+ *
+ * Defines XIo functions for Xilinx OCP in terms of Linux primitives
+ *
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * 2002 (c) MontaVista, Software, Inc.  This file is licensed under the terms
+ * of the GNU General Public License version 2.  This program is licensed
+ * "as is" without any warranty of any kind, whether express or implied.
+ */
+
+#ifndef XIO_H
+#define XIO_H
+
+#include "xbasic_types.h"
+#include <asm/io.h>
+
+typedef u32 XIo_Address;
+
+extern inline u8
+XIo_In8(XIo_Address InAddress)
+{
+	return (u8) in_8((volatile unsigned char *) InAddress);
+}
+extern inline u16
+XIo_In16(XIo_Address InAddress)
+{
+	return (u16) in_be16((volatile unsigned short *) InAddress);
+}
+extern inline u32
+XIo_In32(XIo_Address InAddress)
+{
+	return (u32) in_be32((volatile unsigned *) InAddress);
+}
+extern inline void
+XIo_Out8(XIo_Address OutAddress, u8 Value)
+{
+	out_8((volatile unsigned char *) OutAddress, Value);
+}
+extern inline void
+XIo_Out16(XIo_Address OutAddress, u16 Value)
+{
+	out_be16((volatile unsigned short *) OutAddress, Value);
+}
+extern inline void
+XIo_Out32(XIo_Address OutAddress, u32 Value)
+{
+	out_be32((volatile unsigned *) OutAddress, Value);
+}
+
+#define XIo_ToLittleEndian16(s,d) (*(u16*)(d) = cpu_to_le16((u16)(s)))
+#define XIo_ToLittleEndian32(s,d) (*(u32*)(d) = cpu_to_le32((u32)(s)))
+#define XIo_ToBigEndian16(s,d) (*(u16*)(d) = cpu_to_be16((u16)(s)))
+#define XIo_ToBigEndian32(s,d) (*(u32*)(d) = cpu_to_be32((u32)(s)))
+
+#define XIo_FromLittleEndian16(s,d) (*(u16*)(d) = le16_to_cpu((u16)(s)))
+#define XIo_FromLittleEndian32(s,d) (*(u32*)(d) = le32_to_cpu((u32)(s)))
+#define XIo_FromBigEndian16(s,d) (*(u16*)(d) = be16_to_cpu((u16)(s)))
+#define XIo_FromBigEndian32(s,d) (*(u32*)(d) = be32_to_cpu((u32)(s)))
+
+#endif				/* XIO_H */
diff --git a/include/asm-microblaze/arch-microblaze/xuartlite_l.h b/include/asm-microblaze/arch-microblaze/xuartlite_l.h
new file mode 100755
index 0000000..b381a0d
--- /dev/null
+++ b/include/asm-microblaze/arch-microblaze/xuartlite_l.h
@@ -0,0 +1,256 @@
+/*****************************************************************************
+*
+*	XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+*	AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+*	SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
+*	OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+*	APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+*	THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+*	AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+*	FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+*	WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+*	IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+*	REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+*	INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*	FOR A PARTICULAR PURPOSE.
+*
+*	(c) Copyright 2002 Xilinx Inc.
+*	All rights reserved.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartlite_l.h
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device.  High-level driver functions
+* are defined in xuartlite.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm  04/25/02 First release
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XUARTLITE_L_H /* prevent circular inclusions */
+#define XUARTLITE_L_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xbasic_types.h"
+#include "xio.h"
+
+/************************** Constant Definitions ****************************/
+
+/* UART Lite register offsets */
+
+#define XUL_RX_FIFO_OFFSET		0   /* receive FIFO, read only */
+#define XUL_TX_FIFO_OFFSET		4   /* transmit FIFO, write only */
+#define XUL_STATUS_REG_OFFSET		8   /* status register, read only */
+#define XUL_CONTROL_REG_OFFSET		12  /* control register, write only */
+
+/* control register bit positions */
+
+#define XUL_CR_ENABLE_INTR		0x10	/* enable interrupt */
+#define XUL_CR_FIFO_RX_RESET		0x02	/* reset receive FIFO */
+#define XUL_CR_FIFO_TX_RESET		0x01	/* reset transmit FIFO */
+
+/* status register bit positions */
+
+#define XUL_SR_PARITY_ERROR		0x80
+#define XUL_SR_FRAMING_ERROR		0x40
+#define XUL_SR_OVERRUN_ERROR		0x20
+#define XUL_SR_INTR_ENABLED		0x10	/* interrupt enabled */
+#define XUL_SR_TX_FIFO_FULL		0x08	/* transmit FIFO full */
+#define XUL_SR_TX_FIFO_EMPTY		0x04	/* transmit FIFO empty */
+#define XUL_SR_RX_FIFO_FULL		0x02	/* receive FIFO full */
+#define XUL_SR_RX_FIFO_VALID_DATA	0x01	/* data in receive FIFO */
+
+/* the following constant specifies the size of the FIFOs, the size of the
+ * FIFOs includes the transmitter and receiver such that it is the total number
+ * of bytes that the UART can buffer
+ */
+#define XUL_FIFO_SIZE		    16
+
+/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a
+ * per instance basis
+ */
+#define XUL_STOP_BITS		    1
+
+/* Parity definitions
+ */
+#define XUL_PARITY_NONE		    0
+#define XUL_PARITY_ODD		    1
+#define XUL_PARITY_EVEN		    2
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/*****************************************************************************
+*
+* Low-level driver macros and functions. The list below provides signatures
+* to help the user use the macros.
+*
+* void XUartLite_mSetControlReg(u32 BaseAddress, u32 Mask)
+* u32 XUartLite_mGetControlReg(u32 BaseAddress)
+* u32 XUartLite_mGetStatusReg(u32 BaseAddress)
+*
+* Xboolean XUartLite_mIsReceiveEmpty(u32 BaseAddress)
+* Xboolean XUartLite_mIsTransmitFull(u32 BaseAddress)
+* Xboolean XUartLite_mIsIntrEnabled(u32 BaseAddress)
+*
+* void XUartLite_mEnableIntr(u32 BaseAddress)
+* void XUartLite_mDisableIntr(u32 BaseAddress)
+*
+* void XUartLite_SendByte(u32 BaseAddress, u8 Data);
+* u8 XUartLite_RecvByte(u32 BaseAddress);
+*
+*****************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the control register. Use the XUL_CR_* constants defined
+* above to create the bit-mask to be written to the register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    Mask is the 32-bit value to write to the control register
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XUartLite_mSetControlReg(BaseAddress, Mask) \
+		    XIo_Out32((BaseAddress) + XUL_CONTROL_REG_OFFSET, (Mask))
+
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the control register. Use the XUL_CR_* constants defined
+* above to interpret the bit-mask returned.
+*
+* @param    BaseAddress is the	base address of the device
+*
+* @return   A 32-bit value representing the contents of the control register.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XUartLite_mGetControlReg(BaseAddress) \
+		    XIo_In32((BaseAddress) + XUL_CONTROL_REG_OFFSET)
+
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the status register. Use the XUL_SR_* constants defined
+* above to interpret the bit-mask returned.
+*
+* @param    BaseAddress is the	base address of the device
+*
+* @return   A 32-bit value representing the contents of the status register.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XUartLite_mGetStatusReg(BaseAddress) \
+		    XIo_In32((BaseAddress) + XUL_STATUS_REG_OFFSET)
+
+
+/****************************************************************************/
+/**
+*
+* Check to see if the receiver has data.
+*
+* @param    BaseAddress is the	base address of the device
+*
+* @return   XTRUE if the receiver is empty, XFALSE if there is data present.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XUartLite_mIsReceiveEmpty(BaseAddress) \
+	  (!(XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA))
+
+
+/****************************************************************************/
+/**
+*
+* Check to see if the transmitter is full.
+*
+* @param    BaseAddress is the	base address of the device
+*
+* @return   XTRUE if the transmitter is full, XFALSE otherwise.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XUartLite_mIsTransmitFull(BaseAddress) \
+		(XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL)
+
+
+/****************************************************************************/
+/**
+*
+* Check to see if the interrupt is enabled.
+*
+* @param    BaseAddress is the	base address of the device
+*
+* @return   XTRUE if the interrupt is enabled, XFALSE otherwise.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XUartLite_mIsIntrEnabled(BaseAddress) \
+		(XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED)
+
+
+/****************************************************************************/
+/**
+*
+* Enable the device interrupt. Preserve the contents of the control register.
+*
+* @param    BaseAddress is the	base address of the device
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XUartLite_mEnableIntr(BaseAddress) \
+	       XUartLite_mSetControlReg((BaseAddress), \
+		   XUartLite_mGetControlReg((BaseAddress)) | XUL_CR_ENABLE_INTR)
+
+
+/****************************************************************************/
+/**
+*
+* Disable the device interrupt. Preserve the contents of the control register.
+*
+* @param    BaseAddress is the	base address of the device
+*
+* @return   None.
+*
+* @note	    None.
+*
+*****************************************************************************/
+#define XUartLite_mDisableIntr(BaseAddress) \
+	      XUartLite_mSetControlReg((BaseAddress), \
+		  XUartLite_mGetControlReg((BaseAddress)) & ~XUL_CR_ENABLE_INTR)
+
+
+/************************** Function Prototypes *****************************/
+
+void XUartLite_SendByte(u32 BaseAddress, u8 Data);
+u8 XUartLite_RecvByte(u32 BaseAddress);
+
+
+#endif		  /* end of protection macro */
diff --git a/include/asm-microblaze/bitops.h b/include/asm-microblaze/bitops.h
new file mode 100755
index 0000000..04ea020
--- /dev/null
+++ b/include/asm-microblaze/bitops.h
@@ -0,0 +1,392 @@
+#ifndef _MICROBLAZE_BITOPS_H
+#define _MICROBLAZE_BITOPS_H
+
+/*
+ * Copyright 1992, Linus Torvalds.
+ */
+
+#include <linux/config.h>
+#include <asm/byteorder.h>	/* swab32 */
+#include <asm/system.h>		/* save_flags */
+
+#ifdef __KERNEL__
+/*
+ * Function prototypes to keep gcc -Wall happy
+ */
+
+/*
+ * The __ functions are not atomic
+ */
+
+extern void set_bit(int nr, volatile void * addr);
+extern void __set_bit(int nr, volatile void * addr);
+
+extern void clear_bit(int nr, volatile void * addr);
+#define __clear_bit(nr, addr) clear_bit(nr, addr)
+
+extern void change_bit(int nr, volatile void * addr);
+extern void __change_bit(int nr, volatile void * addr);
+extern int test_and_set_bit(int nr, volatile void * addr);
+extern int __test_and_set_bit(int nr, volatile void * addr);
+extern int test_and_clear_bit(int nr, volatile void * addr);
+extern int __test_and_clear_bit(int nr, volatile void * addr);
+extern int test_and_change_bit(int nr, volatile void * addr);
+extern int __test_and_change_bit(int nr, volatile void * addr);
+extern int __constant_test_bit(int nr, const volatile void * addr);
+extern int __test_bit(int nr, volatile void * addr);
+extern int find_first_zero_bit(void * addr, unsigned size);
+extern int find_next_zero_bit (void * addr, int size, int offset);
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+extern __inline__ unsigned long ffz(unsigned long word)
+{
+	unsigned long result = 0;
+
+	while(word & 1) {
+		result++;
+		word >>= 1;
+	}
+	return result;
+}
+
+
+extern __inline__ void set_bit(int nr, volatile void * addr)
+{
+	int	* a = (int *) addr;
+	int	mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_flags_cli(flags);
+	*a |= mask;
+	restore_flags(flags);
+}
+
+extern __inline__ void __set_bit(int nr, volatile void * addr)
+{
+	int	* a = (int *) addr;
+	int	mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()	barrier()
+#define smp_mb__after_clear_bit()	barrier()
+
+extern __inline__ void clear_bit(int nr, volatile void * addr)
+{
+	int	* a = (int *) addr;
+	int	mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_flags_cli(flags);
+	*a &= ~mask;
+	restore_flags(flags);
+}
+
+extern __inline__ void change_bit(int nr, volatile void * addr)
+{
+	int mask;
+	unsigned long flags;
+	unsigned long *ADDR = (unsigned long *) addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	save_flags_cli(flags);
+	*ADDR ^= mask;
+	restore_flags(flags);
+}
+
+extern __inline__ void __change_bit(int nr, volatile void * addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *) addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+extern __inline__ int test_and_set_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_flags_cli(flags);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	restore_flags(flags);
+
+	return retval;
+}
+
+extern __inline__ int __test_and_set_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+extern __inline__ int test_and_clear_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_flags_cli(flags);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	restore_flags(flags);
+
+	return retval;
+}
+
+extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+extern __inline__ int test_and_change_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_flags_cli(flags);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	restore_flags(flags);
+
+	return retval;
+}
+
+extern __inline__ int __test_and_change_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+extern __inline__ int __constant_test_bit(int nr, const volatile void * addr)
+{
+	return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
+}
+
+extern __inline__ int __test_bit(int nr, volatile void * addr)
+{
+	int	* a = (int *) addr;
+	int	mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	return ((mask & *a) != 0);
+}
+
+#define test_bit(nr,addr) \
+(__builtin_constant_p(nr) ? \
+ __constant_test_bit((nr),(addr)) : \
+ __test_bit((nr),(addr)))
+
+#define find_first_zero_bit(addr, size) \
+	find_next_zero_bit((addr), (size), 0)
+
+extern __inline__ int find_next_zero_bit (void * addr, int size, int offset)
+{
+	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = *(p++);
+		tmp |= ~0UL >> (32-offset);
+		if (size < 32)
+			goto found_first;
+		if (~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size & ~31UL) {
+		if (~(tmp = *(p++)))
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+found_first:
+	tmp |= ~0UL >> size;
+found_middle:
+	return result + ffz(tmp);
+}
+
+#define ffs(x) generic_ffs(x)
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+
+extern __inline__ int ext2_set_bit(int nr, volatile void * addr)
+{
+	int		mask, retval;
+	unsigned long	flags;
+	volatile unsigned char	*ADDR = (unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	save_flags_cli(flags);
+	retval = (mask & *ADDR) != 0;
+	*ADDR |= mask;
+	restore_flags(flags);
+	return retval;
+}
+
+extern __inline__ int ext2_clear_bit(int nr, volatile void * addr)
+{
+	int		mask, retval;
+	unsigned long	flags;
+	volatile unsigned char	*ADDR = (unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	save_flags_cli(flags);
+	retval = (mask & *ADDR) != 0;
+	*ADDR &= ~mask;
+	restore_flags(flags);
+	return retval;
+}
+
+extern __inline__ int ext2_test_bit(int nr, const volatile void * addr)
+{
+	int			mask;
+	const volatile unsigned char	*ADDR = (const unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	return ((mask & *ADDR) != 0);
+}
+
+#define ext2_find_first_zero_bit(addr, size) \
+	ext2_find_next_zero_bit((addr), (size), 0)
+
+extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
+{
+	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if(offset) {
+		/* We hold the little endian value in tmp, but then the
+		 * shift is illegal. So we could keep a big endian value
+		 * in tmp, like this:
+		 *
+		 * tmp = __swab32(*(p++));
+		 * tmp |= ~0UL >> (32-offset);
+		 *
+		 * but this would decrease preformance, so we change the
+		 * shift:
+		 */
+		tmp = *(p++);
+		tmp |= __swab32(~0UL >> (32-offset));
+		if(size < 32)
+			goto found_first;
+		if(~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while(size & ~31UL) {
+		if(~(tmp = *(p++)))
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if(!size)
+		return result;
+	tmp = *p;
+
+found_first:
+	/* tmp is little endian, so we would have to swab the shift,
+	 * see above. But then we have to swab tmp below for ffz, so
+	 * we might as well do this here.
+	 */
+	return result + ffz(__swab32(tmp) | (~0UL << size));
+found_middle:
+	return result + ffz(__swab32(tmp));
+}
+
+/* Bitmap functions for the minix filesystem.  */
+#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr) set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr) test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
+
+/**
+ * hweightN - returns the hamming weight of a N-bit word
+ * @x: the word to weigh
+ *
+ * The Hamming Weight of a number is the total number of bits set in it.
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __KERNEL__ */
+
+#endif /* _MICROBLAZE_BITOPS_H */
diff --git a/include/asm-microblaze/byteorder.h b/include/asm-microblaze/byteorder.h
new file mode 100755
index 0000000..51cacb0
--- /dev/null
+++ b/include/asm-microblaze/byteorder.h
@@ -0,0 +1,53 @@
+/*
+ * include/asm-microblaze/byteorder.h -- Endian id and conversion ops
+ *
+ *  Copyright (C) 2003  John Williams <jwilliams@itee.uq.edu.au>
+ *  Copyright (C) 2001  NEC Corporation
+ *  Copyright (C) 2001  Miles Bader <miles@gnu.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * Written by Miles Bader <miles@gnu.org>
+ * Microblaze port by John Williams
+ */
+
+#ifndef __MICROBLAZE_BYTEORDER_H__
+#define __MICROBLAZE_BYTEORDER_H__
+
+#include <asm/types.h>
+
+#ifdef __GNUC__
+
+/* This is effectively a dupe of the arch-independent byteswap
+   code in include/linux/byteorder/swab.h, however we force a cast
+   of the result up to 32 bits.  This in turn forces the compiler
+   to explicitly clear the high 16 bits, which it wasn't doing otherwise.
+
+   I think this is a symptom of a bug in mb-gcc.  JW 20040303
+*/
+static __inline__ __const__ __u16 ___arch__swab16 (__u16 half_word)
+{
+	/* 32 bit temp to cast result, forcing clearing of high word */
+	__u32 temp;
+
+	temp = ((half_word & 0x00FFU) << 8) | ((half_word & 0xFF00U) >> 8);
+
+	return (__u16) temp;
+}
+
+#define __arch__swab16(x) ___arch__swab16(x)
+
+/* Microblaze has no arch-specific endian conversion insns */
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __GNUC__ */
+
+#include <linux/byteorder/big_endian.h>
+
+#endif /* __MICROBLAZE_BYTEORDER_H__ */
diff --git a/include/asm-microblaze/global_data.h b/include/asm-microblaze/global_data.h
new file mode 100755
index 0000000..a6e7834
--- /dev/null
+++ b/include/asm-microblaze/global_data.h
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct	global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	have_console;	/* serial_init() was called */
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	unsigned long	fb_base;	/* base address of frame buffer */
+	void		**jt;		/* jump table */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC	0x00001		/* Code was relocated to RAM		*/
+#define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
+#define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
+
+#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r31")
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/include/asm-microblaze/io.h b/include/asm-microblaze/io.h
new file mode 100755
index 0000000..3359045
--- /dev/null
+++ b/include/asm-microblaze/io.h
@@ -0,0 +1,128 @@
+/*
+ * include/asm-microblaze/io.h -- Misc I/O operations
+ *
+ *  Copyright (C) 2003     John Williams <jwilliams@itee.uq.edu.au>
+ *  Copyright (C) 2001,02  NEC Corporation
+ *  Copyright (C) 2001,02  Miles Bader <miles@gnu.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * Written by Miles Bader <miles@gnu.org>
+ * Microblaze port by John Williams
+ */
+
+#ifndef __MICROBLAZE_IO_H__
+#define __MICROBLAZE_IO_H__
+
+#define IO_SPACE_LIMIT 0xFFFFFFFF
+
+#define readb(addr) \
+  ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
+#define readw(addr) \
+  ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
+#define readl(addr) \
+  ({ unsigned long __v = (*(volatile unsigned long *) (addr)); __v; })
+
+#define writeb(b, addr) \
+  (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b, addr) \
+  (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b, addr) \
+  (void)((*(volatile unsigned int *) (addr)) = (b))
+
+#define memset_io(a,b,c)        memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c)    memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
+
+#define inb(addr)	readb (addr)
+#define inw(addr)	readw (addr)
+#define inl(addr)	readl (addr)
+#define outb(x, addr)	((void) writeb (x, addr))
+#define outw(x, addr)	((void) writew (x, addr))
+#define outl(x, addr)	((void) writel (x, addr))
+
+/* Some #definitions to keep strange Xilinx code happy */
+#define in_8(addr)	readb (addr)
+#define in_be16(addr)	readw (addr)
+#define in_be32(addr)	readl (addr)
+
+#define out_8(addr,x )	outb (x,addr)
+#define out_be16(addr,x )	outw (x,addr)
+#define out_be32(addr,x )	outl (x,addr)
+
+
+#define inb_p(port)		inb((port))
+#define outb_p(val, port)	outb((val), (port))
+#define inw_p(port)		inw((port))
+#define outw_p(val, port)	outw((val), (port))
+#define inl_p(port)		inl((port))
+#define outl_p(val, port)	outl((val), (port))
+
+/* Some defines to keep the MTD flash drivers happy */
+
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+
+static inline void io_insb (unsigned long port, void *dst, unsigned long count)
+{
+	unsigned char *p = dst;
+	while (count--)
+		*p++ = inb (port);
+}
+static inline void io_insw (unsigned long port, void *dst, unsigned long count)
+{
+	unsigned short *p = dst;
+	while (count--)
+		*p++ = inw (port);
+}
+static inline void io_insl (unsigned long port, void *dst, unsigned long count)
+{
+	unsigned long *p = dst;
+	while (count--)
+		*p++ = inl (port);
+}
+
+static inline void
+io_outsb (unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned char *p = src;
+	while (count--)
+		outb (*p++, port);
+}
+static inline void
+io_outsw (unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned short *p = src;
+	while (count--)
+		outw (*p++, port);
+}
+static inline void
+io_outsl (unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned long *p = src;
+	while (count--)
+		outl (*p++, port);
+}
+
+#define outsb(a,b,l) io_outsb(a,b,l)
+#define outsw(a,b,l) io_outsw(a,b,l)
+#define outsl(a,b,l) io_outsl(a,b,l)
+
+#define insb(a,b,l) io_insb(a,b,l)
+#define insw(a,b,l) io_insw(a,b,l)
+#define insl(a,b,l) io_insl(a,b,l)
+
+
+#define iounmap(addr)				((void)0)
+#define ioremap(physaddr, size)			(physaddr)
+#define ioremap_nocache(physaddr, size)		(physaddr)
+#define ioremap_writethrough(physaddr, size)	(physaddr)
+#define ioremap_fullcache(physaddr, size)	(physaddr)
+
+#endif /* __MICROBLAZE_IO_H__ */
diff --git a/include/asm-microblaze/platform.h b/include/asm-microblaze/platform.h
new file mode 100755
index 0000000..2096cce
--- /dev/null
+++ b/include/asm-microblaze/platform.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_SUZAKU
+#include <asm/suzaku.h>
+#endif
diff --git a/include/asm-microblaze/posix_types.h b/include/asm-microblaze/posix_types.h
new file mode 100755
index 0000000..9a2cc66
--- /dev/null
+++ b/include/asm-microblaze/posix_types.h
@@ -0,0 +1,76 @@
+/*
+ * include/asm-microblaze/posix_types.h -- Kernel versions of standard types
+ *
+ *  Copyright (C) 2003       John Williams <jwilliams@itee.uq.edu.au>
+ *  Copyright (C) 2001,2002  NEC Corporation
+ *  Copyright (C) 2001,2002  Miles Bader <miles@gnu.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * Written by Miles Bader <miles@gnu.org>
+ * Microblaze port by John Williams
+ */
+
+#ifndef __MICROBLAZE_POSIX_TYPES_H__
+#define __MICROBLAZE_POSIX_TYPES_H__
+
+#include <asm/bitops.h>
+
+
+typedef unsigned int	__kernel_dev_t;
+typedef unsigned long	__kernel_ino_t;
+typedef unsigned long long __kernel_ino64_t;
+typedef unsigned int	__kernel_mode_t;
+typedef unsigned int	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef long long	__kernel_loff_t;
+typedef int		__kernel_pid_t;
+typedef unsigned short	__kernel_ipc_pid_t;
+typedef unsigned int	__kernel_uid_t;
+typedef unsigned int	__kernel_gid_t;
+typedef unsigned int	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef int		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned short	__kernel_old_uid_t;
+typedef unsigned short	__kernel_old_gid_t;
+
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fd_set) \
+  __set_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
+#undef __FD_CLR
+#define __FD_CLR(fd, fd_set) \
+  __clear_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fd_set) \
+  __test_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
+#undef	__FD_ZERO
+#define __FD_ZERO(fd_set) \
+  memset (fd_set, 0, sizeof (*(fd_set *)fd_set))
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* __MICROBLAZE_POSIX_TYPES_H__ */
diff --git a/include/asm-microblaze/processor.h b/include/asm-microblaze/processor.h
new file mode 100755
index 0000000..78b8976
--- /dev/null
+++ b/include/asm-microblaze/processor.h
@@ -0,0 +1 @@
+/* FIXME: Implement this! */
diff --git a/include/asm-microblaze/ptrace.h b/include/asm-microblaze/ptrace.h
new file mode 100755
index 0000000..b796d4f
--- /dev/null
+++ b/include/asm-microblaze/ptrace.h
@@ -0,0 +1,116 @@
+/*
+ * include/asm-microblaze/ptrace.h -- Access to CPU registers
+ *
+ *  Copyright (C) 2003       John Williams <jwilliams@itee.uq.edu.au>
+ *  Copyright (C) 2001,2002  NEC Corporation
+ *  Copyright (C) 2001,2002  Miles Bader <miles@gnu.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * Written by Miles Bader <miles@gnu.org>
+ * Microblaze port by John Williams
+ */
+
+#ifndef __MICROBLAZE_PTRACE_H__
+#define __MICROBLAZE_PTRACE_H__
+
+
+/* Microblaze general purpose registers with special meanings.  */
+#define GPR_ZERO	0	/* constant zero */
+#define GPR_ASM		18	/* reserved for assembler */
+#define GPR_SP		1	/* stack pointer */
+#define GPR_GP		2	/* global data pointer */
+#define GPR_EP		30	/* `element pointer' */
+#define GPR_LP		15	/* link pointer (current return address) */
+
+/* These aren't official names, but they make some code more descriptive.  */
+#define GPR_ARG0	5
+#define GPR_ARG1	6
+#define GPR_ARG2	7
+#define GPR_ARG3	8
+#define GPR_ARG4	9
+#define GPR_ARG5	10
+#define GPR_RVAL0	3
+#define GPR_RVAL1	4
+#define GPR_RVAL	GPR_RVAL0
+
+#define NUM_GPRS	32
+
+/* `system' registers.  */
+/* Note these are old v850 values, microblaze has many fewer */
+#define SR_EIPC		0
+#define SR_EIPSW	1
+#define SR_FEPC		2
+#define SR_FEPSW	3
+#define SR_ECR		4
+#define SR_PSW		5
+#define SR_CTPC		16
+#define SR_CTPSW	17
+#define SR_DBPC		18
+#define SR_DBPSW	19
+#define SR_CTBP		20
+#define SR_DIR		21
+#define SR_ASID		23
+
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned long microblaze_reg_t;
+
+/* How processor state is stored on the stack during a syscall/signal.
+   If you change this structure, change the associated assembly-language
+   macros below too (PT_*)!  */
+struct pt_regs
+{
+	/* General purpose registers.  */
+	microblaze_reg_t gpr[NUM_GPRS];
+
+	microblaze_reg_t pc;		/* program counter */
+	microblaze_reg_t psw;		/* program status word */
+
+	microblaze_reg_t kernel_mode;	/* 1 if in `kernel mode', 0 if user mode */
+	microblaze_reg_t single_step;	/* 1 if in single step mode */
+};
+
+
+#define instruction_pointer(regs)	((regs)->pc)
+#define user_mode(regs)			(!(regs)->kernel_mode)
+
+/* When a struct pt_regs is used to save user state for a system call in
+   the kernel, the system call is stored in the space for R0 (since it's
+   never used otherwise, R0 being a constant 0).  Non-system-calls
+   simply store 0 there.  */
+#define PT_REGS_SYSCALL(regs)		(regs)->gpr[0]
+#define PT_REGS_SET_SYSCALL(regs, val)	((regs)->gpr[0] = (val))
+
+#endif /* !__ASSEMBLY__ */
+
+
+/* The number of bytes used to store each register.  */
+#define _PT_REG_SIZE	4
+
+/* Offset of a general purpose register in a stuct pt_regs.  */
+#define PT_GPR(num)	((num) * _PT_REG_SIZE)
+
+/* Offsets of various special registers & fields in a struct pt_regs.  */
+#define NUM_SPECIAL	4
+#define PT_PC		((NUM_GPRS + 0) * _PT_REG_SIZE)
+#define PT_PSW		((NUM_GPRS + 1) * _PT_REG_SIZE)
+#define PT_KERNEL_MODE	((NUM_GPRS + 2) * _PT_REG_SIZE)
+#define PT_SINGLESTEP	((NUM_GPRS + 3) * _PT_REG_SIZE)
+
+#define PT_SYSCALL	PT_GPR(0)
+
+/* Size of struct pt_regs, including alignment.  */
+#define PT_SIZE		((NUM_GPRS + NUM_SPECIAL) * _PT_REG_SIZE)
+
+/* These are `magic' values for PTRACE_PEEKUSR that return info about where
+   a process is located in memory.  */
+#define PT_TEXT_ADDR    (PT_SIZE + 1)
+#define PT_TEXT_LEN     (PT_SIZE + 2)
+#define PT_DATA_ADDR    (PT_SIZE + 3)
+#define PT_DATA_LEN     (PT_SIZE + 4)
+
+#endif /* __MICROBLAZE_PTRACE_H__ */
diff --git a/include/asm-microblaze/serial_xuartlite.h b/include/asm-microblaze/serial_xuartlite.h
new file mode 100755
index 0000000..6cd1e83
--- /dev/null
+++ b/include/asm-microblaze/serial_xuartlite.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/xuartlite_l.h>
diff --git a/include/asm-microblaze/string.h b/include/asm-microblaze/string.h
new file mode 100755
index 0000000..724f5bd
--- /dev/null
+++ b/include/asm-microblaze/string.h
@@ -0,0 +1,31 @@
+/*
+ * include/asm-microblaze/string.h -- Architecture specific string routines
+ *
+ *  Copyright (C) 2003       John Williams <jwilliams@itee.uq.edu.au>
+ *  Copyright (C) 2001,2002  NEC Corporation
+ *  Copyright (C) 2001,2002  Miles Bader <miles@gnu.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * Written by Miles Bader <miles@gnu.org>
+ * Microblaze port by John Williams
+ */
+
+#ifndef __MICROBLAZE_STRING_H__
+#define __MICROBLAZE_STRING_H__
+
+#if 0
+#define __HAVE_ARCH_BCOPY
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMMOVE
+
+extern void *memcpy (void *, const void *, __kernel_size_t);
+extern void bcopy (const char *, char *, int);
+extern void *memset (void *, int, __kernel_size_t);
+extern void *memmove (void *, const void *, __kernel_size_t);
+#endif
+
+#endif /* __MICROBLAZE_STRING_H__ */
diff --git a/include/asm-microblaze/suzaku.h b/include/asm-microblaze/suzaku.h
new file mode 100755
index 0000000..c57a144
--- /dev/null
+++ b/include/asm-microblaze/suzaku.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* System Register (GPIO) */
+#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000
+#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0)
diff --git a/include/asm-microblaze/system.h b/include/asm-microblaze/system.h
new file mode 100755
index 0000000..0297a11
--- /dev/null
+++ b/include/asm-microblaze/system.h
@@ -0,0 +1,161 @@
+/*
+ * include/asm-microblaze/system.h -- Low-level interrupt/thread ops
+ *
+ *  Copyright (C) 2003	John Williams (jwilliams@itee.uq.edu.au)
+ *			based upon microblaze version
+ *  Copyright (C) 2001	NEC Corporation
+ *  Copyright (C) 2001	Miles Bader <miles@gnu.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * Written by Miles Bader <miles@gnu.org>
+ * Microblaze port by John Williams
+ * Microblaze port by John Williams
+ */
+
+#ifndef __MICROBLAZE_SYSTEM_H__
+#define __MICROBLAZE_SYSTEM_H__
+
+#if 0
+#include <linux/linkage.h>
+#endif
+#include <asm/ptrace.h>
+
+#define prepare_to_switch()	do { } while (0)
+
+/*
+ * switch_to(n) should switch tasks to task ptr, first checking that
+ * ptr isn't the current task, in which case it does nothing.
+ */
+struct thread_struct;
+extern void *switch_thread (struct thread_struct *last,
+			    struct thread_struct *next);
+#define switch_to(prev,next,last) do {					\
+	if (prev != next) {						\
+		(last) = switch_thread (&prev->thread, &next->thread);	\
+	}								\
+} while (0)
+
+
+/* Enable/disable interrupts.  */
+#define __sti() \
+{								\
+	register unsigned tmp;					\
+	__asm__ __volatile__ ("					\
+			mfs	%0, rmsr;			\
+			ori	%0, %0, 2;			\
+			mts	rmsr, %0"			\
+			: "=r" (tmp)				\
+			:					\
+			: "memory");				\
+}
+
+#define __cli() \
+{								\
+	register unsigned tmp;					\
+	__asm__ __volatile__ ("					\
+			mfs	%0, rmsr;			\
+			andi	%0, %0, ~2;			\
+			mts	rmsr, %0"			\
+			: "=r" (tmp)				\
+			:					\
+			: "memory");				\
+}
+
+#define __save_flags(flags) \
+	__asm__ __volatile__ ("mfs	%0, rmsr" : "=r" (flags))
+#define __restore_flags(flags) \
+	__asm__ __volatile__ ("mts	rmsr, %0" :: "r" (flags))
+
+#define __save_flags_cli(flags) \
+{								\
+	register unsigned tmp;					\
+	__asm__ __volatile__ ("					\
+			mfs	%0, rmsr;			\
+			andi	%1, %0, ~2;			\
+			mts	rmsr, %1;"			\
+			: "=r" (flags), "=r" (tmp)		\
+			:					\
+			: "memory");				\
+}
+
+#define __save_flags_sti(flags)					\
+{								\
+	register unsigned tmp;					\
+	__asm__ __volatile__ ("					\
+			mfs	%0, rmsr;			\
+			ori	%1, %0, 2;			\
+			mts	rmsr, %1;"			\
+			: "=r" (flags) ,"=r" (tmp)		\
+			:					\
+			: "memory");				\
+}
+
+/* For spinlocks etc */
+#define local_irq_save(flags)	__save_flags_cli (flags)
+#define local_irq_set(flags)	__save_flags_sti (flags)
+#define local_irq_restore(flags) __restore_flags (flags)
+#define local_irq_disable()	__cli ()
+#define local_irq_enable()	__sti ()
+
+#define cli()			__cli ()
+#define sti()			__sti ()
+#define save_flags(flags)	__save_flags (flags)
+#define restore_flags(flags)	__restore_flags (flags)
+#define save_flags_cli(flags)	__save_flags_cli (flags)
+
+/*
+ * Force strict CPU ordering.
+ * Not really required on microblaze...
+ */
+#define nop()			__asm__ __volatile__ ("nop")
+#define mb()			__asm__ __volatile__ ("nop" ::: "memory")
+#define rmb()			mb ()
+#define wmb()			mb ()
+#define set_mb(var, value)	do { var = value; mb(); } while (0)
+#define set_wmb(var, value)	do { var = value; wmb (); } while (0)
+
+#ifdef CONFIG_SMP
+#define smp_mb()	mb ()
+#define smp_rmb()	rmb ()
+#define smp_wmb()	wmb ()
+#else
+#define smp_mb()	barrier ()
+#define smp_rmb()	barrier ()
+#define smp_wmb()	barrier ()
+#endif
+
+#define xchg(ptr, with) \
+  ((__typeof__ (*(ptr)))__xchg ((unsigned long)(with), (ptr), sizeof (*(ptr))))
+#define tas(ptr) (xchg ((ptr), 1))
+
+extern inline unsigned long __xchg (unsigned long with,
+				    __volatile__ void *ptr, int size)
+{
+	unsigned long tmp, flags;
+
+	save_flags_cli (flags);
+
+	switch (size) {
+	case 1:
+		tmp = *(unsigned char *)ptr;
+		*(unsigned char *)ptr = with;
+		break;
+	case 2:
+		tmp = *(unsigned short *)ptr;
+		*(unsigned short *)ptr = with;
+		break;
+	case 4:
+		tmp = *(unsigned long *)ptr;
+		*(unsigned long *)ptr = with;
+		break;
+	}
+
+	restore_flags (flags);
+
+	return tmp;
+}
+
+#endif /* __MICROBLAZE_SYSTEM_H__ */
diff --git a/include/asm-microblaze/types.h b/include/asm-microblaze/types.h
new file mode 100755
index 0000000..8c4bef2
--- /dev/null
+++ b/include/asm-microblaze/types.h
@@ -0,0 +1,57 @@
+#ifndef _ASM_TYPES_H
+#define _ASM_TYPES_H
+
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue.  However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ */
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_TYPES_H */
diff --git a/include/asm-microblaze/u-boot.h b/include/asm-microblaze/u-boot.h
new file mode 100755
index 0000000..e2035bd
--- /dev/null
+++ b/include/asm-microblaze/u-boot.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_
+
+typedef struct bd_info {
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+	unsigned long	bi_sramstart;	/* start of SRAM memory */
+	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
+	unsigned long	bi_baudrate;	/* Console Baudrate */
+} bd_t;
+
+
+#endif	/* _U_BOOT_H_ */
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
new file mode 100755
index 0000000..b8214b1
--- /dev/null
+++ b/include/asm-mips/addrspace.h
@@ -0,0 +1,82 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996 by Ralf Baechle
+ * Copyright (C) 2000 by Maciej W. Rozycki
+ *
+ * Defitions for the address spaces of the MIPS CPUs.
+ */
+#ifndef __ASM_MIPS_ADDRSPACE_H
+#define __ASM_MIPS_ADDRSPACE_H
+
+/*
+ * Memory segments (32bit kernel mode addresses)
+ */
+#define KUSEG			0x00000000
+#define KSEG0			0x80000000
+#define KSEG1			0xa0000000
+#define KSEG2			0xc0000000
+#define KSEG3			0xe0000000
+
+#define K0BASE	KSEG0
+
+/*
+ * Returns the kernel segment base of a given address
+ */
+#ifndef __ASSEMBLY__
+#define KSEGX(a)		(((unsigned long)(a)) & 0xe0000000)
+#else
+#define KSEGX(a)		((a) & 0xe0000000)
+#endif
+
+/*
+ * Returns the physical address of a KSEG0/KSEG1 address
+ */
+#ifndef __ASSEMBLY__
+#define PHYSADDR(a)		(((unsigned long)(a)) & 0x1fffffff)
+#else
+#define PHYSADDR(a)		((a) & 0x1fffffff)
+#endif
+
+/*
+ * Returns the uncached address of a sdram address
+ */
+#ifndef __ASSEMBLY__
+#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229)
+/* We use a 36 bit physical address map here and
+   cannot access physical memory directly from core */
+#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
+#else	/* !CONFIG_AU1X00 */
+#define UNCACHED_SDRAM(a) PHYSADDR(a)
+#endif	/* CONFIG_AU1X00 */
+#endif	/* __ASSEMBLY__ */
+/*
+ * Map an address to a certain kernel segment
+ */
+#ifndef __ASSEMBLY__
+#define KSEG0ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0))
+#define KSEG1ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1))
+#define KSEG2ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2))
+#define KSEG3ADDR(a)		((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3))
+#else
+#define KSEG0ADDR(a)		(((a) & 0x1fffffff) | KSEG0)
+#define KSEG1ADDR(a)		(((a) & 0x1fffffff) | KSEG1)
+#define KSEG2ADDR(a)		(((a) & 0x1fffffff) | KSEG2)
+#define KSEG3ADDR(a)		(((a) & 0x1fffffff) | KSEG3)
+#endif
+
+/*
+ * Memory segments (64bit kernel mode addresses)
+ */
+#define XKUSEG			0x0000000000000000
+#define XKSSEG			0x4000000000000000
+#define XKPHYS			0x8000000000000000
+#define XKSEG			0xc000000000000000
+#define CKSEG0			0xffffffff80000000
+#define CKSEG1			0xffffffffa0000000
+#define CKSSEG			0xffffffffc0000000
+#define CKSEG3			0xffffffffe0000000
+
+#endif /* __ASM_MIPS_ADDRSPACE_H */
diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h
new file mode 100755
index 0000000..4e19dc4
--- /dev/null
+++ b/include/asm-mips/au1x00.h
@@ -0,0 +1,1085 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *	Include file for Alchemy Semiconductor's Au1k CPU.
+ *
+ * Copyright 2000,2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         	ppopov@mvista.com or source@mvista.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+ /*
+  * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
+  */
+
+#ifndef _AU1X00_H_
+#define _AU1X00_H_
+
+#ifndef __ASSEMBLY__
+/* cpu pipeline flush */
+void static inline au_sync(void)
+{
+	__asm__ volatile ("sync");
+}
+
+void static inline au_sync_udelay(int us)
+{
+	__asm__ volatile ("sync");
+	udelay(us);
+}
+
+void static inline au_writeb(u8 val, int reg)
+{
+	*(volatile u8 *)(reg) = val;
+}
+
+void static inline au_writew(u16 val, int reg)
+{
+	*(volatile u16 *)(reg) = val;
+}
+
+void static inline au_writel(u32 val, int reg)
+{
+	*(volatile u32 *)(reg) = val;
+}
+
+static inline u8 au_readb(unsigned long port)
+{
+	return (*(volatile u8 *)port);
+}
+
+static inline u16 au_readw(unsigned long port)
+{
+	return (*(volatile u16 *)port);
+}
+
+static inline u32 au_readl(unsigned long port)
+{
+	return (*(volatile u32 *)port);
+}
+
+/* These next three functions should be a generic part of the MIPS
+ * kernel (with the 'au_' removed from the name) and selected for
+ * processors that support the instructions.
+ * Taken from PPC tree.  -- Dan
+ */
+/* Return the bit position of the most significant 1 bit in a word */
+static __inline__ int __ilog2(unsigned int x)
+{
+	int lz;
+
+	asm volatile (
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		".set\tmips32\n\t"
+		"clz\t%0,%1\n\t"
+		".set\tmips0\n\t"
+		".set\tat\n\t"
+		".set\treorder"
+		: "=r" (lz)
+		: "r" (x));
+
+	return 31 - lz;
+}
+
+static __inline__ int au_ffz(unsigned int x)
+{
+	if ((x = ~x) == 0)
+		return 32;
+	return __ilog2(x & -x);
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static __inline__ int au_ffs(int x)
+{
+	return __ilog2(x & -x) + 1;
+}
+
+#endif /* !ASSEMBLY */
+
+#ifdef CONFIG_PM
+/* no CP0 timer irq */
+#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
+#else
+#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
+#endif
+
+#define CP0_IWATCHLO		$18,1
+#define CP0_DEBUG		$23
+
+/* SDRAM Controller */
+#ifdef CONFIG_AU1550
+
+#define MEM_SDMODE0                0xB4000800
+#define MEM_SDMODE1                0xB4000808
+#define MEM_SDMODE2                0xB4000810
+
+#define MEM_SDADDR0                0xB4000820
+#define MEM_SDADDR1                0xB4000828
+#define MEM_SDADDR2                0xB4000830
+
+#define MEM_SDCONFIGA              0xB4000840
+#define MEM_SDCONFIGB              0xB4000848
+#define MEM_SDPRECMD               0xB40008c0
+#define MEM_SDAUTOREF              0xB40008c8
+
+#define MEM_SDWRMD0                0xB4000880
+#define MEM_SDWRMD1                0xB4000888
+#define MEM_SDWRMD2                0xB4000890
+
+#else /* CONFIG_AU1550 */
+
+#define MEM_SDMODE0                0xB4000000
+#define MEM_SDMODE1                0xB4000004
+#define MEM_SDMODE2                0xB4000008
+
+#define MEM_SDADDR0                0xB400000C
+#define MEM_SDADDR1                0xB4000010
+#define MEM_SDADDR2                0xB4000014
+
+#define MEM_SDREFCFG               0xB4000018
+#define MEM_SDPRECMD               0xB400001C
+#define MEM_SDAUTOREF              0xB4000020
+
+#define MEM_SDWRMD0                0xB4000024
+#define MEM_SDWRMD1                0xB4000028
+#define MEM_SDWRMD2                0xB400002C
+
+#endif /* CONFIG_AU1550 */
+
+#define MEM_SDSLEEP                0xB4000030
+#define MEM_SDSMCKE                0xB4000034
+
+/* Static Bus Controller */
+#define MEM_STCFG0                 0xB4001000
+#define MEM_STTIME0                0xB4001004
+#define MEM_STADDR0                0xB4001008
+
+#define MEM_STCFG1                 0xB4001010
+#define MEM_STTIME1                0xB4001014
+#define MEM_STADDR1                0xB4001018
+
+#define MEM_STCFG2                 0xB4001020
+#define MEM_STTIME2                0xB4001024
+#define MEM_STADDR2                0xB4001028
+
+#define MEM_STCFG3                 0xB4001030
+#define MEM_STTIME3                0xB4001034
+#define MEM_STADDR3                0xB4001038
+
+/* Interrupt Controller 0 */
+#define IC0_CFG0RD                 0xB0400040
+#define IC0_CFG0SET                0xB0400040
+#define IC0_CFG0CLR                0xB0400044
+
+#define IC0_CFG1RD                 0xB0400048
+#define IC0_CFG1SET                0xB0400048
+#define IC0_CFG1CLR                0xB040004C
+
+#define IC0_CFG2RD                 0xB0400050
+#define IC0_CFG2SET                0xB0400050
+#define IC0_CFG2CLR                0xB0400054
+
+#define IC0_REQ0INT                0xB0400054
+#define IC0_SRCRD                  0xB0400058
+#define IC0_SRCSET                 0xB0400058
+#define IC0_SRCCLR                 0xB040005C
+#define IC0_REQ1INT                0xB040005C
+
+#define IC0_ASSIGNRD               0xB0400060
+#define IC0_ASSIGNSET              0xB0400060
+#define IC0_ASSIGNCLR              0xB0400064
+
+#define IC0_WAKERD                 0xB0400068
+#define IC0_WAKESET                0xB0400068
+#define IC0_WAKECLR                0xB040006C
+
+#define IC0_MASKRD                 0xB0400070
+#define IC0_MASKSET                0xB0400070
+#define IC0_MASKCLR                0xB0400074
+
+#define IC0_RISINGRD               0xB0400078
+#define IC0_RISINGCLR              0xB0400078
+#define IC0_FALLINGRD              0xB040007C
+#define IC0_FALLINGCLR             0xB040007C
+
+#define IC0_TESTBIT                0xB0400080
+
+/* Interrupt Controller 1 */
+#define IC1_CFG0RD                 0xB1800040
+#define IC1_CFG0SET                0xB1800040
+#define IC1_CFG0CLR                0xB1800044
+
+#define IC1_CFG1RD                 0xB1800048
+#define IC1_CFG1SET                0xB1800048
+#define IC1_CFG1CLR                0xB180004C
+
+#define IC1_CFG2RD                 0xB1800050
+#define IC1_CFG2SET                0xB1800050
+#define IC1_CFG2CLR                0xB1800054
+
+#define IC1_REQ0INT                0xB1800054
+#define IC1_SRCRD                  0xB1800058
+#define IC1_SRCSET                 0xB1800058
+#define IC1_SRCCLR                 0xB180005C
+#define IC1_REQ1INT                0xB180005C
+
+#define IC1_ASSIGNRD               0xB1800060
+#define IC1_ASSIGNSET              0xB1800060
+#define IC1_ASSIGNCLR              0xB1800064
+
+#define IC1_WAKERD                 0xB1800068
+#define IC1_WAKESET                0xB1800068
+#define IC1_WAKECLR                0xB180006C
+
+#define IC1_MASKRD                 0xB1800070
+#define IC1_MASKSET                0xB1800070
+#define IC1_MASKCLR                0xB1800074
+
+#define IC1_RISINGRD               0xB1800078
+#define IC1_RISINGCLR              0xB1800078
+#define IC1_FALLINGRD              0xB180007C
+#define IC1_FALLINGCLR             0xB180007C
+
+#define IC1_TESTBIT                0xB1800080
+
+/* Interrupt Configuration Modes */
+#define INTC_INT_DISABLED                0
+#define INTC_INT_RISE_EDGE             0x1
+#define INTC_INT_FALL_EDGE             0x2
+#define INTC_INT_RISE_AND_FALL_EDGE    0x3
+#define INTC_INT_HIGH_LEVEL            0x5
+#define INTC_INT_LOW_LEVEL             0x6
+#define INTC_INT_HIGH_AND_LOW_LEVEL    0x7
+
+/* Interrupt Numbers */
+#define AU1X00_UART0_INT          0
+#define AU1000_UART1_INT          1 /* au1000 */
+#define AU1000_UART2_INT          2 /* au1000 */
+
+#define AU1500_PCI_INTA           1 /* au1500 */
+#define AU1500_PCI_INTB           2 /* au1500 */
+
+#define AU1X00_UART3_INT          3
+
+#define AU1000_SSI0_INT           4 /* au1000 */
+#define AU1000_SSI1_INT           5 /* au1000 */
+
+#define AU1500_PCI_INTC           4 /* au1500 */
+#define AU1500_PCI_INTD           5 /* au1500 */
+
+#define AU1X00_DMA_INT_BASE       6
+#define AU1X00_TOY_INT            14
+#define AU1X00_TOY_MATCH0_INT     15
+#define AU1X00_TOY_MATCH1_INT     16
+#define AU1X00_TOY_MATCH2_INT     17
+#define AU1X00_RTC_INT            18
+#define AU1X00_RTC_MATCH0_INT     19
+#define AU1X00_RTC_MATCH1_INT     20
+#define AU1X00_RTC_MATCH2_INT     21
+#define AU1000_IRDA_TX_INT        22 /* au1000 */
+#define AU1000_IRDA_RX_INT        23 /* au1000 */
+#define AU1X00_USB_DEV_REQ_INT    24
+#define AU1X00_USB_DEV_SUS_INT    25
+#define AU1X00_USB_HOST_INT       26
+#define AU1X00_ACSYNC_INT         27
+#define AU1X00_MAC0_DMA_INT       28
+#define AU1X00_MAC1_DMA_INT       29
+#define AU1X00_ETH0_IRQ           AU1X00_MAC0_DMA_INT
+#define AU1X00_ETH1_IRQ           AU1X00_MAC1_DMA_INT
+#define AU1000_I2S_UO_INT         30 /* au1000 */
+#define AU1X00_AC97C_INT          31
+#define AU1X00_LAST_INTC0_INT     AU1X00_AC97C_INT
+#define AU1X00_GPIO_0             32
+#define AU1X00_GPIO_1             33
+#define AU1X00_GPIO_2             34
+#define AU1X00_GPIO_3             35
+#define AU1X00_GPIO_4             36
+#define AU1X00_GPIO_5             37
+#define AU1X00_GPIO_6             38
+#define AU1X00_GPIO_7             39
+#define AU1X00_GPIO_8             40
+#define AU1X00_GPIO_9             41
+#define AU1X00_GPIO_10            42
+#define AU1X00_GPIO_11            43
+#define AU1X00_GPIO_12            44
+#define AU1X00_GPIO_13            45
+#define AU1X00_GPIO_14            46
+#define AU1X00_GPIO_15            47
+
+/* Au1000 only */
+#define AU1000_GPIO_16            48
+#define AU1000_GPIO_17            49
+#define AU1000_GPIO_18            50
+#define AU1000_GPIO_19            51
+#define AU1000_GPIO_20            52
+#define AU1000_GPIO_21            53
+#define AU1000_GPIO_22            54
+#define AU1000_GPIO_23            55
+#define AU1000_GPIO_24            56
+#define AU1000_GPIO_25            57
+#define AU1000_GPIO_26            58
+#define AU1000_GPIO_27            59
+#define AU1000_GPIO_28            60
+#define AU1000_GPIO_29            61
+#define AU1000_GPIO_30            62
+#define AU1000_GPIO_31            63
+
+/* Au1500 only */
+#define AU1500_GPIO_200           48
+#define AU1500_GPIO_201           49
+#define AU1500_GPIO_202           50
+#define AU1500_GPIO_203           51
+#define AU1500_GPIO_20            52
+#define AU1500_GPIO_204           53
+#define AU1500_GPIO_205           54
+#define AU1500_GPIO_23            55
+#define AU1500_GPIO_24            56
+#define AU1500_GPIO_25            57
+#define AU1500_GPIO_26            58
+#define AU1500_GPIO_27            59
+#define AU1500_GPIO_28            60
+#define AU1500_GPIO_206           61
+#define AU1500_GPIO_207           62
+#define AU1500_GPIO_208_215       63
+
+#define AU1X00_MAX_INTR           63
+
+#define AU1100_SD		2
+#define	AU1100_GPIO_208_215	29
+/* REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE */
+
+/* Programmable Counters 0 and 1 */
+#define SYS_BASE                   0xB1900000
+#define SYS_COUNTER_CNTRL          (SYS_BASE + 0x14)
+#define SYS_CNTRL_E1S            (1<<23)
+#define SYS_CNTRL_T1S            (1<<20)
+#define SYS_CNTRL_M21            (1<<19)
+#define SYS_CNTRL_M11            (1<<18)
+#define SYS_CNTRL_M01            (1<<17)
+#define SYS_CNTRL_C1S            (1<<16)
+#define SYS_CNTRL_BP             (1<<14)
+#define SYS_CNTRL_EN1            (1<<13)
+#define SYS_CNTRL_BT1            (1<<12)
+#define SYS_CNTRL_EN0            (1<<11)
+#define SYS_CNTRL_BT0            (1<<10)
+#define SYS_CNTRL_E0             (1<<8)
+#define SYS_CNTRL_E0S            (1<<7)
+#define SYS_CNTRL_32S            (1<<5)
+#define SYS_CNTRL_T0S            (1<<4)
+#define SYS_CNTRL_M20            (1<<3)
+#define SYS_CNTRL_M10            (1<<2)
+#define SYS_CNTRL_M00            (1<<1)
+#define SYS_CNTRL_C0S            (1<<0)
+
+/* Programmable Counter 0 Registers */
+#define SYS_TOYTRIM                 (SYS_BASE + 0)
+#define SYS_TOYWRITE                (SYS_BASE + 4)
+#define SYS_TOYMATCH0               (SYS_BASE + 8)
+#define SYS_TOYMATCH1               (SYS_BASE + 0xC)
+#define SYS_TOYMATCH2               (SYS_BASE + 0x10)
+#define SYS_TOYREAD                 (SYS_BASE + 0x40)
+
+/* Programmable Counter 1 Registers */
+#define SYS_RTCTRIM                 (SYS_BASE + 0x44)
+#define SYS_RTCWRITE                (SYS_BASE + 0x48)
+#define SYS_RTCMATCH0               (SYS_BASE + 0x4C)
+#define SYS_RTCMATCH1               (SYS_BASE + 0x50)
+#define SYS_RTCMATCH2               (SYS_BASE + 0x54)
+#define SYS_RTCREAD                 (SYS_BASE + 0x58)
+
+/* I2S Controller */
+#define I2S_DATA                    0xB1000000
+#define I2S_DATA_MASK        (0xffffff)
+#define I2S_CONFIG                0xB1000004
+#define I2S_CONFIG_XU        (1<<25)
+#define I2S_CONFIG_XO        (1<<24)
+#define I2S_CONFIG_RU        (1<<23)
+#define I2S_CONFIG_RO        (1<<22)
+#define I2S_CONFIG_TR        (1<<21)
+#define I2S_CONFIG_TE        (1<<20)
+#define I2S_CONFIG_TF        (1<<19)
+#define I2S_CONFIG_RR        (1<<18)
+#define I2S_CONFIG_RE        (1<<17)
+#define I2S_CONFIG_RF        (1<<16)
+#define I2S_CONFIG_PD        (1<<11)
+#define I2S_CONFIG_LB        (1<<10)
+#define I2S_CONFIG_IC        (1<<9)
+#define I2S_CONFIG_FM_BIT    7
+#define I2S_CONFIG_FM_MASK     (0x3 << I2S_CONFIG_FM_BIT)
+#define I2S_CONFIG_FM_I2S    (0x0 << I2S_CONFIG_FM_BIT)
+#define I2S_CONFIG_FM_LJ     (0x1 << I2S_CONFIG_FM_BIT)
+#define I2S_CONFIG_FM_RJ     (0x2 << I2S_CONFIG_FM_BIT)
+#define I2S_CONFIG_TN        (1<<6)
+#define I2S_CONFIG_RN        (1<<5)
+#define I2S_CONFIG_SZ_BIT    0
+#define I2S_CONFIG_SZ_MASK     (0x1F << I2S_CONFIG_SZ_BIT)
+
+#define I2S_CONTROL                0xB1000008
+#define I2S_CONTROL_D         (1<<1)
+#define I2S_CONTROL_CE        (1<<0)
+
+/* USB Host Controller */
+/* We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address */
+#define USB_OHCI_BASE             0x10100000
+#define USB_OHCI_LEN              0x00100000
+#define USB_HOST_CONFIG           0xB017fffc
+
+/* USB Device Controller */
+#define USBD_EP0RD                0xB0200000
+#define USBD_EP0WR                0xB0200004
+#define USBD_EP2WR                0xB0200008
+#define USBD_EP3WR                0xB020000C
+#define USBD_EP4RD                0xB0200010
+#define USBD_EP5RD                0xB0200014
+#define USBD_INTEN                0xB0200018
+#define USBD_INTSTAT              0xB020001C
+#define USBDEV_INT_SOF       (1<<12)
+#define USBDEV_INT_HF_BIT    6
+#define USBDEV_INT_HF_MASK   (0x3f << USBDEV_INT_HF_BIT)
+#define USBDEV_INT_CMPLT_BIT  0
+#define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
+#define USBD_CONFIG               0xB0200020
+#define USBD_EP0CS                0xB0200024
+#define USBD_EP2CS                0xB0200028
+#define USBD_EP3CS                0xB020002C
+#define USBD_EP4CS                0xB0200030
+#define USBD_EP5CS                0xB0200034
+#define USBDEV_CS_SU         (1<<14)
+#define USBDEV_CS_NAK        (1<<13)
+#define USBDEV_CS_ACK        (1<<12)
+#define USBDEV_CS_BUSY       (1<<11)
+#define USBDEV_CS_TSIZE_BIT  1
+#define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
+#define USBDEV_CS_STALL      (1<<0)
+#define USBD_EP0RDSTAT            0xB0200040
+#define USBD_EP0WRSTAT            0xB0200044
+#define USBD_EP2WRSTAT            0xB0200048
+#define USBD_EP3WRSTAT            0xB020004C
+#define USBD_EP4RDSTAT            0xB0200050
+#define USBD_EP5RDSTAT            0xB0200054
+#define USBDEV_FSTAT_FLUSH     (1<<6)
+#define USBDEV_FSTAT_UF        (1<<5)
+#define USBDEV_FSTAT_OF        (1<<4)
+#define USBDEV_FSTAT_FCNT_BIT  0
+#define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
+#define USBD_ENABLE               0xB0200058
+#define USBDEV_ENABLE (1<<1)
+#define USBDEV_CE     (1<<0)
+
+/* Ethernet Controllers  */
+#define AU1000_ETH0_BASE          0xB0500000
+#define AU1000_ETH1_BASE          0xB0510000
+#define AU1500_ETH0_BASE	  0xB1500000
+#define AU1500_ETH1_BASE	  0xB1510000
+#define AU1100_ETH0_BASE	  0xB0500000
+#define AU1550_ETH0_BASE	  0xB0500000
+#define AU1550_ETH1_BASE	  0xB0510000
+
+/* 4 byte offsets from AU1000_ETH_BASE */
+#define MAC_CONTROL                     0x0
+#define MAC_RX_ENABLE               (1<<2)
+#define MAC_TX_ENABLE               (1<<3)
+#define MAC_DEF_CHECK               (1<<5)
+#define MAC_SET_BL(X)       (((X)&0x3)<<6)
+#define MAC_AUTO_PAD                (1<<8)
+#define MAC_DISABLE_RETRY          (1<<10)
+#define MAC_DISABLE_BCAST          (1<<11)
+#define MAC_LATE_COL               (1<<12)
+#define MAC_HASH_MODE              (1<<13)
+#define MAC_HASH_ONLY              (1<<15)
+#define MAC_PASS_ALL               (1<<16)
+#define MAC_INVERSE_FILTER         (1<<17)
+#define MAC_PROMISCUOUS            (1<<18)
+#define MAC_PASS_ALL_MULTI         (1<<19)
+#define MAC_FULL_DUPLEX            (1<<20)
+#define MAC_NORMAL_MODE                 0
+#define MAC_INT_LOOPBACK           (1<<21)
+#define MAC_EXT_LOOPBACK           (1<<22)
+#define MAC_DISABLE_RX_OWN         (1<<23)
+#define MAC_BIG_ENDIAN             (1<<30)
+#define MAC_RX_ALL                 (1<<31)
+#define MAC_ADDRESS_HIGH                0x4
+#define MAC_ADDRESS_LOW                 0x8
+#define MAC_MCAST_HIGH                  0xC
+#define MAC_MCAST_LOW                  0x10
+#define MAC_MII_CNTRL                  0x14
+#define MAC_MII_BUSY                (1<<0)
+#define MAC_MII_READ                     0
+#define MAC_MII_WRITE               (1<<1)
+#define MAC_SET_MII_SELECT_REG(X)   (((X)&0x1f)<<6)
+#define MAC_SET_MII_SELECT_PHY(X)   (((X)&0x1f)<<11)
+#define MAC_MII_DATA                   0x18
+#define MAC_FLOW_CNTRL                 0x1C
+#define MAC_FLOW_CNTRL_BUSY         (1<<0)
+#define MAC_FLOW_CNTRL_ENABLE       (1<<1)
+#define MAC_PASS_CONTROL            (1<<2)
+#define MAC_SET_PAUSE(X)        (((X)&0xffff)<<16)
+#define MAC_VLAN1_TAG                  0x20
+#define MAC_VLAN2_TAG                  0x24
+
+/* Ethernet Controller Enable */
+#define AU1000_MAC0_ENABLE       0xB0520000
+#define AU1000_MAC1_ENABLE       0xB0520004
+#define AU1500_MAC0_ENABLE       0xB1520000
+#define AU1500_MAC1_ENABLE       0xB1520004
+#define AU1100_MAC0_ENABLE       0xB0520000
+#define AU1550_MAC0_ENABLE       0xB0520000
+#define AU1550_MAC1_ENABLE       0xB0520004
+
+#define MAC_EN_CLOCK_ENABLE         (1<<0)
+#define MAC_EN_RESET0               (1<<1)
+#define MAC_EN_TOSS                 (0<<2)
+#define MAC_EN_CACHEABLE            (1<<3)
+#define MAC_EN_RESET1               (1<<4)
+#define MAC_EN_RESET2               (1<<5)
+#define MAC_DMA_RESET               (1<<6)
+
+/* Ethernet Controller DMA Channels */
+
+#define MAC0_TX_DMA_ADDR         0xB4004000
+#define MAC1_TX_DMA_ADDR         0xB4004200
+/* offsets from MAC_TX_RING_ADDR address */
+#define MAC_TX_BUFF0_STATUS             0x0
+#define TX_FRAME_ABORTED            (1<<0)
+#define TX_JAB_TIMEOUT              (1<<1)
+#define TX_NO_CARRIER               (1<<2)
+#define TX_LOSS_CARRIER             (1<<3)
+#define TX_EXC_DEF                  (1<<4)
+#define TX_LATE_COLL_ABORT          (1<<5)
+#define TX_EXC_COLL                 (1<<6)
+#define TX_UNDERRUN                 (1<<7)
+#define TX_DEFERRED                 (1<<8)
+#define TX_LATE_COLL                (1<<9)
+#define TX_COLL_CNT_MASK         (0xF<<10)
+#define TX_PKT_RETRY               (1<<31)
+#define MAC_TX_BUFF0_ADDR                0x4
+#define TX_DMA_ENABLE               (1<<0)
+#define TX_T_DONE                   (1<<1)
+#define TX_GET_DMA_BUFFER(X)    (((X)>>2)&0x3)
+#define MAC_TX_BUFF0_LEN                 0x8
+#define MAC_TX_BUFF1_STATUS             0x10
+#define MAC_TX_BUFF1_ADDR               0x14
+#define MAC_TX_BUFF1_LEN                0x18
+#define MAC_TX_BUFF2_STATUS             0x20
+#define MAC_TX_BUFF2_ADDR               0x24
+#define MAC_TX_BUFF2_LEN                0x28
+#define MAC_TX_BUFF3_STATUS             0x30
+#define MAC_TX_BUFF3_ADDR               0x34
+#define MAC_TX_BUFF3_LEN                0x38
+
+#define MAC0_RX_DMA_ADDR         0xB4004100
+#define MAC1_RX_DMA_ADDR         0xB4004300
+/* offsets from MAC_RX_RING_ADDR */
+#define MAC_RX_BUFF0_STATUS              0x0
+#define RX_FRAME_LEN_MASK           0x3fff
+#define RX_WDOG_TIMER              (1<<14)
+#define RX_RUNT                    (1<<15)
+#define RX_OVERLEN                 (1<<16)
+#define RX_COLL                    (1<<17)
+#define RX_ETHER                   (1<<18)
+#define RX_MII_ERROR               (1<<19)
+#define RX_DRIBBLING               (1<<20)
+#define RX_CRC_ERROR               (1<<21)
+#define RX_VLAN1                   (1<<22)
+#define RX_VLAN2                   (1<<23)
+#define RX_LEN_ERROR               (1<<24)
+#define RX_CNTRL_FRAME             (1<<25)
+#define RX_U_CNTRL_FRAME           (1<<26)
+#define RX_MCAST_FRAME             (1<<27)
+#define RX_BCAST_FRAME             (1<<28)
+#define RX_FILTER_FAIL             (1<<29)
+#define RX_PACKET_FILTER           (1<<30)
+#define RX_MISSED_FRAME            (1<<31)
+
+#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN |  \
+		    RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
+		    RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
+#define MAC_RX_BUFF0_ADDR                0x4
+#define RX_DMA_ENABLE               (1<<0)
+#define RX_T_DONE                   (1<<1)
+#define RX_GET_DMA_BUFFER(X)    (((X)>>2)&0x3)
+#define RX_SET_BUFF_ADDR(X)     ((X)&0xffffffc0)
+#define MAC_RX_BUFF1_STATUS              0x10
+#define MAC_RX_BUFF1_ADDR                0x14
+#define MAC_RX_BUFF2_STATUS              0x20
+#define MAC_RX_BUFF2_ADDR                0x24
+#define MAC_RX_BUFF3_STATUS              0x30
+#define MAC_RX_BUFF3_ADDR                0x34
+
+
+/* UARTS 0-3 */
+#define UART0_ADDR                0xB1100000
+#define UART1_ADDR                0xB1200000
+#define UART2_ADDR                0xB1300000
+#define UART3_ADDR                0xB1400000
+#define UART_BASE                 UART0_ADDR
+#define UART_DEBUG_BASE           UART2_ADDR
+
+#define UART_RX		0	/* Receive buffer */
+#define UART_TX		4	/* Transmit buffer */
+#define UART_IER	8	/* Interrupt Enable Register */
+#define UART_IIR	0xC	/* Interrupt ID Register */
+#define UART_FCR	0x10	/* FIFO Control Register */
+#define UART_LCR	0x14	/* Line Control Register */
+#define UART_MCR	0x18	/* Modem Control Register */
+#define UART_LSR	0x1C	/* Line Status Register */
+#define UART_MSR	0x20	/* Modem Status Register */
+#define UART_CLK	0x28	/* Baud Rate Clock Divider */
+#define UART_ENABLE	0x100	/* Uart enable */
+
+#define UART_EN_CE      1       /* Clock enable */
+#define UART_EN_E       2       /* Enable */
+
+#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
+#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK	0xF0 /* Mask for the FIFO trigger range */
+#define UART_FCR_R_TRIGGER_1	0x00 /* Mask for receive trigger set at 1 */
+#define UART_FCR_R_TRIGGER_4	0x40 /* Mask for receive trigger set at 4 */
+#define UART_FCR_R_TRIGGER_8	0x80 /* Mask for receive trigger set at 8 */
+#define UART_FCR_R_TRIGGER_14   0xA0 /* Mask for receive trigger set at 14 */
+#define UART_FCR_T_TRIGGER_0	0x00 /* Mask for transmit trigger set at 0 */
+#define UART_FCR_T_TRIGGER_4	0x10 /* Mask for transmit trigger set at 4 */
+#define UART_FCR_T_TRIGGER_8    0x20 /* Mask for transmit trigger set at 8 */
+#define UART_FCR_T_TRIGGER_12	0x30 /* Mask for transmit trigger set at 12 */
+
+/*
+ * These are the definitions for the Line Control Register
+ */
+#define UART_LCR_SBC	0x40	/* Set break control */
+#define UART_LCR_SPAR	0x20	/* Stick parity (?) */
+#define UART_LCR_EPAR	0x10	/* Even parity select */
+#define UART_LCR_PARITY	0x08	/* Parity Enable */
+#define UART_LCR_STOP	0x04	/* Stop bits: 0=1 stop bit, 1= 2 stop bits */
+#define UART_LCR_WLEN5  0x00	/* Wordlength: 5 bits */
+#define UART_LCR_WLEN6  0x01	/* Wordlength: 6 bits */
+#define UART_LCR_WLEN7  0x02	/* Wordlength: 7 bits */
+#define UART_LCR_WLEN8  0x03	/* Wordlength: 8 bits */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_TEMT	0x40	/* Transmitter empty */
+#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
+#define UART_LSR_BI	0x10	/* Break interrupt indicator */
+#define UART_LSR_FE	0x08	/* Frame error indicator */
+#define UART_LSR_PE	0x04	/* Parity error indicator */
+#define UART_LSR_OE	0x02	/* Overrun error indicator */
+#define UART_LSR_DR	0x01	/* Receiver data ready */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
+#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
+#define UART_IIR_MSI	0x00	/* Modem status interrupt */
+#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
+#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
+#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
+#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
+#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
+#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
+
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
+#define UART_MCR_OUT2	0x08	/* Out2 complement */
+#define UART_MCR_OUT1	0x04	/* Out1 complement */
+#define UART_MCR_RTS	0x02	/* RTS complement */
+#define UART_MCR_DTR	0x01	/* DTR complement */
+
+/*
+ * These are the definitions for the Modem Status Register
+ */
+#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
+#define UART_MSR_RI	0x40	/* Ring Indicator */
+#define UART_MSR_DSR	0x20	/* Data Set Ready */
+#define UART_MSR_CTS	0x10	/* Clear to Send */
+#define UART_MSR_DDCD	0x08	/* Delta DCD */
+#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
+#define UART_MSR_DDSR	0x02	/* Delta DSR */
+#define UART_MSR_DCTS	0x01	/* Delta CTS */
+#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */
+
+
+/* SSIO */
+#define SSI0_STATUS                0xB1600000
+#define SSI_STATUS_BF              (1<<4)
+#define SSI_STATUS_OF              (1<<3)
+#define SSI_STATUS_UF              (1<<2)
+#define SSI_STATUS_D               (1<<1)
+#define SSI_STATUS_B               (1<<0)
+#define SSI0_INT                   0xB1600004
+#define SSI_INT_OI                 (1<<3)
+#define SSI_INT_UI                 (1<<2)
+#define SSI_INT_DI                 (1<<1)
+#define SSI0_INT_ENABLE            0xB1600008
+#define SSI_INTE_OIE               (1<<3)
+#define SSI_INTE_UIE               (1<<2)
+#define SSI_INTE_DIE               (1<<1)
+#define SSI0_CONFIG                0xB1600020
+#define SSI_CONFIG_AO              (1<<24)
+#define SSI_CONFIG_DO              (1<<23)
+#define SSI_CONFIG_ALEN_BIT        20
+#define SSI_CONFIG_ALEN_MASK       (0x7<<20)
+#define SSI_CONFIG_DLEN_BIT        16
+#define SSI_CONFIG_DLEN_MASK       (0x7<<16)
+#define SSI_CONFIG_DD              (1<<11)
+#define SSI_CONFIG_AD              (1<<10)
+#define SSI_CONFIG_BM_BIT          8
+#define SSI_CONFIG_BM_MASK         (0x3<<8)
+#define SSI_CONFIG_CE              (1<<7)
+#define SSI_CONFIG_DP              (1<<6)
+#define SSI_CONFIG_DL              (1<<5)
+#define SSI_CONFIG_EP              (1<<4)
+#define SSI0_ADATA                 0xB1600024
+#define SSI_AD_D                   (1<<24)
+#define SSI_AD_ADDR_BIT            16
+#define SSI_AD_ADDR_MASK           (0xff<<16)
+#define SSI_AD_DATA_BIT            0
+#define SSI_AD_DATA_MASK           (0xfff<<0)
+#define SSI0_CLKDIV                0xB1600028
+#define SSI0_CONTROL               0xB1600100
+#define SSI_CONTROL_CD             (1<<1)
+#define SSI_CONTROL_E              (1<<0)
+
+/* SSI1 */
+#define SSI1_STATUS                0xB1680000
+#define SSI1_INT                   0xB1680004
+#define SSI1_INT_ENABLE            0xB1680008
+#define SSI1_CONFIG                0xB1680020
+#define SSI1_ADATA                 0xB1680024
+#define SSI1_CLKDIV                0xB1680028
+#define SSI1_ENABLE                0xB1680100
+
+/*
+ * Register content definitions
+ */
+#define SSI_STATUS_BF				(1<<4)
+#define SSI_STATUS_OF				(1<<3)
+#define SSI_STATUS_UF				(1<<2)
+#define SSI_STATUS_D				(1<<1)
+#define SSI_STATUS_B				(1<<0)
+
+/* SSI_INT */
+#define SSI_INT_OI					(1<<3)
+#define SSI_INT_UI					(1<<2)
+#define SSI_INT_DI					(1<<1)
+
+/* SSI_INTEN */
+#define SSI_INTEN_OIE				(1<<3)
+#define SSI_INTEN_UIE				(1<<2)
+#define SSI_INTEN_DIE				(1<<1)
+
+#define SSI_CONFIG_AO				(1<<24)
+#define SSI_CONFIG_DO				(1<<23)
+#define SSI_CONFIG_ALEN				(7<<20)
+#define SSI_CONFIG_DLEN				(15<<16)
+#define SSI_CONFIG_DD				(1<<11)
+#define SSI_CONFIG_AD				(1<<10)
+#define SSI_CONFIG_BM				(3<<8)
+#define SSI_CONFIG_CE				(1<<7)
+#define SSI_CONFIG_DP				(1<<6)
+#define SSI_CONFIG_DL				(1<<5)
+#define SSI_CONFIG_EP				(1<<4)
+#define SSI_CONFIG_ALEN_N(N)		((N-1)<<20)
+#define SSI_CONFIG_DLEN_N(N)		((N-1)<<16)
+#define SSI_CONFIG_BM_HI			(0<<8)
+#define SSI_CONFIG_BM_LO			(1<<8)
+#define SSI_CONFIG_BM_CY			(2<<8)
+
+#define SSI_ADATA_D					(1<<24)
+#define SSI_ADATA_ADDR				(0xFF<<16)
+#define SSI_ADATA_DATA				(0x0FFF)
+#define SSI_ADATA_ADDR_N(N)			(N<<16)
+
+#define SSI_ENABLE_CD				(1<<1)
+#define SSI_ENABLE_E				(1<<0)
+
+
+/* IrDA Controller */
+#define IRDA_BASE                 0xB0300000
+#define IR_RING_PTR_STATUS        (IRDA_BASE+0x00)
+#define IR_RING_BASE_ADDR_H       (IRDA_BASE+0x04)
+#define IR_RING_BASE_ADDR_L       (IRDA_BASE+0x08)
+#define IR_RING_SIZE              (IRDA_BASE+0x0C)
+#define IR_RING_PROMPT            (IRDA_BASE+0x10)
+#define IR_RING_ADDR_CMPR         (IRDA_BASE+0x14)
+#define IR_INT_CLEAR              (IRDA_BASE+0x18)
+#define IR_CONFIG_1               (IRDA_BASE+0x20)
+#define IR_RX_INVERT_LED        (1<<0)
+#define IR_TX_INVERT_LED        (1<<1)
+#define IR_ST                   (1<<2)
+#define IR_SF                   (1<<3)
+#define IR_SIR                  (1<<4)
+#define IR_MIR                  (1<<5)
+#define IR_FIR                  (1<<6)
+#define IR_16CRC                (1<<7)
+#define IR_TD                   (1<<8)
+#define IR_RX_ALL               (1<<9)
+#define IR_DMA_ENABLE           (1<<10)
+#define IR_RX_ENABLE            (1<<11)
+#define IR_TX_ENABLE            (1<<12)
+#define IR_LOOPBACK             (1<<14)
+#define IR_SIR_MODE	          (IR_SIR | IR_DMA_ENABLE | \
+				   IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
+#define IR_SIR_FLAGS              (IRDA_BASE+0x24)
+#define IR_ENABLE                 (IRDA_BASE+0x28)
+#define IR_RX_STATUS            (1<<9)
+#define IR_TX_STATUS            (1<<10)
+#define IR_READ_PHY_CONFIG        (IRDA_BASE+0x2C)
+#define IR_WRITE_PHY_CONFIG       (IRDA_BASE+0x30)
+#define IR_MAX_PKT_LEN            (IRDA_BASE+0x34)
+#define IR_RX_BYTE_CNT            (IRDA_BASE+0x38)
+#define IR_CONFIG_2               (IRDA_BASE+0x3C)
+#define IR_MODE_INV             (1<<0)
+#define IR_ONE_PIN              (1<<1)
+#define IR_INTERFACE_CONFIG       (IRDA_BASE+0x40)
+
+/* GPIO */
+#define SYS_PINFUNC               0xB190002C
+#define SYS_PF_USB			(1<<15)	/* 2nd USB device/host */
+#define SYS_PF_U3			(1<<14)	/* GPIO23/U3TXD */
+#define SYS_PF_U2			(1<<13) /* GPIO22/U2TXD */
+#define SYS_PF_U1			(1<<12) /* GPIO21/U1TXD */
+#define SYS_PF_SRC			(1<<11)	/* GPIO6/SROMCKE */
+#define SYS_PF_CK5			(1<<10)	/* GPIO3/CLK5 */
+#define SYS_PF_CK4			(1<<9)	/* GPIO2/CLK4 */
+#define SYS_PF_IRF			(1<<8)	/* GPIO15/IRFIRSEL */
+#define SYS_PF_UR3			(1<<7)	/* GPIO[14:9]/UART3 */
+#define SYS_PF_I2D			(1<<6)	/* GPIO8/I2SDI */
+#define SYS_PF_I2S			(1<<5)	/* I2S/GPIO[29:31] */
+#define SYS_PF_NI2			(1<<4)	/* NI2/GPIO[24:28] */
+#define SYS_PF_U0			(1<<3)	/* U0TXD/GPIO20 */
+#define SYS_PF_RD			(1<<2)	/* IRTXD/GPIO19 */
+#define SYS_PF_A97			(1<<1)	/* AC97/SSL1 */
+#define SYS_PF_S0			(1<<0)	/* SSI_0/GPIO[16:18] */
+#define SYS_TRIOUTRD              0xB1900100
+#define SYS_TRIOUTCLR             0xB1900100
+#define SYS_OUTPUTRD              0xB1900108
+#define SYS_OUTPUTSET             0xB1900108
+#define SYS_OUTPUTCLR             0xB190010C
+#define SYS_PINSTATERD            0xB1900110
+#define SYS_PININPUTEN            0xB1900110
+
+/* GPIO2, Au1500 only */
+#define GPIO2_BASE                0xB1700000
+#define GPIO2_DIR                 (GPIO2_BASE + 0)
+#define GPIO2_DATA_EN             (GPIO2_BASE + 8)
+#define GPIO2_PIN_STATE           (GPIO2_BASE + 0xC)
+#define GPIO2_INT_ENABLE          (GPIO2_BASE + 0x10)
+#define GPIO2_ENABLE              (GPIO2_BASE + 0x14)
+
+/* Power Management */
+#define SYS_SCRATCH0              0xB1900018
+#define SYS_SCRATCH1              0xB190001C
+#define SYS_WAKEMSK               0xB1900034
+#define SYS_ENDIAN                0xB1900038
+#define SYS_POWERCTRL             0xB190003C
+#define SYS_WAKESRC               0xB190005C
+#define SYS_SLPPWR                0xB1900078
+#define SYS_SLEEP                 0xB190007C
+
+/* Clock Controller */
+#define SYS_FREQCTRL0             0xB1900020
+#define SYS_FC_FRDIV2_BIT         22
+#define SYS_FC_FRDIV2_MASK        (0xff << FQC2_FRDIV2_BIT)
+#define SYS_FC_FE2                (1<<21)
+#define SYS_FC_FS2                (1<<20)
+#define SYS_FC_FRDIV1_BIT         12
+#define SYS_FC_FRDIV1_MASK        (0xff << FQC2_FRDIV1_BIT)
+#define SYS_FC_FE1                (1<<11)
+#define SYS_FC_FS1                (1<<10)
+#define SYS_FC_FRDIV0_BIT         2
+#define SYS_FC_FRDIV0_MASK        (0xff << FQC2_FRDIV0_BIT)
+#define SYS_FC_FE0                (1<<1)
+#define SYS_FC_FS0                (1<<0)
+#define SYS_FREQCTRL1             0xB1900024
+#define SYS_FC_FRDIV5_BIT         22
+#define SYS_FC_FRDIV5_MASK        (0xff << FQC2_FRDIV5_BIT)
+#define SYS_FC_FE5                (1<<21)
+#define SYS_FC_FS5                (1<<20)
+#define SYS_FC_FRDIV4_BIT         12
+#define SYS_FC_FRDIV4_MASK        (0xff << FQC2_FRDIV4_BIT)
+#define SYS_FC_FE4                (1<<11)
+#define SYS_FC_FS4                (1<<10)
+#define SYS_FC_FRDIV3_BIT         2
+#define SYS_FC_FRDIV3_MASK        (0xff << FQC2_FRDIV3_BIT)
+#define SYS_FC_FE3                (1<<1)
+#define SYS_FC_FS3                (1<<0)
+#define SYS_CLKSRC                0xB1900028
+#define SYS_CS_ME1_BIT            27
+#define SYS_CS_ME1_MASK           (0x7<<CSC_ME1_BIT)
+#define SYS_CS_DE1                (1<<26)
+#define SYS_CS_CE1                (1<<25)
+#define SYS_CS_ME0_BIT            22
+#define SYS_CS_ME0_MASK           (0x7<<CSC_ME0_BIT)
+#define SYS_CS_DE0                (1<<21)
+#define SYS_CS_CE0                (1<<20)
+#define SYS_CS_MI2_BIT            17
+#define SYS_CS_MI2_MASK           (0x7<<CSC_MI2_BIT)
+#define SYS_CS_DI2                (1<<16)
+#define SYS_CS_CI2                (1<<15)
+#define SYS_CS_MUH_BIT            12
+#define SYS_CS_MUH_MASK           (0x7<<CSC_MUH_BIT)
+#define SYS_CS_DUH                (1<<11)
+#define SYS_CS_CUH                (1<<10)
+#define SYS_CS_MUD_BIT            7
+#define SYS_CS_MUD_MASK           (0x7<<CSC_MUD_BIT)
+#define SYS_CS_DUD                (1<<6)
+#define SYS_CS_CUD                (1<<5)
+#define SYS_CS_MIR_BIT            2
+#define SYS_CS_MIR_MASK           (0x7<<CSC_MIR_BIT)
+#define SYS_CS_DIR                (1<<1)
+#define SYS_CS_CIR                (1<<0)
+
+#define SYS_CS_MUX_AUX            0x1
+#define SYS_CS_MUX_FQ0            0x2
+#define SYS_CS_MUX_FQ1            0x3
+#define SYS_CS_MUX_FQ2            0x4
+#define SYS_CS_MUX_FQ3            0x5
+#define SYS_CS_MUX_FQ4            0x6
+#define SYS_CS_MUX_FQ5            0x7
+#define SYS_CPUPLL                0xB1900060
+#define SYS_AUXPLL                0xB1900064
+
+/* AC97 Controller */
+#define AC97C_CONFIG              0xB0000000
+#define AC97C_RECV_SLOTS_BIT  13
+#define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
+#define AC97C_XMIT_SLOTS_BIT  3
+#define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
+#define AC97C_SG              (1<<2)
+#define AC97C_SYNC            (1<<1)
+#define AC97C_RESET           (1<<0)
+#define AC97C_STATUS              0xB0000004
+#define AC97C_XU              (1<<11)
+#define AC97C_XO              (1<<10)
+#define AC97C_RU              (1<<9)
+#define AC97C_RO              (1<<8)
+#define AC97C_READY           (1<<7)
+#define AC97C_CP              (1<<6)
+#define AC97C_TR              (1<<5)
+#define AC97C_TE              (1<<4)
+#define AC97C_TF              (1<<3)
+#define AC97C_RR              (1<<2)
+#define AC97C_RE              (1<<1)
+#define AC97C_RF              (1<<0)
+#define AC97C_DATA                0xB0000008
+#define AC97C_CMD                 0xB000000C
+#define AC97C_WD_BIT          16
+#define AC97C_READ            (1<<7)
+#define AC97C_INDEX_MASK      0x7f
+#define AC97C_CNTRL               0xB0000010
+#define AC97C_RS              (1<<1)
+#define AC97C_CE              (1<<0)
+
+#define DB1000_BCSR_ADDR 0xAE000000
+#define DB1550_BCSR_ADDR 0xAF000000
+
+#ifdef CONFIG_DBAU1550
+#define DB1XX0_BCSR_ADDR DB1550_BCSR_ADDR
+#else
+#define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR
+#endif
+
+#ifdef CONFIG_SOC_AU1500
+/* Au1500 PCI Controller */
+#define Au1500_CFG_BASE           0xB4005000 /* virtual, kseg0 addr */
+#define Au1500_PCI_CMEM           (Au1500_CFG_BASE + 0)
+#define Au1500_PCI_CFG            (Au1500_CFG_BASE + 4)
+#define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
+#define Au1500_PCI_B2BMASK_CCH    (Au1500_CFG_BASE + 8)
+#define Au1500_PCI_B2B0_VID       (Au1500_CFG_BASE + 0xC)
+#define Au1500_PCI_B2B1_ID        (Au1500_CFG_BASE + 0x10)
+#define Au1500_PCI_MWMASK_DEV     (Au1500_CFG_BASE + 0x14)
+#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
+#define Au1500_PCI_ERR_ADDR       (Au1500_CFG_BASE + 0x1C)
+#define Au1500_PCI_SPEC_INTACK    (Au1500_CFG_BASE + 0x20)
+#define Au1500_PCI_ID             (Au1500_CFG_BASE + 0x100)
+#define Au1500_PCI_STATCMD        (Au1500_CFG_BASE + 0x104)
+#define Au1500_PCI_CLASSREV       (Au1500_CFG_BASE + 0x108)
+#define Au1500_PCI_HDRTYPE        (Au1500_CFG_BASE + 0x10C)
+#define Au1500_PCI_MBAR           (Au1500_CFG_BASE + 0x110)
+
+#define Au1500_PCI_HDR            0xB4005100 /* virtual, kseg0 addr */
+
+/* All of our structures, like pci resource, have 32 bit members.
+ * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
+ * hard to store 0x4 0000 0000 in a 32 bit type.  We require a small patch
+ * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
+ * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
+ * addresses.  For PCI IO, it's simpler because we get to do the ioremap
+ * ourselves and then adjust the device's resources.
+ */
+#define Au1500_EXT_CFG            0x600000000
+#define Au1500_EXT_CFG_TYPE1      0x680000000
+#define Au1500_PCI_IO_START       0x500000000
+#define Au1500_PCI_IO_END         0x5000FFFFF
+#define Au1500_PCI_MEM_START      0x440000000
+#define Au1500_PCI_MEM_END        0x443FFFFFF
+
+#define PCI_IO_START    (Au1500_PCI_IO_START + 0x300)
+#define PCI_IO_END      (Au1500_PCI_IO_END)
+#define PCI_MEM_START   (Au1500_PCI_MEM_START)
+#define PCI_MEM_END     (Au1500_PCI_MEM_END)
+#define PCI_FIRST_DEVFN (0<<3)
+#define PCI_LAST_DEVFN  (19<<3)
+
+#endif
+
+#if defined(CONFIG_SOC_AU1100) || (defined(CONFIG_SOC_AU1000) && !defined(CONFIG_MIPS_PB1000))
+/* no PCI bus controller */
+#define PCI_IO_START    0
+#define PCI_IO_END      0
+#define PCI_MEM_START   0
+#define PCI_MEM_END     0
+#define PCI_FIRST_DEVFN 0
+#define PCI_LAST_DEVFN  0
+#endif
+#define AU1X_SOCK0_IO        0xF00000000
+#define AU1X_SOCK0_PHYS_ATTR 0xF40000000
+#define AU1X_SOCK0_PHYS_MEM  0xF80000000
+
+/* pcmcia socket 1 needs external glue logic so the memory map
+ * differs from board to board.
+ */
+
+/* Only for db board, not older pb */
+#define AU1X_SOCK1_IO        0xF04000000
+#define AU1X_SOCK1_PHYS_ATTR 0xF44000000
+#define AU1X_SOCK1_PHYS_MEM  0xF84000000
+
+#endif
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
new file mode 100755
index 0000000..56d7225
--- /dev/null
+++ b/include/asm-mips/bitops.h
@@ -0,0 +1,912 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1994 - 1997, 1999, 2000  Ralf Baechle (ralf@gnu.org)
+ * Copyright (c) 2000  Silicon Graphics, Inc.
+ */
+#ifndef _ASM_BITOPS_H
+#define _ASM_BITOPS_H
+
+#include <linux/types.h>
+#include <asm/byteorder.h>		/* sigh ... */
+
+#ifdef __KERNEL__
+
+#include <asm/sgidefs.h>
+#include <asm/system.h>
+#include <linux/config.h>
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()	barrier()
+#define smp_mb__after_clear_bit()	barrier()
+
+/*
+ * Only disable interrupt for kernel mode stuff to keep usermode stuff
+ * that dares to use kernel include files alive.
+ */
+#define __bi_flags unsigned long flags
+#define __bi_cli() __cli()
+#define __bi_save_flags(x) __save_flags(x)
+#define __bi_save_and_cli(x) __save_and_cli(x)
+#define __bi_restore_flags(x) __restore_flags(x)
+#else
+#define __bi_flags
+#define __bi_cli()
+#define __bi_save_flags(x)
+#define __bi_save_and_cli(x)
+#define __bi_restore_flags(x)
+#endif /* __KERNEL__ */
+
+#ifdef CONFIG_CPU_HAS_LLSC
+
+#include <asm/mipsregs.h>
+
+/*
+ * These functions for MIPS ISA > 1 are interrupt and SMP proof and
+ * interrupt friendly
+ */
+
+/*
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered.  See __set_bit()
+ * if you do not require the atomic guarantees.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+extern __inline__ void
+set_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
+	unsigned long temp;
+
+	__asm__ __volatile__(
+		"1:\tll\t%0, %1\t\t# set_bit\n\t"
+		"or\t%0, %2\n\t"
+		"sc\t%0, %1\n\t"
+		"beqz\t%0, 1b"
+		: "=&r" (temp), "=m" (*m)
+		: "ir" (1UL << (nr & 0x1f)), "m" (*m));
+}
+
+/*
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+extern __inline__ void __set_bit(int nr, volatile void * addr)
+{
+	unsigned long * m = ((unsigned long *) addr) + (nr >> 5);
+
+	*m |= 1UL << (nr & 31);
+}
+
+/*
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered.  However, it does
+ * not contain a memory barrier, so if it is used for locking purposes,
+ * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
+ * in order to ensure changes are visible on other processors.
+ */
+extern __inline__ void
+clear_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
+	unsigned long temp;
+
+	__asm__ __volatile__(
+		"1:\tll\t%0, %1\t\t# clear_bit\n\t"
+		"and\t%0, %2\n\t"
+		"sc\t%0, %1\n\t"
+		"beqz\t%0, 1b\n\t"
+		: "=&r" (temp), "=m" (*m)
+		: "ir" (~(1UL << (nr & 0x1f))), "m" (*m));
+}
+
+/*
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+extern __inline__ void
+change_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
+	unsigned long temp;
+
+	__asm__ __volatile__(
+		"1:\tll\t%0, %1\t\t# change_bit\n\t"
+		"xor\t%0, %2\n\t"
+		"sc\t%0, %1\n\t"
+		"beqz\t%0, 1b"
+		: "=&r" (temp), "=m" (*m)
+		: "ir" (1UL << (nr & 0x1f)), "m" (*m));
+}
+
+/*
+ * __change_bit - Toggle a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike change_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+extern __inline__ void __change_bit(int nr, volatile void * addr)
+{
+	unsigned long * m = ((unsigned long *) addr) + (nr >> 5);
+
+	*m ^= 1UL << (nr & 31);
+}
+
+/*
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+extern __inline__ int
+test_and_set_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
+	unsigned long temp, res;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\t\t# test_and_set_bit\n"
+		"1:\tll\t%0, %1\n\t"
+		"or\t%2, %0, %3\n\t"
+		"sc\t%2, %1\n\t"
+		"beqz\t%2, 1b\n\t"
+		" and\t%2, %0, %3\n\t"
+		".set\treorder"
+		: "=&r" (temp), "=m" (*m), "=&r" (res)
+		: "r" (1UL << (nr & 0x1f)), "m" (*m)
+		: "memory");
+
+	return res != 0;
+}
+
+/*
+ * __test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+extern __inline__ int __test_and_set_bit(int nr, volatile void * addr)
+{
+	int mask, retval;
+	volatile int *a = addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+
+	return retval;
+}
+
+/*
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+extern __inline__ int
+test_and_clear_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
+	unsigned long temp, res;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\t\t# test_and_clear_bit\n"
+		"1:\tll\t%0, %1\n\t"
+		"or\t%2, %0, %3\n\t"
+		"xor\t%2, %3\n\t"
+		"sc\t%2, %1\n\t"
+		"beqz\t%2, 1b\n\t"
+		" and\t%2, %0, %3\n\t"
+		".set\treorder"
+		: "=&r" (temp), "=m" (*m), "=&r" (res)
+		: "r" (1UL << (nr & 0x1f)), "m" (*m)
+		: "memory");
+
+	return res != 0;
+}
+
+/*
+ * __test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+
+	return retval;
+}
+
+/*
+ * test_and_change_bit - Change a bit and return its new value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+extern __inline__ int
+test_and_change_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
+	unsigned long temp, res;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\t\t# test_and_change_bit\n"
+		"1:\tll\t%0, %1\n\t"
+		"xor\t%2, %0, %3\n\t"
+		"sc\t%2, %1\n\t"
+		"beqz\t%2, 1b\n\t"
+		" and\t%2, %0, %3\n\t"
+		".set\treorder"
+		: "=&r" (temp), "=m" (*m), "=&r" (res)
+		: "r" (1UL << (nr & 0x1f)), "m" (*m)
+		: "memory");
+
+	return res != 0;
+}
+
+/*
+ * __test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+extern __inline__ int __test_and_change_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+
+	return retval;
+}
+
+#else /* MIPS I */
+
+/*
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered.  See __set_bit()
+ * if you do not require the atomic guarantees.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+extern __inline__ void set_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile int	*a = addr;
+	__bi_flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	__bi_save_and_cli(flags);
+	*a |= mask;
+	__bi_restore_flags(flags);
+}
+
+/*
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+extern __inline__ void __set_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile int	*a = addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+/*
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered.  However, it does
+ * not contain a memory barrier, so if it is used for locking purposes,
+ * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
+ * in order to ensure changes are visible on other processors.
+ */
+extern __inline__ void clear_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile int	*a = addr;
+	__bi_flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	__bi_save_and_cli(flags);
+	*a &= ~mask;
+	__bi_restore_flags(flags);
+}
+
+/*
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+extern __inline__ void change_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile int	*a = addr;
+	__bi_flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	__bi_save_and_cli(flags);
+	*a ^= mask;
+	__bi_restore_flags(flags);
+}
+
+/*
+ * __change_bit - Toggle a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike change_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+extern __inline__ void __change_bit(int nr, volatile void * addr)
+{
+	unsigned long * m = ((unsigned long *) addr) + (nr >> 5);
+
+	*m ^= 1UL << (nr & 31);
+}
+
+/*
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+extern __inline__ int test_and_set_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+	__bi_flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	__bi_save_and_cli(flags);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	__bi_restore_flags(flags);
+
+	return retval;
+}
+
+/*
+ * __test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+extern __inline__ int __test_and_set_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+
+	return retval;
+}
+
+/*
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+extern __inline__ int test_and_clear_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+	__bi_flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	__bi_save_and_cli(flags);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	__bi_restore_flags(flags);
+
+	return retval;
+}
+
+/*
+ * __test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+extern __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+
+	return retval;
+}
+
+/*
+ * test_and_change_bit - Change a bit and return its new value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+extern __inline__ int test_and_change_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+	__bi_flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	__bi_save_and_cli(flags);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	__bi_restore_flags(flags);
+
+	return retval;
+}
+
+/*
+ * __test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+extern __inline__ int __test_and_change_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+
+	return retval;
+}
+
+#undef __bi_flags
+#undef __bi_cli
+#undef __bi_save_flags
+#undef __bi_restore_flags
+
+#endif /* MIPS I */
+
+/*
+ * test_bit - Determine whether a bit is set
+ * @nr: bit number to test
+ * @addr: Address to start counting from
+ */
+extern __inline__ int test_bit(int nr, volatile void *addr)
+{
+	return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0;
+}
+
+#ifndef __MIPSEB__
+
+/* Little endian versions. */
+
+/*
+ * find_first_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first zero bit, not the number of the byte
+ * containing a bit.
+ */
+extern __inline__ int find_first_zero_bit (void *addr, unsigned size)
+{
+	unsigned long dummy;
+	int res;
+
+	if (!size)
+		return 0;
+
+	__asm__ (".set\tnoreorder\n\t"
+		".set\tnoat\n"
+		"1:\tsubu\t$1,%6,%0\n\t"
+		"blez\t$1,2f\n\t"
+		"lw\t$1,(%5)\n\t"
+		"addiu\t%5,4\n\t"
+#if (_MIPS_ISA == _MIPS_ISA_MIPS2 ) || (_MIPS_ISA == _MIPS_ISA_MIPS3 ) || \
+    (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5 ) || \
+    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
+		"beql\t%1,$1,1b\n\t"
+		"addiu\t%0,32\n\t"
+#else
+		"addiu\t%0,32\n\t"
+		"beq\t%1,$1,1b\n\t"
+		"nop\n\t"
+		"subu\t%0,32\n\t"
+#endif
+#ifdef __MIPSEB__
+#error "Fix this for big endian"
+#endif /* __MIPSEB__ */
+		"li\t%1,1\n"
+		"1:\tand\t%2,$1,%1\n\t"
+		"beqz\t%2,2f\n\t"
+		"sll\t%1,%1,1\n\t"
+		"bnez\t%1,1b\n\t"
+		"add\t%0,%0,1\n\t"
+		".set\tat\n\t"
+		".set\treorder\n"
+		"2:"
+		: "=r" (res), "=r" (dummy), "=r" (addr)
+		: "0" ((signed int) 0), "1" ((unsigned int) 0xffffffff),
+		  "2" (addr), "r" (size)
+		: "$1");
+
+	return res;
+}
+
+/*
+ * find_next_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+extern __inline__ int find_next_zero_bit (void * addr, int size, int offset)
+{
+	unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
+	int set = 0, bit = offset & 31, res;
+	unsigned long dummy;
+
+	if (bit) {
+		/*
+		 * Look for zero in first byte
+		 */
+#ifdef __MIPSEB__
+#error "Fix this for big endian byte order"
+#endif
+		__asm__(".set\tnoreorder\n\t"
+			".set\tnoat\n"
+			"1:\tand\t$1,%4,%1\n\t"
+			"beqz\t$1,1f\n\t"
+			"sll\t%1,%1,1\n\t"
+			"bnez\t%1,1b\n\t"
+			"addiu\t%0,1\n\t"
+			".set\tat\n\t"
+			".set\treorder\n"
+			"1:"
+			: "=r" (set), "=r" (dummy)
+			: "0" (0), "1" (1 << bit), "r" (*p)
+			: "$1");
+		if (set < (32 - bit))
+			return set + offset;
+		set = 32 - bit;
+		p++;
+	}
+	/*
+	 * No zero yet, search remaining full bytes for a zero
+	 */
+	res = find_first_zero_bit(p, size - 32 * (p - (unsigned int *) addr));
+	return offset + set + res;
+}
+
+#endif /* !(__MIPSEB__) */
+
+/*
+ * ffz - find first zero in word.
+ * @word: The word to search
+ *
+ * Undefined if no zero exists, so code should check against ~0UL first.
+ */
+extern __inline__ unsigned long ffz(unsigned long word)
+{
+	unsigned int	__res;
+	unsigned int	mask = 1;
+
+	__asm__ (
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		"move\t%0,$0\n"
+		"1:\tand\t$1,%2,%1\n\t"
+		"beqz\t$1,2f\n\t"
+		"sll\t%1,1\n\t"
+		"bnez\t%1,1b\n\t"
+		"addiu\t%0,1\n\t"
+		".set\tat\n\t"
+		".set\treorder\n"
+		"2:\n\t"
+		: "=&r" (__res), "=r" (mask)
+		: "r" (word), "1" (mask)
+		: "$1");
+
+	return __res;
+}
+
+#ifdef __KERNEL__
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+#define ffs(x) generic_ffs(x)
+
+/*
+ * hweightN - returns the hamming weight of a N-bit word
+ * @x: the word to weigh
+ *
+ * The Hamming Weight of a number is the total number of bits set in it.
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __KERNEL__ */
+
+#ifdef __MIPSEB__
+/*
+ * find_next_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+extern __inline__ int find_next_zero_bit(void *addr, int size, int offset)
+{
+	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = *(p++);
+		tmp |= ~0UL >> (32-offset);
+		if (size < 32)
+			goto found_first;
+		if (~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size & ~31UL) {
+		if (~(tmp = *(p++)))
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+found_first:
+	tmp |= ~0UL << size;
+found_middle:
+	return result + ffz(tmp);
+}
+
+/* Linus sez that gcc can optimize the following correctly, we'll see if this
+ * holds on the Sparc as it does for the ALPHA.
+ */
+
+#if 0 /* Fool kernel-doc since it doesn't do macros yet */
+/*
+ * find_first_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first zero bit, not the number of the byte
+ * containing a bit.
+ */
+extern int find_first_zero_bit (void *addr, unsigned size);
+#endif
+
+#define find_first_zero_bit(addr, size) \
+	find_next_zero_bit((addr), (size), 0)
+
+#endif /* (__MIPSEB__) */
+
+/* Now for the ext2 filesystem bit operations and helper routines. */
+
+#ifdef __MIPSEB__
+extern __inline__ int ext2_set_bit(int nr, void * addr)
+{
+	int		mask, retval, flags;
+	unsigned char	*ADDR = (unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	save_and_cli(flags);
+	retval = (mask & *ADDR) != 0;
+	*ADDR |= mask;
+	restore_flags(flags);
+	return retval;
+}
+
+extern __inline__ int ext2_clear_bit(int nr, void * addr)
+{
+	int		mask, retval, flags;
+	unsigned char	*ADDR = (unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	save_and_cli(flags);
+	retval = (mask & *ADDR) != 0;
+	*ADDR &= ~mask;
+	restore_flags(flags);
+	return retval;
+}
+
+extern __inline__ int ext2_test_bit(int nr, const void * addr)
+{
+	int			mask;
+	const unsigned char	*ADDR = (const unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	return ((mask & *ADDR) != 0);
+}
+
+#define ext2_find_first_zero_bit(addr, size) \
+	ext2_find_next_zero_bit((addr), (size), 0)
+
+extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
+{
+	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if(offset) {
+		/* We hold the little endian value in tmp, but then the
+		 * shift is illegal. So we could keep a big endian value
+		 * in tmp, like this:
+		 *
+		 * tmp = __swab32(*(p++));
+		 * tmp |= ~0UL >> (32-offset);
+		 *
+		 * but this would decrease preformance, so we change the
+		 * shift:
+		 */
+		tmp = *(p++);
+		tmp |= __swab32(~0UL >> (32-offset));
+		if(size < 32)
+			goto found_first;
+		if(~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while(size & ~31UL) {
+		if(~(tmp = *(p++)))
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if(!size)
+		return result;
+	tmp = *p;
+
+found_first:
+	/* tmp is little endian, so we would have to swab the shift,
+	 * see above. But then we have to swab tmp below for ffz, so
+	 * we might as well do this here.
+	 */
+	return result + ffz(__swab32(tmp) | (~0UL << size));
+found_middle:
+	return result + ffz(__swab32(tmp));
+}
+#else /* !(__MIPSEB__) */
+
+/* Native ext2 byte ordering, just collapse using defines. */
+#define ext2_set_bit(nr, addr) test_and_set_bit((nr), (addr))
+#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr), (addr))
+#define ext2_test_bit(nr, addr) test_bit((nr), (addr))
+#define ext2_find_first_zero_bit(addr, size) find_first_zero_bit((addr), (size))
+#define ext2_find_next_zero_bit(addr, size, offset) \
+		find_next_zero_bit((addr), (size), (offset))
+
+#endif /* !(__MIPSEB__) */
+
+/*
+ * Bitmap functions for the minix filesystem.
+ * FIXME: These assume that Minix uses the native byte/bitorder.
+ * This limits the Minix filesystem's value for data exchange very much.
+ */
+#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr) set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr) test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
+
+#endif /* _ASM_BITOPS_H */
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
new file mode 100755
index 0000000..b9604cf
--- /dev/null
+++ b/include/asm-mips/byteorder.h
@@ -0,0 +1,31 @@
+/* $Id: byteorder.h,v 1.8 1998/11/02 09:29:32 ralf Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) by Ralf Baechle
+ */
+#ifndef _MIPS_BYTEORDER_H
+#define _MIPS_BYTEORDER_H
+
+#include <asm/types.h>
+
+#ifdef __GNUC__
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __GNUC__ */
+
+#if defined (__MIPSEB__)
+#  include <linux/byteorder/big_endian.h>
+#elif defined (__MIPSEL__)
+#  include <linux/byteorder/little_endian.h>
+#else
+#  error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
+#endif
+
+#endif /* _MIPS_BYTEORDER_H */
diff --git a/include/asm-mips/cachectl.h b/include/asm-mips/cachectl.h
new file mode 100755
index 0000000..9cc2b87
--- /dev/null
+++ b/include/asm-mips/cachectl.h
@@ -0,0 +1,24 @@
+/*
+ * cachectl.h -- defines for MIPS cache control system calls
+ *
+ * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ */
+#ifndef	__ASM_MIPS_CACHECTL
+#define	__ASM_MIPS_CACHECTL
+
+/*
+ * Options for cacheflush system call
+ */
+#define	ICACHE	(1<<0)		/* flush instruction cache        */
+#define	DCACHE	(1<<1)		/* writeback and flush data cache */
+#define	BCACHE	(ICACHE|DCACHE)	/* flush both caches              */
+
+/*
+ * Caching modes for the cachectl(2) call
+ *
+ * cachectl(2) is currently not supported and returns ENOSYS.
+ */
+#define CACHEABLE	0	/* make pages cacheable */
+#define UNCACHEABLE	1	/* make pages uncacheable */
+
+#endif	/* __ASM_MIPS_CACHECTL */
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
new file mode 100755
index 0000000..66b0b36
--- /dev/null
+++ b/include/asm-mips/cacheops.h
@@ -0,0 +1,47 @@
+/*
+ * Cache operations for the cache instruction.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * (C) Copyright 1996, 1997 by Ralf Baechle
+ */
+#ifndef	__ASM_MIPS_CACHEOPS_H
+#define	__ASM_MIPS_CACHEOPS_H
+
+/*
+ * Cache Operations
+ */
+#define Index_Invalidate_I      0x00
+#define Index_Writeback_Inv_D   0x01
+#define Index_Invalidate_SI     0x02
+#define Index_Writeback_Inv_SD  0x03
+#define Index_Load_Tag_I	0x04
+#define Index_Load_Tag_D	0x05
+#define Index_Load_Tag_SI	0x06
+#define Index_Load_Tag_SD	0x07
+#define Index_Store_Tag_I	0x08
+#define Index_Store_Tag_D	0x09
+#define Index_Store_Tag_SI	0x0A
+#define Index_Store_Tag_SD	0x0B
+#define Create_Dirty_Excl_D	0x0d
+#define Create_Dirty_Excl_SD	0x0f
+#define Hit_Invalidate_I	0x10
+#define Hit_Invalidate_D	0x11
+#define Hit_Invalidate_SI	0x12
+#define Hit_Invalidate_SD	0x13
+#define Fill			0x14
+#define Hit_Writeback_Inv_D	0x15
+					/* 0x16 is unused */
+#define Hit_Writeback_Inv_SD	0x17
+#define Hit_Writeback_I		0x18
+#define Hit_Writeback_D		0x19
+					/* 0x1a is unused */
+#define Hit_Writeback_SD	0x1b
+					/* 0x1c is unused */
+					/* 0x1e is unused */
+#define Hit_Set_Virtual_SI	0x1e
+#define Hit_Set_Virtual_SD	0x1f
+
+#endif	/* __ASM_MIPS_CACHEOPS_H */
diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h
new file mode 100755
index 0000000..a024194
--- /dev/null
+++ b/include/asm-mips/global_data.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2002-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+#include <asm/regdef.h>
+
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct	global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	have_console;	/* serial_init() was called */
+	unsigned long	ram_size;	/* RAM size */
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	void		**jt;		/* jump table */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC	0x00001		/* Code was relocated to RAM     */
+#define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized */
+#define	GD_FLG_SILENT	0x00004		/* Silent mode			 */
+
+#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("k0")
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/include/asm-mips/inca-ip.h b/include/asm-mips/inca-ip.h
new file mode 100755
index 0000000..e787a1d
--- /dev/null
+++ b/include/asm-mips/inca-ip.h
@@ -0,0 +1,2441 @@
+
+/******************************************************************************
+       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
+
+			       No Warranty
+   Because the program is licensed free of charge, there is no warranty for
+   the program, to the extent permitted by applicable law.  Except when
+   otherwise stated in writing the copyright holders and/or other parties
+   provide the program "as is" without warranty of any kind, either
+   expressed or implied, including, but not limited to, the implied
+   warranties of merchantability and fitness for a particular purpose. The
+   entire risk as to the quality and performance of the program is with
+   you.  should the program prove defective, you assume the cost of all
+   necessary servicing, repair or correction.
+
+   In no event unless required by applicable law or agreed to in writing
+   will any copyright holder, or any other party who may modify and/or
+   redistribute the program as permitted above, be liable to you for
+   damages, including any general, special, incidental or consequential
+   damages arising out of the use or inability to use the program
+   (including but not limited to loss of data or data being rendered
+   inaccurate or losses sustained by you or third parties or a failure of
+   the program to operate with any other programs), even if such holder or
+   other party has been advised of the possibility of such damages.
+******************************************************************************/
+
+
+/***********************************************************************/
+/*  Module      :  WDT register address and bits                       */
+/***********************************************************************/
+
+#define INCA_IP_WDT                          (0xB8000000)
+/***********************************************************************/
+
+
+/***Reset Status Register Power On***/
+#define INCA_IP_WDT_RST_SR                       ((volatile u32*)(INCA_IP_WDT+ 0x0014))
+
+/***Reset Request Register***/
+#define INCA_IP_WDT_RST_REQ                      ((volatile u32*)(INCA_IP_WDT+ 0x0010))
+#define INCA_IP_WDT_RST_REQ_SWBOOT                        (1 << 24)
+#define INCA_IP_WDT_RST_REQ_SWCFG                          (1 << 16)
+#define INCA_IP_WDT_RST_REQ_RRPHY                          (1 << 5)
+#define INCA_IP_WDT_RST_REQ_RRHSP                          (1 << 4)
+#define INCA_IP_WDT_RST_REQ_RRFPI                          (1 << 3)
+#define INCA_IP_WDT_RST_REQ_RREXT                          (1 << 2)
+#define INCA_IP_WDT_RST_REQ_RRDSP                          (1 << 1)
+#define INCA_IP_WDT_RST_REQ_RRCPU                          (1 << 0)
+
+/***NMI Status Register***/
+#define INCA_IP_WDT_NMISR                        ((volatile u32*)(INCA_IP_WDT+ 0x002C))
+#define INCA_IP_WDT_NMISR_NMIWDT                        (1 << 2)
+#define INCA_IP_WDT_NMISR_NMIPLL                        (1 << 1)
+#define INCA_IP_WDT_NMISR_NMIEXT                        (1 << 0)
+
+/***Manufacturer Identification Register***/
+#define INCA_IP_WDT_MANID                        ((volatile u32*)(INCA_IP_WDT+ 0x0070))
+#define INCA_IP_WDT_MANID_MANUF (value)              (((( 1 << 11) - 1) & (value)) << 5)
+
+/***Chip Identification Register***/
+#define INCA_IP_WDT_CHIPID                       ((volatile u32*)(INCA_IP_WDT+ 0x0074))
+#define INCA_IP_WDT_CHIPID_VERSION (value)            (((( 1 << 4) - 1) & (value)) << 28)
+#define INCA_IP_WDT_CHIPID_PART_NUMBER (value)        (((( 1 << 16) - 1) & (value)) << 12)
+#define INCA_IP_WDT_CHIPID_MANID (value)              (((( 1 << 11) - 1) & (value)) << 1)
+
+/***Redesign Tracing Identification Register***/
+#define INCA_IP_WDT_RTID                         ((volatile u32*)(INCA_IP_WDT+ 0x0078))
+#define INCA_IP_WDT_RTID_LC                              (1 << 15)
+#define INCA_IP_WDT_RTID_RIX (value)                (((( 1 << 3) - 1) & (value)) << 0)
+
+/***Watchdog Timer Control Register 0***/
+#define INCA_IP_WDT_WDT_CON0                    ((volatile u32*)(INCA_IP_WDT+ 0x0020))
+
+/***Watchdog Timer Control Register 1***/
+#define INCA_IP_WDT_WDT_CON1                    ((volatile u32*)(INCA_IP_WDT+ 0x0024))
+#define INCA_IP_WDT_WDT_CON1_WDTDR                          (1 << 3)
+#define INCA_IP_WDT_WDT_CON1_WDTIR                          (1 << 2)
+
+/***Watchdog Timer Status Register***/
+#define INCA_IP_WDT_WDT_SR                       ((volatile u32*)(INCA_IP_WDT+ 0x0028))
+#define INCA_IP_WDT_WDT_SR_WDTTIM (value)             (((( 1 << 16) - 1) & (value)) << 16)
+#define INCA_IP_WDT_WDT_SR_WDTPR                          (1 << 5)
+#define INCA_IP_WDT_WDT_SR_WDTTO                          (1 << 4)
+#define INCA_IP_WDT_WDT_SR_WDTDS                          (1 << 3)
+#define INCA_IP_WDT_WDT_SR_WDTIS                          (1 << 2)
+#define INCA_IP_WDT_WDT_SR_WDTOE                          (1 << 1)
+#define INCA_IP_WDT_WDT_SR_WDTAE                          (1 << 0)
+
+/***********************************************************************/
+/*  Module      :  CGU register address and bits                       */
+/***********************************************************************/
+
+#define INCA_IP_CGU                          (0xBF107000)
+/***********************************************************************/
+
+
+/***CGU PLL1 Control Register***/
+#define INCA_IP_CGU_CGU_PLL1CR                   ((volatile u32*)(INCA_IP_CGU+ 0x0008))
+#define INCA_IP_CGU_CGU_PLL1CR_SWRST                          (1 << 31)
+#define INCA_IP_CGU_CGU_PLL1CR_EN                              (1 << 30)
+#define INCA_IP_CGU_CGU_PLL1CR_NDIV (value)               (((( 1 << 6) - 1) & (value)) << 16)
+#define INCA_IP_CGU_CGU_PLL1CR_MDIV (value)               (((( 1 << 4) - 1) & (value)) << 0)
+
+/***CGU PLL0 Control Register***/
+#define INCA_IP_CGU_CGU_PLL0CR                   ((volatile u32*)(INCA_IP_CGU+ 0x0000))
+#define INCA_IP_CGU_CGU_PLL0CR_SWRST                          (1 << 31)
+#define INCA_IP_CGU_CGU_PLL0CR_EN                              (1 << 30)
+#define INCA_IP_CGU_CGU_PLL0CR_NDIV (value)               (((( 1 << 6) - 1) & (value)) << 16)
+#define INCA_IP_CGU_CGU_PLL0CR_MDIV (value)               (((( 1 << 4) - 1) & (value)) << 0)
+
+/***CGU PLL0 Status Register***/
+#define INCA_IP_CGU_CGU_PLL0SR                   ((volatile u32*)(INCA_IP_CGU+ 0x0004))
+#define INCA_IP_CGU_CGU_PLL0SR_LOCK                            (1 << 31)
+#define INCA_IP_CGU_CGU_PLL0SR_RCF                              (1 << 29)
+#define INCA_IP_CGU_CGU_PLL0SR_PLLBYP                        (1 << 15)
+
+/***CGU PLL1 Status Register***/
+#define INCA_IP_CGU_CGU_PLL1SR                   ((volatile u32*)(INCA_IP_CGU+ 0x000C))
+#define INCA_IP_CGU_CGU_PLL1SR_LOCK                            (1 << 31)
+#define INCA_IP_CGU_CGU_PLL1SR_RCF                              (1 << 29)
+#define INCA_IP_CGU_CGU_PLL1SR_PLLBYP                        (1 << 15)
+
+/***CGU Divider Control Register***/
+#define INCA_IP_CGU_CGU_DIVCR                    ((volatile u32*)(INCA_IP_CGU+ 0x0010))
+
+/***CGU Multiplexer Control Register***/
+#define INCA_IP_CGU_CGU_MUXCR                    ((volatile u32*)(INCA_IP_CGU+ 0x0014))
+#define INCA_IP_CGU_CGU_MUXCR_SWRST                          (1 << 31)
+#define INCA_IP_CGU_CGU_MUXCR_MUXII                          (1 << 1)
+#define INCA_IP_CGU_CGU_MUXCR_MUXI                            (1 << 0)
+
+/***CGU Fractional Divider Control Register***/
+#define INCA_IP_CGU_CGU_FDCR                    ((volatile u32*)(INCA_IP_CGU+ 0x0018))
+#define INCA_IP_CGU_CGU_FDCR_FDEN                            (1 << 31)
+#define INCA_IP_CGU_CGU_FDCR_INTEGER (value)            (((( 1 << 12) - 1) & (value)) << 16)
+#define INCA_IP_CGU_CGU_FDCR_FRACTION (value)          (((( 1 << 16) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/*  Module      :  PMU register address and bits                       */
+/***********************************************************************/
+
+#define INCA_IP_PMU                          (0xBF102000)
+/***********************************************************************/
+
+
+/***PM Global Enable Register***/
+#define INCA_IP_PMU_PM_GEN                       ((volatile u32*)(INCA_IP_PMU+ 0x0000))
+#define INCA_IP_PMU_PM_GEN_EN16                            (1 << 16)
+#define INCA_IP_PMU_PM_GEN_EN15                            (1 << 15)
+#define INCA_IP_PMU_PM_GEN_EN14                            (1 << 14)
+#define INCA_IP_PMU_PM_GEN_EN13                            (1 << 13)
+#define INCA_IP_PMU_PM_GEN_EN12                            (1 << 12)
+#define INCA_IP_PMU_PM_GEN_EN11                            (1 << 11)
+#define INCA_IP_PMU_PM_GEN_EN10                            (1 << 10)
+#define INCA_IP_PMU_PM_GEN_EN9                              (1 << 9)
+#define INCA_IP_PMU_PM_GEN_EN8                              (1 << 8)
+#define INCA_IP_PMU_PM_GEN_EN7                              (1 << 7)
+#define INCA_IP_PMU_PM_GEN_EN6                              (1 << 6)
+#define INCA_IP_PMU_PM_GEN_EN5                              (1 << 5)
+#define INCA_IP_PMU_PM_GEN_EN4                              (1 << 4)
+#define INCA_IP_PMU_PM_GEN_EN3                              (1 << 3)
+#define INCA_IP_PMU_PM_GEN_EN2                              (1 << 2)
+#define INCA_IP_PMU_PM_GEN_EN0                              (1 << 0)
+
+/***PM Power Down Enable Register***/
+#define INCA_IP_PMU_PM_PDEN                      ((volatile u32*)(INCA_IP_PMU+ 0x0008))
+#define INCA_IP_PMU_PM_PDEN_EN16                            (1 << 16)
+#define INCA_IP_PMU_PM_PDEN_EN15                            (1 << 15)
+#define INCA_IP_PMU_PM_PDEN_EN14                            (1 << 14)
+#define INCA_IP_PMU_PM_PDEN_EN13                            (1 << 13)
+#define INCA_IP_PMU_PM_PDEN_EN12                            (1 << 12)
+#define INCA_IP_PMU_PM_PDEN_EN11                            (1 << 11)
+#define INCA_IP_PMU_PM_PDEN_EN10                            (1 << 10)
+#define INCA_IP_PMU_PM_PDEN_EN9                              (1 << 9)
+#define INCA_IP_PMU_PM_PDEN_EN8                              (1 << 8)
+#define INCA_IP_PMU_PM_PDEN_EN7                              (1 << 7)
+#define INCA_IP_PMU_PM_PDEN_EN5                              (1 << 5)
+#define INCA_IP_PMU_PM_PDEN_EN4                              (1 << 4)
+#define INCA_IP_PMU_PM_PDEN_EN3                              (1 << 3)
+#define INCA_IP_PMU_PM_PDEN_EN2                              (1 << 2)
+#define INCA_IP_PMU_PM_PDEN_EN0                              (1 << 0)
+
+/***PM Wake-Up from Power Down Register***/
+#define INCA_IP_PMU_PM_WUP                       ((volatile u32*)(INCA_IP_PMU+ 0x0010))
+#define INCA_IP_PMU_PM_WUP_WUP16                          (1 << 16)
+#define INCA_IP_PMU_PM_WUP_WUP15                          (1 << 15)
+#define INCA_IP_PMU_PM_WUP_WUP14                          (1 << 14)
+#define INCA_IP_PMU_PM_WUP_WUP13                          (1 << 13)
+#define INCA_IP_PMU_PM_WUP_WUP12                          (1 << 12)
+#define INCA_IP_PMU_PM_WUP_WUP11                          (1 << 11)
+#define INCA_IP_PMU_PM_WUP_WUP10                          (1 << 10)
+#define INCA_IP_PMU_PM_WUP_WUP9                            (1 << 9)
+#define INCA_IP_PMU_PM_WUP_WUP8                            (1 << 8)
+#define INCA_IP_PMU_PM_WUP_WUP7                            (1 << 7)
+#define INCA_IP_PMU_PM_WUP_WUP5                            (1 << 5)
+#define INCA_IP_PMU_PM_WUP_WUP4                            (1 << 4)
+#define INCA_IP_PMU_PM_WUP_WUP3                            (1 << 3)
+#define INCA_IP_PMU_PM_WUP_WUP2                            (1 << 2)
+#define INCA_IP_PMU_PM_WUP_WUP0                            (1 << 0)
+
+/***PM Control Register***/
+#define INCA_IP_PMU_PM_CR                        ((volatile u32*)(INCA_IP_PMU+ 0x0014))
+#define INCA_IP_PMU_PM_CR_AWEN                            (1 << 31)
+#define INCA_IP_PMU_PM_CR_SWRST                          (1 << 30)
+#define INCA_IP_PMU_PM_CR_SWCR                            (1 << 2)
+#define INCA_IP_PMU_PM_CR_CRD (value)                (((( 1 << 2) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/*  Module      :  BCU register address and bits                       */
+/***********************************************************************/
+
+#define INCA_IP_BCU                          (0xB8000100)
+/***********************************************************************/
+
+
+/***BCU Control Register (0010H)***/
+#define INCA_IP_BCU_BCU_CON                      ((volatile u32*)(INCA_IP_BCU+ 0x0010))
+#define INCA_IP_BCU_BCU_CON_SPC (value)                (((( 1 << 8) - 1) & (value)) << 24)
+#define INCA_IP_BCU_BCU_CON_SPE                              (1 << 19)
+#define INCA_IP_BCU_BCU_CON_PSE                              (1 << 18)
+#define INCA_IP_BCU_BCU_CON_DBG                              (1 << 16)
+#define INCA_IP_BCU_BCU_CON_TOUT (value)               (((( 1 << 16) - 1) & (value)) << 0)
+
+/***BCU Error Control Capture Register (0020H)***/
+#define INCA_IP_BCU_BCU_ECON                    ((volatile u32*)(INCA_IP_BCU+ 0x0020))
+#define INCA_IP_BCU_BCU_ECON_TAG (value)                (((( 1 << 4) - 1) & (value)) << 24)
+#define INCA_IP_BCU_BCU_ECON_RDN                              (1 << 23)
+#define INCA_IP_BCU_BCU_ECON_WRN                              (1 << 22)
+#define INCA_IP_BCU_BCU_ECON_SVM                              (1 << 21)
+#define INCA_IP_BCU_BCU_ECON_ACK (value)                (((( 1 << 2) - 1) & (value)) << 19)
+#define INCA_IP_BCU_BCU_ECON_ABT                              (1 << 18)
+#define INCA_IP_BCU_BCU_ECON_RDY                              (1 << 17)
+#define INCA_IP_BCU_BCU_ECON_TOUT                            (1 << 16)
+#define INCA_IP_BCU_BCU_ECON_ERRCNT (value)             (((( 1 << 16) - 1) & (value)) << 0)
+#define INCA_IP_BCU_BCU_ECON_OPC (value)                (((( 1 << 4) - 1) & (value)) << 28)
+
+/***BCU Error Address Capture Register (0024 H)***/
+#define INCA_IP_BCU_BCU_EADD                    ((volatile u32*)(INCA_IP_BCU+ 0x0024))
+#define INCA_IP_BCU_BCU_EADD_FPIADR
+
+/***BCU Error Data Capture Register (0028H)***/
+#define INCA_IP_BCU_BCU_EDAT                    ((volatile u32*)(INCA_IP_BCU+ 0x0028))
+#define INCA_IP_BCU_BCU_EDAT_FPIDAT
+
+/***********************************************************************/
+/*  Module      :  MBC register address and bits                       */
+/***********************************************************************/
+
+#define INCA_IP_MBC                          (0xBF103000)
+/***********************************************************************/
+
+
+/***Mailbox CPU Configuration Register***/
+#define INCA_IP_MBC_MBC_CFG                      ((volatile u32*)(INCA_IP_MBC+ 0x0080))
+#define INCA_IP_MBC_MBC_CFG_SWAP (value)               (((( 1 << 2) - 1) & (value)) << 6)
+#define INCA_IP_MBC_MBC_CFG_RES                              (1 << 5)
+#define INCA_IP_MBC_MBC_CFG_FWID (value)               (((( 1 << 4) - 1) & (value)) << 1)
+#define INCA_IP_MBC_MBC_CFG_SIZE                            (1 << 0)
+
+/***Mailbox CPU Interrupt Status Register***/
+#define INCA_IP_MBC_MBC_ISR                      ((volatile u32*)(INCA_IP_MBC+ 0x0084))
+#define INCA_IP_MBC_MBC_ISR_B3DA                            (1 << 31)
+#define INCA_IP_MBC_MBC_ISR_B2DA                            (1 << 30)
+#define INCA_IP_MBC_MBC_ISR_B1E                              (1 << 29)
+#define INCA_IP_MBC_MBC_ISR_B0E                              (1 << 28)
+#define INCA_IP_MBC_MBC_ISR_WDT                              (1 << 27)
+#define INCA_IP_MBC_MBC_ISR_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
+
+/***Mailbox CPU Mask Register***/
+#define INCA_IP_MBC_MBC_MSK                      ((volatile u32*)(INCA_IP_MBC+ 0x0088))
+#define INCA_IP_MBC_MBC_MSK_B3DA                            (1 << 31)
+#define INCA_IP_MBC_MBC_MSK_B2DA                            (1 << 30)
+#define INCA_IP_MBC_MBC_MSK_B1E                              (1 << 29)
+#define INCA_IP_MBC_MBC_MSK_B0E                              (1 << 28)
+#define INCA_IP_MBC_MBC_MSK_WDT                              (1 << 27)
+#define INCA_IP_MBC_MBC_MSK_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
+
+/***Mailbox CPU Mask 01 Register***/
+#define INCA_IP_MBC_MBC_MSK01                    ((volatile u32*)(INCA_IP_MBC+ 0x008C))
+#define INCA_IP_MBC_MBC_MSK01_B3DA                            (1 << 31)
+#define INCA_IP_MBC_MBC_MSK01_B2DA                            (1 << 30)
+#define INCA_IP_MBC_MBC_MSK01_B1E                              (1 << 29)
+#define INCA_IP_MBC_MBC_MSK01_B0E                              (1 << 28)
+#define INCA_IP_MBC_MBC_MSK01_WDT                              (1 << 27)
+#define INCA_IP_MBC_MBC_MSK01_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
+
+/***Mailbox CPU Mask 10 Register***/
+#define INCA_IP_MBC_MBC_MSK10                    ((volatile u32*)(INCA_IP_MBC+ 0x0090))
+#define INCA_IP_MBC_MBC_MSK10_B3DA                            (1 << 31)
+#define INCA_IP_MBC_MBC_MSK10_B2DA                            (1 << 30)
+#define INCA_IP_MBC_MBC_MSK10_B1E                              (1 << 29)
+#define INCA_IP_MBC_MBC_MSK10_B0E                              (1 << 28)
+#define INCA_IP_MBC_MBC_MSK10_WDT                              (1 << 27)
+#define INCA_IP_MBC_MBC_MSK10_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
+
+/***Mailbox CPU Short Command Register***/
+#define INCA_IP_MBC_MBC_CMD                      ((volatile u32*)(INCA_IP_MBC+ 0x0094))
+#define INCA_IP_MBC_MBC_CMD_CS270 (value)             (((( 1 << 28) - 1) & (value)) << 0)
+
+/***Mailbox CPU Input Data of Buffer 0***/
+#define INCA_IP_MBC_MBC_ID0                      ((volatile u32*)(INCA_IP_MBC+ 0x0000))
+#define INCA_IP_MBC_MBC_ID0_INDATA
+
+/***Mailbox CPU Input Data of Buffer 1***/
+#define INCA_IP_MBC_MBC_ID1                      ((volatile u32*)(INCA_IP_MBC+ 0x0020))
+#define INCA_IP_MBC_MBC_ID1_INDATA
+
+/***Mailbox CPU Output Data of Buffer 2***/
+#define INCA_IP_MBC_MBC_OD2                      ((volatile u32*)(INCA_IP_MBC+ 0x0040))
+#define INCA_IP_MBC_MBC_OD2_OUTDATA
+
+/***Mailbox CPU Output Data of Buffer 3***/
+#define INCA_IP_MBC_MBC_OD3                      ((volatile u32*)(INCA_IP_MBC+ 0x0060))
+#define INCA_IP_MBC_MBC_OD3_OUTDATA
+
+/***Mailbox CPU Control Register of Buffer 0***/
+#define INCA_IP_MBC_MBC_CR0                      ((volatile u32*)(INCA_IP_MBC+ 0x0004))
+#define INCA_IP_MBC_MBC_CR0_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
+
+/***Mailbox CPU Control Register of Buffer 1***/
+#define INCA_IP_MBC_MBC_CR1                      ((volatile u32*)(INCA_IP_MBC+ 0x0024))
+#define INCA_IP_MBC_MBC_CR1_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
+
+/***Mailbox CPU Control Register of Buffer 2***/
+#define INCA_IP_MBC_MBC_CR2                      ((volatile u32*)(INCA_IP_MBC+ 0x0044))
+#define INCA_IP_MBC_MBC_CR2_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
+
+/***Mailbox CPU Control Register of Buffer 3***/
+#define INCA_IP_MBC_MBC_CR3                      ((volatile u32*)(INCA_IP_MBC+ 0x0064))
+#define INCA_IP_MBC_MBC_CR3_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
+
+/***Mailbox CPU Free Space of Buffer 0***/
+#define INCA_IP_MBC_MBC_FS0                      ((volatile u32*)(INCA_IP_MBC+ 0x0008))
+#define INCA_IP_MBC_MBC_FS0_FS
+
+/***Mailbox CPU Free Space of Buffer 1***/
+#define INCA_IP_MBC_MBC_FS1                      ((volatile u32*)(INCA_IP_MBC+ 0x0028))
+#define INCA_IP_MBC_MBC_FS1_FS
+
+/***Mailbox CPU Free Space of Buffer 2***/
+#define INCA_IP_MBC_MBC_FS2                      ((volatile u32*)(INCA_IP_MBC+ 0x0048))
+#define INCA_IP_MBC_MBC_FS2_FS
+
+/***Mailbox CPU Free Space of Buffer 3***/
+#define INCA_IP_MBC_MBC_FS3                      ((volatile u32*)(INCA_IP_MBC+ 0x0068))
+#define INCA_IP_MBC_MBC_FS3_FS
+
+/***Mailbox CPU Data Available in Buffer 0***/
+#define INCA_IP_MBC_MBC_DA0                      ((volatile u32*)(INCA_IP_MBC+ 0x000C))
+#define INCA_IP_MBC_MBC_DA0_DA
+
+/***Mailbox CPU Data Available in Buffer 1***/
+#define INCA_IP_MBC_MBC_DA1                      ((volatile u32*)(INCA_IP_MBC+ 0x002C))
+#define INCA_IP_MBC_MBC_DA1_DA
+
+/***Mailbox CPU Data Available in Buffer 2***/
+#define INCA_IP_MBC_MBC_DA2                      ((volatile u32*)(INCA_IP_MBC+ 0x004C))
+#define INCA_IP_MBC_MBC_DA2_DA
+
+/***Mailbox CPU Data Available in Buffer 3***/
+#define INCA_IP_MBC_MBC_DA3                      ((volatile u32*)(INCA_IP_MBC+ 0x006C))
+#define INCA_IP_MBC_MBC_DA3_DA
+
+/***Mailbox CPU Input Absolute Pointer of Buffer 0***/
+#define INCA_IP_MBC_MBC_IABS0                    ((volatile u32*)(INCA_IP_MBC+ 0x0010))
+#define INCA_IP_MBC_MBC_IABS0_IABS
+
+/***Mailbox CPU Input Absolute Pointer of Buffer 1***/
+#define INCA_IP_MBC_MBC_IABS1                    ((volatile u32*)(INCA_IP_MBC+ 0x0030))
+#define INCA_IP_MBC_MBC_IABS1_IABS
+
+/***Mailbox CPU Input Absolute Pointer of Buffer 2***/
+#define INCA_IP_MBC_MBC_IABS2                    ((volatile u32*)(INCA_IP_MBC+ 0x0050))
+#define INCA_IP_MBC_MBC_IABS2_IABS
+
+/***Mailbox CPU Input Absolute Pointer of Buffer 3***/
+#define INCA_IP_MBC_MBC_IABS3                    ((volatile u32*)(INCA_IP_MBC+ 0x0070))
+#define INCA_IP_MBC_MBC_IABS3_IABS
+
+/***Mailbox CPU Input Temporary Pointer of Buffer 0***/
+#define INCA_IP_MBC_MBC_ITMP0                    ((volatile u32*)(INCA_IP_MBC+ 0x0014))
+#define INCA_IP_MBC_MBC_ITMP0_ITMP
+
+/***Mailbox CPU Input Temporary Pointer of Buffer 1***/
+#define INCA_IP_MBC_MBC_ITMP1                    ((volatile u32*)(INCA_IP_MBC+ 0x0034))
+#define INCA_IP_MBC_MBC_ITMP1_ITMP
+
+/***Mailbox CPU Input Temporary Pointer of Buffer 2***/
+#define INCA_IP_MBC_MBC_ITMP2                    ((volatile u32*)(INCA_IP_MBC+ 0x0054))
+#define INCA_IP_MBC_MBC_ITMP2_ITMP
+
+/***Mailbox CPU Input Temporary Pointer of Buffer 3***/
+#define INCA_IP_MBC_MBC_ITMP3                    ((volatile u32*)(INCA_IP_MBC+ 0x0074))
+#define INCA_IP_MBC_MBC_ITMP3_ITMP
+
+/***Mailbox CPU Output Absolute Pointer of Buffer 0***/
+#define INCA_IP_MBC_MBC_OABS0                    ((volatile u32*)(INCA_IP_MBC+ 0x0018))
+#define INCA_IP_MBC_MBC_OABS0_OABS
+
+/***Mailbox CPU Output Absolute Pointer of Buffer 1***/
+#define INCA_IP_MBC_MBC_OABS1                    ((volatile u32*)(INCA_IP_MBC+ 0x0038))
+#define INCA_IP_MBC_MBC_OABS1_OABS
+
+/***Mailbox CPU Output Absolute Pointer of Buffer 2***/
+#define INCA_IP_MBC_MBC_OABS2                    ((volatile u32*)(INCA_IP_MBC+ 0x0058))
+#define INCA_IP_MBC_MBC_OABS2_OABS
+
+/***Mailbox CPU Output Absolute Pointer of Buffer 3***/
+#define INCA_IP_MBC_MBC_OABS3                    ((volatile u32*)(INCA_IP_MBC+ 0x0078))
+#define INCA_IP_MBC_MBC_OABS3_OABS
+
+/***Mailbox CPU Output Temporary Pointer of Buffer 0***/
+#define INCA_IP_MBC_MBC_OTMP0                    ((volatile u32*)(INCA_IP_MBC+ 0x001C))
+#define INCA_IP_MBC_MBC_OTMP0_OTMP
+
+/***Mailbox CPU Output Temporary Pointer of Buffer 1***/
+#define INCA_IP_MBC_MBC_OTMP1                    ((volatile u32*)(INCA_IP_MBC+ 0x003C))
+#define INCA_IP_MBC_MBC_OTMP1_OTMP
+
+/***Mailbox CPU Output Temporary Pointer of Buffer 2***/
+#define INCA_IP_MBC_MBC_OTMP2                    ((volatile u32*)(INCA_IP_MBC+ 0x005C))
+#define INCA_IP_MBC_MBC_OTMP2_OTMP
+
+/***Mailbox CPU Output Temporary Pointer of Buffer 3***/
+#define INCA_IP_MBC_MBC_OTMP3                    ((volatile u32*)(INCA_IP_MBC+ 0x007C))
+#define INCA_IP_MBC_MBC_OTMP3_OTMP
+
+/***DSP Control Register***/
+#define INCA_IP_MBC_DCTRL                        ((volatile u32*)(INCA_IP_MBC+ 0x00A0))
+#define INCA_IP_MBC_DCTRL_BA                              (1 << 0)
+#define INCA_IP_MBC_DCTRL_BMOD (value)               (((( 1 << 3) - 1) & (value)) << 1)
+#define INCA_IP_MBC_DCTRL_IDL                              (1 << 4)
+#define INCA_IP_MBC_DCTRL_RES                              (1 << 15)
+
+/***DSP Status Register***/
+#define INCA_IP_MBC_DSTA                         ((volatile u32*)(INCA_IP_MBC+ 0x00A4))
+#define INCA_IP_MBC_DSTA_IDLE                            (1 << 0)
+#define INCA_IP_MBC_DSTA_PD                              (1 << 1)
+
+/***DSP Test 1 Register***/
+#define INCA_IP_MBC_DTST1                        ((volatile u32*)(INCA_IP_MBC+ 0x00A8))
+#define INCA_IP_MBC_DTST1_ABORT                          (1 << 0)
+#define INCA_IP_MBC_DTST1_HWF32                          (1 << 1)
+#define INCA_IP_MBC_DTST1_HWF4M                          (1 << 2)
+#define INCA_IP_MBC_DTST1_HWFOP                          (1 << 3)
+
+/***********************************************************************/
+/*  Module      :  Switch register address and bits                    */
+/***********************************************************************/
+
+#define INCA_IP_Switch                       (0xBF104000)
+/***********************************************************************/
+
+
+/***Unknown Destination Register***/
+#define INCA_IP_Switch_UN_DEST                      ((volatile u32*)(INCA_IP_Switch+ 0x0000))
+#define INCA_IP_Switch_UN_DEST_CB                              (1 << 8)
+#define INCA_IP_Switch_UN_DEST_LB                              (1 << 7)
+#define INCA_IP_Switch_UN_DEST_PB                              (1 << 6)
+#define INCA_IP_Switch_UN_DEST_CM                              (1 << 5)
+#define INCA_IP_Switch_UN_DEST_LM                              (1 << 4)
+#define INCA_IP_Switch_UN_DEST_PM                              (1 << 3)
+#define INCA_IP_Switch_UN_DEST_CU                              (1 << 2)
+#define INCA_IP_Switch_UN_DEST_LU                              (1 << 1)
+#define INCA_IP_Switch_UN_DEST_PU                              (1 << 0)
+
+/***VLAN Control Register***/
+#define INCA_IP_Switch_VLAN_CTRL                    ((volatile u32*)(INCA_IP_Switch+ 0x0004))
+#define INCA_IP_Switch_VLAN_CTRL_SC                              (1 << 6)
+#define INCA_IP_Switch_VLAN_CTRL_SL                              (1 << 5)
+#define INCA_IP_Switch_VLAN_CTRL_SP                              (1 << 4)
+#define INCA_IP_Switch_VLAN_CTRL_TC                              (1 << 3)
+#define INCA_IP_Switch_VLAN_CTRL_TL                              (1 << 2)
+#define INCA_IP_Switch_VLAN_CTRL_TP                              (1 << 1)
+#define INCA_IP_Switch_VLAN_CTRL_VA                              (1 << 0)
+
+/***PC VLAN Configuration Register***/
+#define INCA_IP_Switch_PC_VLAN                      ((volatile u32*)(INCA_IP_Switch+ 0x0008))
+#define INCA_IP_Switch_PC_VLAN_PRI (value)                (((( 1 << 3) - 1) & (value)) << 12)
+#define INCA_IP_Switch_PC_VLAN_VLAN_ID (value)            (((( 1 << 12) - 1) & (value)) << 0)
+
+/***LAN VLAN Configuration Register***/
+#define INCA_IP_Switch_LAN_VLAN                    ((volatile u32*)(INCA_IP_Switch+ 0x000C))
+#define INCA_IP_Switch_LAN_VLAN_PRI (value)                (((( 1 << 3) - 1) & (value)) << 12)
+#define INCA_IP_Switch_LAN_VLAN_VLAN_ID (value)            (((( 1 << 12) - 1) & (value)) << 0)
+
+/***CPU VLAN Configuration Register***/
+#define INCA_IP_Switch_CPU_VLAN                    ((volatile u32*)(INCA_IP_Switch+ 0x0010))
+#define INCA_IP_Switch_CPU_VLAN_PRI (value)                (((( 1 << 3) - 1) & (value)) << 12)
+#define INCA_IP_Switch_CPU_VLAN_VLAN_ID (value)            (((( 1 << 12) - 1) & (value)) << 0)
+
+/***Priority CoS Mapping Register***/
+#define INCA_IP_Switch_PRI_CoS                      ((volatile u32*)(INCA_IP_Switch+ 0x0014))
+#define INCA_IP_Switch_PRI_CoS_P7                              (1 << 7)
+#define INCA_IP_Switch_PRI_CoS_P6                              (1 << 6)
+#define INCA_IP_Switch_PRI_CoS_P5                              (1 << 5)
+#define INCA_IP_Switch_PRI_CoS_P4                              (1 << 4)
+#define INCA_IP_Switch_PRI_CoS_P3                              (1 << 3)
+#define INCA_IP_Switch_PRI_CoS_P2                              (1 << 2)
+#define INCA_IP_Switch_PRI_CoS_P1                              (1 << 1)
+#define INCA_IP_Switch_PRI_CoS_P0                              (1 << 0)
+
+/***Spanning Tree Port Status Register***/
+#define INCA_IP_Switch_ST_PT                        ((volatile u32*)(INCA_IP_Switch+ 0x0018))
+#define INCA_IP_Switch_ST_PT_CPS (value)                (((( 1 << 2) - 1) & (value)) << 4)
+#define INCA_IP_Switch_ST_PT_LPS (value)                (((( 1 << 2) - 1) & (value)) << 2)
+#define INCA_IP_Switch_ST_PT_PPS (value)                (((( 1 << 2) - 1) & (value)) << 0)
+
+/***ARL Control Register***/
+#define INCA_IP_Switch_ARL_CTL                      ((volatile u32*)(INCA_IP_Switch+ 0x001C))
+#define INCA_IP_Switch_ARL_CTL_CHCC                            (1 << 15)
+#define INCA_IP_Switch_ARL_CTL_CHCL                            (1 << 14)
+#define INCA_IP_Switch_ARL_CTL_CHCP                            (1 << 13)
+#define INCA_IP_Switch_ARL_CTL_CC                              (1 << 12)
+#define INCA_IP_Switch_ARL_CTL_CL                              (1 << 11)
+#define INCA_IP_Switch_ARL_CTL_CP                              (1 << 10)
+#define INCA_IP_Switch_ARL_CTL_CG                              (1 << 9)
+#define INCA_IP_Switch_ARL_CTL_PS                              (1 << 8)
+#define INCA_IP_Switch_ARL_CTL_MRO                              (1 << 7)
+#define INCA_IP_Switch_ARL_CTL_SRC                              (1 << 6)
+#define INCA_IP_Switch_ARL_CTL_ATS                              (1 << 5)
+#define INCA_IP_Switch_ARL_CTL_AGE_TICK_SEL (value)       (((( 1 << 3) - 1) & (value)) << 2)
+#define INCA_IP_Switch_ARL_CTL_MAF                              (1 << 1)
+#define INCA_IP_Switch_ARL_CTL_ENL                              (1 << 0)
+#define INCA_IP_Switch_ARL_CTL_Res (value)                (((( 1 << 19) - 1) & (value)) << 13)
+
+/***CPU Access Control Register***/
+#define INCA_IP_Switch_CPU_ACTL                    ((volatile u32*)(INCA_IP_Switch+ 0x0020))
+#define INCA_IP_Switch_CPU_ACTL_RA                              (1 << 31)
+#define INCA_IP_Switch_CPU_ACTL_RW                              (1 << 30)
+#define INCA_IP_Switch_CPU_ACTL_Res (value)                (((( 1 << 21) - 1) & (value)) << 9)
+#define INCA_IP_Switch_CPU_ACTL_AVA                              (1 << 8)
+#define INCA_IP_Switch_CPU_ACTL_IDX (value)                (((( 1 << 8) - 1) & (value)) << 0)
+
+/***CPU Access Data Register 1***/
+#define INCA_IP_Switch_DATA1                        ((volatile u32*)(INCA_IP_Switch+ 0x0024))
+#define INCA_IP_Switch_DATA1_Data (value)               (((( 1 << 24) - 1) & (value)) << 0)
+
+/***CPU Access Data Register 2***/
+#define INCA_IP_Switch_DATA2                        ((volatile u32*)(INCA_IP_Switch+ 0x0028))
+#define INCA_IP_Switch_DATA2_Data
+
+/***CPU Port Control Register***/
+#define INCA_IP_Switch_CPU_PCTL                    ((volatile u32*)(INCA_IP_Switch+ 0x002C))
+#define INCA_IP_Switch_CPU_PCTL_DA_PORTS (value)          (((( 1 << 3) - 1) & (value)) << 11)
+#define INCA_IP_Switch_CPU_PCTL_DAC                              (1 << 10)
+#define INCA_IP_Switch_CPU_PCTL_MA_STATE (value)          (((( 1 << 3) - 1) & (value)) << 7)
+#define INCA_IP_Switch_CPU_PCTL_MAM                              (1 << 6)
+#define INCA_IP_Switch_CPU_PCTL_MA_Ports (value)          (((( 1 << 3) - 1) & (value)) << 3)
+#define INCA_IP_Switch_CPU_PCTL_MAC                              (1 << 2)
+#define INCA_IP_Switch_CPU_PCTL_EML                              (1 << 1)
+#define INCA_IP_Switch_CPU_PCTL_EDL                              (1 << 0)
+#define INCA_IP_Switch_CPU_PCTL_Res (value)                (((( 1 << 18) - 1) & (value)) << 14)
+
+/***DSCP CoS Mapping Register 1***/
+#define INCA_IP_Switch_DSCP_COS1                    ((volatile u32*)(INCA_IP_Switch+ 0x0030))
+#define INCA_IP_Switch_DSCP_COS1_DSCP
+
+/***DSCP CoS Mapping Register 1***/
+#define INCA_IP_Switch_DSCP_COS2                    ((volatile u32*)(INCA_IP_Switch+ 0x0034))
+#define INCA_IP_Switch_DSCP_COS2_DSCP
+
+/***PC WFQ Control Register***/
+#define INCA_IP_Switch_PC_WFQ_CTL                   ((volatile u32*)(INCA_IP_Switch+ 0x0080))
+#define INCA_IP_Switch_PC_WFQ_CTL_P1                              (1 << 9)
+#define INCA_IP_Switch_PC_WFQ_CTL_P0                              (1 << 8)
+#define INCA_IP_Switch_PC_WFQ_CTL_WT1 (value)                (((( 1 << 3) - 1) & (value)) << 5)
+#define INCA_IP_Switch_PC_WFQ_CTL_WT0 (value)                (((( 1 << 3) - 1) & (value)) << 2)
+#define INCA_IP_Switch_PC_WFQ_CTL_SCH_SEL (value)            (((( 1 << 2) - 1) & (value)) << 0)
+
+/***PC TX Control Register***/
+#define INCA_IP_Switch_PC_TX_CTL                    ((volatile u32*)(INCA_IP_Switch+ 0x0084))
+#define INCA_IP_Switch_PC_TX_CTL_ELR                              (1 << 1)
+#define INCA_IP_Switch_PC_TX_CTL_EER                              (1 << 0)
+
+/***LAN WFQ Control Register***/
+#define INCA_IP_Switch_LAN_WFQ_CTL                  ((volatile u32*)(INCA_IP_Switch+ 0x0100))
+#define INCA_IP_Switch_LAN_WFQ_CTL_P1                              (1 << 9)
+#define INCA_IP_Switch_LAN_WFQ_CTL_P0                              (1 << 8)
+#define INCA_IP_Switch_LAN_WFQ_CTL_WT1 (value)                (((( 1 << 3) - 1) & (value)) << 5)
+#define INCA_IP_Switch_LAN_WFQ_CTL_WT0 (value)                (((( 1 << 3) - 1) & (value)) << 2)
+#define INCA_IP_Switch_LAN_WFQ_CTL_SCH_SEL (value)            (((( 1 << 2) - 1) & (value)) << 0)
+
+/***LAN TX Control Register***/
+#define INCA_IP_Switch_LAN_TX_CTL                   ((volatile u32*)(INCA_IP_Switch+ 0x0104))
+#define INCA_IP_Switch_LAN_TX_CTL_ELR                              (1 << 1)
+#define INCA_IP_Switch_LAN_TX_CTL_EER                              (1 << 0)
+
+/***CPU WFQ Control Register***/
+#define INCA_IP_Switch_CPU_WFQ_CTL                  ((volatile u32*)(INCA_IP_Switch+ 0x0180))
+#define INCA_IP_Switch_CPU_WFQ_CTL_P1                              (1 << 9)
+#define INCA_IP_Switch_CPU_WFQ_CTL_P0                              (1 << 8)
+#define INCA_IP_Switch_CPU_WFQ_CTL_WT1 (value)                (((( 1 << 3) - 1) & (value)) << 5)
+#define INCA_IP_Switch_CPU_WFQ_CTL_WT0 (value)                (((( 1 << 3) - 1) & (value)) << 2)
+#define INCA_IP_Switch_CPU_WFQ_CTL_SCH_SEL (value)            (((( 1 << 2) - 1) & (value)) << 0)
+
+/***PM PC RX Watermark Register***/
+#define INCA_IP_Switch_PC_WM                        ((volatile u32*)(INCA_IP_Switch+ 0x0200))
+#define INCA_IP_Switch_PC_WM_RX_WM1 (value)             (((( 1 << 8) - 1) & (value)) << 24)
+#define INCA_IP_Switch_PC_WM_RX_WM2 (value)             (((( 1 << 8) - 1) & (value)) << 16)
+#define INCA_IP_Switch_PC_WM_RX_WM3 (value)             (((( 1 << 8) - 1) & (value)) << 8)
+#define INCA_IP_Switch_PC_WM_RX_WM4 (value)             (((( 1 << 8) - 1) & (value)) << 0)
+
+/***PM LAN RX Watermark Register***/
+#define INCA_IP_Switch_LAN_WM                       ((volatile u32*)(INCA_IP_Switch+ 0x0204))
+#define INCA_IP_Switch_LAN_WM_RX_WM1 (value)             (((( 1 << 8) - 1) & (value)) << 24)
+#define INCA_IP_Switch_LAN_WM_RX_WM2 (value)             (((( 1 << 8) - 1) & (value)) << 16)
+#define INCA_IP_Switch_LAN_WM_RX_WM3 (value)             (((( 1 << 8) - 1) & (value)) << 8)
+#define INCA_IP_Switch_LAN_WM_RX_WM4 (value)             (((( 1 << 8) - 1) & (value)) << 0)
+
+/***PM CPU RX Watermark Register***/
+#define INCA_IP_Switch_CPU_WM                       ((volatile u32*)(INCA_IP_Switch+ 0x0208))
+#define INCA_IP_Switch_CPU_WM_RX_WM1 (value)             (((( 1 << 8) - 1) & (value)) << 24)
+#define INCA_IP_Switch_CPU_WM_RX_WM2 (value)             (((( 1 << 8) - 1) & (value)) << 16)
+#define INCA_IP_Switch_CPU_WM_RX_WM3 (value)             (((( 1 << 8) - 1) & (value)) << 8)
+#define INCA_IP_Switch_CPU_WM_RX_WM4 (value)             (((( 1 << 8) - 1) & (value)) << 0)
+
+/***PM CPU RX Watermark Register***/
+#define INCA_IP_Switch_GBL_WM                       ((volatile u32*)(INCA_IP_Switch+ 0x020C))
+#define INCA_IP_Switch_GBL_WM_GBL_RX_WM1 (value)         (((( 1 << 8) - 1) & (value)) << 24)
+#define INCA_IP_Switch_GBL_WM_GBL_RX_WM2 (value)         (((( 1 << 8) - 1) & (value)) << 16)
+#define INCA_IP_Switch_GBL_WM_GBL_RX_WM3 (value)         (((( 1 << 8) - 1) & (value)) << 8)
+#define INCA_IP_Switch_GBL_WM_GBL_RX_WM4 (value)         (((( 1 << 8) - 1) & (value)) << 0)
+
+/***PM Control Register***/
+#define INCA_IP_Switch_PM_CTL                       ((volatile u32*)(INCA_IP_Switch+ 0x0210))
+#define INCA_IP_Switch_PM_CTL_GDN                              (1 << 3)
+#define INCA_IP_Switch_PM_CTL_CDN                              (1 << 2)
+#define INCA_IP_Switch_PM_CTL_LDN                              (1 << 1)
+#define INCA_IP_Switch_PM_CTL_PDN                              (1 << 0)
+
+/***PM Header Control Register***/
+#define INCA_IP_Switch_PMAC_HD_CTL                  ((volatile u32*)(INCA_IP_Switch+ 0x0280))
+#define INCA_IP_Switch_PMAC_HD_CTL_RL2                              (1 << 21)
+#define INCA_IP_Switch_PMAC_HD_CTL_RC                              (1 << 20)
+#define INCA_IP_Switch_PMAC_HD_CTL_CM                              (1 << 19)
+#define INCA_IP_Switch_PMAC_HD_CTL_CV                              (1 << 18)
+#define INCA_IP_Switch_PMAC_HD_CTL_TYPE_LEN (value)          (((( 1 << 16) - 1) & (value)) << 2)
+#define INCA_IP_Switch_PMAC_HD_CTL_TAG                              (1 << 1)
+#define INCA_IP_Switch_PMAC_HD_CTL_ADD                              (1 << 0)
+
+/***PM Source Address Register 1***/
+#define INCA_IP_Switch_PMAC_SA1                    ((volatile u32*)(INCA_IP_Switch+ 0x0284))
+#define INCA_IP_Switch_PMAC_SA1_SA_47_32 (value)          (((( 1 << 16) - 1) & (value)) << 0)
+
+/***PM Source Address Register 2***/
+#define INCA_IP_Switch_PMAC_SA2                    ((volatile u32*)(INCA_IP_Switch+ 0x0288))
+#define INCA_IP_Switch_PMAC_SA2_SA_31_0
+
+/***PM Dest Address Register 1***/
+#define INCA_IP_Switch_PMAC_DA1                    ((volatile u32*)(INCA_IP_Switch+ 0x028C))
+#define INCA_IP_Switch_PMAC_DA1_DA_47_32 (value)          (((( 1 << 16) - 1) & (value)) << 0)
+
+/***PM Dest Address Register 2***/
+#define INCA_IP_Switch_PMAC_DA2                    ((volatile u32*)(INCA_IP_Switch+ 0x0290))
+#define INCA_IP_Switch_PMAC_DA2_DA_31_0
+
+/***PM VLAN Register***/
+#define INCA_IP_Switch_PMAC_VLAN                    ((volatile u32*)(INCA_IP_Switch+ 0x0294))
+#define INCA_IP_Switch_PMAC_VLAN_PRI (value)                (((( 1 << 3) - 1) & (value)) << 13)
+#define INCA_IP_Switch_PMAC_VLAN_CFI                              (1 << 12)
+#define INCA_IP_Switch_PMAC_VLAN_VLANID (value)             (((( 1 << 12) - 1) & (value)) << 0)
+
+/***PM TX IPG Counter Register***/
+#define INCA_IP_Switch_PMAC_TX_IPG                  ((volatile u32*)(INCA_IP_Switch+ 0x0298))
+#define INCA_IP_Switch_PMAC_TX_IPG_IPGCNT (value)             (((( 1 << 8) - 1) & (value)) << 0)
+
+/***PM RX IPG Counter Register***/
+#define INCA_IP_Switch_PMAC_RX_IPG                  ((volatile u32*)(INCA_IP_Switch+ 0x029C))
+#define INCA_IP_Switch_PMAC_RX_IPG_IPGCNT (value)             (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Mirror Register***/
+#define INCA_IP_Switch_MRR                          ((volatile u32*)(INCA_IP_Switch+ 0x0300))
+#define INCA_IP_Switch_MRR_MRR (value)                (((( 1 << 2) - 1) & (value)) << 6)
+#define INCA_IP_Switch_MRR_EC                              (1 << 5)
+#define INCA_IP_Switch_MRR_EL                              (1 << 4)
+#define INCA_IP_Switch_MRR_EP                              (1 << 3)
+#define INCA_IP_Switch_MRR_IC                              (1 << 2)
+#define INCA_IP_Switch_MRR_IL                              (1 << 1)
+#define INCA_IP_Switch_MRR_IP                              (1 << 0)
+
+/***Packet Length Register***/
+#define INCA_IP_Switch_PKT_LEN                      ((volatile u32*)(INCA_IP_Switch+ 0x0304))
+#define INCA_IP_Switch_PKT_LEN_ADD                              (1 << 11)
+#define INCA_IP_Switch_PKT_LEN_MAX_PKT_LEN (value)        (((( 1 << 11) - 1) & (value)) << 0)
+
+/***MDIO Access Register***/
+#define INCA_IP_Switch_MDIO_ACC                    ((volatile u32*)(INCA_IP_Switch+ 0x0480))
+#define INCA_IP_Switch_MDIO_ACC_RA                              (1 << 31)
+#define INCA_IP_Switch_MDIO_ACC_RW                              (1 << 30)
+#define INCA_IP_Switch_MDIO_ACC_PHY_ADDR (value)          (((( 1 << 5) - 1) & (value)) << 21)
+#define INCA_IP_Switch_MDIO_ACC_REG_ADDR (value)          (((( 1 << 5) - 1) & (value)) << 16)
+#define INCA_IP_Switch_MDIO_ACC_PHY_DATA (value)          (((( 1 << 16) - 1) & (value)) << 0)
+
+/***Ethernet PHY Register***/
+#define INCA_IP_Switch_EPHY                         ((volatile u32*)(INCA_IP_Switch+ 0x0484))
+#define INCA_IP_Switch_EPHY_SL                              (1 << 7)
+#define INCA_IP_Switch_EPHY_SP                              (1 << 6)
+#define INCA_IP_Switch_EPHY_LL                              (1 << 5)
+#define INCA_IP_Switch_EPHY_LP                              (1 << 4)
+#define INCA_IP_Switch_EPHY_DL                              (1 << 3)
+#define INCA_IP_Switch_EPHY_DP                              (1 << 2)
+#define INCA_IP_Switch_EPHY_PL                              (1 << 1)
+#define INCA_IP_Switch_EPHY_PP                              (1 << 0)
+
+/***Pause Write Enable Register***/
+#define INCA_IP_Switch_PWR_EN                       ((volatile u32*)(INCA_IP_Switch+ 0x0488))
+#define INCA_IP_Switch_PWR_EN_PL                              (1 << 1)
+#define INCA_IP_Switch_PWR_EN_PP                              (1 << 0)
+
+/***MDIO Configuration Register***/
+#define INCA_IP_Switch_MDIO_CFG                    ((volatile u32*)(INCA_IP_Switch+ 0x048C))
+#define INCA_IP_Switch_MDIO_CFG_MDS (value)                (((( 1 << 2) - 1) & (value)) << 14)
+#define INCA_IP_Switch_MDIO_CFG_PHY_LAN_ADDR (value)       (((( 1 << 5) - 1) & (value)) << 9)
+#define INCA_IP_Switch_MDIO_CFG_PHY_PC_ADDR (value)        (((( 1 << 5) - 1) & (value)) << 4)
+#define INCA_IP_Switch_MDIO_CFG_UEP                              (1 << 3)
+#define INCA_IP_Switch_MDIO_CFG_PS                              (1 << 2)
+#define INCA_IP_Switch_MDIO_CFG_PT                              (1 << 1)
+#define INCA_IP_Switch_MDIO_CFG_UMM                              (1 << 0)
+
+/***Clock Configuration Register***/
+#define INCA_IP_Switch_CLK_CFG                      ((volatile u32*)(INCA_IP_Switch+ 0x0500))
+#define INCA_IP_Switch_CLK_CFG_ARL_ID                        (1 << 9)
+#define INCA_IP_Switch_CLK_CFG_CPU_ID                        (1 << 8)
+#define INCA_IP_Switch_CLK_CFG_LAN_ID                        (1 << 7)
+#define INCA_IP_Switch_CLK_CFG_PC_ID                          (1 << 6)
+#define INCA_IP_Switch_CLK_CFG_SE_ID                          (1 << 5)
+
+/***********************************************************************/
+/*  Module      :  SSC1 register address and bits                      */
+/***********************************************************************/
+
+#define INCA_IP_SSC1                         (0xB8000500)
+/***********************************************************************/
+
+
+/***Control Register (Programming Mode)***/
+#define INCA_IP_SSC1_SCC_CON_PRG                  ((volatile u32*)(INCA_IP_SSC1+ 0x0010))
+#define INCA_IP_SSC1_SCC_CON_PRG_EN                              (1 << 15)
+#define INCA_IP_SSC1_SCC_CON_PRG_MS                              (1 << 14)
+#define INCA_IP_SSC1_SCC_CON_PRG_AREN                            (1 << 12)
+#define INCA_IP_SSC1_SCC_CON_PRG_BEN                              (1 << 11)
+#define INCA_IP_SSC1_SCC_CON_PRG_PEN                              (1 << 10)
+#define INCA_IP_SSC1_SCC_CON_PRG_REN                              (1 << 9)
+#define INCA_IP_SSC1_SCC_CON_PRG_TEN                              (1 << 8)
+#define INCA_IP_SSC1_SCC_CON_PRG_LB                              (1 << 7)
+#define INCA_IP_SSC1_SCC_CON_PRG_PO                              (1 << 6)
+#define INCA_IP_SSC1_SCC_CON_PRG_PH                              (1 << 5)
+#define INCA_IP_SSC1_SCC_CON_PRG_HB                              (1 << 4)
+#define INCA_IP_SSC1_SCC_CON_PRG_BM (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***SCC Control Register (Operating Mode)***/
+#define INCA_IP_SSC1_SCC_CON_OPR                  ((volatile u32*)(INCA_IP_SSC1+ 0x0010))
+#define INCA_IP_SSC1_SCC_CON_OPR_EN                              (1 << 15)
+#define INCA_IP_SSC1_SCC_CON_OPR_MS                              (1 << 14)
+#define INCA_IP_SSC1_SCC_CON_OPR_BSY                              (1 << 12)
+#define INCA_IP_SSC1_SCC_CON_OPR_BE                              (1 << 11)
+#define INCA_IP_SSC1_SCC_CON_OPR_PE                              (1 << 10)
+#define INCA_IP_SSC1_SCC_CON_OPR_RE                              (1 << 9)
+#define INCA_IP_SSC1_SCC_CON_OPR_TE                              (1 << 8)
+#define INCA_IP_SSC1_SCC_CON_OPR_BC (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***SSC Write Hardware Modified Control Register***/
+#define INCA_IP_SSC1_SSC_WHBCON                   ((volatile u32*)(INCA_IP_SSC1+ 0x0040))
+#define INCA_IP_SSC1_SSC_WHBCON_SETBE                          (1 << 15)
+#define INCA_IP_SSC1_SSC_WHBCON_SETPE                          (1 << 14)
+#define INCA_IP_SSC1_SSC_WHBCON_SETRE                          (1 << 13)
+#define INCA_IP_SSC1_SSC_WHBCON_SETTE                          (1 << 12)
+#define INCA_IP_SSC1_SSC_WHBCON_CLRBE                          (1 << 11)
+#define INCA_IP_SSC1_SSC_WHBCON_CLRPE                          (1 << 10)
+#define INCA_IP_SSC1_SSC_WHBCON_CLRRE                          (1 << 9)
+#define INCA_IP_SSC1_SSC_WHBCON_CLRTE                          (1 << 8)
+
+/***SSC Baudrate Timer Reload Register***/
+#define INCA_IP_SSC1_SSC_BR                       ((volatile u32*)(INCA_IP_SSC1+ 0x0014))
+#define INCA_IP_SSC1_SSC_BR_BR_VALUE (value)          (((( 1 << 16) - 1) & (value)) << 0)
+
+/***SSC Transmitter Buffer Register***/
+#define INCA_IP_SSC1_SSC_TB                       ((volatile u32*)(INCA_IP_SSC1+ 0x0020))
+#define INCA_IP_SSC1_SSC_TB_TB_VALUE (value)          (((( 1 << 16) - 1) & (value)) << 0)
+
+/***SSC Receiver Buffer Register***/
+#define INCA_IP_SSC1_SSC_RB                       ((volatile u32*)(INCA_IP_SSC1+ 0x0024))
+#define INCA_IP_SSC1_SSC_RB_RB_VALUE (value)          (((( 1 << 16) - 1) & (value)) << 0)
+
+/***SSC Receive FIFO Control Register***/
+#define INCA_IP_SSC1_SSC_RXFCON                   ((volatile u32*)(INCA_IP_SSC1+ 0x0030))
+#define INCA_IP_SSC1_SSC_RXFCON_RXFITL (value)             (((( 1 << 6) - 1) & (value)) << 8)
+#define INCA_IP_SSC1_SSC_RXFCON_RXTMEN                        (1 << 2)
+#define INCA_IP_SSC1_SSC_RXFCON_RXFLU                          (1 << 1)
+#define INCA_IP_SSC1_SSC_RXFCON_RXFEN                          (1 << 0)
+
+/***SSC Transmit FIFO Control Register***/
+#define INCA_IP_SSC1_SSC_TXFCON                   ((volatile u32*)(INCA_IP_SSC1+ 0x0034))
+#define INCA_IP_SSC1_SSC_TXFCON_RXFITL (value)             (((( 1 << 6) - 1) & (value)) << 8)
+#define INCA_IP_SSC1_SSC_TXFCON_TXTMEN                        (1 << 2)
+#define INCA_IP_SSC1_SSC_TXFCON_TXFLU                          (1 << 1)
+#define INCA_IP_SSC1_SSC_TXFCON_TXFEN                          (1 << 0)
+
+/***SSC FIFO Status Register***/
+#define INCA_IP_SSC1_SSC_FSTAT                    ((volatile u32*)(INCA_IP_SSC1+ 0x0038))
+#define INCA_IP_SSC1_SSC_FSTAT_TXFFL (value)              (((( 1 << 6) - 1) & (value)) << 8)
+#define INCA_IP_SSC1_SSC_FSTAT_RXFFL (value)              (((( 1 << 6) - 1) & (value)) << 0)
+
+/***SSC Clock Control Register***/
+#define INCA_IP_SSC1_SSC_CLC                      ((volatile u32*)(INCA_IP_SSC1+ 0x0000))
+#define INCA_IP_SSC1_SSC_CLC_RMC (value)                (((( 1 << 8) - 1) & (value)) << 8)
+#define INCA_IP_SSC1_SSC_CLC_DISS                            (1 << 1)
+#define INCA_IP_SSC1_SSC_CLC_DISR                            (1 << 0)
+
+/***********************************************************************/
+/*  Module      :  SSC2 register address and bits                      */
+/***********************************************************************/
+
+#define INCA_IP_SSC2                         (0xB8000600)
+/***********************************************************************/
+
+
+/***Control Register (Programming Mode)***/
+#define INCA_IP_SSC2_SCC_CON_PRG                  ((volatile u32*)(INCA_IP_SSC2+ 0x0010))
+#define INCA_IP_SSC2_SCC_CON_PRG_EN                              (1 << 15)
+#define INCA_IP_SSC2_SCC_CON_PRG_MS                              (1 << 14)
+#define INCA_IP_SSC2_SCC_CON_PRG_AREN                            (1 << 12)
+#define INCA_IP_SSC2_SCC_CON_PRG_BEN                              (1 << 11)
+#define INCA_IP_SSC2_SCC_CON_PRG_PEN                              (1 << 10)
+#define INCA_IP_SSC2_SCC_CON_PRG_REN                              (1 << 9)
+#define INCA_IP_SSC2_SCC_CON_PRG_TEN                              (1 << 8)
+#define INCA_IP_SSC2_SCC_CON_PRG_LB                              (1 << 7)
+#define INCA_IP_SSC2_SCC_CON_PRG_PO                              (1 << 6)
+#define INCA_IP_SSC2_SCC_CON_PRG_PH                              (1 << 5)
+#define INCA_IP_SSC2_SCC_CON_PRG_HB                              (1 << 4)
+#define INCA_IP_SSC2_SCC_CON_PRG_BM (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***SCC Control Register (Operating Mode)***/
+#define INCA_IP_SSC2_SCC_CON_OPR                  ((volatile u32*)(INCA_IP_SSC2+ 0x0010))
+#define INCA_IP_SSC2_SCC_CON_OPR_EN                              (1 << 15)
+#define INCA_IP_SSC2_SCC_CON_OPR_MS                              (1 << 14)
+#define INCA_IP_SSC2_SCC_CON_OPR_BSY                              (1 << 12)
+#define INCA_IP_SSC2_SCC_CON_OPR_BE                              (1 << 11)
+#define INCA_IP_SSC2_SCC_CON_OPR_PE                              (1 << 10)
+#define INCA_IP_SSC2_SCC_CON_OPR_RE                              (1 << 9)
+#define INCA_IP_SSC2_SCC_CON_OPR_TE                              (1 << 8)
+#define INCA_IP_SSC2_SCC_CON_OPR_BC (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***SSC Write Hardware Modified Control Register***/
+#define INCA_IP_SSC2_SSC_WHBCON                   ((volatile u32*)(INCA_IP_SSC2+ 0x0040))
+#define INCA_IP_SSC2_SSC_WHBCON_SETBE                          (1 << 15)
+#define INCA_IP_SSC2_SSC_WHBCON_SETPE                          (1 << 14)
+#define INCA_IP_SSC2_SSC_WHBCON_SETRE                          (1 << 13)
+#define INCA_IP_SSC2_SSC_WHBCON_SETTE                          (1 << 12)
+#define INCA_IP_SSC2_SSC_WHBCON_CLRBE                          (1 << 11)
+#define INCA_IP_SSC2_SSC_WHBCON_CLRPE                          (1 << 10)
+#define INCA_IP_SSC2_SSC_WHBCON_CLRRE                          (1 << 9)
+#define INCA_IP_SSC2_SSC_WHBCON_CLRTE                          (1 << 8)
+
+/***SSC Baudrate Timer Reload Register***/
+#define INCA_IP_SSC2_SSC_BR                       ((volatile u32*)(INCA_IP_SSC2+ 0x0014))
+#define INCA_IP_SSC2_SSC_BR_BR_VALUE (value)          (((( 1 << 16) - 1) & (value)) << 0)
+
+/***SSC Transmitter Buffer Register***/
+#define INCA_IP_SSC2_SSC_TB                       ((volatile u32*)(INCA_IP_SSC2+ 0x0020))
+#define INCA_IP_SSC2_SSC_TB_TB_VALUE (value)          (((( 1 << 16) - 1) & (value)) << 0)
+
+/***SSC Receiver Buffer Register***/
+#define INCA_IP_SSC2_SSC_RB                       ((volatile u32*)(INCA_IP_SSC2+ 0x0024))
+#define INCA_IP_SSC2_SSC_RB_RB_VALUE (value)          (((( 1 << 16) - 1) & (value)) << 0)
+
+/***SSC Receive FIFO Control Register***/
+#define INCA_IP_SSC2_SSC_RXFCON                   ((volatile u32*)(INCA_IP_SSC2+ 0x0030))
+#define INCA_IP_SSC2_SSC_RXFCON_RXFITL (value)             (((( 1 << 6) - 1) & (value)) << 8)
+#define INCA_IP_SSC2_SSC_RXFCON_RXTMEN                        (1 << 2)
+#define INCA_IP_SSC2_SSC_RXFCON_RXFLU                          (1 << 1)
+#define INCA_IP_SSC2_SSC_RXFCON_RXFEN                          (1 << 0)
+
+/***SSC Transmit FIFO Control Register***/
+#define INCA_IP_SSC2_SSC_TXFCON                   ((volatile u32*)(INCA_IP_SSC2+ 0x0034))
+#define INCA_IP_SSC2_SSC_TXFCON_RXFITL (value)             (((( 1 << 6) - 1) & (value)) << 8)
+#define INCA_IP_SSC2_SSC_TXFCON_TXTMEN                        (1 << 2)
+#define INCA_IP_SSC2_SSC_TXFCON_TXFLU                          (1 << 1)
+#define INCA_IP_SSC2_SSC_TXFCON_TXFEN                          (1 << 0)
+
+/***SSC FIFO Status Register***/
+#define INCA_IP_SSC2_SSC_FSTAT                    ((volatile u32*)(INCA_IP_SSC2+ 0x0038))
+#define INCA_IP_SSC2_SSC_FSTAT_TXFFL (value)              (((( 1 << 6) - 1) & (value)) << 8)
+#define INCA_IP_SSC2_SSC_FSTAT_RXFFL (value)              (((( 1 << 6) - 1) & (value)) << 0)
+
+/***SSC Clock Control Register***/
+#define INCA_IP_SSC2_SSC_CLC                      ((volatile u32*)(INCA_IP_SSC2+ 0x0000))
+#define INCA_IP_SSC2_SSC_CLC_RMC (value)                (((( 1 << 8) - 1) & (value)) << 8)
+#define INCA_IP_SSC2_SSC_CLC_DISS                            (1 << 1)
+#define INCA_IP_SSC2_SSC_CLC_DISR                            (1 << 0)
+
+/***********************************************************************/
+/*  Module      :  EBU register address and bits                       */
+/***********************************************************************/
+
+#if defined(CONFIG_INCA_IP)
+#define INCA_IP_EBU                          (0xB8000200)
+#elif defined(CONFIG_PURPLE)
+#define INCA_IP_EBU                          (0xB800D800)
+#endif
+
+/***********************************************************************/
+
+
+/***EBU Clock Control Register***/
+#define INCA_IP_EBU_EBU_CLC                      ((volatile u32*)(INCA_IP_EBU+ 0x0000))
+#define INCA_IP_EBU_EBU_CLC_DISS                            (1 << 1)
+#define INCA_IP_EBU_EBU_CLC_DISR                            (1 << 0)
+
+/***EBU Global Control Register***/
+#define INCA_IP_EBU_EBU_CON                      ((volatile u32*)(INCA_IP_EBU+ 0x0010))
+#define INCA_IP_EBU_EBU_CON_DTACS (value)              (((( 1 << 3) - 1) & (value)) << 20)
+#define INCA_IP_EBU_EBU_CON_DTARW (value)              (((( 1 << 3) - 1) & (value)) << 16)
+#define INCA_IP_EBU_EBU_CON_TOUTC (value)              (((( 1 << 8) - 1) & (value)) << 8)
+#define INCA_IP_EBU_EBU_CON_ARBMODE (value)            (((( 1 << 2) - 1) & (value)) << 6)
+#define INCA_IP_EBU_EBU_CON_ARBSYNC                      (1 << 5)
+#define INCA_IP_EBU_EBU_CON_1                              (1 << 3)
+
+/***EBU Address Select Register 0***/
+#define INCA_IP_EBU_EBU_ADDSEL0                  ((volatile u32*)(INCA_IP_EBU+ 0x0020))
+#define INCA_IP_EBU_EBU_ADDSEL0_BASE (value)               (((( 1 << 20) - 1) & (value)) << 12)
+#define INCA_IP_EBU_EBU_ADDSEL0_MASK (value)               (((( 1 << 4) - 1) & (value)) << 4)
+#define INCA_IP_EBU_EBU_ADDSEL0_MIRRORE                      (1 << 1)
+#define INCA_IP_EBU_EBU_ADDSEL0_REGEN                          (1 << 0)
+
+/***EBU Address Select Register 1***/
+#define INCA_IP_EBU_EBU_ADDSEL1                  ((volatile u32*)(INCA_IP_EBU+ 0x0024))
+#define INCA_IP_EBU_EBU_ADDSEL1_BASE (value)               (((( 1 << 20) - 1) & (value)) << 12)
+#define INCA_IP_EBU_EBU_ADDSEL1_MASK (value)               (((( 1 << 4) - 1) & (value)) << 4)
+#define INCA_IP_EBU_EBU_ADDSEL1_MIRRORE                      (1 << 1)
+#define INCA_IP_EBU_EBU_ADDSEL1_REGEN                          (1 << 0)
+
+/***EBU Address Select Register 2***/
+#define INCA_IP_EBU_EBU_ADDSEL2                  ((volatile u32*)(INCA_IP_EBU+ 0x0028))
+#define INCA_IP_EBU_EBU_ADDSEL2_BASE (value)               (((( 1 << 20) - 1) & (value)) << 12)
+#define INCA_IP_EBU_EBU_ADDSEL2_MASK (value)               (((( 1 << 4) - 1) & (value)) << 4)
+#define INCA_IP_EBU_EBU_ADDSEL2_MIRRORE                      (1 << 1)
+#define INCA_IP_EBU_EBU_ADDSEL2_REGEN                          (1 << 0)
+
+/***EBU Bus Configuration Register 0***/
+#define INCA_IP_EBU_EBU_BUSCON0                  ((volatile u32*)(INCA_IP_EBU+ 0x0060))
+#define INCA_IP_EBU_EBU_BUSCON0_WRDIS                          (1 << 31)
+#define INCA_IP_EBU_EBU_BUSCON0_ALEC (value)               (((( 1 << 2) - 1) & (value)) << 29)
+#define INCA_IP_EBU_EBU_BUSCON0_BCGEN (value)              (((( 1 << 2) - 1) & (value)) << 27)
+#define INCA_IP_EBU_EBU_BUSCON0_AGEN (value)               (((( 1 << 2) - 1) & (value)) << 24)
+#define INCA_IP_EBU_EBU_BUSCON0_CMULTR (value)             (((( 1 << 2) - 1) & (value)) << 22)
+#define INCA_IP_EBU_EBU_BUSCON0_WAIT (value)               (((( 1 << 2) - 1) & (value)) << 20)
+#define INCA_IP_EBU_EBU_BUSCON0_WAITINV                      (1 << 19)
+#define INCA_IP_EBU_EBU_BUSCON0_SETUP                          (1 << 18)
+#define INCA_IP_EBU_EBU_BUSCON0_PORTW (value)              (((( 1 << 2) - 1) & (value)) << 16)
+#define INCA_IP_EBU_EBU_BUSCON0_WAITRDC (value)            (((( 1 << 7) - 1) & (value)) << 9)
+#define INCA_IP_EBU_EBU_BUSCON0_WAITWRC (value)            (((( 1 << 3) - 1) & (value)) << 6)
+#define INCA_IP_EBU_EBU_BUSCON0_HOLDC (value)              (((( 1 << 2) - 1) & (value)) << 4)
+#define INCA_IP_EBU_EBU_BUSCON0_RECOVC (value)             (((( 1 << 2) - 1) & (value)) << 2)
+#define INCA_IP_EBU_EBU_BUSCON0_CMULT (value)              (((( 1 << 2) - 1) & (value)) << 0)
+
+/***EBU Bus Configuration Register 1***/
+#define INCA_IP_EBU_EBU_BUSCON1                  ((volatile u32*)(INCA_IP_EBU+ 0x0064))
+#define INCA_IP_EBU_EBU_BUSCON1_WRDIS                          (1 << 31)
+#define INCA_IP_EBU_EBU_BUSCON1_ALEC (value)               (((( 1 << 2) - 1) & (value)) << 29)
+#define INCA_IP_EBU_EBU_BUSCON1_BCGEN (value)              (((( 1 << 2) - 1) & (value)) << 27)
+#define INCA_IP_EBU_EBU_BUSCON1_AGEN (value)               (((( 1 << 2) - 1) & (value)) << 24)
+#define INCA_IP_EBU_EBU_BUSCON1_CMULTR (value)             (((( 1 << 2) - 1) & (value)) << 22)
+#define INCA_IP_EBU_EBU_BUSCON1_WAIT (value)               (((( 1 << 2) - 1) & (value)) << 20)
+#define INCA_IP_EBU_EBU_BUSCON1_WAITINV                      (1 << 19)
+#define INCA_IP_EBU_EBU_BUSCON1_SETUP                          (1 << 18)
+#define INCA_IP_EBU_EBU_BUSCON1_PORTW (value)              (((( 1 << 2) - 1) & (value)) << 16)
+#define INCA_IP_EBU_EBU_BUSCON1_WAITRDC (value)            (((( 1 << 7) - 1) & (value)) << 9)
+#define INCA_IP_EBU_EBU_BUSCON1_WAITWRC (value)            (((( 1 << 3) - 1) & (value)) << 6)
+#define INCA_IP_EBU_EBU_BUSCON1_HOLDC (value)              (((( 1 << 2) - 1) & (value)) << 4)
+#define INCA_IP_EBU_EBU_BUSCON1_RECOVC (value)             (((( 1 << 2) - 1) & (value)) << 2)
+#define INCA_IP_EBU_EBU_BUSCON1_CMULT (value)              (((( 1 << 2) - 1) & (value)) << 0)
+
+/***EBU Bus Configuration Register 2***/
+#define INCA_IP_EBU_EBU_BUSCON2                  ((volatile u32*)(INCA_IP_EBU+ 0x0068))
+#define INCA_IP_EBU_EBU_BUSCON2_WRDIS                          (1 << 31)
+#define INCA_IP_EBU_EBU_BUSCON2_ALEC (value)               (((( 1 << 2) - 1) & (value)) << 29)
+#define INCA_IP_EBU_EBU_BUSCON2_BCGEN (value)              (((( 1 << 2) - 1) & (value)) << 27)
+#define INCA_IP_EBU_EBU_BUSCON2_AGEN (value)               (((( 1 << 2) - 1) & (value)) << 24)
+#define INCA_IP_EBU_EBU_BUSCON2_CMULTR (value)             (((( 1 << 2) - 1) & (value)) << 22)
+#define INCA_IP_EBU_EBU_BUSCON2_WAIT (value)               (((( 1 << 2) - 1) & (value)) << 20)
+#define INCA_IP_EBU_EBU_BUSCON2_WAITINV                      (1 << 19)
+#define INCA_IP_EBU_EBU_BUSCON2_SETUP                          (1 << 18)
+#define INCA_IP_EBU_EBU_BUSCON2_PORTW (value)              (((( 1 << 2) - 1) & (value)) << 16)
+#define INCA_IP_EBU_EBU_BUSCON2_WAITRDC (value)            (((( 1 << 7) - 1) & (value)) << 9)
+#define INCA_IP_EBU_EBU_BUSCON2_WAITWRC (value)            (((( 1 << 3) - 1) & (value)) << 6)
+#define INCA_IP_EBU_EBU_BUSCON2_HOLDC (value)              (((( 1 << 2) - 1) & (value)) << 4)
+#define INCA_IP_EBU_EBU_BUSCON2_RECOVC (value)             (((( 1 << 2) - 1) & (value)) << 2)
+#define INCA_IP_EBU_EBU_BUSCON2_CMULT (value)              (((( 1 << 2) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/*  Module      :  SDRAM register address and bits                     */
+/***********************************************************************/
+
+#define INCA_IP_SDRAM                        (0xBF800000)
+/***********************************************************************/
+
+
+/***MC Access Error Cause Register***/
+#define INCA_IP_SDRAM_MC_ERRCAUSE                  ((volatile u32*)(INCA_IP_SDRAM+ 0x0100))
+#define INCA_IP_SDRAM_MC_ERRCAUSE_ERR                              (1 << 31)
+#define INCA_IP_SDRAM_MC_ERRCAUSE_PORT (value)               (((( 1 << 4) - 1) & (value)) << 16)
+#define INCA_IP_SDRAM_MC_ERRCAUSE_CAUSE (value)              (((( 1 << 2) - 1) & (value)) << 0)
+#define INCA_IP_SDRAM_MC_ERRCAUSE_Res (value)                (((( 1 << NaN) - 1) & (value)) << NaN)
+
+/***MC Access Error Address Register***/
+#define INCA_IP_SDRAM_MC_ERRADDR                   ((volatile u32*)(INCA_IP_SDRAM+ 0x0108))
+#define INCA_IP_SDRAM_MC_ERRADDR_ADDR
+
+/***MC I/O General Purpose Register***/
+#define INCA_IP_SDRAM_MC_IOGP                      ((volatile u32*)(INCA_IP_SDRAM+ 0x0800))
+#define INCA_IP_SDRAM_MC_IOGP_GPR6 (value)               (((( 1 << 4) - 1) & (value)) << 28)
+#define INCA_IP_SDRAM_MC_IOGP_GPR5 (value)               (((( 1 << 4) - 1) & (value)) << 24)
+#define INCA_IP_SDRAM_MC_IOGP_GPR4 (value)               (((( 1 << 4) - 1) & (value)) << 20)
+#define INCA_IP_SDRAM_MC_IOGP_GPR3 (value)               (((( 1 << 4) - 1) & (value)) << 16)
+#define INCA_IP_SDRAM_MC_IOGP_GPR2 (value)               (((( 1 << 4) - 1) & (value)) << 12)
+#define INCA_IP_SDRAM_MC_IOGP_CPS                              (1 << 11)
+#define INCA_IP_SDRAM_MC_IOGP_CLKDELAY (value)          (((( 1 << 3) - 1) & (value)) << 8)
+#define INCA_IP_SDRAM_MC_IOGP_CLKRAT (value)             (((( 1 << 4) - 1) & (value)) << 4)
+#define INCA_IP_SDRAM_MC_IOGP_RDDEL (value)              (((( 1 << 4) - 1) & (value)) << 0)
+
+/***MC Self Refresh Register***/
+#define INCA_IP_SDRAM_MC_SELFRFSH                  ((volatile u32*)(INCA_IP_SDRAM+ 0x0A00))
+#define INCA_IP_SDRAM_MC_SELFRFSH_PWDS                            (1 << 1)
+#define INCA_IP_SDRAM_MC_SELFRFSH_PWD                              (1 << 0)
+#define INCA_IP_SDRAM_MC_SELFRFSH_Res (value)                (((( 1 << 30) - 1) & (value)) << 2)
+
+/***MC Enable Register***/
+#define INCA_IP_SDRAM_MC_CTRLENA                   ((volatile u32*)(INCA_IP_SDRAM+ 0x1000))
+#define INCA_IP_SDRAM_MC_CTRLENA_ENA                              (1 << 0)
+#define INCA_IP_SDRAM_MC_CTRLENA_Res (value)                (((( 1 << 31) - 1) & (value)) << 1)
+
+/***MC Mode Register Setup Code***/
+#define INCA_IP_SDRAM_MC_MRSCODE                   ((volatile u32*)(INCA_IP_SDRAM+ 0x1008))
+#define INCA_IP_SDRAM_MC_MRSCODE_UMC (value)                (((( 1 << 5) - 1) & (value)) << 7)
+#define INCA_IP_SDRAM_MC_MRSCODE_CL (value)                (((( 1 << 3) - 1) & (value)) << 4)
+#define INCA_IP_SDRAM_MC_MRSCODE_WT                              (1 << 3)
+#define INCA_IP_SDRAM_MC_MRSCODE_BL (value)                (((( 1 << 3) - 1) & (value)) << 0)
+
+/***MC Configuration Data-word Width Register***/
+#define INCA_IP_SDRAM_MC_CFGDW                    ((volatile u32*)(INCA_IP_SDRAM+ 0x1010))
+#define INCA_IP_SDRAM_MC_CFGDW_DW (value)                (((( 1 << 4) - 1) & (value)) << 0)
+#define INCA_IP_SDRAM_MC_CFGDW_Res (value)                (((( 1 << 28) - 1) & (value)) << 4)
+
+/***MC Configuration Physical Bank 0 Register***/
+#define INCA_IP_SDRAM_MC_CFGPB0                    ((volatile u32*)(INCA_IP_SDRAM+ 0x1018))
+#define INCA_IP_SDRAM_MC_CFGPB0_MCSEN0 (value)             (((( 1 << 4) - 1) & (value)) << 12)
+#define INCA_IP_SDRAM_MC_CFGPB0_BANKN0 (value)             (((( 1 << 4) - 1) & (value)) << 8)
+#define INCA_IP_SDRAM_MC_CFGPB0_ROWW0 (value)              (((( 1 << 4) - 1) & (value)) << 4)
+#define INCA_IP_SDRAM_MC_CFGPB0_COLW0 (value)              (((( 1 << 4) - 1) & (value)) << 0)
+#define INCA_IP_SDRAM_MC_CFGPB0_Res (value)                (((( 1 << 16) - 1) & (value)) << 16)
+
+/***MC Latency Register***/
+#define INCA_IP_SDRAM_MC_LATENCY                   ((volatile u32*)(INCA_IP_SDRAM+ 0x1038))
+#define INCA_IP_SDRAM_MC_LATENCY_TRP (value)                (((( 1 << 4) - 1) & (value)) << 16)
+#define INCA_IP_SDRAM_MC_LATENCY_TRAS (value)               (((( 1 << 4) - 1) & (value)) << 12)
+#define INCA_IP_SDRAM_MC_LATENCY_TRCD (value)               (((( 1 << 4) - 1) & (value)) << 8)
+#define INCA_IP_SDRAM_MC_LATENCY_TDPL (value)               (((( 1 << 4) - 1) & (value)) << 4)
+#define INCA_IP_SDRAM_MC_LATENCY_TDAL (value)               (((( 1 << 4) - 1) & (value)) << 0)
+#define INCA_IP_SDRAM_MC_LATENCY_Res (value)                (((( 1 << 12) - 1) & (value)) << 20)
+
+/***MC Refresh Cycle Time Register***/
+#define INCA_IP_SDRAM_MC_TREFRESH                  ((volatile u32*)(INCA_IP_SDRAM+ 0x1040))
+#define INCA_IP_SDRAM_MC_TREFRESH_TREF (value)               (((( 1 << 13) - 1) & (value)) << 0)
+#define INCA_IP_SDRAM_MC_TREFRESH_Res (value)                (((( 1 << 19) - 1) & (value)) << 13)
+
+/***********************************************************************/
+/*  Module      :  GPTU register address and bits                      */
+/***********************************************************************/
+
+#define INCA_IP_GPTU                         (0xB8000300)
+/***********************************************************************/
+
+
+/***GPT Clock Control Register***/
+#define INCA_IP_GPTU_GPT_CLC                      ((volatile u32*)(INCA_IP_GPTU+ 0x0000))
+#define INCA_IP_GPTU_GPT_CLC_RMC (value)                (((( 1 << 8) - 1) & (value)) << 8)
+#define INCA_IP_GPTU_GPT_CLC_DISS                            (1 << 1)
+#define INCA_IP_GPTU_GPT_CLC_DISR                            (1 << 0)
+
+/***GPT Timer 3 Control Register***/
+#define INCA_IP_GPTU_GPT_T3CON                    ((volatile u32*)(INCA_IP_GPTU+ 0x0014))
+#define INCA_IP_GPTU_GPT_T3CON_T3RDIR                        (1 << 15)
+#define INCA_IP_GPTU_GPT_T3CON_T3CHDIR                      (1 << 14)
+#define INCA_IP_GPTU_GPT_T3CON_T3EDGE                        (1 << 13)
+#define INCA_IP_GPTU_GPT_T3CON_BPS1 (value)               (((( 1 << 2) - 1) & (value)) << 11)
+#define INCA_IP_GPTU_GPT_T3CON_T3OTL                          (1 << 10)
+#define INCA_IP_GPTU_GPT_T3CON_T3UD                            (1 << 7)
+#define INCA_IP_GPTU_GPT_T3CON_T3R                              (1 << 6)
+#define INCA_IP_GPTU_GPT_T3CON_T3M (value)                (((( 1 << 3) - 1) & (value)) << 3)
+#define INCA_IP_GPTU_GPT_T3CON_T3I (value)                (((( 1 << 3) - 1) & (value)) << 0)
+
+/***GPT Write Hardware Modified Timer 3 Control Register
+If set and clear bit are written concurrently with 1, the associated bit is not changed.***/
+#define INCA_IP_GPTU_GPT_WHBT3CON                 ((volatile u32*)(INCA_IP_GPTU+ 0x004C))
+#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3CHDIR                (1 << 15)
+#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3CHDIR                (1 << 14)
+#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3EDGE                  (1 << 13)
+#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3EDGE                  (1 << 12)
+#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3OTL                  (1 << 11)
+#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3OTL                  (1 << 10)
+
+/***GPT Timer 2 Control Register***/
+#define INCA_IP_GPTU_GPT_T2CON                    ((volatile u32*)(INCA_IP_GPTU+ 0x0010))
+#define INCA_IP_GPTU_GPT_T2CON_TxRDIR                        (1 << 15)
+#define INCA_IP_GPTU_GPT_T2CON_TxCHDIR                      (1 << 14)
+#define INCA_IP_GPTU_GPT_T2CON_TxEDGE                        (1 << 13)
+#define INCA_IP_GPTU_GPT_T2CON_TxIRDIS                      (1 << 12)
+#define INCA_IP_GPTU_GPT_T2CON_TxRC                            (1 << 9)
+#define INCA_IP_GPTU_GPT_T2CON_TxUD                            (1 << 7)
+#define INCA_IP_GPTU_GPT_T2CON_TxR                              (1 << 6)
+#define INCA_IP_GPTU_GPT_T2CON_TxM (value)                (((( 1 << 3) - 1) & (value)) << 3)
+#define INCA_IP_GPTU_GPT_T2CON_TxI (value)                (((( 1 << 3) - 1) & (value)) << 0)
+
+/***GPT Timer 4 Control Register***/
+#define INCA_IP_GPTU_GPT_T4CON                    ((volatile u32*)(INCA_IP_GPTU+ 0x0018))
+#define INCA_IP_GPTU_GPT_T4CON_TxRDIR                        (1 << 15)
+#define INCA_IP_GPTU_GPT_T4CON_TxCHDIR                      (1 << 14)
+#define INCA_IP_GPTU_GPT_T4CON_TxEDGE                        (1 << 13)
+#define INCA_IP_GPTU_GPT_T4CON_TxIRDIS                      (1 << 12)
+#define INCA_IP_GPTU_GPT_T4CON_TxRC                            (1 << 9)
+#define INCA_IP_GPTU_GPT_T4CON_TxUD                            (1 << 7)
+#define INCA_IP_GPTU_GPT_T4CON_TxR                              (1 << 6)
+#define INCA_IP_GPTU_GPT_T4CON_TxM (value)                (((( 1 << 3) - 1) & (value)) << 3)
+#define INCA_IP_GPTU_GPT_T4CON_TxI (value)                (((( 1 << 3) - 1) & (value)) << 0)
+
+/***GPT Write HW Modified Timer 2 Control Register If set
+ and clear bit are written concurrently with 1, the associated bit is not changed.***/
+#define INCA_IP_GPTU_GPT_WHBT2CON                 ((volatile u32*)(INCA_IP_GPTU+ 0x0048))
+#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxCHDIR                (1 << 15)
+#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxCHDIR                (1 << 14)
+#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxEDGE                  (1 << 13)
+#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxEDGE                  (1 << 12)
+
+/***GPT Write HW Modified Timer 4 Control Register If set
+ and clear bit are written concurrently with 1, the associated bit is not changed.***/
+#define INCA_IP_GPTU_GPT_WHBT4CON                 ((volatile u32*)(INCA_IP_GPTU+ 0x0050))
+#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxCHDIR                (1 << 15)
+#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxCHDIR                (1 << 14)
+#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxEDGE                  (1 << 13)
+#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxEDGE                  (1 << 12)
+
+/***GPT Capture Reload Register***/
+#define INCA_IP_GPTU_GPT_CAPREL                   ((volatile u32*)(INCA_IP_GPTU+ 0x0030))
+#define INCA_IP_GPTU_GPT_CAPREL_CAPREL (value)             (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 2 Register***/
+#define INCA_IP_GPTU_GPT_T2                       ((volatile u32*)(INCA_IP_GPTU+ 0x0034))
+#define INCA_IP_GPTU_GPT_T2_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 3 Register***/
+#define INCA_IP_GPTU_GPT_T3                       ((volatile u32*)(INCA_IP_GPTU+ 0x0038))
+#define INCA_IP_GPTU_GPT_T3_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 4 Register***/
+#define INCA_IP_GPTU_GPT_T4                       ((volatile u32*)(INCA_IP_GPTU+ 0x003C))
+#define INCA_IP_GPTU_GPT_T4_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 5 Register***/
+#define INCA_IP_GPTU_GPT_T5                       ((volatile u32*)(INCA_IP_GPTU+ 0x0040))
+#define INCA_IP_GPTU_GPT_T5_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 6 Register***/
+#define INCA_IP_GPTU_GPT_T6                       ((volatile u32*)(INCA_IP_GPTU+ 0x0044))
+#define INCA_IP_GPTU_GPT_T6_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
+
+/***GPT Timer 6 Control Register***/
+#define INCA_IP_GPTU_GPT_T6CON                    ((volatile u32*)(INCA_IP_GPTU+ 0x0020))
+#define INCA_IP_GPTU_GPT_T6CON_T6SR                            (1 << 15)
+#define INCA_IP_GPTU_GPT_T6CON_T6CLR                          (1 << 14)
+#define INCA_IP_GPTU_GPT_T6CON_BPS2 (value)               (((( 1 << 2) - 1) & (value)) << 11)
+#define INCA_IP_GPTU_GPT_T6CON_T6OTL                          (1 << 10)
+#define INCA_IP_GPTU_GPT_T6CON_T6UD                            (1 << 7)
+#define INCA_IP_GPTU_GPT_T6CON_T6R                              (1 << 6)
+#define INCA_IP_GPTU_GPT_T6CON_T6M (value)                (((( 1 << 3) - 1) & (value)) << 3)
+#define INCA_IP_GPTU_GPT_T6CON_T6I (value)                (((( 1 << 3) - 1) & (value)) << 0)
+
+/***GPT Write HW Modified Timer 6 Control Register If set
+ and clear bit are written concurrently with 1, the associated bit is not changed.***/
+#define INCA_IP_GPTU_GPT_WHBT6CON                 ((volatile u32*)(INCA_IP_GPTU+ 0x0054))
+#define INCA_IP_GPTU_GPT_WHBT6CON_SETT6OTL                  (1 << 11)
+#define INCA_IP_GPTU_GPT_WHBT6CON_CLRT6OTL                  (1 << 10)
+
+/***GPT Timer 5 Control Register***/
+#define INCA_IP_GPTU_GPT_T5CON                    ((volatile u32*)(INCA_IP_GPTU+ 0x001C))
+#define INCA_IP_GPTU_GPT_T5CON_T5SC                            (1 << 15)
+#define INCA_IP_GPTU_GPT_T5CON_T5CLR                          (1 << 14)
+#define INCA_IP_GPTU_GPT_T5CON_CI (value)                (((( 1 << 2) - 1) & (value)) << 12)
+#define INCA_IP_GPTU_GPT_T5CON_T5CC                            (1 << 11)
+#define INCA_IP_GPTU_GPT_T5CON_CT3                              (1 << 10)
+#define INCA_IP_GPTU_GPT_T5CON_T5RC                            (1 << 9)
+#define INCA_IP_GPTU_GPT_T5CON_T5UDE                          (1 << 8)
+#define INCA_IP_GPTU_GPT_T5CON_T5UD                            (1 << 7)
+#define INCA_IP_GPTU_GPT_T5CON_T5R                              (1 << 6)
+#define INCA_IP_GPTU_GPT_T5CON_T5M (value)                (((( 1 << 3) - 1) & (value)) << 3)
+#define INCA_IP_GPTU_GPT_T5CON_T5I (value)                (((( 1 << 3) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/*  Module      :  IOM register address and bits                       */
+/***********************************************************************/
+
+#define INCA_IP_IOM                          (0xBF105000)
+/***********************************************************************/
+
+
+/***Receive FIFO***/
+#define INCA_IP_IOM_RFIFO                        ((volatile u32*)(INCA_IP_IOM+ 0x0000))
+#define INCA_IP_IOM_RFIFO_RXD (value)                (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Transmit FIFO***/
+#define INCA_IP_IOM_XFIFO                        ((volatile u32*)(INCA_IP_IOM+ 0x0000))
+#define INCA_IP_IOM_XFIFO_TXD (value)                (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Interrupt Status Register HDLC***/
+#define INCA_IP_IOM_ISTAH                        ((volatile u32*)(INCA_IP_IOM+ 0x0080))
+#define INCA_IP_IOM_ISTAH_RME                              (1 << 7)
+#define INCA_IP_IOM_ISTAH_RPF                              (1 << 6)
+#define INCA_IP_IOM_ISTAH_RFO                              (1 << 5)
+#define INCA_IP_IOM_ISTAH_XPR                              (1 << 4)
+#define INCA_IP_IOM_ISTAH_XMR                              (1 << 3)
+#define INCA_IP_IOM_ISTAH_XDU                              (1 << 2)
+
+/***Interrupt Mask Register HDLC***/
+#define INCA_IP_IOM_MASKH                        ((volatile u32*)(INCA_IP_IOM+ 0x0080))
+#define INCA_IP_IOM_MASKH_RME                              (1 << 7)
+#define INCA_IP_IOM_MASKH_RPF                              (1 << 6)
+#define INCA_IP_IOM_MASKH_RFO                              (1 << 5)
+#define INCA_IP_IOM_MASKH_XPR                              (1 << 4)
+#define INCA_IP_IOM_MASKH_XMR                              (1 << 3)
+#define INCA_IP_IOM_MASKH_XDU                              (1 << 2)
+
+/***Status Register***/
+#define INCA_IP_IOM_STAR                         ((volatile u32*)(INCA_IP_IOM+ 0x0084))
+#define INCA_IP_IOM_STAR_XDOV                            (1 << 7)
+#define INCA_IP_IOM_STAR_XFW                              (1 << 6)
+#define INCA_IP_IOM_STAR_RACI                            (1 << 3)
+#define INCA_IP_IOM_STAR_XACI                            (1 << 1)
+
+/***Command Register***/
+#define INCA_IP_IOM_CMDR                         ((volatile u32*)(INCA_IP_IOM+ 0x0084))
+#define INCA_IP_IOM_CMDR_RMC                              (1 << 7)
+#define INCA_IP_IOM_CMDR_RRES                            (1 << 6)
+#define INCA_IP_IOM_CMDR_XTF                              (1 << 3)
+#define INCA_IP_IOM_CMDR_XME                              (1 << 1)
+#define INCA_IP_IOM_CMDR_XRES                            (1 << 0)
+
+/***Mode Register***/
+#define INCA_IP_IOM_MODEH                        ((volatile u32*)(INCA_IP_IOM+ 0x0088))
+#define INCA_IP_IOM_MODEH_MDS2                            (1 << 7)
+#define INCA_IP_IOM_MODEH_MDS1                            (1 << 6)
+#define INCA_IP_IOM_MODEH_MDS0                            (1 << 5)
+#define INCA_IP_IOM_MODEH_RAC                              (1 << 3)
+#define INCA_IP_IOM_MODEH_DIM2                            (1 << 2)
+#define INCA_IP_IOM_MODEH_DIM1                            (1 << 1)
+#define INCA_IP_IOM_MODEH_DIM0                            (1 << 0)
+
+/***Extended Mode Register***/
+#define INCA_IP_IOM_EXMR                         ((volatile u32*)(INCA_IP_IOM+ 0x008C))
+#define INCA_IP_IOM_EXMR_XFBS                            (1 << 7)
+#define INCA_IP_IOM_EXMR_RFBS (value)               (((( 1 << 2) - 1) & (value)) << 5)
+#define INCA_IP_IOM_EXMR_SRA                              (1 << 4)
+#define INCA_IP_IOM_EXMR_XCRC                            (1 << 3)
+#define INCA_IP_IOM_EXMR_RCRC                            (1 << 2)
+#define INCA_IP_IOM_EXMR_ITF                              (1 << 0)
+
+/***SAPI1 Register***/
+#define INCA_IP_IOM_SAP1                         ((volatile u32*)(INCA_IP_IOM+ 0x0094))
+#define INCA_IP_IOM_SAP1_SAPI1 (value)              (((( 1 << 6) - 1) & (value)) << 2)
+#define INCA_IP_IOM_SAP1_MHA                              (1 << 0)
+
+/***Receive Frame Byte Count Low***/
+#define INCA_IP_IOM_RBCL                         ((volatile u32*)(INCA_IP_IOM+ 0x0098))
+#define INCA_IP_IOM_RBCL_RBC(value)              (1 << value)
+
+
+/***SAPI2 Register***/
+#define INCA_IP_IOM_SAP2                         ((volatile u32*)(INCA_IP_IOM+ 0x0098))
+#define INCA_IP_IOM_SAP2_SAPI2 (value)              (((( 1 << 6) - 1) & (value)) << 2)
+#define INCA_IP_IOM_SAP2_MLA                              (1 << 0)
+
+/***Receive Frame Byte Count High***/
+#define INCA_IP_IOM_RBCH                         ((volatile u32*)(INCA_IP_IOM+ 0x009C))
+#define INCA_IP_IOM_RBCH_OV                              (1 << 4)
+#define INCA_IP_IOM_RBCH_RBC11                          (1 << 3)
+#define INCA_IP_IOM_RBCH_RBC10                          (1 << 2)
+#define INCA_IP_IOM_RBCH_RBC9                            (1 << 1)
+#define INCA_IP_IOM_RBCH_RBC8                            (1 << 0)
+
+/***TEI1 Register 1***/
+#define INCA_IP_IOM_TEI1                         ((volatile u32*)(INCA_IP_IOM+ 0x009C))
+#define INCA_IP_IOM_TEI1_TEI1 (value)               (((( 1 << 7) - 1) & (value)) << 1)
+#define INCA_IP_IOM_TEI1_EA                              (1 << 0)
+
+/***Receive Status Register***/
+#define INCA_IP_IOM_RSTA                         ((volatile u32*)(INCA_IP_IOM+ 0x00A0))
+#define INCA_IP_IOM_RSTA_VFR                              (1 << 7)
+#define INCA_IP_IOM_RSTA_RDO                              (1 << 6)
+#define INCA_IP_IOM_RSTA_CRC                              (1 << 5)
+#define INCA_IP_IOM_RSTA_RAB                              (1 << 4)
+#define INCA_IP_IOM_RSTA_SA1                              (1 << 3)
+#define INCA_IP_IOM_RSTA_SA0                              (1 << 2)
+#define INCA_IP_IOM_RSTA_TA                              (1 << 0)
+#define INCA_IP_IOM_RSTA_CR                              (1 << 1)
+
+/***TEI2 Register***/
+#define INCA_IP_IOM_TEI2                         ((volatile u32*)(INCA_IP_IOM+ 0x00A0))
+#define INCA_IP_IOM_TEI2_TEI2 (value)               (((( 1 << 7) - 1) & (value)) << 1)
+#define INCA_IP_IOM_TEI2_EA                              (1 << 0)
+
+/***Test Mode Register HDLC***/
+#define INCA_IP_IOM_TMH                          ((volatile u32*)(INCA_IP_IOM+ 0x00A4))
+#define INCA_IP_IOM_TMH_TLP                              (1 << 0)
+
+/***Command/Indication Receive 0***/
+#define INCA_IP_IOM_CIR0                         ((volatile u32*)(INCA_IP_IOM+ 0x00B8))
+#define INCA_IP_IOM_CIR0_CODR0 (value)              (((( 1 << 4) - 1) & (value)) << 4)
+#define INCA_IP_IOM_CIR0_CIC0                            (1 << 3)
+#define INCA_IP_IOM_CIR0_CIC1                            (1 << 2)
+#define INCA_IP_IOM_CIR0_SG                              (1 << 1)
+#define INCA_IP_IOM_CIR0_BAS                              (1 << 0)
+
+/***Command/Indication Transmit 0***/
+#define INCA_IP_IOM_CIX0                         ((volatile u32*)(INCA_IP_IOM+ 0x00B8))
+#define INCA_IP_IOM_CIX0_CODX0 (value)              (((( 1 << 4) - 1) & (value)) << 4)
+#define INCA_IP_IOM_CIX0_TBA2                            (1 << 3)
+#define INCA_IP_IOM_CIX0_TBA1                            (1 << 2)
+#define INCA_IP_IOM_CIX0_TBA0                            (1 << 1)
+#define INCA_IP_IOM_CIX0_BAC                              (1 << 0)
+
+/***Command/Indication Receive 1***/
+#define INCA_IP_IOM_CIR1                         ((volatile u32*)(INCA_IP_IOM+ 0x00BC))
+#define INCA_IP_IOM_CIR1_CODR1 (value)              (((( 1 << 6) - 1) & (value)) << 2)
+
+/***Command/Indication Transmit 1***/
+#define INCA_IP_IOM_CIX1                         ((volatile u32*)(INCA_IP_IOM+ 0x00BC))
+#define INCA_IP_IOM_CIX1_CODX1 (value)              (((( 1 << 6) - 1) & (value)) << 2)
+#define INCA_IP_IOM_CIX1_CICW                            (1 << 1)
+#define INCA_IP_IOM_CIX1_CI1E                            (1 << 0)
+
+/***Controller Data Access Reg. (CH10)***/
+#define INCA_IP_IOM_CDA10                        ((volatile u32*)(INCA_IP_IOM+ 0x0100))
+#define INCA_IP_IOM_CDA10_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Controller Data Access Reg. (CH11)***/
+#define INCA_IP_IOM_CDA11                        ((volatile u32*)(INCA_IP_IOM+ 0x0104))
+#define INCA_IP_IOM_CDA11_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Controller Data Access Reg. (CH20)***/
+#define INCA_IP_IOM_CDA20                        ((volatile u32*)(INCA_IP_IOM+ 0x0108))
+#define INCA_IP_IOM_CDA20_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Controller Data Access Reg. (CH21)***/
+#define INCA_IP_IOM_CDA21                        ((volatile u32*)(INCA_IP_IOM+ 0x010C))
+#define INCA_IP_IOM_CDA21_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH10)***/
+#define INCA_IP_IOM_CDA_TSDP10                   ((volatile u32*)(INCA_IP_IOM+ 0x0110))
+#define INCA_IP_IOM_CDA_TSDP10_DPS                              (1 << 7)
+#define INCA_IP_IOM_CDA_TSDP10_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH11)***/
+#define INCA_IP_IOM_CDA_TSDP11                   ((volatile u32*)(INCA_IP_IOM+ 0x0114))
+#define INCA_IP_IOM_CDA_TSDP11_DPS                              (1 << 7)
+#define INCA_IP_IOM_CDA_TSDP11_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH20)***/
+#define INCA_IP_IOM_CDA_TSDP20                   ((volatile u32*)(INCA_IP_IOM+ 0x0118))
+#define INCA_IP_IOM_CDA_TSDP20_DPS                              (1 << 7)
+#define INCA_IP_IOM_CDA_TSDP20_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH21)***/
+#define INCA_IP_IOM_CDA_TSDP21                   ((volatile u32*)(INCA_IP_IOM+ 0x011C))
+#define INCA_IP_IOM_CDA_TSDP21_DPS                              (1 << 7)
+#define INCA_IP_IOM_CDA_TSDP21_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH10)***/
+#define INCA_IP_IOM_CO_TSDP10                    ((volatile u32*)(INCA_IP_IOM+ 0x0120))
+#define INCA_IP_IOM_CO_TSDP10_DPS                              (1 << 7)
+#define INCA_IP_IOM_CO_TSDP10_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH11)***/
+#define INCA_IP_IOM_CO_TSDP11                    ((volatile u32*)(INCA_IP_IOM+ 0x0124))
+#define INCA_IP_IOM_CO_TSDP11_DPS                              (1 << 7)
+#define INCA_IP_IOM_CO_TSDP11_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH20)***/
+#define INCA_IP_IOM_CO_TSDP20                    ((volatile u32*)(INCA_IP_IOM+ 0x0128))
+#define INCA_IP_IOM_CO_TSDP20_DPS                              (1 << 7)
+#define INCA_IP_IOM_CO_TSDP20_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Time Slot and Data Port Sel. (CH21)***/
+#define INCA_IP_IOM_CO_TSDP21                    ((volatile u32*)(INCA_IP_IOM+ 0x012C))
+#define INCA_IP_IOM_CO_TSDP21_DPS                              (1 << 7)
+#define INCA_IP_IOM_CO_TSDP21_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Ctrl. Reg. Contr. Data Access CH1x***/
+#define INCA_IP_IOM_CDA1_CR                      ((volatile u32*)(INCA_IP_IOM+ 0x0138))
+#define INCA_IP_IOM_CDA1_CR_EN_TBM                        (1 << 5)
+#define INCA_IP_IOM_CDA1_CR_EN_I1                          (1 << 4)
+#define INCA_IP_IOM_CDA1_CR_EN_I0                          (1 << 3)
+#define INCA_IP_IOM_CDA1_CR_EN_O1                          (1 << 2)
+#define INCA_IP_IOM_CDA1_CR_EN_O0                          (1 << 1)
+#define INCA_IP_IOM_CDA1_CR_SWAP                            (1 << 0)
+
+/***Ctrl. Reg. Contr. Data Access CH1x***/
+#define INCA_IP_IOM_CDA2_CR                      ((volatile u32*)(INCA_IP_IOM+ 0x013C))
+#define INCA_IP_IOM_CDA2_CR_EN_TBM                        (1 << 5)
+#define INCA_IP_IOM_CDA2_CR_EN_I1                          (1 << 4)
+#define INCA_IP_IOM_CDA2_CR_EN_I0                          (1 << 3)
+#define INCA_IP_IOM_CDA2_CR_EN_O1                          (1 << 2)
+#define INCA_IP_IOM_CDA2_CR_EN_O0                          (1 << 1)
+#define INCA_IP_IOM_CDA2_CR_SWAP                            (1 << 0)
+
+/***Control Register B-Channel Data***/
+#define INCA_IP_IOM_BCHA_CR                      ((volatile u32*)(INCA_IP_IOM+ 0x0144))
+#define INCA_IP_IOM_BCHA_CR_EN_BC2                        (1 << 4)
+#define INCA_IP_IOM_BCHA_CR_EN_BC1                        (1 << 3)
+
+/***Control Register B-Channel Data***/
+#define INCA_IP_IOM_BCHB_CR                      ((volatile u32*)(INCA_IP_IOM+ 0x0148))
+#define INCA_IP_IOM_BCHB_CR_EN_BC2                        (1 << 4)
+#define INCA_IP_IOM_BCHB_CR_EN_BC1                        (1 << 3)
+
+/***Control Reg. for HDLC and CI1 Data***/
+#define INCA_IP_IOM_DCI_CR                       ((volatile u32*)(INCA_IP_IOM+ 0x014C))
+#define INCA_IP_IOM_DCI_CR_DPS_CI1                      (1 << 7)
+#define INCA_IP_IOM_DCI_CR_EN_CI1                        (1 << 6)
+#define INCA_IP_IOM_DCI_CR_EN_D                            (1 << 5)
+
+/***Control Reg. for HDLC and CI1 Data***/
+#define INCA_IP_IOM_DCIC_CR                      ((volatile u32*)(INCA_IP_IOM+ 0x014C))
+#define INCA_IP_IOM_DCIC_CR_DPS_CI0                      (1 << 7)
+#define INCA_IP_IOM_DCIC_CR_EN_CI0                        (1 << 6)
+#define INCA_IP_IOM_DCIC_CR_DPS_D                          (1 << 5)
+
+/***Control Reg. Serial Data Strobe x***/
+#define INCA_IP_IOM_SDS_CR                       ((volatile u32*)(INCA_IP_IOM+ 0x0154))
+#define INCA_IP_IOM_SDS_CR_ENS_TSS                      (1 << 7)
+#define INCA_IP_IOM_SDS_CR_ENS_TSS_1                  (1 << 6)
+#define INCA_IP_IOM_SDS_CR_ENS_TSS_3                  (1 << 5)
+#define INCA_IP_IOM_SDS_CR_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Control Register IOM Data***/
+#define INCA_IP_IOM_IOM_CR                       ((volatile u32*)(INCA_IP_IOM+ 0x015C))
+#define INCA_IP_IOM_IOM_CR_SPU                              (1 << 7)
+#define INCA_IP_IOM_IOM_CR_CI_CS                          (1 << 5)
+#define INCA_IP_IOM_IOM_CR_TIC_DIS                      (1 << 4)
+#define INCA_IP_IOM_IOM_CR_EN_BCL                        (1 << 3)
+#define INCA_IP_IOM_IOM_CR_CLKM                            (1 << 2)
+#define INCA_IP_IOM_IOM_CR_Res                              (1 << 1)
+#define INCA_IP_IOM_IOM_CR_DIS_IOM                      (1 << 0)
+
+/***Synchronous Transfer Interrupt***/
+#define INCA_IP_IOM_STI                          ((volatile u32*)(INCA_IP_IOM+ 0x0160))
+#define INCA_IP_IOM_STI_STOV21                        (1 << 7)
+#define INCA_IP_IOM_STI_STOV20                        (1 << 6)
+#define INCA_IP_IOM_STI_STOV11                        (1 << 5)
+#define INCA_IP_IOM_STI_STOV10                        (1 << 4)
+#define INCA_IP_IOM_STI_STI21                          (1 << 3)
+#define INCA_IP_IOM_STI_STI20                          (1 << 2)
+#define INCA_IP_IOM_STI_STI11                          (1 << 1)
+#define INCA_IP_IOM_STI_STI10                          (1 << 0)
+
+/***Acknowledge Synchronous Transfer Interrupt***/
+#define INCA_IP_IOM_ASTI                         ((volatile u32*)(INCA_IP_IOM+ 0x0160))
+#define INCA_IP_IOM_ASTI_ACK21                          (1 << 3)
+#define INCA_IP_IOM_ASTI_ACK20                          (1 << 2)
+#define INCA_IP_IOM_ASTI_ACK11                          (1 << 1)
+#define INCA_IP_IOM_ASTI_ACK10                          (1 << 0)
+
+/***Mask Synchronous Transfer Interrupt***/
+#define INCA_IP_IOM_MSTI                         ((volatile u32*)(INCA_IP_IOM+ 0x0164))
+#define INCA_IP_IOM_MSTI_STOV21                        (1 << 7)
+#define INCA_IP_IOM_MSTI_STOV20                        (1 << 6)
+#define INCA_IP_IOM_MSTI_STOV11                        (1 << 5)
+#define INCA_IP_IOM_MSTI_STOV10                        (1 << 4)
+#define INCA_IP_IOM_MSTI_STI21                          (1 << 3)
+#define INCA_IP_IOM_MSTI_STI20                          (1 << 2)
+#define INCA_IP_IOM_MSTI_STI11                          (1 << 1)
+#define INCA_IP_IOM_MSTI_STI10                          (1 << 0)
+
+/***Configuration Register for Serial Data Strobes***/
+#define INCA_IP_IOM_SDS_CONF                    ((volatile u32*)(INCA_IP_IOM+ 0x0168))
+#define INCA_IP_IOM_SDS_CONF_SDS_BCL                      (1 << 0)
+
+/***Monitoring CDA Bits***/
+#define INCA_IP_IOM_MCDA                         ((volatile u32*)(INCA_IP_IOM+ 0x016C))
+#define INCA_IP_IOM_MCDA_MCDA21 (value)             (((( 1 << 2) - 1) & (value)) << 6)
+#define INCA_IP_IOM_MCDA_MCDA20 (value)             (((( 1 << 2) - 1) & (value)) << 4)
+#define INCA_IP_IOM_MCDA_MCDA11 (value)             (((( 1 << 2) - 1) & (value)) << 2)
+#define INCA_IP_IOM_MCDA_MCDA10 (value)             (((( 1 << 2) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/*  Module      :  ASC register address and bits                       */
+/***********************************************************************/
+
+#if defined(CONFIG_INCA_IP)
+#define INCA_IP_ASC                          (0xB8000400)
+#elif defined(CONFIG_PURPLE)
+#define INCA_IP_ASC                          (0xBE500000)
+#endif
+
+/***********************************************************************/
+
+
+/***ASC Port Input Select Register***/
+#define INCA_IP_ASC_ASC_PISEL                    ((volatile u32*)(INCA_IP_ASC+ 0x0004))
+#define INCA_IP_ASC_ASC_PISEL_RIS                              (1 << 0)
+
+/***ASC Control Register***/
+#define INCA_IP_ASC_ASC_CON                      ((volatile u32*)(INCA_IP_ASC+ 0x0010))
+#define INCA_IP_ASC_ASC_CON_R                              (1 << 15)
+#define INCA_IP_ASC_ASC_CON_LB                              (1 << 14)
+#define INCA_IP_ASC_ASC_CON_BRS                              (1 << 13)
+#define INCA_IP_ASC_ASC_CON_ODD                              (1 << 12)
+#define INCA_IP_ASC_ASC_CON_FDE                              (1 << 11)
+#define INCA_IP_ASC_ASC_CON_OE                              (1 << 10)
+#define INCA_IP_ASC_ASC_CON_FE                              (1 << 9)
+#define INCA_IP_ASC_ASC_CON_PE                              (1 << 8)
+#define INCA_IP_ASC_ASC_CON_OEN                              (1 << 7)
+#define INCA_IP_ASC_ASC_CON_FEN                              (1 << 6)
+#define INCA_IP_ASC_ASC_CON_PENRXDI                  (1 << 5)
+#define INCA_IP_ASC_ASC_CON_REN                              (1 << 4)
+#define INCA_IP_ASC_ASC_CON_STP                              (1 << 3)
+#define INCA_IP_ASC_ASC_CON_M (value)                (((( 1 << 3) - 1) & (value)) << 0)
+
+/***ASC Write Hardware Modified Control Register***/
+#define INCA_IP_ASC_ASC_WHBCON                   ((volatile u32*)(INCA_IP_ASC+ 0x0050))
+#define INCA_IP_ASC_ASC_WHBCON_SETOE                          (1 << 13)
+#define INCA_IP_ASC_ASC_WHBCON_SETFE                          (1 << 12)
+#define INCA_IP_ASC_ASC_WHBCON_SETPE                          (1 << 11)
+#define INCA_IP_ASC_ASC_WHBCON_CLROE                          (1 << 10)
+#define INCA_IP_ASC_ASC_WHBCON_CLRFE                          (1 << 9)
+#define INCA_IP_ASC_ASC_WHBCON_CLRPE                          (1 << 8)
+#define INCA_IP_ASC_ASC_WHBCON_SETREN                        (1 << 5)
+#define INCA_IP_ASC_ASC_WHBCON_CLRREN                        (1 << 4)
+
+/***ASC Baudrate Timer/Reload Register***/
+#define INCA_IP_ASC_ASC_BTR                      ((volatile u32*)(INCA_IP_ASC+ 0x0014))
+#define INCA_IP_ASC_ASC_BTR_BR_VALUE (value)          (((( 1 << 13) - 1) & (value)) << 0)
+
+/***ASC Fractional Divider Register***/
+#define INCA_IP_ASC_ASC_FDV                      ((volatile u32*)(INCA_IP_ASC+ 0x0018))
+#define INCA_IP_ASC_ASC_FDV_FD_VALUE (value)          (((( 1 << 9) - 1) & (value)) << 0)
+
+/***ASC IrDA Pulse Mode/Width Register***/
+#define INCA_IP_ASC_ASC_PMW                      ((volatile u32*)(INCA_IP_ASC+ 0x001C))
+#define INCA_IP_ASC_ASC_PMW_IRPW                            (1 << 8)
+#define INCA_IP_ASC_ASC_PMW_PW_VALUE (value)          (((( 1 << 8) - 1) & (value)) << 0)
+
+/***ASC Transmit Buffer Register***/
+#define INCA_IP_ASC_ASC_TBUF                    ((volatile u32*)(INCA_IP_ASC+ 0x0020))
+#define INCA_IP_ASC_ASC_TBUF_TD_VALUE (value)          (((( 1 << 9) - 1) & (value)) << 0)
+
+/***ASC Receive Buffer Register***/
+#define INCA_IP_ASC_ASC_RBUF                    ((volatile u32*)(INCA_IP_ASC+ 0x0024))
+#define INCA_IP_ASC_ASC_RBUF_RD_VALUE (value)          (((( 1 << 9) - 1) & (value)) << 0)
+
+/***ASC Autobaud Control Register***/
+#define INCA_IP_ASC_ASC_ABCON                    ((volatile u32*)(INCA_IP_ASC+ 0x0030))
+#define INCA_IP_ASC_ASC_ABCON_RXINV                          (1 << 11)
+#define INCA_IP_ASC_ASC_ABCON_TXINV                          (1 << 10)
+#define INCA_IP_ASC_ASC_ABCON_ABEM (value)               (((( 1 << 2) - 1) & (value)) << 8)
+#define INCA_IP_ASC_ASC_ABCON_FCDETEN                      (1 << 4)
+#define INCA_IP_ASC_ASC_ABCON_ABDETEN                      (1 << 3)
+#define INCA_IP_ASC_ASC_ABCON_ABSTEN                        (1 << 2)
+#define INCA_IP_ASC_ASC_ABCON_AUREN                          (1 << 1)
+#define INCA_IP_ASC_ASC_ABCON_ABEN                            (1 << 0)
+
+/***Receive FIFO Control Register***/
+#define INCA_IP_ASC_RXFCON                       ((volatile u32*)(INCA_IP_ASC+ 0x0040))
+#define INCA_IP_ASC_RXFCON_RXFITL (value)             (((( 1 << 6) - 1) & (value)) << 8)
+#define INCA_IP_ASC_RXFCON_RXTMEN                        (1 << 2)
+#define INCA_IP_ASC_RXFCON_RXFFLU                        (1 << 1)
+#define INCA_IP_ASC_RXFCON_RXFEN                          (1 << 0)
+
+/***Transmit FIFO Control Register***/
+#define INCA_IP_ASC_TXFCON                       ((volatile u32*)(INCA_IP_ASC+ 0x0044))
+#define INCA_IP_ASC_TXFCON_TXFITL (value)             (((( 1 << 6) - 1) & (value)) << 8)
+#define INCA_IP_ASC_TXFCON_TXTMEN                        (1 << 2)
+#define INCA_IP_ASC_TXFCON_TXFFLU                        (1 << 1)
+#define INCA_IP_ASC_TXFCON_TXFEN                          (1 << 0)
+
+/***FIFO Status Register***/
+#define INCA_IP_ASC_FSTAT                        ((volatile u32*)(INCA_IP_ASC+ 0x0048))
+#define INCA_IP_ASC_FSTAT_TXFFL (value)              (((( 1 << 6) - 1) & (value)) << 8)
+#define INCA_IP_ASC_FSTAT_RXFFL (value)              (((( 1 << 6) - 1) & (value)) << 0)
+
+/***ASC Write HW Modified Autobaud Control Register***/
+#define INCA_IP_ASC_ASC_WHBABCON                 ((volatile u32*)(INCA_IP_ASC+ 0x0054))
+#define INCA_IP_ASC_ASC_WHBABCON_SETABEN                      (1 << 1)
+#define INCA_IP_ASC_ASC_WHBABCON_CLRABEN                      (1 << 0)
+
+/***ASC Autobaud Status Register***/
+#define INCA_IP_ASC_ASC_ABSTAT                   ((volatile u32*)(INCA_IP_ASC+ 0x0034))
+#define INCA_IP_ASC_ASC_ABSTAT_DETWAIT                      (1 << 4)
+#define INCA_IP_ASC_ASC_ABSTAT_SCCDET                        (1 << 3)
+#define INCA_IP_ASC_ASC_ABSTAT_SCSDET                        (1 << 2)
+#define INCA_IP_ASC_ASC_ABSTAT_FCCDET                        (1 << 1)
+#define INCA_IP_ASC_ASC_ABSTAT_FCSDET                        (1 << 0)
+
+/***ASC Write HW Modified Autobaud Status Register***/
+#define INCA_IP_ASC_ASC_WHBABSTAT                 ((volatile u32*)(INCA_IP_ASC+ 0x0058))
+#define INCA_IP_ASC_ASC_WHBABSTAT_SETDETWAIT                (1 << 9)
+#define INCA_IP_ASC_ASC_WHBABSTAT_CLRDETWAIT                (1 << 8)
+#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCCDET                  (1 << 7)
+#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCCDET                  (1 << 6)
+#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCSDET                  (1 << 5)
+#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCSDET                  (1 << 4)
+#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCCDET                  (1 << 3)
+#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCCDET                  (1 << 2)
+#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCSDET                  (1 << 1)
+#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCSDET                  (1 << 0)
+
+/***ASC Clock Control Register***/
+#define INCA_IP_ASC_ASC_CLC                      ((volatile u32*)(INCA_IP_ASC+ 0x0000))
+#define INCA_IP_ASC_ASC_CLC_RMC (value)                (((( 1 << 8) - 1) & (value)) << 8)
+#define INCA_IP_ASC_ASC_CLC_DISS                            (1 << 1)
+#define INCA_IP_ASC_ASC_CLC_DISR                            (1 << 0)
+
+/***********************************************************************/
+/*  Module      :  DMA register address and bits                       */
+/***********************************************************************/
+
+#define INCA_IP_DMA                          (0xBF108000)
+/***********************************************************************/
+
+
+/***DMA RX Channel 0 Command Register***/
+#define INCA_IP_DMA_DMA_RXCCR0                   ((volatile u32*)(INCA_IP_DMA+ 0x0800))
+#define INCA_IP_DMA_DMA_RXCCR0_LBE                              (1 << 31)
+#define INCA_IP_DMA_DMA_RXCCR0_HPEN                            (1 << 30)
+#define INCA_IP_DMA_DMA_RXCCR0_INIT                            (1 << 2)
+#define INCA_IP_DMA_DMA_RXCCR0_OFF                              (1 << 1)
+#define INCA_IP_DMA_DMA_RXCCR0_HR                              (1 << 0)
+
+/***DMA RX Channel 1 Command Register***/
+#define INCA_IP_DMA_DMA_RXCCR1                   ((volatile u32*)(INCA_IP_DMA+ 0x0804))
+#define INCA_IP_DMA_DMA_RXCCR1_LBE                              (1 << 31)
+#define INCA_IP_DMA_DMA_RXCCR1_HPEN                            (1 << 30)
+#define INCA_IP_DMA_DMA_RXCCR1_INIT                            (1 << 2)
+#define INCA_IP_DMA_DMA_RXCCR1_OFF                              (1 << 1)
+#define INCA_IP_DMA_DMA_RXCCR1_HR                              (1 << 0)
+
+/***DMA Receive Interrupt Status Register***/
+#define INCA_IP_DMA_DMA_RXISR                    ((volatile u32*)(INCA_IP_DMA+ 0x0808))
+#define INCA_IP_DMA_DMA_RXISR_RDERRx (value)             (((( 1 << 2) - 1) & (value)) << 8)
+#define INCA_IP_DMA_DMA_RXISR_CMDCPTx (value)            (((( 1 << 2) - 1) & (value)) << 6)
+#define INCA_IP_DMA_DMA_RXISR_EOPx (value)               (((( 1 << 2) - 1) & (value)) << 4)
+#define INCA_IP_DMA_DMA_RXISR_CPTx (value)               (((( 1 << 2) - 1) & (value)) << 2)
+#define INCA_IP_DMA_DMA_RXISR_HLDx (value)               (((( 1 << 2) - 1) & (value)) << 0)
+
+/***DMA Receive Interrupt Mask Register***/
+#define INCA_IP_DMA_DMA_RXIMR                    ((volatile u32*)(INCA_IP_DMA+ 0x080C))
+#define INCA_IP_DMA_DMA_RXIMR_RDERRx (value)             (((( 1 << 2) - 1) & (value)) << 8)
+#define INCA_IP_DMA_DMA_RXIMR_CMDCPTx (value)            (((( 1 << 2) - 1) & (value)) << 6)
+#define INCA_IP_DMA_DMA_RXIMR_EOPx (value)               (((( 1 << 2) - 1) & (value)) << 4)
+#define INCA_IP_DMA_DMA_RXIMR_CPTx (value)               (((( 1 << 2) - 1) & (value)) << 2)
+#define INCA_IP_DMA_DMA_RXIMR_HLDx (value)               (((( 1 << 2) - 1) & (value)) << 0)
+
+/***DMA First Receive Descriptor Addr. for Rx Channel 0
+***/
+#define INCA_IP_DMA_DMA_RXFRDA0                  ((volatile u32*)(INCA_IP_DMA+ 0x0810))
+#define INCA_IP_DMA_DMA_RXFRDA0_RXFRDA (value)             (((( 1 << 28) - 1) & (value)) << 0)
+
+/***DMA First Receive Descriptor Addr. for Rx Channel 1
+***/
+#define INCA_IP_DMA_DMA_RXFRDA1                  ((volatile u32*)(INCA_IP_DMA+ 0x0814))
+#define INCA_IP_DMA_DMA_RXFRDA1_RXFRDA (value)             (((( 1 << 28) - 1) & (value)) << 0)
+
+/***DMA Receive Channel Polling Time***/
+#define INCA_IP_DMA_DMA_RXPOLL                   ((volatile u32*)(INCA_IP_DMA+ 0x0818))
+#define INCA_IP_DMA_DMA_RXPOLL_BSZ1 (value)               (((( 1 << 2) - 1) & (value)) << 30)
+#define INCA_IP_DMA_DMA_RXPOLL_BSZ0 (value)               (((( 1 << 2) - 1) & (value)) << 28)
+#define INCA_IP_DMA_DMA_RXPOLL_RXPOLLTIME (value)         (((( 1 << 8) - 1) & (value)) << 0)
+
+/***DMA TX Channel 0 Command Register (Voice Port)***/
+#define INCA_IP_DMA_DMA_TXCCR0                   ((volatile u32*)(INCA_IP_DMA+ 0x0880))
+#define INCA_IP_DMA_DMA_TXCCR0_LBE                              (1 << 31)
+#define INCA_IP_DMA_DMA_TXCCR0_HPEN                            (1 << 30)
+#define INCA_IP_DMA_DMA_TXCCR0_HR                              (1 << 2)
+#define INCA_IP_DMA_DMA_TXCCR0_OFF                              (1 << 1)
+#define INCA_IP_DMA_DMA_TXCCR0_INIT                            (1 << 0)
+
+/***DMA TX Channel 1 Command Register (Mangmt Port)***/
+#define INCA_IP_DMA_DMA_TXCCR1                   ((volatile u32*)(INCA_IP_DMA+ 0x0884))
+#define INCA_IP_DMA_DMA_TXCCR1_LBE                              (1 << 31)
+#define INCA_IP_DMA_DMA_TXCCR1_HPEN                            (1 << 30)
+#define INCA_IP_DMA_DMA_TXCCR1_HR                              (1 << 2)
+#define INCA_IP_DMA_DMA_TXCCR1_OFF                              (1 << 1)
+#define INCA_IP_DMA_DMA_TXCCR1_INIT                            (1 << 0)
+
+/***DMA TX Channel 2 Command Register (SSC Port)***/
+#define INCA_IP_DMA_DMA_TXCCR2                   ((volatile u32*)(INCA_IP_DMA+ 0x0888))
+#define INCA_IP_DMA_DMA_TXCCR2_LBE                              (1 << 31)
+#define INCA_IP_DMA_DMA_TXCCR2_HPEN                            (1 << 30)
+#define INCA_IP_DMA_DMA_TXCCR2_HBF                              (1 << 29)
+#define INCA_IP_DMA_DMA_TXCCR2_HR                              (1 << 2)
+#define INCA_IP_DMA_DMA_TXCCR2_OFF                              (1 << 1)
+#define INCA_IP_DMA_DMA_TXCCR2_INIT                            (1 << 0)
+
+/***DMA First Receive Descriptor Addr. for Tx Channel 0
+***/
+#define INCA_IP_DMA_DMA_TXFRDA0                  ((volatile u32*)(INCA_IP_DMA+ 0x08A0))
+#define INCA_IP_DMA_DMA_TXFRDA0_TXFRDA (value)             (((( 1 << 28) - 1) & (value)) << 0)
+
+/***DMA First Receive Descriptor Addr. for Tx Channel 1
+***/
+#define INCA_IP_DMA_DMA_TXFRDA1                  ((volatile u32*)(INCA_IP_DMA+ 0x08A4))
+#define INCA_IP_DMA_DMA_TXFRDA1_TXFRDA (value)             (((( 1 << 28) - 1) & (value)) << 0)
+
+/***DMA First Receive Descriptor Addr. for Tx Channel 2
+***/
+#define INCA_IP_DMA_DMA_TXFRDA2                  ((volatile u32*)(INCA_IP_DMA+ 0x08A8))
+#define INCA_IP_DMA_DMA_TXFRDA2_TXFRDA (value)             (((( 1 << 28) - 1) & (value)) << 0)
+
+/***DMA Transmit Channel Arbitration Register***/
+#define INCA_IP_DMA_DMA_TXWGT                    ((volatile u32*)(INCA_IP_DMA+ 0x08C0))
+#define INCA_IP_DMA_DMA_TXWGT_TX2PR (value)              (((( 1 << 2) - 1) & (value)) << 4)
+#define INCA_IP_DMA_DMA_TXWGT_TX1PRI (value)             (((( 1 << 2) - 1) & (value)) << 2)
+#define INCA_IP_DMA_DMA_TXWGT_TX0PRI (value)             (((( 1 << 2) - 1) & (value)) << 0)
+
+/***DMA Transmit Channel Polling Time***/
+#define INCA_IP_DMA_DMA_TXPOLL                   ((volatile u32*)(INCA_IP_DMA+ 0x08C4))
+#define INCA_IP_DMA_DMA_TXPOLL_BSZ2 (value)               (((( 1 << 2) - 1) & (value)) << 30)
+#define INCA_IP_DMA_DMA_TXPOLL_BSZ1 (value)               (((( 1 << 2) - 1) & (value)) << 28)
+#define INCA_IP_DMA_DMA_TXPOLL_BSZ0 (value)               (((( 1 << 2) - 1) & (value)) << 26)
+#define INCA_IP_DMA_DMA_TXPOLL_TXPOLLTIME (value)         (((( 1 << 8) - 1) & (value)) << 0)
+
+/***DMA Transmit Interrupt Status Register***/
+#define INCA_IP_DMA_DMA_TXISR                    ((volatile u32*)(INCA_IP_DMA+ 0x08C8))
+#define INCA_IP_DMA_DMA_TXISR_RDERRx (value)             (((( 1 << 3) - 1) & (value)) << 12)
+#define INCA_IP_DMA_DMA_TXISR_HLDx (value)               (((( 1 << 3) - 1) & (value)) << 9)
+#define INCA_IP_DMA_DMA_TXISR_CPTx (value)               (((( 1 << 3) - 1) & (value)) << 6)
+#define INCA_IP_DMA_DMA_TXISR_EOPx (value)               (((( 1 << 3) - 1) & (value)) << 3)
+#define INCA_IP_DMA_DMA_TXISR_CMDCPTx (value)            (((( 1 << 3) - 1) & (value)) << 0)
+
+/***DMA Transmit Interrupt Mask Register***/
+#define INCA_IP_DMA_DMA_TXIMR                    ((volatile u32*)(INCA_IP_DMA+ 0x08CC))
+#define INCA_IP_DMA_DMA_TXIMR_RDERRx (value)             (((( 1 << 3) - 1) & (value)) << 12)
+#define INCA_IP_DMA_DMA_TXIMR_HLDx (value)               (((( 1 << 3) - 1) & (value)) << 9)
+#define INCA_IP_DMA_DMA_TXIMR_CPTx (value)               (((( 1 << 3) - 1) & (value)) << 6)
+#define INCA_IP_DMA_DMA_TXIMR_EOPx (value)               (((( 1 << 3) - 1) & (value)) << 3)
+#define INCA_IP_DMA_DMA_TXIMR_CMDCPTx (value)            (((( 1 << 3) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/*  Module      :  Debug register address and bits                     */
+/***********************************************************************/
+
+#define INCA_IP_Debug                        (0xBF106000)
+/***********************************************************************/
+
+
+/***MCD Break Bus Switch Register***/
+#define INCA_IP_Debug_MCD_BBS                      ((volatile u32*)(INCA_IP_Debug+ 0x0000))
+#define INCA_IP_Debug_MCD_BBS_BTP1                            (1 << 19)
+#define INCA_IP_Debug_MCD_BBS_BTP0                            (1 << 18)
+#define INCA_IP_Debug_MCD_BBS_BSP1                            (1 << 17)
+#define INCA_IP_Debug_MCD_BBS_BSP0                            (1 << 16)
+#define INCA_IP_Debug_MCD_BBS_BT5EN                          (1 << 15)
+#define INCA_IP_Debug_MCD_BBS_BT4EN                          (1 << 14)
+#define INCA_IP_Debug_MCD_BBS_BT5                              (1 << 13)
+#define INCA_IP_Debug_MCD_BBS_BT4                              (1 << 12)
+#define INCA_IP_Debug_MCD_BBS_BS5EN                          (1 << 7)
+#define INCA_IP_Debug_MCD_BBS_BS4EN                          (1 << 6)
+#define INCA_IP_Debug_MCD_BBS_BS5                              (1 << 5)
+#define INCA_IP_Debug_MCD_BBS_BS4                              (1 << 4)
+
+/***MCD Multiplexer Control Register***/
+#define INCA_IP_Debug_MCD_MCR                      ((volatile u32*)(INCA_IP_Debug+ 0x0008))
+#define INCA_IP_Debug_MCD_MCR_MUX5                            (1 << 4)
+#define INCA_IP_Debug_MCD_MCR_MUX4                            (1 << 3)
+#define INCA_IP_Debug_MCD_MCR_MUX1                            (1 << 0)
+
+/***********************************************************************/
+/*  Module      :  TSF register address and bits                       */
+/***********************************************************************/
+
+#define INCA_IP_TSF                          (0xB8000900)
+/***********************************************************************/
+
+
+/***TSF Configuration Register (0000H)***/
+#define INCA_IP_TSF_TSF_CONF                    ((volatile u32*)(INCA_IP_TSF+ 0x0000))
+#define INCA_IP_TSF_TSF_CONF_PWMEN                          (1 << 2)
+#define INCA_IP_TSF_TSF_CONF_LEDEN                          (1 << 1)
+#define INCA_IP_TSF_TSF_CONF_KEYEN                          (1 << 0)
+
+/***Key scan Configuration Register (0004H)***/
+#define INCA_IP_TSF_KEY_CONF                    ((volatile u32*)(INCA_IP_TSF+ 0x0004))
+#define INCA_IP_TSF_KEY_CONF_SL (value)                (((( 1 << 4) - 1) & (value)) << 0)
+
+/***Scan Register Line 0 and 1 (0008H)***/
+#define INCA_IP_TSF_SREG01                       ((volatile u32*)(INCA_IP_TSF+ 0x0008))
+#define INCA_IP_TSF_SREG01_RES1x (value)              (((( 1 << 12) - 1) & (value)) << 16)
+#define INCA_IP_TSF_SREG01_RES0x (value)              (((( 1 << 13) - 1) & (value)) << 0)
+
+/***Scan Register Line 2 and 3 (000CH)***/
+#define INCA_IP_TSF_SREG23                       ((volatile u32*)(INCA_IP_TSF+ 0x000C))
+#define INCA_IP_TSF_SREG23_RES3x (value)              (((( 1 << 10) - 1) & (value)) << 16)
+#define INCA_IP_TSF_SREG23_RES2x (value)              (((( 1 << 11) - 1) & (value)) << 0)
+
+/***Scan Register Line 4, 5 and 6 (0010H)***/
+#define INCA_IP_TSF_SREG456                      ((volatile u32*)(INCA_IP_TSF+ 0x0010))
+#define INCA_IP_TSF_SREG456_RES6x (value)              (((( 1 << 7) - 1) & (value)) << 24)
+#define INCA_IP_TSF_SREG456_RES5x (value)              (((( 1 << 8) - 1) & (value)) << 16)
+#define INCA_IP_TSF_SREG456_RES4x (value)              (((( 1 << 9) - 1) & (value)) << 0)
+
+/***Scan Register Line 7 to 12 (0014H)***/
+#define INCA_IP_TSF_SREG7to12                    ((volatile u32*)(INCA_IP_TSF+ 0x0014))
+#define INCA_IP_TSF_SREG7to12_RES12x                        (1 << 28)
+#define INCA_IP_TSF_SREG7to12_RES11x (value)             (((( 1 << 2) - 1) & (value)) << 24)
+#define INCA_IP_TSF_SREG7to12_RES10x (value)             (((( 1 << 3) - 1) & (value)) << 20)
+#define INCA_IP_TSF_SREG7to12_RES9x (value)              (((( 1 << 4) - 1) & (value)) << 16)
+#define INCA_IP_TSF_SREG7to12_RES8x (value)              (((( 1 << 5) - 1) & (value)) << 8)
+#define INCA_IP_TSF_SREG7to12_RES7x (value)              (((( 1 << 6) - 1) & (value)) << 0)
+
+/***LEDMUX Configuration Register (0018H)***/
+#define INCA_IP_TSF_LEDMUX_CONF                  ((volatile u32*)(INCA_IP_TSF+ 0x0018))
+#define INCA_IP_TSF_LEDMUX_CONF_ETL1                            (1 << 25)
+#define INCA_IP_TSF_LEDMUX_CONF_ESTA1                          (1 << 24)
+#define INCA_IP_TSF_LEDMUX_CONF_EDPX1                          (1 << 23)
+#define INCA_IP_TSF_LEDMUX_CONF_EACT1                          (1 << 22)
+#define INCA_IP_TSF_LEDMUX_CONF_ESPD1                          (1 << 21)
+#define INCA_IP_TSF_LEDMUX_CONF_ETL0                            (1 << 20)
+#define INCA_IP_TSF_LEDMUX_CONF_ESTA0                          (1 << 19)
+#define INCA_IP_TSF_LEDMUX_CONF_EDPX0                          (1 << 18)
+#define INCA_IP_TSF_LEDMUX_CONF_EACT0                          (1 << 17)
+#define INCA_IP_TSF_LEDMUX_CONF_ESPD0                          (1 << 16)
+#define INCA_IP_TSF_LEDMUX_CONF_INV                              (1 << 1)
+#define INCA_IP_TSF_LEDMUX_CONF_NCOL                            (1 << 0)
+
+/***LED Register (001CH)***/
+#define INCA_IP_TSF_LED_REG                      ((volatile u32*)(INCA_IP_TSF+ 0x001C))
+#define INCA_IP_TSF_LED_REG_Lxy (value)                (((( 1 << 24) - 1) & (value)) << 0)
+
+/***Pulse Width Modulator 1 and 2 Register (0020H)***/
+#define INCA_IP_TSF_PWM12                        ((volatile u32*)(INCA_IP_TSF+ 0x0020))
+#define INCA_IP_TSF_PWM12_PW2PW1 (value)             (((( 1 << NaN) - 1) & (value)) << NaN)
+
+/***********************************************************************/
+/*  Module      :  Ports register address and bits                     */
+/***********************************************************************/
+
+#define INCA_IP_Ports                        (0xB8000A00)
+/***********************************************************************/
+
+
+/***Port 1 Data Output Register (0020H)***/
+#define INCA_IP_Ports_P1_OUT                       ((volatile u32*)(INCA_IP_Ports+ 0x0020))
+#define INCA_IP_Ports_P1_OUT_P(value)               (1 << value)
+
+
+/***Port 2 Data Output Register (0040H)***/
+#define INCA_IP_Ports_P2_OUT                       ((volatile u32*)(INCA_IP_Ports+ 0x0040))
+#define INCA_IP_Ports_P2_OUT_P(value)               (1 << value)
+
+
+/***Port 1 Data Input Register (0024H)***/
+#define INCA_IP_Ports_P1_IN                        ((volatile u32*)(INCA_IP_Ports+ 0x0024))
+#define INCA_IP_Ports_P1_IN_P(value)               (1 << value)
+
+
+/***Port 2 Data Input Register (0044H)***/
+#define INCA_IP_Ports_P2_IN                        ((volatile u32*)(INCA_IP_Ports+ 0x0044))
+#define INCA_IP_Ports_P2_IN_P(value)               (1 << value)
+
+
+/***Port 1 Direction Register (0028H)***/
+#define INCA_IP_Ports_P1_DIR                       ((volatile u32*)(INCA_IP_Ports+ 0x0028))
+#define INCA_IP_Ports_P1_DIR_Port1P(value)         (1 << value)
+
+#define INCA_IP_Ports_P1_DIR_Port2Pn (value)          (((( 1 << 16) - 1) & (value)) << 0)
+
+/***Port 2 Direction Register (0048H)***/
+#define INCA_IP_Ports_P2_DIR                       ((volatile u32*)(INCA_IP_Ports+ 0x0048))
+#define INCA_IP_Ports_P2_DIR_Port1P(value)         (1 << value)
+
+#define INCA_IP_Ports_P2_DIR_Port2Pn (value)          (((( 1 << 16) - 1) & (value)) << 0)
+
+/***Port 0 Alternate Function Select Register 0 (000C H)
+***/
+#define INCA_IP_Ports_P0_ALTSEL                    ((volatile u32*)(INCA_IP_Ports+ 0x000C))
+#define INCA_IP_Ports_P0_ALTSEL_Port0P(value)         (1 << value)
+
+
+/***Port 1 Alternate Function Select Register 0 (002C H)
+***/
+#define INCA_IP_Ports_P1_ALTSEL                    ((volatile u32*)(INCA_IP_Ports+ 0x002C))
+#define INCA_IP_Ports_P1_ALTSEL_Port1P(value)         (1 << value)
+
+#define INCA_IP_Ports_P1_ALTSEL_Port2P(value)         (1 << value)
+
+
+/***Port 2 Alternate Function Select Register 0 (004C H)
+***/
+#define INCA_IP_Ports_P2_ALTSEL                    ((volatile u32*)(INCA_IP_Ports+ 0x004C))
+#define INCA_IP_Ports_P2_ALTSEL_Port1P(value)         (1 << value)
+
+#define INCA_IP_Ports_P2_ALTSEL_Port2P(value)         (1 << value)
+
+
+/***Port 0 Input Schmitt-Trigger Off Register (0010 H)
+***/
+#define INCA_IP_Ports_P0_STOFF                    ((volatile u32*)(INCA_IP_Ports+ 0x0010))
+#define INCA_IP_Ports_P0_STOFF_Port0P(value)         (1 << value)
+
+
+/***Port 1 Input Schmitt-Trigger Off Register (0030 H)
+***/
+#define INCA_IP_Ports_P1_STOFF                    ((volatile u32*)(INCA_IP_Ports+ 0x0030))
+#define INCA_IP_Ports_P1_STOFF_Port1P(value)         (1 << value)
+
+#define INCA_IP_Ports_P1_STOFF_Port2P(value)         (1 << value)
+
+
+/***Port 2 Input Schmitt-Trigger Off Register (0050 H)
+***/
+#define INCA_IP_Ports_P2_STOFF                    ((volatile u32*)(INCA_IP_Ports+ 0x0050))
+#define INCA_IP_Ports_P2_STOFF_Port1P(value)         (1 << value)
+
+#define INCA_IP_Ports_P2_STOFF_Port2P(value)         (1 << value)
+
+
+/***Port 2 Open Drain Control Register (0054H)***/
+#define INCA_IP_Ports_P2_OD                        ((volatile u32*)(INCA_IP_Ports+ 0x0054))
+#define INCA_IP_Ports_P2_OD_Port2P(value)         (1 << value)
+
+
+/***Port 0 Pull Up Device Enable Register (0018 H)***/
+#define INCA_IP_Ports_P0_PUDEN                    ((volatile u32*)(INCA_IP_Ports+ 0x0018))
+#define INCA_IP_Ports_P0_PUDEN_Port0P(value)         (1 << value)
+
+
+/***Port 2 Pull Up Device Enable Register (0058 H)***/
+#define INCA_IP_Ports_P2_PUDEN                    ((volatile u32*)(INCA_IP_Ports+ 0x0058))
+#define INCA_IP_Ports_P2_PUDEN_Port2P(value)         (1 << value)
+
+#define INCA_IP_Ports_P2_PUDEN_Port2P(value)         (1 << value)
+
+
+/***Port 0 Pull Up/Pull Down Select Register (001C H)***/
+#define INCA_IP_Ports_P0_PUDSEL                    ((volatile u32*)(INCA_IP_Ports+ 0x001C))
+#define INCA_IP_Ports_P0_PUDSEL_Port0P(value)         (1 << value)
+
+
+/***Port 2 Pull Up/Pull Down Select Register (005C H)***/
+#define INCA_IP_Ports_P2_PUDSEL                    ((volatile u32*)(INCA_IP_Ports+ 0x005C))
+#define INCA_IP_Ports_P2_PUDSEL_Port2P(value)         (1 << value)
+
+#define INCA_IP_Ports_P2_PUDSEL_Port2P(value)         (1 << value)
+
+
+/***********************************************************************/
+/*  Module      :  DES/3DES register address and bits                 */
+/***********************************************************************/
+
+#define INCA_IP_DES_3DES                    (0xB8000800)
+/***********************************************************************/
+
+
+/***DES Input Data High Register***/
+#define INCA_IP_DES_3DES_DES_IHR                      ((volatile u32*)(INCA_IP_DES_3DES+ 0x0000))
+#define INCA_IP_DES_3DES_DES_IHR_IH(value)               (1 << value)
+
+
+/***DES Input Data Low Register***/
+#define INCA_IP_DES_3DES_DES_ILR                      ((volatile u32*)(INCA_IP_DES_3DES+ 0x0004))
+#define INCA_IP_DES_3DES_DES_ILR_IL(value)               (1 << value)
+
+
+/***DES Key #1 High Register***/
+#define INCA_IP_DES_3DES_DES_K1HR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x0008))
+#define INCA_IP_DES_3DES_DES_K1HR_K1H(value)              (1 << value)
+
+
+/***DES Key #1 Low Register***/
+#define INCA_IP_DES_3DES_DES_K1LR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x000C))
+#define INCA_IP_DES_3DES_DES_K1LR_K1L(value)              (1 << value)
+
+
+/***DES Key #2 High Register***/
+#define INCA_IP_DES_3DES_DES_K2HR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x0010))
+#define INCA_IP_DES_3DES_DES_K2HR_K2H(value)              (1 << value)
+
+
+/***DES Key #2 Low Register***/
+#define INCA_IP_DES_3DES_DES_K2LR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x0014))
+#define INCA_IP_DES_3DES_DES_K2LR_K2L(value)              (1 << value)
+
+
+/***DES Key #3 High Register***/
+#define INCA_IP_DES_3DES_DES_K3HR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x0018))
+#define INCA_IP_DES_3DES_DES_K3HR_K3H(value)              (1 << value)
+
+
+/***DES Key #3 Low Register***/
+#define INCA_IP_DES_3DES_DES_K3LR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x001C))
+#define INCA_IP_DES_3DES_DES_K3LR_K3L(value)              (1 << value)
+
+
+/***DES Initialization Vector High Register***/
+#define INCA_IP_DES_3DES_DES_IVHR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x0020))
+#define INCA_IP_DES_3DES_DES_IVHR_IVH(value)              (1 << value)
+
+
+/***DES Initialization Vector Low Register***/
+#define INCA_IP_DES_3DES_DES_IVLR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x0024))
+#define INCA_IP_DES_3DES_DES_IVLR_IVL(value)              (1 << value)
+
+
+/***DES Control Register***/
+#define INCA_IP_DES_3DES_DES_CONTROLR                 ((volatile u32*)(INCA_IP_DES_3DES+ 0x0028))
+#define INCA_IP_DES_3DES_DES_CONTROLR_KRE                              (1 << 31)
+#define INCA_IP_DES_3DES_DES_CONTROLR_DAU                              (1 << 16)
+#define INCA_IP_DES_3DES_DES_CONTROLR_F(value)               (1 << value)
+
+#define INCA_IP_DES_3DES_DES_CONTROLR_O(value)               (1 << value)
+
+#define INCA_IP_DES_3DES_DES_CONTROLR_GO                              (1 << 8)
+#define INCA_IP_DES_3DES_DES_CONTROLR_STP                              (1 << 7)
+#define INCA_IP_DES_3DES_DES_CONTROLR_IEN                              (1 << 6)
+#define INCA_IP_DES_3DES_DES_CONTROLR_BUS                              (1 << 5)
+#define INCA_IP_DES_3DES_DES_CONTROLR_SM                              (1 << 4)
+#define INCA_IP_DES_3DES_DES_CONTROLR_E_D                              (1 << 3)
+#define INCA_IP_DES_3DES_DES_CONTROLR_M(value)               (1 << value)
+
+
+/***DES Output Data High Register***/
+#define INCA_IP_DES_3DES_DES_OHR                      ((volatile u32*)(INCA_IP_DES_3DES+ 0x002C))
+#define INCA_IP_DES_3DES_DES_OHR_OH(value)               (1 << value)
+
+
+/***DES Output Data Low Register***/
+#define INCA_IP_DES_3DES_DES_OLR                      ((volatile u32*)(INCA_IP_DES_3DES+ 0x0030))
+#define INCA_IP_DES_3DES_DES_OLR_OL(value)               (1 << value)
+
+
+/***********************************************************************/
+/*  Module      :  AES register address and bits                       */
+/***********************************************************************/
+
+#define INCA_IP_AES                          (0xB8000880)
+/***********************************************************************/
+
+
+/***AES Input Data 3 Register***/
+#define INCA_IP_AES_AES_ID3R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_ID3R_I(value)               (1 << value)
+
+
+/***AES Input Data 2 Register***/
+#define INCA_IP_AES_AES_ID2R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_ID2R_I(value)               (1 << value)
+
+
+/***AES Input Data 1 Register***/
+#define INCA_IP_AES_AES_ID1R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_ID1R_I(value)               (1 << value)
+
+
+/***AES Input Data 0 Register***/
+#define INCA_IP_AES_AES_ID0R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_ID0R_I(value)               (1 << value)
+
+
+/***AES Output Data 3 Register***/
+#define INCA_IP_AES_AES_OD3R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_OD3R_O(value)               (1 << value)
+
+
+/***AES Output Data 2 Register***/
+#define INCA_IP_AES_AES_OD2R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_OD2R_O(value)               (1 << value)
+
+
+/***AES Output Data 1 Register***/
+#define INCA_IP_AES_AES_OD1R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_OD1R_O(value)               (1 << value)
+
+
+/***AES Output Data 0 Register***/
+#define INCA_IP_AES_AES_OD0R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_OD0R_O(value)               (1 << value)
+
+
+/***AES Key 7 Register***/
+#define INCA_IP_AES_AES_K7R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_K7R_K(value)               (1 << value)
+
+
+/***AES Key 6 Register***/
+#define INCA_IP_AES_AES_K6R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_K6R_K(value)               (1 << value)
+
+
+/***AES Key 5 Register***/
+#define INCA_IP_AES_AES_K5R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_K5R_K(value)               (1 << value)
+
+
+/***AES Key 4 Register***/
+#define INCA_IP_AES_AES_K4R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_K4R_K(value)               (1 << value)
+
+
+/***AES Key 3 Register***/
+#define INCA_IP_AES_AES_K3R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_K3R_K(value)               (1 << value)
+
+
+/***AES Key 2 Register***/
+#define INCA_IP_AES_AES_K2R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_K2R_K(value)               (1 << value)
+
+
+/***AES Key 1 Register***/
+#define INCA_IP_AES_AES_K1R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_K1R_K(value)               (1 << value)
+
+
+/***AES Key 0 Register***/
+#define INCA_IP_AES_AES_K0R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_K0R_K(value)               (1 << value)
+
+
+/***AES Initialization Vector 3 Register***/
+#define INCA_IP_AES_AES_IV3R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_IV3R_IV(value)               (1 << value)
+
+
+/***AES Initialization Vector 2 Register***/
+#define INCA_IP_AES_AES_IV2R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_IV2R_IV(value)               (1 << value)
+
+
+/***AES Initialization Vector 1 Register***/
+#define INCA_IP_AES_AES_IV1R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_IV1R_IV(value)               (1 << value)
+
+
+/***AES Initialization Vector 0 Register***/
+#define INCA_IP_AES_AES_IV0R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_IV0R_IV (value)                (((( 1 << 32) - 1) &(value)) << 0)
+
+/***AES Control Register***/
+#define INCA_IP_AES_AES_CONTROLR                 ((volatile u32*)(INCA_IP_AES+ 0x0000))
+#define INCA_IP_AES_AES_CONTROLR_KRE                              (1 << 31)
+#define INCA_IP_AES_AES_CONTROLR_DAU                              (1 << 16)
+#define INCA_IP_AES_AES_CONTROLR_PNK                              (1 << 15)
+#define INCA_IP_AES_AES_CONTROLR_F(value)               (1 << value)
+
+#define INCA_IP_AES_AES_CONTROLR_O(value)               (1 << value)
+
+#define INCA_IP_AES_AES_CONTROLR_GO                              (1 << 8)
+#define INCA_IP_AES_AES_CONTROLR_STP                              (1 << 7)
+#define INCA_IP_AES_AES_CONTROLR_IEN                              (1 << 6)
+#define INCA_IP_AES_AES_CONTROLR_BUS                              (1 << 5)
+#define INCA_IP_AES_AES_CONTROLR_SM                              (1 << 4)
+#define INCA_IP_AES_AES_CONTROLR_E_D                              (1 << 3)
+#define INCA_IP_AES_AES_CONTROLR_KV                              (1 << 2)
+#define INCA_IP_AES_AES_CONTROLR_K(value)               (1 << value)
+
+
+/***********************************************************************/
+/*  Module      :  I²C register address and bits                       */
+/***********************************************************************/
+
+#define INCA_IP_IIC                          (0xB8000700)
+/***********************************************************************/
+
+
+/***I²C Port Input Select Register***/
+#define INCA_IP_IIC_IIC_PISEL                    ((volatile u32*)(INCA_IP_IIC+ 0x0004))
+#define INCA_IP_IIC_IIC_PISEL_SDAIS(value)            (1 << value)
+
+#define INCA_IP_IIC_IIC_PISEL_SCLIS(value)            (1 << value)
+
+
+/***I²C Clock Control Register***/
+#define INCA_IP_IIC_IIC_CLC                      ((volatile u32*)(INCA_IP_IIC+ 0x0000))
+#define INCA_IP_IIC_IIC_CLC_RMC (value)                (((( 1 << 8) - 1) & (value)) << 8)
+#define INCA_IP_IIC_IIC_CLC_DISS                            (1 << 1)
+#define INCA_IP_IIC_IIC_CLC_DISR                            (1 << 0)
+
+/***I²C System Control Register***/
+#define INCA_IP_IIC_IIC_SYSCON_0                 ((volatile u32*)(INCA_IP_IIC+ 0x0010))
+#define INCA_IP_IIC_IIC_SYSCON_0_WMEN                            (1 << 31)
+#define INCA_IP_IIC_IIC_SYSCON_0_CI (value)                (((( 1 << 2) - 1) & (value)) << 26)
+#define INCA_IP_IIC_IIC_SYSCON_0_STP                              (1 << 25)
+#define INCA_IP_IIC_IIC_SYSCON_0_IGE                              (1 << 24)
+#define INCA_IP_IIC_IIC_SYSCON_0_TRX                              (1 << 23)
+#define INCA_IP_IIC_IIC_SYSCON_0_INT                              (1 << 22)
+#define INCA_IP_IIC_IIC_SYSCON_0_ACKDIS                        (1 << 21)
+#define INCA_IP_IIC_IIC_SYSCON_0_BUM                              (1 << 20)
+#define INCA_IP_IIC_IIC_SYSCON_0_MOD (value)                (((( 1 << 2) - 1) & (value)) << 18)
+#define INCA_IP_IIC_IIC_SYSCON_0_RSC                              (1 << 17)
+#define INCA_IP_IIC_IIC_SYSCON_0_M10                              (1 << 16)
+#define INCA_IP_IIC_IIC_SYSCON_0_RMEN                            (1 << 15)
+#define INCA_IP_IIC_IIC_SYSCON_0_CO (value)                (((( 1 << 3) - 1) & (value)) << 8)
+#define INCA_IP_IIC_IIC_SYSCON_0_IRQE                            (1 << 7)
+#define INCA_IP_IIC_IIC_SYSCON_0_IRQP                            (1 << 6)
+#define INCA_IP_IIC_IIC_SYSCON_0_IRQD                            (1 << 5)
+#define INCA_IP_IIC_IIC_SYSCON_0_BB                              (1 << 4)
+#define INCA_IP_IIC_IIC_SYSCON_0_LRB                              (1 << 3)
+#define INCA_IP_IIC_IIC_SYSCON_0_SLA                              (1 << 2)
+#define INCA_IP_IIC_IIC_SYSCON_0_AL                              (1 << 1)
+#define INCA_IP_IIC_IIC_SYSCON_0_ADR                              (1 << 0)
+
+/***I²C System Control Register***/
+#define INCA_IP_IIC_IIC_SYSCON_1                 ((volatile u32*)(INCA_IP_IIC+ 0x0010))
+#define INCA_IP_IIC_IIC_SYSCON_1_RM (value)                (((( 1 << 8) - 1) & (value)) << 24)
+#define INCA_IP_IIC_IIC_SYSCON_1_TRX                              (1 << 23)
+#define INCA_IP_IIC_IIC_SYSCON_1_INT                              (1 << 22)
+#define INCA_IP_IIC_IIC_SYSCON_1_ACKDIS                        (1 << 21)
+#define INCA_IP_IIC_IIC_SYSCON_1_BUM                              (1 << 20)
+#define INCA_IP_IIC_IIC_SYSCON_1_MOD (value)                (((( 1 << 2) - 1) & (value)) << 18)
+#define INCA_IP_IIC_IIC_SYSCON_1_RSC                              (1 << 17)
+#define INCA_IP_IIC_IIC_SYSCON_1_M10                              (1 << 16)
+#define INCA_IP_IIC_IIC_SYSCON_1_RMEN                            (1 << 15)
+#define INCA_IP_IIC_IIC_SYSCON_1_CO (value)                (((( 1 << 3) - 1) & (value)) << 8)
+#define INCA_IP_IIC_IIC_SYSCON_1_IRQE                            (1 << 7)
+#define INCA_IP_IIC_IIC_SYSCON_1_IRQP                            (1 << 6)
+#define INCA_IP_IIC_IIC_SYSCON_1_IRQD                            (1 << 5)
+#define INCA_IP_IIC_IIC_SYSCON_1_BB                              (1 << 4)
+#define INCA_IP_IIC_IIC_SYSCON_1_LRB                              (1 << 3)
+#define INCA_IP_IIC_IIC_SYSCON_1_SLA                              (1 << 2)
+#define INCA_IP_IIC_IIC_SYSCON_1_AL                              (1 << 1)
+#define INCA_IP_IIC_IIC_SYSCON_1_ADR                              (1 << 0)
+
+/***I²C System Control Register***/
+#define INCA_IP_IIC_IIC_SYSCON_2                 ((volatile u32*)(INCA_IP_IIC+ 0x0010))
+#define INCA_IP_IIC_IIC_SYSCON_2_WMEN                            (1 << 31)
+#define INCA_IP_IIC_IIC_SYSCON_2_CI (value)                (((( 1 << 2) - 1) & (value)) << 26)
+#define INCA_IP_IIC_IIC_SYSCON_2_STP                              (1 << 25)
+#define INCA_IP_IIC_IIC_SYSCON_2_IGE                              (1 << 24)
+#define INCA_IP_IIC_IIC_SYSCON_2_TRX                              (1 << 23)
+#define INCA_IP_IIC_IIC_SYSCON_2_INT                              (1 << 22)
+#define INCA_IP_IIC_IIC_SYSCON_2_ACKDIS                        (1 << 21)
+#define INCA_IP_IIC_IIC_SYSCON_2_BUM                              (1 << 20)
+#define INCA_IP_IIC_IIC_SYSCON_2_MOD (value)                (((( 1 << 2) - 1) & (value)) << 18)
+#define INCA_IP_IIC_IIC_SYSCON_2_RSC                              (1 << 17)
+#define INCA_IP_IIC_IIC_SYSCON_2_M10                              (1 << 16)
+#define INCA_IP_IIC_IIC_SYSCON_2_WM (value)                (((( 1 << 8) - 1) & (value)) << 8)
+#define INCA_IP_IIC_IIC_SYSCON_2_IRQE                            (1 << 7)
+#define INCA_IP_IIC_IIC_SYSCON_2_IRQP                            (1 << 6)
+#define INCA_IP_IIC_IIC_SYSCON_2_IRQD                            (1 << 5)
+#define INCA_IP_IIC_IIC_SYSCON_2_BB                              (1 << 4)
+#define INCA_IP_IIC_IIC_SYSCON_2_LRB                              (1 << 3)
+#define INCA_IP_IIC_IIC_SYSCON_2_SLA                              (1 << 2)
+#define INCA_IP_IIC_IIC_SYSCON_2_AL                              (1 << 1)
+#define INCA_IP_IIC_IIC_SYSCON_2_ADR                              (1 << 0)
+
+/***I²C Write Hardware Modified System Control Register
+***/
+#define INCA_IP_IIC_IIC_WHBSYSCON                 ((volatile u32*)(INCA_IP_IIC+ 0x0020))
+#define INCA_IP_IIC_IIC_WHBSYSCON_CLRWMEN                      (1 << 31)
+#define INCA_IP_IIC_IIC_WHBSYSCON_SETWMEN                      (1 << 30)
+#define INCA_IP_IIC_IIC_WHBSYSCON_SETSTP                        (1 << 26)
+#define INCA_IP_IIC_IIC_WHBSYSCON_CLRSTP                        (1 << 25)
+#define INCA_IP_IIC_IIC_WHBSYSCON_SETTRX                        (1 << 24)
+#define INCA_IP_IIC_IIC_WHBSYSCON_CLRTRX                        (1 << 23)
+#define INCA_IP_IIC_IIC_WHBSYSCON_SETACKDIS                  (1 << 22)
+#define INCA_IP_IIC_IIC_WHBSYSCON_CLRACKDIS                  (1 << 21)
+#define INCA_IP_IIC_IIC_WHBSYSCON_SETBUM                        (1 << 20)
+#define INCA_IP_IIC_IIC_WHBSYSCON_CLRBUM                        (1 << 19)
+#define INCA_IP_IIC_IIC_WHBSYSCON_SETRSC                        (1 << 17)
+#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRSC                        (1 << 16)
+#define INCA_IP_IIC_IIC_WHBSYSCON_SETRMEN                      (1 << 15)
+#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRMEN                      (1 << 14)
+#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQE                      (1 << 10)
+#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQP                      (1 << 9)
+#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQD                      (1 << 8)
+#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQE                      (1 << 7)
+#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQP                      (1 << 6)
+#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQD                      (1 << 5)
+#define INCA_IP_IIC_IIC_WHBSYSCON_SETAL                          (1 << 2)
+#define INCA_IP_IIC_IIC_WHBSYSCON_CLRAL                          (1 << 1)
+
+/***I²C Bus Control Register***/
+#define INCA_IP_IIC_IIC_BUSCON_0                 ((volatile u32*)(INCA_IP_IIC+ 0x0014))
+#define INCA_IP_IIC_IIC_BUSCON_0_BRPMOD                        (1 << 31)
+#define INCA_IP_IIC_IIC_BUSCON_0_PREDIV (value)             (((( 1 << 2) - 1) & (value)) << 29)
+#define INCA_IP_IIC_IIC_BUSCON_0_ICA9_0 (value)             (((( 1 << 10) - 1) & (value)) << 16)
+#define INCA_IP_IIC_IIC_BUSCON_0_BRP (value)                (((( 1 << 8) - 1) & (value)) << 8)
+#define INCA_IP_IIC_IIC_BUSCON_0_SCLEN(value)            (1 << value)
+
+#define INCA_IP_IIC_IIC_BUSCON_0_SDAEN(value)            (1 << value)
+
+
+/***I²C Bus Control Register***/
+#define INCA_IP_IIC_IIC_BUSCON_1                 ((volatile u32*)(INCA_IP_IIC+ 0x0014))
+#define INCA_IP_IIC_IIC_BUSCON_1_BRPMOD                        (1 << 31)
+#define INCA_IP_IIC_IIC_BUSCON_1_PREDIV (value)             (((( 1 << 2) - 1) & (value)) << 29)
+#define INCA_IP_IIC_IIC_BUSCON_1_ICA7_1 (value)             (((( 1 << 7) - 1) & (value)) << 17)
+#define INCA_IP_IIC_IIC_BUSCON_1_BRP (value)                (((( 1 << 8) - 1) & (value)) << 8)
+#define INCA_IP_IIC_IIC_BUSCON_1_SCLEN(value)            (1 << value)
+
+#define INCA_IP_IIC_IIC_BUSCON_1_SDAEN(value)            (1 << value)
+
+
+/***I²C Receive Transmit Buffer***/
+#define INCA_IP_IIC_IIC_RTB                      ((volatile u32*)(INCA_IP_IIC+ 0x0018))
+#define INCA_IP_IIC_IIC_RTB_RTB(value)              (1 << value)
+
+
+/***********************************************************************/
+/*  Module      :  FB register address and bits                       */
+/***********************************************************************/
+
+#define INCA_IP_FB                          (0xBF880000)
+/***********************************************************************/
+
+
+/***FB Access Error Cause Register***/
+#define INCA_IP_FB_FB_ERRCAUSE                  ((volatile u32*)(INCA_IP_FB+ 0x0100))
+#define INCA_IP_FB_FB_ERRCAUSE_ERR                              (1 << 31)
+#define INCA_IP_FB_FB_ERRCAUSE_PORT (value)               (((( 1 << 4) - 1) & (value)) << 16)
+#define INCA_IP_FB_FB_ERRCAUSE_CAUSE (value)              (((( 1 << 2) - 1) & (value)) << 0)
+
+/***FB Access Error Address Register***/
+#define INCA_IP_FB_FB_ERRADDR                   ((volatile u32*)(INCA_IP_FB+ 0x0108))
+#define INCA_IP_FB_FB_ERRADDR_ADDR
+
+/***FB Configuration Register***/
+#define INCA_IP_FB_FB_CFG                       ((volatile u32*)(INCA_IP_FB+ 0x0800))
+#define INCA_IP_FB_FB_CFG_SVM                              (1 << 0)
+
+/***********************************************************************/
+/*  Module      :  SRAM register address and bits                      */
+/***********************************************************************/
+
+#define INCA_IP_SRAM                         (0xBF980000)
+/***********************************************************************/
+
+
+/***SRAM Size Register***/
+#define INCA_IP_SRAM_SRAM_SIZE                    ((volatile u32*)(INCA_IP_SRAM+ 0x0800))
+#define INCA_IP_SRAM_SRAM_SIZE_SIZE (value)               (((( 1 << 23) - 1) & (value)) << 0)
+
+/***********************************************************************/
+/*  Module      :  BIU register address and bits                       */
+/***********************************************************************/
+
+#define INCA_IP_BIU                          (0xBFA80000)
+/***********************************************************************/
+
+
+/***BIU Identification Register***/
+#define INCA_IP_BIU_BIU_ID                       ((volatile u32*)(INCA_IP_BIU+ 0x0000))
+#define INCA_IP_BIU_BIU_ID_ARCH                            (1 << 16)
+#define INCA_IP_BIU_BIU_ID_ID (value)                (((( 1 << 8) - 1) & (value)) << 8)
+#define INCA_IP_BIU_BIU_ID_REV (value)                (((( 1 << 8) - 1) & (value)) << 0)
+
+/***BIU Access Error Cause Register***/
+#define INCA_IP_BIU_BIU_ERRCAUSE                 ((volatile u32*)(INCA_IP_BIU+ 0x0100))
+#define INCA_IP_BIU_BIU_ERRCAUSE_ERR                              (1 << 31)
+#define INCA_IP_BIU_BIU_ERRCAUSE_PORT (value)               (((( 1 << 4) - 1) & (value)) << 16)
+#define INCA_IP_BIU_BIU_ERRCAUSE_CAUSE (value)              (((( 1 << 2) - 1) & (value)) << 0)
+
+/***BIU Access Error Address Register***/
+#define INCA_IP_BIU_BIU_ERRADDR                  ((volatile u32*)(INCA_IP_BIU+ 0x0108))
+#define INCA_IP_BIU_BIU_ERRADDR_ADDR
+
+/***********************************************************************/
+/*  Module      :  ICU register address and bits                       */
+/***********************************************************************/
+
+#define INCA_IP_ICU                          (0xBF101000)
+/***********************************************************************/
+
+
+/***IM0 Interrupt Status Register***/
+#define INCA_IP_ICU_IM0_ISR                      ((volatile u32*)(INCA_IP_ICU+ 0x0000))
+#define INCA_IP_ICU_IM0_ISR_IR(value)               (1 << value)
+
+
+/***IM1 Interrupt Status Register***/
+#define INCA_IP_ICU_IM1_ISR                      ((volatile u32*)(INCA_IP_ICU+ 0x0200))
+#define INCA_IP_ICU_IM1_ISR_IR(value)               (1 << value)
+
+
+/***IM2 Interrupt Status Register***/
+#define INCA_IP_ICU_IM2_ISR                      ((volatile u32*)(INCA_IP_ICU+ 0x0400))
+#define INCA_IP_ICU_IM2_ISR_IR(value)               (1 << value)
+
+
+/***IM0 Interrupt Enable Register***/
+#define INCA_IP_ICU_IM0_IER                      ((volatile u32*)(INCA_IP_ICU+ 0x0008))
+#define INCA_IP_ICU_IM0_IER_IR(value)               (1 << value)
+
+
+/***IM1 Interrupt Enable Register***/
+#define INCA_IP_ICU_IM1_IER                      ((volatile u32*)(INCA_IP_ICU+ 0x0208))
+#define INCA_IP_ICU_IM1_IER_IR(value)               (1 << value)
+
+
+/***IM2 Interrupt Enable Register***/
+#define INCA_IP_ICU_IM2_IER                      ((volatile u32*)(INCA_IP_ICU+ 0x0408))
+#define INCA_IP_ICU_IM2_IER_IR(value)               (1 << value)
+
+
+/***IM0 Interrupt Output Status Register***/
+#define INCA_IP_ICU_IM0_IOSR                    ((volatile u32*)(INCA_IP_ICU+ 0x0010))
+#define INCA_IP_ICU_IM0_IOSR_IR(value)               (1 << value)
+
+
+/***IM1 Interrupt Output Status Register***/
+#define INCA_IP_ICU_IM1_IOSR                    ((volatile u32*)(INCA_IP_ICU+ 0x0210))
+#define INCA_IP_ICU_IM1_IOSR_IR(value)               (1 << value)
+
+
+/***IM2 Interrupt Output Status Register***/
+#define INCA_IP_ICU_IM2_IOSR                    ((volatile u32*)(INCA_IP_ICU+ 0x0410))
+#define INCA_IP_ICU_IM2_IOSR_IR(value)               (1 << value)
+
+
+/***IM0 Interrupt Request Set Register***/
+#define INCA_IP_ICU_IM0_IRSR                    ((volatile u32*)(INCA_IP_ICU+ 0x0018))
+#define INCA_IP_ICU_IM0_IRSR_IR(value)               (1 << value)
+
+
+/***IM1 Interrupt Request Set Register***/
+#define INCA_IP_ICU_IM1_IRSR                    ((volatile u32*)(INCA_IP_ICU+ 0x0218))
+#define INCA_IP_ICU_IM1_IRSR_IR(value)               (1 << value)
+
+
+/***IM2 Interrupt Request Set Register***/
+#define INCA_IP_ICU_IM2_IRSR                    ((volatile u32*)(INCA_IP_ICU+ 0x0418))
+#define INCA_IP_ICU_IM2_IRSR_IR(value)               (1 << value)
+
+
+/***External Interrupt Control Register***/
+#define INCA_IP_ICU_ICU_EICR                    ((volatile u32*)(INCA_IP_ICU+ 0x0B00))
+#define INCA_IP_ICU_ICU_EICR_EII5 (value)               (((( 1 << 3) - 1) & (value)) << 20)
+#define INCA_IP_ICU_ICU_EICR_EII4 (value)               (((( 1 << 3) - 1) & (value)) << 16)
+#define INCA_IP_ICU_ICU_EICR_EII3 (value)               (((( 1 << 3) - 1) & (value)) << 12)
+#define INCA_IP_ICU_ICU_EICR_EII2 (value)               (((( 1 << 3) - 1) & (value)) << 8)
+#define INCA_IP_ICU_ICU_EICR_EII1 (value)               (((( 1 << 3) - 1) & (value)) << 4)
+#define INCA_IP_ICU_ICU_EICR_EII0 (value)               (((( 1 << 3) - 1) & (value)) << 0)
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
new file mode 100755
index 0000000..857fb03
--- /dev/null
+++ b/include/asm-mips/io.h
@@ -0,0 +1,450 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995 Waldorf GmbH
+ * Copyright (C) 1994 - 2000 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000 FSMLabs, Inc.
+ */
+#ifndef _ASM_IO_H
+#define _ASM_IO_H
+
+#include <linux/config.h>
+#if 0
+#include <linux/pagemap.h>
+#endif
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+
+/*
+ * Slowdown I/O port space accesses for antique hardware.
+ */
+#undef CONF_SLOWDOWN_IO
+
+/*
+ * Sane hardware offers swapping of I/O space accesses in hardware; less
+ * sane hardware forces software to fiddle with this ...
+ */
+#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
+
+#define __ioswab8(x) (x)
+#define __ioswab16(x) swab16(x)
+#define __ioswab32(x) swab32(x)
+
+#else
+
+#define __ioswab8(x) (x)
+#define __ioswab16(x) (x)
+#define __ioswab32(x) (x)
+
+#endif
+
+/*
+ * This file contains the definitions for the MIPS counterpart of the
+ * x86 in/out instructions. This heap of macros and C results in much
+ * better code than the approach of doing it in plain C.  The macros
+ * result in code that is to fast for certain hardware.  On the other
+ * side the performance of the string functions should be improved for
+ * sake of certain devices like EIDE disks that do highspeed polled I/O.
+ *
+ *   Ralf
+ *
+ * This file contains the definitions for the x86 IO instructions
+ * inb/inw/inl/outb/outw/outl and the "string versions" of the same
+ * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
+ * versions of the single-IO instructions (inb_p/inw_p/..).
+ *
+ * This file is not meant to be obfuscating: it's just complicated
+ * to (a) handle it all in a way that makes gcc able to optimize it
+ * as well as possible and (b) trying to avoid writing the same thing
+ * over and over again with slight variations and possibly making a
+ * mistake somewhere.
+ */
+
+/*
+ * On MIPS I/O ports are memory mapped, so we access them using normal
+ * load/store instructions. mips_io_port_base is the virtual address to
+ * which all ports are being mapped.  For sake of efficiency some code
+ * assumes that this is an address that can be loaded with a single lui
+ * instruction, so the lower 16 bits must be zero.  Should be true on
+ * on any sane architecture; generic code does not use this assumption.
+ */
+extern unsigned long mips_io_port_base;
+
+/*
+ * Thanks to James van Artsdalen for a better timing-fix than
+ * the two short jumps: using outb's to a nonexistent port seems
+ * to guarantee better timings even on fast machines.
+ *
+ * On the other hand, I'd like to be sure of a non-existent port:
+ * I feel a bit unsafe about using 0x80 (should be safe, though)
+ *
+ *		Linus
+ *
+ */
+
+#define __SLOW_DOWN_IO \
+	__asm__ __volatile__( \
+		"sb\t$0,0x80(%0)" \
+		: : "r" (mips_io_port_base));
+
+#ifdef CONF_SLOWDOWN_IO
+#ifdef REALLY_SLOW_IO
+#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
+#else
+#define SLOW_DOWN_IO __SLOW_DOWN_IO
+#endif
+#else
+#define SLOW_DOWN_IO
+#endif
+
+/*
+ * Change virtual addresses to physical addresses and vv.
+ * These are trivial on the 1:1 Linux/MIPS mapping
+ */
+extern inline unsigned long virt_to_phys(volatile void * address)
+{
+	return PHYSADDR(address);
+}
+
+extern inline void * phys_to_virt(unsigned long address)
+{
+	return (void *)KSEG0ADDR(address);
+}
+
+/*
+ * IO bus memory addresses are also 1:1 with the physical address
+ */
+extern inline unsigned long virt_to_bus(volatile void * address)
+{
+	return PHYSADDR(address);
+}
+
+extern inline void * bus_to_virt(unsigned long address)
+{
+	return (void *)KSEG0ADDR(address);
+}
+
+/*
+ * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
+ * for the processor.
+ */
+extern unsigned long isa_slot_offset;
+
+extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
+
+#if 0
+extern inline void *ioremap(unsigned long offset, unsigned long size)
+{
+	return __ioremap(offset, size, _CACHE_UNCACHED);
+}
+
+extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
+{
+	return __ioremap(offset, size, _CACHE_UNCACHED);
+}
+
+extern void iounmap(void *addr);
+#endif
+
+/*
+ * XXX We need system specific versions of these to handle EISA address bits
+ * 24-31 on SNI.
+ * XXX more SNI hacks.
+ */
+#define readb(addr) (*(volatile unsigned char *)(addr))
+#define readw(addr) __ioswab16((*(volatile unsigned short *)(addr)))
+#define readl(addr) __ioswab32((*(volatile unsigned int *)(addr)))
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+
+#define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b)
+#define writew(b,addr) (*(volatile unsigned short *)(addr)) = (__ioswab16(b))
+#define writel(b,addr) (*(volatile unsigned int *)(addr)) = (__ioswab32(b))
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+
+#define memset_io(a,b,c)	memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c)	memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c)	memcpy((void *)(a),(b),(c))
+
+/* END SNI HACKS ... */
+
+/*
+ * ISA space is 'always mapped' on currently supported MIPS systems, no need
+ * to explicitly ioremap() it. The fact that the ISA IO space is mapped
+ * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
+ * are physical addresses. The following constant pointer can be
+ * used as the IO-area pointer (it can be iounmapped as well, so the
+ * analogy with PCI is quite large):
+ */
+#define __ISA_IO_base ((char *)(PAGE_OFFSET))
+
+#define isa_readb(a) readb(a)
+#define isa_readw(a) readw(a)
+#define isa_readl(a) readl(a)
+#define isa_writeb(b,a) writeb(b,a)
+#define isa_writew(w,a) writew(w,a)
+#define isa_writel(l,a) writel(l,a)
+
+#define isa_memset_io(a,b,c)     memset_io((a),(b),(c))
+#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c))
+#define isa_memcpy_toio(a,b,c)   memcpy_toio((a),(b),(c))
+
+/*
+ * We don't have csum_partial_copy_fromio() yet, so we cheat here and
+ * just copy it. The net code will then do the checksum later.
+ */
+#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
+#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
+
+static inline int check_signature(unsigned long io_addr,
+				  const unsigned char *signature, int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+#define isa_check_signature(io, s, l) check_signature(i,s,l)
+
+/*
+ * Talk about misusing macros..
+ */
+
+#define __OUT1(s) \
+extern inline void __out##s(unsigned int value, unsigned int port) {
+
+#define __OUT2(m) \
+__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
+
+#define __OUT(m,s,w) \
+__OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \
+__OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \
+__OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \
+	SLOW_DOWN_IO; } \
+__OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \
+	SLOW_DOWN_IO; }
+
+#define __IN1(t,s) \
+extern __inline__ t __in##s(unsigned int port) { t _v;
+
+/*
+ * Required nops will be inserted by the assembler
+ */
+#define __IN2(m) \
+__asm__ __volatile__ ("l" #m "\t%0,%1(%2)"
+
+#define __IN(t,m,s,w) \
+__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \
+__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \
+__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \
+__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
+
+#define __INS1(s) \
+extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
+
+#define __INS2(m) \
+if (count) \
+__asm__ __volatile__ ( \
+	".set\tnoreorder\n\t" \
+	".set\tnoat\n" \
+	"1:\tl" #m "\t$1,%4(%5)\n\t" \
+	"subu\t%1,1\n\t" \
+	"s" #m "\t$1,(%0)\n\t" \
+	"bne\t$0,%1,1b\n\t" \
+	"addiu\t%0,%6\n\t" \
+	".set\tat\n\t" \
+	".set\treorder"
+
+#define __INS(m,s,i) \
+__INS1(s) __INS2(m) \
+	: "=r" (addr), "=r" (count) \
+	: "0" (addr), "1" (count), "i" (0), \
+	  "r" (mips_io_port_base+port), "I" (i) \
+	: "$1");} \
+__INS1(s##c) __INS2(m) \
+	: "=r" (addr), "=r" (count) \
+	: "0" (addr), "1" (count), "ir" (port), \
+	  "r" (mips_io_port_base), "I" (i) \
+	: "$1");}
+
+#define __OUTS1(s) \
+extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
+
+#define __OUTS2(m) \
+if (count) \
+__asm__ __volatile__ ( \
+	".set\tnoreorder\n\t" \
+	".set\tnoat\n" \
+	"1:\tl" #m "\t$1,(%0)\n\t" \
+	"subu\t%1,1\n\t" \
+	"s" #m "\t$1,%4(%5)\n\t" \
+	"bne\t$0,%1,1b\n\t" \
+	"addiu\t%0,%6\n\t" \
+	".set\tat\n\t" \
+	".set\treorder"
+
+#define __OUTS(m,s,i) \
+__OUTS1(s) __OUTS2(m) \
+	: "=r" (addr), "=r" (count) \
+	: "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
+	: "$1");} \
+__OUTS1(s##c) __OUTS2(m) \
+	: "=r" (addr), "=r" (count) \
+	: "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
+	: "$1");}
+
+__IN(unsigned char,b,b,8)
+__IN(unsigned short,h,w,16)
+__IN(unsigned int,w,l,32)
+
+__OUT(b,b,8)
+__OUT(h,w,16)
+__OUT(w,l,32)
+
+__INS(b,b,1)
+__INS(h,w,2)
+__INS(w,l,4)
+
+__OUTS(b,b,1)
+__OUTS(h,w,2)
+__OUTS(w,l,4)
+
+
+/*
+ * Note that due to the way __builtin_constant_p() works, you
+ *  - can't use it inside an inline function (it will never be true)
+ *  - you don't have to worry about side effects within the __builtin..
+ */
+#define outb(val,port) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__outbc((val),(port)) : \
+	__outb((val),(port)))
+
+#define inb(port) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__inbc(port) : \
+	__inb(port))
+
+#define outb_p(val,port) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__outbc_p((val),(port)) : \
+	__outb_p((val),(port)))
+
+#define inb_p(port) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__inbc_p(port) : \
+	__inb_p(port))
+
+#define outw(val,port) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__outwc((val),(port)) : \
+	__outw((val),(port)))
+
+#define inw(port) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__inwc(port) : \
+	__inw(port))
+
+#define outw_p(val,port) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__outwc_p((val),(port)) : \
+	__outw_p((val),(port)))
+
+#define inw_p(port) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__inwc_p(port) : \
+	__inw_p(port))
+
+#define outl(val,port) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__outlc((val),(port)) : \
+	__outl((val),(port)))
+
+#define inl(port) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__inlc(port) : \
+	__inl(port))
+
+#define outl_p(val,port) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__outlc_p((val),(port)) : \
+	__outl_p((val),(port)))
+
+#define inl_p(port) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__inlc_p(port) : \
+	__inl_p(port))
+
+
+#define outsb(port,addr,count) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__outsbc((port),(addr),(count)) : \
+	__outsb ((port),(addr),(count)))
+
+#define insb(port,addr,count) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__insbc((port),(addr),(count)) : \
+	__insb((port),(addr),(count)))
+
+#define outsw(port,addr,count) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__outswc((port),(addr),(count)) : \
+	__outsw ((port),(addr),(count)))
+
+#define insw(port,addr,count) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__inswc((port),(addr),(count)) : \
+	__insw((port),(addr),(count)))
+
+#define outsl(port,addr,count) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__outslc((port),(addr),(count)) : \
+	__outsl ((port),(addr),(count)))
+
+#define insl(port,addr,count) \
+((__builtin_constant_p((port)) && (port) < 32768) ? \
+	__inslc((port),(addr),(count)) : \
+	__insl((port),(addr),(count)))
+
+#define IO_SPACE_LIMIT 0xffff
+
+/*
+ * The caches on some architectures aren't dma-coherent and have need to
+ * handle this in software.  There are three types of operations that
+ * can be applied to dma buffers.
+ *
+ *  - dma_cache_wback_inv(start, size) makes caches and coherent by
+ *    writing the content of the caches back to memory, if necessary.
+ *    The function also invalidates the affected part of the caches as
+ *    necessary before DMA transfers from outside to memory.
+ *  - dma_cache_wback(start, size) makes caches and coherent by
+ *    writing the content of the caches back to memory, if necessary.
+ *    The function also invalidates the affected part of the caches as
+ *    necessary before DMA transfers from outside to memory.
+ *  - dma_cache_inv(start, size) invalidates the affected parts of the
+ *    caches.  Dirty lines of the caches may be written back or simply
+ *    be discarded.  This operation is necessary before dma operations
+ *    to the memory.
+ */
+extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
+extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
+extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+
+#define dma_cache_wback_inv(start,size)	_dma_cache_wback_inv(start,size)
+#define dma_cache_wback(start,size)	_dma_cache_wback(start,size)
+#define dma_cache_inv(start,size)	_dma_cache_inv(start,size)
+
+#endif /* _ASM_IO_H */
diff --git a/include/asm-mips/isadep.h b/include/asm-mips/isadep.h
new file mode 100755
index 0000000..3cd1eb8
--- /dev/null
+++ b/include/asm-mips/isadep.h
@@ -0,0 +1,35 @@
+/*
+ * Various ISA level dependant constants.
+ * Most of the following constants reflect the different layout
+ * of Coprocessor 0 registers.
+ *
+ * Copyright (c) 1998 Harald Koerfgen
+ */
+#include <linux/config.h>
+
+#ifndef __ASM_ISADEP_H
+#define __ASM_ISADEP_H
+
+#if defined(CONFIG_CPU_R3000)
+/*
+ * R2000 or R3000
+ */
+
+/*
+ * kernel or user mode? (CP0_STATUS)
+ */
+#define KU_MASK 0x08
+#define	KU_USER 0x08
+#define KU_KERN 0x00
+
+#else
+/*
+ * kernel or user mode?
+ */
+#define KU_MASK 0x18
+#define	KU_USER 0x10
+#define KU_KERN 0x00
+
+#endif
+
+#endif /* __ASM_ISADEP_H */
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
new file mode 100755
index 0000000..0586c53
--- /dev/null
+++ b/include/asm-mips/mipsregs.h
@@ -0,0 +1,547 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Modified for further R[236]000 support by Paul M. Antoine, 1996.
+ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2003  Maciej W. Rozycki
+ */
+#ifndef _ASM_MIPSREGS_H
+#define _ASM_MIPSREGS_H
+
+#if 0
+#include <linux/linkage.h>
+#endif
+
+/*
+ * The following macros are especially useful for __asm__
+ * inline assembler.
+ */
+#ifndef __STR
+#define __STR(x) #x
+#endif
+#ifndef STR
+#define STR(x) __STR(x)
+#endif
+
+/*
+ * Coprocessor 0 register names
+ */
+#define CP0_INDEX $0
+#define CP0_RANDOM $1
+#define CP0_ENTRYLO0 $2
+#define CP0_ENTRYLO1 $3
+#define CP0_CONF $3
+#define CP0_CONTEXT $4
+#define CP0_PAGEMASK $5
+#define CP0_WIRED $6
+#define CP0_INFO $7
+#define CP0_BADVADDR $8
+#define CP0_COUNT $9
+#define CP0_ENTRYHI $10
+#define CP0_COMPARE $11
+#define CP0_STATUS $12
+#define CP0_CAUSE $13
+#define CP0_EPC $14
+#define CP0_PRID $15
+#define CP0_CONFIG $16
+#define CP0_LLADDR $17
+#define CP0_WATCHLO $18
+#define CP0_WATCHHI $19
+#define CP0_XCONTEXT $20
+#define CP0_FRAMEMASK $21
+#define CP0_DIAGNOSTIC $22
+#define CP0_PERFORMANCE $25
+#define CP0_ECC $26
+#define CP0_CACHEERR $27
+#define CP0_TAGLO $28
+#define CP0_TAGHI $29
+#define CP0_ERROREPC $30
+
+/*
+ * R4640/R4650 cp0 register names.  These registers are listed
+ * here only for completeness; without MMU these CPUs are not useable
+ * by Linux.  A future ELKS port might take make Linux run on them
+ * though ...
+ */
+#define CP0_IBASE $0
+#define CP0_IBOUND $1
+#define CP0_DBASE $2
+#define CP0_DBOUND $3
+#define CP0_CALG $17
+#define CP0_IWATCH $18
+#define CP0_DWATCH $19
+
+/*
+ * Coprocessor 0 Set 1 register names
+ */
+#define CP0_S1_DERRADDR0  $26
+#define CP0_S1_DERRADDR1  $27
+#define CP0_S1_INTCONTROL $20
+/*
+ * Coprocessor 1 (FPU) register names
+ */
+#define CP1_REVISION   $0
+#define CP1_STATUS     $31
+
+/*
+ * FPU Status Register Values
+ */
+/*
+ * Status Register Values
+ */
+
+#define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
+#define FPU_CSR_COND    0x00800000      /* $fcc0 */
+#define FPU_CSR_COND0   0x00800000      /* $fcc0 */
+#define FPU_CSR_COND1   0x02000000      /* $fcc1 */
+#define FPU_CSR_COND2   0x04000000      /* $fcc2 */
+#define FPU_CSR_COND3   0x08000000      /* $fcc3 */
+#define FPU_CSR_COND4   0x10000000      /* $fcc4 */
+#define FPU_CSR_COND5   0x20000000      /* $fcc5 */
+#define FPU_CSR_COND6   0x40000000      /* $fcc6 */
+#define FPU_CSR_COND7   0x80000000      /* $fcc7 */
+
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X 0x0003f000
+#define FPU_CSR_UNI_X   0x00020000
+#define FPU_CSR_INV_X   0x00010000
+#define FPU_CSR_DIV_X   0x00008000
+#define FPU_CSR_OVF_X   0x00004000
+#define FPU_CSR_UDF_X   0x00002000
+#define FPU_CSR_INE_X   0x00001000
+
+#define FPU_CSR_ALL_E   0x00000f80
+#define FPU_CSR_INV_E   0x00000800
+#define FPU_CSR_DIV_E   0x00000400
+#define FPU_CSR_OVF_E   0x00000200
+#define FPU_CSR_UDF_E   0x00000100
+#define FPU_CSR_INE_E   0x00000080
+
+#define FPU_CSR_ALL_S   0x0000007c
+#define FPU_CSR_INV_S   0x00000040
+#define FPU_CSR_DIV_S   0x00000020
+#define FPU_CSR_OVF_S   0x00000010
+#define FPU_CSR_UDF_S   0x00000008
+#define FPU_CSR_INE_S   0x00000004
+
+/* rounding mode */
+#define FPU_CSR_RN      0x0     /* nearest */
+#define FPU_CSR_RZ      0x1     /* towards zero */
+#define FPU_CSR_RU      0x2     /* towards +Infinity */
+#define FPU_CSR_RD      0x3     /* towards -Infinity */
+
+
+/*
+ * Values for PageMask register
+ */
+#include <linux/config.h>
+#ifdef CONFIG_CPU_VR41XX
+#define PM_1K   0x00000000
+#define PM_4K   0x00001800
+#define PM_16K  0x00007800
+#define PM_64K  0x0001f800
+#define PM_256K 0x0007f800
+#else
+#define PM_4K   0x00000000
+#define PM_16K  0x00006000
+#define PM_64K  0x0001e000
+#define PM_256K 0x0007e000
+#define PM_1M   0x001fe000
+#define PM_4M   0x007fe000
+#define PM_16M  0x01ffe000
+#endif
+
+/*
+ * Values used for computation of new tlb entries
+ */
+#define PL_4K   12
+#define PL_16K  14
+#define PL_64K  16
+#define PL_256K 18
+#define PL_1M   20
+#define PL_4M   22
+#define PL_16M  24
+
+/*
+ * Macros to access the system control coprocessor
+ */
+#define read_32bit_cp0_register(source)                         \
+({ int __res;                                                   \
+	__asm__ __volatile__(                                   \
+	".set\tpush\n\t"					\
+	".set\treorder\n\t"					\
+	"mfc0\t%0,"STR(source)"\n\t"                            \
+	".set\tpop"						\
+	: "=r" (__res));                                        \
+	__res;})
+
+#define read_32bit_cp0_set1_register(source)                    \
+({ int __res;                                                   \
+	__asm__ __volatile__(                                   \
+	".set\tpush\n\t"					\
+	".set\treorder\n\t"					\
+	"cfc0\t%0,"STR(source)"\n\t"                            \
+	".set\tpop"						\
+	: "=r" (__res));                                        \
+	__res;})
+
+/*
+ * For now use this only with interrupts disabled!
+ */
+#define read_64bit_cp0_register(source)                         \
+({ int __res;                                                   \
+	__asm__ __volatile__(                                   \
+	".set\tmips3\n\t"                                       \
+	"dmfc0\t%0,"STR(source)"\n\t"                           \
+	".set\tmips0"                                           \
+	: "=r" (__res));                                        \
+	__res;})
+
+#define write_32bit_cp0_register(register,value)                \
+	__asm__ __volatile__(                                   \
+	"mtc0\t%0,"STR(register)"\n\t"				\
+	"nop"							\
+	: : "r" (value));
+
+#define write_32bit_cp0_set1_register(register,value)           \
+	__asm__ __volatile__(                                   \
+	"ctc0\t%0,"STR(register)"\n\t"				\
+	"nop"							\
+	: : "r" (value));
+
+#define write_64bit_cp0_register(register,value)                \
+	__asm__ __volatile__(                                   \
+	".set\tmips3\n\t"                                       \
+	"dmtc0\t%0,"STR(register)"\n\t"                         \
+	".set\tmips0"                                           \
+	: : "r" (value))
+
+/*
+ * This should be changed when we get a compiler that support the MIPS32 ISA.
+ */
+#define read_mips32_cp0_config1()                               \
+({ int __res;                                                   \
+	__asm__ __volatile__(                                   \
+	".set\tnoreorder\n\t"                                   \
+	".set\tnoat\n\t"                                        \
+	".word\t0x40018001\n\t"                                 \
+	"move\t%0,$1\n\t"                                       \
+	".set\tat\n\t"                                          \
+	".set\treorder"                                         \
+	:"=r" (__res));                                         \
+	__res;})
+
+#define tlb_write_indexed()                                     \
+	__asm__ __volatile__(                                   \
+		".set noreorder\n\t"                            \
+		"tlbwi\n\t"                                     \
+".set reorder")
+
+/*
+ * R4x00 interrupt enable / cause bits
+ */
+#define IE_SW0          (1<< 8)
+#define IE_SW1          (1<< 9)
+#define IE_IRQ0         (1<<10)
+#define IE_IRQ1         (1<<11)
+#define IE_IRQ2         (1<<12)
+#define IE_IRQ3         (1<<13)
+#define IE_IRQ4         (1<<14)
+#define IE_IRQ5         (1<<15)
+
+/*
+ * R4x00 interrupt cause bits
+ */
+#define C_SW0           (1<< 8)
+#define C_SW1           (1<< 9)
+#define C_IRQ0          (1<<10)
+#define C_IRQ1          (1<<11)
+#define C_IRQ2          (1<<12)
+#define C_IRQ3          (1<<13)
+#define C_IRQ4          (1<<14)
+#define C_IRQ5          (1<<15)
+
+#ifndef _LANGUAGE_ASSEMBLY
+/*
+ * Manipulate the status register.
+ * Mostly used to access the interrupt bits.
+ */
+#define __BUILD_SET_CP0(name,register)                          \
+extern __inline__ unsigned int                                  \
+set_cp0_##name(unsigned int set)				\
+{                                                               \
+	unsigned int res;                                       \
+								\
+	res = read_32bit_cp0_register(register);                \
+	res |= set;						\
+	write_32bit_cp0_register(register, res);        	\
+								\
+	return res;                                             \
+}								\
+								\
+extern __inline__ unsigned int                                  \
+clear_cp0_##name(unsigned int clear)				\
+{                                                               \
+	unsigned int res;                                       \
+								\
+	res = read_32bit_cp0_register(register);                \
+	res &= ~clear;						\
+	write_32bit_cp0_register(register, res);		\
+								\
+	return res;                                             \
+}								\
+								\
+extern __inline__ unsigned int                                  \
+change_cp0_##name(unsigned int change, unsigned int new)	\
+{                                                               \
+	unsigned int res;                                       \
+								\
+	res = read_32bit_cp0_register(register);                \
+	res &= ~change;                                         \
+	res |= (new & change);                                  \
+	if(change)                                              \
+		write_32bit_cp0_register(register, res);        \
+								\
+	return res;                                             \
+}
+
+__BUILD_SET_CP0(status,CP0_STATUS)
+__BUILD_SET_CP0(cause,CP0_CAUSE)
+__BUILD_SET_CP0(config,CP0_CONFIG)
+
+#endif /* defined (_LANGUAGE_ASSEMBLY) */
+
+/*
+ * Bitfields in the R4xx0 cp0 status register
+ */
+#define ST0_IE			0x00000001
+#define ST0_EXL			0x00000002
+#define ST0_ERL			0x00000004
+#define ST0_KSU			0x00000018
+#  define KSU_USER		0x00000010
+#  define KSU_SUPERVISOR	0x00000008
+#  define KSU_KERNEL		0x00000000
+#define ST0_UX			0x00000020
+#define ST0_SX			0x00000040
+#define ST0_KX 			0x00000080
+#define ST0_DE			0x00010000
+#define ST0_CE			0x00020000
+
+/*
+ * Bitfields in the R[23]000 cp0 status register.
+ */
+#define ST0_IEC                 0x00000001
+#define ST0_KUC			0x00000002
+#define ST0_IEP			0x00000004
+#define ST0_KUP			0x00000008
+#define ST0_IEO			0x00000010
+#define ST0_KUO			0x00000020
+/* bits 6 & 7 are reserved on R[23]000 */
+#define ST0_ISC			0x00010000
+#define ST0_SWC			0x00020000
+#define ST0_CM			0x00080000
+
+/*
+ * Bits specific to the R4640/R4650
+ */
+#define ST0_UM                 (1   <<  4)
+#define ST0_IL                 (1   << 23)
+#define ST0_DL                 (1   << 24)
+
+/*
+ * Bitfields in the TX39 family CP0 Configuration Register 3
+ */
+#define TX39_CONF_ICS_SHIFT	19
+#define TX39_CONF_ICS_MASK	0x00380000
+#define TX39_CONF_ICS_1KB 	0x00000000
+#define TX39_CONF_ICS_2KB 	0x00080000
+#define TX39_CONF_ICS_4KB 	0x00100000
+#define TX39_CONF_ICS_8KB 	0x00180000
+#define TX39_CONF_ICS_16KB 	0x00200000
+
+#define TX39_CONF_DCS_SHIFT	16
+#define TX39_CONF_DCS_MASK	0x00070000
+#define TX39_CONF_DCS_1KB 	0x00000000
+#define TX39_CONF_DCS_2KB 	0x00010000
+#define TX39_CONF_DCS_4KB 	0x00020000
+#define TX39_CONF_DCS_8KB 	0x00030000
+#define TX39_CONF_DCS_16KB 	0x00040000
+
+#define TX39_CONF_CWFON 	0x00004000
+#define TX39_CONF_WBON  	0x00002000
+#define TX39_CONF_RF_SHIFT	10
+#define TX39_CONF_RF_MASK	0x00000c00
+#define TX39_CONF_DOZE		0x00000200
+#define TX39_CONF_HALT		0x00000100
+#define TX39_CONF_LOCK		0x00000080
+#define TX39_CONF_ICE		0x00000020
+#define TX39_CONF_DCE		0x00000010
+#define TX39_CONF_IRSIZE_SHIFT	2
+#define TX39_CONF_IRSIZE_MASK	0x0000000c
+#define TX39_CONF_DRSIZE_SHIFT	0
+#define TX39_CONF_DRSIZE_MASK	0x00000003
+
+/*
+ * Status register bits available in all MIPS CPUs.
+ */
+#define ST0_IM			0x0000ff00
+#define  STATUSB_IP0		8
+#define  STATUSF_IP0		(1   <<  8)
+#define  STATUSB_IP1		9
+#define  STATUSF_IP1		(1   <<  9)
+#define  STATUSB_IP2		10
+#define  STATUSF_IP2		(1   << 10)
+#define  STATUSB_IP3		11
+#define  STATUSF_IP3		(1   << 11)
+#define  STATUSB_IP4		12
+#define  STATUSF_IP4		(1   << 12)
+#define  STATUSB_IP5		13
+#define  STATUSF_IP5		(1   << 13)
+#define  STATUSB_IP6		14
+#define  STATUSF_IP6		(1   << 14)
+#define  STATUSB_IP7		15
+#define  STATUSF_IP7		(1   << 15)
+#define  STATUSB_IP8		0
+#define  STATUSF_IP8		(1   << 0)
+#define  STATUSB_IP9		1
+#define  STATUSF_IP9		(1   << 1)
+#define  STATUSB_IP10		2
+#define  STATUSF_IP10		(1   << 2)
+#define  STATUSB_IP11		3
+#define  STATUSF_IP11		(1   << 3)
+#define  STATUSB_IP12		4
+#define  STATUSF_IP12		(1   << 4)
+#define  STATUSB_IP13		5
+#define  STATUSF_IP13		(1   << 5)
+#define  STATUSB_IP14		6
+#define  STATUSF_IP14		(1   << 6)
+#define  STATUSB_IP15		7
+#define  STATUSF_IP15		(1   << 7)
+#define ST0_CH			0x00040000
+#define ST0_SR			0x00100000
+#define ST0_BEV			0x00400000
+#define ST0_RE			0x02000000
+#define ST0_FR			0x04000000
+#define ST0_CU			0xf0000000
+#define ST0_CU0			0x10000000
+#define ST0_CU1			0x20000000
+#define ST0_CU2			0x40000000
+#define ST0_CU3			0x80000000
+#define ST0_XX			0x80000000	/* MIPS IV naming */
+
+/*
+ * Bitfields and bit numbers in the coprocessor 0 cause register.
+ *
+ * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
+ */
+#define  CAUSEB_EXCCODE		2
+#define  CAUSEF_EXCCODE		(31  <<  2)
+#define  CAUSEB_IP		8
+#define  CAUSEF_IP		(255 <<  8)
+#define  CAUSEB_IP0		8
+#define  CAUSEF_IP0		(1   <<  8)
+#define  CAUSEB_IP1		9
+#define  CAUSEF_IP1		(1   <<  9)
+#define  CAUSEB_IP2		10
+#define  CAUSEF_IP2		(1   << 10)
+#define  CAUSEB_IP3		11
+#define  CAUSEF_IP3		(1   << 11)
+#define  CAUSEB_IP4		12
+#define  CAUSEF_IP4		(1   << 12)
+#define  CAUSEB_IP5		13
+#define  CAUSEF_IP5		(1   << 13)
+#define  CAUSEB_IP6		14
+#define  CAUSEF_IP6		(1   << 14)
+#define  CAUSEB_IP7		15
+#define  CAUSEF_IP7		(1   << 15)
+#define  CAUSEB_IV		23
+#define  CAUSEF_IV		(1   << 23)
+#define  CAUSEB_CE		28
+#define  CAUSEF_CE		(3   << 28)
+#define  CAUSEB_BD		31
+#define  CAUSEF_BD		(1   << 31)
+
+/*
+ * Bits in the coprozessor 0 config register.
+ */
+#define CONF_CM_CACHABLE_NO_WA		0
+#define CONF_CM_CACHABLE_WA		1
+#define CONF_CM_UNCACHED		2
+#define CONF_CM_CACHABLE_NONCOHERENT	3
+#define CONF_CM_CACHABLE_CE		4
+#define CONF_CM_CACHABLE_COW		5
+#define CONF_CM_CACHABLE_CUW		6
+#define CONF_CM_CACHABLE_ACCELERATED	7
+#define CONF_CM_CMASK			7
+#define CONF_DB				(1 <<  4)
+#define CONF_IB				(1 <<  5)
+#define CONF_SC				(1 << 17)
+#define CONF_AC                         (1 << 23)
+#define CONF_HALT                       (1 << 25)
+
+/*
+ * R10000 performance counter definitions.
+ *
+ * FIXME: The R10000 performance counter opens a nice way to implement CPU
+ *        time accounting with a precission of one cycle.  I don't have
+ *        R10000 silicon but just a manual, so ...
+ */
+
+/*
+ * Events counted by counter #0
+ */
+#define CE0_CYCLES			0
+#define CE0_INSN_ISSUED			1
+#define CE0_LPSC_ISSUED			2
+#define CE0_S_ISSUED			3
+#define CE0_SC_ISSUED			4
+#define CE0_SC_FAILED			5
+#define CE0_BRANCH_DECODED		6
+#define CE0_QW_WB_SECONDARY		7
+#define CE0_CORRECTED_ECC_ERRORS	8
+#define CE0_ICACHE_MISSES		9
+#define CE0_SCACHE_I_MISSES		10
+#define CE0_SCACHE_I_WAY_MISSPREDICTED	11
+#define CE0_EXT_INTERVENTIONS_REQ	12
+#define CE0_EXT_INVALIDATE_REQ		13
+#define CE0_VIRTUAL_COHERENCY_COND	14
+#define CE0_INSN_GRADUATED		15
+
+/*
+ * Events counted by counter #1
+ */
+#define CE1_CYCLES			0
+#define CE1_INSN_GRADUATED		1
+#define CE1_LPSC_GRADUATED		2
+#define CE1_S_GRADUATED			3
+#define CE1_SC_GRADUATED		4
+#define CE1_FP_INSN_GRADUATED		5
+#define CE1_QW_WB_PRIMARY		6
+#define CE1_TLB_REFILL			7
+#define CE1_BRANCH_MISSPREDICTED	8
+#define CE1_DCACHE_MISS			9
+#define CE1_SCACHE_D_MISSES		10
+#define CE1_SCACHE_D_WAY_MISSPREDICTED	11
+#define CE1_EXT_INTERVENTION_HITS	12
+#define CE1_EXT_INVALIDATE_REQ		13
+#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS	14
+#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS	15
+
+/*
+ * These flags define in which priviledge mode the counters count events
+ */
+#define CEB_USER	8	/* Count events in user mode, EXL = ERL = 0 */
+#define CEB_SUPERVISOR	4	/* Count events in supvervisor mode EXL = ERL = 0 */
+#define CEB_KERNEL	2	/* Count events in kernel mode EXL = ERL = 0 */
+#define CEB_EXL		1	/* Count events with EXL = 1, ERL = 0 */
+
+#endif /* _ASM_MIPSREGS_H */
diff --git a/include/asm-mips/posix_types.h b/include/asm-mips/posix_types.h
new file mode 100755
index 0000000..879aae2
--- /dev/null
+++ b/include/asm-mips/posix_types.h
@@ -0,0 +1,123 @@
+/* $Id: posix_types.h,v 1.6 2000/02/04 23:32:54 ralf Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle
+ */
+#ifndef _ASM_POSIX_TYPES_H
+#define _ASM_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned int	__kernel_dev_t;
+typedef unsigned long	__kernel_ino_t;
+typedef unsigned int	__kernel_mode_t;
+typedef int		__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef int		__kernel_ipc_pid_t;
+typedef int		__kernel_uid_t;
+typedef int		__kernel_gid_t;
+typedef unsigned int	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef int		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef long		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef int		__kernel_uid32_t;
+typedef int		__kernel_gid32_t;
+typedef __kernel_uid_t	__kernel_old_uid_t;
+typedef __kernel_gid_t	__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long      __kernel_loff_t;
+#endif
+
+typedef struct {
+	long    val[2];
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	__fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+	unsigned long *__tmp = __p->fds_bits;
+	int __i;
+
+	if (__builtin_constant_p(__FDSET_LONGS)) {
+		switch (__FDSET_LONGS) {
+		case 16:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			__tmp[ 4] = 0; __tmp[ 5] = 0;
+			__tmp[ 6] = 0; __tmp[ 7] = 0;
+			__tmp[ 8] = 0; __tmp[ 9] = 0;
+			__tmp[10] = 0; __tmp[11] = 0;
+			__tmp[12] = 0; __tmp[13] = 0;
+			__tmp[14] = 0; __tmp[15] = 0;
+			return;
+
+		case 8:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			__tmp[ 4] = 0; __tmp[ 5] = 0;
+			__tmp[ 6] = 0; __tmp[ 7] = 0;
+			return;
+
+		case 4:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			return;
+		}
+	}
+	__i = __FDSET_LONGS;
+	while (__i) {
+		__i--;
+		*__tmp = 0;
+		__tmp++;
+	}
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* _ASM_POSIX_TYPES_H */
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
new file mode 100755
index 0000000..6838aee
--- /dev/null
+++ b/include/asm-mips/processor.h
@@ -0,0 +1,283 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 Waldorf GMBH
+ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PROCESSOR_H
+#define _ASM_PROCESSOR_H
+
+#include <linux/config.h>
+
+#include <asm/isadep.h>
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#if !defined (_LANGUAGE_ASSEMBLY)
+#if 0
+#include <linux/threads.h>
+#endif
+#include <asm/cachectl.h>
+#include <asm/mipsregs.h>
+#include <asm/reg.h>
+#include <asm/system.h>
+
+struct mips_cpuinfo {
+	unsigned long udelay_val;
+	unsigned long *pgd_quick;
+	unsigned long *pte_quick;
+	unsigned long pgtable_cache_sz;
+};
+
+/*
+ * System setup and hardware flags..
+ * XXX: Should go into mips_cpuinfo.
+ */
+extern void (*cpu_wait)(void);	/* only available on R4[26]00 and R3081 */
+extern void r3081_wait(void);
+extern void r4k_wait(void);
+extern char cyclecounter_available;	/* only available from R4000 upwards. */
+
+extern struct mips_cpuinfo boot_cpu_data;
+extern unsigned int vced_count, vcei_count;
+
+#ifdef CONFIG_SMP
+extern struct mips_cpuinfo cpu_data[];
+#define current_cpu_data cpu_data[smp_processor_id()]
+#else
+#define cpu_data &boot_cpu_data
+#define current_cpu_data boot_cpu_data
+#endif
+
+/*
+ * Bus types (default is ISA, but people can check others with these..)
+ * MCA_bus hardcoded to 0 for now.
+ *
+ * This needs to be extended since MIPS systems are being delivered with
+ * numerous different types of bus systems.
+ */
+extern int EISA_bus;
+#define MCA_bus 0
+#define MCA_bus__is_a_macro /* for versions in ksyms.c */
+
+/*
+ * MIPS has no problems with write protection
+ */
+#define wp_works_ok 1
+#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
+
+/* Lazy FPU handling on uni-processor */
+extern struct task_struct *last_task_used_math;
+
+/*
+ * User space process size: 2GB. This is hardcoded into a few places,
+ * so don't change it unless you know what you are doing.  TASK_SIZE
+ * for a 64 bit kernel expandable to 8192EB, of which the current MIPS
+ * implementations will "only" be able to use 1TB ...
+ */
+#define TASK_SIZE	(0x7fff8000UL)
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE	(TASK_SIZE / 3)
+
+/*
+ * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
+ */
+#define IO_BITMAP_SIZE	32
+
+#define NUM_FPU_REGS	32
+
+struct mips_fpu_hard_struct {
+	double fp_regs[NUM_FPU_REGS];
+	unsigned int control;
+};
+
+/*
+ * It would be nice to add some more fields for emulator statistics, but there
+ * are a number of fixed offsets in offset.h and elsewhere that would have to
+ * be recalculated by hand.  So the additional information will be private to
+ * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
+ */
+typedef u64 fpureg_t;
+struct mips_fpu_soft_struct {
+	fpureg_t	regs[NUM_FPU_REGS];
+	unsigned int	sr;
+};
+
+union mips_fpu_union {
+	struct mips_fpu_hard_struct hard;
+	struct mips_fpu_soft_struct soft;
+};
+
+#define INIT_FPU { \
+	{{0,},} \
+}
+
+typedef struct {
+	unsigned long seg;
+} mm_segment_t;
+
+/*
+ * If you change thread_struct remember to change the #defines below too!
+ */
+struct thread_struct {
+	/* Saved main processor registers. */
+	unsigned long reg16;
+	unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
+	unsigned long reg29, reg30, reg31;
+
+	/* Saved cp0 stuff. */
+	unsigned long cp0_status;
+
+	/* Saved fpu/fpu emulator stuff. */
+	union mips_fpu_union fpu;
+
+	/* Other stuff associated with the thread. */
+	unsigned long cp0_badvaddr;	/* Last user fault */
+	unsigned long cp0_baduaddr;	/* Last kernel fault accessing USEG */
+	unsigned long error_code;
+	unsigned long trap_no;
+#define MF_FIXADE 1			/* Fix address errors in software */
+#define MF_LOGADE 2			/* Log address errors to syslog */
+	unsigned long mflags;
+	mm_segment_t current_ds;
+	unsigned long irix_trampoline;  /* Wheee... */
+	unsigned long irix_oldctx;
+
+	/*
+	 * These are really only needed if the full FPU emulator is configured.
+	 * Would be made conditional on MIPS_FPU_EMULATOR if it weren't for the
+	 * fact that having offset.h rebuilt differently for different config
+	 * options would be asking for trouble.
+	 *
+	 * Saved EPC during delay-slot emulation (see math-emu/cp1emu.c)
+	 */
+	unsigned long dsemul_epc;
+
+	/*
+	 * Pointer to instruction used to induce address error
+	 */
+	unsigned long dsemul_aerpc;
+};
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
+
+#define INIT_THREAD  { \
+	/* \
+	 * saved main processor registers \
+	 */ \
+	0, 0, 0, 0, 0, 0, 0, 0, \
+		       0, 0, 0, \
+	/* \
+	 * saved cp0 stuff \
+	 */ \
+	0, \
+	/* \
+	 * saved fpu/fpu emulator stuff \
+	 */ \
+	INIT_FPU, \
+	/* \
+	 * Other stuff associated with the process \
+	 */ \
+	0, 0, 0, 0, \
+	/* \
+	 * For now the default is to fix address errors \
+	 */ \
+	MF_FIXADE, { 0 }, 0, 0, \
+	/* \
+	 * dsemul_epc and dsemul_aerpc should never be used uninitialized, \
+	 * but... \
+	 */ \
+	0 ,0 \
+}
+
+#ifdef __KERNEL__
+
+#define KERNEL_STACK_SIZE 8192
+
+#if !defined (_LANGUAGE_ASSEMBLY)
+
+/* Free all resources held by a thread. */
+#define release_thread(thread) do { } while(0)
+
+extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
+
+/* Copy and release all segment info associated with a VM */
+#define copy_segments(p, mm) do { } while(0)
+#define release_segments(mm) do { } while(0)
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+extern inline unsigned long thread_saved_pc(struct thread_struct *t)
+{
+	extern void ret_from_fork(void);
+
+	/* New born processes are a special case */
+	if (t->reg31 == (unsigned long) ret_from_fork)
+		return t->reg31;
+
+	return ((unsigned long *)t->reg29)[10];
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ */
+#define start_thread(regs, new_pc, new_sp) do {				\
+	/* New thread looses kernel privileges. */			\
+	regs->cp0_status = (regs->cp0_status & ~(ST0_CU0|ST0_KSU)) | KU_USER;\
+	regs->cp0_epc = new_pc;						\
+	regs->regs[29] = new_sp;					\
+	current->thread.current_ds = USER_DS;				\
+} while (0)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs))
+#define __KSTK_TOS(tsk) ((unsigned long)(tsk) + KERNEL_STACK_SIZE - 32)
+#define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc)))
+#define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29])))
+
+/* Allocation and freeing of basic task resources. */
+/*
+ * NOTE! The task struct and the stack go together
+ */
+#define THREAD_SIZE (2*PAGE_SIZE)
+#define alloc_task_struct() \
+	((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
+#define free_task_struct(p)	free_pages((unsigned long)(p),1)
+#define get_task_struct(tsk)      atomic_inc(&virt_to_page(tsk)->count)
+
+#define init_task	(init_task_union.task)
+#define init_stack	(init_task_union.stack)
+
+#define cpu_relax()	do { } while (0)
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
+#endif /* __KERNEL__ */
+
+/*
+ * Return_address is a replacement for __builtin_return_address(count)
+ * which on certain architectures cannot reasonably be implemented in GCC
+ * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
+ * Note that __builtin_return_address(x>=1) is forbidden because GCC
+ * aborts compilation on some CPUs.  It's simply not possible to unwind
+ * some CPU's stackframes.
+ *
+ * __builtin_return_address works only for non-leaf functions.  We avoid the
+ * overhead of a function call by forcing the compiler to save the return
+ * address register on the stack.
+ */
+#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
+
+#endif /* _ASM_PROCESSOR_H */
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
new file mode 100755
index 0000000..2517adb
--- /dev/null
+++ b/include/asm-mips/ptrace.h
@@ -0,0 +1,86 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000 by Ralf Baechle
+ *
+ * Machine dependent structs and defines to help the user use
+ * the ptrace system call.
+ */
+#ifndef _ASM_PTRACE_H
+#define _ASM_PTRACE_H
+
+#include <asm/isadep.h>
+#include <linux/types.h>
+
+/* 0 - 31 are integer registers, 32 - 63 are fp registers.  */
+#define FPR_BASE	32
+#define PC		64
+#define CAUSE		65
+#define BADVADDR	66
+#define MMHI		67
+#define MMLO		68
+#define FPC_CSR		69
+#define FPC_EIR		70
+
+#ifndef _LANGUAGE_ASSEMBLY
+/*
+ * This struct defines the way the registers are stored on the stack during a
+ * system call/exception. As usual the registers k0/k1 aren't being saved.
+ */
+struct pt_regs {
+	/* Pad bytes for argument save space on the stack. */
+	unsigned long pad0[6];
+
+	/* Saved main processor registers. */
+	unsigned long regs[32];
+
+	/* Other saved registers. */
+	unsigned long lo;
+	unsigned long hi;
+
+	/*
+	 * saved cp0 registers
+	 */
+	unsigned long cp0_epc;
+	unsigned long cp0_badvaddr;
+	unsigned long cp0_status;
+	unsigned long cp0_cause;
+};
+
+#endif /* !(_LANGUAGE_ASSEMBLY) */
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+/* #define PTRACE_GETREGS		12 */
+/* #define PTRACE_SETREGS		13 */
+/* #define PTRACE_GETFPREGS		14 */
+/* #define PTRACE_SETFPREGS		15 */
+/* #define PTRACE_GETFPXREGS		18 */
+/* #define PTRACE_SETFPXREGS		19 */
+
+#define PTRACE_SETOPTIONS	21
+
+/* options set using PTRACE_SETOPTIONS */
+#define PTRACE_O_TRACESYSGOOD	0x00000001
+
+#if 0 /* def _LANGUAGE_ASSEMBLY */
+#include <asm/offset.h>
+#endif
+
+#ifdef __KERNEL__
+
+#ifndef _LANGUAGE_ASSEMBLY
+/*
+ * Does the process account for user or for system time?
+ */
+#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
+
+#define instruction_pointer(regs) ((regs)->cp0_epc)
+
+extern void show_regs(struct pt_regs *);
+#endif /* !(_LANGUAGE_ASSEMBLY) */
+
+#endif
+
+#endif /* _ASM_PTRACE_H */
diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h
new file mode 100755
index 0000000..35505b7
--- /dev/null
+++ b/include/asm-mips/reg.h
@@ -0,0 +1,66 @@
+/*
+ * Various register offset definitions for debuggers, core file
+ * examiners and whatnot.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999 by Ralf Baechle
+ */
+#ifndef __ASM_MIPS_REG_H
+#define __ASM_MIPS_REG_H
+
+/*
+ * This defines/structures correspond to the register layout on stack -
+ * if the order here is changed, it needs to be updated in
+ * include/asm-mips/stackframe.h
+ */
+#define EF_REG0			6
+#define EF_REG1			7
+#define EF_REG2			8
+#define EF_REG3			9
+#define EF_REG4			10
+#define EF_REG5			11
+#define EF_REG6			12
+#define EF_REG7			13
+#define EF_REG8			14
+#define EF_REG9			15
+#define EF_REG10		16
+#define EF_REG11		17
+#define EF_REG12		18
+#define EF_REG13		19
+#define EF_REG14		20
+#define EF_REG15		21
+#define EF_REG16		22
+#define EF_REG17		23
+#define EF_REG18		24
+#define EF_REG19		25
+#define EF_REG20		26
+#define EF_REG21		27
+#define EF_REG22		28
+#define EF_REG23		29
+#define EF_REG24		30
+#define EF_REG25		31
+/*
+ * k0/k1 unsaved
+ */
+#define EF_REG28		34
+#define EF_REG29		35
+#define EF_REG30		36
+#define EF_REG31		37
+
+/*
+ * Saved special registers
+ */
+#define EF_LO			38
+#define EF_HI			39
+
+#define EF_CP0_EPC		40
+#define EF_CP0_BADVADDR		41
+#define EF_CP0_STATUS		42
+#define EF_CP0_CAUSE		44
+
+#define EF_SIZE			180	/* size in bytes */
+
+#endif /* __ASM_MIPS_REG_H */
diff --git a/include/asm-mips/regdef.h b/include/asm-mips/regdef.h
new file mode 100755
index 0000000..691d047
--- /dev/null
+++ b/include/asm-mips/regdef.h
@@ -0,0 +1,52 @@
+/*
+ * include/asm-mips/regdefs.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995 by Ralf Baechle
+ */
+
+#ifndef __ASM_MIPS_REGDEF_H
+#define __ASM_MIPS_REGDEF_H
+
+/*
+ * Symbolic register names for 32 bit ABI
+ */
+#define zero    $0      /* wired zero */
+#define AT      $1      /* assembler temp  - uppercase because of ".set at" */
+#define v0      $2      /* return value */
+#define v1      $3
+#define a0      $4      /* argument registers */
+#define a1      $5
+#define a2      $6
+#define a3      $7
+#define t0      $8      /* caller saved */
+#define t1      $9
+#define t2      $10
+#define t3      $11
+#define t4      $12
+#define t5      $13
+#define t6      $14
+#define t7      $15
+#define s0      $16     /* callee saved */
+#define s1      $17
+#define s2      $18
+#define s3      $19
+#define s4      $20
+#define s5      $21
+#define s6      $22
+#define s7      $23
+#define t8      $24     /* caller saved */
+#define t9      $25
+#define jp      $25     /* PIC jump register */
+#define k0      $26     /* kernel scratch */
+#define k1      $27
+#define gp      $28     /* global pointer */
+#define sp      $29     /* stack pointer */
+#define fp      $30     /* frame pointer */
+#define s8	$30	/* same like fp! */
+#define ra      $31     /* return address */
+
+#endif /* __ASM_MIPS_REGDEF_H */
diff --git a/include/asm-mips/sgidefs.h b/include/asm-mips/sgidefs.h
new file mode 100755
index 0000000..67f2658
--- /dev/null
+++ b/include/asm-mips/sgidefs.h
@@ -0,0 +1,44 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1999, 2001 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef __ASM_SGIDEFS_H
+#define __ASM_SGIDEFS_H
+
+/*
+ * Using a Linux compiler for building Linux seems logic but not to
+ * everybody.
+ */
+#if 0 /* ndef __linux__ */
+#error Use a Linux compiler or give up.
+#endif
+
+/*
+ * Definitions for the ISA levels
+ *
+ * With the introduction of MIPS32 / MIPS64 instruction sets definitions
+ * MIPS ISAs are no longer subsets of each other.  Therefore comparisons
+ * on these symbols except with == may result in unexpected results and
+ * are forbidden!
+ */
+#define _MIPS_ISA_MIPS1		1
+#define _MIPS_ISA_MIPS2		2
+#define _MIPS_ISA_MIPS3		3
+#define _MIPS_ISA_MIPS4		4
+#define _MIPS_ISA_MIPS5		5
+#define _MIPS_ISA_MIPS32	6
+#define _MIPS_ISA_MIPS64	7
+
+/*
+ * Subprogram calling convention
+ */
+#define _MIPS_SIM_ABI32		1
+#define _MIPS_SIM_NABI32	2
+#define _MIPS_SIM_ABI64		3
+
+#endif /* __ASM_SGIDEFS_H */
diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h
new file mode 100755
index 0000000..463a111
--- /dev/null
+++ b/include/asm-mips/string.h
@@ -0,0 +1,157 @@
+/* $Id: string.h,v 1.13 2000/02/19 14:12:14 harald Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle
+ */
+#ifndef __ASM_MIPS_STRING_H
+#define __ASM_MIPS_STRING_H
+
+#include <linux/config.h>
+
+#define __HAVE_ARCH_STRCPY
+extern __inline__ char *strcpy(char *__dest, __const__ char *__src)
+{
+  char *__xdest = __dest;
+
+  __asm__ __volatile__(
+	".set\tnoreorder\n\t"
+	".set\tnoat\n"
+	"1:\tlbu\t$1,(%1)\n\t"
+	"addiu\t%1,1\n\t"
+	"sb\t$1,(%0)\n\t"
+	"bnez\t$1,1b\n\t"
+	"addiu\t%0,1\n\t"
+	".set\tat\n\t"
+	".set\treorder"
+	: "=r" (__dest), "=r" (__src)
+	: "0" (__dest), "1" (__src)
+	: "$1","memory");
+
+  return __xdest;
+}
+
+#define __HAVE_ARCH_STRNCPY
+extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n)
+{
+  char *__xdest = __dest;
+
+  if (__n == 0)
+    return __xdest;
+
+  __asm__ __volatile__(
+	".set\tnoreorder\n\t"
+	".set\tnoat\n"
+	"1:\tlbu\t$1,(%1)\n\t"
+	"subu\t%2,1\n\t"
+	"sb\t$1,(%0)\n\t"
+	"beqz\t$1,2f\n\t"
+	"addiu\t%0,1\n\t"
+	"bnez\t%2,1b\n\t"
+	"addiu\t%1,1\n"
+	"2:\n\t"
+	".set\tat\n\t"
+	".set\treorder"
+	: "=r" (__dest), "=r" (__src), "=r" (__n)
+	: "0" (__dest), "1" (__src), "2" (__n)
+	: "$1","memory");
+
+  return __dest;
+}
+
+#define __HAVE_ARCH_STRCMP
+extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct)
+{
+  int __res;
+
+  __asm__ __volatile__(
+	".set\tnoreorder\n\t"
+	".set\tnoat\n\t"
+	"lbu\t%2,(%0)\n"
+	"1:\tlbu\t$1,(%1)\n\t"
+	"addiu\t%0,1\n\t"
+	"bne\t$1,%2,2f\n\t"
+	"addiu\t%1,1\n\t"
+	"bnez\t%2,1b\n\t"
+	"lbu\t%2,(%0)\n\t"
+#if defined(CONFIG_CPU_R3000)
+	"nop\n\t"
+#endif
+	"move\t%2,$1\n"
+	"2:\tsubu\t%2,$1\n"
+	"3:\t.set\tat\n\t"
+	".set\treorder"
+	: "=r" (__cs), "=r" (__ct), "=r" (__res)
+	: "0" (__cs), "1" (__ct)
+	: "$1");
+
+  return __res;
+}
+
+#define __HAVE_ARCH_STRNCMP
+extern __inline__ int
+strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count)
+{
+	int __res;
+
+	__asm__ __volatile__(
+	".set\tnoreorder\n\t"
+	".set\tnoat\n"
+	"1:\tlbu\t%3,(%0)\n\t"
+	"beqz\t%2,2f\n\t"
+	"lbu\t$1,(%1)\n\t"
+	"subu\t%2,1\n\t"
+	"bne\t$1,%3,3f\n\t"
+	"addiu\t%0,1\n\t"
+	"bnez\t%3,1b\n\t"
+	"addiu\t%1,1\n"
+	"2:\n\t"
+#if defined(CONFIG_CPU_R3000)
+	"nop\n\t"
+#endif
+	"move\t%3,$1\n"
+	"3:\tsubu\t%3,$1\n\t"
+	".set\tat\n\t"
+	".set\treorder"
+	: "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res)
+	: "0" (__cs), "1" (__ct), "2" (__count)
+	: "$1");
+
+	return __res;
+}
+
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *__s, int __c, size_t __count);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
+
+/* Don't build bcopy at all ...  */
+#define __HAVE_ARCH_BCOPY
+
+#define __HAVE_ARCH_MEMSCAN
+extern __inline__ void *memscan(void *__addr, int __c, size_t __size)
+{
+	char *__end = (char *)__addr + __size;
+
+	__asm__(".set\tpush\n\t"
+		".set\tnoat\n\t"
+		".set\treorder\n\t"
+		"1:\tbeq\t%0,%1,2f\n\t"
+		"addiu\t%0,1\n\t"
+		"lb\t$1,-1(%0)\n\t"
+		"bne\t$1,%4,1b\n"
+		"2:\t.set\tpop"
+		: "=r" (__addr), "=r" (__end)
+		: "0" (__addr), "1" (__end), "r" (__c)
+		: "$1");
+
+	return __addr;
+}
+
+#endif /* __ASM_MIPS_STRING_H */
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
new file mode 100755
index 0000000..b6d50e2
--- /dev/null
+++ b/include/asm-mips/system.h
@@ -0,0 +1,268 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999 by Ralf Baechle
+ * Copyright (C) 1996 by Paul M. Antoine
+ * Copyright (C) 1994 - 1999 by Ralf Baechle
+ *
+ * Changed set_except_vector declaration to allow return of previous
+ * vector address value - necessary for "borrowing" vectors.
+ *
+ * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_SYSTEM_H
+#define _ASM_SYSTEM_H
+
+#include <linux/config.h>
+#include <asm/sgidefs.h>
+#include <asm/ptrace.h>
+#if 0
+#include <linux/kernel.h>
+#endif
+
+extern __inline__ void
+__sti(void)
+{
+	__asm__ __volatile__(
+		".set\tpush\n\t"
+		".set\treorder\n\t"
+		".set\tnoat\n\t"
+		"mfc0\t$1,$12\n\t"
+		"ori\t$1,0x1f\n\t"
+		"xori\t$1,0x1e\n\t"
+		"mtc0\t$1,$12\n\t"
+		".set\tpop\n\t"
+		: /* no outputs */
+		: /* no inputs */
+		: "$1", "memory");
+}
+
+/*
+ * For cli() we have to insert nops to make shure that the new value
+ * has actually arrived in the status register before the end of this
+ * macro.
+ * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
+ * no nops at all.
+ */
+extern __inline__ void
+__cli(void)
+{
+	__asm__ __volatile__(
+		".set\tpush\n\t"
+		".set\treorder\n\t"
+		".set\tnoat\n\t"
+		"mfc0\t$1,$12\n\t"
+		"ori\t$1,1\n\t"
+		"xori\t$1,1\n\t"
+		".set\tnoreorder\n\t"
+		"mtc0\t$1,$12\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		".set\tpop\n\t"
+		: /* no outputs */
+		: /* no inputs */
+		: "$1", "memory");
+}
+
+#define __save_flags(x)							\
+__asm__ __volatile__(							\
+	".set\tpush\n\t"						\
+	".set\treorder\n\t"						\
+	"mfc0\t%0,$12\n\t"						\
+	".set\tpop\n\t"							\
+	: "=r" (x))
+
+#define __save_and_cli(x)						\
+__asm__ __volatile__(							\
+	".set\tpush\n\t"						\
+	".set\treorder\n\t"						\
+	".set\tnoat\n\t"						\
+	"mfc0\t%0,$12\n\t"						\
+	"ori\t$1,%0,1\n\t"						\
+	"xori\t$1,1\n\t"						\
+	".set\tnoreorder\n\t"						\
+	"mtc0\t$1,$12\n\t"						\
+	"nop\n\t"							\
+	"nop\n\t"							\
+	"nop\n\t"							\
+	".set\tpop\n\t"							\
+	: "=r" (x)							\
+	: /* no inputs */						\
+	: "$1", "memory")
+
+#define __restore_flags(flags)						\
+do {									\
+	unsigned long __tmp1;						\
+									\
+	__asm__ __volatile__(						\
+		".set\tnoreorder\t\t\t# __restore_flags\n\t"		\
+		".set\tnoat\n\t"					\
+		"mfc0\t$1, $12\n\t"					\
+		"andi\t%0, 1\n\t"					\
+		"ori\t$1, 1\n\t"					\
+		"xori\t$1, 1\n\t"					\
+		"or\t%0, $1\n\t"					\
+		"mtc0\t%0, $12\n\t"					\
+		"nop\n\t"						\
+		"nop\n\t"						\
+		"nop\n\t"						\
+		".set\tat\n\t"						\
+		".set\treorder"						\
+		: "=r" (__tmp1)						\
+		: "0" (flags)						\
+		: "$1", "memory");					\
+} while(0)
+
+#ifdef CONFIG_SMP
+
+extern void __global_sti(void);
+extern void __global_cli(void);
+extern unsigned long __global_save_flags(void);
+extern void __global_restore_flags(unsigned long);
+#  define sti() __global_sti()
+#  define cli() __global_cli()
+#  define save_flags(x) do { x = __global_save_flags(); } while (0)
+#  define restore_flags(x) __global_restore_flags(x)
+#  define save_and_cli(x) do { save_flags(x); cli(); } while(0)
+
+#else /* Single processor */
+
+#  define sti() __sti()
+#  define cli() __cli()
+#  define save_flags(x) __save_flags(x)
+#  define save_and_cli(x) __save_and_cli(x)
+#  define restore_flags(x) __restore_flags(x)
+
+#endif /* SMP */
+
+/* For spinlocks etc */
+#define local_irq_save(x)	__save_and_cli(x);
+#define local_irq_restore(x)	__restore_flags(x);
+#define local_irq_disable()	__cli();
+#define local_irq_enable()	__sti();
+
+/*
+ * These are probably defined overly paranoid ...
+ */
+#ifdef CONFIG_CPU_HAS_WB
+
+#include <asm/wbflush.h>
+#define rmb()	do { } while(0)
+#define wmb()	wbflush()
+#define mb()	wbflush()
+
+#else /* CONFIG_CPU_HAS_WB  */
+
+#define mb()						\
+__asm__ __volatile__(					\
+	"# prevent instructions being moved around\n\t"	\
+	".set\tnoreorder\n\t"				\
+	"# 8 nops to fool the R4400 pipeline\n\t"	\
+	"nop;nop;nop;nop;nop;nop;nop;nop\n\t"		\
+	".set\treorder"					\
+	: /* no output */				\
+	: /* no input */				\
+	: "memory")
+#define rmb() mb()
+#define wmb() mb()
+
+#endif /* CONFIG_CPU_HAS_WB  */
+
+#ifdef CONFIG_SMP
+#define smp_mb()	mb()
+#define smp_rmb()	rmb()
+#define smp_wmb()	wmb()
+#else
+#define smp_mb()	barrier()
+#define smp_rmb()	barrier()
+#define smp_wmb()	barrier()
+#endif
+
+#define set_mb(var, value) \
+do { var = value; mb(); } while (0)
+
+#define set_wmb(var, value) \
+do { var = value; wmb(); } while (0)
+
+#if !defined (_LANGUAGE_ASSEMBLY)
+/*
+ * switch_to(n) should switch tasks to task nr n, first
+ * checking that n isn't the current task, in which case it does nothing.
+ */
+#if 0
+extern asmlinkage void *resume(void *last, void *next);
+#endif
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
+
+#define prepare_to_switch()	do { } while(0)
+#define switch_to(prev,next,last) \
+do { \
+	(last) = resume(prev, next); \
+} while(0)
+
+/*
+ * For 32 and 64 bit operands we can take advantage of ll and sc.
+ * FIXME: This doesn't work for R3000 machines.
+ */
+extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
+{
+#ifdef CONFIG_CPU_HAS_LLSC
+	unsigned long dummy;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\t\t\t# xchg_u32\n\t"
+		".set\tnoat\n\t"
+		"ll\t%0, %3\n"
+		"1:\tmove\t$1, %2\n\t"
+		"sc\t$1, %1\n\t"
+		"beqzl\t$1, 1b\n\t"
+		" ll\t%0, %3\n\t"
+		".set\tat\n\t"
+		".set\treorder"
+		: "=r" (val), "=o" (*m), "=r" (dummy)
+		: "o" (*m), "2" (val)
+		: "memory");
+
+	return val;
+#else
+	unsigned long flags, retval;
+
+	save_flags(flags);
+	cli();
+	retval = *m;
+	*m = val;
+	restore_flags(flags);
+	return retval;
+#endif /* Processor-dependent optimization */
+}
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+#define tas(ptr) (xchg((ptr),1))
+
+static __inline__ unsigned long
+__xchg(unsigned long x, volatile void * ptr, int size)
+{
+	switch (size) {
+		case 4:
+			return xchg_u32(ptr, x);
+	}
+	return x;
+}
+
+extern void *set_except_vector(int n, void *addr);
+
+extern void __die(const char *, struct pt_regs *, const char *where,
+	unsigned long line) __attribute__((noreturn));
+extern void __die_if_kernel(const char *, struct pt_regs *, const char *where,
+	unsigned long line);
+
+#define die(msg, regs)							\
+	__die(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__)
+#define die_if_kernel(msg, regs)					\
+	__die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__)
+
+#endif /* _ASM_SYSTEM_H */
diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h
new file mode 100755
index 0000000..e757e22
--- /dev/null
+++ b/include/asm-mips/types.h
@@ -0,0 +1,77 @@
+/* $Id: types.h,v 1.3 1999/08/18 23:37:50 ralf Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_TYPES_H
+#define _ASM_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if (_MIPS_SZLONG == 64)
+
+typedef __signed__ long __s64;
+typedef unsigned long __u64;
+
+#else
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef __signed char s8;
+typedef unsigned char u8;
+
+typedef __signed short s16;
+typedef unsigned short u16;
+
+typedef __signed int s32;
+typedef unsigned int u32;
+
+#if (_MIPS_SZLONG == 64)
+
+typedef __signed__ long s64;
+typedef unsigned long u64;
+
+#else
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long s64;
+typedef unsigned long long u64;
+#endif
+
+#endif
+
+#define BITS_PER_LONG _MIPS_SZLONG
+
+typedef unsigned long dma_addr_t;
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_TYPES_H */
diff --git a/include/asm-mips/u-boot.h b/include/asm-mips/u-boot.h
new file mode 100755
index 0000000..d1273a4
--- /dev/null
+++ b/include/asm-mips/u-boot.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+typedef struct bd_info {
+	int		bi_baudrate;	/* serial console baudrate */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6];	/* Ethernet adress */
+	unsigned long	bi_arch_number;	/* unique id for this board */
+	unsigned long	bi_boot_params;	/* where this board expects params */
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size  of FLASH memory */
+	unsigned long	bi_flashoffset;	/* reserved area for startup monitor */
+} bd_t;
+#define bi_env_data bi_env->data
+#define bi_env_crc  bi_env->crc
+
+#endif	/* _U_BOOT_H_ */
diff --git a/include/asm-nios/bitops.h b/include/asm-nios/bitops.h
new file mode 100755
index 0000000..7744212
--- /dev/null
+++ b/include/asm-nios/bitops.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_NIOS_BITOPS_H_
+#define _ASM_NIOS_BITOPS_H_
+
+
+extern void set_bit(int nr, volatile void * a);
+extern void clear_bit(int nr, volatile void * a);
+extern int test_and_clear_bit(int nr, volatile void * a);
+extern void change_bit(unsigned long nr, volatile void *addr);
+extern int test_and_set_bit(int nr, volatile void * a);
+extern int test_and_change_bit(int nr, volatile void * addr);
+extern int test_bit(int nr, volatile void * a);
+extern int ffs(int i);
+
+#endif /* _ASM_NIOS_BITOPS_H */
diff --git a/include/asm-nios/byteorder.h b/include/asm-nios/byteorder.h
new file mode 100755
index 0000000..dc71021
--- /dev/null
+++ b/include/asm-nios/byteorder.h
@@ -0,0 +1,30 @@
+/*
+* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+* Scott McNutt <smcnutt@psyent.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#ifndef __ASM_NIOS_BYTEORDER_H
+#define __ASM_NIOS_BYTEORDER_H
+
+#include <asm/types.h>
+#include <linux/byteorder/little_endian.h>
+
+#endif
diff --git a/include/asm-nios/cache.h b/include/asm-nios/cache.h
new file mode 100755
index 0000000..3cdb703
--- /dev/null
+++ b/include/asm-nios/cache.h
@@ -0,0 +1 @@
+/*FIXME: Implement this! */
diff --git a/include/asm-nios/global_data.h b/include/asm-nios/global_data.h
new file mode 100755
index 0000000..fd11389
--- /dev/null
+++ b/include/asm-nios/global_data.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASM_NIOS_GLOBALDATA_H
+#define __ASM_NIOS_GLOBALDATA_H
+
+typedef	struct	global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
+	unsigned long	have_console;	/* serial_init() was called */
+	unsigned long	ram_size;	/* RAM size */
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid */
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+	unsigned long	post_log_word;	/* Record POST activities */
+	unsigned long	post_init_f_time; /* When post_init_f started */
+#endif
+	void		**jt;		/* Standalone app jump table */
+} gd_t;
+
+/* flags */
+#define	GD_FLG_RELOC	0x00001		/* Code was relocated to RAM		*/
+#define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
+#define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
+
+#define DECLARE_GLOBAL_DATA_PTR     register gd_t *gd asm ("%g7")
+
+#endif /* __ASM_NIOS_GLOBALDATA_H */
diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h
new file mode 100755
index 0000000..07499d9
--- /dev/null
+++ b/include/asm-nios/io.h
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_NIOS_IO_H_
+#define __ASM_NIOS_IO_H_
+
+#define readb(addr)\
+	({unsigned char val;\
+	 asm volatile(  "	pfxio	0		\n"\
+		 	"	ld	%0, [%1]	\n"\
+			"	ext8d	%0, %1		\n"\
+			:"=r"(val) : "r" (addr)); val;})
+
+#define readw(addr)\
+	({unsigned short val;\
+	 asm volatile(  "	pfxio	0		\n"\
+		 	"	ld	%0, [%1]	\n"\
+			"	ext16d	%0, %1		\n"\
+			:"=r"(val) : "r" (addr)); val;})
+
+#define readl(addr)\
+	({unsigned long val;\
+	 asm volatile(  "	pfxio	0		\n"\
+		 	"	ld	%0, [%1]	\n"\
+			:"=r"(val) : "r" (addr)); val;})
+
+#define writeb(addr,val)\
+	asm volatile (	"	fill8	%%r0, %1	\n"\
+			"	st8d	[%0], %%r0	\n"\
+			: : "r" (addr), "r" (val) : "r0")
+
+#define writew(addr,val)\
+	asm volatile (	"	fill16	%%r0, %1	\n"\
+			"	st16d	[%0], %%r0	\n"\
+			: : "r" (addr), "r" (val) : "r0")
+
+#define writel(addr,val)\
+	asm volatile (	"	st	[%0], %1	\n"\
+			: : "r" (addr), "r" (val))
+
+#define inb(addr)	readb(addr)
+#define inw(addr)	readw(addr)
+#define inl(addr)	readl(addr)
+#define outb(val,addr)	writeb(addr,val)
+#define outw(val,addr)	writew(addr,val)
+#define outl(val,addr)	writel(addr,val)
+
+static inline void insb (unsigned long port, void *dst, unsigned long count)
+{
+	unsigned char *p = dst;
+	while (count--) *p++ = inb (port);
+}
+static inline void insw (unsigned long port, void *dst, unsigned long count)
+{
+	unsigned short *p = dst;
+	while (count--) *p++ = inw (port);
+}
+static inline void insl (unsigned long port, void *dst, unsigned long count)
+{
+	unsigned long *p = dst;
+	while (count--) *p++ = inl (port);
+}
+
+static inline void outsb (unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned char *p = src;
+	while (count--) outb (*p++, port);
+}
+
+static inline void outsw (unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned short *p = src;
+	while (count--) outw (*p++, port);
+}
+static inline void outsl (unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned long *p = src;
+	while (count--) outl (*p++, port);
+}
+
+#endif /* __ASM_NIOS_IO_H_ */
diff --git a/include/asm-nios/posix_types.h b/include/asm-nios/posix_types.h
new file mode 100755
index 0000000..eb74214
--- /dev/null
+++ b/include/asm-nios/posix_types.h
@@ -0,0 +1,63 @@
+#ifndef __ASM_NIOS_POSIX_TYPES_H
+#define __ASM_NIOS_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short	__kernel_dev_t;
+typedef unsigned long	__kernel_ino_t;
+typedef unsigned short	__kernel_mode_t;
+typedef unsigned short	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef unsigned short	__kernel_ipc_pid_t;
+typedef unsigned short	__kernel_uid_t;
+typedef unsigned short	__kernel_gid_t;
+typedef unsigned long	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef int		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned short	__kernel_old_uid_t;
+typedef unsigned short	__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long	__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define	__FD_SET(d, set)	((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+
+#undef	__FD_CLR
+#define	__FD_CLR(d, set)	((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+
+#undef	__FD_ISSET
+#define	__FD_ISSET(d, set)	((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif
diff --git a/include/asm-nios/processor.h b/include/asm-nios/processor.h
new file mode 100755
index 0000000..78b8976
--- /dev/null
+++ b/include/asm-nios/processor.h
@@ -0,0 +1 @@
+/* FIXME: Implement this! */
diff --git a/include/asm-nios/psr.h b/include/asm-nios/psr.h
new file mode 100755
index 0000000..6e8eba8
--- /dev/null
+++ b/include/asm-nios/psr.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _NIOS_PSR_H
+#define _NIOS_PSR_H
+
+
+#endif /* _NIOS_PSR_H */
diff --git a/include/asm-nios/ptrace.h b/include/asm-nios/ptrace.h
new file mode 100755
index 0000000..73754c8
--- /dev/null
+++ b/include/asm-nios/ptrace.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _NIOS_PTRACE_H
+#define _NIOS_PTRACE_H
+
+struct pt_regs {
+	unsigned global[8];
+	unsigned in[8];
+	unsigned status;
+	unsigned istatus;
+	unsigned retaddr;
+};
+
+
+#endif /* _NIOS_PTRACE_H */
diff --git a/include/asm-nios/status_led.h b/include/asm-nios/status_led.h
new file mode 100755
index 0000000..241c917
--- /dev/null
+++ b/include/asm-nios/status_led.h
@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * asm-nios/status_led.h
+ *
+ * NIOS PIO based status led support functions
+ */
+
+#ifndef __ASM_STATUS_LED_H__
+#define __ASM_STATUS_LED_H__
+
+#include <nios-io.h>
+
+/* led_id_t is unsigned int mask */
+typedef unsigned int led_id_t;
+
+#ifdef	STATUS_LED_WRONLY	/* emulate read access */
+static led_id_t __led_portval = 0;
+#endif
+
+static inline void __led_init (led_id_t mask, int state)
+{
+	nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE;
+
+#ifdef	STATUS_LED_WRONLY	/* emulate read access */
+
+#if (STATUS_LED_ACTIVE == 0)
+	if (state == STATUS_LED_ON)
+		__led_portval &= ~mask;
+	else
+		__led_portval |= mask;
+#else
+	if (state == STATUS_LED_ON)
+		__led_portval |= mask;
+	else
+		__led_portval &= ~mask;
+#endif
+
+	piop->data = __led_portval;
+
+#else	/* !STATUS_LED_WRONLY */
+
+#if (STATUS_LED_ACTIVE == 0)
+	if (state == STATUS_LED_ON)
+		piop->data &= ~mask;
+	else
+		piop->data |= mask;
+#else
+	if (state == STATUS_LED_ON)
+		piop->data |= mask;
+	else
+		piop->data &= ~mask;
+#endif
+
+	piop->direction |= mask;
+
+#endif	/* STATUS_LED_WRONLY */
+}
+
+static inline void __led_toggle (led_id_t mask)
+{
+	nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE;
+
+#ifdef	STATUS_LED_WRONLY	/* emulate read access */
+
+	__led_portval ^= mask;
+	piop->data = __led_portval;
+
+#else	/* !STATUS_LED_WRONLY */
+
+	piop->data ^= mask;
+
+#endif	/* STATUS_LED_WRONLY */
+}
+
+static inline void __led_set (led_id_t mask, int state)
+{
+	nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE;
+
+#ifdef	STATUS_LED_WRONLY	/* emulate read access */
+
+#if (STATUS_LED_ACTIVE == 0)
+	if (state == STATUS_LED_ON)
+		__led_portval &= ~mask;
+	else
+		__led_portval |= mask;
+#else
+	if (state == STATUS_LED_ON)
+		__led_portval |= mask;
+	else
+		__led_portval &= ~mask;
+#endif
+
+	piop->data = __led_portval;
+
+#else	/* !STATUS_LED_WRONLY */
+
+#if (STATUS_LED_ACTIVE == 0)
+	if (state == STATUS_LED_ON)
+		piop->data &= ~mask;
+	else
+		piop->data |= mask;
+#else
+	if (state == STATUS_LED_ON)
+		piop->data |= mask;
+	else
+		piop->data &= ~mask;
+#endif
+
+#endif	/* STATUS_LED_WRONLY */
+}
+
+#endif	/* __ASM_STATUS_LED_H__ */
diff --git a/include/asm-nios/string.h b/include/asm-nios/string.h
new file mode 100755
index 0000000..fa33275
--- /dev/null
+++ b/include/asm-nios/string.h
@@ -0,0 +1,25 @@
+#ifndef __ASM_NIOS_STRING_H
+#define __ASM_NIOS_STRING_H
+
+#undef __HAVE_ARCH_STRRCHR
+extern char * strrchr(const char * s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char * strchr(const char * s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void * memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void * memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMSET
+extern void * memset(void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+extern void memzero(void *ptr, __kernel_size_t n);
+
+#endif
diff --git a/include/asm-nios/system.h b/include/asm-nios/system.h
new file mode 100755
index 0000000..9a9383d
--- /dev/null
+++ b/include/asm-nios/system.h
@@ -0,0 +1,4 @@
+#ifndef _ASM_NIOS_SYSTEM_H_
+#define _ASM_NIOS_SYSTEM_H_
+
+#endif /* _ASM_NIOS_SYSTEM_H */
diff --git a/include/asm-nios/types.h b/include/asm-nios/types.h
new file mode 100755
index 0000000..43fd8f6
--- /dev/null
+++ b/include/asm-nios/types.h
@@ -0,0 +1,57 @@
+#ifndef _NIOS_TYPES_H
+#define _NIOS_TYPES_H
+
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue.  However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ */
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+#endif /* __KERNEL__ */
+
+#endif /* _NIOS_TYPES_H */
diff --git a/include/asm-nios/u-boot.h b/include/asm-nios/u-boot.h
new file mode 100755
index 0000000..aae4be1
--- /dev/null
+++ b/include/asm-nios/u-boot.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2003
+ * Psyent Corporation
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_
+
+typedef struct bd_info {
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+	unsigned long	bi_sramstart;	/* start of SRAM memory */
+	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
+	unsigned long	bi_baudrate;	/* Console Baudrate */
+} bd_t;
+
+
+#endif	/* _U_BOOT_H_ */
diff --git a/include/asm-nios2/bitops.h b/include/asm-nios2/bitops.h
new file mode 100755
index 0000000..e6c1a85
--- /dev/null
+++ b/include/asm-nios2/bitops.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NIOS2_BITOPS_H_
+#define __ASM_NIOS2_BITOPS_H_
+
+
+extern void set_bit(int nr, volatile void * a);
+extern void clear_bit(int nr, volatile void * a);
+extern int test_and_clear_bit(int nr, volatile void * a);
+extern void change_bit(unsigned long nr, volatile void *addr);
+extern int test_and_set_bit(int nr, volatile void * a);
+extern int test_and_change_bit(int nr, volatile void * addr);
+extern int test_bit(int nr, volatile void * a);
+extern int ffs(int i);
+
+#endif /* __ASM_NIOS2_BITOPS_H */
diff --git a/include/asm-nios2/byteorder.h b/include/asm-nios2/byteorder.h
new file mode 100755
index 0000000..495c823
--- /dev/null
+++ b/include/asm-nios2/byteorder.h
@@ -0,0 +1,30 @@
+/*
+* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+* Scott McNutt <smcnutt@psyent.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#ifndef __ASM_NIOS2_BYTEORDER_H_
+#define __ASM_NIOS2_BYTEORDER_H_
+
+#include <asm/types.h>
+#include <linux/byteorder/little_endian.h>
+
+#endif /* __ASM_NIOS2_BYTEORDER_H_ */
diff --git a/include/asm-nios2/cache.h b/include/asm-nios2/cache.h
new file mode 100755
index 0000000..c78f343
--- /dev/null
+++ b/include/asm-nios2/cache.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NIOS2_CACHE_H_
+#define __ASM_NIOS2_CACHE_H_
+
+extern void flush_dcache (unsigned long start, unsigned long size);
+extern void flush_icache (unsigned long start, unsigned long size);
+
+#endif /* __ASM_NIOS2_CACHE_H_ */
diff --git a/include/asm-nios2/global_data.h b/include/asm-nios2/global_data.h
new file mode 100755
index 0000000..a1ac288
--- /dev/null
+++ b/include/asm-nios2/global_data.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	__ASM_NIOS2_GLOBALDATA_H_
+#define __ASM_NIOS2_GLOBALDATA_H_
+
+typedef	struct	global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
+	unsigned long	have_console;	/* serial_init() was called */
+	unsigned long	ram_size;	/* RAM size */
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	env_addr;	/* Address  of Environment struct */
+	unsigned long	env_valid;	/* Checksum of Environment valid */
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+	unsigned long	post_log_word;	/* Record POST activities */
+	unsigned long	post_init_f_time; /* When post_init_f started */
+#endif
+	void		**jt;		/* Standalone app jump table */
+} gd_t;
+
+/* flags */
+#define	GD_FLG_RELOC	0x00001		/* Code was relocated to RAM		*/
+#define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
+#define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
+
+#define DECLARE_GLOBAL_DATA_PTR     register gd_t *gd asm ("r15")
+
+#endif /* __ASM_NIOS2_GLOBALDATA_H_ */
diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h
new file mode 100755
index 0000000..b16a988
--- /dev/null
+++ b/include/asm-nios2/io.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NIOS2_IO_H_
+#define __ASM_NIOS2_IO_H_
+
+#define sync() asm volatile ("sync" : : : "memory");
+
+extern unsigned char inb (unsigned char *port);
+extern unsigned short inw (unsigned short *port);
+extern unsigned inl (unsigned port);
+
+#define readb(addr)\
+	({unsigned char val;\
+	 asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
+#define readw(addr)\
+	({unsigned short val;\
+	 asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
+#define readl(addr)\
+	({unsigned long val;\
+	 asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
+#define writeb(addr,val)\
+	asm volatile ("stbio %0, 0(%1)" : : "r" (addr), "r" (val))
+#define writew(addr,val)\
+	asm volatile ("sthio %0, 0(%1)" : : "r" (addr), "r" (val))
+#define writel(addr,val)\
+	asm volatile ("stwio %0, 0(%1)" : : "r" (addr), "r" (val))
+
+#define inb(addr)	readb(addr)
+#define inw(addr)	readw(addr)
+#define inl(addr)	readl(addr)
+#define outb(addr,val)	writeb(addr,val)
+#define outw(addr,val)	writew(addr,val)
+#define outl(addr,val)	writel(addr,val)
+
+static inline void insb (unsigned long port, void *dst, unsigned long count)
+{
+	unsigned char *p = dst;
+	while (count--) *p++ = inb (port);
+}
+static inline void insw (unsigned long port, void *dst, unsigned long count)
+{
+	unsigned short *p = dst;
+	while (count--) *p++ = inw (port);
+}
+static inline void insl (unsigned long port, void *dst, unsigned long count)
+{
+	unsigned long *p = dst;
+	while (count--) *p++ = inl (port);
+}
+
+static inline void outsb (unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned char *p = src;
+	while (count--) outb (*p++, port);
+}
+
+static inline void outsw (unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned short *p = src;
+	while (count--) outw (*p++, port);
+}
+static inline void outsl (unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned long *p = src;
+	while (count--) outl (*p++, port);
+}
+
+#endif /* __ASM_NIOS2_IO_H_ */
diff --git a/include/asm-nios2/opcodes.h b/include/asm-nios2/opcodes.h
new file mode 100755
index 0000000..211f8ba
--- /dev/null
+++ b/include/asm-nios2/opcodes.h
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NIOS2_OPCODES_H_
+#define __ASM_NIOS2_OPCODES_H_
+
+#define OPCODE_OP(inst)	((inst) & 0x3f)
+#define OPCODE_OPX(inst) (((inst)>>11) & 0x3f)
+#define OPCODE_RA(inst) (((inst)>>27) & 01f)
+#define OPCODE_RB(inst) (((inst)>>22) & 01f)
+#define OPCODE_RC(inst) (((inst)>>17) & 01f)
+
+/* I-TYPE (immediate) and J-TYPE (jump) opcodes
+ */
+#define OPCODE_CALL	0x00
+#define OPCODE_LDBU	0x03
+#define OPCODE_ADDI	0x04
+#define OPCODE_STB	0x05
+#define OPCODE_BR	0x06
+#define OPCODE_LDB	0x07
+#define OPCODE_CMPGEI	0x08
+#define OPCODE_LDHU	0x0B
+#define OPCODE_ANDI	0x0C
+#define OPCODE_STH	0x0D
+#define OPCODE_BGE	0x0E
+#define OPCODE_LDH	0x0F
+#define OPCODE_CMPLTI	0x10
+#define OPCODE_XORI	0x1C
+#define OPCODE_ORI	0x14
+#define OPCODE_STW	0x15
+#define OPCODE_BLT	0x16
+#define OPCODE_LDW	0x17
+#define OPCODE_CMPNEI	0x18
+#define OPCODE_BNE	0x1E
+#define OPCODE_CMPEQI	0x20
+#define OPCODE_LDBUIO	0x23
+#define OPCODE_MULI	0x24
+#define OPCODE_STBIO	0x25
+#define OPCODE_BEQ	0x26
+#define OPCODE_LDBIO	0x27
+#define OPCODE_CMPGEUI	0x28
+#define OPCODE_ANDHI	0x2C
+#define OPCODE_STHIO	0x2D
+#define OPCODE_BGEU	0x2E
+#define OPCODE_LDHIO	0x2F
+#define OPCODE_CMPLTUI	0x30
+#define OPCODE_CUSTOM	0x32
+#define OPCODE_INITD	0x33
+#define OPCODE_ORHI	0x34
+#define OPCODE_STWIO	0x35
+#define OPCODE_BLTU	0x36
+#define OPCODE_LDWIO	0x37
+#define OPCODE_RTYPE	0x3A
+#define OPCODE_LDHUIO	0x2B
+#define OPCODE_FLUSHD	0x3B
+#define OPCODE_XORHI	0x3C
+
+/* R-Type (register) OPX field encodings
+ */
+#define OPCODE_ERET	0x01
+#define OPCODE_ROLI	0x02
+#define OPCODE_ROL	0x03
+#define OPCODE_FLUSHP	0x04
+#define OPCODE_RET	0x05
+#define OPCODE_NOR	0x06
+#define OPCODE_MULXUU	0x07
+#define OPCODE_CMPGE	0x08
+#define OPCODE_BRET	0x09
+#define OPCODE_ROR	0x0B
+#define OPCODE_FLUSHI	0x0C
+#define OPCODE_JMP	0x0D
+#define OPCODE_AND	0x0E
+
+#define OPCODE_CMPLT	0x10
+#define OPCODE_SLLI	0x12
+#define OPCODE_SLL	0x13
+#define OPCODE_OR	0x16
+#define OPCODE_MULXSU	0x17
+#define OPCODE_CMPNE	0x18
+#define OPCODE_SRLI	0x1A
+#define OPCODE_SRL	0x1B
+#define OPCODE_NEXTPC	0x1C
+#define OPCODE_CALLR	0x1D
+#define OPCODE_XOR	0x1E
+#define OPCODE_MULXSS	0x1F
+
+#define OPCODE_CMPEQ	0x20
+#define OPCODE_CMPLTU	0x30
+#define OPCODE_ADD	0x31
+#define OPCODE_DIVU	0x24
+#define OPCODE_DIV	0x25
+#define OPCODE_RDCTL	0x26
+#define OPCODE_MUL	0x27
+#define OPCODE_CMPGEU	0x28
+#define OPCODE_TRAP	0x2D
+#define OPCODE_WRCTL	0x2E
+
+#define OPCODE_BREAK	0x34
+#define OPCODE_SYNC	0x36
+#define OPCODE_INITI	0x29
+#define OPCODE_SUB	0x39
+#define OPCODE_SRAI	0x3A
+#define OPCODE_SRA	0x3B
+
+/*Full instruction encodings for R-Type, without the R's ;-)
+ *
+ * TODO: BREAK, BRET, ERET, RET, SYNC (as needed)
+ */
+#define OPC_TRAP	0x003b683a
+
+#endif /* __ASM_NIOS2_OPCODES_H_ */
diff --git a/include/asm-nios2/posix_types.h b/include/asm-nios2/posix_types.h
new file mode 100755
index 0000000..c2deea6
--- /dev/null
+++ b/include/asm-nios2/posix_types.h
@@ -0,0 +1,63 @@
+#ifndef __ASM_NIOS2_POSIX_TYPES_H_
+#define __ASM_NIOS2_POSIX_TYPES_H_
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short	__kernel_dev_t;
+typedef unsigned long	__kernel_ino_t;
+typedef unsigned short	__kernel_mode_t;
+typedef unsigned short	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef unsigned short	__kernel_ipc_pid_t;
+typedef unsigned short	__kernel_uid_t;
+typedef unsigned short	__kernel_gid_t;
+typedef unsigned long	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef int		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned short	__kernel_old_uid_t;
+typedef unsigned short	__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long	__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define	__FD_SET(d, set)	((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+
+#undef	__FD_CLR
+#define	__FD_CLR(d, set)	((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+
+#undef	__FD_ISSET
+#define	__FD_ISSET(d, set)	((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* __ASM_NIOS2_POSIX_TYPES_H_ */
diff --git a/include/asm-nios2/processor.h b/include/asm-nios2/processor.h
new file mode 100755
index 0000000..68502a5
--- /dev/null
+++ b/include/asm-nios2/processor.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NIOS2_PROCESSOR_H_
+#define __ASM_NIOS2_PROCESSOR_H_
+#endif /* __ASM_NIOS2_PROCESSOR_H_ */
diff --git a/include/asm-nios2/psr.h b/include/asm-nios2/psr.h
new file mode 100755
index 0000000..a498b46
--- /dev/null
+++ b/include/asm-nios2/psr.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NIOS2_PSR_H_
+#define __ASM_NIOS2_PSR_H_
+
+
+#endif /* __ASM_NIOS2_PSR_H_ */
diff --git a/include/asm-nios2/ptrace.h b/include/asm-nios2/ptrace.h
new file mode 100755
index 0000000..5430880
--- /dev/null
+++ b/include/asm-nios2/ptrace.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_NIOS2_PTRACE_H_
+#define __ASM_NIOS2_PTRACE_H_
+
+struct pt_regs {
+	unsigned reg[32];
+	unsigned status;
+};
+
+
+#endif /* __ASM_NIOS2_PTRACE_H_ */
diff --git a/include/asm-nios2/status_led.h b/include/asm-nios2/status_led.h
new file mode 100755
index 0000000..20f8d90
--- /dev/null
+++ b/include/asm-nios2/status_led.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_STATUS_LED_H__
+#define __ASM_STATUS_LED_H__
+
+typedef unsigned led_id_t;
+extern void __led_init (led_id_t mask, int state);
+extern void __led_set (led_id_t mask, int state);
+inline void __led_toggle (led_id_t mask);
+
+#endif	/* __ASM_STATUS_LED_H__ */
diff --git a/include/asm-nios2/string.h b/include/asm-nios2/string.h
new file mode 100755
index 0000000..e864903
--- /dev/null
+++ b/include/asm-nios2/string.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_NIOS2_STRING_H_
+#define __ASM_NIOS2_STRING_H_
+
+#undef __HAVE_ARCH_STRRCHR
+extern char * strrchr(const char * s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char * strchr(const char * s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void * memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void * memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMSET
+extern void * memset(void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+extern void memzero(void *ptr, __kernel_size_t n);
+
+#endif /* __ASM_NIOS2_STRING_H_ */
diff --git a/include/asm-nios2/system.h b/include/asm-nios2/system.h
new file mode 100755
index 0000000..ec84f59
--- /dev/null
+++ b/include/asm-nios2/system.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_NIOS2_SYSTEM_H_
+#define __ASM_NIOS2_SYSTEM_H_
+
+#endif /* __ASM_NIOS2_SYSTEM_H */
diff --git a/include/asm-nios2/types.h b/include/asm-nios2/types.h
new file mode 100755
index 0000000..39e2641
--- /dev/null
+++ b/include/asm-nios2/types.h
@@ -0,0 +1,57 @@
+#ifndef __ASM_NIOS2_TYPES_H_
+#define __ASM_NIOS2_TYPES_H_
+
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue.  However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ */
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_NIOS2_TYPES_H */
diff --git a/include/asm-nios2/u-boot.h b/include/asm-nios2/u-boot.h
new file mode 100755
index 0000000..3f29962
--- /dev/null
+++ b/include/asm-nios2/u-boot.h
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __ASM_NIOS2_U_BOOT_H_
+#define __ASM_NIOS2_U_BOOT_H_
+
+typedef struct bd_info {
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+	unsigned long	bi_sramstart;	/* start of SRAM memory */
+	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
+	unsigned long	bi_baudrate;	/* Console Baudrate */
+} bd_t;
+
+
+#endif	/* __ASM_NIOS2_U_BOOT_H_ */
diff --git a/include/asm-ppc/5xx_immap.h b/include/asm-ppc/5xx_immap.h
new file mode 100755
index 0000000..8e57057
--- /dev/null
+++ b/include/asm-ppc/5xx_immap.h
@@ -0,0 +1,439 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation,
+ */
+
+/*
+ * File:		5xx_immap.h
+ *
+ * Discription:		MPC555 Internal Memory Map
+ *
+ */
+
+#ifndef __IMMAP_5XX__
+#define __IMMAP_5XX__
+
+/* System Configuration Registers.
+*/
+typedef	struct sys_conf {
+	uint sc_siumcr;
+	uint sc_sypcr;
+	char res1[6];
+	ushort sc_swsr;
+	uint sc_sipend;
+	uint sc_simask;
+	uint sc_siel;
+	uint sc_sivec;
+	uint sc_tesr;
+	uint sc_sgpiodt1;
+	uint sc_sgpiodt2;
+	uint sc_sgpiocr;
+	uint sc_emcr;
+	uint sc_res1aa;
+	uint sc_res1ab;
+	uint sc_pdmcr;
+	char res3[192];
+} sysconf5xx_t;
+
+
+/* Memory Controller Registers.
+*/
+typedef struct	mem_ctlr {
+	uint memc_br0;
+	uint memc_or0;
+	uint memc_br1;
+	uint memc_or1;
+	uint memc_br2;
+	uint memc_or2;
+	uint memc_br3;
+	uint memc_or3;
+	char res1[32];
+	uint memc_dmbr;
+	uint memc_dmor;
+	char res2[48];
+	ushort memc_mstat;
+	ushort memc_res4a;
+	char res3[132];
+} memctl5xx_t;
+
+/* System Integration Timers.
+*/
+typedef struct	sys_int_timers {
+	ushort sit_tbscr;
+	char res1[2];
+	uint sit_tbref0;
+	uint sit_tbref1;
+	char res2[20];
+	ushort sit_rtcsc;
+	char res3[2];
+	uint sit_rtc;
+	uint sit_rtsec;
+	uint sit_rtcal;
+	char res4[16];
+	ushort sit_piscr;
+	char res5[2];
+	uint sit_pitc;
+	uint sit_pitr;
+	char res6[52];
+} sit5xx_t;
+
+/* Clocks and Reset
+*/
+typedef struct clk_and_reset {
+	uint car_sccr;
+	uint car_plprcr;
+	ushort car_rsr;
+	ushort car_res7a;
+	ushort car_colir;
+	ushort car_res7b;
+	ushort car_vsrmcr;
+	ushort car_res7c;
+	char res1[108];
+
+} car5xx_t;
+
+#define TBSCR_TBE		((ushort)0x0001)
+
+/* System Integration Timer Keys
+*/
+typedef struct sitk {
+	uint sitk_tbscrk;
+	uint sitk_tbref0k;
+	uint sitk_tbref1k;
+	uint sitk_tbk;
+	char res1[16];
+	uint sitk_rtcsck;
+	uint sitk_rtck;
+	uint sitk_rtseck;
+	uint sitk_rtcalk;
+	char res2[16];
+	uint sitk_piscrk;
+	uint sitk_pitck;
+	char res3[56];
+} sitk5xx_t;
+
+/* Clocks and Reset Keys.
+*/
+typedef struct cark {
+	uint	cark_sccrk;
+	uint	cark_plprcrk;
+	uint	cark_rsrk;
+	char	res1[1140];
+} cark8xx_t;
+
+/* The key to unlock registers maintained by keep-alive power.
+*/
+#define KAPWR_KEY	((unsigned int)0x55ccaa33)
+
+/* Flash Configuration
+*/
+typedef struct fl {
+	uint fl_cmfmcr;
+	uint fl_cmftst;
+	uint fl_cmfctl;
+	char res1[52];
+} fl5xx_t;
+
+/* Dpram Control
+*/
+typedef struct dprc {
+	ushort dprc_dptmcr;
+	ushort dprc_ramtst;
+	ushort dprc_rambar;
+	ushort dprc_misrh;
+	ushort dprc_misrl;
+	ushort dprc_miscnt;
+} dprc5xx_t;
+
+/* Time Processor Unit
+*/
+typedef struct tpu {
+	ushort tpu_tpumcr;
+	ushort tpu_tcr;
+	ushort tpu_dscr;
+	ushort tpu_dssr;
+	ushort tpu_ticr;
+	ushort tpu_cier;
+	ushort tpu_cfsr0;
+	ushort tpu_cfsr1;
+	ushort tpu_cfsr2;
+	ushort tpu_cfsr3;
+	ushort tpu_hsqr0;
+	ushort tpu_hsqr1;
+	ushort tpu_hsrr0;
+	ushort tpu_hsrr1;
+	ushort tpu_cpr0;
+	ushort tpu_cpr1;
+	ushort tpu_cisr;
+	ushort tpu_lr;
+	ushort tpu_sglr;
+	ushort tpu_dcnr;
+	ushort tpu_tpumcr2;
+	ushort tpu_tpumcr3;
+	ushort tpu_isdr;
+	ushort tpu_iscr;
+	char   res1[208];
+	char   tpu[16][16];
+	char   res2[512];
+} tpu5xx_t;
+
+/* QADC
+*/
+typedef struct qadc {
+	ushort qadc_64mcr;
+	ushort qadc_64test;
+	ushort qadc_64int;
+	u_char  qadc_portqa;
+	u_char  qadc_portqb;
+	ushort qadc_ddrqa;
+	ushort qadc_qacr0;
+	ushort qadc_qacr1;
+	ushort qadc_qacr2;
+	ushort qadc_qasr0;
+	ushort qadc_qasr1;
+	char   res1[492];
+       /* command convertion word table */
+	ushort qadc_ccw[64];
+       /* result word table, unsigned right justified */
+	ushort qadc_rjurr[64];
+       /* result word table, signed left justified */
+	ushort qadc_ljsrr[64];
+       /* result word table, unsigned left justified */
+	ushort qadc_ljurr[64];
+} qadc5xx_t;
+
+/* QSMCM
+*/
+typedef struct qsmcm {
+	ushort qsmcm_qsmcr;
+	ushort qsmcm_qtest;
+	ushort qsmcm_qdsci_il;
+	ushort qsmcm_qspi_il;
+	ushort qsmcm_scc1r0;
+	ushort qsmcm_scc1r1;
+	ushort qsmcm_sc1sr;
+	ushort qsmcm_sc1dr;
+	char   res1[2];
+	char   res2[2];
+	ushort qsmcm_portqs;
+	u_char qsmcm_pqspar;
+	u_char qsmcm_ddrqs;
+	ushort qsmcm_spcr0;
+	ushort qsmcm_spcr1;
+	ushort qsmcm_spcr2;
+	u_char qsmcm_spcr3;
+	u_char qsmcm_spsr;
+	ushort qsmcm_scc2r0;
+	ushort qsmcm_scc2r1;
+	ushort qsmcm_sc2sr;
+	ushort qsmcm_sc2dr;
+	ushort qsmcm_qsci1cr;
+	ushort qsmcm_qsci1sr;
+	ushort qsmcm_sctq[16];
+	ushort qsmcm_scrq[16];
+	char   res3[212];
+	ushort qsmcm_recram[32];
+	ushort qsmcm_tranram[32];
+	u_char qsmcm_comdram[32];
+	char   res[3616];
+} qsmcm5xx_t;
+
+
+/* MIOS
+*/
+
+typedef struct mios {
+	ushort mios_mpwmsm0perr;                 /* mpwmsm0 */
+	ushort mios_mpwmsm0pulr;
+	ushort mios_mpwmsm0cntr;
+	ushort mios_mpwmsm0scr;
+	ushort mios_mpwmsm1perr;                 /* mpwmsm1 */
+	ushort mios_mpwmsm1pulr;
+	ushort mios_mpwmsm1cntr;
+	ushort mios_mpwmsm1scr;
+	ushort mios_mpwmsm2perr;                 /* mpwmsm2 */
+	ushort mios_mpwmsm2pulr;
+	ushort mios_mpwmsm2cntr;
+	ushort mios_mpwmsm2scr;
+	ushort mios_mpwmsm3perr;                 /* mpwmsm3 */
+	ushort mios_mpwmsm3pulr;
+	ushort mios_mpwmsm3cntr;
+	ushort mios_mpwmsm3scr;
+	char res1[16];
+	ushort mios_mmcsm6cnt;                   /* mmcsm6 */
+	ushort mios_mmcsm6mlr;
+	ushort mios_mmcsm6scrd, mmcsm6scr;
+	char res2[32];
+	ushort mios_mdasm11ar;                   /* mdasm11 */
+	ushort mios_mdasm11br;
+	ushort mios_mdasm11scrd, mdasm11scr;
+	ushort mios_mdasm12ar;                   /* mdasm12 */
+	ushort mios_mdasm12br;
+	ushort mios_mdasm12scrd, mdasm12scr;
+	ushort mios_mdasm13ar;                   /* mdasm13 */
+	ushort mios_mdasm13br;
+	ushort mios_mdasm13scrd, mdasm13scr;
+	ushort mios_mdasm14ar;                   /* mdasm14 */
+	ushort mios_mdasm14br;
+	ushort mios_mdasm14scrd, mdasm14scr;
+	ushort mios_mdasm15ar;                   /* mdasm15 */
+	ushort mios_mdasm15br;
+	ushort mios_mdasm15scrd, mdasm15scr;
+	ushort mios_mpwmsm16perr;                /* mpwmsm16 */
+	ushort mios_mpwmsm16pulr;
+	ushort mios_mpwmsm16cntr;
+	ushort mios_mpwmsm16scr;
+	ushort mios_mpwmsm17perr;                /* mpwmsm17 */
+	ushort mios_mpwmsm17pulr;
+	ushort mios_mpwmsm17cntr;
+	ushort mios_mpwmsm17scr;
+	ushort mios_mpwmsm18perr;                /* mpwmsm18 */
+	ushort mios_mpwmsm18pulr;
+	ushort mios_mpwmsm18cntr;
+	ushort mios_mpwmsm18scr;
+	ushort mios_mpwmsm19perr;                /* mpwmsm19 */
+	ushort mios_mpwmsm19pulr;
+	ushort mios_mpwmsm19cntr;
+	ushort mios_mpwmsm19scr;
+	char res3[16];
+	ushort mios_mmcsm22cnt;                  /* mmcsm22 */
+	ushort mios_mmcsm22mlr;
+	ushort mios_mmcsm22scrd, mmcsm22scr;
+	char res4[32];
+	ushort mios_mdasm27ar;                   /* mdasm27 */
+	ushort mios_mdasm27br;
+	ushort mios_mdasm27scrd, mdasm27scr;
+	ushort mios_mdasm28ar;                   /*mdasm28 */
+	ushort mios_mdasm28br;
+	ushort mios_mdasm28scrd, mdasm28scr;
+	ushort mios_mdasm29ar;                   /* mdasm29 */
+	ushort mios_mdasm29br;
+	ushort mios_mdasm29scrd, mdasm29scr;
+	ushort mios_mdasm30ar;                   /* mdasm30 */
+	ushort mios_mdasm30br;
+	ushort mios_mdasm30scrd, mdasm30scr;
+	ushort mios_mdasm31ar;                   /* mdasm31 */
+	ushort mios_mdasm31br;
+	ushort mios_mdasm31scrd, mdasm31scr;
+	ushort mios_mpiosm32dr;
+	ushort mios_mpiosm32ddr;
+	char res5[1788];
+	ushort mios_mios1tpcr;
+	char mios_res13[2];
+	ushort mios_mios1vnr;
+	ushort mios_mios1mcr;
+	char res6[12];
+	ushort mios_res42z;
+	ushort mios_mcpsmscr;
+	char res7[1000];
+	ushort mios_mios1sr0;
+	char res12[2];
+	ushort mios_mios1er0;
+	ushort mios_mios1rpr0;
+	char res8[40];
+	ushort mios_mios1lvl0;
+	char res9[14];
+	ushort mios_mios1sr1;
+	char res10[2];
+	ushort mios_mios1er1;
+	ushort mios_mios1rpr1;
+	char res11[40];
+	ushort mios_mios1lvl1;
+	char res13[1038];
+} mios5xx_t;
+
+/* Toucan Module
+*/
+typedef struct tcan {
+	ushort tcan_tcnmcr;
+	ushort tcan_cantcr;
+	ushort tcan_canicr;
+	u_char tcan_canctrl0;
+	u_char tcan_canctrl1;
+	u_char tcan_presdiv;
+	u_char tcan_canctrl2;
+	ushort tcan_timer;
+	char res1[4];
+	ushort tcan_rxgmskhi;
+	ushort tcan_rxgmsklo;
+	ushort tcan_rx14mskhi;
+	ushort tcan_rx14msklo;
+	ushort tcan_rx15mskhi;
+	ushort tcan_rx15msklo;
+	char res2[4];
+	ushort tcan_estat;
+	ushort tcan_imask;
+	ushort tcan_iflag;
+	u_char tcan_rxectr;
+	u_char tcan_txectr;
+	char res3[88];
+	struct {
+	       ushort scr;
+	       ushort id_high;
+	       ushort id_low;
+	       u_char data[8];
+		   char res4[2];
+	    } tcan_mbuff[16];
+	    char res5[640];
+} tcan5xx_t;
+
+/* UIMB
+*/
+typedef struct uimb {
+	uint uimb_umcr;
+	char res1[12];
+	uint uimb_utstcreg;
+	char res2[12];
+	uint uimb_uipend;
+} uimb5xx_t;
+
+
+/* Internal Memory Map MPC555
+*/
+typedef struct immap {
+	char               res1[262144];       	/* CMF Flash A 256 Kbytes */
+	char               res2[196608];       	/* CMF Flash B 192 Kbytes */
+	char               res3[2670592];      	/* Reserved for Flash */
+	sysconf5xx_t       im_siu_conf;        	/* SIU Configuration */
+	memctl5xx_t	   im_memctl;		/* Memory Controller */
+	sit5xx_t           im_sit;		/* System Integration Timers */
+	car5xx_t	   im_clkrst;		/* Clocks and Reset */
+	sitk5xx_t          im_sitk;            	/* System Integration Timer Keys*/
+	cark8xx_t          im_clkrstk;         	/* Clocks and Resert Keys */
+	fl5xx_t	           im_fla;	        /* Flash Module A */
+	fl5xx_t	           im_flb;	        /* Flash Module B */
+	char               res4[14208];        	/* Reserved for SIU */
+	dprc5xx_t	   im_dprc;            	/* Dpram Control Register */
+	char               res5[8180];         	/* Reserved */
+	char               dptram[6144];       	/* Dptram */
+	char               res6[2048];         	/* Reserved */
+	tpu5xx_t	   im_tpua;		/* Time Proessing Unit A */
+	tpu5xx_t	   im_tpub;  	      	/* Time Processing Unit B */
+	qadc5xx_t	   im_qadca;           	/* QADC A */
+	qadc5xx_t	   im_qadcb;           	/* QADC B */
+	qsmcm5xx_t	   im_qsmcm;		/* SCI and SPI */
+	mios5xx_t      	   im_mios;		/* MIOS */
+	tcan5xx_t          im_tcana;           	/* Toucan A */
+	tcan5xx_t          im_tcanb;	       	/* Toucan B */
+	char               res7[1792];         	/* Reserved */
+	uimb5xx_t          im_uimb;	        /* UIMB */
+} immap_t;
+
+#endif /* __IMMAP_5XX__ */
diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h
new file mode 100755
index 0000000..40679cb
--- /dev/null
+++ b/include/asm-ppc/8xx_immap.h
@@ -0,0 +1,511 @@
+
+/*
+ * MPC8xx Internal Memory Map
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * The I/O on the MPC860 is comprised of blocks of special registers
+ * and the dual port ram for the Communication Processor Module.
+ * Within this space are functional units such as the SIU, memory
+ * controller, system timers, and other control functions.  It is
+ * a combination that I found difficult to separate into logical
+ * functional files.....but anyone else is welcome to try.  -- Dan
+ */
+#ifndef __IMMAP_8XX__
+#define __IMMAP_8XX__
+
+/* System configuration registers.
+*/
+typedef	struct sys_conf {
+	uint	sc_siumcr;
+	uint	sc_sypcr;
+	uint	sc_swt;
+	char	res1[2];
+	ushort	sc_swsr;
+	uint	sc_sipend;
+	uint	sc_simask;
+	uint	sc_siel;
+	uint	sc_sivec;
+	uint	sc_tesr;
+	char	res2[0xc];
+	uint	sc_sdcr;
+	char	res3[0x4c];
+} sysconf8xx_t;
+
+/* PCMCIA configuration registers.
+*/
+typedef struct pcmcia_conf {
+	uint	pcmc_pbr0;
+	uint	pcmc_por0;
+	uint	pcmc_pbr1;
+	uint	pcmc_por1;
+	uint	pcmc_pbr2;
+	uint	pcmc_por2;
+	uint	pcmc_pbr3;
+	uint	pcmc_por3;
+	uint	pcmc_pbr4;
+	uint	pcmc_por4;
+	uint	pcmc_pbr5;
+	uint	pcmc_por5;
+	uint	pcmc_pbr6;
+	uint	pcmc_por6;
+	uint	pcmc_pbr7;
+	uint	pcmc_por7;
+	char	res1[0x20];
+	uint	pcmc_pgcra;
+	uint	pcmc_pgcrb;
+	uint	pcmc_pscr;
+	char	res2[4];
+	uint	pcmc_pipr;
+	char	res3[4];
+	uint	pcmc_per;
+	char	res4[4];
+} pcmconf8xx_t;
+
+/* Memory controller registers.
+*/
+typedef struct	mem_ctlr {
+	uint	memc_br0;
+	uint	memc_or0;
+	uint	memc_br1;
+	uint	memc_or1;
+	uint	memc_br2;
+	uint	memc_or2;
+	uint	memc_br3;
+	uint	memc_or3;
+	uint	memc_br4;
+	uint	memc_or4;
+	uint	memc_br5;
+	uint	memc_or5;
+	uint	memc_br6;
+	uint	memc_or6;
+	uint	memc_br7;
+	uint	memc_or7;
+	char	res1[0x24];
+	uint	memc_mar;
+	uint	memc_mcr;
+	char	res2[4];
+	uint	memc_mamr;
+	uint	memc_mbmr;
+	ushort	memc_mstat;
+	ushort	memc_mptpr;
+	uint	memc_mdr;
+	char	res3[0x80];
+} memctl8xx_t;
+
+/* System Integration Timers.
+*/
+typedef struct	sys_int_timers {
+	ushort	sit_tbscr;
+	char	res0[0x02];
+	uint	sit_tbreff0;
+	uint	sit_tbreff1;
+	char	res1[0x14];
+	ushort	sit_rtcsc;
+	char	res2[0x02];
+	uint	sit_rtc;
+	uint	sit_rtsec;
+	uint	sit_rtcal;
+	char	res3[0x10];
+	ushort	sit_piscr;
+	char	res4[2];
+	uint	sit_pitc;
+	uint	sit_pitr;
+	char	res5[0x34];
+} sit8xx_t;
+
+#define TBSCR_TBIRQ_MASK	((ushort)0xff00)
+#define TBSCR_REFA		((ushort)0x0080)
+#define TBSCR_REFB		((ushort)0x0040)
+#define TBSCR_REFAE		((ushort)0x0008)
+#define TBSCR_REFBE		((ushort)0x0004)
+#define TBSCR_TBF		((ushort)0x0002)
+#define TBSCR_TBE		((ushort)0x0001)
+
+#define RTCSC_RTCIRQ_MASK	((ushort)0xff00)
+#define RTCSC_SEC		((ushort)0x0080)
+#define RTCSC_ALR		((ushort)0x0040)
+#define RTCSC_38K		((ushort)0x0010)
+#define RTCSC_SIE		((ushort)0x0008)
+#define RTCSC_ALE		((ushort)0x0004)
+#define RTCSC_RTF		((ushort)0x0002)
+#define RTCSC_RTE		((ushort)0x0001)
+
+#define PISCR_PIRQ_MASK		((ushort)0xff00)
+#define PISCR_PS		((ushort)0x0080)
+#define PISCR_PIE		((ushort)0x0004)
+#define PISCR_PTF		((ushort)0x0002)
+#define PISCR_PTE		((ushort)0x0001)
+
+/* Clocks and Reset.
+*/
+typedef struct clk_and_reset {
+	uint	car_sccr;
+	uint	car_plprcr;
+	uint	car_rsr;
+	char	res[0x74];        /* Reserved area                  */
+} car8xx_t;
+
+/* System Integration Timers keys.
+*/
+typedef struct sitk {
+	uint	sitk_tbscrk;
+	uint	sitk_tbreff0k;
+	uint	sitk_tbreff1k;
+	uint	sitk_tbk;
+	char	res1[0x10];
+	uint	sitk_rtcsck;
+	uint	sitk_rtck;
+	uint	sitk_rtseck;
+	uint	sitk_rtcalk;
+	char	res2[0x10];
+	uint	sitk_piscrk;
+	uint	sitk_pitck;
+	char	res3[0x38];
+} sitk8xx_t;
+
+/* Clocks and reset keys.
+*/
+typedef struct cark {
+	uint	cark_sccrk;
+	uint	cark_plprcrk;
+	uint	cark_rsrk;
+	char	res[0x474];
+} cark8xx_t;
+
+/* The key to unlock registers maintained by keep-alive power.
+*/
+#define KAPWR_KEY	((unsigned int)0x55ccaa33)
+
+/* Video interface.  MPC823 Only.
+*/
+typedef struct vid823 {
+	ushort	vid_vccr;
+	ushort	res1;
+	u_char	vid_vsr;
+	u_char	res2;
+	u_char	vid_vcmr;
+	u_char	res3;
+	uint	vid_vbcb;
+	uint	res4;
+	uint	vid_vfcr0;
+	uint	vid_vfaa0;
+	uint	vid_vfba0;
+	uint	vid_vfcr1;
+	uint	vid_vfaa1;
+	uint	vid_vfba1;
+	u_char	res5[0x18];
+} vid823_t;
+
+/* LCD interface.  823 Only.
+*/
+typedef struct lcd {
+	uint	lcd_lccr;
+	uint	lcd_lchcr;
+	uint	lcd_lcvcr;
+	char	res1[4];
+	uint	lcd_lcfaa;
+	uint	lcd_lcfba;
+	char	lcd_lcsr;
+	char	res2[0x7];
+} lcd823_t;
+
+/* I2C
+*/
+typedef struct i2c {
+	u_char	i2c_i2mod;
+	char	res1[3];
+	u_char	i2c_i2add;
+	char	res2[3];
+	u_char	i2c_i2brg;
+	char	res3[3];
+	u_char	i2c_i2com;
+	char	res4[3];
+	u_char	i2c_i2cer;
+	char	res5[3];
+	u_char	i2c_i2cmr;
+	char	res6[0x8b];
+} i2c8xx_t;
+
+/* DMA control/status registers.
+*/
+typedef struct sdma_csr {
+	char	res1[4];
+	uint	sdma_sdar;
+	u_char	sdma_sdsr;
+	char	res3[3];
+	u_char	sdma_sdmr;
+	char	res4[3];
+	u_char	sdma_idsr1;
+	char	res5[3];
+	u_char	sdma_idmr1;
+	char	res6[3];
+	u_char	sdma_idsr2;
+	char	res7[3];
+	u_char	sdma_idmr2;
+	char	res8[0x13];
+} sdma8xx_t;
+
+/* Communication Processor Module Interrupt Controller.
+*/
+typedef struct cpm_ic {
+	ushort	cpic_civr;
+	char	res[0xe];
+	uint	cpic_cicr;
+	uint	cpic_cipr;
+	uint	cpic_cimr;
+	uint	cpic_cisr;
+} cpic8xx_t;
+
+/* Input/Output Port control/status registers.
+*/
+typedef struct io_port {
+	ushort	iop_padir;
+	ushort	iop_papar;
+	ushort	iop_paodr;
+	ushort	iop_padat;
+	char	res1[8];
+	ushort	iop_pcdir;
+	ushort	iop_pcpar;
+	ushort	iop_pcso;
+	ushort	iop_pcdat;
+	ushort	iop_pcint;
+	char	res2[6];
+	ushort	iop_pddir;
+	ushort	iop_pdpar;
+	char	res3[2];
+	ushort	iop_pddat;
+	uint	utmode;
+	char	res4[4];
+} iop8xx_t;
+
+/* Communication Processor Module Timers
+*/
+typedef struct cpm_timers {
+	ushort	cpmt_tgcr;
+	char	res1[0xe];
+	ushort	cpmt_tmr1;
+	ushort	cpmt_tmr2;
+	ushort	cpmt_trr1;
+	ushort	cpmt_trr2;
+	ushort	cpmt_tcr1;
+	ushort	cpmt_tcr2;
+	ushort	cpmt_tcn1;
+	ushort	cpmt_tcn2;
+	ushort	cpmt_tmr3;
+	ushort	cpmt_tmr4;
+	ushort	cpmt_trr3;
+	ushort	cpmt_trr4;
+	ushort	cpmt_tcr3;
+	ushort	cpmt_tcr4;
+	ushort	cpmt_tcn3;
+	ushort	cpmt_tcn4;
+	ushort	cpmt_ter1;
+	ushort	cpmt_ter2;
+	ushort	cpmt_ter3;
+	ushort	cpmt_ter4;
+	char	res2[8];
+} cpmtimer8xx_t;
+
+/* Finally, the Communication Processor stuff.....
+*/
+typedef struct scc {		/* Serial communication channels */
+	uint	scc_gsmrl;
+	uint	scc_gsmrh;
+	ushort	scc_psmr;
+	char	res1[2];
+	ushort	scc_todr;
+	ushort	scc_dsr;
+	ushort	scc_scce;
+	char	res2[2];
+	ushort	scc_sccm;
+	char	res3;
+	u_char	scc_sccs;
+	char	res4[8];
+} scc_t;
+
+typedef struct smc {		/* Serial management channels */
+	char	res1[2];
+	ushort	smc_smcmr;
+	char	res2[2];
+	u_char	smc_smce;
+	char	res3[3];
+	u_char	smc_smcm;
+	char	res4[5];
+} smc_t;
+
+/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
+ * it fits within the address space.
+ */
+
+typedef struct fec {
+	uint	fec_addr_low;		/* lower 32 bits of station address	*/
+	ushort	fec_addr_high;		/* upper 16 bits of station address	*/
+	ushort	res1;			/* reserved				*/
+	uint	fec_hash_table_high;	/* upper 32-bits of hash table		*/
+	uint	fec_hash_table_low;	/* lower 32-bits of hash table		*/
+	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
+	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
+	uint	fec_r_buff_size;	/* Rx buffer size			*/
+	uint	res2[9];		/* reserved				*/
+	uint	fec_ecntrl;		/* ethernet control register		*/
+	uint	fec_ievent;		/* interrupt event register		*/
+	uint	fec_imask;		/* interrupt mask register		*/
+	uint	fec_ivec;		/* interrupt level and vector status	*/
+	uint	fec_r_des_active;	/* Rx ring updated flag			*/
+	uint	fec_x_des_active;	/* Tx ring updated flag			*/
+	uint	res3[10];		/* reserved				*/
+	uint	fec_mii_data;		/* MII data register			*/
+	uint	fec_mii_speed;		/* MII speed control register		*/
+	uint	res4[17];		/* reserved				*/
+	uint	fec_r_bound;		/* end of RAM (read-only)		*/
+	uint	fec_r_fstart;		/* Rx FIFO start address		*/
+	uint	res5[6];		/* reserved				*/
+	uint	fec_x_fstart;		/* Tx FIFO start address		*/
+	uint	res6[17];		/* reserved				*/
+	uint	fec_fun_code;		/* fec SDMA function code		*/
+	uint	res7[3];		/* reserved				*/
+	uint	fec_r_cntrl;		/* Rx control register			*/
+	uint	fec_r_hash;		/* Rx hash register			*/
+	uint	res8[14];		/* reserved				*/
+	uint	fec_x_cntrl;		/* Tx control register			*/
+	uint	res9[0x1e];		/* reserved				*/
+} fec_t;
+
+/* The FEC and LCD color map share the same address space....
+ * I guess we will never see an 823T :-).
+ */
+union fec_lcd {
+	fec_t	fl_un_fec;
+	u_char	fl_un_cmap[0x200];
+};
+
+typedef struct comm_proc {
+	/* General control and status registers.
+	*/
+	ushort	cp_cpcr;
+	u_char	res1[2];
+	ushort	cp_rccr;
+	u_char	res2;
+	u_char	cp_rmds;
+	u_char	res3[4];
+	ushort	cp_cpmcr1;
+	ushort	cp_cpmcr2;
+	ushort	cp_cpmcr3;
+	ushort	cp_cpmcr4;
+	u_char	res4[2];
+	ushort	cp_rter;
+	u_char	res5[2];
+	ushort	cp_rtmr;
+	u_char	res6[0x14];
+
+	/* Baud rate generators.
+	*/
+	uint	cp_brgc1;
+	uint	cp_brgc2;
+	uint	cp_brgc3;
+	uint	cp_brgc4;
+
+	/* Serial Communication Channels.
+	*/
+	scc_t	cp_scc[4];
+
+	/* Serial Management Channels.
+	*/
+	smc_t	cp_smc[2];
+
+	/* Serial Peripheral Interface.
+	*/
+	ushort	cp_spmode;
+	u_char	res7[4];
+	u_char	cp_spie;
+	u_char	res8[3];
+	u_char	cp_spim;
+	u_char	res9[2];
+	u_char	cp_spcom;
+	u_char	res10[2];
+
+	/* Parallel Interface Port.
+	*/
+	u_char	res11[2];
+	ushort	cp_pipc;
+	u_char	res12[2];
+	ushort	cp_ptpr;
+	uint	cp_pbdir;
+	uint	cp_pbpar;
+	u_char	res13[2];
+	ushort	cp_pbodr;
+	uint	cp_pbdat;
+
+	/* Port E - MPC87x/88x only.
+	 */
+	uint	cp_pedir;
+	uint	cp_pepar;
+	uint	cp_peso;
+	uint	cp_peodr;
+	uint	cp_pedat;
+
+	/* Communications Processor Timing Register -
+	   Contains RMII Timing for the FECs on MPC87x/88x only.
+	*/
+	uint	cp_cptr;
+
+	/* Serial Interface and Time Slot Assignment.
+	*/
+	uint	cp_simode;
+	u_char	cp_sigmr;
+	u_char	res15;
+	u_char	cp_sistr;
+	u_char	cp_sicmr;
+	u_char	res16[4];
+	uint	cp_sicr;
+	uint	cp_sirp;
+	u_char	res17[0xc];
+
+	/* 256 bytes of MPC823 video controller RAM array.
+	*/
+	u_char	cp_vcram[0x100];
+	u_char	cp_siram[0x200];
+
+	/* The fast ethernet controller is not really part of the CPM,
+	 * but it resides in the address space.
+	 * The LCD color map is also here.
+	 */
+	union	fec_lcd	fl_un;
+#define cp_fec		fl_un.fl_un_fec
+#define lcd_cmap	fl_un.fl_un_cmap
+	char	res18[0xE00];
+
+	/* The MPC885 family has a second FEC here */
+	fec_t	cp_fec2;
+#define cp_fec1	cp_fec	/* consistency macro */
+
+	/* Dual Ported RAM follows.
+	 * There are many different formats for this memory area
+	 * depending upon the devices used and options chosen.
+	 * Some processors don't have all of it populated.
+	 */
+	u_char	cp_dpmem[0x1C00];	/* BD / Data / ucode */
+	u_char	cp_dparam[0x400];	/* Parameter RAM */
+} cpm8xx_t;
+
+/* Internal memory map.
+*/
+typedef struct immap {
+	sysconf8xx_t	im_siu_conf;	/* SIU Configuration */
+	pcmconf8xx_t	im_pcmcia;	/* PCMCIA Configuration */
+	memctl8xx_t	im_memctl;	/* Memory Controller */
+	sit8xx_t	im_sit;		/* System integration timers */
+	car8xx_t	im_clkrst;	/* Clocks and reset */
+	sitk8xx_t	im_sitk;	/* Sys int timer keys */
+	cark8xx_t	im_clkrstk;	/* Clocks and reset keys */
+	vid823_t	im_vid;		/* Video (823 only) */
+	lcd823_t	im_lcd;		/* LCD (823 only) */
+	i2c8xx_t	im_i2c;		/* I2C control/status */
+	sdma8xx_t	im_sdma;	/* SDMA control/status */
+	cpic8xx_t	im_cpic;	/* CPM Interrupt Controller */
+	iop8xx_t	im_ioport;	/* IO Port control/status */
+	cpmtimer8xx_t	im_cpmtimer;	/* CPM timers */
+	cpm8xx_t	im_cpm;		/* Communication processor */
+} immap_t;
+
+#endif /* __IMMAP_8XX__ */
diff --git a/include/asm-ppc/atomic.h b/include/asm-ppc/atomic.h
new file mode 100755
index 0000000..23f22df
--- /dev/null
+++ b/include/asm-ppc/atomic.h
@@ -0,0 +1,95 @@
+/*
+ * PowerPC atomic operations
+ */
+
+#ifndef _ASM_PPC_ATOMIC_H_
+#define _ASM_PPC_ATOMIC_H_
+
+#include <linux/config.h>
+
+#ifdef CONFIG_SMP
+typedef struct { volatile int counter; } atomic_t;
+#else
+typedef struct { int counter; } atomic_t;
+#endif
+
+#define ATOMIC_INIT(i)	{ (i) }
+
+#define atomic_read(v)		((v)->counter)
+#define atomic_set(v,i)		(((v)->counter) = (i))
+
+extern void atomic_clear_mask(unsigned long mask, unsigned long *addr);
+extern void atomic_set_mask(unsigned long mask, unsigned long *addr);
+
+extern __inline__ int atomic_add_return(int a, atomic_t *v)
+{
+	int t;
+
+	__asm__ __volatile__("\n\
+1:	lwarx	%0,0,%3\n\
+	add	%0,%2,%0\n\
+	stwcx.	%0,0,%3\n\
+	bne-	1b"
+	: "=&r" (t), "=m" (*v)
+	: "r" (a), "r" (v), "m" (*v)
+	: "cc");
+
+	return t;
+}
+
+extern __inline__ int atomic_sub_return(int a, atomic_t *v)
+{
+	int t;
+
+	__asm__ __volatile__("\n\
+1:	lwarx	%0,0,%3\n\
+	subf	%0,%2,%0\n\
+	stwcx.	%0,0,%3\n\
+	bne-	1b"
+	: "=&r" (t), "=m" (*v)
+	: "r" (a), "r" (v), "m" (*v)
+	: "cc");
+
+	return t;
+}
+
+extern __inline__ int atomic_inc_return(atomic_t *v)
+{
+	int t;
+
+	__asm__ __volatile__("\n\
+1:	lwarx	%0,0,%2\n\
+	addic	%0,%0,1\n\
+	stwcx.	%0,0,%2\n\
+	bne-	1b"
+	: "=&r" (t), "=m" (*v)
+	: "r" (v), "m" (*v)
+	: "cc");
+
+	return t;
+}
+
+extern __inline__ int atomic_dec_return(atomic_t *v)
+{
+	int t;
+
+	__asm__ __volatile__("\n\
+1:	lwarx	%0,0,%2\n\
+	addic	%0,%0,-1\n\
+	stwcx.	%0,0,%2\n\
+	bne	1b"
+	: "=&r" (t), "=m" (*v)
+	: "r" (v), "m" (*v)
+	: "cc");
+
+	return t;
+}
+
+#define atomic_add(a, v)		((void) atomic_add_return((a), (v)))
+#define atomic_sub(a, v)		((void) atomic_sub_return((a), (v)))
+#define atomic_sub_and_test(a, v)	(atomic_sub_return((a), (v)) == 0)
+#define atomic_inc(v)			((void) atomic_inc_return((v)))
+#define atomic_dec(v)			((void) atomic_dec_return((v)))
+#define atomic_dec_and_test(v)		(atomic_dec_return((v)) == 0)
+
+#endif /* _ASM_PPC_ATOMIC_H_ */
diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h
new file mode 100755
index 0000000..3264915
--- /dev/null
+++ b/include/asm-ppc/bitops.h
@@ -0,0 +1,333 @@
+/*
+ * bitops.h: Bit string operations on the ppc
+ */
+
+#ifndef _PPC_BITOPS_H
+#define _PPC_BITOPS_H
+
+#include <linux/config.h>
+#include <asm/byteorder.h>
+
+extern void set_bit(int nr, volatile void *addr);
+extern void clear_bit(int nr, volatile void *addr);
+extern void change_bit(int nr, volatile void *addr);
+extern int test_and_set_bit(int nr, volatile void *addr);
+extern int test_and_clear_bit(int nr, volatile void *addr);
+extern int test_and_change_bit(int nr, volatile void *addr);
+
+/*
+ * Arguably these bit operations don't imply any memory barrier or
+ * SMP ordering, but in fact a lot of drivers expect them to imply
+ * both, since they do on x86 cpus.
+ */
+#ifdef CONFIG_SMP
+#define SMP_WMB		"eieio\n"
+#define SMP_MB		"\nsync"
+#else
+#define SMP_WMB
+#define SMP_MB
+#endif /* CONFIG_SMP */
+
+#define __INLINE_BITOPS	1
+
+#if __INLINE_BITOPS
+/*
+ * These used to be if'd out here because using : "cc" as a constraint
+ * resulted in errors from egcs.  Things may be OK with gcc-2.95.
+ */
+extern __inline__ void set_bit(int nr, volatile void * addr)
+{
+	unsigned long old;
+	unsigned long mask = 1 << (nr & 0x1f);
+	unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+
+	__asm__ __volatile__(SMP_WMB "\
+1:	lwarx	%0,0,%3\n\
+	or	%0,%0,%2\n\
+	stwcx.	%0,0,%3\n\
+	bne	1b"
+	SMP_MB
+	: "=&r" (old), "=m" (*p)
+	: "r" (mask), "r" (p), "m" (*p)
+	: "cc" );
+}
+
+extern __inline__ void clear_bit(int nr, volatile void *addr)
+{
+	unsigned long old;
+	unsigned long mask = 1 << (nr & 0x1f);
+	unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+
+	__asm__ __volatile__(SMP_WMB "\
+1:	lwarx	%0,0,%3\n\
+	andc	%0,%0,%2\n\
+	stwcx.	%0,0,%3\n\
+	bne	1b"
+	SMP_MB
+	: "=&r" (old), "=m" (*p)
+	: "r" (mask), "r" (p), "m" (*p)
+	: "cc");
+}
+
+extern __inline__ void change_bit(int nr, volatile void *addr)
+{
+	unsigned long old;
+	unsigned long mask = 1 << (nr & 0x1f);
+	unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+
+	__asm__ __volatile__(SMP_WMB "\
+1:	lwarx	%0,0,%3\n\
+	xor	%0,%0,%2\n\
+	stwcx.	%0,0,%3\n\
+	bne	1b"
+	SMP_MB
+	: "=&r" (old), "=m" (*p)
+	: "r" (mask), "r" (p), "m" (*p)
+	: "cc");
+}
+
+extern __inline__ int test_and_set_bit(int nr, volatile void *addr)
+{
+	unsigned int old, t;
+	unsigned int mask = 1 << (nr & 0x1f);
+	volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
+
+	__asm__ __volatile__(SMP_WMB "\
+1:	lwarx	%0,0,%4\n\
+	or	%1,%0,%3\n\
+	stwcx.	%1,0,%4\n\
+	bne	1b"
+	SMP_MB
+	: "=&r" (old), "=&r" (t), "=m" (*p)
+	: "r" (mask), "r" (p), "m" (*p)
+	: "cc");
+
+	return (old & mask) != 0;
+}
+
+extern __inline__ int test_and_clear_bit(int nr, volatile void *addr)
+{
+	unsigned int old, t;
+	unsigned int mask = 1 << (nr & 0x1f);
+	volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
+
+	__asm__ __volatile__(SMP_WMB "\
+1:	lwarx	%0,0,%4\n\
+	andc	%1,%0,%3\n\
+	stwcx.	%1,0,%4\n\
+	bne	1b"
+	SMP_MB
+	: "=&r" (old), "=&r" (t), "=m" (*p)
+	: "r" (mask), "r" (p), "m" (*p)
+	: "cc");
+
+	return (old & mask) != 0;
+}
+
+extern __inline__ int test_and_change_bit(int nr, volatile void *addr)
+{
+	unsigned int old, t;
+	unsigned int mask = 1 << (nr & 0x1f);
+	volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
+
+	__asm__ __volatile__(SMP_WMB "\
+1:	lwarx	%0,0,%4\n\
+	xor	%1,%0,%3\n\
+	stwcx.	%1,0,%4\n\
+	bne	1b"
+	SMP_MB
+	: "=&r" (old), "=&r" (t), "=m" (*p)
+	: "r" (mask), "r" (p), "m" (*p)
+	: "cc");
+
+	return (old & mask) != 0;
+}
+#endif /* __INLINE_BITOPS */
+
+extern __inline__ int test_bit(int nr, __const__ volatile void *addr)
+{
+	__const__ unsigned int *p = (__const__ unsigned int *) addr;
+
+	return ((p[nr >> 5] >> (nr & 0x1f)) & 1) != 0;
+}
+
+/* Return the bit position of the most significant 1 bit in a word */
+extern __inline__ int __ilog2(unsigned int x)
+{
+	int lz;
+
+	asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
+	return 31 - lz;
+}
+
+extern __inline__ int ffz(unsigned int x)
+{
+	if ((x = ~x) == 0)
+		return 32;
+	return __ilog2(x & -x);
+}
+
+#ifdef __KERNEL__
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+extern __inline__ int ffs(int x)
+{
+	return __ilog2(x & -x) + 1;
+}
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __KERNEL__ */
+
+/*
+ * This implementation of find_{first,next}_zero_bit was stolen from
+ * Linus' asm-alpha/bitops.h.
+ */
+#define find_first_zero_bit(addr, size) \
+	find_next_zero_bit((addr), (size), 0)
+
+extern __inline__ unsigned long find_next_zero_bit(void * addr,
+	unsigned long size, unsigned long offset)
+{
+	unsigned int * p = ((unsigned int *) addr) + (offset >> 5);
+	unsigned int result = offset & ~31UL;
+	unsigned int tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = *p++;
+		tmp |= ~0UL >> (32-offset);
+		if (size < 32)
+			goto found_first;
+		if (tmp != ~0U)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size >= 32) {
+		if ((tmp = *p++) != ~0U)
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+found_first:
+	tmp |= ~0UL << size;
+found_middle:
+	return result + ffz(tmp);
+}
+
+
+#define _EXT2_HAVE_ASM_BITOPS_
+
+#ifdef __KERNEL__
+/*
+ * test_and_{set,clear}_bit guarantee atomicity without
+ * disabling interrupts.
+ */
+#define ext2_set_bit(nr, addr)		test_and_set_bit((nr) ^ 0x18, addr)
+#define ext2_clear_bit(nr, addr)	test_and_clear_bit((nr) ^ 0x18, addr)
+
+#else
+extern __inline__ int ext2_set_bit(int nr, void * addr)
+{
+	int		mask;
+	unsigned char	*ADDR = (unsigned char *) addr;
+	int oldbit;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	oldbit = (*ADDR & mask) ? 1 : 0;
+	*ADDR |= mask;
+	return oldbit;
+}
+
+extern __inline__ int ext2_clear_bit(int nr, void * addr)
+{
+	int		mask;
+	unsigned char	*ADDR = (unsigned char *) addr;
+	int oldbit;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	oldbit = (*ADDR & mask) ? 1 : 0;
+	*ADDR = *ADDR & ~mask;
+	return oldbit;
+}
+#endif	/* __KERNEL__ */
+
+extern __inline__ int ext2_test_bit(int nr, __const__ void * addr)
+{
+	__const__ unsigned char	*ADDR = (__const__ unsigned char *) addr;
+
+	return (ADDR[nr >> 3] >> (nr & 7)) & 1;
+}
+
+/*
+ * This implementation of ext2_find_{first,next}_zero_bit was stolen from
+ * Linus' asm-alpha/bitops.h and modified for a big-endian machine.
+ */
+
+#define ext2_find_first_zero_bit(addr, size) \
+	ext2_find_next_zero_bit((addr), (size), 0)
+
+extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
+	unsigned long size, unsigned long offset)
+{
+	unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
+	unsigned int result = offset & ~31UL;
+	unsigned int tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = cpu_to_le32p(p++);
+		tmp |= ~0UL >> (32-offset);
+		if (size < 32)
+			goto found_first;
+		if (tmp != ~0U)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size >= 32) {
+		if ((tmp = cpu_to_le32p(p++)) != ~0U)
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = cpu_to_le32p(p);
+found_first:
+	tmp |= ~0U << size;
+found_middle:
+	return result + ffz(tmp);
+}
+
+/* Bitmap functions for the minix filesystem.  */
+#define minix_test_and_set_bit(nr,addr) ext2_set_bit(nr,addr)
+#define minix_set_bit(nr,addr) ((void)ext2_set_bit(nr,addr))
+#define minix_test_and_clear_bit(nr,addr) ext2_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr) ext2_test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size) ext2_find_first_zero_bit(addr,size)
+
+#endif /* _PPC_BITOPS_H */
diff --git a/include/asm-ppc/byteorder.h b/include/asm-ppc/byteorder.h
new file mode 100755
index 0000000..3f5bcf6
--- /dev/null
+++ b/include/asm-ppc/byteorder.h
@@ -0,0 +1,84 @@
+#ifndef _PPC_BYTEORDER_H
+#define _PPC_BYTEORDER_H
+
+#include <asm/types.h>
+
+#ifdef __GNUC__
+
+extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
+{
+	unsigned val;
+
+	__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
+	return val;
+}
+
+extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val)
+{
+	__asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
+}
+
+extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
+{
+	unsigned val;
+
+	__asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
+	return val;
+}
+
+extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
+{
+	__asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
+}
+
+/* alas, egcs sounds like it has a bug in this code that doesn't use the
+   inline asm correctly, and can cause file corruption. Until I hear that
+   it's fixed, I can live without the extra speed. I hope. */
+#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90)
+#if 0
+#  define __arch_swab16(x) ld_le16(&x)
+#  define __arch_swab32(x) ld_le32(&x)
+#else
+static __inline__ __attribute__((const)) __u16 ___arch__swab16(__u16 value)
+{
+	__u16 result;
+
+	__asm__("rlwimi %0,%1,8,16,23"
+	    : "=r" (result)
+	    : "r" (value), "0" (value >> 8));
+	return result;
+}
+
+static __inline__ __attribute__((const)) __u32 ___arch__swab32(__u32 value)
+{
+	__u32 result;
+
+	__asm__("rlwimi %0,%1,24,16,23\n\t"
+	    "rlwimi %0,%1,8,8,15\n\t"
+	    "rlwimi %0,%1,24,0,7"
+	    : "=r" (result)
+	    : "r" (value), "0" (value >> 24));
+	return result;
+}
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+#endif /* 0 */
+
+#endif
+
+/* The same, but returns converted value from the location pointer by addr. */
+#define __arch__swab16p(addr) ld_le16(addr)
+#define __arch__swab32p(addr) ld_le32(addr)
+
+/* The same, but do the conversion in situ, ie. put the value back to addr. */
+#define __arch__swab16s(addr) st_le16(addr,*addr)
+#define __arch__swab32s(addr) st_le32(addr,*addr)
+
+#endif /* __GNUC__ */
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+#define __BYTEORDER_HAS_U64__
+#endif
+#include <linux/byteorder/big_endian.h>
+
+#endif /* _PPC_BYTEORDER_H */
diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h
new file mode 100755
index 0000000..5befab4
--- /dev/null
+++ b/include/asm-ppc/cache.h
@@ -0,0 +1,89 @@
+/*
+ * include/asm-ppc/cache.h
+ */
+#ifndef __ARCH_PPC_CACHE_H
+#define __ARCH_PPC_CACHE_H
+
+#include <linux/config.h>
+#include <asm/processor.h>
+
+/* bytes per L1 cache line */
+#if !defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if defined(CONFIG_PPC64BRIDGE)
+#define L1_CACHE_BYTES	128
+#else
+#define	L1_CACHE_BYTES  32
+#endif /* PPC64 */
+#else
+#define	L1_CACHE_BYTES	16
+#endif /* !8xx || 8260 */
+
+#define	L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
+#define	L1_CACHE_PAGES		8
+
+#define	SMP_CACHE_BYTES L1_CACHE_BYTES
+
+#ifdef MODULE
+#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
+#else
+#define __cacheline_aligned					\
+  __attribute__((__aligned__(L1_CACHE_BYTES),			\
+		 __section__(".data.cacheline_aligned")))
+#endif
+
+#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+extern void flush_dcache_range(unsigned long start, unsigned long stop);
+extern void clean_dcache_range(unsigned long start, unsigned long stop);
+extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
+#ifdef CFG_INIT_RAM_LOCK
+extern void unlock_ram_in_cache(void);
+#endif /* CFG_INIT_RAM_LOCK */
+#endif /* __ASSEMBLY__ */
+
+/* prep registers for L2 */
+#define CACHECRBA       0x80000823      /* Cache configuration register address */
+#define L2CACHE_MASK	0x03	/* Mask for 2 L2 Cache bits */
+#define L2CACHE_512KB	0x00	/* 512KB */
+#define L2CACHE_256KB	0x01	/* 256KB */
+#define L2CACHE_1MB	0x02	/* 1MB */
+#define L2CACHE_NONE	0x03	/* NONE */
+#define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */
+
+#ifdef CONFIG_8xx
+/* Cache control on the MPC8xx is provided through some additional
+ * special purpose registers.
+ */
+#define IC_CST		560	/* Instruction cache control/status */
+#define IC_ADR		561	/* Address needed for some commands */
+#define IC_DAT		562	/* Read-only data register */
+#define DC_CST		568	/* Data cache control/status */
+#define DC_ADR		569	/* Address needed for some commands */
+#define DC_DAT		570	/* Read-only data register */
+
+/* Commands.  Only the first few are available to the instruction cache.
+*/
+#define	IDC_ENABLE	0x02000000	/* Cache enable */
+#define IDC_DISABLE	0x04000000	/* Cache disable */
+#define IDC_LDLCK	0x06000000	/* Load and lock */
+#define IDC_UNLINE	0x08000000	/* Unlock line */
+#define IDC_UNALL	0x0a000000	/* Unlock all */
+#define IDC_INVALL	0x0c000000	/* Invalidate all */
+
+#define DC_FLINE	0x0e000000	/* Flush data cache line */
+#define DC_SFWT		0x01000000	/* Set forced writethrough mode */
+#define DC_CFWT		0x03000000	/* Clear forced writethrough mode */
+#define DC_SLES		0x05000000	/* Set little endian swap mode */
+#define DC_CLES		0x07000000	/* Clear little endian swap mode */
+
+/* Status.
+*/
+#define IDC_ENABLED	0x80000000	/* Cache is enabled */
+#define IDC_CERR1	0x00200000	/* Cache error 1 */
+#define IDC_CERR2	0x00100000	/* Cache error 2 */
+#define IDC_CERR3	0x00080000	/* Cache error 3 */
+
+#define DC_DFWT		0x40000000	/* Data cache is forced write through */
+#define DC_LES		0x20000000	/* Caches are little endian mode */
+#endif /* CONFIG_8xx */
+
+#endif
diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h
new file mode 100755
index 0000000..2a9774a
--- /dev/null
+++ b/include/asm-ppc/cpm_8260.h
@@ -0,0 +1,768 @@
+
+/*
+ * MPC8260 Communication Processor Module.
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ *
+ * This file contains structures and information for the communication
+ * processor channels found in the dual port RAM or parameter RAM.
+ * All CPM control and status is available through the MPC8260 internal
+ * memory map.  See immap.h for details.
+ */
+#ifndef __CPM_82XX__
+#define __CPM_82XX__
+
+#include <asm/immap_8260.h>
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST	((uint)0x80000000)
+#define CPM_CR_PAGE	((uint)0x7c000000)
+#define CPM_CR_SBLOCK	((uint)0x03e00000)
+#define CPM_CR_FLG	((uint)0x00010000)
+#define CPM_CR_MCN	((uint)0x00003fc0)
+#define CPM_CR_OPCODE	((uint)0x0000000f)
+
+/* Device sub-block and page codes.
+*/
+#define CPM_CR_SCC1_SBLOCK	(0x04)
+#define CPM_CR_SCC2_SBLOCK	(0x05)
+#define CPM_CR_SCC3_SBLOCK	(0x06)
+#define CPM_CR_SCC4_SBLOCK	(0x07)
+#define CPM_CR_SMC1_SBLOCK	(0x08)
+#define CPM_CR_SMC2_SBLOCK	(0x09)
+#define CPM_CR_SPI_SBLOCK	(0x0a)
+#define CPM_CR_I2C_SBLOCK	(0x0b)
+#define CPM_CR_TIMER_SBLOCK	(0x0f)
+#define CPM_CR_RAND_SBLOCK	(0x0e)
+#define CPM_CR_FCC1_SBLOCK	(0x10)
+#define CPM_CR_FCC2_SBLOCK	(0x11)
+#define CPM_CR_FCC3_SBLOCK	(0x12)
+#define CPM_CR_IDMA1_SBLOCK	(0x14)
+#define CPM_CR_IDMA2_SBLOCK	(0x15)
+#define CPM_CR_IDMA3_SBLOCK	(0x16)
+#define CPM_CR_IDMA4_SBLOCK	(0x17)
+#define CPM_CR_MCC1_SBLOCK	(0x1c)
+
+#define CPM_CR_SCC1_PAGE	(0x00)
+#define CPM_CR_SCC2_PAGE	(0x01)
+#define CPM_CR_SCC3_PAGE	(0x02)
+#define CPM_CR_SCC4_PAGE	(0x03)
+#define CPM_CR_SMC1_PAGE	(0x07)
+#define CPM_CR_SMC2_PAGE	(0x08)
+#define CPM_CR_SPI_PAGE		(0x09)
+#define CPM_CR_I2C_PAGE		(0x0a)
+#define CPM_CR_TIMER_PAGE	(0x0a)
+#define CPM_CR_RAND_PAGE	(0x0a)
+#define CPM_CR_FCC1_PAGE	(0x04)
+#define CPM_CR_FCC2_PAGE	(0x05)
+#define CPM_CR_FCC3_PAGE	(0x06)
+#define CPM_CR_IDMA1_PAGE	(0x07)
+#define CPM_CR_IDMA2_PAGE	(0x08)
+#define CPM_CR_IDMA3_PAGE	(0x09)
+#define CPM_CR_IDMA4_PAGE	(0x0a)
+#define CPM_CR_MCC1_PAGE	(0x07)
+#define CPM_CR_MCC2_PAGE	(0x08)
+
+/* Some opcodes (there are more...later)
+*/
+#define CPM_CR_INIT_TRX		((ushort)0x0000)
+#define CPM_CR_INIT_RX		((ushort)0x0001)
+#define CPM_CR_INIT_TX		((ushort)0x0002)
+#define CPM_CR_HUNT_MODE	((ushort)0x0003)
+#define CPM_CR_STOP_TX		((ushort)0x0004)
+#define CPM_CR_RESTART_TX	((ushort)0x0006)
+#define CPM_CR_SET_GADDR	((ushort)0x0008)
+
+#define mk_cr_cmd(PG, SBC, MCN, OP) \
+	((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
+
+/* Dual Port RAM addresses.  The first 16K is available for almost
+ * any CPM use, so we put the BDs there.  The first 128 bytes are
+ * used for SMC1 and SMC2 parameter RAM, so we start allocating
+ * BDs above that.  All of this must change when we start
+ * downloading RAM microcode.
+ */
+#define CPM_DATAONLY_BASE	((uint)128)
+#define CPM_DP_NOSPACE		((uint)0x7fffffff)
+#ifndef CONFIG_MPC8272_FAMILY
+#define CPM_DATAONLY_SIZE	((uint)(8 * 1024) - CPM_DATAONLY_BASE)
+#define CPM_FCC_SPECIAL_BASE	((uint)0x0000b000)
+#else  /* 8247/48/71/72 */
+#define CPM_DATAONLY_SIZE	((uint)(4 * 1024) - CPM_DATAONLY_BASE)
+#define CPM_FCC_SPECIAL_BASE	((uint)0x00009000)
+#endif /* !CONFIG_MPC8272_FAMILY */
+
+/* The number of pages of host memory we allocate for CPM.  This is
+ * done early in kernel initialization to get physically contiguous
+ * pages.
+ */
+#define NUM_CPM_HOST_PAGES	2
+
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+extern	cpm8260_t	*cpmp;		/* Pointer to comm processor */
+uint		m8260_cpm_dpalloc(uint size, uint align);
+uint		m8260_cpm_hostalloc(uint size, uint align);
+void		m8260_cpm_setbrg(uint brg, uint rate);
+void		m8260_cpm_fastbrg(uint brg, uint rate, int div16);
+void		m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
+
+/* Buffer descriptors used by many of the CPM protocols.
+*/
+typedef struct cpm_buf_desc {
+	ushort	cbd_sc;		/* Status and Control */
+	ushort	cbd_datlen;	/* Data length in buffer */
+	uint	cbd_bufaddr;	/* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
+#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
+#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
+#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
+#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
+#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
+#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
+#define BD_SC_BR	((ushort)0x0020)	/* Break received */
+#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
+#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
+#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
+#define BD_SC_CD	((ushort)0x0001)	/* ?? */
+
+/* Function code bits, usually generic to devices.
+*/
+#define CPMFCR_GBL	((u_char)0x20)	/* Set memory snooping */
+#define CPMFCR_EB	((u_char)0x10)	/* Set big endian byte order */
+#define CPMFCR_TC2	((u_char)0x04)	/* Transfer code 2 value */
+#define CPMFCR_DTB	((u_char)0x02)	/* Use local bus for data when set */
+#define CPMFCR_BDB	((u_char)0x01)	/* Use local bus for BD when set */
+
+/* Parameter RAM offsets from the base.
+*/
+#ifndef CFG_CPM_POST_WORD_ADDR
+#define CPM_POST_WORD_ADDR      0x80FC	/* steal a long at the end of SCC1 */
+#else
+#define CPM_POST_WORD_ADDR	CFG_CPM_POST_WORD_ADDR
+#endif
+
+#ifndef CFG_CPM_BOOTCOUNT_ADDR
+#define CPM_BOOTCOUNT_ADDR	(CPM_POST_WORD_ADDR - 2*sizeof(ulong))
+#else
+#define CPM_BOOTCOUNT_ADDR	CFG_CPM_BOOTCOUNT_ADDR
+#endif
+
+#define PROFF_SCC1		((uint)0x8000)
+#define PROFF_SCC2		((uint)0x8100)
+#define PROFF_SCC3		((uint)0x8200)
+#define PROFF_SCC4		((uint)0x8300)
+#define PROFF_FCC1		((uint)0x8400)
+#define PROFF_FCC2		((uint)0x8500)
+#define PROFF_FCC3		((uint)0x8600)
+#define PROFF_MCC1		((uint)0x8700)
+#define PROFF_SMC1_BASE		((uint)0x87fc)
+#define PROFF_IDMA1_BASE	((uint)0x87fe)
+#define PROFF_MCC2		((uint)0x8800)
+#define PROFF_SMC2_BASE		((uint)0x88fc)
+#define PROFF_IDMA2_BASE	((uint)0x88fe)
+#define PROFF_SPI_BASE		((uint)0x89fc)
+#define PROFF_IDMA3_BASE	((uint)0x89fe)
+#define PROFF_TIMERS		((uint)0x8ae0)
+#define PROFF_REVNUM		((uint)0x8af0)
+#define PROFF_RAND		((uint)0x8af8)
+#define PROFF_I2C_BASE		((uint)0x8afc)
+#define PROFF_IDMA4_BASE	((uint)0x8afe)
+
+/* The SMCs are relocated to any of the first eight DPRAM pages.
+ * We will fix these at the first locations of DPRAM, until we
+ * get some microcode patches :-).
+ * The parameter ram space for the SMCs is fifty-some bytes, and
+ * they are required to start on a 64 byte boundary.
+ */
+#define PROFF_SMC1	(0)
+#define PROFF_SMC2	(64)
+#define PROFF_SPI	((16*1024) - 128)
+
+/* Define enough so I can at least use the serial port as a UART.
+ */
+typedef struct smc_uart {
+	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
+	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
+	u_char	smc_rfcr;	/* Rx function code */
+	u_char	smc_tfcr;	/* Tx function code */
+	ushort	smc_mrblr;	/* Max receive buffer length */
+	uint	smc_rstate;	/* Internal */
+	uint	smc_idp;	/* Internal */
+	ushort	smc_rbptr;	/* Internal */
+	ushort	smc_ibc;	/* Internal */
+	uint	smc_rxtmp;	/* Internal */
+	uint	smc_tstate;	/* Internal */
+	uint	smc_tdp;	/* Internal */
+	ushort	smc_tbptr;	/* Internal */
+	ushort	smc_tbc;	/* Internal */
+	uint	smc_txtmp;	/* Internal */
+	ushort	smc_maxidl;	/* Maximum idle characters */
+	ushort	smc_tmpidl;	/* Temporary idle counter */
+	ushort	smc_brklen;	/* Last received break length */
+	ushort	smc_brkec;	/* rcv'd break condition counter */
+	ushort	smc_brkcr;	/* xmt break count register */
+	ushort	smc_rmask;	/* Temporary bit mask */
+	uint	smc_stmp;	/* SDMA Temp */
+} smc_uart_t;
+
+/* SMC uart mode register (Internal memory map).
+*/
+#define	SMCMR_REN	((ushort)0x0001)
+#define SMCMR_TEN	((ushort)0x0002)
+#define SMCMR_DM	((ushort)0x000c)
+#define SMCMR_SM_GCI	((ushort)0x0000)
+#define SMCMR_SM_UART	((ushort)0x0020)
+#define SMCMR_SM_TRANS	((ushort)0x0030)
+#define SMCMR_SM_MASK	((ushort)0x0030)
+#define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
+#define SMCMR_REVD	SMCMR_PM_EVEN
+#define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
+#define SMCMR_BS	SMCMR_PEN
+#define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
+#define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
+#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)
+
+/* SMC Event and Mask register.
+*/
+#define	SMCM_TXE	((unsigned char)0x10)
+#define	SMCM_BSY	((unsigned char)0x04)
+#define	SMCM_TX		((unsigned char)0x02)
+#define	SMCM_RX		((unsigned char)0x01)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST		((uint)0x00020000)
+#define CPM_BRG_EN		((uint)0x00010000)
+#define CPM_BRG_EXTC_INT	((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK3_9	((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK5_15	((uint)0x00008000)
+#define CPM_BRG_ATB		((uint)0x00002000)
+#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
+#define CPM_BRG_DIV16		((uint)0x00000001)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP		((uint)0x00040000)
+#define SCC_GSMRH_GDE		((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
+#define SCC_GSMRH_REVD		((uint)0x00002000)
+#define SCC_GSMRH_TRX		((uint)0x00001000)
+#define SCC_GSMRH_TTX		((uint)0x00000800)
+#define SCC_GSMRH_CDP		((uint)0x00000400)
+#define SCC_GSMRH_CTSP		((uint)0x00000200)
+#define SCC_GSMRH_CDS		((uint)0x00000100)
+#define SCC_GSMRH_CTSS		((uint)0x00000080)
+#define SCC_GSMRH_TFL		((uint)0x00000040)
+#define SCC_GSMRH_RFW		((uint)0x00000020)
+#define SCC_GSMRH_TXSY		((uint)0x00000010)
+#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8		((uint)0x00000008)
+#define SCC_GSMRH_SYNL4		((uint)0x00000004)
+#define SCC_GSMRH_RTSM		((uint)0x00000002)
+#define SCC_GSMRH_RSYN		((uint)0x00000001)
+
+#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
+#define SCC_GSMRL_TCI		((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
+#define SCC_GSMRL_RINV		((uint)0x02000000)
+#define SCC_GSMRL_TINV		((uint)0x01000000)
+#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48	((uint)0x00800000)
+#define SCC_GSMRL_TPL_32	((uint)0x00600000)
+#define SCC_GSMRL_TPL_16	((uint)0x00400000)
+#define SCC_GSMRL_TPL_8		((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
+#define SCC_GSMRL_TPP_01	((uint)0x00100000)
+#define SCC_GSMRL_TPP_10	((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
+#define SCC_GSMRL_TEND		((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
+#define SCC_GSMRL_ENR		((uint)0x00000020)
+#define SCC_GSMRL_ENT		((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
+#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
+
+#define SCC_TODR_TOD		((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define	SCCM_TXE	((unsigned char)0x10)
+#define	SCCM_BSY	((unsigned char)0x04)
+#define	SCCM_TX		((unsigned char)0x02)
+#define	SCCM_RX		((unsigned char)0x01)
+
+typedef struct scc_param {
+	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
+	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
+	u_char	scc_rfcr;	/* Rx function code */
+	u_char	scc_tfcr;	/* Tx function code */
+	ushort	scc_mrblr;	/* Max receive buffer length */
+	uint	scc_rstate;	/* Internal */
+	uint	scc_idp;	/* Internal */
+	ushort	scc_rbptr;	/* Internal */
+	ushort	scc_ibc;	/* Internal */
+	uint	scc_rxtmp;	/* Internal */
+	uint	scc_tstate;	/* Internal */
+	uint	scc_tdp;	/* Internal */
+	ushort	scc_tbptr;	/* Internal */
+	ushort	scc_tbc;	/* Internal */
+	uint	scc_txtmp;	/* Internal */
+	uint	scc_rcrc;	/* Internal */
+	uint	scc_tcrc;	/* Internal */
+} sccp_t;
+
+/* CPM Ethernet through SCC1.
+ */
+typedef struct scc_enet {
+	sccp_t	sen_genscc;
+	uint	sen_cpres;	/* Preset CRC */
+	uint	sen_cmask;	/* Constant mask for CRC */
+	uint	sen_crcec;	/* CRC Error counter */
+	uint	sen_alec;	/* alignment error counter */
+	uint	sen_disfc;	/* discard frame counter */
+	ushort	sen_pads;	/* Tx short frame pad character */
+	ushort	sen_retlim;	/* Retry limit threshold */
+	ushort	sen_retcnt;	/* Retry limit counter */
+	ushort	sen_maxflr;	/* maximum frame length register */
+	ushort	sen_minflr;	/* minimum frame length register */
+	ushort	sen_maxd1;	/* maximum DMA1 length */
+	ushort	sen_maxd2;	/* maximum DMA2 length */
+	ushort	sen_maxd;	/* Rx max DMA */
+	ushort	sen_dmacnt;	/* Rx DMA counter */
+	ushort	sen_maxb;	/* Max BD byte count */
+	ushort	sen_gaddr1;	/* Group address filter */
+	ushort	sen_gaddr2;
+	ushort	sen_gaddr3;
+	ushort	sen_gaddr4;
+	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf0rba;	/* Internal */
+	uint	sen_tbuf0crc;	/* Internal */
+	ushort	sen_tbuf0bcnt;	/* Internal */
+	ushort	sen_paddrh;	/* physical address (MSB) */
+	ushort	sen_paddrm;
+	ushort	sen_paddrl;	/* physical address (LSB) */
+	ushort	sen_pper;	/* persistence */
+	ushort	sen_rfbdptr;	/* Rx first BD pointer */
+	ushort	sen_tfbdptr;	/* Tx first BD pointer */
+	ushort	sen_tlbdptr;	/* Tx last BD pointer */
+	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf1rba;	/* Internal */
+	uint	sen_tbuf1crc;	/* Internal */
+	ushort	sen_tbuf1bcnt;	/* Internal */
+	ushort	sen_txlen;	/* Tx Frame length counter */
+	ushort	sen_iaddr1;	/* Individual address filter */
+	ushort	sen_iaddr2;
+	ushort	sen_iaddr3;
+	ushort	sen_iaddr4;
+	ushort	sen_boffcnt;	/* Backoff counter */
+
+	/* NOTE: Some versions of the manual have the following items
+	 * incorrectly documented.  Below is the proper order.
+	 */
+	ushort	sen_taddrh;	/* temp address (MSB) */
+	ushort	sen_taddrm;
+	ushort	sen_taddrl;	/* temp address (LSB) */
+} scc_enet_t;
+
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
+#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
+#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
+#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
+#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
+#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
+
+/* SCC Mode Register (PSMR) as used by Ethernet.
+*/
+#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
+#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
+#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
+#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
+#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
+#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
+#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
+#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
+#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
+#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
+#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
+#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
+#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_RX_EMPTY	((ushort)0x8000)
+#define BD_ENET_RX_WRAP		((ushort)0x2000)
+#define BD_ENET_RX_INTR		((ushort)0x1000)
+#define BD_ENET_RX_LAST		((ushort)0x0800)
+#define BD_ENET_RX_FIRST	((ushort)0x0400)
+#define BD_ENET_RX_MISS		((ushort)0x0100)
+#define BD_ENET_RX_BC		((ushort)0x0080)	/* FCC Only */
+#define BD_ENET_RX_MC		((ushort)0x0040)	/* FCC Only */
+#define BD_ENET_RX_LG		((ushort)0x0020)
+#define BD_ENET_RX_NO		((ushort)0x0010)
+#define BD_ENET_RX_SH		((ushort)0x0008)
+#define BD_ENET_RX_CR		((ushort)0x0004)
+#define BD_ENET_RX_OV		((ushort)0x0002)
+#define BD_ENET_RX_CL		((ushort)0x0001)
+#define BD_ENET_RX_STATS	((ushort)0x01ff)	/* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_TX_READY	((ushort)0x8000)
+#define BD_ENET_TX_PAD		((ushort)0x4000)
+#define BD_ENET_TX_WRAP		((ushort)0x2000)
+#define BD_ENET_TX_INTR		((ushort)0x1000)
+#define BD_ENET_TX_LAST		((ushort)0x0800)
+#define BD_ENET_TX_TC		((ushort)0x0400)
+#define BD_ENET_TX_DEF		((ushort)0x0200)
+#define BD_ENET_TX_HB		((ushort)0x0100)
+#define BD_ENET_TX_LC		((ushort)0x0080)
+#define BD_ENET_TX_RL		((ushort)0x0040)
+#define BD_ENET_TX_RCMASK	((ushort)0x003c)
+#define BD_ENET_TX_UN		((ushort)0x0002)
+#define BD_ENET_TX_CSL		((ushort)0x0001)
+#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+	sccp_t	scc_genscc;
+	uint	scc_res1;	/* Reserved */
+	uint	scc_res2;	/* Reserved */
+	ushort	scc_maxidl;	/* Maximum idle chars */
+	ushort	scc_idlc;	/* temp idle counter */
+	ushort	scc_brkcr;	/* Break count register */
+	ushort	scc_parec;	/* receive parity error counter */
+	ushort	scc_frmec;	/* receive framing error counter */
+	ushort	scc_nosec;	/* receive noise counter */
+	ushort	scc_brkec;	/* receive break condition counter */
+	ushort	scc_brkln;	/* last received break length */
+	ushort	scc_uaddr1;	/* UART address character 1 */
+	ushort	scc_uaddr2;	/* UART address character 2 */
+	ushort	scc_rtemp;	/* Temp storage */
+	ushort	scc_toseq;	/* Transmit out of sequence char */
+	ushort	scc_char1;	/* control character 1 */
+	ushort	scc_char2;	/* control character 2 */
+	ushort	scc_char3;	/* control character 3 */
+	ushort	scc_char4;	/* control character 4 */
+	ushort	scc_char5;	/* control character 5 */
+	ushort	scc_char6;	/* control character 6 */
+	ushort	scc_char7;	/* control character 7 */
+	ushort	scc_char8;	/* control character 8 */
+	ushort	scc_rccm;	/* receive control character mask */
+	ushort	scc_rccr;	/* receive control character register */
+	ushort	scc_rlbc;	/* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR		((ushort)0x1000)
+#define UART_SCCM_GLT		((ushort)0x0800)
+#define UART_SCCM_AB		((ushort)0x0200)
+#define UART_SCCM_IDL		((ushort)0x0100)
+#define UART_SCCM_GRA		((ushort)0x0080)
+#define UART_SCCM_BRKE		((ushort)0x0040)
+#define UART_SCCM_BRKS		((ushort)0x0020)
+#define UART_SCCM_CCR		((ushort)0x0008)
+#define UART_SCCM_BSY		((ushort)0x0004)
+#define UART_SCCM_TX		((ushort)0x0002)
+#define UART_SCCM_RX		((ushort)0x0001)
+
+/* The SCC PSMR when used as a UART.
+*/
+#define SCU_PSMR_FLC		((ushort)0x8000)
+#define SCU_PSMR_SL		((ushort)0x4000)
+#define SCU_PSMR_CL		((ushort)0x3000)
+#define SCU_PSMR_UM		((ushort)0x0c00)
+#define SCU_PSMR_FRZ		((ushort)0x0200)
+#define SCU_PSMR_RZS		((ushort)0x0100)
+#define SCU_PSMR_SYN		((ushort)0x0080)
+#define SCU_PSMR_DRT		((ushort)0x0040)
+#define SCU_PSMR_PEN		((ushort)0x0010)
+#define SCU_PSMR_RPM		((ushort)0x000c)
+#define SCU_PSMR_REVP		((ushort)0x0008)
+#define SCU_PSMR_TPM		((ushort)0x0003)
+#define SCU_PSMR_TEVP		((ushort)0x0003)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+	sccp_t	st_genscc;
+	uint	st_cpres;	/* Preset CRC */
+	uint	st_cmask;	/* Constant mask for CRC */
+} scc_trans_t;
+
+#define BD_SCC_TX_LAST		((ushort)0x0800)
+
+/* How about some FCCs.....
+*/
+#define FCC_GFMR_DIAG_NORM	((uint)0x00000000)
+#define FCC_GFMR_DIAG_LE	((uint)0x40000000)
+#define FCC_GFMR_DIAG_AE	((uint)0x80000000)
+#define FCC_GFMR_DIAG_ALE	((uint)0xc0000000)
+#define FCC_GFMR_TCI		((uint)0x20000000)
+#define FCC_GFMR_TRX		((uint)0x10000000)
+#define FCC_GFMR_TTX		((uint)0x08000000)
+#define FCC_GFMR_TTX		((uint)0x08000000)
+#define FCC_GFMR_CDP		((uint)0x04000000)
+#define FCC_GFMR_CTSP		((uint)0x02000000)
+#define FCC_GFMR_CDS		((uint)0x01000000)
+#define FCC_GFMR_CTSS		((uint)0x00800000)
+#define FCC_GFMR_SYNL_NONE	((uint)0x00000000)
+#define FCC_GFMR_SYNL_AUTO	((uint)0x00004000)
+#define FCC_GFMR_SYNL_8		((uint)0x00008000)
+#define FCC_GFMR_SYNL_16	((uint)0x0000c000)
+#define FCC_GFMR_RTSM		((uint)0x00002000)
+#define FCC_GFMR_RENC_NRZ	((uint)0x00000000)
+#define FCC_GFMR_RENC_NRZI	((uint)0x00000800)
+#define FCC_GFMR_REVD		((uint)0x00000400)
+#define FCC_GFMR_TENC_NRZ	((uint)0x00000000)
+#define FCC_GFMR_TENC_NRZI	((uint)0x00000100)
+#define FCC_GFMR_TCRC_16	((uint)0x00000000)
+#define FCC_GFMR_TCRC_32	((uint)0x00000080)
+#define FCC_GFMR_ENR		((uint)0x00000020)
+#define FCC_GFMR_ENT		((uint)0x00000010)
+#define FCC_GFMR_MODE_ENET	((uint)0x0000000c)
+#define FCC_GFMR_MODE_ATM	((uint)0x0000000a)
+#define FCC_GFMR_MODE_HDLC	((uint)0x00000000)
+
+/* Generic FCC parameter ram.
+*/
+typedef struct fcc_param {
+	ushort	fcc_riptr;	/* Rx Internal temp pointer */
+	ushort	fcc_tiptr;	/* Tx Internal temp pointer */
+	ushort	fcc_res1;
+	ushort	fcc_mrblr;	/* Max receive buffer length, mod 32 bytes */
+	uint	fcc_rstate;	/* Upper byte is Func code, must be set */
+	uint	fcc_rbase;	/* Receive BD base */
+	ushort	fcc_rbdstat;	/* RxBD status */
+	ushort	fcc_rbdlen;	/* RxBD down counter */
+	uint	fcc_rdptr;	/* RxBD internal data pointer */
+	uint	fcc_tstate;	/* Upper byte is Func code, must be set */
+	uint	fcc_tbase;	/* Transmit BD base */
+	ushort	fcc_tbdstat;	/* TxBD status */
+	ushort	fcc_tbdlen;	/* TxBD down counter */
+	uint	fcc_tdptr;	/* TxBD internal data pointer */
+	uint	fcc_rbptr;	/* Rx BD Internal buf pointer */
+	uint	fcc_tbptr;	/* Tx BD Internal buf pointer */
+	uint	fcc_rcrc;	/* Rx temp CRC */
+	uint	fcc_res2;
+	uint	fcc_tcrc;	/* Tx temp CRC */
+} fccp_t;
+
+
+/* Ethernet controller through FCC.
+*/
+typedef struct fcc_enet {
+	fccp_t	fen_genfcc;
+	uint	fen_statbuf;	/* Internal status buffer */
+	uint	fen_camptr;	/* CAM address */
+	uint	fen_cmask;	/* Constant mask for CRC */
+	uint	fen_cpres;	/* Preset CRC */
+	uint	fen_crcec;	/* CRC Error counter */
+	uint	fen_alec;	/* alignment error counter */
+	uint	fen_disfc;	/* discard frame counter */
+	ushort	fen_retlim;	/* Retry limit */
+	ushort	fen_retcnt;	/* Retry counter */
+	ushort	fen_pper;	/* Persistence */
+	ushort	fen_boffcnt;	/* backoff counter */
+	uint	fen_gaddrh;	/* Group address filter, high 32-bits */
+	uint	fen_gaddrl;	/* Group address filter, low 32-bits */
+	ushort	fen_tfcstat;	/* out of sequence TxBD */
+	ushort	fen_tfclen;
+	uint	fen_tfcptr;
+	ushort	fen_mflr;	/* Maximum frame length (1518) */
+	ushort	fen_paddrh;	/* MAC address */
+	ushort	fen_paddrm;
+	ushort	fen_paddrl;
+	ushort	fen_ibdcount;	/* Internal BD counter */
+	ushort	fen_idbstart;	/* Internal BD start pointer */
+	ushort	fen_ibdend;	/* Internal BD end pointer */
+	ushort	fen_txlen;	/* Internal Tx frame length counter */
+	uint	fen_ibdbase[8]; /* Internal use */
+	uint	fen_iaddrh;	/* Individual address filter */
+	uint	fen_iaddrl;
+	ushort	fen_minflr;	/* Minimum frame length (64) */
+	ushort	fen_taddrh;	/* Filter transfer MAC address */
+	ushort	fen_taddrm;
+	ushort	fen_taddrl;
+	ushort	fen_padptr;	/* Pointer to pad byte buffer */
+	ushort	fen_cftype;	/* control frame type */
+	ushort	fen_cfrange;	/* control frame range */
+	ushort	fen_maxb;	/* maximum BD count */
+	ushort	fen_maxd1;	/* Max DMA1 length (1520) */
+	ushort	fen_maxd2;	/* Max DMA2 length (1520) */
+	ushort	fen_maxd;	/* internal max DMA count */
+	ushort	fen_dmacnt;	/* internal DMA counter */
+	uint	fen_octc;	/* Total octect counter */
+	uint	fen_colc;	/* Total collision counter */
+	uint	fen_broc;	/* Total broadcast packet counter */
+	uint	fen_mulc;	/* Total multicast packet count */
+	uint	fen_uspc;	/* Total packets < 64 bytes */
+	uint	fen_frgc;	/* Total packets < 64 bytes with errors */
+	uint	fen_ospc;	/* Total packets > 1518 */
+	uint	fen_jbrc;	/* Total packets > 1518 with errors */
+	uint	fen_p64c;	/* Total packets == 64 bytes */
+	uint	fen_p65c;	/* Total packets 64 < bytes <= 127 */
+	uint	fen_p128c;	/* Total packets 127 < bytes <= 255 */
+	uint	fen_p256c;	/* Total packets 256 < bytes <= 511 */
+	uint	fen_p512c;	/* Total packets 512 < bytes <= 1023 */
+	uint	fen_p1024c;	/* Total packets 1024 < bytes <= 1518 */
+	uint	fen_cambuf;	/* Internal CAM buffer poiner */
+	ushort	fen_rfthr;	/* Received frames threshold */
+	ushort	fen_rfcnt;	/* Received frames count */
+} fcc_enet_t;
+
+/* FCC Event/Mask register as used by Ethernet.
+*/
+#define FCC_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
+#define FCC_ENET_RXC	((ushort)0x0040)	/* Control Frame Received */
+#define FCC_ENET_TXC	((ushort)0x0020)	/* Out of seq. Tx sent */
+#define FCC_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
+#define FCC_ENET_RXF	((ushort)0x0008)	/* Full frame received */
+#define FCC_ENET_BSY	((ushort)0x0004)	/* Busy.  Rx Frame dropped */
+#define FCC_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
+#define FCC_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
+
+/* FCC Mode Register (FPSMR) as used by Ethernet.
+*/
+#define FCC_PSMR_HBC	((uint)0x80000000)	/* Enable heartbeat */
+#define FCC_PSMR_FC	((uint)0x40000000)	/* Force Collision */
+#define FCC_PSMR_SBT	((uint)0x20000000)	/* Stop backoff timer */
+#define FCC_PSMR_LPB	((uint)0x10000000)	/* Local protect. 1 = FDX */
+#define FCC_PSMR_LCW	((uint)0x08000000)	/* Late collision select */
+#define FCC_PSMR_FDE	((uint)0x04000000)	/* Full Duplex Enable */
+#define FCC_PSMR_MON	((uint)0x02000000)	/* RMON Enable */
+#define FCC_PSMR_PRO	((uint)0x00400000)	/* Promiscuous Enable */
+#define FCC_PSMR_FCE	((uint)0x00200000)	/* Flow Control Enable */
+#define FCC_PSMR_RSH	((uint)0x00100000)	/* Receive Short Frames */
+#define FCC_PSMR_RMII	((uint)0x00020000)	/* Use RMII interface */
+#define FCC_PSMR_CAM	((uint)0x00000400)	/* CAM enable */
+#define FCC_PSMR_BRO	((uint)0x00000200)	/* Broadcast pkt discard */
+#define FCC_PSMR_ENCRC	((uint)0x00000080)	/* Use 32-bit CRC */
+
+/* IIC parameter RAM.
+*/
+typedef struct iic {
+	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
+	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
+	u_char	iic_rfcr;	/* Rx function code */
+	u_char	iic_tfcr;	/* Tx function code */
+	ushort	iic_mrblr;	/* Max receive buffer length */
+	uint	iic_rstate;	/* Internal */
+	uint	iic_rdp;	/* Internal */
+	ushort	iic_rbptr;	/* Internal */
+	ushort	iic_rbc;	/* Internal */
+	uint	iic_rxtmp;	/* Internal */
+	uint	iic_tstate;	/* Internal */
+	uint	iic_tdp;	/* Internal */
+	ushort	iic_tbptr;	/* Internal */
+	ushort	iic_tbc;	/* Internal */
+	uint	iic_txtmp;	/* Internal */
+} iic_t;
+
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
+	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
+	u_char	spi_rfcr;	/* Rx function code */
+	u_char	spi_tfcr;	/* Tx function code */
+	ushort	spi_mrblr;	/* Max receive buffer length */
+	uint	spi_rstate;	/* Internal */
+	uint	spi_rdp;	/* Internal */
+	ushort	spi_rbptr;	/* Internal */
+	ushort	spi_rbc;	/* Internal */
+	uint	spi_rxtmp;	/* Internal */
+	uint	spi_tstate;	/* Internal */
+	uint	spi_tdp;	/* Internal */
+	ushort	spi_tbptr;	/* Internal */
+	ushort	spi_tbc;	/* Internal */
+	uint	spi_txtmp;	/* Internal */
+	uint	spi_res;	/* Tx temp. */
+	uint	spi_res1[4];	/* SDMA temp. */
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
+#define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
+#define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
+#define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
+#define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
+#define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
+#define SPMODE_EN	((ushort)0x0100)	/* Enable */
+#define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
+#define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
+
+#define SPMODE_LEN(x)	((((x)-1)&0xF)<<4)
+#define SPMODE_PM(x)	((x) &0xF)
+
+/* SPI Event/Mask register.
+*/
+#define SPI_EMASK		0x37	/* Event Mask				*/
+#define SPI_MME			0x20	/* Multi-Master Error			*/
+#define SPI_TXE			0x10	/* Transmit Error			*/
+#define SPI_BSY			0x04	/* Busy					*/
+#define SPI_TXB			0x02	/* Tx Buffer Empty			*/
+#define SPI_RXB			0x01	/* RX Buffer full/closed		*/
+
+#define SPI_STR			0x80	/* SPCOM: Start transmit		*/
+
+#define SPI_EB		((u_char)0x10)		/* big endian byte order */
+
+#define BD_IIC_START		((ushort)0x0400)
+
+#endif /* __CPM_82XX__ */
diff --git a/include/asm-ppc/cpm_85xx.h b/include/asm-ppc/cpm_85xx.h
new file mode 100755
index 0000000..a74a3a1
--- /dev/null
+++ b/include/asm-ppc/cpm_85xx.h
@@ -0,0 +1,830 @@
+
+/*
+ * MPC85xx Communication Processor Module
+ * Copyright (c) 2003,Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * MPC8260 Communication Processor Module.
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ *
+ * This file contains structures and information for the communication
+ * processor channels found in the dual port RAM or parameter RAM.
+ * All CPM control and status is available through the MPC8260 internal
+ * memory map.  See immap.h for details.
+ */
+#ifndef __CPM_85XX__
+#define __CPM_85XX__
+
+#include <asm/immap_85xx.h>
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST	((uint)0x80000000)
+#define CPM_CR_PAGE	((uint)0x7c000000)
+#define CPM_CR_SBLOCK	((uint)0x03e00000)
+#define CPM_CR_FLG	((uint)0x00010000)
+#define CPM_CR_MCN	((uint)0x00003fc0)
+#define CPM_CR_OPCODE	((uint)0x0000000f)
+
+/* Device sub-block and page codes.
+*/
+#define CPM_CR_SCC1_SBLOCK	(0x04)
+#define CPM_CR_SCC2_SBLOCK	(0x05)
+#define CPM_CR_SCC3_SBLOCK	(0x06)
+#define CPM_CR_SCC4_SBLOCK	(0x07)
+#define CPM_CR_SMC1_SBLOCK	(0x08)
+#define CPM_CR_SMC2_SBLOCK	(0x09)
+#define CPM_CR_SPI_SBLOCK	(0x0a)
+#define CPM_CR_I2C_SBLOCK	(0x0b)
+#define CPM_CR_TIMER_SBLOCK	(0x0f)
+#define CPM_CR_RAND_SBLOCK	(0x0e)
+#define CPM_CR_FCC1_SBLOCK	(0x10)
+#define CPM_CR_FCC2_SBLOCK	(0x11)
+#define CPM_CR_FCC3_SBLOCK	(0x12)
+#define CPM_CR_MCC1_SBLOCK	(0x1c)
+
+#define CPM_CR_SCC1_PAGE	(0x00)
+#define CPM_CR_SCC2_PAGE	(0x01)
+#define CPM_CR_SCC3_PAGE	(0x02)
+#define CPM_CR_SCC4_PAGE	(0x03)
+#define CPM_CR_SPI_PAGE		(0x09)
+#define CPM_CR_I2C_PAGE		(0x0a)
+#define CPM_CR_TIMER_PAGE	(0x0a)
+#define CPM_CR_RAND_PAGE	(0x0a)
+#define CPM_CR_FCC1_PAGE	(0x04)
+#define CPM_CR_FCC2_PAGE	(0x05)
+#define CPM_CR_FCC3_PAGE	(0x06)
+#define CPM_CR_MCC1_PAGE	(0x07)
+#define CPM_CR_MCC2_PAGE	(0x08)
+
+/* Some opcodes (there are more...later)
+*/
+#define CPM_CR_INIT_TRX		((ushort)0x0000)
+#define CPM_CR_INIT_RX		((ushort)0x0001)
+#define CPM_CR_INIT_TX		((ushort)0x0002)
+#define CPM_CR_HUNT_MODE	((ushort)0x0003)
+#define CPM_CR_STOP_TX		((ushort)0x0004)
+#define CPM_CR_RESTART_TX	((ushort)0x0006)
+#define CPM_CR_SET_GADDR	((ushort)0x0008)
+
+#define mk_cr_cmd(PG, SBC, MCN, OP) \
+	((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
+
+/* Dual Port RAM addresses.  The first 16K is available for almost
+ * any CPM use, so we put the BDs there.  The first 128 bytes are
+ * used for SMC1 and SMC2 parameter RAM, so we start allocating
+ * BDs above that.  All of this must change when we start
+ * downloading RAM microcode.
+ */
+#define CPM_DATAONLY_BASE	((uint)128)
+#define CPM_DP_NOSPACE		((uint)0x7FFFFFFF)
+#if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
+#define CPM_FCC_SPECIAL_BASE	((uint)0x00009000)
+#define CPM_DATAONLY_SIZE	((uint)(8 * 1024) - CPM_DATAONLY_BASE)
+#else	/* MPC8540, MPC8560 */
+#define CPM_FCC_SPECIAL_BASE	((uint)0x0000B000)
+#define CPM_DATAONLY_SIZE	((uint)(16 * 1024) - CPM_DATAONLY_BASE)
+#endif
+
+/* The number of pages of host memory we allocate for CPM.  This is
+ * done early in kernel initialization to get physically contiguous
+ * pages.
+ */
+#define NUM_CPM_HOST_PAGES	2
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+/*extern	cpm8560_t	*cpmp;	 Pointer to comm processor */
+uint		m8560_cpm_dpalloc(uint size, uint align);
+uint		m8560_cpm_hostalloc(uint size, uint align);
+void		m8560_cpm_setbrg(uint brg, uint rate);
+void		m8560_cpm_fastbrg(uint brg, uint rate, int div16);
+void		m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
+
+/* Buffer descriptors used by many of the CPM protocols.
+*/
+typedef struct cpm_buf_desc {
+	ushort	cbd_sc;		/* Status and Control */
+	ushort	cbd_datlen;	/* Data length in buffer */
+	uint	cbd_bufaddr;	/* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
+#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
+#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
+#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
+#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
+#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
+#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
+#define BD_SC_BR	((ushort)0x0020)	/* Break received */
+#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
+#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
+#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
+#define BD_SC_CD	((ushort)0x0001)	/* ?? */
+
+/* Function code bits, usually generic to devices.
+*/
+#define CPMFCR_GBL	((u_char)0x20)	/* Set memory snooping */
+#define CPMFCR_EB	((u_char)0x10)	/* Set big endian byte order */
+#define CPMFCR_TC2	((u_char)0x04)	/* Transfer code 2 value */
+#define CPMFCR_DTB	((u_char)0x02)	/* Use local bus for data when set */
+#define CPMFCR_BDB	((u_char)0x01)	/* Use local bus for BD when set */
+
+/* Parameter RAM offsets from the base.
+*/
+#define CPM_POST_WORD_ADDR      0x80FC	/* steal a long at the end of SCC1 */
+#define PROFF_SCC1		((uint)0x8000)
+#define PROFF_SCC2		((uint)0x8100)
+#define PROFF_SCC3		((uint)0x8200)
+#define PROFF_SCC4		((uint)0x8300)
+#define PROFF_FCC1		((uint)0x8400)
+#define PROFF_FCC2		((uint)0x8500)
+#define PROFF_FCC3		((uint)0x8600)
+#define PROFF_MCC1		((uint)0x8700)
+#define PROFF_MCC2		((uint)0x8800)
+#define PROFF_SPI_BASE		((uint)0x89fc)
+#define PROFF_TIMERS		((uint)0x8ae0)
+#define PROFF_REVNUM		((uint)0x8af0)
+#define PROFF_RAND		((uint)0x8af8)
+#define PROFF_I2C_BASE		((uint)0x8afc)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST		((uint)0x00020000)
+#define CPM_BRG_EN		((uint)0x00010000)
+#define CPM_BRG_EXTC_INT	((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK3_9	((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK5_15	((uint)0x00008000)
+#define CPM_BRG_ATB		((uint)0x00002000)
+#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
+#define CPM_BRG_DIV16		((uint)0x00000001)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP		((uint)0x00040000)
+#define SCC_GSMRH_GDE		((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
+#define SCC_GSMRH_REVD		((uint)0x00002000)
+#define SCC_GSMRH_TRX		((uint)0x00001000)
+#define SCC_GSMRH_TTX		((uint)0x00000800)
+#define SCC_GSMRH_CDP		((uint)0x00000400)
+#define SCC_GSMRH_CTSP		((uint)0x00000200)
+#define SCC_GSMRH_CDS		((uint)0x00000100)
+#define SCC_GSMRH_CTSS		((uint)0x00000080)
+#define SCC_GSMRH_TFL		((uint)0x00000040)
+#define SCC_GSMRH_RFW		((uint)0x00000020)
+#define SCC_GSMRH_TXSY		((uint)0x00000010)
+#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8		((uint)0x00000008)
+#define SCC_GSMRH_SYNL4		((uint)0x00000004)
+#define SCC_GSMRH_RTSM		((uint)0x00000002)
+#define SCC_GSMRH_RSYN		((uint)0x00000001)
+
+#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
+#define SCC_GSMRL_TCI		((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
+#define SCC_GSMRL_RINV		((uint)0x02000000)
+#define SCC_GSMRL_TINV		((uint)0x01000000)
+#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48	((uint)0x00800000)
+#define SCC_GSMRL_TPL_32	((uint)0x00600000)
+#define SCC_GSMRL_TPL_16	((uint)0x00400000)
+#define SCC_GSMRL_TPL_8		((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
+#define SCC_GSMRL_TPP_01	((uint)0x00100000)
+#define SCC_GSMRL_TPP_10	((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
+#define SCC_GSMRL_TEND		((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
+#define SCC_GSMRL_ENR		((uint)0x00000020)
+#define SCC_GSMRL_ENT		((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
+#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
+
+#define SCC_TODR_TOD		((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define	SCCM_TXE	((unsigned char)0x10)
+#define	SCCM_BSY	((unsigned char)0x04)
+#define	SCCM_TX		((unsigned char)0x02)
+#define	SCCM_RX		((unsigned char)0x01)
+
+typedef struct scc_param {
+	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
+	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
+	u_char	scc_rfcr;	/* Rx function code */
+	u_char	scc_tfcr;	/* Tx function code */
+	ushort	scc_mrblr;	/* Max receive buffer length */
+	uint	scc_rstate;	/* Internal */
+	uint	scc_idp;	/* Internal */
+	ushort	scc_rbptr;	/* Internal */
+	ushort	scc_ibc;	/* Internal */
+	uint	scc_rxtmp;	/* Internal */
+	uint	scc_tstate;	/* Internal */
+	uint	scc_tdp;	/* Internal */
+	ushort	scc_tbptr;	/* Internal */
+	ushort	scc_tbc;	/* Internal */
+	uint	scc_txtmp;	/* Internal */
+	uint	scc_rcrc;	/* Internal */
+	uint	scc_tcrc;	/* Internal */
+} sccp_t;
+
+/* CPM Ethernet through SCC1.
+ */
+typedef struct scc_enet {
+	sccp_t	sen_genscc;
+	uint	sen_cpres;	/* Preset CRC */
+	uint	sen_cmask;	/* Constant mask for CRC */
+	uint	sen_crcec;	/* CRC Error counter */
+	uint	sen_alec;	/* alignment error counter */
+	uint	sen_disfc;	/* discard frame counter */
+	ushort	sen_pads;	/* Tx short frame pad character */
+	ushort	sen_retlim;	/* Retry limit threshold */
+	ushort	sen_retcnt;	/* Retry limit counter */
+	ushort	sen_maxflr;	/* maximum frame length register */
+	ushort	sen_minflr;	/* minimum frame length register */
+	ushort	sen_maxd1;	/* maximum DMA1 length */
+	ushort	sen_maxd2;	/* maximum DMA2 length */
+	ushort	sen_maxd;	/* Rx max DMA */
+	ushort	sen_dmacnt;	/* Rx DMA counter */
+	ushort	sen_maxb;	/* Max BD byte count */
+	ushort	sen_gaddr1;	/* Group address filter */
+	ushort	sen_gaddr2;
+	ushort	sen_gaddr3;
+	ushort	sen_gaddr4;
+	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf0rba;	/* Internal */
+	uint	sen_tbuf0crc;	/* Internal */
+	ushort	sen_tbuf0bcnt;	/* Internal */
+	ushort	sen_paddrh;	/* physical address (MSB) */
+	ushort	sen_paddrm;
+	ushort	sen_paddrl;	/* physical address (LSB) */
+	ushort	sen_pper;	/* persistence */
+	ushort	sen_rfbdptr;	/* Rx first BD pointer */
+	ushort	sen_tfbdptr;	/* Tx first BD pointer */
+	ushort	sen_tlbdptr;	/* Tx last BD pointer */
+	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf1rba;	/* Internal */
+	uint	sen_tbuf1crc;	/* Internal */
+	ushort	sen_tbuf1bcnt;	/* Internal */
+	ushort	sen_txlen;	/* Tx Frame length counter */
+	ushort	sen_iaddr1;	/* Individual address filter */
+	ushort	sen_iaddr2;
+	ushort	sen_iaddr3;
+	ushort	sen_iaddr4;
+	ushort	sen_boffcnt;	/* Backoff counter */
+
+	/* NOTE: Some versions of the manual have the following items
+	 * incorrectly documented.  Below is the proper order.
+	 */
+	ushort	sen_taddrh;	/* temp address (MSB) */
+	ushort	sen_taddrm;
+	ushort	sen_taddrl;	/* temp address (LSB) */
+} scc_enet_t;
+
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
+#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
+#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
+#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
+#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
+#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
+
+/* SCC Mode Register (PSMR) as used by Ethernet.
+*/
+#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
+#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
+#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
+#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
+#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
+#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
+#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
+#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
+#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
+#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
+#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
+#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
+#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_RX_EMPTY	((ushort)0x8000)
+#define BD_ENET_RX_WRAP		((ushort)0x2000)
+#define BD_ENET_RX_INTR		((ushort)0x1000)
+#define BD_ENET_RX_LAST		((ushort)0x0800)
+#define BD_ENET_RX_FIRST	((ushort)0x0400)
+#define BD_ENET_RX_MISS		((ushort)0x0100)
+#define BD_ENET_RX_BC		((ushort)0x0080)	/* FCC Only */
+#define BD_ENET_RX_MC		((ushort)0x0040)	/* FCC Only */
+#define BD_ENET_RX_LG		((ushort)0x0020)
+#define BD_ENET_RX_NO		((ushort)0x0010)
+#define BD_ENET_RX_SH		((ushort)0x0008)
+#define BD_ENET_RX_CR		((ushort)0x0004)
+#define BD_ENET_RX_OV		((ushort)0x0002)
+#define BD_ENET_RX_CL		((ushort)0x0001)
+#define BD_ENET_RX_STATS	((ushort)0x01ff)	/* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_TX_READY	((ushort)0x8000)
+#define BD_ENET_TX_PAD		((ushort)0x4000)
+#define BD_ENET_TX_WRAP		((ushort)0x2000)
+#define BD_ENET_TX_INTR		((ushort)0x1000)
+#define BD_ENET_TX_LAST		((ushort)0x0800)
+#define BD_ENET_TX_TC		((ushort)0x0400)
+#define BD_ENET_TX_DEF		((ushort)0x0200)
+#define BD_ENET_TX_HB		((ushort)0x0100)
+#define BD_ENET_TX_LC		((ushort)0x0080)
+#define BD_ENET_TX_RL		((ushort)0x0040)
+#define BD_ENET_TX_RCMASK	((ushort)0x003c)
+#define BD_ENET_TX_UN		((ushort)0x0002)
+#define BD_ENET_TX_CSL		((ushort)0x0001)
+#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+	sccp_t	scc_genscc;
+	uint	scc_res1;	/* Reserved */
+	uint	scc_res2;	/* Reserved */
+	ushort	scc_maxidl;	/* Maximum idle chars */
+	ushort	scc_idlc;	/* temp idle counter */
+	ushort	scc_brkcr;	/* Break count register */
+	ushort	scc_parec;	/* receive parity error counter */
+	ushort	scc_frmec;	/* receive framing error counter */
+	ushort	scc_nosec;	/* receive noise counter */
+	ushort	scc_brkec;	/* receive break condition counter */
+	ushort	scc_brkln;	/* last received break length */
+	ushort	scc_uaddr1;	/* UART address character 1 */
+	ushort	scc_uaddr2;	/* UART address character 2 */
+	ushort	scc_rtemp;	/* Temp storage */
+	ushort	scc_toseq;	/* Transmit out of sequence char */
+	ushort	scc_char1;	/* control character 1 */
+	ushort	scc_char2;	/* control character 2 */
+	ushort	scc_char3;	/* control character 3 */
+	ushort	scc_char4;	/* control character 4 */
+	ushort	scc_char5;	/* control character 5 */
+	ushort	scc_char6;	/* control character 6 */
+	ushort	scc_char7;	/* control character 7 */
+	ushort	scc_char8;	/* control character 8 */
+	ushort	scc_rccm;	/* receive control character mask */
+	ushort	scc_rccr;	/* receive control character register */
+	ushort	scc_rlbc;	/* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR		((ushort)0x1000)
+#define UART_SCCM_GLT		((ushort)0x0800)
+#define UART_SCCM_AB		((ushort)0x0200)
+#define UART_SCCM_IDL		((ushort)0x0100)
+#define UART_SCCM_GRA		((ushort)0x0080)
+#define UART_SCCM_BRKE		((ushort)0x0040)
+#define UART_SCCM_BRKS		((ushort)0x0020)
+#define UART_SCCM_CCR		((ushort)0x0008)
+#define UART_SCCM_BSY		((ushort)0x0004)
+#define UART_SCCM_TX		((ushort)0x0002)
+#define UART_SCCM_RX		((ushort)0x0001)
+
+/* The SCC PSMR when used as a UART.
+*/
+#define SCU_PSMR_FLC		((ushort)0x8000)
+#define SCU_PSMR_SL		((ushort)0x4000)
+#define SCU_PSMR_CL		((ushort)0x3000)
+#define SCU_PSMR_UM		((ushort)0x0c00)
+#define SCU_PSMR_FRZ		((ushort)0x0200)
+#define SCU_PSMR_RZS		((ushort)0x0100)
+#define SCU_PSMR_SYN		((ushort)0x0080)
+#define SCU_PSMR_DRT		((ushort)0x0040)
+#define SCU_PSMR_PEN		((ushort)0x0010)
+#define SCU_PSMR_RPM		((ushort)0x000c)
+#define SCU_PSMR_REVP		((ushort)0x0008)
+#define SCU_PSMR_TPM		((ushort)0x0003)
+#define SCU_PSMR_TEVP		((ushort)0x0003)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+	sccp_t	st_genscc;
+	uint	st_cpres;	/* Preset CRC */
+	uint	st_cmask;	/* Constant mask for CRC */
+} scc_trans_t;
+
+#define BD_SCC_TX_LAST		((ushort)0x0800)
+
+/* How about some FCCs.....
+*/
+#define FCC_GFMR_DIAG_NORM	((uint)0x00000000)
+#define FCC_GFMR_DIAG_LE	((uint)0x40000000)
+#define FCC_GFMR_DIAG_AE	((uint)0x80000000)
+#define FCC_GFMR_DIAG_ALE	((uint)0xc0000000)
+#define FCC_GFMR_TCI		((uint)0x20000000)
+#define FCC_GFMR_TRX		((uint)0x10000000)
+#define FCC_GFMR_TTX		((uint)0x08000000)
+#define FCC_GFMR_TTX		((uint)0x08000000)
+#define FCC_GFMR_CDP		((uint)0x04000000)
+#define FCC_GFMR_CTSP		((uint)0x02000000)
+#define FCC_GFMR_CDS		((uint)0x01000000)
+#define FCC_GFMR_CTSS		((uint)0x00800000)
+#define FCC_GFMR_SYNL_NONE	((uint)0x00000000)
+#define FCC_GFMR_SYNL_AUTO	((uint)0x00004000)
+#define FCC_GFMR_SYNL_8		((uint)0x00008000)
+#define FCC_GFMR_SYNL_16	((uint)0x0000c000)
+#define FCC_GFMR_RTSM		((uint)0x00002000)
+#define FCC_GFMR_RENC_NRZ	((uint)0x00000000)
+#define FCC_GFMR_RENC_NRZI	((uint)0x00000800)
+#define FCC_GFMR_REVD		((uint)0x00000400)
+#define FCC_GFMR_TENC_NRZ	((uint)0x00000000)
+#define FCC_GFMR_TENC_NRZI	((uint)0x00000100)
+#define FCC_GFMR_TCRC_16	((uint)0x00000000)
+#define FCC_GFMR_TCRC_32	((uint)0x00000080)
+#define FCC_GFMR_ENR		((uint)0x00000020)
+#define FCC_GFMR_ENT		((uint)0x00000010)
+#define FCC_GFMR_MODE_ENET	((uint)0x0000000c)
+#define FCC_GFMR_MODE_ATM	((uint)0x0000000a)
+#define FCC_GFMR_MODE_HDLC	((uint)0x00000000)
+
+/* Generic FCC parameter ram.
+*/
+typedef struct fcc_param {
+	ushort	fcc_riptr;	/* Rx Internal temp pointer */
+	ushort	fcc_tiptr;	/* Tx Internal temp pointer */
+	ushort	fcc_res1;
+	ushort	fcc_mrblr;	/* Max receive buffer length, mod 32 bytes */
+	uint	fcc_rstate;	/* Upper byte is Func code, must be set */
+	uint	fcc_rbase;	/* Receive BD base */
+	ushort	fcc_rbdstat;	/* RxBD status */
+	ushort	fcc_rbdlen;	/* RxBD down counter */
+	uint	fcc_rdptr;	/* RxBD internal data pointer */
+	uint	fcc_tstate;	/* Upper byte is Func code, must be set */
+	uint	fcc_tbase;	/* Transmit BD base */
+	ushort	fcc_tbdstat;	/* TxBD status */
+	ushort	fcc_tbdlen;	/* TxBD down counter */
+	uint	fcc_tdptr;	/* TxBD internal data pointer */
+	uint	fcc_rbptr;	/* Rx BD Internal buf pointer */
+	uint	fcc_tbptr;	/* Tx BD Internal buf pointer */
+	uint	fcc_rcrc;	/* Rx temp CRC */
+	uint	fcc_res2;
+	uint	fcc_tcrc;	/* Tx temp CRC */
+} fccp_t;
+
+
+/* Ethernet controller through FCC.
+*/
+typedef struct fcc_enet {
+	fccp_t	fen_genfcc;
+	uint	fen_statbuf;	/* Internal status buffer */
+	uint	fen_camptr;	/* CAM address */
+	uint	fen_cmask;	/* Constant mask for CRC */
+	uint	fen_cpres;	/* Preset CRC */
+	uint	fen_crcec;	/* CRC Error counter */
+	uint	fen_alec;	/* alignment error counter */
+	uint	fen_disfc;	/* discard frame counter */
+	ushort	fen_retlim;	/* Retry limit */
+	ushort	fen_retcnt;	/* Retry counter */
+	ushort	fen_pper;	/* Persistence */
+	ushort	fen_boffcnt;	/* backoff counter */
+	uint	fen_gaddrh;	/* Group address filter, high 32-bits */
+	uint	fen_gaddrl;	/* Group address filter, low 32-bits */
+	ushort	fen_tfcstat;	/* out of sequence TxBD */
+	ushort	fen_tfclen;
+	uint	fen_tfcptr;
+	ushort	fen_mflr;	/* Maximum frame length (1518) */
+	ushort	fen_paddrh;	/* MAC address */
+	ushort	fen_paddrm;
+	ushort	fen_paddrl;
+	ushort	fen_ibdcount;	/* Internal BD counter */
+	ushort	fen_ibdstart;	/* Internal BD start pointer */
+	ushort	fen_ibdend;	/* Internal BD end pointer */
+	ushort	fen_txlen;	/* Internal Tx frame length counter */
+	uint	fen_ibdbase[8]; /* Internal use */
+	uint	fen_iaddrh;	/* Individual address filter */
+	uint	fen_iaddrl;
+	ushort	fen_minflr;	/* Minimum frame length (64) */
+	ushort	fen_taddrh;	/* Filter transfer MAC address */
+	ushort	fen_taddrm;
+	ushort	fen_taddrl;
+	ushort	fen_padptr;	/* Pointer to pad byte buffer */
+	ushort	fen_cftype;	/* control frame type */
+	ushort	fen_cfrange;	/* control frame range */
+	ushort	fen_maxb;	/* maximum BD count */
+	ushort	fen_maxd1;	/* Max DMA1 length (1520) */
+	ushort	fen_maxd2;	/* Max DMA2 length (1520) */
+	ushort	fen_maxd;	/* internal max DMA count */
+	ushort	fen_dmacnt;	/* internal DMA counter */
+	uint	fen_octc;	/* Total octect counter */
+	uint	fen_colc;	/* Total collision counter */
+	uint	fen_broc;	/* Total broadcast packet counter */
+	uint	fen_mulc;	/* Total multicast packet count */
+	uint	fen_uspc;	/* Total packets < 64 bytes */
+	uint	fen_frgc;	/* Total packets < 64 bytes with errors */
+	uint	fen_ospc;	/* Total packets > 1518 */
+	uint	fen_jbrc;	/* Total packets > 1518 with errors */
+	uint	fen_p64c;	/* Total packets == 64 bytes */
+	uint	fen_p65c;	/* Total packets 64 < bytes <= 127 */
+	uint	fen_p128c;	/* Total packets 127 < bytes <= 255 */
+	uint	fen_p256c;	/* Total packets 256 < bytes <= 511 */
+	uint	fen_p512c;	/* Total packets 512 < bytes <= 1023 */
+	uint	fen_p1024c;	/* Total packets 1024 < bytes <= 1518 */
+	uint	fen_cambuf;	/* Internal CAM buffer poiner */
+	ushort	fen_rfthr;	/* Received frames threshold */
+	ushort	fen_rfcnt;	/* Received frames count */
+} fcc_enet_t;
+
+/* FCC Event/Mask register as used by Ethernet.
+*/
+#define FCC_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
+#define FCC_ENET_RXC	((ushort)0x0040)	/* Control Frame Received */
+#define FCC_ENET_TXC	((ushort)0x0020)	/* Out of seq. Tx sent */
+#define FCC_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
+#define FCC_ENET_RXF	((ushort)0x0008)	/* Full frame received */
+#define FCC_ENET_BSY	((ushort)0x0004)	/* Busy.  Rx Frame dropped */
+#define FCC_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
+#define FCC_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
+
+/* FCC Mode Register (FPSMR) as used by Ethernet.
+*/
+#define FCC_PSMR_HBC	((uint)0x80000000)	/* Enable heartbeat */
+#define FCC_PSMR_FC	((uint)0x40000000)	/* Force Collision */
+#define FCC_PSMR_SBT	((uint)0x20000000)	/* Stop backoff timer */
+#define FCC_PSMR_LPB	((uint)0x10000000)	/* Local protect. 1 = FDX */
+#define FCC_PSMR_LCW	((uint)0x08000000)	/* Late collision select */
+#define FCC_PSMR_FDE	((uint)0x04000000)	/* Full Duplex Enable */
+#define FCC_PSMR_MON	((uint)0x02000000)	/* RMON Enable */
+#define FCC_PSMR_PRO	((uint)0x00400000)	/* Promiscuous Enable */
+#define FCC_PSMR_FCE	((uint)0x00200000)	/* Flow Control Enable */
+#define FCC_PSMR_RSH	((uint)0x00100000)	/* Receive Short Frames */
+#define FCC_PSMR_CAM	((uint)0x00000400)	/* CAM enable */
+#define FCC_PSMR_BRO	((uint)0x00000200)	/* Broadcast pkt discard */
+#define FCC_PSMR_ENCRC	((uint)0x00000080)	/* Use 32-bit CRC */
+
+/* IIC parameter RAM.
+*/
+typedef struct iic {
+	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
+	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
+	u_char	iic_rfcr;	/* Rx function code */
+	u_char	iic_tfcr;	/* Tx function code */
+	ushort	iic_mrblr;	/* Max receive buffer length */
+	uint	iic_rstate;	/* Internal */
+	uint	iic_rdp;	/* Internal */
+	ushort	iic_rbptr;	/* Internal */
+	ushort	iic_rbc;	/* Internal */
+	uint	iic_rxtmp;	/* Internal */
+	uint	iic_tstate;	/* Internal */
+	uint	iic_tdp;	/* Internal */
+	ushort	iic_tbptr;	/* Internal */
+	ushort	iic_tbc;	/* Internal */
+	uint	iic_txtmp;	/* Internal */
+} iic_t;
+
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
+	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
+	u_char	spi_rfcr;	/* Rx function code */
+	u_char	spi_tfcr;	/* Tx function code */
+	ushort	spi_mrblr;	/* Max receive buffer length */
+	uint	spi_rstate;	/* Internal */
+	uint	spi_rdp;	/* Internal */
+	ushort	spi_rbptr;	/* Internal */
+	ushort	spi_rbc;	/* Internal */
+	uint	spi_rxtmp;	/* Internal */
+	uint	spi_tstate;	/* Internal */
+	uint	spi_tdp;	/* Internal */
+	ushort	spi_tbptr;	/* Internal */
+	ushort	spi_tbc;	/* Internal */
+	uint	spi_txtmp;	/* Internal */
+	uint	spi_res;	/* Tx temp. */
+	uint	spi_res1[4];	/* SDMA temp. */
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
+#define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
+#define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
+#define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
+#define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
+#define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
+#define SPMODE_EN	((ushort)0x0100)	/* Enable */
+#define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
+#define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
+
+#define SPMODE_LEN(x)	((((x)-1)&0xF)<<4)
+#define SPMODE_PM(x)	((x) &0xF)
+
+#define SPI_EB		((u_char)0x10)		/* big endian byte order */
+
+#define BD_IIC_START	((ushort)0x0400)
+
+/*-----------------------------------------------------------------------
+ * CMXFCR - CMX FCC Clock Route Register                                15-12
+ */
+#define CMXFCR_FC1         0x40000000   /* FCC1 connection              */
+#define CMXFCR_RF1CS_MSK   0x38000000   /* Receive FCC1 Clock Source Mask */
+#define CMXFCR_TF1CS_MSK   0x07000000   /* Transmit FCC1 Clock Source Mask */
+#define CMXFCR_FC2         0x00400000   /* FCC2 connection              */
+#define CMXFCR_RF2CS_MSK   0x00380000   /* Receive FCC2 Clock Source Mask */
+#define CMXFCR_TF2CS_MSK   0x00070000   /* Transmit FCC2 Clock Source Mask */
+#define CMXFCR_FC3         0x00004000   /* FCC3 connection              */
+#define CMXFCR_RF3CS_MSK   0x00003800   /* Receive FCC3 Clock Source Mask */
+#define CMXFCR_TF3CS_MSK   0x00000700   /* Transmit FCC3 Clock Source Mask */
+
+#define CMXFCR_RF1CS_BRG5  0x00000000   /* Receive FCC1 Clock Source is BRG5 */
+#define CMXFCR_RF1CS_BRG6  0x08000000   /* Receive FCC1 Clock Source is BRG6 */
+#define CMXFCR_RF1CS_BRG7  0x10000000   /* Receive FCC1 Clock Source is BRG7 */
+#define CMXFCR_RF1CS_BRG8  0x18000000   /* Receive FCC1 Clock Source is BRG8 */
+#define CMXFCR_RF1CS_CLK9  0x20000000   /* Receive FCC1 Clock Source is CLK9 */
+#define CMXFCR_RF1CS_CLK10 0x28000000   /* Receive FCC1 Clock Source is CLK10 */
+#define CMXFCR_RF1CS_CLK11 0x30000000   /* Receive FCC1 Clock Source is CLK11 */
+#define CMXFCR_RF1CS_CLK12 0x38000000   /* Receive FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_TF1CS_BRG5  0x00000000   /* Transmit FCC1 Clock Source is BRG5 */
+#define CMXFCR_TF1CS_BRG6  0x01000000   /* Transmit FCC1 Clock Source is BRG6 */
+#define CMXFCR_TF1CS_BRG7  0x02000000   /* Transmit FCC1 Clock Source is BRG7 */
+#define CMXFCR_TF1CS_BRG8  0x03000000   /* Transmit FCC1 Clock Source is BRG8 */
+#define CMXFCR_TF1CS_CLK9  0x04000000   /* Transmit FCC1 Clock Source is CLK9 */
+#define CMXFCR_TF1CS_CLK10 0x05000000   /* Transmit FCC1 Clock Source is CLK10 */
+#define CMXFCR_TF1CS_CLK11 0x06000000   /* Transmit FCC1 Clock Source is CLK11 */
+#define CMXFCR_TF1CS_CLK12 0x07000000   /* Transmit FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_RF2CS_BRG5  0x00000000   /* Receive FCC2 Clock Source is BRG5 */
+#define CMXFCR_RF2CS_BRG6  0x00080000   /* Receive FCC2 Clock Source is BRG6 */
+#define CMXFCR_RF2CS_BRG7  0x00100000   /* Receive FCC2 Clock Source is BRG7 */
+#define CMXFCR_RF2CS_BRG8  0x00180000   /* Receive FCC2 Clock Source is BRG8 */
+#define CMXFCR_RF2CS_CLK13 0x00200000   /* Receive FCC2 Clock Source is CLK13 */
+#define CMXFCR_RF2CS_CLK14 0x00280000   /* Receive FCC2 Clock Source is CLK14 */
+#define CMXFCR_RF2CS_CLK15 0x00300000   /* Receive FCC2 Clock Source is CLK15 */
+#define CMXFCR_RF2CS_CLK16 0x00380000   /* Receive FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_TF2CS_BRG5  0x00000000   /* Transmit FCC2 Clock Source is BRG5 */
+#define CMXFCR_TF2CS_BRG6  0x00010000   /* Transmit FCC2 Clock Source is BRG6 */
+#define CMXFCR_TF2CS_BRG7  0x00020000   /* Transmit FCC2 Clock Source is BRG7 */
+#define CMXFCR_TF2CS_BRG8  0x00030000   /* Transmit FCC2 Clock Source is BRG8 */
+#define CMXFCR_TF2CS_CLK13 0x00040000   /* Transmit FCC2 Clock Source is CLK13 */
+#define CMXFCR_TF2CS_CLK14 0x00050000   /* Transmit FCC2 Clock Source is CLK14 */
+#define CMXFCR_TF2CS_CLK15 0x00060000   /* Transmit FCC2 Clock Source is CLK15 */
+#define CMXFCR_TF2CS_CLK16 0x00070000   /* Transmit FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_RF3CS_BRG5  0x00000000   /* Receive FCC3 Clock Source is BRG5 */
+#define CMXFCR_RF3CS_BRG6  0x00000800   /* Receive FCC3 Clock Source is BRG6 */
+#define CMXFCR_RF3CS_BRG7  0x00001000   /* Receive FCC3 Clock Source is BRG7 */
+#define CMXFCR_RF3CS_BRG8  0x00001800   /* Receive FCC3 Clock Source is BRG8 */
+#define CMXFCR_RF3CS_CLK13 0x00002000   /* Receive FCC3 Clock Source is CLK13 */
+#define CMXFCR_RF3CS_CLK14 0x00002800   /* Receive FCC3 Clock Source is CLK14 */
+#define CMXFCR_RF3CS_CLK15 0x00003000   /* Receive FCC3 Clock Source is CLK15 */
+#define CMXFCR_RF3CS_CLK16 0x00003800   /* Receive FCC3 Clock Source is CLK16 */
+
+#define CMXFCR_TF3CS_BRG5  0x00000000   /* Transmit FCC3 Clock Source is BRG5 */
+#define CMXFCR_TF3CS_BRG6  0x00000100   /* Transmit FCC3 Clock Source is BRG6 */
+#define CMXFCR_TF3CS_BRG7  0x00000200   /* Transmit FCC3 Clock Source is BRG7 */
+#define CMXFCR_TF3CS_BRG8  0x00000300   /* Transmit FCC3 Clock Source is BRG8 */
+#define CMXFCR_TF3CS_CLK13 0x00000400   /* Transmit FCC3 Clock Source is CLK13 */
+#define CMXFCR_TF3CS_CLK14 0x00000500   /* Transmit FCC3 Clock Source is CLK14 */
+#define CMXFCR_TF3CS_CLK15 0x00000600   /* Transmit FCC3 Clock Source is CLK15 */
+#define CMXFCR_TF3CS_CLK16 0x00000700   /* Transmit FCC3 Clock Source is CLK16 */
+
+/*-----------------------------------------------------------------------
+ * CMXSCR - CMX SCC Clock Route Register                                15-14
+ */
+#define CMXSCR_GR1         0x80000000   /* Grant Support of SCC1        */
+#define CMXSCR_SC1         0x40000000   /* SCC1 connection              */
+#define CMXSCR_RS1CS_MSK   0x38000000   /* Receive SCC1 Clock Source Mask */
+#define CMXSCR_TS1CS_MSK   0x07000000   /* Transmit SCC1 Clock Source Mask */
+#define CMXSCR_GR2         0x00800000   /* Grant Support of SCC2        */
+#define CMXSCR_SC2         0x00400000   /* SCC2 connection              */
+#define CMXSCR_RS2CS_MSK   0x00380000   /* Receive SCC2 Clock Source Mask */
+#define CMXSCR_TS2CS_MSK   0x00070000   /* Transmit SCC2 Clock Source Mask */
+#define CMXSCR_GR3         0x00008000   /* Grant Support of SCC3        */
+#define CMXSCR_SC3         0x00004000   /* SCC3 connection              */
+#define CMXSCR_RS3CS_MSK   0x00003800   /* Receive SCC3 Clock Source Mask */
+#define CMXSCR_TS3CS_MSK   0x00000700   /* Transmit SCC3 Clock Source Mask */
+#define CMXSCR_GR4         0x00000080   /* Grant Support of SCC4        */
+#define CMXSCR_SC4         0x00000040   /* SCC4 connection              */
+#define CMXSCR_RS4CS_MSK   0x00000038   /* Receive SCC4 Clock Source Mask */
+#define CMXSCR_TS4CS_MSK   0x00000007   /* Transmit SCC4 Clock Source Mask */
+
+#define CMXSCR_RS1CS_BRG1  0x00000000   /* SCC1 Rx Clock Source is BRG1 */
+#define CMXSCR_RS1CS_BRG2  0x08000000   /* SCC1 Rx Clock Source is BRG2 */
+#define CMXSCR_RS1CS_BRG3  0x10000000   /* SCC1 Rx Clock Source is BRG3 */
+#define CMXSCR_RS1CS_BRG4  0x18000000   /* SCC1 Rx Clock Source is BRG4 */
+#define CMXSCR_RS1CS_CLK11 0x20000000   /* SCC1 Rx Clock Source is CLK11 */
+#define CMXSCR_RS1CS_CLK12 0x28000000   /* SCC1 Rx Clock Source is CLK12 */
+#define CMXSCR_RS1CS_CLK3  0x30000000   /* SCC1 Rx Clock Source is CLK3 */
+#define CMXSCR_RS1CS_CLK4  0x38000000   /* SCC1 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS1CS_BRG1  0x00000000   /* SCC1 Tx Clock Source is BRG1 */
+#define CMXSCR_TS1CS_BRG2  0x01000000   /* SCC1 Tx Clock Source is BRG2 */
+#define CMXSCR_TS1CS_BRG3  0x02000000   /* SCC1 Tx Clock Source is BRG3 */
+#define CMXSCR_TS1CS_BRG4  0x03000000   /* SCC1 Tx Clock Source is BRG4 */
+#define CMXSCR_TS1CS_CLK11 0x04000000   /* SCC1 Tx Clock Source is CLK11 */
+#define CMXSCR_TS1CS_CLK12 0x05000000   /* SCC1 Tx Clock Source is CLK12 */
+#define CMXSCR_TS1CS_CLK3  0x06000000   /* SCC1 Tx Clock Source is CLK3 */
+#define CMXSCR_TS1CS_CLK4  0x07000000   /* SCC1 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS2CS_BRG1  0x00000000   /* SCC2 Rx Clock Source is BRG1 */
+#define CMXSCR_RS2CS_BRG2  0x00080000   /* SCC2 Rx Clock Source is BRG2 */
+#define CMXSCR_RS2CS_BRG3  0x00100000   /* SCC2 Rx Clock Source is BRG3 */
+#define CMXSCR_RS2CS_BRG4  0x00180000   /* SCC2 Rx Clock Source is BRG4 */
+#define CMXSCR_RS2CS_CLK11 0x00200000   /* SCC2 Rx Clock Source is CLK11 */
+#define CMXSCR_RS2CS_CLK12 0x00280000   /* SCC2 Rx Clock Source is CLK12 */
+#define CMXSCR_RS2CS_CLK3  0x00300000   /* SCC2 Rx Clock Source is CLK3 */
+#define CMXSCR_RS2CS_CLK4  0x00380000   /* SCC2 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS2CS_BRG1  0x00000000   /* SCC2 Tx Clock Source is BRG1 */
+#define CMXSCR_TS2CS_BRG2  0x00010000   /* SCC2 Tx Clock Source is BRG2 */
+#define CMXSCR_TS2CS_BRG3  0x00020000   /* SCC2 Tx Clock Source is BRG3 */
+#define CMXSCR_TS2CS_BRG4  0x00030000   /* SCC2 Tx Clock Source is BRG4 */
+#define CMXSCR_TS2CS_CLK11 0x00040000   /* SCC2 Tx Clock Source is CLK11 */
+#define CMXSCR_TS2CS_CLK12 0x00050000   /* SCC2 Tx Clock Source is CLK12 */
+#define CMXSCR_TS2CS_CLK3  0x00060000   /* SCC2 Tx Clock Source is CLK3 */
+#define CMXSCR_TS2CS_CLK4  0x00070000   /* SCC2 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS3CS_BRG1  0x00000000   /* SCC3 Rx Clock Source is BRG1 */
+#define CMXSCR_RS3CS_BRG2  0x00000800   /* SCC3 Rx Clock Source is BRG2 */
+#define CMXSCR_RS3CS_BRG3  0x00001000   /* SCC3 Rx Clock Source is BRG3 */
+#define CMXSCR_RS3CS_BRG4  0x00001800   /* SCC3 Rx Clock Source is BRG4 */
+#define CMXSCR_RS3CS_CLK5  0x00002000   /* SCC3 Rx Clock Source is CLK5 */
+#define CMXSCR_RS3CS_CLK6  0x00002800   /* SCC3 Rx Clock Source is CLK6 */
+#define CMXSCR_RS3CS_CLK7  0x00003000   /* SCC3 Rx Clock Source is CLK7 */
+#define CMXSCR_RS3CS_CLK8  0x00003800   /* SCC3 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS3CS_BRG1  0x00000000   /* SCC3 Tx Clock Source is BRG1 */
+#define CMXSCR_TS3CS_BRG2  0x00000100   /* SCC3 Tx Clock Source is BRG2 */
+#define CMXSCR_TS3CS_BRG3  0x00000200   /* SCC3 Tx Clock Source is BRG3 */
+#define CMXSCR_TS3CS_BRG4  0x00000300   /* SCC3 Tx Clock Source is BRG4 */
+#define CMXSCR_TS3CS_CLK5  0x00000400   /* SCC3 Tx Clock Source is CLK5 */
+#define CMXSCR_TS3CS_CLK6  0x00000500   /* SCC3 Tx Clock Source is CLK6 */
+#define CMXSCR_TS3CS_CLK7  0x00000600   /* SCC3 Tx Clock Source is CLK7 */
+#define CMXSCR_TS3CS_CLK8  0x00000700   /* SCC3 Tx Clock Source is CLK8 */
+
+#define CMXSCR_RS4CS_BRG1  0x00000000   /* SCC4 Rx Clock Source is BRG1 */
+#define CMXSCR_RS4CS_BRG2  0x00000008   /* SCC4 Rx Clock Source is BRG2 */
+#define CMXSCR_RS4CS_BRG3  0x00000010   /* SCC4 Rx Clock Source is BRG3 */
+#define CMXSCR_RS4CS_BRG4  0x00000018   /* SCC4 Rx Clock Source is BRG4 */
+#define CMXSCR_RS4CS_CLK5  0x00000020   /* SCC4 Rx Clock Source is CLK5 */
+#define CMXSCR_RS4CS_CLK6  0x00000028   /* SCC4 Rx Clock Source is CLK6 */
+#define CMXSCR_RS4CS_CLK7  0x00000030   /* SCC4 Rx Clock Source is CLK7 */
+#define CMXSCR_RS4CS_CLK8  0x00000038   /* SCC4 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS4CS_BRG1  0x00000000   /* SCC4 Tx Clock Source is BRG1 */
+#define CMXSCR_TS4CS_BRG2  0x00000001   /* SCC4 Tx Clock Source is BRG2 */
+#define CMXSCR_TS4CS_BRG3  0x00000002   /* SCC4 Tx Clock Source is BRG3 */
+#define CMXSCR_TS4CS_BRG4  0x00000003   /* SCC4 Tx Clock Source is BRG4 */
+#define CMXSCR_TS4CS_CLK5  0x00000004   /* SCC4 Tx Clock Source is CLK5 */
+#define CMXSCR_TS4CS_CLK6  0x00000005   /* SCC4 Tx Clock Source is CLK6 */
+#define CMXSCR_TS4CS_CLK7  0x00000006   /* SCC4 Tx Clock Source is CLK7 */
+#define CMXSCR_TS4CS_CLK8  0x00000007   /* SCC4 Tx Clock Source is CLK8 */
+
+#endif /* __CPM_85XX__ */
diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
new file mode 100755
index 0000000..908007c
--- /dev/null
+++ b/include/asm-ppc/e300.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ * Liberty Eran (liberty@freescale.com)
+ */
+
+#ifndef	__E300_H__
+#define __E300_H__
+
+/*
+ * e300 Processor Version & Revision Numbers
+ */
+#define PVR_83xx 0x80830000
+#define PVR_8349_REV10 (PVR_83xx | 0x0010)
+#define PVR_8349_REV11 (PVR_83xx | 0x0011)
+
+/*
+ * Hardware Implementation-Dependent Register 0 (HID0)
+ */
+
+/* #define HID0 1008 already defined in processor.h */
+#define HID0_MASK_MACHINE_CHECK              0x00000000
+#define HID0_ENABLE_MACHINE_CHECK            0x80000000
+
+#define HID0_DISABLE_CACHE_PARITY            0x00000000
+#define HID0_ENABLE_CACHE_PARITY             0x40000000
+
+#define HID0_DISABLE_ADDRESS_PARITY          0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_ADDRESS_PARITY           0x20000000
+
+#define HID0_DISABLE_DATA_PARITY             0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_DATE_PARITY              0x10000000
+
+#define HID0_CORE_CLK_OUT                    0x00000000
+#define HID0_CORE_CLK_OUT_DIV_2              0x08000000
+
+#define HID0_ENABLE_ARTRY_OUT_PRECHARGE      0x00000000 /* on mpc8349ads must be enabled */
+#define HID0_DISABLE_ARTRY_OUT_PRECHARGE     0x01000000
+
+#define HID0_DISABLE_DOSE_MODE               0x00000000
+#define HID0_ENABLE_DOSE_MODE                0x00800000
+
+#define HID0_DISABLE_NAP_MODE                0x00000000
+#define HID0_ENABLE_NAP_MODE                 0x00400000
+
+#define HID0_DISABLE_SLEEP_MODE              0x00000000
+#define HID0_ENABLE_SLEEP_MODE               0x00200000
+
+#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
+#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT  0x00100000
+
+#define HID0_SOFT_RESET                      0x00010000
+
+#define HID0_DISABLE_INSTRUCTION_CACHE       0x00000000
+#define HID0_ENABLE_INSTRUCTION_CACHE        0x00008000
+
+#define HID0_DISABLE_DATA_CACHE              0x00000000
+#define HID0_ENABLE_DATA_CACHE               0x00004000
+
+#define HID0_LOCK_INSTRUCTION_CACHE          0x00002000
+
+#define HID0_LOCK_DATA_CACHE                 0x00001000
+
+#define HID0_INVALIDATE_INSTRUCTION_CACHE    0x00000800
+
+#define HID0_INVALIDATE_DATA_CACHE           0x00000400
+
+#define HID0_DISABLE_M_BIT                   0x00000000
+#define HID0_ENABLE_M_BIT                    0x00000080
+
+#define HID0_FBIOB                           0x00000010
+
+#define HID0_DISABLE_ADDRESS_BROADCAST       0x00000000
+#define HID0_ENABLE_ADDRESS_BROADCAST        0x00000008
+
+#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION  0x00000000
+#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
+
+/*
+ * Hardware Implementation-Dependent Register 2 (HID2)
+ */
+#define HID2		1011
+
+#define HID2_LET       0x08000000
+#define HID2_HBE       0x00040000
+#define HID2_IWLCK_000 0x00000000 /* no ways locked */
+#define HID2_IWLCK_001 0x00002000 /* way 0 locked */
+#define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
+#define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
+#define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
+#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
+#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
+
+
+/* BAT (block address translation */
+#define BATU_BEPI_MSK	    0xfffe0000
+#define BATU_BL_MSK         0x00001ffc
+
+#define BATU_BL_128K        0x00000000
+#define BATU_BL_256K        0x00000004
+#define BATU_BL_512K        0x0000000c
+#define BATU_BL_1M          0x0000001c
+#define BATU_BL_2M          0x0000003c
+#define BATU_BL_4M          0x0000007c
+#define BATU_BL_8M          0x000000fc
+#define BATU_BL_16M         0x000001fc
+#define BATU_BL_32M         0x000003fc
+#define BATU_BL_64M         0x000007fc
+#define BATU_BL_128M        0x00000ffc
+#define BATU_BL_256M        0x00001ffc
+
+#define BATU_VS             0x00000002
+#define BATU_VP             0x00000001
+
+#define BATL_BRPN_MSK       0xfffe0000
+#define BATL_WIMG_MSK       0x00000078
+
+#define BATL_WRITETHROUGH   0x00000040
+#define BATL_CACHEINHIBIT   0x00000020
+#define BATL_MEMCOHERENCE   0x00000010
+#define BATL_GUARDEDSTORAGE 0x00000008
+
+#define BATL_PP_MSK         0x00000003
+#define BATL_PP_00          0x00000000 /* No access */
+#define BATL_PP_01          0x00000001 /* Read-only */
+#define BATL_PP_10          0x00000002 /* Read-write */
+#define BATL_PP_11        	0x00000003
+
+#endif	/* __E300_H__ */
diff --git a/include/asm-ppc/errno.h b/include/asm-ppc/errno.h
new file mode 100755
index 0000000..ff364b8
--- /dev/null
+++ b/include/asm-ppc/errno.h
@@ -0,0 +1,138 @@
+#ifndef _PPC_ERRNO_H
+#define _PPC_ERRNO_H
+
+#define	EPERM		 1	/* Operation not permitted */
+#define	ENOENT		 2	/* No such file or directory */
+#define	ESRCH		 3	/* No such process */
+#define	EINTR		 4	/* Interrupted system call */
+#define	EIO		 5	/* I/O error */
+#define	ENXIO		 6	/* No such device or address */
+#define	E2BIG		 7	/* Arg list too long */
+#define	ENOEXEC		 8	/* Exec format error */
+#define	EBADF		 9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+#define	ENOSYS		38	/* Function not implemented */
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+#define	EDEADLOCK	58	/* File locking deadlock error */
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale NFS file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+
+/* Should never be seen by user programs */
+#define ERESTARTSYS	512
+#define ERESTARTNOINTR	513
+#define ERESTARTNOHAND	514	/* restart if no handler.. */
+#define ENOIOCTLCMD	515	/* No ioctl command */
+
+#define _LAST_ERRNO	515
+
+#endif
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
new file mode 100755
index 0000000..b73af96
--- /dev/null
+++ b/include/asm-ppc/global_data.h
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+#include "asm/types.h"
+
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+
+typedef	struct	global_data {
+	bd_t		*bd;
+	unsigned long	flags;
+	unsigned long	baudrate;
+	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
+	unsigned long	bus_clk;
+#if defined(CONFIG_CPM2)
+	/* There are many clocks on the MPC8260 - see page 9-5 */
+	unsigned long	vco_out;
+	unsigned long	cpm_clk;
+	unsigned long	scc_clk;
+	unsigned long	brg_clk;
+#endif
+#if defined(CONFIG_MPC83XX)
+	/* There are other clocks in the MPC83XX */
+	u32 csb_clk;
+	u32 tsec1_clk;
+	u32 tsec2_clk;
+	u32 core_clk;
+	u32 usbmph_clk;
+	u32 usbdr_clk;
+	u32 i2c_clk;
+	u32 enc_clk;
+	u32 lbiu_clk;
+	u32 lclk_clk;
+	u32 ddr_clk;
+	u32 pci_clk;
+#endif
+#if defined(CONFIG_MPC5xxx)
+	unsigned long	ipb_clk;
+	unsigned long	pci_clk;
+#endif
+#if defined(CONFIG_MPC8220)
+	unsigned long   bExtUart;
+	unsigned long   inp_clk;
+	unsigned long   pci_clk;
+	unsigned long   vco_clk;
+	unsigned long   pev_clk;
+	unsigned long   flb_clk;
+#endif
+	unsigned long	ram_size;	/* RAM size */
+	unsigned long	reloc_off;	/* Relocation Offset */
+	unsigned long	reset_status;	/* reset status register at boot	*/
+	unsigned long	env_addr;	/* Address  of Environment struct	*/
+	unsigned long	env_valid;	/* Checksum of Environment valid?	*/
+	unsigned long	have_console;	/* serial_init() was called		*/
+#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_CPM2)
+	unsigned int	dp_alloc_base;
+	unsigned int	dp_alloc_top;
+#endif
+#if defined(CFG_GT_6426x)
+	unsigned int	mirror_hack[16];
+#endif
+#if defined(CONFIG_A3000)	|| \
+    defined(CONFIG_HIDDEN_DRAGON)  || \
+    defined(CONFIG_MUSENKI)	||  \
+    defined(CONFIG_SANDPOINT)
+	void *		console_addr;
+#endif
+#ifdef CONFIG_AMIGAONEG3SE
+	unsigned long	relocaddr;	/* Start address of U-Boot in RAM */
+#endif
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
+	unsigned long	fb_base;	/* Base address of framebuffer memory	*/
+#endif
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+	unsigned long	post_log_word;  /* Record POST activities */
+	unsigned long	post_init_f_time;  /* When post_init_f started */
+#endif
+#ifdef CONFIG_BOARD_TYPES
+	unsigned long	board_type;
+#endif
+#ifdef CONFIG_MODEM_SUPPORT
+	unsigned long do_mdm_init;
+	unsigned long be_quiet;
+#endif
+#ifdef CONFIG_LWMON
+	unsigned long kbd_status;
+#endif
+	void		**jt;		/* jump table */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC	0x00001		/* Code was relocated to RAM		*/
+#define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
+#define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
+
+#if 1
+#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r29")
+#else /* We could use plain global data, but the resulting code is bigger */
+#define XTRN_DECLARE_GLOBAL_DATA_PTR	extern
+#define DECLARE_GLOBAL_DATA_PTR     XTRN_DECLARE_GLOBAL_DATA_PTR \
+				    gd_t *gd
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h
new file mode 100755
index 0000000..fa9d164
--- /dev/null
+++ b/include/asm-ppc/i2c.h
@@ -0,0 +1,103 @@
+/*
+ * Freescale I2C Controller
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2003, Motorola, Inc.
+ * author: Eran Liberty (liberty@freescale.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_I2C_H_
+#define _ASM_I2C_H_
+
+#include <asm/types.h>
+
+typedef struct i2c
+{
+    u8 adr;          /**< I2C slave address              */
+#define I2C_ADR	      0xFE
+#define I2C_ADR_SHIFT 1
+#define I2C_ADR_RES   ~(I2C_ADR)
+    u8 res0[3];
+    u8 fdr;          /**< I2C frequency divider register */
+#define IC2_FDR       0x3F
+#define IC2_FDR_SHIFT 0
+#define IC2_FDR_RES   ~(IC2_FDR)
+    u8 res1[3];
+    u8 cr;           /**< I2C control redister           */
+#define I2C_CR_MEN	  0x80
+#define I2C_CR_MIEN	  0x40
+#define I2C_CR_MSTA   0x20
+#define I2C_CR_MTX    0x10
+#define I2C_CR_TXAK   0x08
+#define I2C_CR_RSTA   0x04
+#define I2C_CR_BCST   0x01
+    u8 res2[3];
+    u8 sr;           /**< I2C status register            */
+#define I2C_SR_MCF    0x80
+#define I2C_SR_MAAS   0x40
+#define I2C_SR_MBB    0x20
+#define I2C_SR_MAL    0x10
+#define I2C_SR_BCSTM  0x08
+#define I2C_SR_SRW    0x04
+#define I2C_SR_MIF    0x02
+#define I2C_SR_RXAK   0x01
+    u8 res3[3];
+    u8 dr;           /**< I2C data register              */
+#define I2C_DR 0xFF
+#define I2C_DR_SHIFT 0
+#define I2C_DR_RES ~(I2C_DR)
+    u8 res4[3];
+    u8 dfsrr;        /**< I2C digital filter sampling rate register */
+#define I2C_DFSRR 0x3F
+#define I2C_DFSRR_SHIFT 0
+#define I2C_DFSRR_RES ~(I2C_DR)
+    u8 res5[3];
+    u8 res6[0xE8];
+} i2c_t;
+
+#ifndef CFG_HZ
+#error CFG_HZ is not defined in /include/configs/${BOARD}.h
+#endif
+#define I2C_TIMEOUT (CFG_HZ/4)
+
+#ifndef CFG_IMMRBAR
+#error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h
+#endif
+
+#ifndef CFG_I2C_OFFSET
+#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
+#endif
+
+#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
+/*
+ * MPC8349 have two i2c bus
+ */
+extern i2c_t * mpc8349_i2c;
+#define I2C mpc8349_i2c
+#else
+#define I2C ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET))
+#endif
+
+#define I2C_READ  1
+#define I2C_WRITE 0
+
+#endif	/* _ASM_I2C_H_ */
diff --git a/include/asm-ppc/immap_8220.h b/include/asm-ppc/immap_8220.h
new file mode 100755
index 0000000..f9595f4
--- /dev/null
+++ b/include/asm-ppc/immap_8220.h
@@ -0,0 +1,246 @@
+/*
+ * MPC8220 Internal Memory Map
+ * Copyright (c) 2004 TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * The Internal Memory Map of the 8220.
+ *
+ */
+#ifndef __IMMAP_MPC8220__
+#define __IMMAP_MPC8220__
+
+/*
+ * System configuration registers.
+ */
+typedef struct sys_conf {
+    u16     mbar;       /* 0x00 */
+    u16     res1;
+
+    u16     res2;       /* 0x04 */
+    u16     sdramds;
+
+    u32     res3[6];    /* 0x08 */
+
+    u32     cscfg[6];   /* 0x20 */
+
+    u32     res4[2];    /* 0x38 */
+
+    u8      res5[3];    /* 0x40 */
+    u8      rstctrl;
+
+    u8      res6[3];    /* 0x44 */
+    u8      rststat;
+
+    u32     res7[2];    /* 0x48 */
+
+    u32     jtagid;     /* 0x50 */
+} sysconf8220_t;
+
+
+/*
+ * Memory controller registers.
+ */
+typedef struct mem_ctlr {
+    ushort  mode;           /* 0x100 */
+    ushort  res1;
+    u32     ctrl;           /* 0x104 */
+    u32     cfg1;           /* 0x108 */
+    u32     cfg2;           /* 0x10c */
+} memctl8220_t;
+
+/*
+ * XLB Arbitration registers
+ */
+typedef struct xlb_arb
+{
+    uint    res1[16];       /* 0x200 */
+    uint    config;         /* 0x240 */
+    uint    version;        /* 0x244 */
+    uint    status;         /* 0x248 */
+    uint    intEnable;      /* 0x24c */
+    uint    addrCap;        /* 0x250 */
+    uint    busSigCap;      /* 0x254 */
+    uint    addrTenTimeOut; /* 0x258 */
+    uint    dataTenTimeOut; /* 0x25c */
+    uint    busActTimeOut;  /* 0x260 */
+    uint    mastPriEn;      /* 0x264 */
+    uint    mastPriority;   /* 0x268 */
+    uint    baseAddr;       /* 0x26c */
+} xlbarb8220_t;
+
+/*
+ * Flexbus registers
+ */
+typedef struct flexbus
+{
+    ushort  csar0;          /* 0x00 */
+    ushort  res1;
+    uint    csmr0;          /* 0x04 */
+    uint    cscr0;          /* 0x08 */
+
+    ushort  csar1;          /* 0x0c */
+    ushort  res2;
+    uint    csmr1;          /* 0x10 */
+    uint    cscr1;          /* 0x14 */
+
+    ushort  csar2;          /* 0x18 */
+    ushort  res3;
+    uint    csmr2;          /* 0x1c */
+    uint    cscr2;          /* 0x20 */
+
+    ushort  csar3;          /* 0x24 */
+    ushort  res4;
+    uint    csmr3;          /* 0x28 */
+    uint    cscr3;          /* 0x2c */
+
+    ushort  csar4;          /* 0x30 */
+    ushort  res5;
+    uint    csmr4;          /* 0x34 */
+    uint    cscr4;          /* 0x38 */
+
+    ushort  csar5;          /* 0x3c */
+    ushort  res6;
+    uint    csmr5;          /* 0x40 */
+    uint    cscr5;          /* 0x44 */
+} flexbus8220_t;
+
+/*
+ * GPIO registers
+ */
+typedef struct gpio
+{
+    u32     out;        /* 0x00 */
+    u32     obs;        /* 0x04 */
+    u32     obc;        /* 0x08 */
+    u32     obt;        /* 0x0c */
+    u32     en;         /* 0x10 */
+    u32     ebs;        /* 0x14 */
+    u32     ebc;        /* 0x18 */
+    u32     ebt;        /* 0x1c */
+    u32     mc;         /* 0x20 */
+    u32     st;         /* 0x24 */
+    u32     intr;       /* 0x28 */
+} gpio8220_t;
+
+/*
+ * General Purpose Timer registers
+ */
+typedef struct gptimer
+{
+    u8  OCPW;
+    u8  OctIct;
+    u8  Control;
+    u8  Mode;
+
+    u16 Prescl;  /* Prescale */
+    u16 Count;   /* Count */
+
+    u16 PwmWid;  /* PWM Width */
+    u8  PwmOp;   /* Output Polarity */
+    u8  PwmLd;   /* Immediate Update */
+
+    u16 Capture; /* Capture internal counter */
+    u8  OvfPin;  /* Ovf and Pin */
+    u8  Int;     /* Interrupts */
+} gptmr8220_t;
+
+/*
+ * PSC registers
+ */
+typedef struct psc
+{
+    u32 mr1_2;             /* 0x00 Mode reg 1 & 2 */
+    u32 sr_csr;            /* 0x04 Status/Clock Select reg */
+    u32 cr;                /* 0x08 Command reg */
+    u8  xmitbuf[4];        /* 0x0c Receive/Transmit Buffer */
+    u32 ipcr_acr;          /* 0x10 Input Port Change/Auxiliary Control reg */
+    u32 isr_imr;           /* 0x14 Interrupt Status/Mask reg */
+    u32 ctur;              /* 0x18 Counter Timer Upper reg */
+    u32 ctlr;              /* 0x1c Counter Timer Lower reg */
+    u32 rsvd1[4];          /* 0x20 ... 0x2c */
+    u32 ivr;               /* 0x30 Interrupt Vector reg */
+    u32 ipr;               /* 0x34 Input Port reg */
+    u32 opsetr;            /* 0x38 Output Port Set reg */
+    u32 opresetr;          /* 0x3c Output Port Reset reg */
+    u32 sicr;              /* 0x40 PSC/IrDA control reg */
+    u32 ircr1;             /* 0x44 IrDA control reg 1*/
+    u32 ircr2;             /* 0x48 IrDA control reg 2*/
+    u32 irsdr;             /* 0x4c IrDA SIR Divide reg */
+    u32 irmdr;             /* 0x50 IrDA MIR Divide reg */
+    u32 irfdr;             /* 0x54 PSC IrDA FIR Divide reg */
+    u32 rfnum;             /* 0x58 RX-FIFO counter */
+    u32 txnum;             /* 0x5c TX-FIFO counter */
+    u32 rfdata;            /* 0x60 RX-FIFO data */
+    u32 rfstat;            /* 0x64 RX-FIFO status */
+    u32 rfcntl;            /* 0x68 RX-FIFO control */
+    u32 rfalarm;           /* 0x6c RX-FIFO alarm */
+    u32 rfrptr;            /* 0x70 RX-FIFO read pointer */
+    u32 rfwptr;            /* 0x74 RX-FIFO write pointer */
+    u32 rflfrptr;          /* 0x78 RX-FIFO last read frame pointer */
+    u32 rflfwptr;          /* 0x7c RX-FIFO last write frame pointer */
+
+    u32 tfdata;            /* 0x80 TX-FIFO data */
+    u32 tfstat;            /* 0x84 TX-FIFO status */
+    u32 tfcntl;            /* 0x88 TX-FIFO control */
+    u32 tfalarm;           /* 0x8c TX-FIFO alarm */
+    u32 tfrptr;            /* 0x90 TX-FIFO read pointer */
+    u32 tfwptr;            /* 0x94 TX-FIFO write pointer */
+    u32 tflfrptr;          /* 0x98 TX-FIFO last read frame pointer */
+    u32 tflfwptr;          /* 0x9c TX-FIFO last write frame pointer */
+} psc8220_t;
+
+/*
+ * Interrupt Controller registers
+ */
+typedef struct interrupt_controller {
+} intctl8220_t;
+
+
+/* Fast controllers
+*/
+
+/*
+ * I2C registers
+ */
+typedef struct i2c
+{
+    u8   adr;            /* 0x00 */
+    u8   res1[3];
+    u8   fdr;            /* 0x04 */
+    u8   res2[3];
+    u8   cr;             /* 0x08 */
+    u8   res3[3];
+    u8   sr;             /* 0x0C */
+    u8   res4[3];
+    u8   dr;             /* 0x10 */
+    u8   res5[3];
+    u32  reserved0;      /* 0x14 */
+    u32  reserved1;      /* 0x18 */
+    u32  reserved2;      /* 0x1c */
+    u8   icr;            /* 0x20 */
+    u8   res6[3];
+} i2c8220_t;
+
+/*
+ * Port Configuration Registers
+ */
+typedef struct pcfg
+{
+    uint    pcfg0;          /* 0x00 */
+    uint    pcfg1;          /* 0x04 */
+    uint    pcfg2;          /* 0x08 */
+    uint    pcfg3;          /* 0x0c */
+} pcfg8220_t;
+
+/* ...and the whole thing wrapped up....
+*/
+typedef struct immap {
+    sysconf8220_t   im_sysconf; /* System Configuration */
+    memctl8220_t    im_memctl;  /* Memory Controller */
+    xlbarb8220_t    im_xlbarb;  /* XLB Arbitration */
+    psc8220_t       im_psc;     /* PSC controller */
+    flexbus8220_t   im_fb;      /* FlexBus Controller */
+    i2c8220_t       im_i2c;     /* I2C control/status */
+    pcfg8220_t      im_pcfg;    /* Port configuration */
+} immap_t;
+
+#endif /* __IMMAP_MPC8220__ */
diff --git a/include/asm-ppc/immap_8260.h b/include/asm-ppc/immap_8260.h
new file mode 100755
index 0000000..4974ae5
--- /dev/null
+++ b/include/asm-ppc/immap_8260.h
@@ -0,0 +1,599 @@
+/*
+ * MPC8260 Internal Memory Map
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ *
+ * The Internal Memory Map of the 8260.	 I don't know how generic
+ * this will be, as I don't have any knowledge of the subsequent
+ * parts at this time.	I copied this from the 8xx_immap.h.
+ */
+#ifndef __IMMAP_82XX__
+#define __IMMAP_82XX__
+
+/* System configuration registers.
+*/
+typedef struct sys_conf {
+	uint	sc_siumcr;
+	uint	sc_sypcr;
+	char	res1[6];
+	ushort	sc_swsr;
+	char	res2[20];
+	uint	sc_bcr;
+	u_char	sc_ppc_acr;
+	char	res3[3];
+	uint	sc_ppc_alrh;
+	uint	sc_ppc_alrl;
+	u_char	sc_lcl_acr;
+	char	res4[3];
+	uint	sc_lcl_alrh;
+	uint	sc_lcl_alrl;
+	uint	sc_tescr1;
+	uint	sc_tescr2;
+	uint	sc_ltescr1;
+	uint	sc_ltescr2;
+	uint	sc_pdtea;
+	u_char	sc_pdtem;
+	char	res5[3];
+	uint	sc_ldtea;
+	u_char	sc_ldtem;
+	char	res6[163];
+} sysconf8260_t;
+
+
+/* Memory controller registers.
+*/
+typedef struct	mem_ctlr {
+	uint	memc_br0;
+	uint	memc_or0;
+	uint	memc_br1;
+	uint	memc_or1;
+	uint	memc_br2;
+	uint	memc_or2;
+	uint	memc_br3;
+	uint	memc_or3;
+	uint	memc_br4;
+	uint	memc_or4;
+	uint	memc_br5;
+	uint	memc_or5;
+	uint	memc_br6;
+	uint	memc_or6;
+	uint	memc_br7;
+	uint	memc_or7;
+	uint	memc_br8;
+	uint	memc_or8;
+	uint	memc_br9;
+	uint	memc_or9;
+	uint	memc_br10;
+	uint	memc_or10;
+	uint	memc_br11;
+	uint	memc_or11;
+	char	res1[8];
+	uint	memc_mar;
+	char	res2[4];
+	uint	memc_mamr;
+	uint	memc_mbmr;
+	uint	memc_mcmr;
+	char	res3[8];
+	ushort	memc_mptpr;
+	char	res4[2];
+	uint	memc_mdr;
+	char	res5[4];
+	uint	memc_psdmr;
+	uint	memc_lsdmr;
+	u_char	memc_purt;
+	char	res6[3];
+	u_char	memc_psrt;
+	char	res7[3];
+	u_char	memc_lurt;
+	char	res8[3];
+	u_char	memc_lsrt;
+	char	res9[3];
+	uint	memc_immr;
+	uint	memc_pcibr0;
+	uint	memc_pcibr1;
+	char	res10[16];
+	uint	memc_pcimsk0;
+	uint	memc_pcimsk1;
+	char	res11[52];
+} memctl8260_t;
+
+/* System Integration Timers.
+*/
+typedef struct	sys_int_timers {
+	char	res1[32];
+	ushort	sit_tmcntsc;
+	char	res2[2];
+	uint	sit_tmcnt;
+	char	res3[4];
+	uint	sit_tmcntal;
+	char	res4[16];
+	ushort	sit_piscr;
+	char	res5[2];
+	uint	sit_pitc;
+	uint	sit_pitr;
+	char	res6[94];
+	char	res7[390];
+} sit8260_t;
+
+/* PCI
+ */
+typedef struct pci_config {
+	uint	pci_omisr;
+	uint	pci_ominr;
+	char	res1[8];
+	uint	pci_ifqpr;
+	uint	pci_ofqpr;
+	char	res2[8];
+	uint	pci_imr0;
+	uint	pci_imr1;
+	uint	pci_omr0;
+	uint	pci_omr1;
+	uint	pci_odr;
+	char	res3[4];
+	uint	pci_idr;
+	char	res4[20];
+	uint	pci_imisr;
+	uint	pci_imimr;
+	char	res5[24];
+	uint	pci_ifhpr;
+	char	res5_2[4];
+	uint	pci_iftpr;
+	char	res6[4];
+	uint	pci_iphpr;
+	char	res6_2[4];
+	uint	pci_iptpr;
+	char	res7[4];
+	uint	pci_ofhpr;
+	char	res7_2[4];
+	uint	pci_oftpr;
+	char	res8[4];
+	uint	pci_ophpr;
+	char	res8_2[4];
+	uint	pci_optpr;
+	char	res9[8];
+	uint	pci_mucr;
+	char	res10[8];
+	uint	pci_qbar;
+	char	res11[12];
+	uint	pci_dmamr0;
+	uint	pci_dmasr0;
+	uint	pci_dmacdar0;
+	char	res12[4];
+	uint	pci_dmasar0;
+	char	res13[4];
+	uint	pci_dmadar0;
+	char	res14[4];
+	uint	pci_dmabcr0;
+	uint	pci_dmandar0;
+	char	res15[88];
+	uint	pci_dmamr1;
+	uint	pci_dmasr1;
+	uint	pci_dmacdar1;
+	char	res16[4];
+	uint	pci_dmasar1;
+	char	res17[4];
+	uint	pci_dmadar1;
+	char	res18[4];
+	uint	pci_dmabcr1;
+	uint	pci_dmandar1;
+	char	res19[88];
+	uint	pci_dmamr2;
+	uint	pci_dmasr2;
+	uint	pci_dmacdar2;
+	char	res20[4];
+	uint	pci_dmasar2;
+	char	res21[4];
+	uint	pci_dmadar2;
+	char	res22[4];
+	uint	pci_dmabcr2;
+	uint	pci_dmandar2;
+	char	res23[88];
+	uint	pci_dmamr3;
+	uint	pci_dmasr3;
+	uint	pci_dmacdar3;
+	char	res24[4];
+	uint	pci_dmasar3;
+	char	res25[4];
+	uint	pci_dmadar3;
+	char	res26[4];
+	uint	pci_dmabcr3;
+	uint	pci_dmandar3;
+	char	res27[344];
+	uint	pci_potar0;
+	char	res28[4];
+	uint	pci_pobar0;
+	char	res29[4];
+	uint	pci_pocmr0;
+	char	res30[4];
+	uint	pci_potar1;
+	char	res31[4];
+	uint	pci_pobar1;
+	char	res32[4];
+	uint	pci_pocmr1;
+	char	res33[4];
+	uint	pci_potar2;
+	char	res34[4];
+	uint	pci_pobar2;
+	char	res35[4];
+	uint	pci_pocmr2;
+	char	res36[52];
+	uint	pci_ptcr;
+	uint	pci_gpcr;
+	uint	pci_gcr;
+	uint	pci_esr;
+	uint	pci_emr;
+	uint	pci_ecr;
+	uint	pci_eacr;
+	char	res37[4];
+	uint	pci_edcr;
+	char	res38[4];
+	uint	pci_eccr;
+	char	res39[44];
+	uint	pci_pitar1;
+	char	res40[4];
+	uint	pci_pibar1;
+	char	res41[4];
+	uint	pci_picmr1;
+	char	res42[4];
+	uint	pci_pitar0;
+	char	res43[4];
+	uint	pci_pibar0;
+	char	res44[4];
+	uint	pci_picmr0;
+	char	res45[4];
+	uint	pci_cfg_addr;
+	uint	pci_cfg_data;
+	uint	pci_int_ack;
+	char	res46[756];
+}pci8260_t;
+#define PISCR_PIRQ_MASK		((ushort)0xff00)
+#define PISCR_PS		((ushort)0x0080)
+#define PISCR_PIE		((ushort)0x0004)
+#define PISCR_PTF		((ushort)0x0002)
+#define PISCR_PTE		((ushort)0x0001)
+
+/* Interrupt Controller.
+*/
+typedef struct interrupt_controller {
+	ushort	ic_sicr;
+	char	res1[2];
+	uint	ic_sivec;
+	uint	ic_sipnrh;
+	uint	ic_sipnrl;
+	uint	ic_siprr;
+	uint	ic_scprrh;
+	uint	ic_scprrl;
+	uint	ic_simrh;
+	uint	ic_simrl;
+	uint	ic_siexr;
+	char	res2[88];
+} intctl8260_t;
+
+/* Clocks and Reset.
+*/
+typedef struct clk_and_reset {
+	uint	car_sccr;
+	char	res1[4];
+	uint	car_scmr;
+	char	res2[4];
+	uint	car_rsr;
+	uint	car_rmr;
+	char	res[104];
+} car8260_t;
+
+/* Input/Output Port control/status registers.
+ * Names consistent with processor manual, although they are different
+ * from the original 8xx names.......
+ */
+typedef struct io_port {
+	uint	iop_pdira;
+	uint	iop_ppara;
+	uint	iop_psora;
+	uint	iop_podra;
+	uint	iop_pdata;
+	char	res1[12];
+	uint	iop_pdirb;
+	uint	iop_pparb;
+	uint	iop_psorb;
+	uint	iop_podrb;
+	uint	iop_pdatb;
+	char	res2[12];
+	uint	iop_pdirc;
+	uint	iop_pparc;
+	uint	iop_psorc;
+	uint	iop_podrc;
+	uint	iop_pdatc;
+	char	res3[12];
+	uint	iop_pdird;
+	uint	iop_ppard;
+	uint	iop_psord;
+	uint	iop_podrd;
+	uint	iop_pdatd;
+	char	res4[12];
+} iop8260_t;
+
+/* Communication Processor Module Timers
+*/
+typedef struct cpm_timers {
+	u_char	cpmt_tgcr1;
+	char	res1[3];
+	u_char	cpmt_tgcr2;
+	char	res2[11];
+	ushort	cpmt_tmr1;
+	ushort	cpmt_tmr2;
+	ushort	cpmt_trr1;
+	ushort	cpmt_trr2;
+	ushort	cpmt_tcr1;
+	ushort	cpmt_tcr2;
+	ushort	cpmt_tcn1;
+	ushort	cpmt_tcn2;
+	ushort	cpmt_tmr3;
+	ushort	cpmt_tmr4;
+	ushort	cpmt_trr3;
+	ushort	cpmt_trr4;
+	ushort	cpmt_tcr3;
+	ushort	cpmt_tcr4;
+	ushort	cpmt_tcn3;
+	ushort	cpmt_tcn4;
+	ushort	cpmt_ter1;
+	ushort	cpmt_ter2;
+	ushort	cpmt_ter3;
+	ushort	cpmt_ter4;
+	char	res3[584];
+} cpmtimer8260_t;
+
+/* DMA control/status registers.
+*/
+typedef struct sdma_csr {
+	char	res0[24];
+	u_char	sdma_sdsr;
+	char	res1[3];
+	u_char	sdma_sdmr;
+	char	res2[3];
+	u_char	sdma_idsr1;
+	char	res3[3];
+	u_char	sdma_idmr1;
+	char	res4[3];
+	u_char	sdma_idsr2;
+	char	res5[3];
+	u_char	sdma_idmr2;
+	char	res6[3];
+	u_char	sdma_idsr3;
+	char	res7[3];
+	u_char	sdma_idmr3;
+	char	res8[3];
+	u_char	sdma_idsr4;
+	char	res9[3];
+	u_char	sdma_idmr4;
+	char	res10[707];
+} sdma8260_t;
+
+/* Fast controllers
+*/
+typedef struct fcc {
+	uint	fcc_gfmr;
+	uint	fcc_fpsmr;
+	ushort	fcc_ftodr;
+	char	res1[2];
+	ushort	fcc_fdsr;
+	char	res2[2];
+	ushort	fcc_fcce;
+	char	res3[2];
+	ushort	fcc_fccm;
+	char	res4[2];
+	u_char	fcc_fccs;
+	char	res5[3];
+	u_char	fcc_ftirr_phy[4];
+} fcc_t;
+
+/* Fast controllers continued
+ */
+typedef struct fcc_c {
+	uint	fcc_firper;
+	uint	fcc_firer;
+	uint	fcc_firsr_hi;
+	uint	fcc_firsr_lo;
+	u_char	fcc_gfemr;
+	char	res1[15];
+} fcc_c_t;
+
+/* TC Layer
+ */
+typedef struct tclayer {
+	ushort	tc_tcmode;
+	ushort	tc_cdsmr;
+	ushort	tc_tcer;
+	ushort	tc_rcc;
+	ushort	tc_tcmr;
+	ushort	tc_fcc;
+	ushort	tc_ccc;
+	ushort	tc_icc;
+	ushort	tc_tcc;
+	ushort	tc_ecc;
+	char	res1[12];
+} tclayer_t;
+
+/* I2C
+*/
+typedef struct i2c {
+	u_char	i2c_i2mod;
+	char	res1[3];
+	u_char	i2c_i2add;
+	char	res2[3];
+	u_char	i2c_i2brg;
+	char	res3[3];
+	u_char	i2c_i2com;
+	char	res4[3];
+	u_char	i2c_i2cer;
+	char	res5[3];
+	u_char	i2c_i2cmr;
+	char	res6[331];
+} i2c8260_t;
+
+typedef struct scc {		/* Serial communication channels */
+	uint	scc_gsmrl;
+	uint	scc_gsmrh;
+	ushort	scc_psmr;
+	char	res1[2];
+	ushort	scc_todr;
+	ushort	scc_dsr;
+	ushort	scc_scce;
+	char	res2[2];
+	ushort	scc_sccm;
+	char	res3;
+	u_char	scc_sccs;
+	char	res4[8];
+} scc_t;
+
+typedef struct smc {		/* Serial management channels */
+	char	res1[2];
+	ushort	smc_smcmr;
+	char	res2[2];
+	u_char	smc_smce;
+	char	res3[3];
+	u_char	smc_smcm;
+	char	res4[5];
+} smc_t;
+
+/* Serial Peripheral Interface.
+*/
+typedef struct im_spi {
+	ushort	spi_spmode;
+	char	res1[4];
+	u_char	spi_spie;
+	char	res2[3];
+	u_char	spi_spim;
+	char	res3[2];
+	u_char	spi_spcom;
+	char	res4[82];
+} im_spi_t;
+
+/* CPM Mux.
+*/
+typedef struct cpmux {
+	u_char	cmx_si1cr;
+	char	res1;
+	u_char	cmx_si2cr;
+	char	res2;
+	uint	cmx_fcr;
+	uint	cmx_scr;
+	u_char	cmx_smr;
+	char	res3;
+	ushort	cmx_uar;
+	char	res4[16];
+} cpmux_t;
+
+/* SIRAM control
+*/
+typedef struct siram {
+	ushort	si_amr;
+	ushort	si_bmr;
+	ushort	si_cmr;
+	ushort	si_dmr;
+	u_char	si_gmr;
+	char	res1;
+	u_char	si_cmdr;
+	char	res2;
+	u_char	si_str;
+	char	res3;
+	ushort	si_rsr;
+} siramctl_t;
+
+typedef struct mcc {
+	ushort	mcc_mcce;
+	char	res1[2];
+	ushort	mcc_mccm;
+	char	res2[2];
+	u_char	mcc_mccf;
+	char	res3[7];
+} mcc_t;
+
+typedef struct comm_proc {
+	uint	cp_cpcr;
+	uint	cp_rccr;
+	char	res1[14];
+	ushort	cp_rter;
+	char	res2[2];
+	ushort	cp_rtmr;
+	ushort	cp_rtscr;
+	char	res3[2];
+	uint	cp_rtsr;
+	char	res4[12];
+} cpm8260_t;
+
+/* ...and the whole thing wrapped up....
+*/
+typedef struct immap {
+	/* Some references are into the unique and known dpram spaces,
+	 * others are from the generic base.
+	 */
+#define im_dprambase	im_dpram1
+	u_char		im_dpram1[16*1024];
+	char		res1[16*1024];
+	u_char		im_dpram2[4*1024];
+	char		res2[8*1024];
+	u_char		im_dpram3[4*1024];
+	char		res3[16*1024];
+
+	sysconf8260_t	im_siu_conf;	/* SIU Configuration */
+	memctl8260_t	im_memctl;	/* Memory Controller */
+	sit8260_t	im_sit;		/* System Integration Timers */
+	pci8260_t	im_pci;		/* PCI Configuration */
+	intctl8260_t	im_intctl;	/* Interrupt Controller */
+	car8260_t	im_clkrst;	/* Clocks and reset */
+	iop8260_t	im_ioport;	/* IO Port control/status */
+	cpmtimer8260_t	im_cpmtimer;	/* CPM timers */
+	sdma8260_t	im_sdma;	/* SDMA control/status */
+
+	fcc_t		im_fcc[3];	/* Three FCCs */
+
+	char		res4[32];
+	fcc_c_t		im_fcc_c[3];	/* Continued FCCs */
+	char		res4a[32];
+
+	tclayer_t	im_tclayer[8];	/* Eight TCLayers */
+	ushort		tc_tcgsr;
+	ushort		tc_tcger;
+
+	/* First set of baud rate generators.
+	*/
+	char		res4b[236];
+	uint		im_brgc5;
+	uint		im_brgc6;
+	uint		im_brgc7;
+	uint		im_brgc8;
+
+	char		res5[608];
+
+	i2c8260_t	im_i2c;		/* I2C control/status */
+	cpm8260_t	im_cpm;		/* Communication processor */
+
+	/* Second set of baud rate generators.
+	*/
+	uint		im_brgc1;
+	uint		im_brgc2;
+	uint		im_brgc3;
+	uint		im_brgc4;
+
+	scc_t		im_scc[4];	/* Four SCCs */
+	smc_t		im_smc[2];	/* Couple of SMCs */
+	im_spi_t	im_spi;		/* A SPI */
+	cpmux_t		im_cpmux;	/* CPM clock route mux */
+	siramctl_t	im_siramctl1;	/* First SI RAM Control */
+	mcc_t		im_mcc1;	/* First MCC */
+	siramctl_t	im_siramctl2;	/* Second SI RAM Control */
+	mcc_t		im_mcc2;	/* Second MCC */
+
+	char		res6[1184];
+
+	ushort		im_si1txram[256];
+	char		res7[512];
+	ushort		im_si1rxram[256];
+	char		res8[512];
+	ushort		im_si2txram[256];
+	char		res9[512];
+	ushort		im_si2rxram[256];
+	char		res10[512];
+	char		res11[4096];
+} immap_t;
+
+#endif /* __IMMAP_82XX__ */
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
new file mode 100755
index 0000000..6c2c712
--- /dev/null
+++ b/include/asm-ppc/immap_83xx.h
@@ -0,0 +1,1049 @@
+/*
+ * MPC8349 Internal Memory Map
+ * Copyright (c) 2004 Freescale Semiconductor.
+ * Eran Liberty (liberty@freescale.com)
+ *
+ * based on:
+ * - MPC8260 Internal Memory Map
+ *   Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ * - MPC85xx Internal Memory Map
+ *   Copyright(c) 2002,2003 Motorola Inc.
+ *   Xianghua Xiao (x.xiao@motorola.com)
+ */
+#ifndef __IMMAP_8349__
+#define __IMMAP_8349__
+
+#include <asm/types.h>
+#include <asm/i2c.h>
+
+/*
+ * Local Access Window.
+ */
+typedef struct law8349 {
+	u32 bar; /* LBIU local access window base address register */
+/* Identifies the 20 most-significant address bits of the base of local
+ * access window n. The specified base address should be aligned to the
+ * window size, as defined by LBLAWARn[SIZE].
+ */
+#define LAWBAR_BAR         0xFFFFF000
+#define LAWBAR_RES	     ~(LAWBAR_BAR)
+	u32 ar; /* LBIU local access window attribute register */
+} law8349_t;
+
+/*
+ * System configuration registers.
+ */
+typedef struct sysconf8349 {
+	u32 immrbar; /* Internal memory map base address register */
+	u8 res0[0x04];
+	u32 altcbar; /* Alternate configuration base address register */
+/* Identifies the12 most significant address bits of an alternate base
+ * address used for boot sequencer configuration accesses.
+ */
+#define ALTCBAR_BASE_ADDR     0xFFF00000
+#define ALTCBAR_RES           ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
+	u8 res1[0x14];
+	law8349_t lblaw[4]; /* LBIU local access window */
+	u8 res2[0x20];
+	law8349_t pcilaw[2]; /* PCI local access window */
+	u8 res3[0x30];
+	law8349_t ddrlaw[2]; /* DDR local access window */
+	u8 res4[0x50];
+	u32 sgprl; /* System General Purpose Register Low */
+	u32 sgprh; /* System General Purpose Register High */
+	u32 spridr; /* System Part and Revision ID Register */
+#define SPRIDR_PARTID         0xFFFF0000 /* Part Identification. */
+#define SPRIDR_REVID          0x0000FFFF /* Revision Identification. */
+	u8 res5[0x04];
+	u32 spcr; /* System Priority Configuration Register */
+#define SPCR_PCIHPE   0x10000000 /* PCI Highest Priority Enable. */
+#define SPCR_PCIPR    0x03000000 /* PCI bridge system bus request priority. */
+#define SPCR_TBEN     0x00400000 /* E300 PowerPC core time base unit enable. */
+#define SPCR_COREPR   0x00300000 /* E300 PowerPC Core system bus request priority. */
+#define SPCR_TSEC1DP  0x00003000 /* TSEC1 data priority. */
+#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */
+#define SPCR_TSEC1EP  0x00000300 /* TSEC1 emergency priority. */
+#define SPCR_TSEC2DP  0x00000030 /* TSEC2 data priority. */
+#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */
+#define SPCR_TSEC2EP  0x00000003 /* TSEC2 emergency priority. */
+#define SPCR_RES      ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
+			| SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
+			| SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
+	u32 sicrl; /* System General Purpose Register Low */
+#define SICRL_LDP_A   0x80000000
+#define SICRL_USB0    0x40000000
+#define SICRL_USB1    0x20000000
+#define SICRL_UART    0x0C000000
+#define SICRL_GPIO1_A 0x02000000
+#define SICRL_GPIO1_B 0x01000000
+#define SICRL_GPIO1_C 0x00800000
+#define SICRL_GPIO1_D 0x00400000
+#define SICRL_GPIO1_E 0x00200000
+#define SICRL_GPIO1_F 0x00180000
+#define SICRL_GPIO1_G 0x00040000
+#define SICRL_GPIO1_H 0x00020000
+#define SICRL_GPIO1_I 0x00010000
+#define SICRL_GPIO1_J 0x00008000
+#define SICRL_GPIO1_K 0x00004000
+#define SICRL_GPIO1_L 0x00003000
+#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \
+			| SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \
+			| SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \
+			| SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \
+			| SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L )
+	u32 sicrh; /* System General Purpose Register High */
+#define SICRH_DDR     0x80000000
+#define SICRH_TSEC1_A 0x10000000
+#define SICRH_TSEC1_B 0x08000000
+#define SICRH_TSEC1_C 0x04000000
+#define SICRH_TSEC1_D 0x02000000
+#define SICRH_TSEC1_E 0x01000000
+#define SICRH_TSEC1_F 0x00800000
+#define SICRH_TSEC2_A 0x00400000
+#define SICRH_TSEC2_B 0x00200000
+#define SICRH_TSEC2_C 0x00100000
+#define SICRH_TSEC2_D 0x00080000
+#define SICRH_TSEC2_E 0x00040000
+#define SICRH_TSEC2_F 0x00020000
+#define SICRH_TSEC2_G 0x00010000
+#define SICRH_TSEC2_H 0x00008000
+#define SICRH_GPIO2_A 0x00004000
+#define SICRH_GPIO2_B 0x00002000
+#define SICRH_GPIO2_C 0x00001000
+#define SICRH_GPIO2_D 0x00000800
+#define SICRH_GPIO2_E 0x00000400
+#define SICRH_GPIO2_F 0x00000200
+#define SICRH_GPIO2_G 0x00000180
+#define SICRH_GPIO2_H 0x00000060
+#define SICRH_TSOBI1  0x00000002
+#define SICRH_TSOBI2  0x00000001
+#define SICRh_RES     ~(  SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
+			| SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
+			| SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
+			| SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
+			| SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \
+			| SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \
+			| SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \
+			| SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
+			| SICRH_TSOBI2)
+	u8 res6[0xE4];
+} sysconf8349_t;
+
+/*
+ * Watch Dog Timer (WDT) Registers
+ */
+typedef struct wdt8349 {
+	u8 res0[4];
+	u32 swcrr; /* System watchdog control register */
+	u32 swcnr; /* System watchdog count register */
+#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
+#define SWCNR_RES  ~(SWCNR_SWCN)
+	u8 res1[2];
+	u16 swsrr; /* System watchdog service register */
+	u8 res2[0xF0];
+} wdt8349_t;
+
+/*
+ * RTC/PIT Module Registers
+ */
+typedef struct rtclk8349 {
+	u32 cnr; /* control register */
+#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit  */
+#define CNR_CLIN 0x00000040 /* Input Clock Control Bit  */
+#define CNR_AIM  0x00000002 /* Alarm Interrupt Mask Bit  */
+#define CNR_SIM  0x00000001 /* Second Interrupt Mask Bit  */
+#define CNR_RES  ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
+	u32 ldr; /* load register */
+	u32 psr; /* prescale register */
+	u32 ctr; /* register */
+	u32 evr; /* event register */
+#define RTEVR_SIF  0x00000001 /* Second Interrupt Flag Bit  */
+#define RTEVR_AIF  0x00000002 /* Alarm Interrupt Flag Bit  */
+#define RTEVR_RES  ~(EVR_SIF | EVR_AIF)
+	u32 alr; /* alarm register */
+	u8 res0[0xE8];
+} rtclk8349_t;
+
+/*
+ * Global timper module
+ */
+
+typedef struct gtm8349 {
+	u8    cfr1; /* Timer1/2 Configuration  */
+#define CFR1_PCAS 0x80 /* Pair Cascade mode  */
+#define CFR1_BCM  0x40  /* Backward compatible mode  */
+#define CFR1_STP2 0x20 /* Stop timer  */
+#define CFR1_RST2 0x10 /* Reset timer  */
+#define CFR1_GM2  0x08 /* Gate mode for pin 2  */
+#define CFR1_GM1  0x04 /* Gate mode for pin 1  */
+#define CFR1_STP1 0x02 /* Stop timer  */
+#define CFR1_RST1 0x01 /* Reset timer  */
+	u8    res0[3];
+	u8    cfr2; /* Timer3/4 Configuration  */
+#define CFR2_PCAS 0x80 /* Pair Cascade mode  */
+#define CFR2_SCAS 0x40 /* Super Cascade mode  */
+#define CFR2_STP4 0x20 /* Stop timer  */
+#define CFR2_RST4 0x10 /* Reset timer  */
+#define CFR2_GM4  0x08 /* Gate mode for pin 4  */
+#define CFR2_GM3  0x04 /* Gate mode for pin 3  */
+#define CFR2_STP3 0x02 /* Stop timer  */
+#define CFR2_RST3 0x01 /* Reset timer  */
+	u8    res1[10];
+	u16   mdr1; /* Timer1 Mode Register  */
+#define MDR_SPS  0xff00 /* Secondary Prescaler value  */
+#define MDR_CE   0x00c0 /* Capture edge and enable interrupt  */
+#define MDR_OM   0x0020 /* Output mode  */
+#define MDR_ORI  0x0010 /* Output reference interrupt enable  */
+#define MDR_FRR  0x0008 /* Free run/restart  */
+#define MDR_ICLK 0x0006 /* Input clock source for the timer  */
+#define MDR_GE   0x0001 /* Gate enable  */
+	u16   mdr2; /* Timer2 Mode Register  */
+	u16   rfr1; /* Timer1 Reference Register  */
+	u16   rfr2; /* Timer2 Reference Register  */
+	u16   cpr1; /* Timer1 Capture Register  */
+	u16   cpr2; /* Timer2 Capture Register  */
+	u16   cnr1; /* Timer1 Counter Register  */
+	u16   cnr2; /* Timer2 Counter Register  */
+	u16   mdr3; /* Timer3 Mode Register  */
+	u16   mdr4; /* Timer4 Mode Register  */
+	u16   rfr3; /* Timer3 Reference Register  */
+	u16   rfr4; /* Timer4 Reference Register  */
+	u16   cpr3; /* Timer3 Capture Register  */
+	u16   cpr4; /* Timer4 Capture Register  */
+	u16   cnr3; /* Timer3 Counter Register  */
+	u16   cnr4; /* Timer4 Counter Register  */
+	u16   evr1; /* Timer1 Event Register  */
+	u16   evr2; /* Timer2 Event Register  */
+	u16   evr3; /* Timer3 Event Register  */
+	u16   evr4; /* Timer4 Event Register  */
+#define GTEVR_REF 0x0002 /* Output reference event  */
+#define GTEVR_CAP 0x0001 /* Counter Capture event   */
+#define GTEVR_RES ~(EVR_CAP|EVR_REF)
+	u16   psr1; /* Timer1 Prescaler Register  */
+	u16   psr2; /* Timer2 Prescaler Register  */
+	u16   psr3; /* Timer3 Prescaler Register  */
+	u16   psr4; /* Timer4 Prescaler Register  */
+	u8    res[0xC0];
+} gtm8349_t;
+
+/*
+ * Integrated Programmable Interrupt Controller
+ */
+typedef struct ipic8349 {
+	u32    sicfr; /*  System Global Interrupt Configuration Register (SICFR)  */
+#define SICFR_HPI  0x7f000000 /*  Highest Priority Interrupt  */
+#define SICFR_MPSB 0x00400000 /*  Mixed interrupts Priority Scheme for group B  */
+#define SICFR_MPSA 0x00200000 /*  Mixed interrupts Priority Scheme for group A  */
+#define SICFR_IPSD 0x00080000 /*  Internal interrupts Priority Scheme for group D  */
+#define SICFR_IPSA 0x00010000 /*  Internal interrupts Priority Scheme for group A  */
+#define SICFR_HPIT 0x00000300 /*  HPI priority position IPIC output interrupt Type  */
+#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
+	u32    sivcr; /*  System Global Interrupt Vector Register (SIVCR)  */
+#define SICVR_IVECX 0xfc000000 /*  Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation)  */
+#define SICVR_IVEC  0x0000007f /*  Interrupt vector  */
+#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
+	u32    sipnr_h; /*  System Internal Interrupt Pending Register - High (SIPNR_H)  */
+#define SIIH_TSEC1TX 0x80000000 /*  TSEC1 Tx interrupt  */
+#define SIIH_TSEC1RX 0x40000000 /*  TSEC1 Rx interrupt  */
+#define SIIH_TSEC1ER 0x20000000 /*  TSEC1 Eror interrupt  */
+#define SIIH_TSEC2TX 0x10000000 /*  TSEC2 Tx interrupt  */
+#define SIIH_TSEC2RX 0x08000000 /*  TSEC2 Rx interrupt  */
+#define SIIH_TSEC2ER 0x04000000 /*  TSEC2 Eror interrupt  */
+#define SIIH_USB2DR  0x02000000 /*  USB2 DR interrupt  */
+#define SIIH_USB2MPH 0x01000000 /*  USB2 MPH interrupt  */
+#define SIIH_UART1   0x00000080 /*  UART1 interrupt  */
+#define SIIH_UART2   0x00000040 /*  UART2 interrupt  */
+#define SIIH_SEC     0x00000020 /*  SEC interrupt  */
+#define SIIH_I2C1    0x00000004 /*  I2C1 interrupt  */
+#define SIIH_I2C2    0x00000002 /*  I2C1 interrupt  */
+#define SIIH_SPI     0x00000001 /*  SPI interrupt  */
+#define SIIH_RES	~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
+			| SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
+			| SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \
+			| SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \
+			| SIIH_I2C2 | SIIH_SPI)
+	u32    sipnr_l; /*  System Internal Interrupt Pending Register - Low (SIPNR_L)  */
+#define SIIL_RTCS  0x80000000 /*  RTC SECOND interrupt  */
+#define SIIL_PIT   0x40000000 /*  PIT interrupt  */
+#define SIIL_PCI1  0x20000000 /*  PCI1 interrupt  */
+#define SIIL_PCI2  0x10000000 /*  PCI2 interrupt  */
+#define SIIL_RTCA  0x08000000 /*  RTC ALARM interrupt  */
+#define SIIL_MU    0x04000000 /*  Message Unit interrupt  */
+#define SIIL_SBA   0x02000000 /*  System Bus Arbiter interrupt  */
+#define SIIL_DMA   0x01000000 /*  DMA interrupt  */
+#define SIIL_GTM4  0x00800000 /*  GTM4 interrupt  */
+#define SIIL_GTM8  0x00400000 /*  GTM8 interrupt  */
+#define SIIL_GPIO1 0x00200000 /*  GPIO1 interrupt  */
+#define SIIL_GPIO2 0x00100000 /*  GPIO2 interrupt  */
+#define SIIL_DDR   0x00080000 /*  DDR interrupt  */
+#define SIIL_LBC   0x00040000 /*  LBC interrupt  */
+#define SIIL_GTM2  0x00020000 /*  GTM2 interrupt  */
+#define SIIL_GTM6  0x00010000 /*  GTM6 interrupt  */
+#define SIIL_PMC   0x00008000 /*  PMC interrupt  */
+#define SIIL_GTM3  0x00000800 /*  GTM3 interrupt  */
+#define SIIL_GTM7  0x00000400 /*  GTM7 interrupt  */
+#define SIIL_GTM1  0x00000020 /*  GTM1 interrupt  */
+#define SIIL_GTM5  0x00000010 /*  GTM5 interrupt  */
+#define SIIL_DPTC  0x00000001 /*  DPTC interrupt (!!! Invisible for user !!!)  */
+#define SIIL_RES	~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
+			| SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
+			| SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
+			| SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \
+			| SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \
+			| SIIL_GTM5 |SIIL_DPTC )
+	u32    siprr_a; /*  System Internal Interrupt Group A Priority Register (PRR)  */
+	u8     res0[8];
+	u32    siprr_d; /*  System Internal Interrupt Group D Priority Register (PRR)  */
+	u32    simsr_h; /*  System Internal Interrupt Mask Register - High (SIIH)  */
+	u32    simsr_l; /*  System Internal Interrupt Mask Register - Low (SIIL)  */
+	u8     res1[4];
+	u32    sepnr;   /*  System External Interrupt Pending Register (SEI)  */
+	u32    smprr_a; /*  System Mixed Interrupt Group A Priority Register (PRR)  */
+	u32    smprr_b; /*  System Mixed Interrupt Group B Priority Register (PRR)  */
+#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */
+#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */
+#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */
+#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */
+#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */
+#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */
+#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */
+#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */
+#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
+	u32    semsr; /*  System External Interrupt Mask Register (SEI)  */
+#define SEI_IRQ0  0x80000000 /*  IRQ0 external interrupt  */
+#define SEI_IRQ1  0x40000000 /*  IRQ1 external interrupt  */
+#define SEI_IRQ2  0x20000000 /*  IRQ2 external interrupt  */
+#define SEI_IRQ3  0x10000000 /*  IRQ3 external interrupt  */
+#define SEI_IRQ4  0x08000000 /*  IRQ4 external interrupt  */
+#define SEI_IRQ5  0x04000000 /*  IRQ5 external interrupt  */
+#define SEI_IRQ6  0x02000000 /*  IRQ6 external interrupt  */
+#define SEI_IRQ7  0x01000000 /*  IRQ7 external interrupt  */
+#define SEI_SIRQ0 0x00008000 /*  SIRQ0 external interrupt  */
+#define SEI_RES		~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \
+			| SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \
+			| SEI_SIRQ0)
+	u32    secnr; /*  System External Interrupt Control Register (SECNR) */
+#define SECNR_MIXB0T 0xc0000000 /*  MIXB0 priority position IPIC output interrupt type  */
+#define SECNR_MIXB1T 0x30000000 /*  MIXB1 priority position IPIC output interrupt type  */
+#define SECNR_MIXA0T 0x00c00000 /*  MIXA0 priority position IPIC output interrupt type  */
+#define SECNR_SYSA1T 0x00300000 /*  MIXA1 priority position IPIC output interrupt type  */
+#define SECNR_EDI0   0x00008000 /*  IRQ0 external interrupt edge/level detect  */
+#define SECNR_EDI1   0x00004000 /*  IRQ1 external interrupt edge/level detect  */
+#define SECNR_EDI2   0x00002000 /*  IRQ2 external interrupt edge/level detect  */
+#define SECNR_EDI3   0x00001000 /*  IRQ3 external interrupt edge/level detect  */
+#define SECNR_EDI4   0x00000800 /*  IRQ4 external interrupt edge/level detect  */
+#define SECNR_EDI5   0x00000400 /*  IRQ5 external interrupt edge/level detect  */
+#define SECNR_EDI6   0x00000200 /*  IRQ6 external interrupt edge/level detect  */
+#define SECNR_EDI7   0x00000100 /*  IRQ7 external interrupt edge/level detect  */
+#define SECNR_RES	~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \
+			| SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \
+			| SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \
+			| SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7)
+	u32   sersr; /*  System Error Status Register (SERR)  */
+	u32   sermr; /*  System Error Mask Register (SERR)  */
+#define SERR_IRQ0 0x80000000 /*  IRQ0 MCP request  */
+#define SERR_WDT  0x40000000 /*  WDT MCP request  */
+#define SERR_SBA  0x20000000 /*  SBA MCP request  */
+#define SERR_DDR  0x10000000 /*  DDR MCP request  */
+#define SERR_LBC  0x08000000 /*  LBC MCP request  */
+#define SERR_PCI1 0x04000000 /*  PCI1 MCP request  */
+#define SERR_PCI2 0x02000000 /*  PCI2 MCP request  */
+#define SERR_MU   0x01000000 /*  MU MCP request  */
+#define SERR_RNC  0x00010000 /*  MU MCP request (!!! Non-visible for users !!!)  */
+#define SERR_RES	~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
+			|SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
+			|SERR_RNC )
+	u32    sercr; /*  System Error Control Register  (SERCR)  */
+#define SERCR_MCPR 0x00000001 /*  MCP Route  */
+#define SERCR_RES ~(SERCR_MCPR)
+	u8    res2[4];
+	u32   sifcr_h; /*  System Internal Interrupt Force Register - High (SIIH)  */
+	u32   sifcr_l; /*  System Internal Interrupt Force Register - Low (SIIL)  */
+	u32   sefcr;   /*  System External Interrupt Force Register (SEI)  */
+	u32   serfr;   /*  System Error Force Register (SERR)  */
+	u8    res3[0xA0];
+} ipic8349_t;
+
+/*
+ * System Arbiter Registers
+ */
+typedef struct arbiter8349 {
+	u32 acr; /* Arbiter Configuration Register */
+#define ACR_COREDIS    0x10000000 /* Core disable. */
+#define ACR_PIPE_DEP   0x00070000 /* Pipeline depth (number of outstanding transactions). */
+#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */
+#define ACR_RPTCNT     0x00000700 /* Repeat count. */
+#define ACR_APARK      0x00000030 /* Address parking. */
+#define ACR_PARKM	   0x0000000F /* Parking master. */
+#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
+	u32 atr; /* Arbiter Timers Register */
+#define ATR_DTO 0x00FF0000 /* Data time out. */
+#define ATR_ATO	0x000000FF /* Address time out. */
+#define ATR_RES ~(ATR_DTO|ATR_ATO)
+	u8 res[4];
+	u32 aer; /* Arbiter Event Register (AE)*/
+	u32 aidr; /* Arbiter Interrupt Definition Register (AE) */
+	u32 amr; /* Arbiter Mask Register (AE) */
+	u32 aeatr; /* Arbiter Event Attributes Register */
+#define AEATR_EVENT   0x07000000 /* Event type. */
+#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */
+#define AEATR_TBST    0x00000800 /* Transfer burst. */
+#define AEATR_TSIZE   0x00000700 /* Transfer Size. */
+#define AEATR_TTYPE	  0x0000001F /* Transfer Type. */
+#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE)
+	u32 aeadr; /* Arbiter Event Address Register */
+	u32 aerr; /* Arbiter Event Response Register (AE)*/
+#define AE_ETEA 0x00000020 /* Transfer error. */
+#define AE_RES_ 0x00000010 /* Reserved transfer type. */
+#define AE_ECW  0x00000008 /* External control word transfer type. */
+#define AE_AO   0x00000004 /* Address Only transfer type. */
+#define AE_DTO  0x00000002 /* Data time out. */
+#define AE_ATO	0x00000001 /* Address time out. */
+#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
+	u8 res1[0xDC];
+} arbiter8349_t;
+
+/*
+ * Reset Module
+ */
+typedef struct reset8349 {
+	u32    rcwl; /* RCWL Register  */
+#define RCWL_LBIUCM  0x80000000 /* LBIUCM  */
+#define RCWL_LBIUCM_SHIFT    31
+#define RCWL_DDRCM   0x40000000 /* DDRCM  */
+#define RCWL_DDRCM_SHIFT     30
+#define RCWL_SVCOD   0x30000000 /* SVCOD  */
+#define RCWL_SPMF    0x0f000000 /* SPMF  */
+#define RCWL_SPMF_SHIFT      24
+#define RCWL_COREPLL 0x007F0000 /* COREPLL  */
+#define RCWL_COREPLL_SHIFT   16
+#define RCWL_CEVCOD  0x000000C0 /* CEVCOD  */
+#define RCWL_CEPDF   0x00000020 /* CEPDF  */
+#define RCWL_CEPMF   0x0000001F /* CEPMF  */
+#define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
+	u32    rcwh; /* RCHL Register  */
+#define RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+#define RCWH_PCIHOST_SHIFT   31
+#define RCWH_PCI64   0x40000000 /* PCI64  */
+#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB  */
+#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB  */
+#define RCWH_COREDIS 0x08000000 /* COREDIS  */
+#define RCWH_BMS     0x04000000 /* BMS  */
+#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ  */
+#define RCWH_SWEN    0x00800000 /* SWEN  */
+#define RCWH_ROMLOC  0x00700000 /* ROMLOC  */
+#define RCWH_TSEC1M  0x0000c000 /* TSEC1M  */
+#define RCWH_TSEC2M  0x00003000 /* TSEC2M  */
+#define RCWH_TPR     0x00000100 /* TPR  */
+#define RCWH_TLE     0x00000008 /* TLE  */
+#define RCWH_LALE    0x00000004 /* LALE  */
+#define RCWH_RES	~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
+			| RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
+			| RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
+			| RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \
+			| RCWH_TLE | RCWH_LALE)
+	u8     res0[8];
+	u32    rsr; /* Reset status Register  */
+#define RSR_RSTSRC 0xE0000000 /* Reset source  */
+#define RSR_RSTSRC_SHIFT   29
+#define RSR_BSF    0x00010000 /* Boot seq. fail  */
+#define RSR_BSF_SHIFT      16
+#define RSR_SWSR   0x00002000 /* software soft reset  */
+#define RSR_SWSR_SHIFT     13
+#define RSR_SWHR   0x00001000 /* software hard reset  */
+#define RSR_SWHR_SHIFT     12
+#define RSR_JHRS   0x00000200 /* jtag hreset  */
+#define RSR_JHRS_SHIFT      9
+#define RSR_JSRS   0x00000100 /* jtag sreset status  */
+#define RSR_JSRS_SHIFT      8
+#define RSR_CSHR   0x00000010 /* checkstop reset status  */
+#define RSR_CSHR_SHIFT      4
+#define RSR_SWRS   0x00000008 /* software watchdog reset status  */
+#define RSR_SWRS_SHIFT      3
+#define RSR_BMRS   0x00000004 /* bus monitop reset status  */
+#define RSR_BMRS_SHIFT      2
+#define RSR_SRS    0x00000002 /* soft reset status  */
+#define RSR_SRS_SHIFT       1
+#define RSR_HRS    0x00000001 /* hard reset status  */
+#define RSR_HRS_SHIFT       0
+#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS)
+	u32    rmr; /* Reset mode Register  */
+#define RMR_CSRE   0x00000001 /* checkstop reset enable  */
+#define RMR_CSRE_SHIFT      0
+#define RMR_RES ~(RMR_CSRE)
+	u32    rpr; /* Reset protection Register  */
+	u32    rcr; /* Reset Control Register  */
+#define RCR_SWHR 0x00000002 /* software hard reset  */
+#define RCR_SWSR 0x00000001 /* software soft reset  */
+#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
+	u32    rcer; /* Reset Control Enable Register  */
+#define RCER_CRE 0x00000001 /* software hard reset  */
+#define RCER_RES ~(RCER_CRE)
+	u8     res1[0xDC];
+} reset8349_t;
+
+typedef struct clk8349 {
+	u32    spmr; /* system PLL mode Register  */
+#define SPMR_LBIUCM  0x80000000 /* LBIUCM  */
+#define SPMR_DDRCM   0x40000000 /* DDRCM  */
+#define SPMR_SVCOD   0x30000000 /* SVCOD  */
+#define SPMR_SPMF    0x0F000000 /* SPMF  */
+#define SPMR_CKID    0x00800000 /* CKID  */
+#define SPMR_CKID_SHIFT 23
+#define SPMR_COREPLL 0x007F0000 /* COREPLL  */
+#define SPMR_CEVCOD  0x000000C0 /* CEVCOD  */
+#define SPMR_CEPDF   0x00000020 /* CEPDF  */
+#define SPMR_CEPMF   0x0000001F /* CEPMF  */
+#define SPMR_RES	~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
+			| SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
+			| SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
+	u32    occr; /* output clock control Register  */
+#define OCCR_PCICOE0 0x80000000 /* PCICOE0  */
+#define OCCR_PCICOE1 0x40000000 /* PCICOE1  */
+#define OCCR_PCICOE2 0x20000000 /* PCICOE2  */
+#define OCCR_PCICOE3 0x10000000 /* PCICOE3  */
+#define OCCR_PCICOE4 0x08000000 /* PCICOE4  */
+#define OCCR_PCICOE5 0x04000000 /* PCICOE5  */
+#define OCCR_PCICOE6 0x02000000 /* PCICOE6  */
+#define OCCR_PCICOE7 0x01000000 /* PCICOE7  */
+#define OCCR_PCICD0  0x00800000 /* PCICD0  */
+#define OCCR_PCICD1  0x00400000 /* PCICD1  */
+#define OCCR_PCICD2  0x00200000 /* PCICD2  */
+#define OCCR_PCICD3  0x00100000 /* PCICD3  */
+#define OCCR_PCICD4  0x00080000 /* PCICD4  */
+#define OCCR_PCICD5  0x00040000 /* PCICD5  */
+#define OCCR_PCICD6  0x00020000 /* PCICD6  */
+#define OCCR_PCICD7  0x00010000 /* PCICD7  */
+#define OCCR_PCI1CR  0x00000002 /* PCI1CR  */
+#define OCCR_PCI2CR  0x00000001 /* PCI2CR  */
+#define OCCR_RES	~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \
+			| OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \
+			| OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \
+			| OCCR_PCICD1 | OCCR_PCICD2  | OCCR_PCICD3 \
+			| OCCR_PCICD4  | OCCR_PCICD5 | OCCR_PCICD6  \
+			| OCCR_PCICD7  | OCCR_PCI1CR  | OCCR_PCI2CR )
+	u32    sccr; /* system clock control Register  */
+#define SCCR_TSEC1CM  0xc0000000 /* TSEC1CM  */
+#define SCCR_TSEC1CM_SHIFT 30
+#define SCCR_TSEC2CM  0x30000000 /* TSEC2CM  */
+#define SCCR_TSEC2CM_SHIFT 28
+#define SCCR_ENCCM    0x03000000 /* ENCCM  */
+#define SCCR_ENCCM_SHIFT 24
+#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM  */
+#define SCCR_USBMPHCM_SHIFT 22
+#define SCCR_USBDRCM  0x00300000 /* USBDRCM  */
+#define SCCR_USBDRCM_SHIFT 20
+#define SCCR_PCICM    0x00010000 /* PCICM  */
+#define SCCR_RES	~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
+			| SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
+	u8     res0[0xF4];
+} clk8349_t;
+
+/*
+ * Power Management Control Module
+ */
+typedef struct pmc8349 {
+	u32    pmccr; /* PMC Configuration Register  */
+#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable  */
+#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable  */
+#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
+	u32    pmcer; /* PMC Event Register  */
+#define PMCER_PMCI  0x00000001 /* PMC Interrupt  */
+#define PMCER_RES ~(PMCER_PMCI)
+	u32    pmcmr; /* PMC Mask Register  */
+#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable  */
+#define PMCMR_RES ~(PMCMR_PMCIE)
+	u8 res0[0xF4];
+} pmc8349_t;
+
+
+/*
+ * general purpose I/O module
+ */
+typedef struct gpio8349 {
+	u32 dir; /* direction register */
+	u32 odr; /* open drain register */
+	u32 dat; /* data register */
+	u32 ier; /* interrupt event register */
+	u32 imr; /* interrupt mask register */
+	u32 icr; /* external interrupt control register */
+	u8 res0[0xE8];
+} gpio8349_t;
+
+/*
+ * DDR Memory Controller Memory Map
+ */
+typedef struct ddr_cs_bnds{
+	u32 csbnds;
+#define CSBNDS_SA 0x00FF0000
+#define CSBNDS_SA_SHIFT    8
+#define CSBNDS_EA 0x000000FF
+#define CSBNDS_EA_SHIFT   24
+	u8  res0[4];
+} ddr_cs_bnds_t;
+
+typedef struct ddr8349{
+	ddr_cs_bnds_t csbnds[4];            /**< Chip Select x Memory Bounds */
+	u8 res0[0x60];
+	u32 cs_config[4];       /**< Chip Select x Configuration */
+#define CSCONFIG_EN         0x80000000
+#define CSCONFIG_AP         0x00800000
+#define CSCONFIG_ROW_BIT    0x00000700
+#define CSCONFIG_ROW_BIT_12 0x00000000
+#define CSCONFIG_ROW_BIT_13 0x00000100
+#define CSCONFIG_ROW_BIT_14 0x00000200
+#define CSCONFIG_COL_BIT    0x00000007
+#define CSCONFIG_COL_BIT_8  0x00000000
+#define CSCONFIG_COL_BIT_9  0x00000001
+#define CSCONFIG_COL_BIT_10 0x00000002
+#define CSCONFIG_COL_BIT_11 0x00000003
+	u8 res1[0x78];
+	u32 timing_cfg_1;       /**< SDRAM Timing Configuration 1 */
+#define TIMING_CFG1_PRETOACT 0x70000000
+#define TIMING_CFG1_PRETOACT_SHIFT   28
+#define TIMING_CFG1_ACTTOPRE 0x0F000000
+#define TIMING_CFG1_ACTTOPRE_SHIFT   24
+#define TIMING_CFG1_ACTTORW  0x00700000
+#define TIMING_CFG1_ACTTORW_SHIFT    20
+#define TIMING_CFG1_CASLAT   0x00070000
+#define TIMING_CFG1_CASLAT_SHIFT     16
+#define TIMING_CFG1_REFREC   0x0000F000
+#define TIMING_CFG1_REFREC_SHIFT     12
+#define TIMING_CFG1_WRREC    0x00000700
+#define TIMING_CFG1_WRREC_SHIFT       8
+#define TIMING_CFG1_ACTTOACT 0x00000070
+#define TIMING_CFG1_ACTTOACT_SHIFT    4
+#define TIMING_CFG1_WRTORD   0x00000007
+#define TIMING_CFG1_WRTORD_SHIFT      0
+#define TIMING_CFG1_CASLAT_20 0x00030000  /* CAS latency = 2.0 */
+#define TIMING_CFG1_CASLAT_25 0x00040000  /* CAS latency = 2.5 */
+
+	u32 timing_cfg_2;       /**< SDRAM Timing Configuration 2 */
+#define TIMING_CFG2_CPO           0x0F000000
+#define TIMING_CFG2_CPO_SHIFT             24
+#define TIMING_CFG2_ACSM          0x00080000
+#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
+#define TIMING_CFG2_WR_DATA_DELAY_SHIFT   10
+#define TIMING_CFG2_CPO_DEF       0x00000000  /* default (= CASLAT + 1) */
+
+	u32 sdram_cfg;          /**< SDRAM Control Configuration */
+#define SDRAM_CFG_MEM_EN     0x80000000
+#define SDRAM_CFG_SREN       0x40000000
+#define SDRAM_CFG_ECC_EN     0x20000000
+#define SDRAM_CFG_RD_EN      0x10000000
+#define SDRAM_CFG_SDRAM_TYPE 0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT   24
+#define SDRAM_CFG_DYN_PWR    0x00200000
+#define SDRAM_CFG_32_BE      0x00080000
+#define SDRAM_CFG_8_BE       0x00040000
+#define SDRAM_CFG_NCAP       0x00020000
+#define SDRAM_CFG_2T_EN      0x00008000
+#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
+
+	u8 res2[4];
+	u32 sdram_mode;         /**< SDRAM Mode Configuration */
+#define SDRAM_MODE_ESD 0xFFFF0000
+#define SDRAM_MODE_ESD_SHIFT   16
+#define SDRAM_MODE_SD  0x0000FFFF
+#define SDRAM_MODE_SD_SHIFT     0
+#define DDR_MODE_EXT_MODEREG    0x4000  /* select extended mode reg */
+#define DDR_MODE_EXT_OPMODE     0x3FF8  /* operating mode, mask */
+#define DDR_MODE_EXT_OP_NORMAL  0x0000  /* normal operation */
+#define DDR_MODE_QFC            0x0004  /* QFC / compatibility, mask */
+#define DDR_MODE_QFC_COMP       0x0000  /* compatible to older SDRAMs */
+#define DDR_MODE_WEAK           0x0002  /* weak drivers */
+#define DDR_MODE_DLL_DIS        0x0001  /* disable DLL */
+#define DDR_MODE_CASLAT         0x0070  /* CAS latency, mask */
+#define DDR_MODE_CASLAT_15      0x0010  /* CAS latency 1.5 */
+#define DDR_MODE_CASLAT_20      0x0020  /* CAS latency 2 */
+#define DDR_MODE_CASLAT_25      0x0060  /* CAS latency 2.5 */
+#define DDR_MODE_CASLAT_30      0x0030  /* CAS latency 3 */
+#define DDR_MODE_BTYPE_SEQ      0x0000  /* sequential burst */
+#define DDR_MODE_BTYPE_ILVD     0x0008  /* interleaved burst */
+#define DDR_MODE_BLEN_2         0x0001  /* burst length 2 */
+#define DDR_MODE_BLEN_4         0x0002  /* burst length 4 */
+#define DDR_REFINT_166MHZ_7US   1302        /* exact value for 7.8125 µs */
+#define DDR_BSTOPRE     256     /* use 256 cycles as a starting point */
+#define DDR_MODE_MODEREG        0x0000  /* select mode register */
+
+	u8 res3[8];
+	u32 sdram_interval;     /**< SDRAM Interval Configuration */
+#define SDRAM_INTERVAL_REFINT  0x3FFF0000
+#define SDRAM_INTERVAL_REFINT_SHIFT    16
+#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
+#define SDRAM_INTERVAL_BSTOPRE_SHIFT    0
+	u8   res9[8];
+	u32  sdram_clk_cntl;
+#define DDR_SDRAM_CLK_CNTL_SS_EN		0x80000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05	0x02000000
+
+	u8 res4[0xCCC];
+	u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
+	u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
+	u32 ecc_err_inject;     /**< Memory Data Path Error Injection Mask ECC */
+	u8 res5[0x14];
+	u32 capture_data_hi;    /**< Memory Data Path Read Capture High */
+	u32 capture_data_lo;    /**< Memory Data Path Read Capture Low */
+	u32 capture_ecc;        /**< Memory Data Path Read Capture ECC */
+	u8 res6[0x14];
+	u32 err_detect;         /**< Memory Error Detect */
+	u32 err_disable;        /**< Memory Error Disable */
+	u32 err_int_en;         /**< Memory Error Interrupt Enable */
+	u32 capture_attributes; /**< Memory Error Attributes Capture */
+	u32 capture_address;    /**< Memory Error Address Capture */
+	u32 capture_ext_address;/**< Memory Error Extended Address Capture */
+	u32 err_sbe;            /**< Memory Single-Bit ECC Error Management */
+	u8 res7[0xA4];
+	u32 debug_reg;
+	u8 res8[0xFC];
+} ddr8349_t;
+
+/*
+ * I2C1 Controller
+ */
+
+
+/*
+ * DUART
+ */
+typedef struct duart8349{
+	u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
+	u8 uier_udmb;      /**< combined register for UIER and UDMB */
+	u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
+	u8 ulcr;        /**< line control register */
+	u8 umcr;        /**< MODEM control register */
+	u8 ulsr;        /**< line status register */
+	u8 umsr;        /**< MODEM status register */
+	u8 uscr;        /**< scratch register */
+	u8 res0[8];
+	u8 udsr;        /**< DMA status register */
+	u8 res1[3];
+	u8 res2[0xEC];
+} duart8349_t;
+
+/*
+ * Local Bus Controller Registers
+ */
+typedef struct lbus_bank{
+	u32 br;             /**< Base Register  */
+	u32 or;             /**< Base Register  */
+} lbus_bank_t;
+
+typedef struct lbus8349 {
+	lbus_bank_t bank[8];
+	u8 res0[0x28];
+	u32 mar;                /**< UPM Address Register */
+	u8 res1[0x4];
+	u32 mamr;               /**< UPMA Mode Register */
+	u32 mbmr;               /**< UPMB Mode Register */
+	u32 mcmr;               /**< UPMC Mode Register */
+	u8 res2[0x8];
+	u32 mrtpr;              /**< Memory Refresh Timer Prescaler Register */
+	u32 mdr;                /**< UPM Data Register */
+	u8 res3[0x8];
+	u32 lsdmr;              /**< SDRAM Mode Register */
+	u8 res4[0x8];
+	u32 lurt;               /**< UPM Refresh Timer */
+	u32 lsrt;               /**< SDRAM Refresh Timer */
+	u8 res5[0x8];
+	u32 ltesr;              /**< Transfer Error Status Register */
+	u32 ltedr;              /**< Transfer Error Disable Register */
+	u32 lteir;              /**< Transfer Error Interrupt Register */
+	u32 lteatr;             /**< Transfer Error Attributes Register */
+	u32 ltear;              /**< Transfer Error Address Register */
+	u8 res6[0xC];
+	u32 lbcr;               /**< Configuration Register */
+#define LBCR_LDIS  0x80000000
+#define LBCR_LDIS_SHIFT    31
+#define LBCR_BCTLC 0x00C00000
+#define LBCR_BCTLC_SHIFT   22
+#define LBCR_LPBSE 0x00020000
+#define LBCR_LPBSE_SHIFT   17
+#define LBCR_EPAR  0x00010000
+#define LBCR_EPAR_SHIFT    16
+#define LBCR_BMT   0x0000FF00
+#define LBCR_BMT_SHIFT      8
+	u32 lcrr;               /**< Clock Ratio Register */
+#define LCRR_DBYP    0x80000000
+#define LCRR_DBYP_SHIFT      31
+#define LCRR_BUFCMDC 0x30000000
+#define LCRR_BUFCMDC_SHIFT   28
+#define LCRR_ECL     0x03000000
+#define LCRR_ECL_SHIFT       24
+#define LCRR_EADC    0x00030000
+#define LCRR_EADC_SHIFT      16
+#define LCRR_CLKDIV  0x0000000F
+#define LCRR_CLKDIV_SHIFT     0
+
+
+	u8 res7[0x28];
+	u8 res8[0xF00];
+} lbus8349_t;
+
+/*
+ * Serial Peripheral Interface
+ */
+typedef struct spi8349
+{
+	u32 mode;     /**< mode register  */
+	u32 event;    /**< event register */
+	u32 mask;     /**< mask register  */
+	u32 com;      /**< command register */
+	u8 res0[0x10];
+	u32 tx;       /**< transmit register */
+	u32 rx;       /**< receive register */
+	u8 res1[0xD8];
+} spi8349_t;
+
+typedef struct dma8349 {
+	u8 fixme[0x300];
+} dma8349_t;
+
+/*
+ * PCI Software Configuration Registers
+ */
+typedef struct pciconf8349 {
+	u32	config_address;
+#define PCI_CONFIG_ADDRESS_EN	0x80000000
+#define PCI_CONFIG_ADDRESS_BN_SHIFT	16
+#define PCI_CONFIG_ADDRESS_BN_MASK	0x00ff0000
+#define PCI_CONFIG_ADDRESS_DN_SHIFT	11
+#define PCI_CONFIG_ADDRESS_DN_MASK	0x0000f800
+#define PCI_CONFIG_ADDRESS_FN_SHIFT	8
+#define PCI_CONFIG_ADDRESS_FN_MASK	0x00000700
+#define PCI_CONFIG_ADDRESS_RN_SHIFT	0
+#define PCI_CONFIG_ADDRESS_RN_MASK	0x000000fc
+	u32 config_data;
+	u32 int_ack;
+	u8	res[116];
+} pciconf8349_t;
+
+/*
+ * PCI Outbound Translation Register
+ */
+typedef struct pci_outbound_window {
+	u32	potar;
+	u8	res0[4];
+	u32	pobar;
+	u8	res1[4];
+	u32	pocmr;
+	u8	res2[4];
+} pot8349_t;
+/*
+ * Sequencer
+ */
+typedef struct ios8349 {
+	pot8349_t	pot[6];
+#define POTAR_TA_MASK	0x000fffff
+#define	POBAR_BA_MASK	0x000fffff
+#define	POCMR_EN	0x80000000
+#define	POCMR_IO	0x40000000	/* 0--memory space 1--I/O space */
+#define	POCMR_SE	0x20000000	/* streaming enable */
+#define	POCMR_DST	0x10000000	/* 0--PCI1 1--PCI2*/
+#define	POCMR_CM_MASK	0x000fffff
+#define	POCMR_CM_4G	0x00000000
+#define	POCMR_CM_2G	0x00080000
+#define	POCMR_CM_1G	0x000C0000
+#define	POCMR_CM_512M	0x000E0000
+#define	POCMR_CM_256M	0x000F0000
+#define	POCMR_CM_128M	0x000F8000
+#define	POCMR_CM_64M	0x000FC000
+#define	POCMR_CM_32M	0x000FE000
+#define	POCMR_CM_16M	0x000FF000
+#define	POCMR_CM_8M	0x000FF800
+#define	POCMR_CM_4M	0x000FFC00
+#define	POCMR_CM_2M	0x000FFE00
+#define	POCMR_CM_1M	0x000FFF00
+#define	POCMR_CM_512K	0x000FFF80
+#define	POCMR_CM_256K	0x000FFFC0
+#define	POCMR_CM_128K	0x000FFFE0
+#define	POCMR_CM_64K	0x000FFFF0
+#define	POCMR_CM_32K	0x000FFFF8
+#define	POCMR_CM_16K	0x000FFFFC
+#define	POCMR_CM_8K	0x000FFFFE
+#define	POCMR_CM_4K	0x000FFFFF
+	u8	res0[0x60];
+	u32	pmcr;
+	u8	res1[4];
+	u32	dtcr;
+	u8	res2[4];
+} ios8349_t;
+
+/*
+ * PCI Controller Control and Status Registers
+ */
+typedef struct pcictrl8349 {
+	u32	esr;
+#define ESR_MERR	0x80000000
+#define ESR_APAR	0x00000400
+#define	ESR_PCISERR	0x00000200
+#define	ESR_MPERR	0x00000100
+#define	ESR_TPERR	0x00000080
+#define	ESR_NORSP	0x00000040
+#define	ESR_TABT	0x00000020
+	u32	ecdr;
+#define ECDR_APAR	0x00000400
+#define	ECDR_PCISERR	0x00000200
+#define	ECDR_MPERR	0x00000100
+#define	ECDR_TPERR	0x00000080
+#define	ECDR_NORSP	0x00000040
+#define	ECDR_TABT	0x00000020
+	u32 eer;
+#define EER_APAR	0x00000400
+#define	EER_PCISERR	0x00000200
+#define	EER_MPERR	0x00000100
+#define	EER_TPERR	0x00000080
+#define	EER_NORSP	0x00000040
+#define	EER_TABT	0x00000020
+	u32	eatcr;
+#define	EATCR_ERRTYPR_MASK	0x70000000
+#define	EATCR_ERRTYPR_APR	0x00000000	/* address parity error */
+#define	EATCR_ERRTYPR_WDPR	0x10000000	/* write data parity error */
+#define	EATCR_ERRTYPR_RDPR	0x20000000	/* read data parity error */
+#define	EATCR_ERRTYPR_MA	0x30000000	/* master abort */
+#define	EATCR_ERRTYPR_TA	0x40000000	/* target abort */
+#define	EATCR_ERRTYPR_SE	0x50000000	/* system error indication received */
+#define	EATCR_ERRTYPR_PEA	0x60000000	/* parity error indication received on a read */
+#define	EATCR_ERRTYPR_PEW	0x70000000	/* parity error indication received on a write */
+#define EATCR_BN_MASK		0x0f000000	/* beat number */
+#define	EATCR_BN_1st		0x00000000
+#define	EATCR_BN_2ed		0x01000000
+#define	EATCR_BN_3rd		0x02000000
+#define	EATCR_BN_4th		0x03000000
+#define	EATCR_BN_5th		0x0400000
+#define	EATCR_BN_6th		0x05000000
+#define	EATCR_BN_7th		0x06000000
+#define	EATCR_BN_8th		0x07000000
+#define	EATCR_BN_9th		0x08000000
+#define EATCR_TS_MASK		0x00300000	/* transaction size */
+#define	EATCR_TS_4		0x00000000
+#define	EATCR_TS_1		0x00100000
+#define	EATCR_TS_2		0x00200000
+#define	EATCR_TS_3		0x00300000
+#define	EATCR_ES_MASK		0x000f0000	/* error source */
+#define	EATCR_ES_EM		0x00000000	/* external master */
+#define	EATCR_ES_DMA		0x00050000
+#define	EATCR_CMD_MASK		0x0000f000
+#define	EATCR_HBE_MASK		0x00000f00	/* PCI high byte enable*/
+#define	EATCR_BE_MASK		0x000000f0	/* PCI byte enable */
+#define	EATCR_HPB		0x00000004	/* high parity bit */
+#define	EATCR_PB		0x00000002	/* parity bit*/
+#define	EATCR_VI		0x00000001	/* error information valid */
+	u32	eacr;
+	u32	eeacr;
+	u32	edlcr;
+	u32	edhcr;
+	u32	gcr;
+	u32	ecr;
+	u32	gsr;
+	u8	res0[12];
+	u32	pitar2;
+	u8	res1[4];
+	u32	pibar2;
+	u32	piebar2;
+	u32	piwar2;
+	u8	res2[4];
+	u32	pitar1;
+	u8	res3[4];
+	u32	pibar1;
+	u32	piebar1;
+	u32	piwar1;
+	u8	res4[4];
+	u32	pitar0;
+	u8	res5[4];
+	u32	pibar0;
+	u8	res6[4];
+	u32	piwar0;
+	u8	res7[132];
+#define PITAR_TA_MASK		0x000fffff
+#define PIBAR_MASK		0xffffffff
+#define PIEBAR_EBA_MASK		0x000fffff
+#define PIWAR_EN		0x80000000
+#define PIWAR_PF		0x20000000
+#define	PIWAR_RTT_MASK		0x000f0000
+#define	PIWAR_RTT_NO_SNOOP	0x00040000
+#define PIWAR_RTT_SNOOP		0x00050000
+#define	PIWAR_WTT_MASK		0x0000f000
+#define	PIWAR_WTT_NO_SNOOP	0x00004000
+#define PIWAR_WTT_SNOOP		0x00005000
+#define	PIWAR_IWS_MASK	0x0000003F
+#define	PIWAR_IWS_4K	0x0000000B
+#define	PIWAR_IWS_8K	0x0000000C
+#define	PIWAR_IWS_16K	0x0000000D
+#define	PIWAR_IWS_32K	0x0000000E
+#define	PIWAR_IWS_64K	0x0000000F
+#define	PIWAR_IWS_128K	0x00000010
+#define	PIWAR_IWS_256K	0x00000011
+#define	PIWAR_IWS_512K	0x00000012
+#define	PIWAR_IWS_1M	0x00000013
+#define	PIWAR_IWS_2M	0x00000014
+#define	PIWAR_IWS_4M	0x00000015
+#define	PIWAR_IWS_8M	0x00000016
+#define	PIWAR_IWS_16M	0x00000017
+#define	PIWAR_IWS_32M	0x00000018
+#define	PIWAR_IWS_64M	0x00000019
+#define	PIWAR_IWS_128M	0x0000001A
+#define	PIWAR_IWS_256M	0x0000001B
+#define	PIWAR_IWS_512M	0x0000001C
+#define	PIWAR_IWS_1G	0x0000001D
+#define	PIWAR_IWS_2G	0x0000001E
+} pcictrl8349_t;
+
+/*
+ * USB
+ */
+typedef struct usb8349 {
+	u8 fixme[0x2000];
+} usb8349_t;
+
+/*
+ * TSEC
+ */
+typedef struct tsec8349 {
+	u8 fixme[0x1000];
+} tsec8349_t;
+
+/*
+ * Security
+ */
+typedef struct security8349 {
+	u8 fixme[0x10000];
+} security8349_t;
+
+typedef struct immap {
+	sysconf8349_t sysconf; /* System configuration */
+	wdt8349_t     wdt;     /* Watch Dog Timer (WDT) Registers */
+	rtclk8349_t   rtc;     /* Real Time Clock Module Registers */
+	rtclk8349_t   pit;     /* Periodic Interval Timer */
+	gtm8349_t     gtm[2];  /* Global Timers Module */
+	ipic8349_t    ipic;    /* Integrated Programmable Interrupt Controller */
+	arbiter8349_t arbiter; /* System Arbiter Registers */
+	reset8349_t   reset;   /* Reset Module */
+	clk8349_t     clk;     /* System Clock Module */
+	pmc8349_t     pmc;     /* Power Management Control Module */
+	gpio8349_t    pgio[2]; /* general purpose I/O module */
+	u8 res0[0x200];
+	u8 DDL_DDR[0x100];
+	u8 DDL_LBIU[0x100];
+	u8 res1[0xE00];
+	ddr8349_t     ddr;     /* DDR Memory Controller Memory */
+	i2c_t     i2c[2];      /* I2C1 Controller */
+	u8 res2[0x1300];
+	duart8349_t   duart[2];/* DUART */
+	u8 res3[0x900];
+	lbus8349_t    lbus;    /* Local Bus Controller Registers */
+	u8 res4[0x1000];
+	spi8349_t     spi;     /* Serial Peripheral Interface */
+	u8 res5[0xF00];
+	dma8349_t     dma;     /* DMA */
+	pciconf8349_t pci_conf[2];  /* PCI Software Configuration Registers */
+	ios8349_t     ios;     /* Sequencer */
+	pcictrl8349_t pci_ctrl[2];  /* PCI Controller Control and Status Registers */
+	u8 res6[0x19900];
+	usb8349_t     usb;
+	tsec8349_t    tsec[2];
+	u8 res7[0xA000];
+	security8349_t security;
+} immap_t;
+
+#endif /* __IMMAP_8349__ */
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
new file mode 100755
index 0000000..2f10e95
--- /dev/null
+++ b/include/asm-ppc/immap_85xx.h
@@ -0,0 +1,1594 @@
+/*
+ * MPC85xx Internal Memory Map
+ *
+ * Copyright(c) 2002,2003 Motorola Inc.
+ * Xianghua Xiao (x.xiao@motorola.com)
+ *
+ */
+
+#ifndef __IMMAP_85xx__
+#define __IMMAP_85xx__
+
+/*
+ * Local-Access Registers and ECM Registers(0x0000-0x2000)
+ */
+typedef struct ccsr_local_ecm {
+	uint	ccsrbar;	/* 0x0 - Control Configuration Status Registers Base Address Register */
+	char	res1[4];
+	uint	altcbar;	/* 0x8 - Alternate Configuration Base Address Register */
+	char	res2[4];
+	uint	altcar;		/* 0x10 - Alternate Configuration Attribute Register */
+	char	res3[12];
+	uint	bptr;		/* 0x20 - Boot Page Translation Register */
+	char	res4[3044];
+	uint	lawbar0;	/* 0xc08 - Local Access Window 0 Base Address Register */
+	char	res5[4];
+	uint	lawar0;		/* 0xc10 - Local Access Window 0 Attributes Register */
+	char	res6[20];
+	uint	lawbar1;	/* 0xc28 - Local Access Window 1 Base Address Register */
+	char	res7[4];
+	uint	lawar1;		/* 0xc30 - Local Access Window 1 Attributes Register */
+	char	res8[20];
+	uint	lawbar2;	/* 0xc48 - Local Access Window 2 Base Address Register */
+	char	res9[4];
+	uint	lawar2;		/* 0xc50 - Local Access Window 2 Attributes Register */
+	char	res10[20];
+	uint	lawbar3;	/* 0xc68 - Local Access Window 3 Base Address Register */
+	char	res11[4];
+	uint	lawar3;		/* 0xc70 - Local Access Window 3 Attributes Register */
+	char	res12[20];
+	uint	lawbar4;	/* 0xc88 - Local Access Window 4 Base Address Register */
+	char	res13[4];
+	uint	lawar4;		/* 0xc90 - Local Access Window 4 Attributes Register */
+	char	res14[20];
+	uint	lawbar5;	/* 0xca8 - Local Access Window 5 Base Address Register */
+	char	res15[4];
+	uint	lawar5;		/* 0xcb0 - Local Access Window 5 Attributes Register */
+	char	res16[20];
+	uint	lawbar6;	/* 0xcc8 - Local Access Window 6 Base Address Register */
+	char	res17[4];
+	uint	lawar6;		/* 0xcd0 - Local Access Window 6 Attributes Register */
+	char	res18[20];
+	uint	lawbar7;	/* 0xce8 - Local Access Window 7 Base Address Register */
+	char	res19[4];
+	uint	lawar7;		/* 0xcf0 - Local Access Window 7 Attributes Register */
+	char	res20[780];
+	uint	eebacr;		/* 0x1000 - ECM CCB Address Configuration Register */
+	char	res21[12];
+	uint	eebpcr;		/* 0x1010 - ECM CCB Port Configuration Register */
+	char	res22[3564];
+	uint	eedr;		/* 0x1e00 - ECM Error Detect Register */
+	char	res23[4];
+	uint	eeer;		/* 0x1e08 - ECM Error Enable Register */
+	uint	eeatr;		/* 0x1e0c - ECM Error Attributes Capture Register */
+	uint	eeadr;		/* 0x1e10 - ECM Error Address Capture Register */
+	char	res24[492];
+} ccsr_local_ecm_t;
+
+/*
+ * DDR memory controller registers(0x2000-0x3000)
+ */
+typedef struct ccsr_ddr {
+	uint	cs0_bnds;		/* 0x2000 - DDR Chip Select 0 Memory Bounds */
+	char	res1[4];
+	uint	cs1_bnds;		/* 0x2008 - DDR Chip Select 1 Memory Bounds */
+	char	res2[4];
+	uint	cs2_bnds;		/* 0x2010 - DDR Chip Select 2 Memory Bounds */
+	char	res3[4];
+	uint	cs3_bnds;		/* 0x2018 - DDR Chip Select 3 Memory Bounds */
+	char	res4[100];
+	uint	cs0_config;		/* 0x2080 - DDR Chip Select Configuration */
+	uint	cs1_config;		/* 0x2084 - DDR Chip Select Configuration */
+	uint	cs2_config;		/* 0x2088 - DDR Chip Select Configuration */
+	uint	cs3_config;		/* 0x208c - DDR Chip Select Configuration */
+	char	res5[112];
+	uint	ext_refrec;		/* 0x2100 - DDR SDRAM Extended Refresh Recovery */
+	uint	timing_cfg_0;		/* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
+	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
+	uint	timing_cfg_2;		/* 0x210c - DDR SDRAM Timing Configuration Register 2 */
+	uint	sdram_cfg;		/* 0x2110 - DDR SDRAM Control Configuration */
+	uint	sdram_cfg_2;		/* 0x2114 - DDR SDRAM Control Configuration 2 */
+	uint	sdram_mode;		/* 0x2118 - DDR SDRAM Mode Configuration */
+	uint	sdram_mode_2;		/* 0x211c - DDR SDRAM Mode Configuration 2*/
+	uint	sdram_md_cntl;		/* 0x2120 - DDR SDRAM Mode Control */
+	uint	sdram_interval;		/* 0x2124 - DDR SDRAM Interval Configuration */
+	uint	sdram_data_init;	/* 0x2128 - DDR SDRAM Data initialization */
+	char	res6[4];
+	uint	sdram_clk_cntl;		/* 0x2130 - DDR SDRAM Clock Control */
+	char	res7[20];
+	uint	init_address;		/* 0x2148 - DDR training initialization address */
+	uint	init_ext_address;	/* 0x214C - DDR training initialization extended address */
+	char	res8_1[2728];
+	uint	ip_rev1;		/* 0x2BF8 - DDR IP Block Revision 1 */
+	uint	ip_rev2;		/* 0x2BFC - DDR IP Block Revision 2 */
+	char	res8_2[512];
+	uint	data_err_inject_hi;	/* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
+	uint	data_err_inject_lo;	/* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
+	uint	ecc_err_inject;		/* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
+	char	res9[20];
+	uint	capture_data_hi;	/* 0x2e20 - DDR Memory Data Path Read Capture High */
+	uint	capture_data_lo;	/* 0x2e24 - DDR Memory Data Path Read Capture Low */
+	uint	capture_ecc;		/* 0x2e28 - DDR Memory Data Path Read Capture ECC */
+	char	res10[20];
+	uint	err_detect;		/* 0x2e40 - DDR Memory Error Detect */
+	uint	err_disable;		/* 0x2e44 - DDR Memory Error Disable */
+	uint	err_int_en;		/* 0x2e48 - DDR  */
+	uint	capture_attributes;	/* 0x2e4c - DDR Memory Error Attributes Capture */
+	uint	capture_address;	/* 0x2e50 - DDR Memory Error Address Capture */
+	uint	capture_ext_address;	/* 0x2e54 - DDR Memory Error Extended Address Capture */
+	uint	err_sbe;		/* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
+	char	res11[164];
+	uint	debug_1;		/* 0x2f00 */
+	uint	debug_2;
+	uint	debug_3;
+	uint	debug_4;
+	char	res12[240];
+} ccsr_ddr_t;
+
+/*
+ * I2C Registers(0x3000-0x4000)
+ */
+typedef struct ccsr_i2c {
+	u_char	i2cadr;		/* 0x3000 - I2C Address Register */
+#define MPC85xx_I2CADR_MASK	0xFE
+	char	res1[3];
+	u_char	i2cfdr;		/* 0x3004 - I2C Frequency Divider Register */
+#define MPC85xx_I2CFDR_MASK	0x3F
+	char	res2[3];
+	u_char	i2ccr;		/* 0x3008 - I2C Control Register */
+#define MPC85xx_I2CCR_MEN	0x80
+#define MPC85xx_I2CCR_MIEN	0x40
+#define MPC85xx_I2CCR_MSTA      0x20
+#define MPC85xx_I2CCR_MTX       0x10
+#define MPC85xx_I2CCR_TXAK      0x08
+#define MPC85xx_I2CCR_RSTA      0x04
+#define MPC85xx_I2CCR_BCST      0x01
+	char	res3[3];
+	u_char	i2csr;		/* 0x300c - I2C Status Register */
+#define MPC85xx_I2CSR_MCF	0x80
+#define MPC85xx_I2CSR_MAAS      0x40
+#define MPC85xx_I2CSR_MBB       0x20
+#define MPC85xx_I2CSR_MAL       0x10
+#define MPC85xx_I2CSR_BCSTM     0x08
+#define MPC85xx_I2CSR_SRW       0x04
+#define MPC85xx_I2CSR_MIF       0x02
+#define MPC85xx_I2CSR_RXAK      0x01
+	char	res4[3];
+	u_char	i2cdr;		/* 0x3010 - I2C Data Register */
+#define MPC85xx_I2CDR_DATA	0xFF
+	char	res5[3];
+	u_char	i2cdfsrr;	/* 0x3014 - I2C Digital Filtering Sampling Rate Register */
+#define MPC85xx_I2CDFSRR	0x3F
+	char	res6[4075];
+} ccsr_i2c_t;
+
+#if defined(CONFIG_MPC8540) \
+	|| defined(CONFIG_MPC8541) \
+	|| defined(CONFIG_MPC8548) \
+	|| defined(CONFIG_MPC8555)
+/* DUART Registers(0x4000-0x5000) */
+typedef struct ccsr_duart {
+	char	res1[1280];
+	u_char	urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
+	u_char	uier1_udmb1;	/* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
+	u_char	uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
+	u_char	ulcr1;		/* 0x4503 - UART1 Line Control Register */
+	u_char	umcr1;		/* 0x4504 - UART1 Modem Control Register */
+	u_char	ulsr1;		/* 0x4505 - UART1 Line Status Register */
+	u_char	umsr1;		/* 0x4506 - UART1 Modem Status Register */
+	u_char	uscr1;		/* 0x4507 - UART1 Scratch Register */
+	char	res2[8];
+	u_char	udsr1;		/* 0x4510 - UART1 DMA Status Register */
+	char	res3[239];
+	u_char	urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
+	u_char	uier2_udmb2;	/* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
+	u_char	uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
+	u_char	ulcr2;		/* 0x4603 - UART2 Line Control Register */
+	u_char	umcr2;		/* 0x4604 - UART2 Modem Control Register */
+	u_char	ulsr2;		/* 0x4605 - UART2 Line Status Register */
+	u_char	umsr2;		/* 0x4606 - UART2 Modem Status Register */
+	u_char	uscr2;		/* 0x4607 - UART2 Scratch Register */
+	char	res4[8];
+	u_char	udsr2;		/* 0x4610 - UART2 DMA Status Register */
+	char	res5[2543];
+} ccsr_duart_t;
+#else /* MPC8560 uses UART on its CPM */
+typedef struct ccsr_duart {
+	char res[4096];
+} ccsr_duart_t;
+#endif
+
+/* Local Bus Controller Registers(0x5000-0x6000) */
+/* Omitting OCeaN(0x6000) and Reserved(0x7000) block */
+
+typedef struct ccsr_lbc {
+	uint	br0;		/* 0x5000 - LBC Base Register 0 */
+	uint	or0;		/* 0x5004 - LBC Options Register 0 */
+	uint	br1;		/* 0x5008 - LBC Base Register 1 */
+	uint	or1;		/* 0x500c - LBC Options Register 1 */
+	uint	br2;		/* 0x5010 - LBC Base Register 2 */
+	uint	or2;		/* 0x5014 - LBC Options Register 2 */
+	uint	br3;		/* 0x5018 - LBC Base Register 3 */
+	uint	or3;		/* 0x501c - LBC Options Register 3 */
+	uint	br4;		/* 0x5020 - LBC Base Register 4 */
+	uint	or4;		/* 0x5024 - LBC Options Register 4 */
+	uint	br5;		/* 0x5028 - LBC Base Register 5 */
+	uint	or5;		/* 0x502c - LBC Options Register 5 */
+	uint	br6;		/* 0x5030 - LBC Base Register 6 */
+	uint	or6;		/* 0x5034 - LBC Options Register 6 */
+	uint	br7;		/* 0x5038 - LBC Base Register 7 */
+	uint	or7;		/* 0x503c - LBC Options Register 7 */
+	char	res1[40];
+	uint	mar;		/* 0x5068 - LBC UPM Address Register */
+	char	res2[4];
+	uint	mamr;		/* 0x5070 - LBC UPMA Mode Register */
+	uint	mbmr;		/* 0x5074 - LBC UPMB Mode Register */
+	uint	mcmr;		/* 0x5078 - LBC UPMC Mode Register */
+	char	res3[8];
+	uint	mrtpr;		/* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
+	uint	mdr;		/* 0x5088 - LBC UPM Data Register */
+	char	res4[8];
+	uint	lsdmr;		/* 0x5094 - LBC SDRAM Mode Register */
+	char	res5[8];
+	uint	lurt;		/* 0x50a0 - LBC UPM Refresh Timer */
+	uint	lsrt;		/* 0x50a4 - LBC SDRAM Refresh Timer */
+	char	res6[8];
+	uint	ltesr;		/* 0x50b0 - LBC Transfer Error Status Register */
+	uint	ltedr;		/* 0x50b4 - LBC Transfer Error Disable Register */
+	uint	lteir;		/* 0x50b8 - LBC Transfer Error Interrupt Register */
+	uint	lteatr;		/* 0x50bc - LBC Transfer Error Attributes Register */
+	uint	ltear;		/* 0x50c0 - LBC Transfer Error Address Register */
+	char	res7[12];
+	uint	lbcr;		/* 0x50d0 - LBC Configuration Register */
+	uint	lcrr;		/* 0x50d4 - LBC Clock Ratio Register */
+	char	res8[12072];
+} ccsr_lbc_t;
+
+/*
+ * PCI Registers(0x8000-0x9000)
+ * Omitting Reserved(0x9000-0x2_0000)
+ */
+typedef struct ccsr_pcix {
+	uint	cfg_addr;	/* 0x8000 - PCIX Configuration Address Register */
+	uint	cfg_data;	/* 0x8004 - PCIX Configuration Data Register */
+	uint	int_ack;	/* 0x8008 - PCIX Interrupt Acknowledge Register */
+	char	res1[3060];
+	uint	potar0;		/* 0x8c00 - PCIX Outbound Transaction Address Register 0 */
+	uint	potear0;	/* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */
+	uint	powbar0;	/* 0x8c08 - PCIX Outbound Window Base Address Register 0 */
+	uint	powbear0;	/* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */
+	uint	powar0;		/* 0x8c10 - PCIX Outbound Window Attributes Register 0 */
+	char	res2[12];
+	uint	potar1;		/* 0x8c20 - PCIX Outbound Transaction Address Register 1 */
+	uint	potear1;	/* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */
+	uint	powbar1;	/* 0x8c28 - PCIX Outbound Window Base Address Register 1 */
+	uint	powbear1;	/* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */
+	uint	powar1;		/* 0x8c30 - PCIX Outbound Window Attributes Register 1 */
+	char	res3[12];
+	uint	potar2;		/* 0x8c40 - PCIX Outbound Transaction Address Register 2 */
+	uint	potear2;	/* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */
+	uint	powbar2;	/* 0x8c48 - PCIX Outbound Window Base Address Register 2 */
+	uint	powbear2;	/* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */
+	uint	powar2;		/* 0x8c50 - PCIX Outbound Window Attributes Register 2 */
+	char	res4[12];
+	uint	potar3;		/* 0x8c60 - PCIX Outbound Transaction Address Register 3 */
+	uint	potear3;	/* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */
+	uint	powbar3;	/* 0x8c68 - PCIX Outbound Window Base Address Register 3 */
+	uint	powbear3;	/* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */
+	uint	powar3;		/* 0x8c70 - PCIX Outbound Window Attributes Register 3 */
+	char	res5[12];
+	uint	potar4;		/* 0x8c80 - PCIX Outbound Transaction Address Register 4 */
+	uint	potear4;	/* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */
+	uint	powbar4;	/* 0x8c88 - PCIX Outbound Window Base Address Register 4 */
+	uint	powbear4;	/* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */
+	uint	powar4;		/* 0x8c90 - PCIX Outbound Window Attributes Register 4 */
+	char	res6[268];
+	uint	pitar3;		/* 0x8da0 - PCIX Inbound Translation Address Register 3  */
+	uint	pitear3;	/* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */
+	uint	piwbar3;	/* 0x8da8 - PCIX Inbound Window Base Address Register 3 */
+	uint	piwbear3;	/* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */
+	uint	piwar3;		/* 0x8db0 - PCIX Inbound Window Attributes Register 3 */
+	char	res7[12];
+	uint	pitar2;		/* 0x8dc0 - PCIX Inbound Translation Address Register 2  */
+	uint	pitear2;	/* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */
+	uint	piwbar2;	/* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */
+	uint	piwbear2;	/* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */
+	uint	piwar2;		/* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */
+	char	res8[12];
+	uint	pitar1;		/* 0x8de0 - PCIX Inbound Translation Address Register 1  */
+	uint	pitear1;	/* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */
+	uint	piwbar1;	/* 0x8de8 - PCIX Inbound Window Base Address Register 1 */
+	char	res9[4];
+	uint	piwar1;		/* 0x8df0 - PCIX Inbound Window Attributes Register 1 */
+	char	res10[12];
+	uint	pedr;		/* 0x8e00 - PCIX Error Detect Register */
+	uint	pecdr;		/* 0x8e04 - PCIX Error Capture Disable Register */
+	uint	peer;		/* 0x8e08 - PCIX Error Enable Register */
+	uint	peattrcr;	/* 0x8e0c - PCIX Error Attributes Capture Register */
+	uint	peaddrcr;	/* 0x8e10 - PCIX Error Address Capture Register */
+	uint	peextaddrcr;	/* 0x8e14 - PCIX  Error Extended Address Capture Register */
+	uint	pedlcr;		/* 0x8e18 - PCIX Error Data Low Capture Register */
+	uint	pedhcr;		/* 0x8e1c - PCIX Error Error Data High Capture Register */
+	char	res11[94688];
+} ccsr_pcix_t;
+
+/*
+ * L2 Cache Registers(0x2_0000-0x2_1000)
+ */
+typedef struct ccsr_l2cache {
+	uint	l2ctl;		/* 0x20000 - L2 configuration register 0 */
+	char	res1[12];
+	uint	l2cewar0;	/* 0x20010 - L2 cache external write address register 0 */
+	char	res2[4];
+	uint	l2cewcr0;	/* 0x20018 - L2 cache external write control register 0 */
+	char	res3[4];
+	uint	l2cewar1;	/* 0x20020 - L2 cache external write address register 1 */
+	char	res4[4];
+	uint	l2cewcr1;	/* 0x20028 - L2 cache external write control register 1 */
+	char	res5[4];
+	uint	l2cewar2;	/* 0x20030 - L2 cache external write address register 2 */
+	char	res6[4];
+	uint	l2cewcr2;	/* 0x20038 - L2 cache external write control register 2 */
+	char	res7[4];
+	uint	l2cewar3;	/* 0x20040 - L2 cache external write address register 3 */
+	char	res8[4];
+	uint	l2cewcr3;	/* 0x20048 - L2 cache external write control register 3 */
+	char	res9[180];
+	uint	l2srbar0;	/* 0x20100 - L2 memory-mapped SRAM base address register 0 */
+	char	res10[4];
+	uint	l2srbar1;	/* 0x20108 - L2 memory-mapped SRAM base address register 1 */
+	char	res11[3316];
+	uint	l2errinjhi;	/* 0x20e00 - L2 error injection mask high register */
+	uint	l2errinjlo;	/* 0x20e04 - L2 error injection mask low register */
+	uint	l2errinjctl;	/* 0x20e08 - L2 error injection tag/ECC control register */
+	char	res12[20];
+	uint	l2captdatahi;	/* 0x20e20 - L2 error data high capture register */
+	uint	l2captdatalo;	/* 0x20e24 - L2 error data low capture register */
+	uint	l2captecc;	/* 0x20e28 - L2 error ECC capture register */
+	char	res13[20];
+	uint	l2errdet;	/* 0x20e40 - L2 error detect register */
+	uint	l2errdis;	/* 0x20e44 - L2 error disable register */
+	uint	l2errinten;	/* 0x20e48 - L2 error interrupt enable register */
+	uint	l2errattr;	/* 0x20e4c - L2 error attributes capture register */
+	uint	l2erraddr;	/* 0x20e50 - L2 error address capture register */
+	char	res14[4];
+	uint	l2errctl;	/* 0x20e58 - L2 error control register */
+	char	res15[420];
+} ccsr_l2cache_t;
+
+/*
+ * DMA Registers(0x2_1000-0x2_2000)
+ */
+typedef struct ccsr_dma {
+	char	res1[256];
+	uint	mr0;		/* 0x21100 - DMA 0 Mode Register */
+	uint	sr0;		/* 0x21104 - DMA 0 Status Register */
+	char	res2[4];
+	uint	clndar0;	/* 0x2110c - DMA 0 Current Link Descriptor Address Register */
+	uint	satr0;		/* 0x21110 - DMA 0 Source Attributes Register */
+	uint	sar0;		/* 0x21114 - DMA 0 Source Address Register */
+	uint	datr0;		/* 0x21118 - DMA 0 Destination Attributes Register */
+	uint	dar0;		/* 0x2111c - DMA 0 Destination Address Register */
+	uint	bcr0;		/* 0x21120 - DMA 0 Byte Count Register */
+	char	res3[4];
+	uint	nlndar0;	/* 0x21128 - DMA 0 Next Link Descriptor Address Register */
+	char	res4[8];
+	uint	clabdar0;	/* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
+	char	res5[4];
+	uint	nlsdar0;	/* 0x2113c - DMA 0 Next List Descriptor Address Register */
+	uint	ssr0;		/* 0x21140 - DMA 0 Source Stride Register */
+	uint	dsr0;		/* 0x21144 - DMA 0 Destination Stride Register */
+	char	res6[56];
+	uint	mr1;		/* 0x21180 - DMA 1 Mode Register */
+	uint	sr1;		/* 0x21184 - DMA 1 Status Register */
+	char	res7[4];
+	uint	clndar1;	/* 0x2118c - DMA 1 Current Link Descriptor Address Register */
+	uint	satr1;		/* 0x21190 - DMA 1 Source Attributes Register */
+	uint	sar1;		/* 0x21194 - DMA 1 Source Address Register */
+	uint	datr1;		/* 0x21198 - DMA 1 Destination Attributes Register */
+	uint	dar1;		/* 0x2119c - DMA 1 Destination Address Register */
+	uint	bcr1;		/* 0x211a0 - DMA 1 Byte Count Register */
+	char	res8[4];
+	uint	nlndar1;	/* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
+	char	res9[8];
+	uint	clabdar1;	/* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
+	char	res10[4];
+	uint	nlsdar1;	/* 0x211bc - DMA 1 Next List Descriptor Address Register */
+	uint	ssr1;		/* 0x211c0 - DMA 1 Source Stride Register */
+	uint	dsr1;		/* 0x211c4 - DMA 1 Destination Stride Register */
+	char	res11[56];
+	uint	mr2;		/* 0x21200 - DMA 2 Mode Register */
+	uint	sr2;		/* 0x21204 - DMA 2 Status Register */
+	char	res12[4];
+	uint	clndar2;	/* 0x2120c - DMA 2 Current Link Descriptor Address Register */
+	uint	satr2;		/* 0x21210 - DMA 2 Source Attributes Register */
+	uint	sar2;		/* 0x21214 - DMA 2 Source Address Register */
+	uint	datr2;		/* 0x21218 - DMA 2 Destination Attributes Register */
+	uint	dar2;		/* 0x2121c - DMA 2 Destination Address Register */
+	uint	bcr2;		/* 0x21220 - DMA 2 Byte Count Register */
+	char	res13[4];
+	uint	nlndar2;	/* 0x21228 - DMA 2 Next Link Descriptor Address Register */
+	char	res14[8];
+	uint	clabdar2;	/* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
+	char	res15[4];
+	uint	nlsdar2;	/* 0x2123c - DMA 2 Next List Descriptor Address Register */
+	uint	ssr2;		/* 0x21240 - DMA 2 Source Stride Register */
+	uint	dsr2;		/* 0x21244 - DMA 2 Destination Stride Register */
+	char	res16[56];
+	uint	mr3;		/* 0x21280 - DMA 3 Mode Register */
+	uint	sr3;		/* 0x21284 - DMA 3 Status Register */
+	char	res17[4];
+	uint	clndar3;	/* 0x2128c - DMA 3 Current Link Descriptor Address Register */
+	uint	satr3;		/* 0x21290 - DMA 3 Source Attributes Register */
+	uint	sar3;		/* 0x21294 - DMA 3 Source Address Register */
+	uint	datr3;		/* 0x21298 - DMA 3 Destination Attributes Register */
+	uint	dar3;		/* 0x2129c - DMA 3 Destination Address Register */
+	uint	bcr3;		/* 0x212a0 - DMA 3 Byte Count Register */
+	char	res18[4];
+	uint	nlndar3;	/* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
+	char	res19[8];
+	uint	clabdar3;	/* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
+	char	res20[4];
+	uint	nlsdar3;	/* 0x212bc - DMA 3 Next List Descriptor Address Register */
+	uint	ssr3;		/* 0x212c0 - DMA 3 Source Stride Register */
+	uint	dsr3;		/* 0x212c4 - DMA 3 Destination Stride Register */
+	char	res21[56];
+	uint	dgsr;		/* 0x21300 - DMA General Status Register */
+	char	res22[11516];
+} ccsr_dma_t;
+
+/*
+ * tsec1 tsec2: 24000-26000
+ */
+typedef struct ccsr_tsec {
+	char	res1[16];
+	uint	ievent;		/* 0x24010 - Interrupt Event Register */
+	uint	imask;		/* 0x24014 - Interrupt Mask Register */
+	uint	edis;		/* 0x24018 - Error Disabled Register */
+	char	res2[4];
+	uint	ecntrl;		/* 0x24020 - Ethernet Control Register */
+	uint	minflr;		/* 0x24024 - Minimum Frame Length Register */
+	uint	ptv;		/* 0x24028 - Pause Time Value Register */
+	uint	dmactrl;	/* 0x2402c - DMA Control Register */
+	uint	tbipa;		/* 0x24030 - TBI PHY Address Register */
+	char	res3[88];
+	uint	fifo_tx_thr;		/* 0x2408c - FIFO transmit threshold register */
+	char	res4[8];
+	uint	fifo_tx_starve;		/* 0x24098 - FIFO transmit starve register */
+	uint	fifo_tx_starve_shutoff;		/* 0x2409c - FIFO transmit starve shutoff register */
+	char	res5[96];
+	uint	tctrl;		/* 0x24100 - Transmit Control Register */
+	uint	tstat;		/* 0x24104 - Transmit Status Register */
+	char	res6[4];
+	uint	tbdlen;		/* 0x2410c - Transmit Buffer Descriptor Data Length Register */
+	char	res7[16];
+	uint	ctbptrh;	/* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */
+	uint	ctbptr;		/* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */
+	char	res8[88];
+	uint	tbptrh;		/* 0x24180 - Transmit Buffer Descriptor Pointer High Register */
+	uint	tbptr;		/* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */
+	char	res9[120];
+	uint	tbaseh;		/* 0x24200 - Transmit Descriptor Base Address High Register */
+	uint	tbase;		/* 0x24204 - Transmit Descriptor Base Address Register */
+	char	res10[168];
+	uint	ostbd;		/* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
+	uint	ostbdp;		/* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
+	uint	os32tbdp;	/* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */
+	uint	os32iptrh;	/* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */
+	uint	os32iptrl;	/* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */
+	uint	os32tbdr;	/* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */
+	uint	os32iil;	/* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */
+	char	res11[52];
+	uint	rctrl;		/* 0x24300 - Receive Control Register */
+	uint	rstat;		/* 0x24304 - Receive Status Register */
+	char	res12[4];
+	uint	rbdlen;		/* 0x2430c - RxBD Data Length Register */
+	char	res13[16];
+	uint	crbptrh;	/* 0x24320 - Current Receive Buffer Descriptor Pointer High */
+	uint	crbptr;		/* 0x24324 - Current Receive Buffer Descriptor Pointer */
+	char	res14[24];
+	uint	mrblr;		/* 0x24340 - Maximum Receive Buffer Length Register */
+	uint	mrblr2r3;	/* 0x24344 - Maximum Receive Buffer Length R2R3 Register */
+	char	res15[56];
+	uint	rbptrh;		/* 0x24380 - Receive Buffer Descriptor Pointer High 0 */
+	uint	rbptr;		/* 0x24384 - Receive Buffer Descriptor Pointer */
+	uint	rbptrh1;	/* 0x24388 - Receive Buffer Descriptor Pointer High 1 */
+	uint	rbptrl1;	/* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */
+	uint	rbptrh2;	/* 0x24390 - Receive Buffer Descriptor Pointer High 2 */
+	uint	rbptrl2;	/* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */
+	uint	rbptrh3;	/* 0x24398 - Receive Buffer Descriptor Pointer High 3 */
+	uint	rbptrl3;	/* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */
+	char	res16[96];
+	uint	rbaseh;		/* 0x24400 - Receive Descriptor Base Address High 0 */
+	uint	rbase;		/* 0x24404 - Receive Descriptor Base Address */
+	uint	rbaseh1;	/* 0x24408 - Receive Descriptor Base Address High 1 */
+	uint	rbasel1;	/* 0x2440c - Receive Descriptor Base Address Low 1 */
+	uint	rbaseh2;	/* 0x24410 - Receive Descriptor Base Address High 2 */
+	uint	rbasel2;	/* 0x24414 - Receive Descriptor Base Address Low 2 */
+	uint	rbaseh3;	/* 0x24418 - Receive Descriptor Base Address High 3 */
+	uint	rbasel3;	/* 0x2441c - Receive Descriptor Base Address Low 3 */
+	char	res17[224];
+	uint	maccfg1;	/* 0x24500 - MAC Configuration 1 Register */
+	uint	maccfg2;	/* 0x24504 - MAC Configuration 2 Register */
+	uint	ipgifg;		/* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
+	uint	hafdup;		/* 0x2450c - Half Duplex Register */
+	uint	maxfrm;		/* 0x24510 - Maximum Frame Length Register */
+	char	res18[12];
+	uint	miimcfg;	/* 0x24520 - MII Management Configuration Register */
+	uint	miimcom;	/* 0x24524 - MII Management Command Register */
+	uint	miimadd;	/* 0x24528 - MII Management Address Register */
+	uint	miimcon;	/* 0x2452c - MII Management Control Register */
+	uint	miimstat;	/* 0x24530 - MII Management Status Register */
+	uint	miimind;	/* 0x24534 - MII Management Indicator Register */
+	char	res19[4];
+	uint	ifstat;		/* 0x2453c - Interface Status Register */
+	uint	macstnaddr1;	/* 0x24540 - Station Address Part 1 Register */
+	uint	macstnaddr2;	/* 0x24544 - Station Address Part 2 Register */
+	char	res20[312];
+	uint	tr64;		/* 0x24680 - Transmit and Receive 64-byte Frame Counter */
+	uint	tr127;		/* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
+	uint	tr255;		/* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
+	uint	tr511;		/* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
+	uint	tr1k;		/* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
+	uint	trmax;		/* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
+	uint	trmgv;		/* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
+	uint	rbyt;		/* 0x2469c - Receive Byte Counter */
+	uint	rpkt;		/* 0x246a0 - Receive Packet Counter */
+	uint	rfcs;		/* 0x246a4 - Receive FCS Error Counter */
+	uint	rmca;		/* 0x246a8 - Receive Multicast Packet Counter */
+	uint	rbca;		/* 0x246ac - Receive Broadcast Packet Counter */
+	uint	rxcf;		/* 0x246b0 - Receive Control Frame Packet Counter */
+	uint	rxpf;		/* 0x246b4 - Receive Pause Frame Packet Counter */
+	uint	rxuo;		/* 0x246b8 - Receive Unknown OP Code Counter */
+	uint	raln;		/* 0x246bc - Receive Alignment Error Counter */
+	uint	rflr;		/* 0x246c0 - Receive Frame Length Error Counter */
+	uint	rcde;		/* 0x246c4 - Receive Code Error Counter */
+	uint	rcse;		/* 0x246c8 - Receive Carrier Sense Error Counter */
+	uint	rund;		/* 0x246cc - Receive Undersize Packet Counter */
+	uint	rovr;		/* 0x246d0 - Receive Oversize Packet Counter */
+	uint	rfrg;		/* 0x246d4 - Receive Fragments Counter */
+	uint	rjbr;		/* 0x246d8 - Receive Jabber Counter */
+	uint	rdrp;		/* 0x246dc - Receive Drop Counter */
+	uint	tbyt;		/* 0x246e0 - Transmit Byte Counter Counter */
+	uint	tpkt;		/* 0x246e4 - Transmit Packet Counter */
+	uint	tmca;		/* 0x246e8 - Transmit Multicast Packet Counter */
+	uint	tbca;		/* 0x246ec - Transmit Broadcast Packet Counter */
+	uint	txpf;		/* 0x246f0 - Transmit Pause Control Frame Counter */
+	uint	tdfr;		/* 0x246f4 - Transmit Deferral Packet Counter */
+	uint	tedf;		/* 0x246f8 - Transmit Excessive Deferral Packet Counter */
+	uint	tscl;		/* 0x246fc - Transmit Single Collision Packet Counter */
+	uint	tmcl;		/* 0x24700 - Transmit Multiple Collision Packet Counter */
+	uint	tlcl;		/* 0x24704 - Transmit Late Collision Packet Counter */
+	uint	txcl;		/* 0x24708 - Transmit Excessive Collision Packet Counter */
+	uint	tncl;		/* 0x2470c - Transmit Total Collision Counter */
+	char	res21[4];
+	uint	tdrp;		/* 0x24714 - Transmit Drop Frame Counter */
+	uint	tjbr;		/* 0x24718 - Transmit Jabber Frame Counter */
+	uint	tfcs;		/* 0x2471c - Transmit FCS Error Counter */
+	uint	txcf;		/* 0x24720 - Transmit Control Frame Counter */
+	uint	tovr;		/* 0x24724 - Transmit Oversize Frame Counter */
+	uint	tund;		/* 0x24728 - Transmit Undersize Frame Counter */
+	uint	tfrg;		/* 0x2472c - Transmit Fragments Frame Counter */
+	uint	car1;		/* 0x24730 - Carry Register One */
+	uint	car2;		/* 0x24734 - Carry Register Two */
+	uint	cam1;		/* 0x24738 - Carry Mask Register One */
+	uint	cam2;		/* 0x2473c - Carry Mask Register Two */
+	char	res22[192];
+	uint	iaddr0;		/* 0x24800 - Indivdual address register 0 */
+	uint	iaddr1;		/* 0x24804 - Indivdual address register 1 */
+	uint	iaddr2;		/* 0x24808 - Indivdual address register 2 */
+	uint	iaddr3;		/* 0x2480c - Indivdual address register 3 */
+	uint	iaddr4;		/* 0x24810 - Indivdual address register 4 */
+	uint	iaddr5;		/* 0x24814 - Indivdual address register 5 */
+	uint	iaddr6;		/* 0x24818 - Indivdual address register 6 */
+	uint	iaddr7;		/* 0x2481c - Indivdual address register 7 */
+	char	res23[96];
+	uint	gaddr0;		/* 0x24880 - Global address register 0 */
+	uint	gaddr1;		/* 0x24884 - Global address register 1 */
+	uint	gaddr2;		/* 0x24888 - Global address register 2 */
+	uint	gaddr3;		/* 0x2488c - Global address register 3 */
+	uint	gaddr4;		/* 0x24890 - Global address register 4 */
+	uint	gaddr5;		/* 0x24894 - Global address register 5 */
+	uint	gaddr6;		/* 0x24898 - Global address register 6 */
+	uint	gaddr7;		/* 0x2489c - Global address register 7 */
+	char	res24[96];
+	uint	pmd0;		/* 0x24900 - Pattern Match Data Register */
+	char	res25[4];
+	uint	pmask0;		/* 0x24908 - Pattern Mask Register */
+	char	res26[4];
+	uint	pcntrl0;	/* 0x24910 - Pattern Match Control Register */
+	char	res27[4];
+	uint	pattrb0;	/* 0x24918 - Pattern Match Attributes Register */
+	uint	pattrbeli0;	/* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd1;		/* 0x24920 - Pattern Match Data Register */
+	char	res28[4];
+	uint	pmask1;		/* 0x24928 - Pattern Mask Register */
+	char	res29[4];
+	uint	pcntrl1;	/* 0x24930 - Pattern Match Control Register */
+	char	res30[4];
+	uint	pattrb1;	/* 0x24938 - Pattern Match Attributes Register */
+	uint	pattrbeli1;	/* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd2;		/* 0x24940 - Pattern Match Data Register */
+	char	res31[4];
+	uint	pmask2;		/* 0x24948 - Pattern Mask Register */
+	char	res32[4];
+	uint	pcntrl2;	/* 0x24950 - Pattern Match Control Register */
+	char	res33[4];
+	uint	pattrb2;	/* 0x24958 - Pattern Match Attributes Register */
+	uint	pattrbeli2;	/* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd3;		/* 0x24960 - Pattern Match Data Register */
+	char	res34[4];
+	uint	pmask3;		/* 0x24968 - Pattern Mask Register */
+	char	res35[4];
+	uint	pcntrl3;	/* 0x24970 - Pattern Match Control Register */
+	char	res36[4];
+	uint	pattrb3;	/* 0x24978 - Pattern Match Attributes Register */
+	uint	pattrbeli3;	/* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd4;		/* 0x24980 - Pattern Match Data Register */
+	char	res37[4];
+	uint	pmask4;		/* 0x24988 - Pattern Mask Register */
+	char	res38[4];
+	uint	pcntrl4;	/* 0x24990 - Pattern Match Control Register */
+	char	res39[4];
+	uint	pattrb4;	/* 0x24998 - Pattern Match Attributes Register */
+	uint	pattrbeli4;	/* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd5;		/* 0x249a0 - Pattern Match Data Register */
+	char	res40[4];
+	uint	pmask5;		/* 0x249a8 - Pattern Mask Register */
+	char	res41[4];
+	uint	pcntrl5;	/* 0x249b0 - Pattern Match Control Register */
+	char	res42[4];
+	uint	pattrb5;	/* 0x249b8 - Pattern Match Attributes Register */
+	uint	pattrbeli5;	/* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd6;		/* 0x249c0 - Pattern Match Data Register */
+	char	res43[4];
+	uint	pmask6;		/* 0x249c8 - Pattern Mask Register */
+	char	res44[4];
+	uint	pcntrl6;	/* 0x249d0 - Pattern Match Control Register */
+	char	res45[4];
+	uint	pattrb6;	/* 0x249d8 - Pattern Match Attributes Register */
+	uint	pattrbeli6;	/* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd7;		/* 0x249e0 - Pattern Match Data Register */
+	char	res46[4];
+	uint	pmask7;		/* 0x249e8 - Pattern Mask Register */
+	char	res47[4];
+	uint	pcntrl7;	/* 0x249f0 - Pattern Match Control Register */
+	char	res48[4];
+	uint	pattrb7;	/* 0x249f8 - Pattern Match Attributes Register */
+	uint	pattrbeli7;	/* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd8;		/* 0x24a00 - Pattern Match Data Register */
+	char	res49[4];
+	uint	pmask8;		/* 0x24a08 - Pattern Mask Register */
+	char	res50[4];
+	uint	pcntrl8;	/* 0x24a10 - Pattern Match Control Register */
+	char	res51[4];
+	uint	pattrb8;	/* 0x24a18 - Pattern Match Attributes Register */
+	uint	pattrbeli8;	/* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd9;		/* 0x24a20 - Pattern Match Data Register */
+	char	res52[4];
+	uint	pmask9;		/* 0x24a28 - Pattern Mask Register */
+	char	res53[4];
+	uint	pcntrl9;	/* 0x24a30 - Pattern Match Control Register */
+	char	res54[4];
+	uint	pattrb9;	/* 0x24a38 - Pattern Match Attributes Register */
+	uint	pattrbeli9;	/* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd10;		/* 0x24a40 - Pattern Match Data Register */
+	char	res55[4];
+	uint	pmask10;	/* 0x24a48 - Pattern Mask Register */
+	char	res56[4];
+	uint	pcntrl10;	/* 0x24a50 - Pattern Match Control Register */
+	char	res57[4];
+	uint	pattrb10;	/* 0x24a58 - Pattern Match Attributes Register */
+	uint	pattrbeli10;	/* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd11;		/* 0x24a60 - Pattern Match Data Register */
+	char	res58[4];
+	uint	pmask11;	/* 0x24a68 - Pattern Mask Register */
+	char	res59[4];
+	uint	pcntrl11;	/* 0x24a70 - Pattern Match Control Register */
+	char	res60[4];
+	uint	pattrb11;	/* 0x24a78 - Pattern Match Attributes Register */
+	uint	pattrbeli11;	/* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd12;		/* 0x24a80 - Pattern Match Data Register */
+	char	res61[4];
+	uint	pmask12;	/* 0x24a88 - Pattern Mask Register */
+	char	res62[4];
+	uint	pcntrl12;	/* 0x24a90 - Pattern Match Control Register */
+	char	res63[4];
+	uint	pattrb12;	/* 0x24a98 - Pattern Match Attributes Register */
+	uint	pattrbeli12;	/* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd13;		/* 0x24aa0 - Pattern Match Data Register */
+	char	res64[4];
+	uint	pmask13;	/* 0x24aa8 - Pattern Mask Register */
+	char	res65[4];
+	uint	pcntrl13;	/* 0x24ab0 - Pattern Match Control Register */
+	char	res66[4];
+	uint	pattrb13;	/* 0x24ab8 - Pattern Match Attributes Register */
+	uint	pattrbeli13;	/* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd14;		/* 0x24ac0 - Pattern Match Data Register */
+	char	res67[4];
+	uint	pmask14;	/* 0x24ac8 - Pattern Mask Register */
+	char	res68[4];
+	uint	pcntrl14;	/* 0x24ad0 - Pattern Match Control Register */
+	char	res69[4];
+	uint	pattrb14;	/* 0x24ad8 - Pattern Match Attributes Register */
+	uint	pattrbeli14;	/* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */
+	uint	pmd15;		/* 0x24ae0 - Pattern Match Data Register */
+	char	res70[4];
+	uint	pmask15;	/* 0x24ae8 - Pattern Mask Register */
+	char	res71[4];
+	uint	pcntrl15;	/* 0x24af0 - Pattern Match Control Register */
+	char	res72[4];
+	uint	pattrb15;	/* 0x24af8 - Pattern Match Attributes Register */
+	uint	pattrbeli15;	/* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */
+	char	res73[248];
+	uint	attr;		/* 0x24bf8 - Attributes Register */
+	uint	attreli;	/* 0x24bfc - Attributes Extract Length and Extract Index Register */
+	char	res74[1024];
+} ccsr_tsec_t;
+
+/*
+ * PIC Registers(0x2_6000-0x4_0000-0x8_0000)
+ */
+typedef struct ccsr_pic {
+	char 	res0[106496];	/* 0x26000-0x40000 */
+	char	res1[64];
+	uint	ipidr0;		/* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
+	char	res2[12];
+	uint	ipidr1;		/* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
+	char	res3[12];
+	uint	ipidr2;		/* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
+	char	res4[12];
+	uint	ipidr3;		/* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
+	char	res5[12];
+	uint	ctpr;		/* 0x40080 - Current Task Priority Register */
+	char	res6[12];
+	uint	whoami;		/* 0x40090 - Who Am I Register */
+	char	res7[12];
+	uint	iack;		/* 0x400a0 - Interrupt Acknowledge Register */
+	char	res8[12];
+	uint	eoi;		/* 0x400b0 - End Of Interrupt Register */
+	char	res9[3916];
+	uint	frr;		/* 0x41000 - Feature Reporting Register */
+	char	res10[28];
+	uint	gcr;		/* 0x41020 - Global Configuration Register */
+#define MPC85xx_PICGCR_RST   0x80000000
+#define MPC85xx_PICGCR_M     0x20000000
+	char	res11[92];
+	uint	vir;		/* 0x41080 - Vendor Identification Register */
+	char	res12[12];
+	uint	pir;		/* 0x41090 - Processor Initialization Register */
+	char	res13[12];
+	uint	ipivpr0;	/* 0x410a0 - IPI Vector/Priority Register 0 */
+	char	res14[12];
+	uint	ipivpr1;	/* 0x410b0 - IPI Vector/Priority Register 1 */
+	char	res15[12];
+	uint	ipivpr2;	/* 0x410c0 - IPI Vector/Priority Register 2 */
+	char	res16[12];
+	uint	ipivpr3;	/* 0x410d0 - IPI Vector/Priority Register 3 */
+	char	res17[12];
+	uint	svr;		/* 0x410e0 - Spurious Vector Register */
+	char	res18[12];
+	uint	tfrr;		/* 0x410f0 - Timer Frequency Reporting Register */
+	char	res19[12];
+	uint	gtccr0;		/* 0x41100 - Global Timer Current Count Register 0 */
+	char	res20[12];
+	uint	gtbcr0;		/* 0x41110 - Global Timer Base Count Register 0 */
+	char	res21[12];
+	uint	gtvpr0;		/* 0x41120 - Global Timer Vector/Priority Register 0 */
+	char	res22[12];
+	uint	gtdr0;		/* 0x41130 - Global Timer Destination Register 0 */
+	char	res23[12];
+	uint	gtccr1;		/* 0x41140 - Global Timer Current Count Register 1 */
+	char	res24[12];
+	uint	gtbcr1;		/* 0x41150 - Global Timer Base Count Register 1 */
+	char	res25[12];
+	uint	gtvpr1;		/* 0x41160 - Global Timer Vector/Priority Register 1 */
+	char	res26[12];
+	uint	gtdr1;		/* 0x41170 - Global Timer Destination Register 1 */
+	char	res27[12];
+	uint	gtccr2;		/* 0x41180 - Global Timer Current Count Register 2 */
+	char	res28[12];
+	uint	gtbcr2;		/* 0x41190 - Global Timer Base Count Register 2 */
+	char	res29[12];
+	uint	gtvpr2;		/* 0x411a0 - Global Timer Vector/Priority Register 2 */
+	char	res30[12];
+	uint	gtdr2;		/* 0x411b0 - Global Timer Destination Register 2 */
+	char	res31[12];
+	uint	gtccr3;		/* 0x411c0 - Global Timer Current Count Register 3 */
+	char	res32[12];
+	uint	gtbcr3;		/* 0x411d0 - Global Timer Base Count Register 3 */
+	char	res33[12];
+	uint	gtvpr3;		/* 0x411e0 - Global Timer Vector/Priority Register 3 */
+	char	res34[12];
+	uint	gtdr3;		/* 0x411f0 - Global Timer Destination Register 3 */
+	char	res35[268];
+	uint	tcr;		/* 0x41300 - Timer Control Register */
+	char	res36[12];
+	uint	irqsr0;		/* 0x41310 - IRQ_OUT Summary Register 0 */
+	char	res37[12];
+	uint	irqsr1;		/* 0x41320 - IRQ_OUT Summary Register 1 */
+	char	res38[12];
+	uint	cisr0;		/* 0x41330 - Critical Interrupt Summary Register 0 */
+	char	res39[12];
+	uint	cisr1;		/* 0x41340 - Critical Interrupt Summary Register 1 */
+	char	res40[188];
+	uint	msgr0;		/* 0x41400 - Message Register 0 */
+	char	res41[12];
+	uint	msgr1;		/* 0x41410 - Message Register 1 */
+	char	res42[12];
+	uint	msgr2;		/* 0x41420 - Message Register 2 */
+	char	res43[12];
+	uint	msgr3;		/* 0x41430 - Message Register 3 */
+	char	res44[204];
+	uint	mer;		/* 0x41500 - Message Enable Register */
+	char	res45[12];
+	uint	msr;		/* 0x41510 - Message Status Register */
+	char	res46[60140];
+	uint	eivpr0;		/* 0x50000 - External Interrupt Vector/Priority Register 0 */
+	char	res47[12];
+	uint	eidr0;		/* 0x50010 - External Interrupt Destination Register 0 */
+	char	res48[12];
+	uint	eivpr1;		/* 0x50020 - External Interrupt Vector/Priority Register 1 */
+	char	res49[12];
+	uint	eidr1;		/* 0x50030 - External Interrupt Destination Register 1 */
+	char	res50[12];
+	uint	eivpr2;		/* 0x50040 - External Interrupt Vector/Priority Register 2 */
+	char	res51[12];
+	uint	eidr2;		/* 0x50050 - External Interrupt Destination Register 2 */
+	char	res52[12];
+	uint	eivpr3;		/* 0x50060 - External Interrupt Vector/Priority Register 3 */
+	char	res53[12];
+	uint	eidr3;		/* 0x50070 - External Interrupt Destination Register 3 */
+	char	res54[12];
+	uint	eivpr4;		/* 0x50080 - External Interrupt Vector/Priority Register 4 */
+	char	res55[12];
+	uint	eidr4;		/* 0x50090 - External Interrupt Destination Register 4 */
+	char	res56[12];
+	uint	eivpr5;		/* 0x500a0 - External Interrupt Vector/Priority Register 5 */
+	char	res57[12];
+	uint	eidr5;		/* 0x500b0 - External Interrupt Destination Register 5 */
+	char	res58[12];
+	uint	eivpr6;		/* 0x500c0 - External Interrupt Vector/Priority Register 6 */
+	char	res59[12];
+	uint	eidr6;		/* 0x500d0 - External Interrupt Destination Register 6 */
+	char	res60[12];
+	uint	eivpr7;		/* 0x500e0 - External Interrupt Vector/Priority Register 7 */
+	char	res61[12];
+	uint	eidr7;		/* 0x500f0 - External Interrupt Destination Register 7 */
+	char	res62[12];
+	uint	eivpr8;		/* 0x50100 - External Interrupt Vector/Priority Register 8 */
+	char	res63[12];
+	uint	eidr8;		/* 0x50110 - External Interrupt Destination Register 8 */
+	char	res64[12];
+	uint	eivpr9;		/* 0x50120 - External Interrupt Vector/Priority Register 9 */
+	char	res65[12];
+	uint	eidr9;		/* 0x50130 - External Interrupt Destination Register 9 */
+	char	res66[12];
+	uint	eivpr10;	/* 0x50140 - External Interrupt Vector/Priority Register 10 */
+	char	res67[12];
+	uint	eidr10;		/* 0x50150 - External Interrupt Destination Register 10 */
+	char	res68[12];
+	uint	eivpr11;	/* 0x50160 - External Interrupt Vector/Priority Register 11 */
+	char	res69[12];
+	uint	eidr11;		/* 0x50170 - External Interrupt Destination Register 11 */
+	char	res70[140];
+	uint	iivpr0;		/* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
+	char	res71[12];
+	uint	iidr0;		/* 0x50210 - Internal Interrupt Destination Register 0 */
+	char	res72[12];
+	uint	iivpr1;		/* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
+	char	res73[12];
+	uint	iidr1;		/* 0x50230 - Internal Interrupt Destination Register 1 */
+	char	res74[12];
+	uint	iivpr2;		/* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
+	char	res75[12];
+	uint	iidr2;		/* 0x50250 - Internal Interrupt Destination Register 2 */
+	char	res76[12];
+	uint	iivpr3;		/* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
+	char	res77[12];
+	uint	iidr3;		/* 0x50270 - Internal Interrupt Destination Register 3 */
+	char	res78[12];
+	uint	iivpr4;		/* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
+	char	res79[12];
+	uint	iidr4;		/* 0x50290 - Internal Interrupt Destination Register 4 */
+	char	res80[12];
+	uint	iivpr5;		/* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
+	char	res81[12];
+	uint	iidr5;		/* 0x502b0 - Internal Interrupt Destination Register 5 */
+	char	res82[12];
+	uint	iivpr6;		/* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
+	char	res83[12];
+	uint	iidr6;		/* 0x502d0 - Internal Interrupt Destination Register 6 */
+	char	res84[12];
+	uint	iivpr7;		/* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
+	char	res85[12];
+	uint	iidr7;		/* 0x502f0 - Internal Interrupt Destination Register 7 */
+	char	res86[12];
+	uint	iivpr8;		/* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
+	char	res87[12];
+	uint	iidr8;		/* 0x50310 - Internal Interrupt Destination Register 8 */
+	char	res88[12];
+	uint	iivpr9;		/* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
+	char	res89[12];
+	uint	iidr9;		/* 0x50330 - Internal Interrupt Destination Register 9 */
+	char	res90[12];
+	uint	iivpr10;	/* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
+	char	res91[12];
+	uint	iidr10;		/* 0x50350 - Internal Interrupt Destination Register 10 */
+	char	res92[12];
+	uint	iivpr11;	/* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
+	char	res93[12];
+	uint	iidr11;		/* 0x50370 - Internal Interrupt Destination Register 11 */
+	char	res94[12];
+	uint	iivpr12;	/* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
+	char	res95[12];
+	uint	iidr12;		/* 0x50390 - Internal Interrupt Destination Register 12 */
+	char	res96[12];
+	uint	iivpr13;	/* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
+	char	res97[12];
+	uint	iidr13;		/* 0x503b0 - Internal Interrupt Destination Register 13 */
+	char	res98[12];
+	uint	iivpr14;	/* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
+	char	res99[12];
+	uint	iidr14;		/* 0x503d0 - Internal Interrupt Destination Register 14 */
+	char	res100[12];
+	uint	iivpr15;	/* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
+	char	res101[12];
+	uint	iidr15;		/* 0x503f0 - Internal Interrupt Destination Register 15 */
+	char	res102[12];
+	uint	iivpr16;	/* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
+	char	res103[12];
+	uint	iidr16;		/* 0x50410 - Internal Interrupt Destination Register 16 */
+	char	res104[12];
+	uint	iivpr17;	/* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
+	char	res105[12];
+	uint	iidr17;		/* 0x50430 - Internal Interrupt Destination Register 17 */
+	char	res106[12];
+	uint	iivpr18;	/* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
+	char	res107[12];
+	uint	iidr18;		/* 0x50450 - Internal Interrupt Destination Register 18 */
+	char	res108[12];
+	uint	iivpr19;	/* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
+	char	res109[12];
+	uint	iidr19;		/* 0x50470 - Internal Interrupt Destination Register 19 */
+	char	res110[12];
+	uint	iivpr20;	/* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
+	char	res111[12];
+	uint	iidr20;		/* 0x50490 - Internal Interrupt Destination Register 20 */
+	char	res112[12];
+	uint	iivpr21;	/* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
+	char	res113[12];
+	uint	iidr21;		/* 0x504b0 - Internal Interrupt Destination Register 21 */
+	char	res114[12];
+	uint	iivpr22;	/* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
+	char	res115[12];
+	uint	iidr22;		/* 0x504d0 - Internal Interrupt Destination Register 22 */
+	char	res116[12];
+	uint	iivpr23;	/* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
+	char	res117[12];
+	uint	iidr23;		/* 0x504f0 - Internal Interrupt Destination Register 23 */
+	char	res118[12];
+	uint	iivpr24;	/* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
+	char	res119[12];
+	uint	iidr24;		/* 0x50510 - Internal Interrupt Destination Register 24 */
+	char	res120[12];
+	uint	iivpr25;	/* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
+	char	res121[12];
+	uint	iidr25;		/* 0x50530 - Internal Interrupt Destination Register 25 */
+	char	res122[12];
+	uint	iivpr26;	/* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
+	char	res123[12];
+	uint	iidr26;		/* 0x50550 - Internal Interrupt Destination Register 26 */
+	char	res124[12];
+	uint	iivpr27;	/* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
+	char	res125[12];
+	uint	iidr27;		/* 0x50570 - Internal Interrupt Destination Register 27 */
+	char	res126[12];
+	uint	iivpr28;	/* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
+	char	res127[12];
+	uint	iidr28;		/* 0x50590 - Internal Interrupt Destination Register 28 */
+	char	res128[12];
+	uint	iivpr29;	/* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
+	char	res129[12];
+	uint	iidr29;		/* 0x505b0 - Internal Interrupt Destination Register 29 */
+	char	res130[12];
+	uint	iivpr30;	/* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
+	char	res131[12];
+	uint	iidr30;		/* 0x505d0 - Internal Interrupt Destination Register 30 */
+	char	res132[12];
+	uint	iivpr31;	/* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
+	char	res133[12];
+	uint	iidr31;		/* 0x505f0 - Internal Interrupt Destination Register 31 */
+	char	res134[4108];
+	uint	mivpr0;		/* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
+	char	res135[12];
+	uint	midr0;		/* 0x51610 - Messaging Interrupt Destination Register 0 */
+	char	res136[12];
+	uint	mivpr1;		/* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
+	char	res137[12];
+	uint	midr1;		/* 0x51630 - Messaging Interrupt Destination Register 1 */
+	char	res138[12];
+	uint	mivpr2;		/* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
+	char	res139[12];
+	uint	midr2;		/* 0x51650 - Messaging Interrupt Destination Register 2 */
+	char	res140[12];
+	uint	mivpr3;		/* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
+	char	res141[12];
+	uint	midr3;		/* 0x51670 - Messaging Interrupt Destination Register 3 */
+	char	res142[59852];
+	uint	ipi0dr0;	/* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
+	char	res143[12];
+	uint	ipi0dr1;	/* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
+	char	res144[12];
+	uint	ipi0dr2;	/* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
+	char	res145[12];
+	uint	ipi0dr3;	/* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
+	char	res146[12];
+	uint	ctpr0;		/* 0x60080 - Current Task Priority Register for Processor 0 */
+	char	res147[12];
+	uint	whoami0;	/* 0x60090 - Who Am I Register for Processor 0 */
+	char	res148[12];
+	uint	iack0;		/* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
+	char	res149[12];
+	uint	eoi0;		/* 0x600b0 - End Of Interrupt Register for Processor 0 */
+	char	res150[130892];
+} ccsr_pic_t;
+
+/*
+ * CPM Block(0x8_0000-0xc_0000)
+ */
+#ifndef CONFIG_CPM2
+typedef struct ccsr_cpm {
+	char res[262144];
+} ccsr_cpm_t;
+#else
+/*
+ * 0x8000-0x8ffff:DPARM
+ * 0x9000-0x90bff: General SIU
+ */
+typedef struct ccsr_cpm_siu {
+	char 	res1[80];
+	uint	smaer;
+	uint	smser;
+	uint	smevr;
+	char    res2[4];
+	uint	lmaer;
+	uint	lmser;
+	uint	lmevr;
+	char	res3[2964];
+} ccsr_cpm_siu_t;
+
+/* 0x90c00-0x90cff: Interrupt Controller */
+typedef struct ccsr_cpm_intctl {
+	ushort  sicr;
+	char    res1[2];
+	uint    sivec;
+	uint    sipnrh;
+	uint    sipnrl;
+	uint    siprr;
+	uint    scprrh;
+	uint    scprrl;
+	uint    simrh;
+	uint    simrl;
+	uint    siexr;
+	char    res2[88];
+	uint	sccr;
+	char	res3[124];
+} ccsr_cpm_intctl_t;
+
+/* 0x90d00-0x90d7f: input/output port */
+typedef struct ccsr_cpm_iop {
+	uint    pdira;
+	uint    ppara;
+	uint    psora;
+	uint    podra;
+	uint    pdata;
+	char    res1[12];
+	uint    pdirb;
+	uint    pparb;
+	uint    psorb;
+	uint    podrb;
+	uint    pdatb;
+	char    res2[12];
+	uint    pdirc;
+	uint    pparc;
+	uint    psorc;
+	uint    podrc;
+	uint    pdatc;
+	char    res3[12];
+	uint    pdird;
+	uint    ppard;
+	uint    psord;
+	uint    podrd;
+	uint    pdatd;
+	char    res4[12];
+} ccsr_cpm_iop_t;
+
+/* 0x90d80-0x91017: CPM timers */
+typedef struct ccsr_cpm_timer {
+	u_char  tgcr1;
+	char    res1[3];
+	u_char  tgcr2;
+	char    res2[11];
+	ushort  tmr1;
+	ushort  tmr2;
+	ushort  trr1;
+	ushort  trr2;
+	ushort  tcr1;
+	ushort  tcr2;
+	ushort  tcn1;
+	ushort  tcn2;
+	ushort  tmr3;
+	ushort  tmr4;
+	ushort  trr3;
+	ushort  trr4;
+	ushort  tcr3;
+	ushort  tcr4;
+	ushort  tcn3;
+	ushort  tcn4;
+	ushort  ter1;
+	ushort  ter2;
+	ushort  ter3;
+	ushort  ter4;
+	char    res3[608];
+} ccsr_cpm_timer_t;
+
+/* 0x91018-0x912ff: SDMA */
+typedef struct ccsr_cpm_sdma {
+	uchar	sdsr;
+	char 	res1[3];
+	uchar 	sdmr;
+	char 	res2[739];
+} ccsr_cpm_sdma_t;
+
+/* 0x91300-0x9131f: FCC1 */
+typedef struct ccsr_cpm_fcc1 {
+	uint    gfmr;
+	uint    fpsmr;
+	ushort  ftodr;
+	char    res1[2];
+	ushort  fdsr;
+	char    res2[2];
+	ushort  fcce;
+	char    res3[2];
+	ushort  fccm;
+	char    res4[2];
+	u_char  fccs;
+	char    res5[3];
+	u_char  ftirr_phy[4];
+} ccsr_cpm_fcc1_t;
+
+/* 0x91320-0x9133f: FCC2 */
+typedef struct ccsr_cpm_fcc2 {
+	uint    gfmr;
+	uint    fpsmr;
+	ushort  ftodr;
+	char    res1[2];
+	ushort  fdsr;
+	char    res2[2];
+	ushort  fcce;
+	char    res3[2];
+	ushort  fccm;
+	char    res4[2];
+	u_char  fccs;
+	char    res5[3];
+	u_char  ftirr_phy[4];
+} ccsr_cpm_fcc2_t;
+
+/* 0x91340-0x9137f: FCC3 */
+typedef struct ccsr_cpm_fcc3 {
+	uint    gfmr;
+	uint    fpsmr;
+	ushort  ftodr;
+	char    res1[2];
+	ushort  fdsr;
+	char    res2[2];
+	ushort  fcce;
+	char    res3[2];
+	ushort  fccm;
+	char    res4[2];
+	u_char  fccs;
+	char    res5[3];
+	char	res[36];
+} ccsr_cpm_fcc3_t;
+
+/* 0x91380-0x9139f: FCC1 extended */
+typedef struct ccsr_cpm_fcc1_ext {
+	uint	firper;
+	uint	firer;
+	uint	firsr_h;
+	uint	firsr_l;
+	u_char	gfemr;
+	char	res[15];
+
+} ccsr_cpm_fcc1_ext_t;
+
+/* 0x913a0-0x913cf: FCC2 extended */
+typedef struct ccsr_cpm_fcc2_ext {
+	uint	firper;
+	uint	firer;
+	uint	firsr_h;
+	uint	firsr_l;
+	u_char	gfemr;
+	char	res[31];
+} ccsr_cpm_fcc2_ext_t;
+
+/* 0x913d0-0x913ff: FCC3 extended */
+typedef struct ccsr_cpm_fcc3_ext {
+	u_char	gfemr;
+	char	res[47];
+} ccsr_cpm_fcc3_ext_t;
+
+/* 0x91400-0x915ef: TC layers */
+typedef struct ccsr_cpm_tmp1 {
+	char 	res[496];
+} ccsr_cpm_tmp1_t;
+
+/* 0x915f0-0x9185f: BRGs:5,6,7,8 */
+typedef struct ccsr_cpm_brg2 {
+	uint	brgc5;
+	uint	brgc6;
+	uint	brgc7;
+	uint	brgc8;
+	char	res[608];
+} ccsr_cpm_brg2_t;
+
+/* 0x91860-0x919bf: I2C */
+typedef struct ccsr_cpm_i2c {
+	u_char  i2mod;
+	char    res1[3];
+	u_char  i2add;
+	char    res2[3];
+	u_char  i2brg;
+	char    res3[3];
+	u_char  i2com;
+	char    res4[3];
+	u_char  i2cer;
+	char    res5[3];
+	u_char  i2cmr;
+	char    res6[331];
+} ccsr_cpm_i2c_t;
+
+/* 0x919c0-0x919ef: CPM core */
+typedef struct ccsr_cpm_cp {
+	uint    cpcr;
+	uint    rccr;
+	char    res1[14];
+	ushort  rter;
+	char    res2[2];
+	ushort  rtmr;
+	ushort  rtscr;
+	char    res3[2];
+	uint    rtsr;
+	char    res4[12];
+} ccsr_cpm_cp_t;
+
+/* 0x919f0-0x919ff: BRGs:1,2,3,4 */
+typedef struct ccsr_cpm_brg1 {
+	uint	brgc1;
+	uint	brgc2;
+	uint	brgc3;
+	uint	brgc4;
+} ccsr_cpm_brg1_t;
+
+/* 0x91a00-0x91a9f: SCC1-SCC4 */
+typedef struct ccsr_cpm_scc {
+	uint    gsmrl;
+	uint    gsmrh;
+	ushort  psmr;
+	char    res1[2];
+	ushort  todr;
+	ushort  dsr;
+	ushort  scce;
+	char    res2[2];
+	ushort  sccm;
+	char    res3;
+	u_char  sccs;
+	char    res4[8];
+} ccsr_cpm_scc_t;
+
+/* 0x91a80-0x91a9f */
+typedef struct ccsr_cpm_tmp2 {
+	char 	res[32];
+} ccsr_cpm_tmp2_t;
+
+/* 0x91aa0-0x91aff: SPI */
+typedef struct ccsr_cpm_spi {
+	ushort  spmode;
+	char    res1[4];
+	u_char  spie;
+	char    res2[3];
+	u_char  spim;
+	char    res3[2];
+	u_char  spcom;
+	char    res4[82];
+} ccsr_cpm_spi_t;
+
+/* 0x91b00-0x91b1f: CPM MUX */
+typedef struct ccsr_cpm_mux {
+	u_char  cmxsi1cr;
+	char    res1;
+	u_char  cmxsi2cr;
+	char    res2;
+	uint    cmxfcr;
+	uint    cmxscr;
+	char    res3[2];
+	ushort  cmxuar;
+	char    res4[16];
+} ccsr_cpm_mux_t;
+
+/* 0x91b20-0xbffff: SI,MCC,etc */
+typedef struct ccsr_cpm_tmp3 {
+	char res[58592];
+} ccsr_cpm_tmp3_t;
+
+typedef struct ccsr_cpm_iram {
+	unsigned long iram[8192];
+	char res[98304];
+} ccsr_cpm_iram_t;
+
+typedef struct ccsr_cpm {
+	/* Some references are into the unique and known dpram spaces,
+	 * others are from the generic base.
+	 */
+#define im_dprambase    	im_dpram1
+	u_char          	im_dpram1[16*1024];
+	char            	res1[16*1024];
+	u_char          	im_dpram2[16*1024];
+	char            	res2[16*1024];
+	ccsr_cpm_siu_t  	im_cpm_siu;     /* SIU Configuration */
+	ccsr_cpm_intctl_t    	im_cpm_intctl;  /* Interrupt Controller */
+	ccsr_cpm_iop_t       	im_cpm_iop;     /* IO Port control/status */
+	ccsr_cpm_timer_t  	im_cpm_timer;   /* CPM timers */
+	ccsr_cpm_sdma_t      	im_cpm_sdma;    /* SDMA control/status */
+	ccsr_cpm_fcc1_t		im_cpm_fcc1;
+	ccsr_cpm_fcc2_t		im_cpm_fcc2;
+	ccsr_cpm_fcc3_t		im_cpm_fcc3;
+	ccsr_cpm_fcc1_ext_t	im_cpm_fcc1_ext;
+	ccsr_cpm_fcc2_ext_t	im_cpm_fcc2_ext;
+	ccsr_cpm_fcc3_ext_t	im_cpm_fcc3_ext;
+	ccsr_cpm_tmp1_t		im_cpm_tmp1;
+	ccsr_cpm_brg2_t		im_cpm_brg2;
+	ccsr_cpm_i2c_t		im_cpm_i2c;
+	ccsr_cpm_cp_t		im_cpm_cp;
+	ccsr_cpm_brg1_t		im_cpm_brg1;
+	ccsr_cpm_scc_t		im_cpm_scc[4];
+	ccsr_cpm_tmp2_t		im_cpm_tmp2;
+	ccsr_cpm_spi_t		im_cpm_spi;
+	ccsr_cpm_mux_t		im_cpm_mux;
+	ccsr_cpm_tmp3_t		im_cpm_tmp3;
+	ccsr_cpm_iram_t		im_cpm_iram;
+} ccsr_cpm_t;
+#endif
+
+/*
+ * RapidIO Registers(0xc_0000-0xe_0000)
+ */
+typedef struct ccsr_rio {
+	uint	didcar;		/* 0xc0000 - Device Identity Capability Register */
+	uint	dicar;		/* 0xc0004 - Device Information Capability Register */
+	uint	aidcar;		/* 0xc0008 - Assembly Identity Capability Register */
+	uint	aicar;		/* 0xc000c - Assembly Information Capability Register */
+	uint	pefcar;		/* 0xc0010 - Processing Element Features Capability Register */
+	uint	spicar;		/* 0xc0014 - Switch Port Information Capability Register */
+	uint	socar;		/* 0xc0018 - Source Operations Capability Register */
+	uint	docar;		/* 0xc001c - Destination Operations Capability Register */
+	char	res1[32];
+	uint	msr;		/* 0xc0040 - Mailbox Command And Status Register */
+	uint	pwdcsr;		/* 0xc0044 - Port-Write and Doorbell Command And Status Register */
+	char	res2[4];
+	uint	pellccsr;	/* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
+	char	res3[12];
+	uint	lcsbacsr;	/* 0xc005c - Local Configuration Space Base Address Command and Status Register */
+	uint	bdidcsr;	/* 0xc0060 - Base Device ID Command and Status Register */
+	char	res4[4];
+	uint	hbdidlcsr;	/* 0xc0068 - Host Base Device ID Lock Command and Status Register */
+	uint	ctcsr;		/* 0xc006c - Component Tag Command and Status Register */
+	char	res5[144];
+	uint	pmbh0csr;	/* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
+	char	res6[28];
+	uint	pltoccsr;	/* 0xc0120 - Port Link Time-out Control Command and Status Register */
+	uint	prtoccsr;	/* 0xc0124 - Port Response Time-out Control Command and Status Register */
+	char	res7[20];
+	uint	pgccsr;		/* 0xc013c - Port General Command and Status Register */
+	uint	plmreqcsr;	/* 0xc0140 - Port Link Maintenance Request Command and Status Register */
+	uint	plmrespcsr;	/* 0xc0144 - Port Link Maintenance Response Command and Status Register */
+	uint	plascsr;	/* 0xc0148 - Port Local Ackid Status Command and Status Register */
+	char	res8[12];
+	uint	pescsr;		/* 0xc0158 - Port Error and Status Command and Status Register */
+	uint	pccsr;		/* 0xc015c - Port Control Command and Status Register */
+	char	res9[65184];
+	uint	cr;		/* 0xd0000 - Port Control Command and Status Register */
+	char	res10[12];
+	uint	pcr;		/* 0xd0010 - Port Configuration Register */
+	uint	peir;		/* 0xd0014 - Port Error Injection Register */
+	char	res11[3048];
+	uint	rowtar0;	/* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
+	char	res12[12];
+	uint	rowar0;		/* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
+	char	res13[12];
+	uint	rowtar1;	/* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
+	char	res14[4];
+	uint	rowbar1;	/* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
+	char	res15[4];
+	uint	rowar1;		/* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
+	char	res16[12];
+	uint	rowtar2;	/* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
+	char	res17[4];
+	uint	rowbar2;	/* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
+	char	res18[4];
+	uint	rowar2;		/* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
+	char	res19[12];
+	uint	rowtar3;	/* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
+	char	res20[4];
+	uint	rowbar3;	/* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
+	char	res21[4];
+	uint	rowar3;		/* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
+	char	res22[12];
+	uint	rowtar4;	/* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
+	char	res23[4];
+	uint	rowbar4;	/* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
+	char	res24[4];
+	uint	rowar4;		/* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
+	char	res25[12];
+	uint	rowtar5;	/* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
+	char	res26[4];
+	uint	rowbar5;	/* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
+	char	res27[4];
+	uint	rowar5;		/* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
+	char	res28[12];
+	uint	rowtar6;	/* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
+	char	res29[4];
+	uint	rowbar6;	/* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
+	char	res30[4];
+	uint	rowar6;		/* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
+	char	res31[12];
+	uint	rowtar7;	/* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
+	char	res32[4];
+	uint	rowbar7;	/* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
+	char	res33[4];
+	uint	rowar7;		/* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
+	char	res34[12];
+	uint	rowtar8;	/* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
+	char	res35[4];
+	uint	rowbar8;	/* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
+	char	res36[4];
+	uint	rowar8;		/* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
+	char	res37[76];
+	uint	riwtar4;	/* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
+	char	res38[4];
+	uint	riwbar4;	/* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
+	char	res39[4];
+	uint	riwar4;		/* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
+	char	res40[12];
+	uint	riwtar3;	/* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
+	char	res41[4];
+	uint	riwbar3;	/* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
+	char	res42[4];
+	uint	riwar3;		/* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
+	char	res43[12];
+	uint	riwtar2;	/* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
+	char	res44[4];
+	uint	riwbar2;	/* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
+	char	res45[4];
+	uint	riwar2;		/* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
+	char	res46[12];
+	uint	riwtar1;	/* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
+	char	res47[4];
+	uint	riwbar1;	/* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
+	char	res48[4];
+	uint	riwar1;		/* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
+	char	res49[12];
+	uint	riwtar0;	/* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
+	char	res50[12];
+	uint	riwar0;		/* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
+	char	res51[12];
+	uint	pnfedr;		/* 0xd0e00 - Port Notification/Fatal Error Detect Register */
+	uint	pnfedir;	/* 0xd0e04 - Port Notification/Fatal Error Detect Register */
+	uint	pnfeier;	/* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
+	uint	pecr;		/* 0xd0e0c - Port Error Control Register */
+	uint	pepcsr0;	/* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
+	uint	pepr1;		/* 0xd0e14 - Port Error Packet Register 1 */
+	uint	pepr2;		/* 0xd0e18 - Port Error Packet Register 2 */
+	char	res52[4];
+	uint	predr;		/* 0xd0e20 - Port Recoverable Error Detect Register */
+	char	res53[4];
+	uint	pertr;		/* 0xd0e28 - Port Error Recovery Threshold Register */
+	uint	prtr;		/* 0xd0e2c - Port Retry Threshold Register */
+	char	res54[464];
+	uint	omr;		/* 0xd1000 - Outbound Mode Register */
+	uint	osr;		/* 0xd1004 - Outbound Status Register */
+	uint	eodqtpar;	/* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
+	uint	odqtpar;	/* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */
+	uint	eosar;		/* 0xd1010 - Extended Outbound Unit Source Address Register */
+	uint	osar;		/* 0xd1014 - Outbound Unit Source Address Register */
+	uint	odpr;		/* 0xd1018 - Outbound Destination Port Register */
+	uint	odatr;		/* 0xd101c - Outbound Destination Attributes Register */
+	uint	odcr;		/* 0xd1020 - Outbound Doubleword Count Register */
+	uint	eodqhpar;	/* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
+	uint	odqhpar;	/* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */
+	char	res55[52];
+	uint	imr;		/* 0xd1060 - Outbound Mode Register */
+	uint	isr;		/* 0xd1064 - Inbound Status Register */
+	uint	eidqtpar;	/* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
+	uint	idqtpar;	/* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */
+	uint	eifqhpar;	/* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */
+	uint	ifqhpar;	/* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */
+	char	res56[1000];
+	uint	dmr;		/* 0xd1460 - Doorbell Mode Register */
+	uint	dsr;		/* 0xd1464 - Doorbell Status Register */
+	uint	edqtpar;	/* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */
+	uint	dqtpar;		/* 0xd146c - Doorbell Queue Tail Pointer Address Register */
+	uint	edqhpar;	/* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */
+	uint	dqhpar;		/* 0xd1474 - Doorbell Queue Head Pointer Address Register */
+	char	res57[104];
+	uint	pwmr;		/* 0xd14e0 - Port-Write Mode Register */
+	uint	pwsr;		/* 0xd14e4 - Port-Write Status Register */
+	uint	epwqbar;	/* 0xd14e8 - Extended Port-Write Queue Base Address Register */
+	uint	pwqbar;		/* 0xd14ec - Port-Write Queue Base Address Register */
+	char	res58[60176];
+} ccsr_rio_t;
+
+/*
+ * Global Utilities Register Block(0xe_0000-0xf_ffff)
+ */
+typedef struct ccsr_gur {
+	uint	porpllsr;	/* 0xe0000 - POR PLL ratio status register */
+	uint	porbmsr;	/* 0xe0004 - POR boot mode status register */
+	uint	porimpscr;	/* 0xe0008 - POR I/O impedance status and control register */
+	uint	pordevsr;	/* 0xe000c - POR I/O device status regsiter */
+	uint	pordbgmsr;	/* 0xe0010 - POR debug mode status register */
+	char	res1[12];
+	uint	gpporcr;	/* 0xe0020 - General-purpose POR configuration register */
+	char	res2[12];
+	uint	gpiocr;		/* 0xe0030 - GPIO control register */
+	char	res3[12];
+	uint	gpoutdr;	/* 0xe0040 - General-purpose output data register */
+	char	res4[12];
+	uint	gpindr;		/* 0xe0050 - General-purpose input data register */
+	char	res5[12];
+	uint	pmuxcr;		/* 0xe0060 - Alternate function signal multiplex control */
+	char	res6[12];
+	uint	devdisr;	/* 0xe0070 - Device disable control */
+	char	res7[12];
+	uint	powmgtcsr;	/* 0xe0080 - Power management status and control register */
+	char	res8[12];
+	uint	mcpsumr;	/* 0xe0090 - Machine check summary register */
+	char	res9[12];
+	uint	pvr;		/* 0xe00a0 - Processor version register */
+	uint	svr;		/* 0xe00a4 - System version register */
+	char	res10[3416];
+	uint	clkocr;		/* 0xe0e00 - Clock out select register */
+	char	res11[12];
+	uint	ddrdllcr;	/* 0xe0e10 - DDR DLL control register */
+	char	res12[12];
+	uint	lbcdllcr;	/* 0xe0e20 - LBC DLL control register */
+	char	res13[248];
+	uint	lbiuiplldcr0;	/* 0xe0f1c -- LBIU PLL Debug Reg 0 */
+	uint	lbiuiplldcr1;	/* 0xe0f20 -- LBIU PLL Debug Reg 1 */
+	uint	ddrioovcr;	/* 0xe0f24 - DDR IO Override Control */
+	uint	res14;		/* 0xe0f28 */
+	uint	tsec34ioovcr;	/* 0xe0f2c - eTSEC 3/4 IO override control */
+	char	res15[61651];
+} ccsr_gur_t;
+
+typedef struct immap {
+	ccsr_local_ecm_t	im_local_ecm;
+	ccsr_ddr_t		im_ddr;
+	ccsr_i2c_t		im_i2c;
+	ccsr_duart_t		im_duart;
+	ccsr_lbc_t		im_lbc;
+	ccsr_pcix_t		im_pcix;
+	ccsr_l2cache_t		im_l2cache;
+	ccsr_dma_t		im_dma;
+	ccsr_tsec_t		im_tsec1;
+	ccsr_tsec_t		im_tsec2;
+	ccsr_pic_t		im_pic;
+	ccsr_cpm_t		im_cpm;
+	ccsr_rio_t		im_rio;
+	ccsr_gur_t		im_gur;
+} immap_t;
+
+extern immap_t  *immr;
+
+#endif /*__IMMAP_85xx__*/
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
new file mode 100755
index 0000000..8e5fe11
--- /dev/null
+++ b/include/asm-ppc/io.h
@@ -0,0 +1,180 @@
+/* originally from linux source.
+ * removed the dependencies on CONFIG_ values
+ * removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__)
+ * Modified By Rob Taylor, Flying Pig Systems, 2000
+ */
+
+#ifndef _PPC_IO_H
+#define _PPC_IO_H
+
+#include <linux/config.h>
+#include <asm/byteorder.h>
+
+#define SIO_CONFIG_RA   0x398
+#define SIO_CONFIG_RD   0x399
+
+
+#define readb(addr) in_8((volatile u8 *)(addr))
+#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
+#if !defined(__BIG_ENDIAN)
+#define readw(addr) (*(volatile u16 *) (addr))
+#define readl(addr) (*(volatile u32 *) (addr))
+#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
+#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
+#else
+#define readw(addr) in_le16((volatile u16 *)(addr))
+#define readl(addr) in_le32((volatile u32 *)(addr))
+#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
+#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
+#endif
+
+/*
+ * The insw/outsw/insl/outsl macros don't do byte-swapping.
+ * They are only used in practice for transferring buffers which
+ * are arrays of bytes, and byte-swapping is not appropriate in
+ * that case.  - paulus
+ */
+#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define outsb(port, buf, ns)    _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw(port, buf, ns)    _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl(port, buf, nl)    _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define inb(port)       in_8((u8 *)((port)+_IO_BASE))
+#define outb(val, port)     out_8((u8 *)((port)+_IO_BASE), (val))
+#if !defined(__BIG_ENDIAN)
+#define inw(port)       in_be16((u16 *)((port)+_IO_BASE))
+#define outw(val, port)     out_be16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port)       in_be32((u32 *)((port)+_IO_BASE))
+#define outl(val, port)     out_be32((u32 *)((port)+_IO_BASE), (val))
+#else
+#define inw(port)       in_le16((u16 *)((port)+_IO_BASE))
+#define outw(val, port)     out_le16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port)       in_le32((u32 *)((port)+_IO_BASE))
+#define outl(val, port)     out_le32((u32 *)((port)+_IO_BASE), (val))
+#endif
+
+#define inb_p(port)     in_8((u8 *)((port)+_IO_BASE))
+#define outb_p(val, port)   out_8((u8 *)((port)+_IO_BASE), (val))
+#define inw_p(port)     in_le16((u16 *)((port)+_IO_BASE))
+#define outw_p(val, port)   out_le16((u16 *)((port)+_IO_BASE), (val))
+#define inl_p(port)     in_le32((u32 *)((port)+_IO_BASE))
+#define outl_p(val, port)   out_le32((u32 *)((port)+_IO_BASE), (val))
+
+extern void _insb(volatile u8 *port, void *buf, int ns);
+extern void _outsb(volatile u8 *port, const void *buf, int ns);
+extern void _insw(volatile u16 *port, void *buf, int ns);
+extern void _outsw(volatile u16 *port, const void *buf, int ns);
+extern void _insl(volatile u32 *port, void *buf, int nl);
+extern void _outsl(volatile u32 *port, const void *buf, int nl);
+extern void _insw_ns(volatile u16 *port, void *buf, int ns);
+extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
+extern void _insl_ns(volatile u32 *port, void *buf, int nl);
+extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
+
+/*
+ * The *_ns versions below don't do byte-swapping.
+ * Neither do the standard versions now, these are just here
+ * for older code.
+ */
+#define insw_ns(port, buf, ns)  _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl_ns(port, buf, nl)  _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+
+#define IO_SPACE_LIMIT ~0
+
+#define memset_io(a,b,c)       memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c)  memcpy((void *)(a),(b),(c))
+
+/*
+ * Enforce In-order Execution of I/O:
+ * Acts as a barrier to ensure all previous I/O accesses have
+ * completed before any further ones are issued.
+ */
+#define eieio() __asm__ __volatile__ ("eieio" : : : "memory");
+#define sync()  __asm__ __volatile__ ("sync" : : : "memory");
+
+/* Enforce in-order execution of data I/O.
+ * No distinction between read/write on PPC; use eieio for all three.
+ */
+#define iobarrier_rw() eieio()
+#define iobarrier_r()  eieio()
+#define iobarrier_w()  eieio()
+
+/*
+ * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ */
+extern inline int in_8(volatile u8 *addr)
+{
+    int ret;
+
+    __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+    return ret;
+}
+
+extern inline void out_8(volatile u8 *addr, int val)
+{
+    __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+
+extern inline int in_le16(volatile u16 *addr)
+{
+    int ret;
+
+    __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) :
+		  "r" (addr), "m" (*addr));
+    return ret;
+}
+
+extern inline int in_be16(volatile u16 *addr)
+{
+    int ret;
+
+    __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+    return ret;
+}
+
+extern inline void out_le16(volatile u16 *addr, int val)
+{
+    __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
+		  "r" (val), "r" (addr));
+}
+
+extern inline void out_be16(volatile u16 *addr, int val)
+{
+    __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+
+extern inline unsigned in_le32(volatile u32 *addr)
+{
+    unsigned ret;
+
+    __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
+		 "r" (addr), "m" (*addr));
+    return ret;
+}
+
+extern inline unsigned in_be32(volatile u32 *addr)
+{
+    unsigned ret;
+
+    __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+    return ret;
+}
+
+extern inline void out_le32(volatile unsigned *addr, int val)
+{
+    __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
+		 "r" (val), "r" (addr));
+}
+
+extern inline void out_be32(volatile unsigned *addr, int val)
+{
+    __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+}
+
+#endif
diff --git a/include/asm-ppc/iopin_8260.h b/include/asm-ppc/iopin_8260.h
new file mode 100755
index 0000000..21ed8c2
--- /dev/null
+++ b/include/asm-ppc/iopin_8260.h
@@ -0,0 +1,168 @@
+/*
+ * MPC8260 I/O port pin manipulation functions
+ */
+
+#ifndef _ASM_IOPIN_8260_H_
+#define _ASM_IOPIN_8260_H_
+
+#include <linux/types.h>
+#include <asm/immap_8260.h>
+
+#ifdef __KERNEL__
+
+typedef
+    struct {
+	u_char port:2;	/* port number (A=0, B=1, C=2, D=3) */
+	u_char pin:5;	/* port pin (0-31) */
+	u_char flag:1;	/* for whatever */
+    }
+iopin_t;
+
+#define IOPIN_PORTA	0
+#define IOPIN_PORTB	1
+#define IOPIN_PORTC	2
+#define IOPIN_PORTD	3
+
+extern __inline__ void
+iopin_set_high(iopin_t *iopin)
+{
+    volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+    datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void
+iopin_set_low(iopin_t *iopin)
+{
+    volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+    datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint
+iopin_is_high(iopin_t *iopin)
+{
+    volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+    return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint
+iopin_is_low(iopin_t *iopin)
+{
+    volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+    return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void
+iopin_set_out(iopin_t *iopin)
+{
+    volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+    dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void
+iopin_set_in(iopin_t *iopin)
+{
+    volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+    dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint
+iopin_is_out(iopin_t *iopin)
+{
+    volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+    return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint
+iopin_is_in(iopin_t *iopin)
+{
+    volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+    return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void
+iopin_set_odr(iopin_t *iopin)
+{
+    volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+    odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void
+iopin_set_act(iopin_t *iopin)
+{
+    volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+    odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint
+iopin_is_odr(iopin_t *iopin)
+{
+    volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+    return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint
+iopin_is_act(iopin_t *iopin)
+{
+    volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+    return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void
+iopin_set_ded(iopin_t *iopin)
+{
+    volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+    parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void
+iopin_set_gen(iopin_t *iopin)
+{
+    volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+    parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint
+iopin_is_ded(iopin_t *iopin)
+{
+    volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+    return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint
+iopin_is_gen(iopin_t *iopin)
+{
+    volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+    return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+extern __inline__ void
+iopin_set_opt2(iopin_t *iopin)
+{
+    volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+    sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
+}
+
+extern __inline__ void
+iopin_set_opt1(iopin_t *iopin)
+{
+    volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+    sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
+}
+
+extern __inline__ uint
+iopin_is_opt2(iopin_t *iopin)
+{
+    volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+    return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
+}
+
+extern __inline__ uint
+iopin_is_opt1(iopin_t *iopin)
+{
+    volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+    return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IOPIN_8260_H_ */
diff --git a/include/asm-ppc/iopin_8xx.h b/include/asm-ppc/iopin_8xx.h
new file mode 100755
index 0000000..1946eb2
--- /dev/null
+++ b/include/asm-ppc/iopin_8xx.h
@@ -0,0 +1,395 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * MPC8xx I/O port pin manipulation functions
+ * Roughly based on iopin_8260.h
+ */
+
+#ifndef _ASM_IOPIN_8XX_H_
+#define _ASM_IOPIN_8XX_H_
+
+#include <linux/types.h>
+#include <asm/8xx_immap.h>
+
+#ifdef __KERNEL__
+
+typedef struct {
+	u_char port:2;	/* port number (A=0, B=1, C=2, D=3) */
+	u_char pin:5;	/* port pin (0-31) */
+	u_char flag:1;	/* for whatever */
+} iopin_t;
+
+#define IOPIN_PORTA	0
+#define IOPIN_PORTB	1
+#define IOPIN_PORTC	2
+#define IOPIN_PORTD	3
+
+extern __inline__ void
+iopin_set_high(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+		*datp |= (1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+		*datp |= (1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+		*datp |= (1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+		*datp |= (1 << (15 - iopin->pin));
+	}
+}
+
+extern __inline__ void
+iopin_set_low(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+		*datp &= ~(1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+		*datp &= ~(1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+		*datp &= ~(1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+		*datp &= ~(1 << (15 - iopin->pin));
+	}
+}
+
+extern __inline__ uint
+iopin_is_high(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+		return (*datp >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+		return (*datp >> (31 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+		return (*datp >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+		return (*datp >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+extern __inline__ uint
+iopin_is_low(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+		return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+		return ((*datp >> (31 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+		return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+		return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+extern __inline__ void
+iopin_set_out(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+		*dirp |= (1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+		*dirp |= (1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+		*dirp |= (1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+		*dirp |= (1 << (15 - iopin->pin));
+	}
+}
+
+extern __inline__ void
+iopin_set_in(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+		*dirp &= ~(1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+		*dirp &= ~(1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+		*dirp &= ~(1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+		*dirp &= ~(1 << (15 - iopin->pin));
+	}
+}
+
+extern __inline__ uint
+iopin_is_out(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+		return (*dirp >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+		return (*dirp >> (31 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+		return (*dirp >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+		return (*dirp >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+extern __inline__ uint
+iopin_is_in(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+		return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+		return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+		return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+		return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+extern __inline__ void
+iopin_set_odr(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+		*odrp |= (1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+		*odrp |= (1 << (31 - iopin->pin));
+	}
+}
+
+extern __inline__ void
+iopin_set_act(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+		*odrp &= ~(1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+		*odrp &= ~(1 << (31 - iopin->pin));
+	}
+}
+
+extern __inline__ uint
+iopin_is_odr(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+		return (*odrp >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+		return (*odrp >> (31 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+extern __inline__ uint
+iopin_is_act(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+		return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+		return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+extern __inline__ void
+iopin_set_ded(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+		*parp |= (1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+		*parp |= (1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+		*parp |= (1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+		*parp |= (1 << (15 - iopin->pin));
+	}
+}
+
+extern __inline__ void
+iopin_set_gen(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+		*parp &= ~(1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+		*parp &= ~(1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+		*parp &= ~(1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+		*parp &= ~(1 << (15 - iopin->pin));
+	}
+}
+
+extern __inline__ uint
+iopin_is_ded(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+		return (*parp >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+		return (*parp >> (31 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+		return (*parp >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+		return (*parp >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+extern __inline__ uint
+iopin_is_gen(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTA) {
+		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+		return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+		return ((*parp >> (31 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+		return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+		return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+extern __inline__ void
+iopin_set_opt2(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+		*sorp |= (1 << (15 - iopin->pin));
+	}
+}
+
+extern __inline__ void
+iopin_set_opt1(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+		*sorp &= ~(1 << (15 - iopin->pin));
+	}
+}
+
+extern __inline__ uint
+iopin_is_opt2(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+		return (*sorp >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+extern __inline__ uint
+iopin_is_opt1(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+		return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+extern __inline__ void
+iopin_set_falledge(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+		*intp |= (1 << (15 - iopin->pin));
+	}
+}
+
+extern __inline__ void
+iopin_set_anyedge(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+		*intp &= ~(1 << (15 - iopin->pin));
+	}
+}
+
+extern __inline__ uint
+iopin_is_falledge(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+		return (*intp >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+extern __inline__ uint
+iopin_is_anyedge(iopin_t *iopin)
+{
+	if (iopin->port == IOPIN_PORTC) {
+		volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+		return ((*intp >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IOPIN_8XX_H_ */
diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h
new file mode 100755
index 0000000..45f01de
--- /dev/null
+++ b/include/asm-ppc/m8260_pci.h
@@ -0,0 +1,166 @@
+
+#ifndef _PPC_KERNEL_M8260_PCI_H
+#define _PPC_KERNEL_M8260_PCI_H
+
+#define M8265_PCIBR0	0x101ac
+#define M8265_PCIBR1	0x101b0
+#define M8265_PCIMSK0	0x101c4
+#define M8265_PCIMSK1	0x101c8
+
+/* Bit definitions for PCIBR registers */
+
+#define PCIBR_ENABLE        0x00000001
+
+/* Bit definitions for PCIMSK registers */
+
+#define PCIMSK_32KB         0xFFFF8000  /* Size of window, smallest */
+#define PCIMSK_64KB         0xFFFF0000
+#define PCIMSK_128KB        0xFFFE0000
+#define PCIMSK_256KB        0xFFFC0000
+#define PCIMSK_512KB        0xFFF80000
+#define PCIMSK_1MB          0xFFF00000
+#define PCIMSK_2MB          0xFFE00000
+#define PCIMSK_4MB          0xFFC00000
+#define PCIMSK_8MB          0xFF800000
+#define PCIMSK_16MB         0xFF000000
+#define PCIMSK_32MB         0xFE000000
+#define PCIMSK_64MB         0xFC000000
+#define PCIMSK_128MB        0xF8000000
+#define PCIMSK_256MB        0xF0000000
+#define PCIMSK_512MB        0xE0000000
+#define PCIMSK_1GB          0xC0000000  /* Size of window, largest */
+
+
+#define M826X_SCCR_PCI_MODE_EN 0x100
+
+
+/*
+ * Outbound ATU registers (3 sets). These registers control how 60x bus (local)
+ * addresses are translated to PCI addresses when the MPC826x is a PCI bus
+ * master (initiator).
+ */
+
+#define POTAR_REG0          0x10800     /* PCI Outbound Translation Addr registers */
+#define POTAR_REG1          0x10818
+#define POTAR_REG2          0x10830
+
+#define POBAR_REG0          0x10808     /* PCI Outbound Base Addr registers */
+#define POBAR_REG1          0x10820
+#define POBAR_REG2          0x10838
+
+#define POCMR_REG0          0x10810     /* PCI Outbound Comparison Mask registers */
+#define POCMR_REG1          0x10828
+#define POCMR_REG2          0x10840
+
+/* Bit definitions for POMCR registers */
+
+#define POCMR_MASK_4KB      0x000FFFFF
+#define POCMR_MASK_8KB      0x000FFFFE
+#define POCMR_MASK_16KB     0x000FFFFC
+#define POCMR_MASK_32KB     0x000FFFF8
+#define POCMR_MASK_64KB     0x000FFFF0
+#define POCMR_MASK_128KB    0x000FFFE0
+#define POCMR_MASK_256KB    0x000FFFC0
+#define POCMR_MASK_512KB    0x000FFF80
+#define POCMR_MASK_1MB      0x000FFF00
+#define POCMR_MASK_2MB      0x000FFE00
+#define POCMR_MASK_4MB      0x000FFC00
+#define POCMR_MASK_8MB      0x000FF800
+#define POCMR_MASK_16MB     0x000FF000
+#define POCMR_MASK_32MB     0x000FE000
+#define POCMR_MASK_64MB     0x000FC000
+#define POCMR_MASK_128MB    0x000F8000
+#define POCMR_MASK_256MB    0x000F0000
+#define POCMR_MASK_512MB    0x000E0000
+#define POCMR_MASK_1GB      0x000C0000
+
+#define POCMR_ENABLE        0x80000000
+#define POCMR_PCI_IO        0x40000000
+#define POCMR_PREFETCH_EN   0x20000000
+
+/* Soft PCI reset */
+
+#define PCI_GCR_REG         0x10880
+
+/* Bit definitions for PCI_GCR registers */
+
+#define PCIGCR_PCI_BUS_EN   0x1
+
+/*
+ * Inbound ATU registers (2 sets). These registers control how PCI addresses
+ * are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target.
+ */
+
+#define PITAR_REG1          0x108D0
+#define PIBAR_REG1          0x108D8
+#define PICMR_REG1          0x108E0
+#define PITAR_REG0          0x108E8
+#define PIBAR_REG0          0x108F0
+#define PICMR_REG0          0x108F8
+
+/* Bit definitions for PCI Inbound Comparison Mask registers */
+
+#define PICMR_MASK_4KB       0x000FFFFF
+#define PICMR_MASK_8KB       0x000FFFFE
+#define PICMR_MASK_16KB      0x000FFFFC
+#define PICMR_MASK_32KB      0x000FFFF8
+#define PICMR_MASK_64KB      0x000FFFF0
+#define PICMR_MASK_128KB     0x000FFFE0
+#define PICMR_MASK_256KB     0x000FFFC0
+#define PICMR_MASK_512KB     0x000FFF80
+#define PICMR_MASK_1MB       0x000FFF00
+#define PICMR_MASK_2MB       0x000FFE00
+#define PICMR_MASK_4MB       0x000FFC00
+#define PICMR_MASK_8MB       0x000FF800
+#define PICMR_MASK_16MB      0x000FF000
+#define PICMR_MASK_32MB      0x000FE000
+#define PICMR_MASK_64MB      0x000FC000
+#define PICMR_MASK_128MB     0x000F8000
+#define PICMR_MASK_256MB     0x000F0000
+#define PICMR_MASK_512MB     0x000E0000
+#define PICMR_MASK_1GB       0x000C0000
+
+#define PICMR_ENABLE         0x80000000
+#define PICMR_NO_SNOOP_EN    0x40000000
+#define PICMR_PREFETCH_EN    0x20000000
+
+/* PCI error Registers */
+
+#define	PCI_ERROR_STATUS_REG		0x10884
+#define	PCI_ERROR_MASK_REG		0x10888
+#define	PCI_ERROR_CONTROL_REG		0x1088C
+#define PCI_ERROR_ADRS_CAPTURE_REG      0x10890
+#define PCI_ERROR_DATA_CAPTURE_REG      0x10898
+#define PCI_ERROR_CTRL_CAPTURE_REG      0x108A0
+
+/* PCI error Register bit defines */
+
+#define	PCI_ERROR_PCI_ADDR_PAR			0x00000001
+#define	PCI_ERROR_PCI_DATA_PAR_WR		0x00000002
+#define	PCI_ERROR_PCI_DATA_PAR_RD		0x00000004
+#define	PCI_ERROR_PCI_NO_RSP			0x00000008
+#define	PCI_ERROR_PCI_TAR_ABT			0x00000010
+#define	PCI_ERROR_PCI_SERR			0x00000020
+#define	PCI_ERROR_PCI_PERR_RD			0x00000040
+#define	PCI_ERROR_PCI_PERR_WR			0x00000080
+#define	PCI_ERROR_I2O_OFQO			0x00000100
+#define	PCI_ERROR_I2O_IPQO			0x00000200
+#define	PCI_ERROR_IRA				0x00000400
+#define	PCI_ERROR_NMI				0x00000800
+#define	PCI_ERROR_I2O_DBMC			0x00001000
+
+/*
+ * Register pair used to generate configuration cycles on the PCI bus
+ * and access the MPC826x's own PCI configuration registers.
+ */
+
+#define PCI_CFG_ADDR_REG     0x10900
+#define PCI_CFG_DATA_REG     0x10904
+
+/* Bus parking decides where the bus control sits when idle */
+/* If modifying memory controllers for PCI park on the core */
+
+#define PPC_ACR_BUS_PARK_CORE 0x6
+#define PPC_ACR_BUS_PARK_PCI  0x3
+
+#endif /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/include/asm-ppc/mc146818rtc.h b/include/asm-ppc/mc146818rtc.h
new file mode 100755
index 0000000..5f806c4
--- /dev/null
+++ b/include/asm-ppc/mc146818rtc.h
@@ -0,0 +1,27 @@
+/*
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef __ASM_PPC_MC146818RTC_H
+#define __ASM_PPC_MC146818RTC_H
+
+#include <asm/io.h>
+
+#ifndef RTC_PORT
+#define RTC_PORT(x) (0x70 + (x))
+#define RTC_ALWAYS_BCD  1   /* RTC operates in binary mode */
+#endif
+
+/*
+ * The yet supported machines all access the RTC index register via
+ * an ISA port access but the way to access the date register differs ...
+ */
+#define CMOS_READ(addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+inb_p(RTC_PORT(1)); \
+})
+#define CMOS_WRITE(val, addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+outb_p((val),RTC_PORT(1)); \
+})
+
+#endif /* __ASM_PPC_MC146818RTC_H */
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
new file mode 100755
index 0000000..2606b79
--- /dev/null
+++ b/include/asm-ppc/mmu.h
@@ -0,0 +1,473 @@
+/*
+ * PowerPC memory management structures
+ */
+
+#ifndef _PPC_MMU_H_
+#define _PPC_MMU_H_
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+/* Hardware Page Table Entry */
+typedef struct _PTE {
+#ifdef CONFIG_PPC64BRIDGE
+	unsigned long long vsid:52;
+	unsigned long api:5;
+	unsigned long :5;
+	unsigned long h:1;
+	unsigned long v:1;
+	unsigned long long rpn:52;
+#else /* CONFIG_PPC64BRIDGE */
+	unsigned long v:1;	/* Entry is valid */
+	unsigned long vsid:24;	/* Virtual segment identifier */
+	unsigned long h:1;	/* Hash algorithm indicator */
+	unsigned long api:6;	/* Abbreviated page index */
+	unsigned long rpn:20;	/* Real (physical) page number */
+#endif /* CONFIG_PPC64BRIDGE */
+	unsigned long    :3;	/* Unused */
+	unsigned long r:1;	/* Referenced */
+	unsigned long c:1;	/* Changed */
+	unsigned long w:1;	/* Write-thru cache mode */
+	unsigned long i:1;	/* Cache inhibited */
+	unsigned long m:1;	/* Memory coherence */
+	unsigned long g:1;	/* Guarded */
+	unsigned long  :1;	/* Unused */
+	unsigned long pp:2;	/* Page protection */
+} PTE;
+
+/* Values for PP (assumes Ks=0, Kp=1) */
+#define PP_RWXX	0	/* Supervisor read/write, User none */
+#define PP_RWRX 1	/* Supervisor read/write, User read */
+#define PP_RWRW 2	/* Supervisor read/write, User read/write */
+#define PP_RXRX 3	/* Supervisor read,       User read */
+
+/* Segment Register */
+typedef struct _SEGREG {
+	unsigned long t:1;	/* Normal or I/O  type */
+	unsigned long ks:1;	/* Supervisor 'key' (normally 0) */
+	unsigned long kp:1;	/* User 'key' (normally 1) */
+	unsigned long n:1;	/* No-execute */
+	unsigned long :4;	/* Unused */
+	unsigned long vsid:24;	/* Virtual Segment Identifier */
+} SEGREG;
+
+/* Block Address Translation (BAT) Registers */
+typedef struct _P601_BATU {	/* Upper part of BAT for 601 processor */
+	unsigned long bepi:15;	/* Effective page index (virtual address) */
+	unsigned long :8;	/* unused */
+	unsigned long w:1;
+	unsigned long i:1;	/* Cache inhibit */
+	unsigned long m:1;	/* Memory coherence */
+	unsigned long ks:1;	/* Supervisor key (normally 0) */
+	unsigned long kp:1;	/* User key (normally 1) */
+	unsigned long pp:2;	/* Page access protections */
+} P601_BATU;
+
+typedef struct _BATU {		/* Upper part of BAT (all except 601) */
+#ifdef CONFIG_PPC64BRIDGE
+	unsigned long long bepi:47;
+#else /* CONFIG_PPC64BRIDGE */
+	unsigned long bepi:15;	/* Effective page index (virtual address) */
+#endif /* CONFIG_PPC64BRIDGE */
+	unsigned long :4;	/* Unused */
+	unsigned long bl:11;	/* Block size mask */
+	unsigned long vs:1;	/* Supervisor valid */
+	unsigned long vp:1;	/* User valid */
+} BATU;
+
+typedef struct _P601_BATL {	/* Lower part of BAT for 601 processor */
+	unsigned long brpn:15;	/* Real page index (physical address) */
+	unsigned long :10;	/* Unused */
+	unsigned long v:1;	/* Valid bit */
+	unsigned long bl:6;	/* Block size mask */
+} P601_BATL;
+
+typedef struct _BATL {		/* Lower part of BAT (all except 601) */
+#ifdef CONFIG_PPC64BRIDGE
+	unsigned long long brpn:47;
+#else /* CONFIG_PPC64BRIDGE */
+	unsigned long brpn:15;	/* Real page index (physical address) */
+#endif /* CONFIG_PPC64BRIDGE */
+	unsigned long :10;	/* Unused */
+	unsigned long w:1;	/* Write-thru cache */
+	unsigned long i:1;	/* Cache inhibit */
+	unsigned long m:1;	/* Memory coherence */
+	unsigned long g:1;	/* Guarded (MBZ in IBAT) */
+	unsigned long :1;	/* Unused */
+	unsigned long pp:2;	/* Page access protections */
+} BATL;
+
+typedef struct _BAT {
+	BATU batu;		/* Upper register */
+	BATL batl;		/* Lower register */
+} BAT;
+
+typedef struct _P601_BAT {
+	P601_BATU batu;		/* Upper register */
+	P601_BATL batl;		/* Lower register */
+} P601_BAT;
+
+/*
+ * Simulated two-level MMU.  This structure is used by the kernel
+ * to keep track of MMU mappings and is used to update/maintain
+ * the hardware HASH table which is really a cache of mappings.
+ *
+ * The simulated structures mimic the hardware available on other
+ * platforms, notably the 80x86 and 680x0.
+ */
+
+typedef struct _pte {
+   	unsigned long page_num:20;
+   	unsigned long flags:12;		/* Page flags (some unused bits) */
+} pte;
+
+#define PD_SHIFT (10+12)		/* Page directory */
+#define PD_MASK  0x02FF
+#define PT_SHIFT (12)			/* Page Table */
+#define PT_MASK  0x02FF
+#define PG_SHIFT (12)			/* Page Entry */
+
+
+/* MMU context */
+
+typedef struct _MMU_context {
+	SEGREG	segs[16];	/* Segment registers */
+	pte	**pmap;		/* Two-level page-map structure */
+} MMU_context;
+
+extern void _tlbie(unsigned long va);	/* invalidate a TLB entry */
+extern void _tlbia(void);		/* invalidate all TLB entries */
+
+typedef enum {
+	IBAT0 = 0, IBAT1, IBAT2, IBAT3,
+	DBAT0, DBAT1, DBAT2, DBAT3
+} ppc_bat_t;
+
+extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
+extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
+
+#endif /* __ASSEMBLY__ */
+
+/* Block size masks */
+#define BL_128K	0x000
+#define BL_256K 0x001
+#define BL_512K 0x003
+#define BL_1M   0x007
+#define BL_2M   0x00F
+#define BL_4M   0x01F
+#define BL_8M   0x03F
+#define BL_16M  0x07F
+#define BL_32M  0x0FF
+#define BL_64M  0x1FF
+#define BL_128M 0x3FF
+#define BL_256M 0x7FF
+
+/* BAT Access Protection */
+#define BPP_XX	0x00		/* No access */
+#define BPP_RX	0x01		/* Read only */
+#define BPP_RW	0x02		/* Read/write */
+
+/* Used to set up SDR1 register */
+#define HASH_TABLE_SIZE_64K	0x00010000
+#define HASH_TABLE_SIZE_128K	0x00020000
+#define HASH_TABLE_SIZE_256K	0x00040000
+#define HASH_TABLE_SIZE_512K	0x00080000
+#define HASH_TABLE_SIZE_1M	0x00100000
+#define HASH_TABLE_SIZE_2M	0x00200000
+#define HASH_TABLE_SIZE_4M	0x00400000
+#define HASH_TABLE_MASK_64K	0x000
+#define HASH_TABLE_MASK_128K	0x001
+#define HASH_TABLE_MASK_256K	0x003
+#define HASH_TABLE_MASK_512K	0x007
+#define HASH_TABLE_MASK_1M	0x00F
+#define HASH_TABLE_MASK_2M	0x01F
+#define HASH_TABLE_MASK_4M	0x03F
+
+/* Control/status registers for the MPC8xx.
+ * A write operation to these registers causes serialized access.
+ * During software tablewalk, the registers used perform mask/shift-add
+ * operations when written/read.  A TLB entry is created when the Mx_RPN
+ * is written, and the contents of several registers are used to
+ * create the entry.
+ */
+#define MI_CTR		784	/* Instruction TLB control register */
+#define MI_GPM		0x80000000	/* Set domain manager mode */
+#define MI_PPM		0x40000000	/* Set subpage protection */
+#define MI_CIDEF	0x20000000	/* Set cache inhibit when MMU dis */
+#define MI_RSV4I	0x08000000	/* Reserve 4 TLB entries */
+#define MI_PPCS		0x02000000	/* Use MI_RPN prob/priv state */
+#define MI_IDXMASK	0x00001f00	/* TLB index to be loaded */
+#define MI_RESETVAL	0x00000000	/* Value of register at reset */
+
+/* These are the Ks and Kp from the PowerPC books.  For proper operation,
+ * Ks = 0, Kp = 1.
+ */
+#define MI_AP		786
+#define MI_Ks		0x80000000	/* Should not be set */
+#define MI_Kp		0x40000000	/* Should always be set */
+
+/* The effective page number register.  When read, contains the information
+ * about the last instruction TLB miss.  When MI_RPN is written, bits in
+ * this register are used to create the TLB entry.
+ */
+#define MI_EPN		787
+#define MI_EPNMASK	0xfffff000	/* Effective page number for entry */
+#define MI_EVALID	0x00000200	/* Entry is valid */
+#define MI_ASIDMASK	0x0000000f	/* ASID match value */
+					/* Reset value is undefined */
+
+/* A "level 1" or "segment" or whatever you want to call it register.
+ * For the instruction TLB, it contains bits that get loaded into the
+ * TLB entry when the MI_RPN is written.
+ */
+#define MI_TWC		789
+#define MI_APG		0x000001e0	/* Access protection group (0) */
+#define MI_GUARDED	0x00000010	/* Guarded storage */
+#define MI_PSMASK	0x0000000c	/* Mask of page size bits */
+#define MI_PS8MEG	0x0000000c	/* 8M page size */
+#define MI_PS512K	0x00000004	/* 512K page size */
+#define MI_PS4K_16K	0x00000000	/* 4K or 16K page size */
+#define MI_SVALID	0x00000001	/* Segment entry is valid */
+					/* Reset value is undefined */
+
+/* Real page number.  Defined by the pte.  Writing this register
+ * causes a TLB entry to be created for the instruction TLB, using
+ * additional information from the MI_EPN, and MI_TWC registers.
+ */
+#define MI_RPN		790
+
+/* Define an RPN value for mapping kernel memory to large virtual
+ * pages for boot initialization.  This has real page number of 0,
+ * large page size, shared page, cache enabled, and valid.
+ * Also mark all subpages valid and write access.
+ */
+#define MI_BOOTINIT	0x000001fd
+
+#define MD_CTR		792	/* Data TLB control register */
+#define MD_GPM		0x80000000	/* Set domain manager mode */
+#define MD_PPM		0x40000000	/* Set subpage protection */
+#define MD_CIDEF	0x20000000	/* Set cache inhibit when MMU dis */
+#define MD_WTDEF	0x10000000	/* Set writethrough when MMU dis */
+#define MD_RSV4I	0x08000000	/* Reserve 4 TLB entries */
+#define MD_TWAM		0x04000000	/* Use 4K page hardware assist */
+#define MD_PPCS		0x02000000	/* Use MI_RPN prob/priv state */
+#define MD_IDXMASK	0x00001f00	/* TLB index to be loaded */
+#define MD_RESETVAL	0x04000000	/* Value of register at reset */
+
+#define M_CASID		793	/* Address space ID (context) to match */
+#define MC_ASIDMASK	0x0000000f	/* Bits used for ASID value */
+
+
+/* These are the Ks and Kp from the PowerPC books.  For proper operation,
+ * Ks = 0, Kp = 1.
+ */
+#define MD_AP		794
+#define MD_Ks		0x80000000	/* Should not be set */
+#define MD_Kp		0x40000000	/* Should always be set */
+
+/* The effective page number register.  When read, contains the information
+ * about the last instruction TLB miss.  When MD_RPN is written, bits in
+ * this register are used to create the TLB entry.
+ */
+#define MD_EPN		795
+#define MD_EPNMASK	0xfffff000	/* Effective page number for entry */
+#define MD_EVALID	0x00000200	/* Entry is valid */
+#define MD_ASIDMASK	0x0000000f	/* ASID match value */
+					/* Reset value is undefined */
+
+/* The pointer to the base address of the first level page table.
+ * During a software tablewalk, reading this register provides the address
+ * of the entry associated with MD_EPN.
+ */
+#define M_TWB		796
+#define	M_L1TB		0xfffff000	/* Level 1 table base address */
+#define M_L1INDX	0x00000ffc	/* Level 1 index, when read */
+					/* Reset value is undefined */
+
+/* A "level 1" or "segment" or whatever you want to call it register.
+ * For the data TLB, it contains bits that get loaded into the TLB entry
+ * when the MD_RPN is written.  It is also provides the hardware assist
+ * for finding the PTE address during software tablewalk.
+ */
+#define MD_TWC		797
+#define MD_L2TB		0xfffff000	/* Level 2 table base address */
+#define MD_L2INDX	0xfffffe00	/* Level 2 index (*pte), when read */
+#define MD_APG		0x000001e0	/* Access protection group (0) */
+#define MD_GUARDED	0x00000010	/* Guarded storage */
+#define MD_PSMASK	0x0000000c	/* Mask of page size bits */
+#define MD_PS8MEG	0x0000000c	/* 8M page size */
+#define MD_PS512K	0x00000004	/* 512K page size */
+#define MD_PS4K_16K	0x00000000	/* 4K or 16K page size */
+#define MD_WT		0x00000002	/* Use writethrough page attribute */
+#define MD_SVALID	0x00000001	/* Segment entry is valid */
+					/* Reset value is undefined */
+
+
+/* Real page number.  Defined by the pte.  Writing this register
+ * causes a TLB entry to be created for the data TLB, using
+ * additional information from the MD_EPN, and MD_TWC registers.
+ */
+#define MD_RPN		798
+
+/* This is a temporary storage register that could be used to save
+ * a processor working register during a tablewalk.
+ */
+#define M_TW		799
+
+/*
+ * At present, all PowerPC 400-class processors share a similar TLB
+ * architecture. The instruction and data sides share a unified,
+ * 64-entry, fully-associative TLB which is maintained totally under
+ * software control. In addition, the instruction side has a
+ * hardware-managed, 4-entry, fully- associative TLB which serves as a
+ * first level to the shared TLB. These two TLBs are known as the UTLB
+ * and ITLB, respectively.
+ */
+
+#define        PPC4XX_TLB_SIZE 64
+
+/*
+ * TLB entries are defined by a "high" tag portion and a "low" data
+ * portion.  On all architectures, the data portion is 32-bits.
+ *
+ * TLB entries are managed entirely under software control by reading,
+ * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
+ * instructions.
+ */
+
+#define	TLB_LO          1
+#define	TLB_HI          0
+
+#define	TLB_DATA        TLB_LO
+#define	TLB_TAG         TLB_HI
+
+/* Tag portion */
+
+#define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
+#define TLB_PAGESZ_MASK 0x00000380
+#define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
+#define   PAGESZ_1K		0
+#define   PAGESZ_4K             1
+#define   PAGESZ_16K            2
+#define   PAGESZ_64K            3
+#define   PAGESZ_256K           4
+#define   PAGESZ_1M             5
+#define   PAGESZ_4M             6
+#define   PAGESZ_16M            7
+#define TLB_VALID       0x00000040      /* Entry is valid */
+
+/* Data portion */
+
+#define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
+#define TLB_PERM_MASK   0x00000300
+#define TLB_EX          0x00000200      /* Instruction execution allowed */
+#define TLB_WR          0x00000100      /* Writes permitted */
+#define TLB_ZSEL_MASK   0x000000F0
+#define TLB_ZSEL(x)     (((x) & 0xF) << 4)
+#define TLB_ATTR_MASK   0x0000000F
+#define TLB_W           0x00000008      /* Caching is write-through */
+#define TLB_I           0x00000004      /* Caching is inhibited */
+#define TLB_M           0x00000002      /* Memory is coherent */
+#define TLB_G           0x00000001      /* Memory is guarded from prefetch */
+
+/*
+ * e500 support
+ */
+
+#define MAS0_TLBSEL     0x10000000
+#define MAS0_ESEL       0x000F0000
+#define MAS0_NV         0x00000001
+
+#define MAS1_VALID      0x80000000
+#define MAS1_IPROT      0x40000000
+#define MAS1_TID        0x00FF0000
+#define MAS1_TS         0x00001000
+#define MAS1_TSIZE   	0x00000F00
+
+#define MAS2_EPN        0xFFFFF000
+#define MAS2_SHAREN     0x00000200
+#define MAS2_X0         0x00000040
+#define MAS2_X1         0x00000020
+#define MAS2_W          0x00000010
+#define MAS2_I          0x00000008
+#define MAS2_M          0x00000004
+#define MAS2_G          0x00000002
+#define MAS2_E          0x00000001
+
+#define MAS3_RPN        0xFFFFF000
+#define MAS3_U0         0x00000200
+#define MAS3_U1         0x00000100
+#define MAS3_U2         0x00000080
+#define MAS3_U3         0x00000040
+#define MAS3_UX         0x00000020
+#define MAS3_SX         0x00000010
+#define MAS3_UW         0x00000008
+#define MAS3_SW         0x00000004
+#define MAS3_UR         0x00000002
+#define MAS3_SR         0x00000001
+
+#define MAS4_TLBSELD    0x10000000
+#define MAS4_TIDDSEL    0x00030000
+#define MAS4_DSHAREN    0x00001000
+#define MAS4_TSIZED(x)  (x << 8)
+#define MAS4_X0D        0x00000040
+#define MAS4_X1D        0x00000020
+#define MAS4_WD         0x00000010
+#define MAS4_ID         0x00000008
+#define MAS4_MD         0x00000004
+#define MAS4_GD         0x00000002
+#define MAS4_ED         0x00000001
+
+#define MAS6_SPID       0x00FF0000
+#define MAS6_SAS        0x00000001
+
+#define BOOKE_PAGESZ_1K         0
+#define BOOKE_PAGESZ_4K         1
+#define BOOKE_PAGESZ_16K        2
+#define BOOKE_PAGESZ_64K        3
+#define BOOKE_PAGESZ_256K       4
+#define BOOKE_PAGESZ_1M         5
+#define BOOKE_PAGESZ_4M         6
+#define BOOKE_PAGESZ_16M        7
+#define BOOKE_PAGESZ_64M        8
+#define BOOKE_PAGESZ_256M       9
+#define BOOKE_PAGESZ_1GB        10
+#define BOOKE_PAGESZ_4GB        11
+
+#define LAWBAR_BASE_ADDR	0x000FFFFF
+#define LAWAR_EN		0x80000000
+#define LAWAR_TRGT_IF		0x00F00000
+#define LAWAR_SIZE		0x0000003F
+
+#define LAWAR_TRGT_IF_PCI	0x00000000
+#define LAWAR_TRGT_IF_PCI1	0x00000000
+#define LAWAR_TRGT_IF_PCIX	0x00000000
+#define LAWAR_TRGT_IF_PCI2	0x00100000
+#define LAWAR_TRGT_IF_LBC	0x00400000
+#define LAWAR_TRGT_IF_CCSR	0x00800000
+#define LAWAR_TRGT_IF_RIO	0x00c00000
+#define LAWAR_TRGT_IF_DDR	0x00f00000
+
+#define LAWAR_SIZE_BASE		0xa
+#define LAWAR_SIZE_4K		(LAWAR_SIZE_BASE+1)
+#define LAWAR_SIZE_8K		(LAWAR_SIZE_BASE+2)
+#define LAWAR_SIZE_16K		(LAWAR_SIZE_BASE+3)
+#define LAWAR_SIZE_32K		(LAWAR_SIZE_BASE+4)
+#define LAWAR_SIZE_64K		(LAWAR_SIZE_BASE+5)
+#define LAWAR_SIZE_128K		(LAWAR_SIZE_BASE+6)
+#define LAWAR_SIZE_256K		(LAWAR_SIZE_BASE+7)
+#define LAWAR_SIZE_512K		(LAWAR_SIZE_BASE+8)
+#define LAWAR_SIZE_1M		(LAWAR_SIZE_BASE+9)
+#define LAWAR_SIZE_2M		(LAWAR_SIZE_BASE+10)
+#define LAWAR_SIZE_4M		(LAWAR_SIZE_BASE+11)
+#define LAWAR_SIZE_8M		(LAWAR_SIZE_BASE+12)
+#define LAWAR_SIZE_16M		(LAWAR_SIZE_BASE+13)
+#define LAWAR_SIZE_32M		(LAWAR_SIZE_BASE+14)
+#define LAWAR_SIZE_64M		(LAWAR_SIZE_BASE+15)
+#define LAWAR_SIZE_128M		(LAWAR_SIZE_BASE+16)
+#define LAWAR_SIZE_256M		(LAWAR_SIZE_BASE+17)
+#define LAWAR_SIZE_512M		(LAWAR_SIZE_BASE+18)
+#define LAWAR_SIZE_1G		(LAWAR_SIZE_BASE+19)
+#define LAWAR_SIZE_2G		(LAWAR_SIZE_BASE+20)
+
+#endif /* _PPC_MMU_H_ */
diff --git a/include/asm-ppc/mpc8349_pci.h b/include/asm-ppc/mpc8349_pci.h
new file mode 100755
index 0000000..48255a3
--- /dev/null
+++ b/include/asm-ppc/mpc8349_pci.h
@@ -0,0 +1,167 @@
+#ifndef _PPC_KERNEL_MPC8349_PCI_H
+#define _PPC_KERNEL_MPC8349_PCI_H
+
+
+#define M8265_PCIBR0	0x101ac
+#define M8265_PCIBR1	0x101b0
+#define M8265_PCIMSK0	0x101c4
+#define M8265_PCIMSK1	0x101c8
+
+/* Bit definitions for PCIBR registers */
+
+#define PCIBR_ENABLE        0x00000001
+
+/* Bit definitions for PCIMSK registers */
+
+#define PCIMSK_32KB         0xFFFF8000  /* Size of window, smallest */
+#define PCIMSK_64KB         0xFFFF0000
+#define PCIMSK_128KB        0xFFFE0000
+#define PCIMSK_256KB        0xFFFC0000
+#define PCIMSK_512KB        0xFFF80000
+#define PCIMSK_1MB          0xFFF00000
+#define PCIMSK_2MB          0xFFE00000
+#define PCIMSK_4MB          0xFFC00000
+#define PCIMSK_8MB          0xFF800000
+#define PCIMSK_16MB         0xFF000000
+#define PCIMSK_32MB         0xFE000000
+#define PCIMSK_64MB         0xFC000000
+#define PCIMSK_128MB        0xF8000000
+#define PCIMSK_256MB        0xF0000000
+#define PCIMSK_512MB        0xE0000000
+#define PCIMSK_1GB          0xC0000000  /* Size of window, largest */
+
+
+#define M826X_SCCR_PCI_MODE_EN 0x100
+
+
+/*
+ * Outbound ATU registers (3 sets). These registers control how 60x bus
+ * (local) addresses are translated to PCI addresses when the MPC826x is
+ * a PCI bus master (initiator).
+ */
+
+#define POTAR_REG0          0x10800     /* PCI Outbound Translation Addr registers */
+#define POTAR_REG1          0x10818
+#define POTAR_REG2          0x10830
+
+#define POBAR_REG0          0x10808     /* PCI Outbound Base Addr registers */
+#define POBAR_REG1          0x10820
+#define POBAR_REG2          0x10838
+
+#define POCMR_REG0          0x10810     /* PCI Outbound Comparison Mask registers */
+#define POCMR_REG1          0x10828
+#define POCMR_REG2          0x10840
+
+/* Bit definitions for POMCR registers */
+
+#define POCMR_MASK_4KB      0x000FFFFF
+#define POCMR_MASK_8KB      0x000FFFFE
+#define POCMR_MASK_16KB     0x000FFFFC
+#define POCMR_MASK_32KB     0x000FFFF8
+#define POCMR_MASK_64KB     0x000FFFF0
+#define POCMR_MASK_128KB    0x000FFFE0
+#define POCMR_MASK_256KB    0x000FFFC0
+#define POCMR_MASK_512KB    0x000FFF80
+#define POCMR_MASK_1MB      0x000FFF00
+#define POCMR_MASK_2MB      0x000FFE00
+#define POCMR_MASK_4MB      0x000FFC00
+#define POCMR_MASK_8MB      0x000FF800
+#define POCMR_MASK_16MB     0x000FF000
+#define POCMR_MASK_32MB     0x000FE000
+#define POCMR_MASK_64MB     0x000FC000
+#define POCMR_MASK_128MB    0x000F8000
+#define POCMR_MASK_256MB    0x000F0000
+#define POCMR_MASK_512MB    0x000E0000
+#define POCMR_MASK_1GB      0x000C0000
+
+#define POCMR_ENABLE        0x80000000
+#define POCMR_PCI_IO        0x40000000
+#define POCMR_PREFETCH_EN   0x20000000
+
+/* Soft PCI reset */
+
+#define PCI_GCR_REG         0x10880
+
+/* Bit definitions for PCI_GCR registers */
+
+#define PCIGCR_PCI_BUS_EN   0x1
+
+/*
+ * Inbound ATU registers (2 sets). These registers control how PCI
+ * addresses are translated to 60x bus (local) addresses when the
+ * MPC826x is a PCI bus target.
+ */
+
+#define PITAR_REG1          0x108D0
+#define PIBAR_REG1          0x108D8
+#define PICMR_REG1          0x108E0
+#define PITAR_REG0          0x108E8
+#define PIBAR_REG0          0x108F0
+#define PICMR_REG0          0x108F8
+
+/* Bit definitions for PCI Inbound Comparison Mask registers */
+
+#define PICMR_MASK_4KB       0x000FFFFF
+#define PICMR_MASK_8KB       0x000FFFFE
+#define PICMR_MASK_16KB      0x000FFFFC
+#define PICMR_MASK_32KB      0x000FFFF8
+#define PICMR_MASK_64KB      0x000FFFF0
+#define PICMR_MASK_128KB     0x000FFFE0
+#define PICMR_MASK_256KB     0x000FFFC0
+#define PICMR_MASK_512KB     0x000FFF80
+#define PICMR_MASK_1MB       0x000FFF00
+#define PICMR_MASK_2MB       0x000FFE00
+#define PICMR_MASK_4MB       0x000FFC00
+#define PICMR_MASK_8MB       0x000FF800
+#define PICMR_MASK_16MB      0x000FF000
+#define PICMR_MASK_32MB      0x000FE000
+#define PICMR_MASK_64MB      0x000FC000
+#define PICMR_MASK_128MB     0x000F8000
+#define PICMR_MASK_256MB     0x000F0000
+#define PICMR_MASK_512MB     0x000E0000
+#define PICMR_MASK_1GB       0x000C0000
+
+#define PICMR_ENABLE         0x80000000
+#define PICMR_NO_SNOOP_EN    0x40000000
+#define PICMR_PREFETCH_EN    0x20000000
+
+/* PCI error Registers */
+
+#define	PCI_ERROR_STATUS_REG		0x10884
+#define	PCI_ERROR_MASK_REG		0x10888
+#define	PCI_ERROR_CONTROL_REG		0x1088C
+#define PCI_ERROR_ADRS_CAPTURE_REG      0x10890
+#define PCI_ERROR_DATA_CAPTURE_REG      0x10898
+#define PCI_ERROR_CTRL_CAPTURE_REG      0x108A0
+
+/* PCI error Register bit defines */
+
+#define	PCI_ERROR_PCI_ADDR_PAR			0x00000001
+#define	PCI_ERROR_PCI_DATA_PAR_WR		0x00000002
+#define	PCI_ERROR_PCI_DATA_PAR_RD		0x00000004
+#define	PCI_ERROR_PCI_NO_RSP			0x00000008
+#define	PCI_ERROR_PCI_TAR_ABT			0x00000010
+#define	PCI_ERROR_PCI_SERR			0x00000020
+#define	PCI_ERROR_PCI_PERR_RD			0x00000040
+#define	PCI_ERROR_PCI_PERR_WR			0x00000080
+#define	PCI_ERROR_I2O_OFQO			0x00000100
+#define	PCI_ERROR_I2O_IPQO			0x00000200
+#define	PCI_ERROR_IRA				0x00000400
+#define	PCI_ERROR_NMI				0x00000800
+#define	PCI_ERROR_I2O_DBMC			0x00001000
+
+/*
+ * Register pair used to generate configuration cycles on the PCI bus
+ * and access the MPC826x's own PCI configuration registers.
+ */
+
+#define PCI_CFG_ADDR_REG     0x10900
+#define PCI_CFG_DATA_REG     0x10904
+
+/* Bus parking decides where the bus control sits when idle */
+/* If modifying memory controllers for PCI park on the core */
+
+#define PPC_ACR_BUS_PARK_CORE 0x6
+#define PPC_ACR_BUS_PARK_PCI  0x3
+
+#endif /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/include/asm-ppc/pci_io.h b/include/asm-ppc/pci_io.h
new file mode 100755
index 0000000..9b738c3
--- /dev/null
+++ b/include/asm-ppc/pci_io.h
@@ -0,0 +1,43 @@
+/* originally from linux source (asm-ppc/io.h).
+ * Sanity added by Rob Taylor, Flying Pig Systems, 2000
+ */
+#ifndef _PCI_IO_H_
+#define _PCI_IO_H_
+
+#include "io.h"
+
+
+#define pci_read_le16(addr, dest) \
+    __asm__ __volatile__("lhbrx %0,0,%1" : "=r" (dest) : \
+		  "r" (addr), "m" (*addr));
+
+#define pci_write_le16(addr, val) \
+    __asm__ __volatile__("sthbrx %1,0,%2" : "=m" (*addr) : \
+		  "r" (val), "r" (addr));
+
+
+#define pci_read_le32(addr, dest) \
+    __asm__ __volatile__("lwbrx %0,0,%1" : "=r" (dest) : \
+		 "r" (addr), "m" (*addr));
+
+#define pci_write_le32(addr, val) \
+__asm__ __volatile__("stwbrx %1,0,%2" : "=m" (*addr) : \
+		 "r" (val), "r" (addr));
+
+#define pci_readb(addr,b) ((b) = *(volatile u8 *) (addr))
+#define pci_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
+
+#if !defined(__BIG_ENDIAN)
+#define pci_readw(addr,b) ((b) = *(volatile u16 *) (addr))
+#define pci_readl(addr,b) ((b) = *(volatile u32 *) (addr))
+#define pci_writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
+#define pci_writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
+#else
+#define pci_readw(addr,b) pci_read_le16((volatile u16 *)(addr),(b))
+#define pci_readl(addr,b) pci_read_le32((volatile u32 *)(addr),(b))
+#define pci_writew(b,addr) pci_write_le16((volatile u16 *)(addr),(b))
+#define pci_writel(b,addr) pci_write_le32((volatile u32 *)(addr),(b))
+#endif
+
+
+#endif /* _PCI_IO_H_ */
diff --git a/include/asm-ppc/pnp.h b/include/asm-ppc/pnp.h
new file mode 100755
index 0000000..22ceba2
--- /dev/null
+++ b/include/asm-ppc/pnp.h
@@ -0,0 +1,643 @@
+/* 11/02/95                                                                   */
+/*----------------------------------------------------------------------------*/
+/*      Plug and Play header definitions                                      */
+/*----------------------------------------------------------------------------*/
+
+/* Structure map for PnP on PowerPC Reference Platform                        */
+/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993.  It        */
+/* (or later versions) is available on Compuserve in the PLUGPLAY area.       */
+/* This code has extensions to that specification, namely new short and       */
+/* long tag types for platform dependent information                          */
+
+/* Warning: LE notation used throughout this file                             */
+
+/* For enum's: if given in hex then they are bit significant, i.e.            */
+/* only one bit is on for each enum                                           */
+
+#ifndef _PNP_
+#define _PNP_
+
+#ifndef __ASSEMBLY__
+#define MAX_MEM_REGISTERS 9
+#define MAX_IO_PORTS 20
+#define MAX_IRQS 7
+/*#define MAX_DMA_CHANNELS 7*/
+
+/* Interrupt controllers */
+
+#define PNPinterrupt0 "PNP0000"      /* AT Interrupt Controller               */
+#define PNPinterrupt1 "PNP0001"      /* EISA Interrupt Controller             */
+#define PNPinterrupt2 "PNP0002"      /* MCA Interrupt Controller              */
+#define PNPinterrupt3 "PNP0003"      /* APIC                                  */
+#define PNPExtInt     "IBM000D"      /* PowerPC Extended Interrupt Controller */
+
+/* Timers */
+
+#define PNPtimer0     "PNP0100"      /* AT Timer                              */
+#define PNPtimer1     "PNP0101"      /* EISA Timer                            */
+#define PNPtimer2     "PNP0102"      /* MCA Timer                             */
+
+/* DMA controllers */
+
+#define PNPdma0       "PNP0200"      /* AT DMA Controller                     */
+#define PNPdma1       "PNP0201"      /* EISA DMA Controller                   */
+#define PNPdma2       "PNP0202"      /* MCA DMA Controller                    */
+
+/* start of August 15, 1994 additions */
+/* CMOS */
+#define PNPCMOS       "IBM0009"      /* CMOS                                  */
+
+/* L2 Cache */
+#define PNPL2         "IBM0007"      /* L2 Cache                              */
+
+/* NVRAM */
+#define PNPNVRAM      "IBM0008"      /* NVRAM                                 */
+
+/* Power Management */
+#define PNPPM         "IBM0005"      /* Power Management                      */
+/* end of August 15, 1994 additions */
+
+/* Keyboards */
+
+#define PNPkeyboard0  "PNP0300"      /* IBM PC/XT KB Cntlr (83 key, no mouse) */
+#define PNPkeyboard1  "PNP0301"      /* Olivetti ICO (102 key)                */
+#define PNPkeyboard2  "PNP0302"      /* IBM PC/AT KB Cntlr (84 key)           */
+#define PNPkeyboard3  "PNP0303"      /* IBM Enhanced (101/2 key, PS/2 mouse)  */
+#define PNPkeyboard4  "PNP0304"      /* Nokia 1050 KB Cntlr                   */
+#define PNPkeyboard5  "PNP0305"      /* Nokia 9140 KB Cntlr                   */
+#define PNPkeyboard6  "PNP0306"      /* Standard Japanese KB Cntlr            */
+#define PNPkeyboard7  "PNP0307"      /* Microsoft Windows (R) KB Cntlr        */
+
+/* Parallel port controllers */
+
+#define PNPparallel0 "PNP0400"       /* Standard LPT Parallel Port            */
+#define PNPparallel1 "PNP0401"       /* ECP Parallel Port                     */
+#define PNPepp       "IBM001C"       /* EPP Parallel Port                     */
+
+/* Serial port controllers */
+
+#define PNPserial0   "PNP0500"       /* Standard PC Serial port               */
+#define PNPSerial1   "PNP0501"       /* 16550A Compatible Serial port         */
+
+/* Disk controllers */
+
+#define PNPdisk0     "PNP0600"       /* Generic ESDI/IDE/ATA Compat HD Cntlr  */
+#define PNPdisk1     "PNP0601"       /* Plus Hardcard II                      */
+#define PNPdisk2     "PNP0602"       /* Plus Hardcard IIXL/EZ                 */
+
+/* Diskette controllers */
+
+#define PNPdiskette0 "PNP0700"       /* PC Standard Floppy Disk Controller    */
+
+/* Display controllers */
+
+#define PNPdisplay0  "PNP0900"       /* VGA Compatible                        */
+#define PNPdisplay1  "PNP0901"       /* Video Seven VGA                       */
+#define PNPdisplay2  "PNP0902"       /* 8514/A Compatible                     */
+#define PNPdisplay3  "PNP0903"       /* Trident VGA                           */
+#define PNPdisplay4  "PNP0904"       /* Cirrus Logic Laptop VGA               */
+#define PNPdisplay5  "PNP0905"       /* Cirrus Logic VGA                      */
+#define PNPdisplay6  "PNP0906"       /* Tseng ET4000 or ET4000/W32            */
+#define PNPdisplay7  "PNP0907"       /* Western Digital VGA                   */
+#define PNPdisplay8  "PNP0908"       /* Western Digital Laptop VGA            */
+#define PNPdisplay9  "PNP0909"       /* S3                                    */
+#define PNPdisplayA  "PNP090A"       /* ATI Ultra Pro/Plus (Mach 32)          */
+#define PNPdisplayB  "PNP090B"       /* ATI Ultra (Mach 8)                    */
+#define PNPdisplayC  "PNP090C"       /* XGA Compatible                        */
+#define PNPdisplayD  "PNP090D"       /* ATI VGA Wonder                        */
+#define PNPdisplayE  "PNP090E"       /* Weitek P9000 Graphics Adapter         */
+#define PNPdisplayF  "PNP090F"       /* Oak Technology VGA                    */
+
+/* Peripheral busses */
+
+#define PNPbuses0    "PNP0A00"       /* ISA Bus                               */
+#define PNPbuses1    "PNP0A01"       /* EISA Bus                              */
+#define PNPbuses2    "PNP0A02"       /* MCA Bus                               */
+#define PNPbuses3    "PNP0A03"       /* PCI Bus                               */
+#define PNPbuses4    "PNP0A04"       /* VESA/VL Bus                           */
+
+/* RTC, BIOS, planar devices */
+
+#define PNPspeaker0  "PNP0800"       /* AT Style Speaker Sound                */
+#define PNPrtc0      "PNP0B00"       /* AT RTC                                */
+#define PNPpnpbios0  "PNP0C00"       /* PNP BIOS (only created by root enum)  */
+#define PNPpnpbios1  "PNP0C01"       /* System Board Memory Device            */
+#define PNPpnpbios2  "PNP0C02"       /* Math Coprocessor                      */
+#define PNPpnpbios3  "PNP0C03"       /* PNP BIOS Event Notification Interrupt */
+
+/* PCMCIA controller */
+
+#define PNPpcmcia0   "PNP0E00"       /* Intel 82365 Compatible PCMCIA Cntlr   */
+
+/* Mice */
+
+#define PNPmouse0    "PNP0F00"       /* Microsoft Bus Mouse                   */
+#define PNPmouse1    "PNP0F01"       /* Microsoft Serial Mouse                */
+#define PNPmouse2    "PNP0F02"       /* Microsoft Inport Mouse                */
+#define PNPmouse3    "PNP0F03"       /* Microsoft PS/2 Mouse                  */
+#define PNPmouse4    "PNP0F04"       /* Mousesystems Mouse                    */
+#define PNPmouse5    "PNP0F05"       /* Mousesystems 3 Button Mouse - COM2    */
+#define PNPmouse6    "PNP0F06"       /* Genius Mouse - COM1                   */
+#define PNPmouse7    "PNP0F07"       /* Genius Mouse - COM2                   */
+#define PNPmouse8    "PNP0F08"       /* Logitech Serial Mouse                 */
+#define PNPmouse9    "PNP0F09"       /* Microsoft Ballpoint Serial Mouse      */
+#define PNPmouseA    "PNP0F0A"       /* Microsoft PNP Mouse                   */
+#define PNPmouseB    "PNP0F0B"       /* Microsoft PNP Ballpoint Mouse         */
+
+/* Modems */
+
+#define PNPmodem0    "PNP9000"       /* Specific IDs TBD                      */
+
+/* Network controllers */
+
+#define PNPnetworkC9 "PNP80C9"       /* IBM Token Ring                        */
+#define PNPnetworkCA "PNP80CA"       /* IBM Token Ring II                     */
+#define PNPnetworkCB "PNP80CB"       /* IBM Token Ring II/Short               */
+#define PNPnetworkCC "PNP80CC"       /* IBM Token Ring 4/16Mbs                */
+#define PNPnetwork27 "PNP8327"       /* IBM Token Ring (All types)            */
+#define PNPnetworket "IBM0010"       /* IBM Ethernet used by Power PC         */
+#define PNPneteisaet "IBM2001"       /* IBM Ethernet EISA adapter             */
+#define PNPAMD79C970 "IBM0016"       /* AMD 79C970 (PCI Ethernet)             */
+
+/* SCSI controllers */
+
+#define PNPscsi0     "PNPA000"       /* Adaptec 154x Compatible SCSI Cntlr    */
+#define PNPscsi1     "PNPA001"       /* Adaptec 174x Compatible SCSI Cntlr    */
+#define PNPscsi2     "PNPA002"       /* Future Domain 16-700 Compat SCSI Cntlr*/
+#define PNPscsi3     "PNPA003"       /* Panasonic CDROM Adapter (SBPro/SB16)  */
+#define PNPscsiF     "IBM000F"       /* NCR 810 SCSI Controller               */
+#define PNPscsi825   "IBM001B"       /* NCR 825 SCSI Controller               */
+#define PNPscsi875   "IBM0018"       /* NCR 875 SCSI Controller               */
+
+/* Sound/Video, Multimedia */
+
+#define PNPmm0       "PNPB000"       /* Sound Blaster Compatible Sound Device */
+#define PNPmm1       "PNPB001"       /* MS Windows Sound System Compat Device */
+#define PNPmmF       "IBM000E"       /* Crystal CS4231 Audio Device           */
+#define PNPv7310     "IBM0015"       /* ASCII V7310 Video Capture Device      */
+#define PNPmm4232    "IBM0017"       /* Crystal CS4232 Audio Device           */
+#define PNPpmsyn     "IBM001D"       /* YMF 289B chip (Yamaha)                */
+#define PNPgp4232    "IBM0012"       /* Crystal CS4232 Game Port              */
+#define PNPmidi4232  "IBM0013"       /* Crystal CS4232 MIDI                   */
+
+/* Operator Panel */
+#define PNPopctl     "IBM000B"       /* Operator's panel                      */
+
+/* Service Processor */
+#define PNPsp        "IBM0011"       /* IBM Service Processor                 */
+#define PNPLTsp      "IBM001E"       /* Lightning/Terlingua Support Processor */
+#define PNPLTmsp     "IBM001F"       /* Lightning/Terlingua Mini-SP           */
+
+/* Memory Controller */
+#define PNPmemctl    "IBM000A"       /* Memory controller                     */
+
+/* Graphics Assist */
+#define PNPg_assist  "IBM0014"       /* Graphics Assist                       */
+
+/* Miscellaneous Device Controllers */
+#define PNPtablet    "IBM0019"       /* IBM Tablet Controller                 */
+
+/* PNP Packet Handles */
+
+#define S1_Packet                0x0A   /* Version resource                   */
+#define S2_Packet                0x15   /* Logical DEVID (without flags)      */
+#define S2_Packet_flags          0x16   /* Logical DEVID (with flags)         */
+#define S3_Packet                0x1C   /* Compatible device ID               */
+#define S4_Packet                0x22   /* IRQ resource (without flags)       */
+#define S4_Packet_flags          0x23   /* IRQ resource (with flags)          */
+#define S5_Packet                0x2A   /* DMA resource                       */
+#define S6_Packet                0x30   /* Depend funct start (w/o priority)  */
+#define S6_Packet_priority       0x31   /* Depend funct start (w/ priority)   */
+#define S7_Packet                0x38   /* Depend funct end                   */
+#define S8_Packet                0x47   /* I/O port resource (w/o fixed loc)  */
+#define S9_Packet_fixed          0x4B   /* I/O port resource (w/ fixed loc)   */
+#define S14_Packet               0x71   /* Vendor defined                     */
+#define S15_Packet               0x78   /* End of resource (w/o checksum)     */
+#define S15_Packet_checksum      0x79   /* End of resource (w/ checksum)      */
+#define L1_Packet                0x81   /* Memory range                       */
+#define L1_Shadow                0x20   /* Memory is shadowable               */
+#define L1_32bit_mem             0x18   /* 32-bit memory only                 */
+#define L1_8_16bit_mem           0x10   /* 8- and 16-bit supported            */
+#define L1_Decode_Hi             0x04   /* decode supports high address       */
+#define L1_Cache                 0x02   /* read cacheable, write-through      */
+#define L1_Writeable             0x01   /* Memory is writeable                */
+#define L2_Packet                0x82   /* ANSI ID string                     */
+#define L3_Packet                0x83   /* Unicode ID string                  */
+#define L4_Packet                0x84   /* Vendor defined                     */
+#define L5_Packet                0x85   /* Large I/O                          */
+#define L6_Packet                0x86   /* 32-bit Fixed Loc Mem Range Desc    */
+#define END_TAG                  0x78   /* End of resource                    */
+#define DF_START_TAG             0x30   /* Dependent function start           */
+#define DF_START_TAG_priority    0x31   /* Dependent function start           */
+#define DF_END_TAG               0x38   /* Dependent function end             */
+#define SUBOPTIMAL_CONFIGURATION 0x2    /* Priority byte sub optimal config   */
+
+/* Device Base Type Codes */
+
+typedef enum _PnP_BASE_TYPE {
+  Reserved = 0,
+  MassStorageDevice = 1,
+  NetworkInterfaceController = 2,
+  DisplayController = 3,
+  MultimediaController = 4,
+  MemoryController = 5,
+  BridgeController = 6,
+  CommunicationsDevice = 7,
+  SystemPeripheral = 8,
+  InputDevice = 9,
+  ServiceProcessor = 0x0A,              /* 11/2/95                            */
+  } PnP_BASE_TYPE;
+
+/* Device Sub Type Codes */
+
+typedef enum _PnP_SUB_TYPE {
+  SCSIController = 0,
+  IDEController = 1,
+  FloppyController = 2,
+  IPIController = 3,
+  OtherMassStorageController = 0x80,
+
+  EthernetController = 0,
+  TokenRingController = 1,
+  FDDIController = 2,
+  OtherNetworkController = 0x80,
+
+  VGAController= 0,
+  SVGAController= 1,
+  XGAController= 2,
+  OtherDisplayController = 0x80,
+
+  VideoController = 0,
+  AudioController = 1,
+  OtherMultimediaController = 0x80,
+
+  RAM = 0,
+  FLASH = 1,
+  OtherMemoryDevice = 0x80,
+
+  HostProcessorBridge = 0,
+  ISABridge = 1,
+  EISABridge = 2,
+  MicroChannelBridge = 3,
+  PCIBridge = 4,
+  PCMCIABridge = 5,
+  VMEBridge = 6,
+  OtherBridgeDevice = 0x80,
+
+  RS232Device = 0,
+  ATCompatibleParallelPort = 1,
+  OtherCommunicationsDevice = 0x80,
+
+  ProgrammableInterruptController = 0,
+  DMAController = 1,
+  SystemTimer = 2,
+  RealTimeClock = 3,
+  L2Cache = 4,
+  NVRAM = 5,
+  PowerManagement = 6,
+  CMOS = 7,
+  OperatorPanel = 8,
+  ServiceProcessorClass1 = 9,
+  ServiceProcessorClass2 = 0xA,
+  ServiceProcessorClass3 = 0xB,
+  GraphicAssist = 0xC,
+  SystemPlanar = 0xF,                   /* 10/5/95                            */
+  OtherSystemPeripheral = 0x80,
+
+  KeyboardController = 0,
+  Digitizer = 1,
+  MouseController = 2,
+  TabletController = 3,                 /* 10/27/95                           */
+  OtherInputController = 0x80,
+
+  GeneralMemoryController = 0,
+  } PnP_SUB_TYPE;
+
+/* Device Interface Type Codes */
+
+typedef enum _PnP_INTERFACE {
+  General = 0,
+  GeneralSCSI = 0,
+  GeneralIDE = 0,
+  ATACompatible = 1,
+
+  GeneralFloppy = 0,
+  Compatible765 = 1,
+  NS398_Floppy = 2,                     /* NS Super I/O wired to use index
+					   register at port 398 and data
+					   register at port 399               */
+  NS26E_Floppy = 3,                     /* Ports 26E and 26F                  */
+  NS15C_Floppy = 4,                     /* Ports 15C and 15D                  */
+  NS2E_Floppy = 5,                      /* Ports 2E and 2F                    */
+  CHRP_Floppy = 6,                      /* CHRP Floppy in PR*P system         */
+
+  GeneralIPI = 0,
+
+  GeneralEther = 0,
+  GeneralToken = 0,
+  GeneralFDDI = 0,
+
+  GeneralVGA = 0,
+  GeneralSVGA = 0,
+  GeneralXGA = 0,
+
+  GeneralVideo = 0,
+  GeneralAudio = 0,
+  CS4232Audio = 1,                      /* CS 4232 Plug 'n Play Configured    */
+
+  GeneralRAM = 0,
+  GeneralFLASH = 0,
+  PCIMemoryController = 0,              /* PCI Config Method                  */
+  RS6KMemoryController = 1,             /* RS6K Config Method                 */
+
+  GeneralHostBridge = 0,
+  GeneralISABridge = 0,
+  GeneralEISABridge = 0,
+  GeneralMCABridge = 0,
+  GeneralPCIBridge = 0,
+  PCIBridgeDirect = 0,
+  PCIBridgeIndirect = 1,
+  PCIBridgeRS6K = 2,
+  GeneralPCMCIABridge = 0,
+  GeneralVMEBridge = 0,
+
+  GeneralRS232 = 0,
+  COMx = 1,
+  Compatible16450 = 2,
+  Compatible16550 = 3,
+  NS398SerPort = 4,                     /* NS Super I/O wired to use index
+					   register at port 398 and data
+					   register at port 399               */
+  NS26ESerPort = 5,                     /* Ports 26E and 26F                  */
+  NS15CSerPort = 6,                     /* Ports 15C and 15D                  */
+  NS2ESerPort = 7,                      /* Ports 2E and 2F                    */
+
+  GeneralParPort = 0,
+  LPTx = 1,
+  NS398ParPort = 2,                     /* NS Super I/O wired to use index
+					   register at port 398 and data
+					   register at port 399               */
+  NS26EParPort = 3,                     /* Ports 26E and 26F                  */
+  NS15CParPort = 4,                     /* Ports 15C and 15D                  */
+  NS2EParPort = 5,                      /* Ports 2E and 2F                    */
+
+  GeneralPIC = 0,
+  ISA_PIC = 1,
+  EISA_PIC = 2,
+  MPIC = 3,
+  RS6K_PIC = 4,
+
+  GeneralDMA = 0,
+  ISA_DMA = 1,
+  EISA_DMA = 2,
+
+  GeneralTimer = 0,
+  ISA_Timer = 1,
+  EISA_Timer = 2,
+  GeneralRTC = 0,
+  ISA_RTC = 1,
+
+  StoreThruOnly = 1,
+  StoreInEnabled = 2,
+  RS6KL2Cache = 3,
+
+  IndirectNVRAM = 0,                    /* Indirectly addressed               */
+  DirectNVRAM = 1,                      /* Memory Mapped                      */
+  IndirectNVRAM24 = 2,                  /* Indirectly addressed - 24 bit      */
+
+  GeneralPowerManagement = 0,
+  EPOWPowerManagement = 1,
+  PowerControl = 2,                    /* d1378 */
+
+  GeneralCMOS = 0,
+
+  GeneralOPPanel = 0,
+  HarddiskLight = 1,
+  CDROMLight = 2,
+  PowerLight = 3,
+  KeyLock = 4,
+  ANDisplay = 5,                        /* AlphaNumeric Display               */
+  SystemStatusLED = 6,                  /* 3 digit 7 segment LED              */
+  CHRP_SystemStatusLED = 7,             /* CHRP LEDs in PR*P system           */
+
+  GeneralServiceProcessor = 0,
+
+  TransferData = 1,
+  IGMC32 = 2,
+  IGMC64 = 3,
+
+  GeneralSystemPlanar = 0,              /* 10/5/95                            */
+
+  } PnP_INTERFACE;
+
+/* PnP resources */
+
+/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */
+
+typedef struct _SERIAL_ID {
+  unsigned char VendorID0;              /*    Bit(7)=0                        */
+					/*    Bits(6:2)=1st character in      */
+					/*       compressed ASCII             */
+					/*    Bits(1:0)=2nd character in      */
+					/*       compressed ASCII bits(4:3)   */
+  unsigned char VendorID1;              /*    Bits(7:5)=2nd character in      */
+					/*       compressed ASCII bits(2:0)   */
+					/*    Bits(4:0)=3rd character in      */
+					/*       compressed ASCII             */
+  unsigned char VendorID2;              /* Product number - vendor assigned   */
+  unsigned char VendorID3;              /* Product number - vendor assigned   */
+
+/* Serial number is to provide uniqueness if more than one board of same      */
+/* type is in system.  Must be "FFFFFFFF" if feature not supported.           */
+
+  unsigned char Serial0;                /* Unique serial number bits (7:0)    */
+  unsigned char Serial1;                /* Unique serial number bits (15:8)   */
+  unsigned char Serial2;                /* Unique serial number bits (23:16)  */
+  unsigned char Serial3;                /* Unique serial number bits (31:24)  */
+  unsigned char Checksum;
+  } SERIAL_ID;
+
+typedef enum _PnPItemName {
+  Unused = 0,
+  PnPVersion = 1,
+  LogicalDevice = 2,
+  CompatibleDevice = 3,
+  IRQFormat = 4,
+  DMAFormat = 5,
+  StartDepFunc = 6,
+  EndDepFunc = 7,
+  IOPort = 8,
+  FixedIOPort = 9,
+  Res1 = 10,
+  Res2 = 11,
+  Res3 = 12,
+  SmallVendorItem = 14,
+  EndTag = 15,
+  MemoryRange = 1,
+  ANSIIdentifier = 2,
+  UnicodeIdentifier = 3,
+  LargeVendorItem = 4,
+  MemoryRange32 = 5,
+  MemoryRangeFixed32 = 6,
+  } PnPItemName;
+
+/* Define a bunch of access functions for the bits in the tag field */
+
+/* Tag type - 0 = small; 1 = large */
+#define tag_type(t) (((t) & 0x80)>>7)
+#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7))
+
+/* Small item name is 4 bits - one of PnPItemName enum above */
+#define tag_small_item_name(t) (((t) & 0x78)>>3)
+#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3))
+
+/* Small item count is 3 bits - count of further bytes in packet */
+#define tag_small_count(t) ((t) & 0x07)
+#define set_tag_count(t,v) (t = (t & 0x78) | (v))
+
+/* Large item name is 7 bits - one of PnPItemName enum above */
+#define tag_large_item_name(t) ((t) & 0x7f)
+#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v))
+
+/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */
+
+typedef union _PnP_TAG_PACKET {
+  struct _S1_Pack{                      /* VERSION PACKET                     */
+    unsigned char Tag;                  /* small tag = 0x0a                   */
+    unsigned char Version[2];           /* PnP version, Vendor version        */
+    } S1_Pack;
+
+  struct _S2_Pack{                      /* LOGICAL DEVICE ID PACKET           */
+    unsigned char Tag;                  /* small tag = 0x15 or 0x16           */
+    unsigned char DevId[4];             /* Logical device id                  */
+    unsigned char Flags[2];             /* bit(0) boot device;                */
+					/* bit(7:1) cmd in range x31-x37      */
+					/* bit(7:0) cmd in range x28-x3f (opt)*/
+    } S2_Pack;
+
+  struct _S3_Pack{                      /* COMPATIBLE DEVICE ID PACKET        */
+    unsigned char Tag;                  /* small tag = 0x1c                   */
+    unsigned char CompatId[4];          /* Compatible device id               */
+    } S3_Pack;
+
+  struct _S4_Pack{                      /* IRQ PACKET                         */
+    unsigned char Tag;                  /* small tag = 0x22 or 0x23           */
+    unsigned char IRQMask[2];           /* bit(0) is IRQ0, ...;               */
+					/* bit(0) is IRQ8 ...                 */
+    unsigned char IRQInfo;              /* optional; assume bit(0)=1; else    */
+					/*  bit(0) - high true edge sensitive */
+					/*  bit(1) - low true edge sensitive  */
+					/*  bit(2) - high true level sensitive*/
+					/*  bit(3) - low true level sensitive */
+					/*  bit(7:4) - must be 0              */
+    } S4_Pack;
+
+  struct _S5_Pack{                      /* DMA PACKET                         */
+    unsigned char Tag;                  /* small tag = 0x2a                   */
+    unsigned char DMAMask;              /* bit(0) is channel 0 ...            */
+    unsigned char DMAInfo;
+    } S5_Pack;
+
+  struct _S6_Pack{                      /* START DEPENDENT FUNCTION PACKET    */
+    unsigned char Tag;                  /* small tag = 0x30 or 0x31           */
+    unsigned char Priority;             /* Optional; if missing then x01; else*/
+					/*  x00 = best possible               */
+					/*  x01 = acceptible                  */
+					/*  x02 = sub-optimal but functional  */
+    } S6_Pack;
+
+  struct _S7_Pack{                      /* END DEPENDENT FUNCTION PACKET      */
+    unsigned char Tag;                  /* small tag = 0x38                   */
+    } S7_Pack;
+
+  struct _S8_Pack{                      /* VARIABLE I/O PORT PACKET           */
+    unsigned char Tag;                  /* small tag x47                      */
+    unsigned char IOInfo;               /* x0  = decode only bits(9:0);       */
+#define  ISAAddr16bit         0x01      /* x01 = decode bits(15:0)            */
+    unsigned char RangeMin[2];          /* Min base address                   */
+    unsigned char RangeMax[2];          /* Max base address                   */
+    unsigned char IOAlign;              /* base alignmt, incr in 1B blocks    */
+    unsigned char IONum;                /* number of contiguous I/O ports     */
+    } S8_Pack;
+
+  struct _S9_Pack{                      /* FIXED I/O PORT PACKET              */
+    unsigned char Tag;                  /* small tag = 0x4b                   */
+    unsigned char Range[2];             /* base address 10 bits               */
+    unsigned char IONum;                /* number of contiguous I/O ports     */
+    } S9_Pack;
+
+  struct _S14_Pack{                     /* VENDOR DEFINED PACKET              */
+    unsigned char Tag;                  /* small tag = 0x7m m = 1-7           */
+    union _S14_Data{
+      unsigned char Data[7];            /* Vendor defined                     */
+      struct _S14_PPCPack{              /* Pr*p s14 pack                      */
+	 unsigned char Type;            /* 00=non-IBM                         */
+	 unsigned char PPCData[6];      /* Vendor defined                     */
+	} S14_PPCPack;
+      } S14_Data;
+    } S14_Pack;
+
+  struct _S15_Pack{                     /* END PACKET                         */
+    unsigned char Tag;                  /* small tag = 0x78 or 0x79           */
+    unsigned char Check;                /* optional - checksum                */
+    } S15_Pack;
+
+  struct _L1_Pack{                      /* MEMORY RANGE PACKET                */
+    unsigned char Tag;                  /* large tag = 0x81                   */
+    unsigned char Count0;               /* x09                                */
+    unsigned char Count1;               /* x00                                */
+    unsigned char Data[9];              /* a variable array of bytes,         */
+					/* count in tag                       */
+    } L1_Pack;
+
+  struct _L2_Pack{                      /* ANSI ID STRING PACKET              */
+    unsigned char Tag;                  /* large tag = 0x82                   */
+    unsigned char Count0;               /* Length of string                   */
+    unsigned char Count1;
+    unsigned char Identifier[1];        /* a variable array of bytes,         */
+					/* count in tag                       */
+    } L2_Pack;
+
+  struct _L3_Pack{                      /* UNICODE ID STRING PACKET           */
+    unsigned char Tag;                  /* large tag = 0x83                   */
+    unsigned char Count0;               /* Length + 2 of string               */
+    unsigned char Count1;
+    unsigned char Country0;             /* TBD                                */
+    unsigned char Country1;             /* TBD                                */
+    unsigned char Identifier[1];        /* a variable array of bytes,         */
+					/* count in tag                       */
+    } L3_Pack;
+
+  struct _L4_Pack{                      /* VENDOR DEFINED PACKET              */
+    unsigned char Tag;                  /* large tag = 0x84                   */
+    unsigned char Count0;
+    unsigned char Count1;
+    union _L4_Data{
+      unsigned char Data[1];            /* a variable array of bytes,         */
+					/* count in tag                       */
+      struct _L4_PPCPack{               /* Pr*p L4 packet                     */
+	 unsigned char Type;            /* 00=non-IBM                         */
+	 unsigned char PPCData[1];      /* a variable array of bytes,         */
+					/* count in tag                       */
+	} L4_PPCPack;
+      } L4_Data;
+    } L4_Pack;
+
+  struct _L5_Pack{
+    unsigned char Tag;                  /* large tag = 0x85                   */
+    unsigned char Count0;               /* Count = 17                         */
+    unsigned char Count1;
+    unsigned char Data[17];
+    } L5_Pack;
+
+  struct _L6_Pack{
+    unsigned char Tag;                  /* large tag = 0x86                   */
+    unsigned char Count0;               /* Count = 9                          */
+    unsigned char Count1;
+    unsigned char Data[9];
+    } L6_Pack;
+
+  } PnP_TAG_PACKET;
+
+#endif /* __ASSEMBLY__ */
+#endif  /* ndef _PNP_ */
diff --git a/include/asm-ppc/posix_types.h b/include/asm-ppc/posix_types.h
new file mode 100755
index 0000000..9170728
--- /dev/null
+++ b/include/asm-ppc/posix_types.h
@@ -0,0 +1,109 @@
+#ifndef _PPC_POSIX_TYPES_H
+#define _PPC_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned int	__kernel_dev_t;
+typedef unsigned int	__kernel_ino_t;
+typedef unsigned int	__kernel_mode_t;
+typedef unsigned short	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef unsigned int	__kernel_uid_t;
+typedef unsigned int	__kernel_gid_t;
+typedef unsigned int	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef long		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef short             __kernel_ipc_pid_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned int	__kernel_old_uid_t;
+typedef unsigned int	__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long	__kernel_loff_t;
+#endif
+
+typedef struct {
+	int	val[2];
+} __kernel_fsid_t;
+
+#ifndef __GNUC__
+
+#define	__FD_SET(d, set)	((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+#define	__FD_CLR(d, set)	((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+#define	__FD_ISSET(d, set)	((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+#define	__FD_ZERO(set)	\
+  ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
+
+#else /* __GNUC__ */
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
+    || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
+/* With GNU C, use inline functions instead so args are evaluated only once: */
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+	unsigned long _tmp = fd / __NFDBITS;
+	unsigned long _rem = fd % __NFDBITS;
+	fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+	unsigned long _tmp = fd / __NFDBITS;
+	unsigned long _rem = fd % __NFDBITS;
+	fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
+{
+	unsigned long _tmp = fd / __NFDBITS;
+	unsigned long _rem = fd % __NFDBITS;
+	return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *p)
+{
+	unsigned int *tmp = (unsigned int *)p->fds_bits;
+	int i;
+
+	if (__builtin_constant_p(__FDSET_LONGS)) {
+		switch (__FDSET_LONGS) {
+			case 8:
+				tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0;
+				tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0;
+				return;
+		}
+	}
+	i = __FDSET_LONGS;
+	while (i) {
+		i--;
+		*tmp = 0;
+		tmp++;
+	}
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* __GNUC__ */
+#endif /* _PPC_POSIX_TYPES_H */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
new file mode 100755
index 0000000..8113783
--- /dev/null
+++ b/include/asm-ppc/processor.h
@@ -0,0 +1,1064 @@
+#ifndef __ASM_PPC_PROCESSOR_H
+#define __ASM_PPC_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#include <linux/config.h>
+
+#include <asm/ptrace.h>
+#include <asm/types.h>
+
+/* Machine State Register (MSR) Fields */
+
+#ifdef CONFIG_PPC64BRIDGE
+#define MSR_SF		(1<<63)
+#define MSR_ISF		(1<<61)
+#endif /* CONFIG_PPC64BRIDGE */
+#define MSR_UCLE        (1<<26)         /* User-mode cache lock enable (e500) */
+#define MSR_VEC		(1<<25)		/* Enable AltiVec(74xx) */
+#define MSR_SPE         (1<<25)         /* Enable SPE(e500) */
+#define MSR_POW		(1<<18)		/* Enable Power Management */
+#define MSR_WE		(1<<18)		/* Wait State Enable */
+#define MSR_TGPR	(1<<17)		/* TLB Update registers in use */
+#define MSR_CE		(1<<17)		/* Critical Interrupt Enable */
+#define MSR_ILE		(1<<16)		/* Interrupt Little Endian */
+#define MSR_EE		(1<<15)		/* External Interrupt Enable */
+#define MSR_PR		(1<<14)		/* Problem State / Privilege Level */
+#define MSR_FP		(1<<13)		/* Floating Point enable */
+#define MSR_ME		(1<<12)		/* Machine Check Enable */
+#define MSR_FE0		(1<<11)		/* Floating Exception mode 0 */
+#define MSR_SE		(1<<10)		/* Single Step */
+#define MSR_DWE         (1<<10)         /* Debug Wait Enable (4xx) */
+#define MSR_UBLE        (1<<10)         /* BTB lock enable (e500) */
+#define MSR_BE		(1<<9)		/* Branch Trace */
+#define MSR_DE		(1<<9) 		/* Debug Exception Enable */
+#define MSR_FE1		(1<<8)		/* Floating Exception mode 1 */
+#define MSR_IP		(1<<6)		/* Exception prefix 0x000/0xFFF */
+#define MSR_IR		(1<<5) 		/* Instruction Relocate */
+#define MSR_IS          (1<<5)          /* Book E Instruction space */
+#define MSR_DR		(1<<4) 		/* Data Relocate */
+#define MSR_DS          (1<<4)          /* Book E Data space */
+#define MSR_PE		(1<<3)		/* Protection Enable */
+#define MSR_PX		(1<<2)		/* Protection Exclusive Mode */
+#define MSR_PMM         (1<<2)          /* Performance monitor mark bit (e500) */
+#define MSR_RI		(1<<1)		/* Recoverable Exception */
+#define MSR_LE		(1<<0) 		/* Little Endian */
+
+#ifdef CONFIG_APUS_FAST_EXCEPT
+#define MSR_		MSR_ME|MSR_IP|MSR_RI
+#else
+#define MSR_		MSR_ME|MSR_RI
+#endif
+#ifndef CONFIG_E500
+#define MSR_KERNEL      MSR_|MSR_IR|MSR_DR
+#else
+#define MSR_KERNEL	MSR_ME
+#endif
+#define MSR_USER	MSR_KERNEL|MSR_PR|MSR_EE
+
+/* Floating Point Status and Control Register (FPSCR) Fields */
+
+#define FPSCR_FX	0x80000000	/* FPU exception summary */
+#define FPSCR_FEX	0x40000000	/* FPU enabled exception summary */
+#define FPSCR_VX	0x20000000	/* Invalid operation summary */
+#define FPSCR_OX	0x10000000	/* Overflow exception summary */
+#define FPSCR_UX	0x08000000	/* Underflow exception summary */
+#define FPSCR_ZX	0x04000000	/* Zero-devide exception summary */
+#define FPSCR_XX	0x02000000	/* Inexact exception summary */
+#define FPSCR_VXSNAN	0x01000000	/* Invalid op for SNaN */
+#define FPSCR_VXISI	0x00800000	/* Invalid op for Inv - Inv */
+#define FPSCR_VXIDI	0x00400000	/* Invalid op for Inv / Inv */
+#define FPSCR_VXZDZ	0x00200000	/* Invalid op for Zero / Zero */
+#define FPSCR_VXIMZ	0x00100000	/* Invalid op for Inv * Zero */
+#define FPSCR_VXVC	0x00080000	/* Invalid op for Compare */
+#define FPSCR_FR	0x00040000	/* Fraction rounded */
+#define FPSCR_FI	0x00020000	/* Fraction inexact */
+#define FPSCR_FPRF	0x0001f000	/* FPU Result Flags */
+#define FPSCR_FPCC	0x0000f000	/* FPU Condition Codes */
+#define FPSCR_VXSOFT	0x00000400	/* Invalid op for software request */
+#define FPSCR_VXSQRT	0x00000200	/* Invalid op for square root */
+#define FPSCR_VXCVI	0x00000100	/* Invalid op for integer convert */
+#define FPSCR_VE	0x00000080	/* Invalid op exception enable */
+#define FPSCR_OE	0x00000040	/* IEEE overflow exception enable */
+#define FPSCR_UE	0x00000020	/* IEEE underflow exception enable */
+#define FPSCR_ZE	0x00000010	/* IEEE zero divide exception enable */
+#define FPSCR_XE	0x00000008	/* FP inexact exception enable */
+#define FPSCR_NI	0x00000004	/* FPU non IEEE-Mode */
+#define FPSCR_RN	0x00000003	/* FPU rounding control */
+
+/* Special Purpose Registers (SPRNs)*/
+
+#define SPRN_CDBCR	0x3D7	/* Cache Debug Control Register */
+#define SPRN_CTR	0x009	/* Count Register */
+#define SPRN_DABR	0x3F5	/* Data Address Breakpoint Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_DAC1	0x3F6	/* Data Address Compare 1 */
+#define SPRN_DAC2	0x3F7	/* Data Address Compare 2 */
+#else
+#define SPRN_DAC1       0x13C   /* Book E Data Address Compare 1 */
+#define SPRN_DAC2       0x13D   /* Book E Data Address Compare 2 */
+#endif  /* CONFIG_BOOKE */
+#define SPRN_DAR	0x013	/* Data Address Register */
+#define SPRN_DBAT0L	0x219	/* Data BAT 0 Lower Register */
+#define SPRN_DBAT0U	0x218	/* Data BAT 0 Upper Register */
+#define SPRN_DBAT1L	0x21B	/* Data BAT 1 Lower Register */
+#define SPRN_DBAT1U	0x21A	/* Data BAT 1 Upper Register */
+#define SPRN_DBAT2L	0x21D	/* Data BAT 2 Lower Register */
+#define SPRN_DBAT2U	0x21C	/* Data BAT 2 Upper Register */
+#define SPRN_DBAT3L	0x21F	/* Data BAT 3 Lower Register */
+#define SPRN_DBAT3U	0x21E	/* Data BAT 3 Upper Register */
+#define SPRN_DBAT4L	0x239   /* Data BAT 4 Lower Register */
+#define SPRN_DBAT4U	0x238   /* Data BAT 4 Upper Register */
+#define SPRN_DBAT5L	0x23B   /* Data BAT 5 Lower Register */
+#define SPRN_DBAT5U	0x23A   /* Data BAT 5 Upper Register */
+#define SPRN_DBAT6L	0x23D   /* Data BAT 6 Lower Register */
+#define SPRN_DBAT6U	0x23C   /* Data BAT 6 Upper Register */
+#define SPRN_DBAT7L	0x23F   /* Data BAT 7 Lower Register */
+#define SPRN_DBAT7U	0x23E   /* Data BAT 7 Lower Register */
+#define SPRN_DBCR	0x3F2	/* Debug Control Regsiter */
+#define   DBCR_EDM	0x80000000
+#define   DBCR_IDM	0x40000000
+#define   DBCR_RST(x)	(((x) & 0x3) << 28)
+#define     DBCR_RST_NONE       	0
+#define     DBCR_RST_CORE       	1
+#define     DBCR_RST_CHIP       	2
+#define     DBCR_RST_SYSTEM		3
+#define   DBCR_IC	0x08000000	/* Instruction Completion Debug Evnt */
+#define   DBCR_BT	0x04000000	/* Branch Taken Debug Event */
+#define   DBCR_EDE	0x02000000	/* Exception Debug Event */
+#define   DBCR_TDE	0x01000000	/* TRAP Debug Event */
+#define   DBCR_FER	0x00F80000	/* First Events Remaining Mask */
+#define   DBCR_FT	0x00040000	/* Freeze Timers on Debug Event */
+#define   DBCR_IA1	0x00020000	/* Instr. Addr. Compare 1 Enable */
+#define   DBCR_IA2	0x00010000	/* Instr. Addr. Compare 2 Enable */
+#define   DBCR_D1R	0x00008000	/* Data Addr. Compare 1 Read Enable */
+#define   DBCR_D1W	0x00004000	/* Data Addr. Compare 1 Write Enable */
+#define   DBCR_D1S(x)	(((x) & 0x3) << 12)	/* Data Adrr. Compare 1 Size */
+#define     DAC_BYTE	0
+#define     DAC_HALF	1
+#define     DAC_WORD	2
+#define     DAC_QUAD	3
+#define   DBCR_D2R	0x00000800	/* Data Addr. Compare 2 Read Enable */
+#define   DBCR_D2W	0x00000400	/* Data Addr. Compare 2 Write Enable */
+#define   DBCR_D2S(x)	(((x) & 0x3) << 8)	/* Data Addr. Compare 2 Size */
+#define   DBCR_SBT	0x00000040	/* Second Branch Taken Debug Event */
+#define   DBCR_SED	0x00000020	/* Second Exception Debug Event */
+#define   DBCR_STD	0x00000010	/* Second Trap Debug Event */
+#define   DBCR_SIA	0x00000008	/* Second IAC Enable */
+#define   DBCR_SDA	0x00000004	/* Second DAC Enable */
+#define   DBCR_JOI	0x00000002	/* JTAG Serial Outbound Int. Enable */
+#define   DBCR_JII	0x00000001	/* JTAG Serial Inbound Int. Enable */
+#ifndef CONFIG_BOOKE
+#define SPRN_DBCR0      0x3F2           /* Debug Control Register 0 */
+#else
+#define SPRN_DBCR0      0x134           /* Book E Debug Control Register 0 */
+#endif /* CONFIG_BOOKE */
+#ifndef CONFIG_BOOKE
+#define SPRN_DBCR1	0x3BD	/* Debug Control Register 1 */
+#define SPRN_DBSR	0x3F0	/* Debug Status Register */
+#else
+#define SPRN_DBCR1      0x135           /* Book E Debug Control Register 1 */
+#define SPRN_DBSR       0x130           /* Book E Debug Status Register */
+#define   DBSR_IC           0x08000000  /* Book E Instruction Completion  */
+#define   DBSR_TIE          0x01000000  /* Book E Trap Instruction Event */
+#endif /* CONFIG_BOOKE */
+#define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
+#define   DCCR_NOCACHE		0	/* Noncacheable */
+#define   DCCR_CACHE		1	/* Cacheable */
+#define SPRN_DCMP	0x3D1	/* Data TLB Compare Register */
+#define SPRN_DCWR	0x3BA	/* Data Cache Write-thru Register */
+#define   DCWR_COPY		0	/* Copy-back */
+#define   DCWR_WRITE		1	/* Write-through */
+#ifndef CONFIG_BOOKE
+#define SPRN_DEAR	0x3D5	/* Data Error Address Register */
+#else
+#define SPRN_DEAR       0x03D   /* Book E Data Error Address Register */
+#endif /* CONFIG_BOOKE */
+#define SPRN_DEC	0x016	/* Decrement Register */
+#define SPRN_DMISS	0x3D0	/* Data TLB Miss Register */
+#define SPRN_DSISR	0x012	/* Data Storage Interrupt Status Register */
+#define SPRN_EAR	0x11A	/* External Address Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_ESR	0x3D4	/* Exception Syndrome Register */
+#else
+#define SPRN_ESR        0x03E           /* Book E Exception Syndrome Register */
+#endif /* CONFIG_BOOKE */
+#define   ESR_IMCP	0x80000000	/* Instr. Machine Check - Protection */
+#define   ESR_IMCN	0x40000000	/* Instr. Machine Check - Non-config */
+#define   ESR_IMCB	0x20000000	/* Instr. Machine Check - Bus error */
+#define   ESR_IMCT	0x10000000	/* Instr. Machine Check - Timeout */
+#define   ESR_PIL	0x08000000	/* Program Exception - Illegal */
+#define   ESR_PPR	0x04000000	/* Program Exception - Priveleged */
+#define   ESR_PTR	0x02000000	/* Program Exception - Trap */
+#define   ESR_DST	0x00800000	/* Storage Exception - Data miss */
+#define   ESR_DIZ	0x00400000	/* Storage Exception - Zone fault */
+#define SPRN_EVPR	0x3D6	/* Exception Vector Prefix Register */
+#define SPRN_HASH1	0x3D2	/* Primary Hash Address Register */
+#define SPRN_HASH2	0x3D3	/* Secondary Hash Address Resgister */
+#define SPRN_HID0	0x3F0	/* Hardware Implementation Register 0 */
+
+#define HID0_ICE_SHIFT		15
+#define HID0_DCE_SHIFT		14
+#define HID0_DLOCK_SHIFT	12
+
+#define   HID0_EMCP	(1<<31)		/* Enable Machine Check pin */
+#define   HID0_EBA	(1<<29)		/* Enable Bus Address Parity */
+#define   HID0_EBD	(1<<28)		/* Enable Bus Data Parity */
+#define   HID0_SBCLK	(1<<27)
+#define   HID0_EICE	(1<<26)
+#define   HID0_ECLK	(1<<25)
+#define   HID0_PAR	(1<<24)
+#define   HID0_DOZE	(1<<23)
+#define   HID0_NAP	(1<<22)
+#define   HID0_SLEEP	(1<<21)
+#define   HID0_DPM	(1<<20)
+#define   HID0_ICE	(1<<HID0_ICE_SHIFT)	/* Instruction Cache Enable */
+#define   HID0_DCE	(1<<HID0_DCE_SHIFT)	/* Data Cache Enable */
+#define   HID0_ILOCK	(1<<13)		/* Instruction Cache Lock */
+#define   HID0_DLOCK	(1<<HID0_DLOCK_SHIFT)	/* Data Cache Lock */
+#define   HID0_ICFI	(1<<11)		/* Instr. Cache Flash Invalidate */
+#define   HID0_DCFI	(1<<10)		/* Data Cache Flash Invalidate */
+#define   HID0_DCI	HID0_DCFI
+#define   HID0_SPD	(1<<9)		/* Speculative disable */
+#define   HID0_SGE	(1<<7)		/* Store Gathering Enable */
+#define   HID0_SIED	HID_SGE		/* Serial Instr. Execution [Disable] */
+#define   HID0_DCFA	(1<<6)		/* Data Cache Flush Assist */
+#define   HID0_BTIC	(1<<5)		/* Branch Target Instruction Cache Enable */
+#define   HID0_ABE	(1<<3)		/* Address Broadcast Enable */
+#define   HID0_BHTE	(1<<2)		/* Branch History Table Enable */
+#define   HID0_BTCD	(1<<1)		/* Branch target cache disable */
+#define SPRN_HID1	0x3F1	/* Hardware Implementation Register 1 */
+#define SPRN_IABR	0x3F2	/* Instruction Address Breakpoint Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_IAC1	0x3F4	/* Instruction Address Compare 1 */
+#define SPRN_IAC2	0x3F5	/* Instruction Address Compare 2 */
+#else
+#define SPRN_IAC1       0x138   /* Book E Instruction Address Compare 1 */
+#define SPRN_IAC2       0x139   /* Book E Instruction Address Compare 2 */
+#endif /* CONFIG_BOOKE */
+#define SPRN_IBAT0L	0x211	/* Instruction BAT 0 Lower Register */
+#define SPRN_IBAT0U	0x210	/* Instruction BAT 0 Upper Register */
+#define SPRN_IBAT1L	0x213	/* Instruction BAT 1 Lower Register */
+#define SPRN_IBAT1U	0x212	/* Instruction BAT 1 Upper Register */
+#define SPRN_IBAT2L	0x215	/* Instruction BAT 2 Lower Register */
+#define SPRN_IBAT2U	0x214	/* Instruction BAT 2 Upper Register */
+#define SPRN_IBAT3L	0x217	/* Instruction BAT 3 Lower Register */
+#define SPRN_IBAT3U	0x216	/* Instruction BAT 3 Upper Register */
+#define SPRN_IBAT4L	0x231   /* Instruction BAT 4 Lower Register */
+#define SPRN_IBAT4U	0x230   /* Instruction BAT 4 Upper Register */
+#define SPRN_IBAT5L	0x233   /* Instruction BAT 5 Lower Register */
+#define SPRN_IBAT5U	0x232   /* Instruction BAT 5 Upper Register */
+#define SPRN_IBAT6L	0x235   /* Instruction BAT 6 Lower Register */
+#define SPRN_IBAT6U	0x234   /* Instruction BAT 6 Upper Register */
+#define SPRN_IBAT7L	0x237   /* Instruction BAT 7 Lower Register */
+#define SPRN_IBAT7U	0x236   /* Instruction BAT 7 Upper Register */
+#define SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
+#define   ICCR_NOCACHE		0	/* Noncacheable */
+#define   ICCR_CACHE		1	/* Cacheable */
+#define SPRN_ICDBDR	0x3D3	/* Instruction Cache Debug Data Register */
+#define SPRN_ICMP	0x3D5	/* Instruction TLB Compare Register */
+#define SPRN_ICTC	0x3FB	/* Instruction Cache Throttling Control Reg */
+#define SPRN_IMISS	0x3D4	/* Instruction TLB Miss Register */
+#define SPRN_IMMR	0x27E  	/* Internal Memory Map Register */
+#define SPRN_L2CR	0x3F9	/* Level 2 Cache Control Regsiter */
+#define SPRN_LR		0x008	/* Link Register */
+#define SPRN_MBAR       0x137   /* System memory base address */
+#define SPRN_MMCR0	0x3B8	/* Monitor Mode Control Register 0 */
+#define SPRN_MMCR1	0x3BC	/* Monitor Mode Control Register 1 */
+#define SPRN_PBL1	0x3FC	/* Protection Bound Lower 1 */
+#define SPRN_PBL2	0x3FE	/* Protection Bound Lower 2 */
+#define SPRN_PBU1	0x3FD	/* Protection Bound Upper 1 */
+#define SPRN_PBU2	0x3FF	/* Protection Bound Upper 2 */
+#ifndef CONFIG_BOOKE
+#define SPRN_PID	0x3B1	/* Process ID */
+#define SPRN_PIR	0x3FF	/* Processor Identification Register */
+#else
+#define SPRN_PID        0x030   /* Book E Process ID */
+#define SPRN_PIR        0x11E   /* Book E Processor Identification Register */
+#endif /* CONFIG_BOOKE */
+#define SPRN_PIT	0x3DB	/* Programmable Interval Timer */
+#define SPRN_PMC1	0x3B9	/* Performance Counter Register 1 */
+#define SPRN_PMC2	0x3BA	/* Performance Counter Register 2 */
+#define SPRN_PMC3	0x3BD	/* Performance Counter Register 3 */
+#define SPRN_PMC4	0x3BE	/* Performance Counter Register 4 */
+#define SPRN_PVR	0x11F	/* Processor Version Register */
+#define SPRN_RPA	0x3D6	/* Required Physical Address Register */
+#define SPRN_SDA	0x3BF	/* Sampled Data Address Register */
+#define SPRN_SDR1	0x019	/* MMU Hash Base Register */
+#define SPRN_SGR	0x3B9	/* Storage Guarded Register */
+#define   SGR_NORMAL		0
+#define   SGR_GUARDED		1
+#define SPRN_SIA	0x3BB	/* Sampled Instruction Address Register */
+#define SPRN_SPRG0	0x110	/* Special Purpose Register General 0 */
+#define SPRN_SPRG1	0x111	/* Special Purpose Register General 1 */
+#define SPRN_SPRG2	0x112	/* Special Purpose Register General 2 */
+#define SPRN_SPRG3	0x113	/* Special Purpose Register General 3 */
+#define SPRN_SRR0	0x01A	/* Save/Restore Register 0 */
+#define SPRN_SRR1	0x01B	/* Save/Restore Register 1 */
+#define SPRN_SRR2	0x3DE	/* Save/Restore Register 2 */
+#define SPRN_SRR3 	0x3DF	/* Save/Restore Register 3 */
+#ifdef CONFIG_BOOKE
+#define SPRN_SVR	0x3FF	/* System Version Register */
+#else
+#define SPRN_SVR	0x11E	/* System Version Register */
+#endif
+#define SPRN_TBHI	0x3DC	/* Time Base High */
+#define SPRN_TBHU	0x3CC	/* Time Base High User-mode */
+#define SPRN_TBLO	0x3DD	/* Time Base Low */
+#define SPRN_TBLU	0x3CD	/* Time Base Low User-mode */
+#define SPRN_TBRL	0x10C	/* Time Base Read Lower Register */
+#define SPRN_TBRU	0x10D	/* Time Base Read Upper Register */
+#define SPRN_TBWL	0x11C	/* Time Base Write Lower Register */
+#define SPRN_TBWU	0x11D	/* Time Base Write Upper Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_TCR	0x3DA	/* Timer Control Register */
+#else
+#define SPRN_TCR        0x154   /* Book E Timer Control Register */
+#endif /* CONFIG_BOOKE */
+#define   TCR_WP(x)		(((x)&0x3)<<30)	/* WDT Period */
+#define     WP_2_17		0		/* 2^17 clocks */
+#define     WP_2_21		1		/* 2^21 clocks */
+#define     WP_2_25		2		/* 2^25 clocks */
+#define     WP_2_29		3		/* 2^29 clocks */
+#define   TCR_WRC(x)		(((x)&0x3)<<28)	/* WDT Reset Control */
+#define     WRC_NONE		0		/* No reset will occur */
+#define     WRC_CORE		1		/* Core reset will occur */
+#define     WRC_CHIP		2		/* Chip reset will occur */
+#define     WRC_SYSTEM		3		/* System reset will occur */
+#define   TCR_WIE		0x08000000	/* WDT Interrupt Enable */
+#define   TCR_PIE		0x04000000	/* PIT Interrupt Enable */
+#define   TCR_FP(x)		(((x)&0x3)<<24)	/* FIT Period */
+#define     FP_2_9		0		/* 2^9 clocks */
+#define     FP_2_13		1		/* 2^13 clocks */
+#define     FP_2_17		2		/* 2^17 clocks */
+#define     FP_2_21		3		/* 2^21 clocks */
+#define   TCR_FIE		0x00800000	/* FIT Interrupt Enable */
+#define   TCR_ARE		0x00400000	/* Auto Reload Enable */
+#define SPRN_THRM1	0x3FC	/* Thermal Management Register 1 */
+#define   THRM1_TIN		(1<<0)
+#define   THRM1_TIV		(1<<1)
+#define   THRM1_THRES		(0x7f<<2)
+#define   THRM1_TID		(1<<29)
+#define   THRM1_TIE		(1<<30)
+#define   THRM1_V		(1<<31)
+#define SPRN_THRM2	0x3FD	/* Thermal Management Register 2 */
+#define SPRN_THRM3	0x3FE	/* Thermal Management Register 3 */
+#define   THRM3_E		(1<<31)
+#define SPRN_TLBMISS    0x3D4   /* 980 7450 TLB Miss Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_TSR	0x3D8	/* Timer Status Register */
+#else
+#define SPRN_TSR        0x150   /* Book E Timer Status Register */
+#endif /* CONFIG_BOOKE */
+#define   TSR_ENW		0x80000000	/* Enable Next Watchdog */
+#define   TSR_WIS		0x40000000	/* WDT Interrupt Status */
+#define   TSR_WRS(x)		(((x)&0x3)<<28)	/* WDT Reset Status */
+#define     WRS_NONE		0		/* No WDT reset occurred */
+#define     WRS_CORE		1		/* WDT forced core reset */
+#define     WRS_CHIP		2		/* WDT forced chip reset */
+#define     WRS_SYSTEM		3		/* WDT forced system reset */
+#define   TSR_PIS		0x08000000	/* PIT Interrupt Status */
+#define   TSR_FIS		0x04000000	/* FIT Interrupt Status */
+#define SPRN_UMMCR0	0x3A8	/* User Monitor Mode Control Register 0 */
+#define SPRN_UMMCR1	0x3AC	/* User Monitor Mode Control Register 0 */
+#define SPRN_UPMC1	0x3A9	/* User Performance Counter Register 1 */
+#define SPRN_UPMC2	0x3AA	/* User Performance Counter Register 2 */
+#define SPRN_UPMC3	0x3AD	/* User Performance Counter Register 3 */
+#define SPRN_UPMC4	0x3AE	/* User Performance Counter Register 4 */
+#define SPRN_USIA	0x3AB	/* User Sampled Instruction Address Register */
+#define SPRN_XER	0x001	/* Fixed Point Exception Register */
+#define SPRN_ZPR	0x3B0	/* Zone Protection Register */
+
+/* Book E definitions */
+#define SPRN_DECAR	0x036	/* Decrementer Auto Reload Register */
+#define SPRN_CSRR0	0x03A	/* Critical SRR0 */
+#define SPRN_CSRR1	0x03B	/* Critical SRR0 */
+#define SPRN_IVPR	0x03F	/* Interrupt Vector Prefix Register */
+#define SPRN_USPRG0	0x100	/* User Special Purpose Register General 0 */
+#define SPRN_SPRG4R	0x104	/* Special Purpose Register General 4 Read */
+#define SPRN_SPRG5R	0x105	/* Special Purpose Register General 5 Read */
+#define SPRN_SPRG6R	0x106	/* Special Purpose Register General 6 Read */
+#define SPRN_SPRG7R	0x107	/* Special Purpose Register General 7 Read */
+#define SPRN_SPRG4W	0x114	/* Special Purpose Register General 4 Write */
+#define SPRN_SPRG5W	0x115	/* Special Purpose Register General 5 Write */
+#define SPRN_SPRG6W	0x116	/* Special Purpose Register General 6 Write */
+#define SPRN_SPRG7W	0x117	/* Special Purpose Register General 7 Write */
+#define SPRN_DBCR2	0x136	/* Debug Control Register 2 */
+#define SPRN_IAC3	0x13A	/* Instruction Address Compare 3 */
+#define SPRN_IAC4	0x13B	/* Instruction Address Compare 4 */
+#define SPRN_DVC1	0x13E	/* Data Value Compare Register 1 */
+#define SPRN_DVC2	0x13F	/* Data Value Compare Register 2 */
+#define SPRN_IVOR0	0x190	/* Interrupt Vector Offset Register 0 */
+#define SPRN_IVOR1	0x191	/* Interrupt Vector Offset Register 1 */
+#define SPRN_IVOR2	0x192	/* Interrupt Vector Offset Register 2 */
+#define SPRN_IVOR3	0x193	/* Interrupt Vector Offset Register 3 */
+#define SPRN_IVOR4	0x194	/* Interrupt Vector Offset Register 4 */
+#define SPRN_IVOR5	0x195	/* Interrupt Vector Offset Register 5 */
+#define SPRN_IVOR6	0x196	/* Interrupt Vector Offset Register 6 */
+#define SPRN_IVOR7	0x197	/* Interrupt Vector Offset Register 7 */
+#define SPRN_IVOR8	0x198	/* Interrupt Vector Offset Register 8 */
+#define SPRN_IVOR9	0x199	/* Interrupt Vector Offset Register 9 */
+#define SPRN_IVOR10	0x19a	/* Interrupt Vector Offset Register 10 */
+#define SPRN_IVOR11	0x19b	/* Interrupt Vector Offset Register 11 */
+#define SPRN_IVOR12	0x19c	/* Interrupt Vector Offset Register 12 */
+#define SPRN_IVOR13	0x19d	/* Interrupt Vector Offset Register 13 */
+#define SPRN_IVOR14	0x19e	/* Interrupt Vector Offset Register 14 */
+#define SPRN_IVOR15	0x19f	/* Interrupt Vector Offset Register 15 */
+
+/* e500 definitions */
+#define SPRN_L1CSR0     0x3f2   /* L1 Cache Control and Status Register 0 */
+#define   L1CSR0_DCFI           0x00000002      /* Data Cache Flash Invalidate */
+#define   L1CSR0_DCE            0x00000001      /* Data Cache Enable */
+#define SPRN_L1CSR1     0x3f3   /* L1 Cache Control and Status Register 1 */
+#define   L1CSR1_ICFI           0x00000002      /* Instruction Cache Flash Invalidate */
+#define   L1CSR1_ICE            0x00000001      /* Instruction Cache Enable */
+
+#define SPRN_MMUCSR0	0x3f4	/* MMU control and status register 0 */
+#define SPRN_MAS0       0x270   /* MMU Assist Register 0 */
+#define SPRN_MAS1       0x271   /* MMU Assist Register 1 */
+#define SPRN_MAS2       0x272   /* MMU Assist Register 2 */
+#define SPRN_MAS3       0x273   /* MMU Assist Register 3 */
+#define SPRN_MAS4       0x274   /* MMU Assist Register 4 */
+#define SPRN_MAS5       0x275   /* MMU Assist Register 5 */
+#define SPRN_MAS6       0x276   /* MMU Assist Register 6 */
+#define SPRN_MAS7	0x3B0	/* MMU Assist Register 7 */
+
+#define SPRN_IVOR32     0x210   /* Interrupt Vector Offset Register 32 */
+#define SPRN_IVOR33     0x211   /* Interrupt Vector Offset Register 33 */
+#define SPRN_IVOR34     0x212   /* Interrupt Vector Offset Register 34 */
+#define SPRN_IVOR35     0x213   /* Interrupt Vector Offset Register 35 */
+#define SPRN_SPEFSCR    0x200   /* SPE & Embedded FP Status & Control */
+
+#define SPRN_MCSRR0     0x23a   /* Machine Check Save and Restore Register 0 */
+#define SPRN_MCSRR1     0x23b   /* Machine Check Save and Restore Register 1 */
+#define SPRN_BUCSR	0x3f5	/* Branch Control and Status Register */
+#define SPRN_BBEAR      0x201   /* Branch Buffer Entry Address Register */
+#define SPRN_BBTAR      0x202   /* Branch Buffer Target Address Register */
+#define SPRN_PID1       0x279   /* Process ID Register 1 */
+#define SPRN_PID2       0x27a   /* Process ID Register 2 */
+#define SPRN_MCSR	0x23c	/* Machine Check Syndrome register */
+#define ESR_ST          0x00800000      /* Store Operation */
+
+/* Short-hand versions for a number of the above SPRNs */
+
+#define CTR	SPRN_CTR	/* Counter Register */
+#define DAR	SPRN_DAR	/* Data Address Register */
+#define DABR	SPRN_DABR	/* Data Address Breakpoint Register */
+#define DAC1	SPRN_DAC1	/* Data Address Register 1 */
+#define DAC2	SPRN_DAC2	/* Data Address Register 2 */
+#define DBAT0L	SPRN_DBAT0L	/* Data BAT 0 Lower Register */
+#define DBAT0U	SPRN_DBAT0U	/* Data BAT 0 Upper Register */
+#define DBAT1L	SPRN_DBAT1L	/* Data BAT 1 Lower Register */
+#define DBAT1U	SPRN_DBAT1U	/* Data BAT 1 Upper Register */
+#define DBAT2L	SPRN_DBAT2L	/* Data BAT 2 Lower Register */
+#define DBAT2U	SPRN_DBAT2U	/* Data BAT 2 Upper Register */
+#define DBAT3L	SPRN_DBAT3L	/* Data BAT 3 Lower Register */
+#define DBAT3U	SPRN_DBAT3U	/* Data BAT 3 Upper Register */
+#define DBAT4L	SPRN_DBAT4L     /* Data BAT 4 Lower Register */
+#define DBAT4U	SPRN_DBAT4U     /* Data BAT 4 Upper Register */
+#define DBAT5L	SPRN_DBAT5L     /* Data BAT 5 Lower Register */
+#define DBAT5U	SPRN_DBAT5U     /* Data BAT 5 Upper Register */
+#define DBAT6L	SPRN_DBAT6L     /* Data BAT 6 Lower Register */
+#define DBAT6U	SPRN_DBAT6U     /* Data BAT 6 Upper Register */
+#define DBAT7L	SPRN_DBAT7L     /* Data BAT 7 Lower Register */
+#define DBAT7U	SPRN_DBAT7U     /* Data BAT 7 Upper Register */
+#define DBCR0	SPRN_DBCR0	/* Debug Control Register 0 */
+#define DBCR1	SPRN_DBCR1	/* Debug Control Register 1 */
+#define DBSR	SPRN_DBSR	/* Debug Status Register */
+#define DCMP	SPRN_DCMP      	/* Data TLB Compare Register */
+#define DEC	SPRN_DEC       	/* Decrement Register */
+#define DMISS	SPRN_DMISS     	/* Data TLB Miss Register */
+#define DSISR	SPRN_DSISR	/* Data Storage Interrupt Status Register */
+#define EAR	SPRN_EAR       	/* External Address Register */
+#define ESR	SPRN_ESR	/* Exception Syndrome Register */
+#define HASH1	SPRN_HASH1	/* Primary Hash Address Register */
+#define HASH2	SPRN_HASH2	/* Secondary Hash Address Register */
+#define HID0	SPRN_HID0	/* Hardware Implementation Register 0 */
+#define HID1	SPRN_HID1	/* Hardware Implementation Register 1 */
+#define IABR	SPRN_IABR      	/* Instruction Address Breakpoint Register */
+#define IAC1	SPRN_IAC1	/* Instruction Address Register 1 */
+#define IAC2	SPRN_IAC2	/* Instruction Address Register 2 */
+#define IBAT0L	SPRN_IBAT0L	/* Instruction BAT 0 Lower Register */
+#define IBAT0U	SPRN_IBAT0U	/* Instruction BAT 0 Upper Register */
+#define IBAT1L	SPRN_IBAT1L	/* Instruction BAT 1 Lower Register */
+#define IBAT1U	SPRN_IBAT1U	/* Instruction BAT 1 Upper Register */
+#define IBAT2L	SPRN_IBAT2L	/* Instruction BAT 2 Lower Register */
+#define IBAT2U	SPRN_IBAT2U	/* Instruction BAT 2 Upper Register */
+#define IBAT3L	SPRN_IBAT3L	/* Instruction BAT 3 Lower Register */
+#define IBAT3U	SPRN_IBAT3U	/* Instruction BAT 3 Upper Register */
+#define IBAT4L	SPRN_IBAT4L	/* Instruction BAT 4 Lower Register */
+#define IBAT4U	SPRN_IBAT4U	/* Instruction BAT 4 Upper Register */
+#define IBAT5L	SPRN_IBAT5L	/* Instruction BAT 5 Lower Register */
+#define IBAT5U	SPRN_IBAT5U	/* Instruction BAT 5 Upper Register */
+#define IBAT6L	SPRN_IBAT6L	/* Instruction BAT 6 Lower Register */
+#define IBAT6U	SPRN_IBAT6U	/* Instruction BAT 6 Upper Register */
+#define IBAT7L 	SPRN_IBAT7L	/* Instruction BAT 7 Lower Register */
+#define IBAT7U	SPRN_IBAT7U	/* Instruction BAT 7 Lower Register */
+#define ICMP	SPRN_ICMP	/* Instruction TLB Compare Register */
+#define IMISS	SPRN_IMISS	/* Instruction TLB Miss Register */
+#define IMMR	SPRN_IMMR      	/* PPC 860/821 Internal Memory Map Register */
+#define L2CR	SPRN_L2CR    	/* PPC 750 L2 control register */
+#define LR	SPRN_LR
+#define MBAR    SPRN_MBAR       /* System memory base address */
+#if defined(CONFIG_E500)
+#define PIR	SPRN_PIR
+#endif
+#define SVR	SPRN_SVR	/* System-On-Chip Version Register */
+#define PVR	SPRN_PVR	/* Processor Version */
+#define RPA	SPRN_RPA	/* Required Physical Address Register */
+#define SDR1	SPRN_SDR1      	/* MMU hash base register */
+#define SPR0	SPRN_SPRG0	/* Supervisor Private Registers */
+#define SPR1	SPRN_SPRG1
+#define SPR2	SPRN_SPRG2
+#define SPR3	SPRN_SPRG3
+#define SPRG0   SPRN_SPRG0
+#define SPRG1   SPRN_SPRG1
+#define SPRG2   SPRN_SPRG2
+#define SPRG3   SPRN_SPRG3
+#define SRR0	SPRN_SRR0	/* Save and Restore Register 0 */
+#define SRR1	SPRN_SRR1	/* Save and Restore Register 1 */
+#define SVR	SPRN_SVR	/* System Version Register */
+#define TBRL	SPRN_TBRL	/* Time Base Read Lower Register */
+#define TBRU	SPRN_TBRU	/* Time Base Read Upper Register */
+#define TBWL	SPRN_TBWL	/* Time Base Write Lower Register */
+#define TBWU	SPRN_TBWU	/* Time Base Write Upper Register */
+#define TCR	SPRN_TCR	/* Timer Control Register */
+#define TSR	SPRN_TSR	/* Timer Status Register */
+#define ICTC	1019
+#define THRM1	SPRN_THRM1	/* Thermal Management Register 1 */
+#define THRM2	SPRN_THRM2	/* Thermal Management Register 2 */
+#define THRM3	SPRN_THRM3	/* Thermal Management Register 3 */
+#define XER	SPRN_XER
+
+#define DECAR	SPRN_DECAR
+#define CSRR0	SPRN_CSRR0
+#define CSRR1	SPRN_CSRR1
+#define IVPR	SPRN_IVPR
+#define USPRG0	SPRN_USPRG0
+#define SPRG4R	SPRN_SPRG4R
+#define SPRG5R	SPRN_SPRG5R
+#define SPRG6R	SPRN_SPRG6R
+#define SPRG7R	SPRN_SPRG7R
+#define SPRG4W	SPRN_SPRG4W
+#define SPRG5W	SPRN_SPRG5W
+#define SPRG6W	SPRN_SPRG6W
+#define SPRG7W	SPRN_SPRG7W
+#define DEAR	SPRN_DEAR
+#define DBCR2	SPRN_DBCR2
+#define IAC3	SPRN_IAC3
+#define IAC4	SPRN_IAC4
+#define DVC1	SPRN_DVC1
+#define DVC2	SPRN_DVC2
+#define IVOR0	SPRN_IVOR0
+#define IVOR1	SPRN_IVOR1
+#define IVOR2	SPRN_IVOR2
+#define IVOR3	SPRN_IVOR3
+#define IVOR4	SPRN_IVOR4
+#define IVOR5	SPRN_IVOR5
+#define IVOR6	SPRN_IVOR6
+#define IVOR7	SPRN_IVOR7
+#define IVOR8	SPRN_IVOR8
+#define IVOR9	SPRN_IVOR9
+#define IVOR10	SPRN_IVOR10
+#define IVOR11	SPRN_IVOR11
+#define IVOR12	SPRN_IVOR12
+#define IVOR13	SPRN_IVOR13
+#define IVOR14	SPRN_IVOR14
+#define IVOR15	SPRN_IVOR15
+#define IVOR32	SPRN_IVOR32
+#define IVOR33	SPRN_IVOR33
+#define IVOR34	SPRN_IVOR34
+#define IVOR35	SPRN_IVOR35
+#define MCSRR0	SPRN_MCSRR0
+#define MCSRR1	SPRN_MCSRR1
+#define L1CSR0 	SPRN_L1CSR0
+#define L1CSR1	SPRN_L1CSR1
+#define MCSR	SPRN_MCSR
+#define MMUCSR0	SPRN_MMUCSR0
+#define BUCSR	SPRN_BUCSR
+#define PID0	SPRN_PID
+#define PID1	SPRN_PID1
+#define PID2	SPRN_PID2
+#define MAS0	SPRN_MAS0
+#define MAS1 	SPRN_MAS1
+#define MAS2	SPRN_MAS2
+#define MAS3	SPRN_MAS3
+#define MAS4	SPRN_MAS4
+#define MAS5	SPRN_MAS5
+#define MAS6	SPRN_MAS6
+#define MAS7	SPRN_MAS7
+
+/* Device Control Registers */
+
+#define DCRN_BEAR	0x090	/* Bus Error Address Register */
+#define DCRN_BESR	0x091	/* Bus Error Syndrome Register */
+#define   BESR_DSES    	0x80000000	/* Data-Side Error Status */
+#define   BESR_DMES	0x40000000	/* DMA Error Status */
+#define   BESR_RWS	0x20000000	/* Read/Write Status */
+#define   BESR_ETMASK	0x1C000000	/* Error Type */
+#define     ET_PROT	0
+#define     ET_PARITY	1
+#define     ET_NCFG	2
+#define     ET_BUSERR	4
+#define     ET_BUSTO	6
+#define DCRN_DMACC0	0x0C4	/* DMA Chained Count Register 0 */
+#define DCRN_DMACC1	0x0CC	/* DMA Chained Count Register 1 */
+#define DCRN_DMACC2	0x0D4	/* DMA Chained Count Register 2 */
+#define DCRN_DMACC3	0x0DC    /* DMA Chained Count Register 3 */
+#define DCRN_DMACR0	0x0C0    /* DMA Channel Control Register 0 */
+#define DCRN_DMACR1	0x0C8    /* DMA Channel Control Register 1 */
+#define DCRN_DMACR2	0x0D0    /* DMA Channel Control Register 2 */
+#define DCRN_DMACR3	0x0D8    /* DMA Channel Control Register 3 */
+#define DCRN_DMACT0	0x0C1    /* DMA Count Register 0 */
+#define DCRN_DMACT1	0x0C9    /* DMA Count Register 1 */
+#define DCRN_DMACT2	0x0D1    /* DMA Count Register 2 */
+#define DCRN_DMACT3	0x0D9    /* DMA Count Register 3 */
+#define DCRN_DMADA0	0x0C2    /* DMA Destination Address Register 0 */
+#define DCRN_DMADA1	0x0CA    /* DMA Destination Address Register 1 */
+#define DCRN_DMADA2	0x0D2    /* DMA Destination Address Register 2 */
+#define DCRN_DMADA3	0x0DA    /* DMA Destination Address Register 3 */
+#define DCRN_DMASA0	0x0C3    /* DMA Source Address Register 0 */
+#define DCRN_DMASA1	0x0CB    /* DMA Source Address Register 1 */
+#define DCRN_DMASA2	0x0D3    /* DMA Source Address Register 2 */
+#define DCRN_DMASA3	0x0DB    /* DMA Source Address Register 3 */
+#define DCRN_DMASR	0x0E0    /* DMA Status Register */
+#define DCRN_EXIER	0x042    /* External Interrupt Enable Register */
+#define   EXIER_CIE	0x80000000	/* Critical Interrupt Enable */
+#define   EXIER_SRIE	0x08000000	/* Serial Port Rx Int. Enable */
+#define   EXIER_STIE	0x04000000	/* Serial Port Tx Int. Enable */
+#define   EXIER_JRIE	0x02000000	/* JTAG Serial Port Rx Int. Enable */
+#define   EXIER_JTIE	0x01000000	/* JTAG Serial Port Tx Int. Enable */
+#define   EXIER_D0IE	0x00800000	/* DMA Channel 0 Interrupt Enable */
+#define   EXIER_D1IE	0x00400000	/* DMA Channel 1 Interrupt Enable */
+#define   EXIER_D2IE	0x00200000	/* DMA Channel 2 Interrupt Enable */
+#define   EXIER_D3IE	0x00100000	/* DMA Channel 3 Interrupt Enable */
+#define   EXIER_E0IE	0x00000010	/* External Interrupt 0 Enable */
+#define   EXIER_E1IE	0x00000008	/* External Interrupt 1 Enable */
+#define   EXIER_E2IE	0x00000004	/* External Interrupt 2 Enable */
+#define   EXIER_E3IE	0x00000002	/* External Interrupt 3 Enable */
+#define   EXIER_E4IE	0x00000001	/* External Interrupt 4 Enable */
+#define DCRN_EXISR	0x040    /* External Interrupt Status Register */
+#define DCRN_IOCR	0x0A0    /* Input/Output Configuration Register */
+#define   IOCR_E0TE	0x80000000
+#define   IOCR_E0LP	0x40000000
+#define   IOCR_E1TE	0x20000000
+#define   IOCR_E1LP	0x10000000
+#define   IOCR_E2TE	0x08000000
+#define   IOCR_E2LP	0x04000000
+#define   IOCR_E3TE	0x02000000
+#define   IOCR_E3LP	0x01000000
+#define   IOCR_E4TE	0x00800000
+#define   IOCR_E4LP	0x00400000
+#define   IOCR_EDT     	0x00080000
+#define   IOCR_SOR     	0x00040000
+#define   IOCR_EDO	0x00008000
+#define   IOCR_2XC	0x00004000
+#define   IOCR_ATC	0x00002000
+#define   IOCR_SPD	0x00001000
+#define   IOCR_BEM	0x00000800
+#define   IOCR_PTD	0x00000400
+#define   IOCR_ARE	0x00000080
+#define   IOCR_DRC	0x00000020
+#define   IOCR_RDM(x)	(((x) & 0x3) << 3)
+#define   IOCR_TCS	0x00000004
+#define   IOCR_SCS	0x00000002
+#define   IOCR_SPC	0x00000001
+
+/* System-On-Chip Version Register */
+
+/* System-On-Chip Version Register (SVR) field extraction */
+
+#define SVR_VER(svr)	(((svr) >> 16) & 0xFFFF) /* Version field */
+#define SVR_REV(svr)	(((svr) >>  0) & 0xFFFF) /* Revision field */
+
+#define SVR_CID(svr)	(((svr) >> 28) & 0x0F)   /* Company or manufacturer ID */
+#define SVR_SOCOP(svr)	(((svr) >> 22) & 0x3F)   /* SOC integration options */
+#define SVR_SID(svr)	(((svr) >> 16) & 0x3F)   /* SOC ID */
+#define SVR_PROC(svr)	(((svr) >> 12) & 0x0F)   /* Process revision field */
+#define SVR_MFG(svr)	(((svr) >>  8) & 0x0F)   /* Manufacturing revision */
+#define SVR_MJREV(svr)	(((svr) >>  4) & 0x0F)   /* Major SOC design revision indicator */
+#define SVR_MNREV(svr)	(((svr) >>  0) & 0x0F)   /* Minor SOC design revision indicator */
+
+/* System-On-Chip Version Numbers (version field only) */
+#define SVR_MPC5200	0x8011
+
+/* Processor Version Register */
+
+/* Processor Version Register (PVR) field extraction */
+
+#define PVR_VER(pvr)  (((pvr) >>  16) & 0xFFFF)	/* Version field */
+#define PVR_REV(pvr)  (((pvr) >>   0) & 0xFFFF)	/* Revison field */
+
+/*
+ * AMCC has further subdivided the standard PowerPC 16-bit version and
+ * revision subfields of the PVR for the PowerPC 403s into the following:
+ */
+
+#define PVR_FAM(pvr)	(((pvr) >> 20) & 0xFFF)	/* Family field */
+#define PVR_MEM(pvr)	(((pvr) >> 16) & 0xF)	/* Member field */
+#define PVR_CORE(pvr)	(((pvr) >> 12) & 0xF)	/* Core field */
+#define PVR_CFG(pvr)	(((pvr) >>  8) & 0xF)	/* Configuration field */
+#define PVR_MAJ(pvr)	(((pvr) >>  4) & 0xF)	/* Major revision field */
+#define PVR_MIN(pvr)	(((pvr) >>  0) & 0xF)	/* Minor revision field */
+
+/* Processor Version Numbers */
+
+#define PVR_403GA	0x00200000
+#define PVR_403GB	0x00200100
+#define PVR_403GC	0x00200200
+#define PVR_403GCX	0x00201400
+#define PVR_405GP	0x40110000
+#define PVR_405GP_RB	0x40110040
+#define PVR_405GP_RC	0x40110082
+#define PVR_405GP_RD	0x401100C4
+#define PVR_405GP_RE	0x40110145  /* same as pc405cr rev c */
+#define PVR_405CR_RA	0x40110041
+#define PVR_405CR_RB	0x401100C5
+#define PVR_405CR_RC	0x40110145  /* same as pc405gp rev e */
+#define PVR_405EP_RA	0x51210950
+#define PVR_405GPR_RB	0x50910951
+#define PVR_440GP_RB	0x40120440
+#define PVR_440GP_RC	0x40120481
+#define PVR_440EP_RA	0x42221850
+#define PVR_440EP_RB	0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440GR_RA	0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440GX_RA	0x51B21850
+#define PVR_440GX_RB	0x51B21851
+#define PVR_440GX_RC	0x51B21892
+#define PVR_440GX_RF	0x51B21894
+#define PVR_405EP_RB	0x51210950
+#define PVR_440SP_RA	0x53221850
+#define PVR_440SP_RB	0x53221891
+#define PVR_601		0x00010000
+#define PVR_602		0x00050000
+#define PVR_603		0x00030000
+#define PVR_603e	0x00060000
+#define PVR_603ev	0x00070000
+#define PVR_603r	0x00071000
+#define PVR_604		0x00040000
+#define PVR_604e	0x00090000
+#define PVR_604r	0x000A0000
+#define PVR_620		0x00140000
+#define PVR_740		0x00080000
+#define PVR_750		PVR_740
+#define PVR_740P	0x10080000
+#define PVR_750P	PVR_740P
+#define PVR_7400        0x000C0000
+#define PVR_7410        0x800C0000
+#define PVR_7450        0x80000000
+
+#define PVR_85xx	0x80200000
+#define PVR_85xx_REV1	(PVR_85xx | 0x0010)
+#define PVR_85xx_REV2	(PVR_85xx | 0x0020)
+
+
+/*
+ * For the 8xx processors, all of them report the same PVR family for
+ * the PowerPC core. The various versions of these processors must be
+ * differentiated by the version number in the Communication Processor
+ * Module (CPM).
+ */
+#define PVR_821		0x00500000
+#define PVR_823		PVR_821
+#define PVR_850		PVR_821
+#define PVR_860		PVR_821
+#define PVR_7400       	0x000C0000
+#define PVR_8240	0x00810100
+
+/*
+ * PowerQUICC II family processors report different PVR values depending
+ * on silicon process (HiP3, HiP4, HiP7, etc.)
+ */
+#define PVR_8260        PVR_8240
+#define PVR_8260_HIP3   0x00810101
+#define PVR_8260_HIP4   0x80811014
+#define PVR_8260_HIP7   0x80822011
+#define PVR_8260_HIP7R1 0x80822013
+#define PVR_8260_HIP7RA	0x80822014
+
+
+/*
+ * System Version Register
+ */
+
+/* System Version Register (SVR) field extraction */
+
+#define SVR_VER(svr)	(((svr) >>  16) & 0xFFFF)	/* Version field */
+#define SVR_REV(svr)	(((svr) >>   0) & 0xFFFF)	/* Revison field */
+
+#define SVR_FAM(svr)	(((svr) >> 20) & 0xFFF)	/* Family field */
+#define SVR_MEM(svr)	(((svr) >> 16) & 0xF)	/* Member field */
+
+#define SVR_MAJ(svr)	(((svr) >>  4) & 0xF)	/* Major revision field*/
+#define SVR_MIN(svr)	(((svr) >>  0) & 0xF)	/* Minor revision field*/
+
+
+/*
+ * SVR_VER() Version Values
+ */
+
+#define SVR_8540	0x8030
+#define SVR_8560	0x8070
+#define SVR_8555	0x8079
+#define SVR_8541	0x807A
+#define SVR_8548	0x8031
+#define SVR_8548_E	0x8039
+
+
+/* I am just adding a single entry for 8260 boards.  I think we may be
+ * able to combine mbx, fads, rpxlite, bseip, and classic into a single
+ * generic 8xx as well.  The boards containing these processors are either
+ * identical at the processor level (due to the high integration) or so
+ * wildly different that testing _machine at run time is best replaced by
+ * conditional compilation by board type (found in their respective .h file).
+ *	-- Dan
+ */
+#define _MACH_prep	0x00000001
+#define _MACH_Pmac	0x00000002	/* pmac or pmac clone (non-chrp) */
+#define _MACH_chrp	0x00000004	/* chrp machine */
+#define _MACH_mbx	0x00000008	/* Motorola MBX board */
+#define _MACH_apus	0x00000010	/* amiga with phase5 powerup */
+#define _MACH_fads	0x00000020	/* Motorola FADS board */
+#define _MACH_rpxlite	0x00000040	/* RPCG RPX-Lite 8xx board */
+#define _MACH_bseip	0x00000080	/* Bright Star Engineering ip-Engine */
+#define _MACH_yk	0x00000100	/* Motorola Yellowknife */
+#define _MACH_gemini	0x00000200	/* Synergy Microsystems gemini board */
+#define _MACH_classic	0x00000400	/* RPCG RPX-Classic 8xx board */
+#define _MACH_oak	0x00000800	/* IBM "Oak" 403 eval. board */
+#define _MACH_walnut	0x00001000	/* AMCC "Walnut" 405GP eval. board */
+#define _MACH_8260	0x00002000	/* Generic 8260 */
+#define _MACH_sandpoint 0x00004000	/* Motorola SPS Processor eval board */
+#define _MACH_tqm860	0x00008000	/* TQM860/L */
+#define _MACH_tqm8xxL	0x00010000	/* TQM8xxL */
+#define _MACH_hidden_dragon 0x00020000	/* Motorola Hidden Dragon eval board */
+
+
+/* see residual.h for these */
+#define _PREP_Motorola 0x01  /* motorola prep */
+#define _PREP_Firm     0x02  /* firmworks prep */
+#define _PREP_IBM      0x00  /* ibm prep */
+#define _PREP_Bull     0x03  /* bull prep */
+#define _PREP_Radstone 0x04  /* Radstone Technology PLC prep */
+
+/*
+ * Radstone board types
+ */
+#define RS_SYS_TYPE_PPC1   0
+#define RS_SYS_TYPE_PPC2   1
+#define RS_SYS_TYPE_PPC1a  2
+#define RS_SYS_TYPE_PPC2a  3
+#define RS_SYS_TYPE_PPC4   4
+#define RS_SYS_TYPE_PPC4a  5
+#define RS_SYS_TYPE_PPC2ep 6
+
+/* these are arbitrary */
+#define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
+#define _CHRP_IBM      0x05  /* IBM chrp, the longtrail and longtrail 2 */
+
+#define _GLOBAL(n)\
+	.globl n;\
+n:
+
+/* Macros for setting and retrieving special purpose registers */
+
+#define stringify(s)	tostring(s)
+#define tostring(s)	#s
+
+#define mfdcr(rn)	({unsigned int rval; \
+			asm volatile("mfdcr %0," stringify(rn) \
+				     : "=r" (rval)); rval;})
+#define mtdcr(rn, v)	asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
+
+#define mfmsr()		({unsigned int rval; \
+			asm volatile("mfmsr %0" : "=r" (rval)); rval;})
+#define mtmsr(v)	asm volatile("mtmsr %0" : : "r" (v))
+
+#define mfspr(rn)	({unsigned int rval; \
+			asm volatile("mfspr %0," stringify(rn) \
+				     : "=r" (rval)); rval;})
+#define mtspr(rn, v)	asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
+
+#define tlbie(v)	asm volatile("tlbie %0 \n sync" : : "r" (v))
+
+/* Segment Registers */
+
+#define SR0	0
+#define SR1	1
+#define SR2	2
+#define SR3	3
+#define SR4	4
+#define SR5	5
+#define SR6	6
+#define SR7	7
+#define SR8	8
+#define SR9	9
+#define SR10	10
+#define SR11	11
+#define SR12	12
+#define SR13	13
+#define SR14	14
+#define SR15	15
+
+#ifndef __ASSEMBLY__
+#ifndef CONFIG_MACH_SPECIFIC
+extern int _machine;
+extern int have_of;
+#endif /* CONFIG_MACH_SPECIFIC */
+
+/* what kind of prep workstation we are */
+extern int _prep_type;
+/*
+ * This is used to identify the board type from a given PReP board
+ * vendor. Board revision is also made available.
+ */
+extern unsigned char ucSystemType;
+extern unsigned char ucBoardRev;
+extern unsigned char ucBoardRevMaj, ucBoardRevMin;
+
+struct task_struct;
+void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
+void release_thread(struct task_struct *);
+
+/*
+ * Create a new kernel thread.
+ */
+extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+
+/*
+ * Bus types
+ */
+#define EISA_bus 0
+#define EISA_bus__is_a_macro /* for versions in ksyms.c */
+#define MCA_bus 0
+#define MCA_bus__is_a_macro /* for versions in ksyms.c */
+
+/* Lazy FPU handling on uni-processor */
+extern struct task_struct *last_task_used_math;
+extern struct task_struct *last_task_used_altivec;
+
+/*
+ * this is the minimum allowable io space due to the location
+ * of the io areas on prep (first one at 0x80000000) but
+ * as soon as I get around to remapping the io areas with the BATs
+ * to match the mac we can raise this. -- Cort
+ */
+#define TASK_SIZE	(0x80000000UL)
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE	(TASK_SIZE / 8 * 3)
+
+typedef struct {
+	unsigned long seg;
+} mm_segment_t;
+
+struct thread_struct {
+	unsigned long	ksp;		/* Kernel stack pointer */
+	unsigned long	wchan;		/* Event task is sleeping on */
+	struct pt_regs	*regs;		/* Pointer to saved register state */
+	mm_segment_t	fs;		/* for get_fs() validation */
+	void		*pgdir;		/* root of page-table tree */
+	signed long     last_syscall;
+	double		fpr[32];	/* Complete floating point set */
+	unsigned long	fpscr_pad;	/* fpr ... fpscr must be contiguous */
+	unsigned long	fpscr;		/* Floating point status */
+#ifdef CONFIG_ALTIVEC
+	vector128	vr[32];		/* Complete AltiVec set */
+	vector128	vscr;		/* AltiVec status */
+	unsigned long	vrsave;
+#endif /* CONFIG_ALTIVEC */
+};
+
+#define INIT_SP		(sizeof(init_stack) + (unsigned long) &init_stack)
+
+#define INIT_THREAD  { \
+	INIT_SP, /* ksp */ \
+	0, /* wchan */ \
+	(struct pt_regs *)INIT_SP - 1, /* regs */ \
+	KERNEL_DS, /*fs*/ \
+	swapper_pg_dir, /* pgdir */ \
+	0, /* last_syscall */ \
+	{0}, 0, 0 \
+}
+
+/*
+ * Note: the vm_start and vm_end fields here should *not*
+ * be in kernel space.  (Could vm_end == vm_start perhaps?)
+ */
+#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
+		    PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
+		    1, NULL, NULL }
+
+/*
+ * Return saved PC of a blocked thread. For now, this is the "user" PC
+ */
+static inline unsigned long thread_saved_pc(struct thread_struct *t)
+{
+	return (t->regs) ? t->regs->nip : 0;
+}
+
+#define copy_segments(tsk, mm)		do { } while (0)
+#define release_segments(mm)		do { } while (0)
+#define forget_segments()		do { } while (0)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define KSTK_EIP(tsk)  ((tsk)->thread.regs->nip)
+#define KSTK_ESP(tsk)  ((tsk)->thread.regs->gpr[1])
+
+/*
+ * NOTE! The task struct and the stack go together
+ */
+#define THREAD_SIZE (2*PAGE_SIZE)
+#define alloc_task_struct() \
+	((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
+#define free_task_struct(p)	free_pages((unsigned long)(p),1)
+#define get_task_struct(tsk)      atomic_inc(&mem_map[MAP_NR(tsk)].count)
+
+/* in process.c - for early bootup debug -- Cort */
+int ll_printk(const char *, ...);
+void ll_puts(const char *);
+
+#define init_task	(init_task_union.task)
+#define init_stack	(init_task_union.stack)
+
+/* In misc.c */
+void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
+
+#endif /* ndef ASSEMBLY*/
+
+#ifdef CONFIG_MACH_SPECIFIC
+#if defined(CONFIG_8xx)
+#define _machine _MACH_8xx
+#define have_of 0
+#elif defined(CONFIG_OAK)
+#define _machine _MACH_oak
+#define have_of	0
+#elif defined(CONFIG_WALNUT)
+#define _machine _MACH_walnut
+#define have_of 0
+#elif defined(CONFIG_APUS)
+#define _machine _MACH_apus
+#define have_of 0
+#elif defined(CONFIG_GEMINI)
+#define _machine _MACH_gemini
+#define have_of 0
+#elif defined(CONFIG_8260)
+#define _machine _MACH_8260
+#define have_of 0
+#elif defined(CONFIG_SANDPOINT)
+#define _machine _MACH_sandpoint
+#elif defined(CONFIG_HIDDEN_DRAGON)
+#define _machine _MACH_hidden_dragon
+#define have_of 0
+#else
+#error "Machine not defined correctly"
+#endif
+#endif /* CONFIG_MACH_SPECIFIC */
+
+#endif /* __ASM_PPC_PROCESSOR_H */
diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h
new file mode 100755
index 0000000..3c2f4e6
--- /dev/null
+++ b/include/asm-ppc/ptrace.h
@@ -0,0 +1,107 @@
+#ifndef _PPC_PTRACE_H
+#define _PPC_PTRACE_H
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ *
+ * this should only contain volatile regs
+ * since we can keep non-volatile in the thread_struct
+ * should set this up when only volatiles are saved
+ * by intr code.
+ *
+ * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
+ * that the overall structure is a multiple of 16 bytes in length.
+ *
+ * Note that the offsets of the fields in this struct correspond with
+ * the PT_* values below.  This simplifies arch/ppc/kernel/ptrace.c.
+ */
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_PPC64BRIDGE
+#define PPC_REG unsigned long /*long*/
+#else
+#define PPC_REG unsigned long
+#endif
+struct pt_regs {
+	PPC_REG gpr[32];
+	PPC_REG nip;
+	PPC_REG msr;
+	PPC_REG orig_gpr3;	/* Used for restarting system calls */
+	PPC_REG ctr;
+	PPC_REG link;
+	PPC_REG xer;
+	PPC_REG ccr;
+	PPC_REG mq;		/* 601 only (not used at present) */
+				/* Used on APUS to hold IPL value. */
+	PPC_REG trap;		/* Reason for being here */
+	PPC_REG dar;		/* Fault registers */
+	PPC_REG dsisr;
+	PPC_REG result; 	/* Result of a system call */
+};
+#endif
+
+#define STACK_FRAME_OVERHEAD	16	/* size of minimum stack frame */
+
+/* Size of stack frame allocated when calling signal handler. */
+#define __SIGNAL_FRAMESIZE	64
+
+#define instruction_pointer(regs) ((regs)->nip)
+#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0	0
+#define PT_R1	1
+#define PT_R2	2
+#define PT_R3	3
+#define PT_R4	4
+#define PT_R5	5
+#define PT_R6	6
+#define PT_R7	7
+#define PT_R8	8
+#define PT_R9	9
+#define PT_R10	10
+#define PT_R11	11
+#define PT_R12	12
+#define PT_R13	13
+#define PT_R14	14
+#define PT_R15	15
+#define PT_R16	16
+#define PT_R17	17
+#define PT_R18	18
+#define PT_R19	19
+#define PT_R20	20
+#define PT_R21	21
+#define PT_R22	22
+#define PT_R23	23
+#define PT_R24	24
+#define PT_R25	25
+#define PT_R26	26
+#define PT_R27	27
+#define PT_R28	28
+#define PT_R29	29
+#define PT_R30	30
+#define PT_R31	31
+
+#define PT_NIP	32
+#define PT_MSR	33
+#ifdef __KERNEL__
+#define PT_ORIG_R3 34
+#endif
+#define PT_CTR	35
+#define PT_LNK	36
+#define PT_XER	37
+#define PT_CCR	38
+#define PT_MQ	39
+
+#define PT_FPR0	48	/* each FP reg occupies 2 slots in this space */
+#define PT_FPR31 (PT_FPR0 + 2*31)
+#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
+
+#endif
diff --git a/include/asm-ppc/residual.h b/include/asm-ppc/residual.h
new file mode 100755
index 0000000..dc85edb
--- /dev/null
+++ b/include/asm-ppc/residual.h
@@ -0,0 +1,331 @@
+/* 7/18/95                                                                    */
+/*----------------------------------------------------------------------------*/
+/*      Residual Data header definitions and prototypes                       */
+/*----------------------------------------------------------------------------*/
+
+/* Structure map for RESIDUAL on PowerPC Reference Platform                   */
+/* residual.h - Residual data structure passed in r3.                         */
+/*              Load point passed in r4 to boot image.                        */
+/* For enum's: if given in hex then they are bit significant,                 */
+/*             i.e. only one bit is on for each enum                          */
+/* Reserved fields must be filled with zeros.                                */
+
+#ifndef _RESIDUAL_
+#define _RESIDUAL_
+
+#ifndef __ASSEMBLY__
+
+#define MAX_CPUS 32                     /* These should be set to the maximum */
+#define MAX_MEMS 64                     /* number possible for this system.   */
+#define MAX_DEVICES 256                 /* Changing these will change the     */
+#define AVE_PNP_SIZE 32                 /* structure, hence the version of    */
+#define MAX_MEM_SEGS 64                 /* this header file.                  */
+
+/*----------------------------------------------------------------------------*/
+/*               Public structures...                                         */
+/*----------------------------------------------------------------------------*/
+
+#include "pnp.h"
+
+typedef enum _L1CACHE_TYPE {
+  NoneCAC = 0,
+  SplitCAC = 1,
+  CombinedCAC = 2
+  } L1CACHE_TYPE;
+
+typedef enum _TLB_TYPE {
+  NoneTLB = 0,
+  SplitTLB = 1,
+  CombinedTLB = 2
+  } TLB_TYPE;
+
+typedef enum _FIRMWARE_SUPPORT {
+  Conventional = 0x01,
+  OpenFirmware = 0x02,
+  Diagnostics = 0x04,
+  LowDebug = 0x08,
+  Multiboot = 0x10,
+  LowClient = 0x20,
+  Hex41 = 0x40,
+  FAT = 0x80,
+  ISO9660 = 0x0100,
+  SCSI_InitiatorID_Override = 0x0200,
+  Tape_Boot = 0x0400,
+  FW_Boot_Path = 0x0800
+  } FIRMWARE_SUPPORT;
+
+typedef enum _FIRMWARE_SUPPLIERS {
+  IBMFirmware = 0x00,
+  MotoFirmware = 0x01,                  /* 7/18/95                            */
+  FirmWorks = 0x02,                     /* 10/5/95                            */
+  Bull = 0x03,                          /* 04/03/96                           */
+  } FIRMWARE_SUPPLIERS;
+
+typedef enum _ENDIAN_SWITCH_METHODS {
+  UsePort92 = 0x01,
+  UsePCIConfigA8 = 0x02,
+  UseFF001030 = 0x03,
+  } ENDIAN_SWITCH_METHODS;
+
+typedef enum _SPREAD_IO_METHODS {
+  UsePort850 = 0x00,
+/*UsePCIConfigA8 = 0x02,*/
+  } SPREAD_IO_METHODS;
+
+typedef struct _VPD {
+
+  /* Box dependent stuff */
+  unsigned char PrintableModel[32];     /* Null terminated string.
+					   Must be of the form:
+					   vvv,<20h>,<model designation>,<0x0>
+					   where vvv is the vendor ID
+					   e.g. IBM PPS MODEL 6015<0x0>       */
+  unsigned char Serial[16];             /* 12/94:
+					   Serial Number; must be of the form:
+					   vvv<serial number> where vvv is the
+					   vendor ID.
+					   e.g. IBM60151234567<20h><20h>      */
+  unsigned char Reserved[48];
+  unsigned long FirmwareSupplier;       /* See FirmwareSuppliers enum         */
+  unsigned long FirmwareSupports;       /* See FirmwareSupport enum           */
+  unsigned long NvramSize;              /* Size of nvram in bytes             */
+  unsigned long NumSIMMSlots;
+  unsigned short EndianSwitchMethod;    /* See EndianSwitchMethods enum       */
+  unsigned short SpreadIOMethod;        /* See SpreadIOMethods enum           */
+  unsigned long SmpIar;
+  unsigned long RAMErrLogOffset;        /* Heap offset to error log           */
+  unsigned long Reserved5;
+  unsigned long Reserved6;
+  unsigned long ProcessorHz;            /* Processor clock frequency in Hertz */
+  unsigned long ProcessorBusHz;         /* Processor bus clock frequency      */
+  unsigned long Reserved7;
+  unsigned long TimeBaseDivisor;        /* (Bus clocks per timebase tic)*1000 */
+  unsigned long WordWidth;              /* Word width in bits                 */
+  unsigned long PageSize;               /* Page size in bytes                 */
+  unsigned long CoherenceBlockSize;     /* Unit of transfer in/out of cache
+					   for which coherency is maintained;
+					   normally <= CacheLineSize.         */
+  unsigned long GranuleSize;            /* Unit of lock allocation to avoid   */
+					/*   false sharing of locks.          */
+
+  /* L1 Cache variables */
+  unsigned long CacheSize;              /* L1 Cache size in KB. This is the   */
+					/*   total size of the L1, whether    */
+					/*   combined or split                */
+  unsigned long CacheAttrib;            /* L1CACHE_TYPE                       */
+  unsigned long CacheAssoc;             /* L1 Cache associativity. Use this
+					   for combined cache. If split, put
+					   zeros here.                        */
+  unsigned long CacheLineSize;          /* L1 Cache line size in bytes. Use
+					   for combined cache. If split, put
+					   zeros here.                        */
+  /* For split L1 Cache: (= combined if combined cache) */
+  unsigned long I_CacheSize;
+  unsigned long I_CacheAssoc;
+  unsigned long I_CacheLineSize;
+  unsigned long D_CacheSize;
+  unsigned long D_CacheAssoc;
+  unsigned long D_CacheLineSize;
+
+  /* Translation Lookaside Buffer variables */
+  unsigned long TLBSize;                /* Total number of TLBs on the system */
+  unsigned long TLBAttrib;              /* Combined I+D or split TLB          */
+  unsigned long TLBAssoc;               /* TLB Associativity. Use this for
+					   combined TLB. If split, put zeros
+					   here.                              */
+  /* For split TLB: (= combined if combined TLB) */
+  unsigned long I_TLBSize;
+  unsigned long I_TLBAssoc;
+  unsigned long D_TLBSize;
+  unsigned long D_TLBAssoc;
+
+  unsigned long ExtendedVPD;            /* Offset to extended VPD area;
+					   null if unused                     */
+  } VPD;
+
+typedef enum _DEVICE_FLAGS {
+  Enabled = 0x4000,                     /* 1 - PCI device is enabled          */
+  Integrated = 0x2000,
+  Failed = 0x1000,                      /* 1 - device failed POST code tests  */
+  Static = 0x0800,                      /* 0 - dynamically configurable
+					   1 - static                         */
+  Dock = 0x0400,                        /* 0 - not a docking station device
+					   1 - is a docking station device    */
+  Boot = 0x0200,                        /* 0 - device cannot be used for BOOT
+					   1 - can be a BOOT device           */
+  Configurable = 0x0100,                /* 1 - device is configurable         */
+  Disableable = 0x80,                   /* 1 - device can be disabled         */
+  PowerManaged = 0x40,                  /* 0 - not managed; 1 - managed       */
+  ReadOnly = 0x20,                      /* 1 - device is read only            */
+  Removable = 0x10,                     /* 1 - device is removable            */
+  ConsoleIn = 0x08,
+  ConsoleOut = 0x04,
+  Input = 0x02,
+  Output = 0x01
+  } DEVICE_FLAGS;
+
+typedef enum _BUS_ID {
+  ISADEVICE = 0x01,
+  EISADEVICE = 0x02,
+  PCIDEVICE = 0x04,
+  PCMCIADEVICE = 0x08,
+  PNPISADEVICE = 0x10,
+  MCADEVICE = 0x20,
+  MXDEVICE = 0x40,                      /* Devices on mezzanine bus           */
+  PROCESSORDEVICE = 0x80,               /* Devices on processor bus           */
+  VMEDEVICE = 0x100,
+  } BUS_ID;
+
+typedef struct _DEVICE_ID {
+  unsigned long BusId;                  /* See BUS_ID enum above              */
+  unsigned long DevId;                  /* Big Endian format                  */
+  unsigned long SerialNum;              /* For multiple usage of a single
+					   DevId                              */
+  unsigned long Flags;                  /* See DEVICE_FLAGS enum above        */
+  unsigned char BaseType;               /* See pnp.h for bit definitions      */
+  unsigned char SubType;                /* See pnp.h for bit definitions      */
+  unsigned char Interface;              /* See pnp.h for bit definitions      */
+  unsigned char Spare;
+  } DEVICE_ID;
+
+typedef union _BUS_ACCESS {
+  struct _PnPAccess{
+    unsigned char CSN;
+    unsigned char LogicalDevNumber;
+    unsigned short ReadDataPort;
+    } PnPAccess;
+  struct _ISAAccess{
+    unsigned char SlotNumber;           /* ISA Slot Number generally not
+					   available; 0 if unknown            */
+    unsigned char LogicalDevNumber;
+    unsigned short ISAReserved;
+    } ISAAccess;
+  struct _MCAAccess{
+    unsigned char SlotNumber;
+    unsigned char LogicalDevNumber;
+    unsigned short MCAReserved;
+    } MCAAccess;
+  struct _PCMCIAAccess{
+    unsigned char SlotNumber;
+    unsigned char LogicalDevNumber;
+    unsigned short PCMCIAReserved;
+    } PCMCIAAccess;
+  struct _EISAAccess{
+    unsigned char SlotNumber;
+    unsigned char FunctionNumber;
+    unsigned short EISAReserved;
+    } EISAAccess;
+  struct _PCIAccess{
+    unsigned char BusNumber;
+    unsigned char DevFuncNumber;
+    unsigned short PCIReserved;
+    } PCIAccess;
+  struct _ProcBusAccess{
+    unsigned char BusNumber;
+    unsigned char BUID;
+    unsigned short ProcBusReserved;
+    } ProcBusAccess;
+  } BUS_ACCESS;
+
+/* Per logical device information */
+typedef struct _PPC_DEVICE {
+  DEVICE_ID DeviceId;
+  BUS_ACCESS BusAccess;
+
+  /* The following three are offsets into the DevicePnPHeap */
+  /* All are in PnP compressed format                       */
+  unsigned long AllocatedOffset;        /* Allocated resource description     */
+  unsigned long PossibleOffset;         /* Possible resource description      */
+  unsigned long CompatibleOffset;       /* Compatible device identifiers      */
+  } PPC_DEVICE;
+
+typedef enum _CPU_STATE {
+  CPU_GOOD = 0,                         /* CPU is present, and active         */
+  CPU_GOOD_FW = 1,                      /* CPU is present, and in firmware    */
+  CPU_OFF = 2,                          /* CPU is present, but inactive       */
+  CPU_FAILED = 3,                       /* CPU is present, but failed POST    */
+  CPU_NOT_PRESENT = 255                 /* CPU not present                    */
+  } CPU_STATE;
+
+typedef struct _PPC_CPU {
+  unsigned long CpuType;                /* Result of mfspr from Processor
+					   Version Register (PVR).
+					   PVR(0-15) = Version (e.g. 601)
+					   PVR(16-31 = EC Level               */
+  unsigned char CpuNumber;              /* CPU Number for this processor      */
+  unsigned char CpuState;               /* CPU State, see CPU_STATE enum      */
+  unsigned short Reserved;
+  } PPC_CPU;
+
+typedef struct _PPC_MEM {
+  unsigned long SIMMSize;               /* 0 - absent or bad
+					   8M, 32M (in MB)                    */
+  } PPC_MEM;
+
+typedef enum _MEM_USAGE {
+  Other = 0x8000,
+  ResumeBlock = 0x4000,                 /* for use by power management        */
+  SystemROM = 0x2000,                   /* Flash memory (populated)           */
+  UnPopSystemROM = 0x1000,              /* Unpopulated part of SystemROM area */
+  IOMemory = 0x0800,
+  SystemIO = 0x0400,
+  SystemRegs = 0x0200,
+  PCIAddr = 0x0100,
+  PCIConfig = 0x80,
+  ISAAddr = 0x40,
+  Unpopulated = 0x20,                   /* Unpopulated part of System Memory  */
+  Free = 0x10,                          /* Free part of System Memory         */
+  BootImage = 0x08,                     /* BootImage part of System Memory    */
+  FirmwareCode = 0x04,                  /* FirmwareCode part of System Memory */
+  FirmwareHeap = 0x02,                  /* FirmwareHeap part of System Memory */
+  FirmwareStack = 0x01                  /* FirmwareStack part of System Memory*/
+  } MEM_USAGE;
+
+typedef struct _MEM_MAP {
+  unsigned long Usage;                  /* See MEM_USAGE above                */
+  unsigned long BasePage;               /* Page number measured in 4KB pages  */
+  unsigned long PageCount;              /* Page count measured in 4KB pages   */
+  } MEM_MAP;
+
+typedef struct _RESIDUAL {
+  unsigned long ResidualLength;         /* Length of Residual                 */
+  unsigned char Version;                /* of this data structure             */
+  unsigned char Revision;               /* of this data structure             */
+  unsigned short EC;                    /* of this data structure             */
+  /* VPD */
+  VPD VitalProductData;
+  /* CPU */
+  unsigned short MaxNumCpus;            /* Max CPUs in this system            */
+  unsigned short ActualNumCpus;         /* ActualNumCpus < MaxNumCpus means   */
+					/* that there are unpopulated or      */
+					/* otherwise unusable cpu locations   */
+  PPC_CPU Cpus[MAX_CPUS];
+  /* Memory */
+  unsigned long TotalMemory;            /* Total amount of memory installed   */
+  unsigned long GoodMemory;             /* Total amount of good memory        */
+  unsigned long ActualNumMemSegs;
+  MEM_MAP Segs[MAX_MEM_SEGS];
+  unsigned long ActualNumMemories;
+  PPC_MEM Memories[MAX_MEMS];
+  /* Devices */
+  unsigned long ActualNumDevices;
+  PPC_DEVICE Devices[MAX_DEVICES];
+  unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE];
+  } RESIDUAL;
+
+
+extern RESIDUAL *res;
+extern void print_residual_device_info(void);
+extern PPC_DEVICE *residual_find_device(unsigned long BusMask,
+					unsigned char * DevID, int BaseType,
+					int SubType, int Interface, int n);
+extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag,
+				       int n);
+extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p,
+						    unsigned packet_type,
+						    int n);
+extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p,
+						    unsigned packet_type,
+						    int n);
+#endif /* __ASSEMBLY__ */
+#endif  /* ndef _RESIDUAL_ */
diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h
new file mode 100755
index 0000000..4bd66a7
--- /dev/null
+++ b/include/asm-ppc/sigcontext.h
@@ -0,0 +1,15 @@
+#ifndef _ASM_PPC_SIGCONTEXT_H
+#define _ASM_PPC_SIGCONTEXT_H
+
+#include <asm/ptrace.h>
+
+
+struct sigcontext_struct {
+	unsigned long	_unused[4];
+	int		signal;
+	unsigned long	handler;
+	unsigned long	oldmask;
+	struct pt_regs 	*regs;
+};
+
+#endif
diff --git a/include/asm-ppc/signal.h b/include/asm-ppc/signal.h
new file mode 100755
index 0000000..b11a28e
--- /dev/null
+++ b/include/asm-ppc/signal.h
@@ -0,0 +1,154 @@
+#ifndef _ASMPPC_SIGNAL_H
+#define _ASMPPC_SIGNAL_H
+
+#include <linux/types.h>
+
+/* Avoid too many header ordering problems.  */
+struct siginfo;
+
+/* Most things should be clean enough to redefine this at will, if care
+   is taken to make libc match.  */
+
+#define _NSIG		64
+#define _NSIG_BPW	32
+#define _NSIG_WORDS	(_NSIG / _NSIG_BPW)
+
+typedef unsigned long old_sigset_t;		/* at least 32 bits */
+
+typedef struct {
+	unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+#define SIGHUP		 1
+#define SIGINT		 2
+#define SIGQUIT		 3
+#define SIGILL		 4
+#define SIGTRAP		 5
+#define SIGABRT		 6
+#define SIGIOT		 6
+#define SIGBUS		 7
+#define SIGFPE		 8
+#define SIGKILL		 9
+#define SIGUSR1		10
+#define SIGSEGV		11
+#define SIGUSR2		12
+#define SIGPIPE		13
+#define SIGALRM		14
+#define SIGTERM		15
+#define SIGSTKFLT	16
+#define SIGCHLD		17
+#define SIGCONT		18
+#define SIGSTOP		19
+#define SIGTSTP		20
+#define SIGTTIN		21
+#define SIGTTOU		22
+#define SIGURG		23
+#define SIGXCPU		24
+#define SIGXFSZ		25
+#define SIGVTALRM	26
+#define SIGPROF		27
+#define SIGWINCH	28
+#define SIGIO		29
+#define SIGPOLL		SIGIO
+/*
+#define SIGLOST		29
+*/
+#define SIGPWR		30
+#define SIGSYS		31
+#define	SIGUNUSED	31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN	32
+#define SIGRTMAX	(_NSIG-1)
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK is not currently supported, but will allow sigaltstack(2).
+ * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP	0x00000001
+#define SA_NOCLDWAIT	0x00000002 /* not supported yet */
+#define SA_SIGINFO	0x00000004
+#define SA_ONSTACK	0x08000000
+#define SA_RESTART	0x10000000
+#define SA_NODEFER	0x40000000
+#define SA_RESETHAND	0x80000000
+
+#define SA_NOMASK	SA_NODEFER
+#define SA_ONESHOT	SA_RESETHAND
+#define SA_INTERRUPT	0x20000000 /* dummy -- ignored */
+
+#define SA_RESTORER	0x04000000
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK	1
+#define SS_DISABLE	2
+
+#define MINSIGSTKSZ	2048
+#define SIGSTKSZ	8192
+#ifdef __KERNEL__
+
+/*
+ * These values of sa_flags are used only by the kernel as part of the
+ * irq handling routines.
+ *
+ * SA_INTERRUPT is also used by the irq handling routines.
+ * SA_SHIRQ is for shared interrupt support on PCI and EISA.
+ */
+#define SA_PROBE		SA_ONESHOT
+#define SA_SAMPLE_RANDOM	SA_RESTART
+#define SA_SHIRQ		0x04000000
+#endif
+
+#define SIG_BLOCK          0	/* for blocking signals */
+#define SIG_UNBLOCK        1	/* for unblocking signals */
+#define SIG_SETMASK        2	/* for setting the signal mask */
+
+/* Type of a signal handler.  */
+typedef void (*__sighandler_t)(int);
+
+#define SIG_DFL	((__sighandler_t)0)	/* default signal handling */
+#define SIG_IGN	((__sighandler_t)1)	/* ignore signal */
+#define SIG_ERR	((__sighandler_t)-1)	/* error return from signal */
+
+struct old_sigaction {
+	__sighandler_t sa_handler;
+	old_sigset_t sa_mask;
+	unsigned long sa_flags;
+	void (*sa_restorer)(void);
+};
+
+struct sigaction {
+	__sighandler_t sa_handler;
+	unsigned long sa_flags;
+	void (*sa_restorer)(void);
+	sigset_t sa_mask;		/* mask last for extensibility */
+};
+
+struct k_sigaction {
+	struct sigaction sa;
+};
+
+typedef struct sigaltstack {
+	void *ss_sp;
+	int ss_flags;
+	size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+#include <asm/sigcontext.h>
+
+#endif
+
+#endif
diff --git a/include/asm-ppc/status_led.h b/include/asm-ppc/status_led.h
new file mode 100755
index 0000000..eb81f37
--- /dev/null
+++ b/include/asm-ppc/status_led.h
@@ -0,0 +1,77 @@
+/*
+ * asm/status_led.h
+ *
+ * MPC8xx/MPC8260/MPC5xx based status led support functions
+ */
+
+#ifndef __ASM_STATUS_LED_H__
+#define __ASM_STATUS_LED_H__
+
+/* if not overriden */
+#ifndef CONFIG_BOARD_SPECIFIC_LED
+# if defined(CONFIG_8xx)
+#  include <mpc8xx.h>
+# elif defined(CONFIG_8260)
+#  include <mpc8260.h>
+# elif defined(CONFIG_5xx)
+#  include <mpc5xx.h>
+# else
+#  error CPU specific Status LED header file missing.
+#endif
+
+/* led_id_t is unsigned long mask */
+typedef unsigned long led_id_t;
+
+static inline void __led_init (led_id_t mask, int state)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+#ifdef STATUS_LED_PAR
+	immr->STATUS_LED_PAR &= ~mask;
+#endif
+#ifdef STATUS_LED_ODR
+	immr->STATUS_LED_ODR &= ~mask;
+#endif
+
+#if (STATUS_LED_ACTIVE == 0)
+	if (state == STATUS_LED_ON)
+		immr->STATUS_LED_DAT &= ~mask;
+	else
+		immr->STATUS_LED_DAT |= mask;
+#else
+	if (state == STATUS_LED_ON)
+		immr->STATUS_LED_DAT |= mask;
+	else
+		immr->STATUS_LED_DAT &= ~mask;
+#endif
+#ifdef STATUS_LED_DIR
+	immr->STATUS_LED_DIR |= mask;
+#endif
+}
+
+static inline void __led_toggle (led_id_t mask)
+{
+	((immap_t *) CFG_IMMR)->STATUS_LED_DAT ^= mask;
+}
+
+static inline void __led_set (led_id_t mask, int state)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+#if (STATUS_LED_ACTIVE == 0)
+	if (state == STATUS_LED_ON)
+		immr->STATUS_LED_DAT &= ~mask;
+	else
+		immr->STATUS_LED_DAT |= mask;
+#else
+	if (state == STATUS_LED_ON)
+		immr->STATUS_LED_DAT |= mask;
+	else
+		immr->STATUS_LED_DAT &= ~mask;
+#endif
+
+}
+
+#endif
+
+#endif	/* __ASM_STATUS_LED_H__ */
diff --git a/include/asm-ppc/string.h b/include/asm-ppc/string.h
new file mode 100755
index 0000000..d912a6b
--- /dev/null
+++ b/include/asm-ppc/string.h
@@ -0,0 +1,29 @@
+#ifndef _PPC_STRING_H_
+#define _PPC_STRING_H_
+
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRNCPY
+#define __HAVE_ARCH_STRLEN
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRCAT
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_BCOPY
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMMOVE
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_MEMCHR
+
+extern int strcasecmp(const char *, const char *);
+extern int strncasecmp(const char *, const char *, int);
+extern char * strcpy(char *,const char *);
+extern char * strncpy(char *,const char *, __kernel_size_t);
+extern __kernel_size_t strlen(const char *);
+extern int strcmp(const char *,const char *);
+extern char * strcat(char *, const char *);
+extern void * memset(void *,int,__kernel_size_t);
+extern void * memcpy(void *,const void *,__kernel_size_t);
+extern void * memmove(void *,const void *,__kernel_size_t);
+extern int memcmp(const void *,const void *,__kernel_size_t);
+extern void * memchr(const void *,int,__kernel_size_t);
+
+#endif
diff --git a/include/asm-ppc/types.h b/include/asm-ppc/types.h
new file mode 100755
index 0000000..4ebbb9e
--- /dev/null
+++ b/include/asm-ppc/types.h
@@ -0,0 +1,50 @@
+#ifndef _PPC_TYPES_H
+#define _PPC_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+typedef struct {
+	__u32 u[4];
+} __attribute((aligned(16))) vector128;
+
+#ifdef __KERNEL__
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* DMA addresses are 32-bits wide */
+typedef u32 dma_addr_t;
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
new file mode 100755
index 0000000..f7aa55f
--- /dev/null
+++ b/include/asm-ppc/u-boot.h
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2000 - 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __U_BOOT_H__
+#define __U_BOOT_H__
+
+/*
+ * Board information passed to Linux kernel from U-Boot
+ *
+ * include/asm-ppc/u-boot.h
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef struct bd_info {
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+	unsigned long	bi_sramstart;	/* start of SRAM memory */
+	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
+	|| defined(CONFIG_E500)
+	unsigned long	bi_immr_base;	/* base of IMMR register */
+#endif
+#if defined(CONFIG_MPC5xxx)
+	unsigned long	bi_mbar_base;	/* base of internal registers */
+#endif
+#if defined(CONFIG_MPC83XX)
+	unsigned long	bi_immrbar;
+#endif
+#if defined(CONFIG_MPC8220)
+	unsigned long	bi_mbar_base;	/* base of internal registers */
+	unsigned long   bi_inpfreq;     /* Input Freq, In MHz */
+	unsigned long   bi_pcifreq;     /* PCI Freq, in MHz */
+	unsigned long   bi_pevfreq;     /* PEV Freq, in MHz */
+	unsigned long   bi_flbfreq;     /* Flexbus Freq, in MHz */
+	unsigned long   bi_vcofreq;     /* VCO Freq, in MHz */
+#endif
+	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6];	/* Ethernet adress */
+	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
+	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
+	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
+#if defined(CONFIG_CPM2)
+	unsigned long	bi_cpmfreq;	/* CPM_CLK Freq, in MHz */
+	unsigned long	bi_brgfreq;	/* BRG_CLK Freq, in MHz */
+	unsigned long	bi_sccfreq;	/* SCC_CLK Freq, in MHz */
+	unsigned long	bi_vco;		/* VCO Out from PLL, in MHz */
+#endif
+#if defined(CONFIG_MPC5xxx)
+	unsigned long	bi_ipbfreq;	/* IPB Bus Freq, in MHz */
+	unsigned long	bi_pcifreq;	/* PCI Bus Freq, in MHz */
+#endif
+	unsigned long	bi_baudrate;	/* Console Baudrate */
+#if defined(CONFIG_405)   || \
+    defined(CONFIG_405GP) || \
+    defined(CONFIG_405CR) || \
+    defined(CONFIG_405EP) || \
+    defined(CONFIG_440)
+	unsigned char	bi_s_version[4];	/* Version of this structure */
+	unsigned char	bi_r_version[32];	/* Version of the ROM (AMCC) */
+	unsigned int	bi_procfreq;	/* CPU (Internal) Freq, in Hz */
+	unsigned int	bi_plb_busfreq;	/* PLB Bus speed, in Hz */
+	unsigned int	bi_pci_busfreq;	/* PCI Bus speed, in Hz */
+	unsigned char	bi_pci_enetaddr[6];	/* PCI Ethernet MAC address */
+#endif
+#if defined(CONFIG_HYMOD)
+	hymod_conf_t	bi_hymod_conf;	/* hymod configuration information */
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+	/* second onboard ethernet port */
+	unsigned char   bi_enet1addr[6];
+#endif
+#ifdef CONFIG_HAS_ETH2
+	/* third onboard ethernet port */
+	unsigned char	bi_enet2addr[6];
+#endif
+#ifdef CONFIG_HAS_ETH3
+	unsigned char   bi_enet3addr[6];
+#endif
+
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR)
+	unsigned int	bi_opbfreq;		/* OPB clock in Hz */
+	int		bi_iic_fast[2];		/* Use fast i2c mode */
+#endif
+#if defined(CONFIG_NX823)
+	unsigned char	bi_sernum[8];
+#endif
+#if defined(CONFIG_4xx)
+#if defined(CONFIG_440GX)
+	int 		bi_phynum[4];           /* Determines phy mapping */
+	int 		bi_phymode[4];          /* Determines phy mode */
+#elif defined(CONFIG_405EP) || defined(CONFIG_440)
+	int 		bi_phynum[2];           /* Determines phy mapping */
+	int 		bi_phymode[2];          /* Determines phy mode */
+#else
+	int 		bi_phynum[1];           /* Determines phy mapping */
+	int 		bi_phymode[1];          /* Determines phy mode */
+#endif
+#endif /* defined(CONFIG_4xx) */
+} bd_t;
+
+#endif /* __ASSEMBLY__ */
+#endif	/* __U_BOOT_H__ */
diff --git a/include/at91rm9200_i2c.h b/include/at91rm9200_i2c.h
new file mode 100755
index 0000000..c2ec2f1
--- /dev/null
+++ b/include/at91rm9200_i2c.h
@@ -0,0 +1,126 @@
+/* ---------------------------------------------------------------------------- */
+/*	    ATMEL Microcontroller Software Support  -  ROUSSET	-		*/
+/* ---------------------------------------------------------------------------- */
+/*  The software is delivered "AS IS" without warranty or condition of any	*/
+/*  kind, either express, implied or statutory. This includes without		*/
+/*  limitation any warranty or condition with respect to merchantability or	*/
+/*  fitness for any particular purpose, or against the infringements of		*/
+/*  intellectual property rights of others.					*/
+/* ---------------------------------------------------------------------------- */
+/* File Name	       : at91rm9200_i2c.h					*/
+/* Object	       : AT91RM9200 / TWI definitions				*/
+/* Generated	       : AT91 SW Application Group  12/03/2002 (10:48:02)	*/
+/*										*/
+/* ---------------------------------------------------------------------------- */
+
+#ifndef AT91RM9200_TWI_H
+#define AT91RM9200_TWI_H
+
+/* ******************************************************************************/
+/*		SOFTWARE API DEFINITION	 FOR Two-wire Interface			*/
+/* ******************************************************************************/
+#ifndef __ASSEMBLY__
+
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR;	/* Control Register			*/
+	AT91_REG	 TWI_MMR;	/* Master Mode Register			*/
+	AT91_REG	 TWI_SMR;	/* Slave Mode Register			*/
+	AT91_REG	 TWI_IADR;	/* Internal Address Register		*/
+	AT91_REG	 TWI_CWGR;	/* Clock Waveform Generator Register	*/
+	AT91_REG	 Reserved0[3];
+	AT91_REG	 TWI_SR;	/* Status Register			*/
+	AT91_REG	 TWI_IER;	/* Interrupt Enable Register		*/
+	AT91_REG	 TWI_IDR;	/* Interrupt Disable Register		*/
+	AT91_REG	 TWI_IMR;	/* Interrupt Mask Register		*/
+	AT91_REG	 TWI_RHR;	/* Receive Holding Register		*/
+	AT91_REG	 TWI_THR;	/* Transmit Holding Register		*/
+	AT91_REG	 Reserved1[50];
+	AT91_REG	 TWI_RPR;	/* Receive Pointer Register		*/
+	AT91_REG	 TWI_RCR;	/* Receive Counter Register		*/
+	AT91_REG	 TWI_TPR;	/* Transmit Pointer Register		*/
+	AT91_REG	 TWI_TCR;	/* Transmit Counter Register		*/
+	AT91_REG	 TWI_RNPR;	/* Receive Next Pointer Register	*/
+	AT91_REG	 TWI_RNCR;	/* Receive Next Counter Register	*/
+	AT91_REG	 TWI_TNPR;	/* Transmit Next Pointer Register	*/
+	AT91_REG	 TWI_TNCR;	/* Transmit Next Counter Register	*/
+	AT91_REG	 TWI_PTCR;	/* PDC Transfer Control Register	*/
+	AT91_REG	 TWI_PTSR;	/* PDC Transfer Status Register		*/
+} AT91S_TWI, *AT91PS_TWI;
+
+#endif
+
+/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------		*/
+#define AT91C_TWI_START (0x1 <<	 0)	/* (TWI) Send a START Condition		*/
+#define AT91C_TWI_STOP	(0x1 <<	 1)	/* (TWI) Send a STOP Condition		*/
+#define AT91C_TWI_MSEN	(0x1 <<	 2)	/* (TWI) TWI Master Transfer Enabled	*/
+#define AT91C_TWI_MSDIS (0x1 <<	 3)	/* (TWI) TWI Master Transfer Disabled	*/
+#define AT91C_TWI_SVEN	(0x1 <<	 4)	/* (TWI) TWI Slave Transfer Enabled	*/
+#define AT91C_TWI_SVDIS (0x1 <<	 5)	/* (TWI) TWI Slave Transfer Disabled	*/
+#define AT91C_TWI_SWRST (0x1 <<	 7)	/* (TWI) Software Reset		*/
+/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------	*/
+#define AT91C_TWI_IADRSZ      (0x3 <<  8) /* (TWI) Internal Device Address Size */
+#define	  AT91C_TWI_IADRSZ_NO	  (0x0 <<  8) /* (TWI) No internal device address	*/
+#define	  AT91C_TWI_IADRSZ_1_BYTE (0x1 <<  8) /* (TWI) One-byte internal device address */
+#define	  AT91C_TWI_IADRSZ_2_BYTE (0x2 <<  8) /* (TWI) Two-byte internal device address */
+#define	  AT91C_TWI_IADRSZ_3_BYTE (0x3 <<  8) /* (TWI) Three-byte internal device address */
+#define AT91C_TWI_MREAD (0x1 << 12)	/* (TWI) Master Read Direction		*/
+#define AT91C_TWI_DADR	(0x7F <<  6)	/* (TWI) Device Address			*/
+/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------	*/
+#define AT91C_TWI_SADR	(0x7F << 16)	/* (TWI) Slave Device Address		*/
+/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------	*/
+#define AT91C_TWI_CLDIV	 (0xFF <<  0)	/* (TWI) Clock Low Divider		*/
+#define AT91C_TWI_CHDIV	 (0xFF <<  8)	/* (TWI) Clock High Divider		*/
+#define AT91C_TWI_CKDIV	 (0x7 << 16)	/* (TWI) Clock Divider			*/
+/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------		*/
+#define AT91C_TWI_TXCOMP (0x1 <<  0)	/* (TWI) Transmission Completed		*/
+#define AT91C_TWI_RXRDY	 (0x1 <<  1)	/* (TWI) Receive holding register ReaDY */
+#define AT91C_TWI_TXRDY	 (0x1 <<  2)	/* (TWI) Transmit holding register ReaDY*/
+#define AT91C_TWI_SVREAD (0x1 <<  3)	/* (TWI) Slave Read			*/
+#define AT91C_TWI_SVACC	 (0x1 <<  4)	/* (TWI) Slave Access			*/
+#define AT91C_TWI_GCACC	 (0x1 <<  5)	/* (TWI) General Call Access		*/
+#define AT91C_TWI_OVRE	 (0x1 <<  6)	/* (TWI) Overrun Error			*/
+#define AT91C_TWI_UNRE	 (0x1 <<  7)	/* (TWI) Underrun Error			*/
+#define AT91C_TWI_NACK	 (0x1 <<  8)	/* (TWI) Not Acknowledged		*/
+#define AT91C_TWI_ARBLST (0x1 <<  9)	/* (TWI) Arbitration Lost		*/
+/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
+/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register ------- */
+/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------	*/
+
+/*
+    i2c Support for Atmel's AT91RM9200 Two-Wire Interface
+
+    (c) Rick Bronson
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef AT91_I2C_H
+#define AT91_I2C_H
+
+#define AT91C_TWI_CLOCK		100000
+#define AT91C_TWI_SCLOCK	(10 * AT91C_MASTER_CLOCK / AT91C_TWI_CLOCK)
+#define AT91C_TWI_CKDIV1	(2 << 16)	/* TWI clock divider.  NOTE: see Errata #22 */
+
+#if (AT91C_TWI_SCLOCK % 10) >= 5
+#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 5)
+#else
+#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 6)
+#endif
+#define AT91C_TWI_CLDIV3 ((AT91C_TWI_CLDIV2 + (4 - AT91C_TWI_CLDIV2 % 4)) >> 2)
+
+#define AT91C_EEPROM_I2C_ADDRESS	(0x50 << 16)
+
+#endif	/* __ASSEMBLY__ */
+#endif	/* AT91RM9200_TWI_H */
diff --git a/include/at91rm9200_net.h b/include/at91rm9200_net.h
new file mode 100755
index 0000000..f799206
--- /dev/null
+++ b/include/at91rm9200_net.h
@@ -0,0 +1,57 @@
+/*
+ * Ethernet:	An implementation of the Ethernet Device Driver suite for the
+ *		uClinux 2.0.38 operating system. This Driver has been developed
+ *		for AT75C220 board.
+ *
+ * NOTE:	The driver is implemented for one MAC
+ *
+ * Version:	@(#)at91rm9200_net.h	1.0.0	01/10/2001
+ *
+ * Authors:	Lineo Inc <www.lineo.com>
+ *
+ *
+ *		This program is free software; you can redistribute it and/or
+ *		modify it under the terms of the GNU General Public License
+ *		as published by the Free Software Foundation; either version
+ *		2 of the License, or (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_ETHERNET
+#define AT91RM9200_ETHERNET
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#define FALSE 0
+#define TRUE 1
+
+
+#define ETHERNET_ADDRESS_SIZE           6
+
+typedef unsigned char UCHAR;
+
+/* Interface to drive the physical layer */
+typedef struct _AT91S_PhyOps
+{
+	unsigned char (*Init)(AT91S_EMAC *pmac);
+	unsigned int (*IsPhyConnected)(AT91S_EMAC  *pmac);
+	unsigned char (*GetLinkSpeed)(AT91S_EMAC *pmac);
+	unsigned char (*AutoNegotiate)(AT91S_EMAC *pmac, int *);
+
+} AT91S_PhyOps,*AT91PS_PhyOps;
+
+
+#define EMAC_DESC_DONE 0x00000001  /* ownership bit */
+#define EMAC_DESC_WRAP 0x00000002  /* bit for wrap */
+
+/******************  function prototypes **********************/
+
+/* MII functions */
+void at91rm9200_EmacEnableMDIO(AT91PS_EMAC p_mac);
+void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac);
+UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput);
+UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput);
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops);
+
+#endif /* AT91RM9200_ETHERNET */
diff --git a/include/ata.h b/include/ata.h
new file mode 100755
index 0000000..8584226
--- /dev/null
+++ b/include/ata.h
@@ -0,0 +1,258 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Most of the following information was derived from the document
+ * "Information Technology - AT Attachment-3 Interface (ATA-3)"
+ * which can be found at:
+ * http://www.dt.wdc.com/ata/ata-3/ata3r5v.zip
+ * ftp://poctok.iae.nsk.su/pub/asm/Documents/IDE/ATA3R5V.ZIP
+ * ftp://ftp.fee.vutbr.cz/pub/doc/io/ata/ata-3/ata3r5v.zip
+ */
+
+#ifndef	_ATA_H
+#define _ATA_H
+
+/* Register addressing depends on the hardware design; for instance,
+ * 8-bit (register) and 16-bit (data) accesses might use different
+ * address spaces. This is implemented by the following definitions.
+ */
+#ifndef CFG_ATA_STRIDE
+#define CFG_ATA_STRIDE	1
+#endif
+
+#define ATA_IO_DATA(x)	(CFG_ATA_DATA_OFFSET+((x) * CFG_ATA_STRIDE))
+#define ATA_IO_REG(x)	(CFG_ATA_REG_OFFSET +((x) * CFG_ATA_STRIDE))
+#define ATA_IO_ALT(x)	(CFG_ATA_ALT_OFFSET +((x) * CFG_ATA_STRIDE))
+
+/*
+ * I/O Register Descriptions
+ */
+#define ATA_DATA_REG	ATA_IO_DATA(0)
+#define ATA_ERROR_REG	ATA_IO_REG(1)
+#define ATA_SECT_CNT	ATA_IO_REG(2)
+#define ATA_SECT_NUM	ATA_IO_REG(3)
+#define ATA_CYL_LOW	ATA_IO_REG(4)
+#define ATA_CYL_HIGH	ATA_IO_REG(5)
+#define ATA_DEV_HD	ATA_IO_REG(6)
+#define ATA_COMMAND	ATA_IO_REG(7)
+#define ATA_DATA_EVEN	ATA_IO_REG(8)
+#define ATA_DATA_ODD	ATA_IO_REG(9)
+#define ATA_STATUS	ATA_COMMAND
+#define ATA_DEV_CTL	ATA_IO_ALT(6)
+#define ATA_LBA_LOW	ATA_SECT_NUM
+#define ATA_LBA_MID	ATA_CYL_LOW
+#define ATA_LBA_HIGH	ATA_CYL_HIGH
+#define ATA_LBA_SEL	ATA_DEV_CTL
+
+/*
+ * Status register bits
+ */
+#define ATA_STAT_BUSY	0x80	/* Device Busy			*/
+#define ATA_STAT_READY	0x40	/* Device Ready			*/
+#define ATA_STAT_FAULT	0x20	/* Device Fault			*/
+#define ATA_STAT_SEEK	0x10	/* Device Seek Complete		*/
+#define ATA_STAT_DRQ	0x08	/* Data Request (ready)		*/
+#define ATA_STAT_CORR	0x04	/* Corrected Data Error		*/
+#define ATA_STAT_INDEX	0x02	/* Vendor specific		*/
+#define ATA_STAT_ERR	0x01	/* Error			*/
+
+/*
+ * Device / Head Register Bits
+ */
+#define ATA_DEVICE(x)	((x & 1)<<4)
+#define ATA_LBA		0xE0
+
+/*
+ * ATA Commands (only mandatory commands listed here)
+ */
+#define ATA_CMD_READ	0x20	/* Read Sectors (with retries)	*/
+#define ATA_CMD_READN	0x21	/* Read Sectors ( no  retries)	*/
+#define ATA_CMD_WRITE	0x30	/* Write Sectores (with retries)*/
+#define ATA_CMD_WRITEN	0x31	/* Write Sectors  ( no  retries)*/
+#define ATA_CMD_VRFY	0x40	/* Read Verify  (with retries)	*/
+#define ATA_CMD_VRFYN	0x41	/* Read verify  ( no  retries)	*/
+#define ATA_CMD_SEEK	0x70	/* Seek				*/
+#define ATA_CMD_DIAG	0x90	/* Execute Device Diagnostic	*/
+#define ATA_CMD_INIT	0x91	/* Initialize Device Parameters	*/
+#define ATA_CMD_RD_MULT	0xC4	/* Read Multiple		*/
+#define ATA_CMD_WR_MULT	0xC5	/* Write Multiple		*/
+#define ATA_CMD_SETMULT	0xC6	/* Set Multiple Mode		*/
+#define ATA_CMD_RD_DMA	0xC8	/* Read DMA (with retries)	*/
+#define ATA_CMD_RD_DMAN	0xC9	/* Read DMS ( no  retries)	*/
+#define ATA_CMD_WR_DMA	0xCA	/* Write DMA (with retries)	*/
+#define ATA_CMD_WR_DMAN	0xCB	/* Write DMA ( no  retires)	*/
+#define ATA_CMD_IDENT	0xEC	/* Identify Device		*/
+#define ATA_CMD_SETF	0xEF	/* Set Features			*/
+#define ATA_CMD_CHK_PWR	0xE5	/* Check Power Mode		*/
+
+#define ATA_CMD_READ_EXT 0x24	/* Read Sectors (with retries)	with 48bit addressing */
+#define ATA_CMD_WRITE_EXT	0x34	/* Write Sectores (with retries) with 48bit addressing */
+#define ATA_CMD_VRFY_EXT	0x42	/* Read Verify	(with retries)	with 48bit addressing */
+
+/*
+ * ATAPI Commands
+ */
+#define ATAPI_CMD_IDENT 0xA1 /* Identify AT Atachment Packed Interface Device */
+#define ATAPI_CMD_PACKET 0xA0 /* Packed Command */
+
+
+#define ATAPI_CMD_INQUIRY 0x12
+#define ATAPI_CMD_REQ_SENSE 0x03
+#define ATAPI_CMD_READ_CAP 0x25
+#define ATAPI_CMD_START_STOP 0x1B
+#define ATAPI_CMD_READ_12 0xA8
+
+
+#define ATA_GET_ERR()	inb(ATA_STATUS)
+#define ATA_GET_STAT()	inb(ATA_STATUS)
+#define ATA_OK_STAT(stat,good,bad)	(((stat)&((good)|(bad)))==(good))
+#define ATA_BAD_R_STAT	(ATA_STAT_BUSY	| ATA_STAT_ERR)
+#define ATA_BAD_W_STAT	(ATA_BAD_R_STAT	| ATA_STAT_FAULT)
+#define ATA_BAD_STAT	(ATA_BAD_R_STAT	| ATA_STAT_DRQ)
+#define ATA_DRIVE_READY	(ATA_READY_STAT	| ATA_STAT_SEEK)
+#define ATA_DATA_READY	(ATA_STAT_DRQ)
+
+#define ATA_BLOCKSIZE	512	/* bytes */
+#define ATA_BLOCKSHIFT	9	/* 2 ^ ATA_BLOCKSIZESHIFT = 512 */
+#define ATA_SECTORWORDS	(512 / sizeof(unsigned long))
+
+#ifndef ATA_RESET_TIME
+#define ATA_RESET_TIME	60	/* spec allows up to 31 seconds */
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * structure returned by ATA_CMD_IDENT, as per ANSI ATA2 rev.2f spec
+ */
+typedef struct hd_driveid {
+	unsigned short	config;		/* lots of obsolete bit flags */
+	unsigned short	cyls;		/* "physical" cyls */
+	unsigned short	reserved2;	/* reserved (word 2) */
+	unsigned short	heads;		/* "physical" heads */
+	unsigned short	track_bytes;	/* unformatted bytes per track */
+	unsigned short	sector_bytes;	/* unformatted bytes per sector */
+	unsigned short	sectors;	/* "physical" sectors per track */
+	unsigned short	vendor0;	/* vendor unique */
+	unsigned short	vendor1;	/* vendor unique */
+	unsigned short	vendor2;	/* vendor unique */
+	unsigned char	serial_no[20];	/* 0 = not_specified */
+	unsigned short	buf_type;
+	unsigned short	buf_size;	/* 512 byte increments; 0 = not_specified */
+	unsigned short	ecc_bytes;	/* for r/w long cmds; 0 = not_specified */
+	unsigned char	fw_rev[8];	/* 0 = not_specified */
+	unsigned char	model[40];	/* 0 = not_specified */
+	unsigned char	max_multsect;	/* 0=not_implemented */
+	unsigned char	vendor3;	/* vendor unique */
+	unsigned short	dword_io;	/* 0=not_implemented; 1=implemented */
+	unsigned char	vendor4;	/* vendor unique */
+	unsigned char	capability;	/* bits 0:DMA 1:LBA 2:IORDYsw 3:IORDYsup*/
+	unsigned short	reserved50;	/* reserved (word 50) */
+	unsigned char	vendor5;	/* vendor unique */
+	unsigned char	tPIO;		/* 0=slow, 1=medium, 2=fast */
+	unsigned char	vendor6;	/* vendor unique */
+	unsigned char	tDMA;		/* 0=slow, 1=medium, 2=fast */
+	unsigned short	field_valid;	/* bits 0:cur_ok 1:eide_ok */
+	unsigned short	cur_cyls;	/* logical cylinders */
+	unsigned short	cur_heads;	/* logical heads */
+	unsigned short	cur_sectors;	/* logical sectors per track */
+	unsigned short	cur_capacity0;	/* logical total sectors on drive */
+	unsigned short	cur_capacity1;	/*  (2 words, misaligned int)     */
+	unsigned char	multsect;	/* current multiple sector count */
+	unsigned char	multsect_valid;	/* when (bit0==1) multsect is ok */
+	unsigned int	lba_capacity;	/* total number of sectors */
+	unsigned short	dma_1word;	/* single-word dma info */
+	unsigned short	dma_mword;	/* multiple-word dma info */
+	unsigned short  eide_pio_modes; /* bits 0:mode3 1:mode4 */
+	unsigned short  eide_dma_min;	/* min mword dma cycle time (ns) */
+	unsigned short  eide_dma_time;	/* recommended mword dma cycle time (ns) */
+	unsigned short  eide_pio;       /* min cycle time (ns), no IORDY  */
+	unsigned short  eide_pio_iordy; /* min cycle time (ns), with IORDY */
+	unsigned short	words69_70[2];	/* reserved words 69-70 */
+	unsigned short	words71_74[4];	/* reserved words 71-74 */
+	unsigned short  queue_depth;	/*  */
+	unsigned short  words76_79[4];	/* reserved words 76-79 */
+	unsigned short  major_rev_num;	/*  */
+	unsigned short  minor_rev_num;	/*  */
+	unsigned short  command_set_1;	/* bits 0:Smart 1:Security 2:Removable 3:PM */
+	unsigned short	command_set_2;	/* bits 14:Smart Enabled 13:0 zero 10:lba48 support*/
+	unsigned short  cfsse;		/* command set-feature supported extensions */
+	unsigned short  cfs_enable_1;	/* command set-feature enabled */
+	unsigned short  cfs_enable_2;	/* command set-feature enabled */
+	unsigned short  csf_default;	/* command set-feature default */
+	unsigned short  dma_ultra;	/*  */
+	unsigned short	word89;		/* reserved (word 89) */
+	unsigned short	word90;		/* reserved (word 90) */
+	unsigned short	CurAPMvalues;	/* current APM values */
+	unsigned short	word92;		/* reserved (word 92) */
+	unsigned short	hw_config;	/* hardware config */
+	unsigned short	words94_99[6];/* reserved words 94-99 */
+	/*unsigned long long  lba48_capacity; /--* 4 16bit values containing lba 48 total number of sectors */
+	unsigned short	lba48_capacity[4]; /* 4 16bit values containing lba 48 total number of sectors */
+	unsigned short	words104_125[22];/* reserved words 104-125 */
+	unsigned short	last_lun;	/* reserved (word 126) */
+	unsigned short	word127;	/* reserved (word 127) */
+	unsigned short	dlf;		/* device lock function
+					 * 15:9	reserved
+					 * 8	security level 1:max 0:high
+					 * 7:6	reserved
+					 * 5	enhanced erase
+					 * 4	expire
+					 * 3	frozen
+					 * 2	locked
+					 * 1	en/disabled
+					 * 0	capability
+					 */
+	unsigned short  csfo;		/* current set features options
+					 * 15:4	reserved
+					 * 3	auto reassign
+					 * 2	reverting
+					 * 1	read-look-ahead
+					 * 0	write cache
+					 */
+	unsigned short	words130_155[26];/* reserved vendor words 130-155 */
+	unsigned short	word156;
+	unsigned short	words157_159[3];/* reserved vendor words 157-159 */
+	unsigned short	words160_255[95];/* reserved words 160-255 */
+} hd_driveid_t;
+
+
+/*
+ * PIO Mode Configuration
+ *
+ * See ATA-3 (AT Attachment-3 Interface) documentation, Figure 14 / Table 21
+ */
+
+typedef struct {
+	unsigned int	t_setup;	/* Setup  Time in [ns] or clocks	*/
+	unsigned int	t_length;	/* Length Time in [ns] or clocks	*/
+	unsigned int	t_hold;		/* Hold   Time in [ns] or clocks	*/
+}
+pio_config_t;
+
+#define	IDE_MAX_PIO_MODE	4	/* max suppurted PIO mode		*/
+
+/* ------------------------------------------------------------------------- */
+
+#endif /* _ATA_H */
diff --git a/include/bcm5221.h b/include/bcm5221.h
new file mode 100755
index 0000000..6fb94aa
--- /dev/null
+++ b/include/bcm5221.h
@@ -0,0 +1,104 @@
+/*
+ * Broadcom BCM5221 Ethernet PHY
+ *
+ * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
+ * Anders Larsen <alarsen@rea.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define	BCM5221_BMCR 		0	/* Basic Mode Control Register */
+#define BCM5221_BMSR		1	/* Basic Mode Status Register */
+#define BCM5221_PHYID1		2	/* PHY Identifier Register 1 */
+#define BCM5221_PHYID2		3	/* PHY Identifier Register 2 */
+#define BCM5221_ANAR		4	/* Auto-negotiation Advertisement Register  */
+#define BCM5221_ANLPAR		5	/* Auto-negotiation Link Partner Ability Register */
+#define BCM5221_ANER		6	/* Auto-negotiation Expansion Register  */
+#define BCM5221_ACSR		24	/* Auxiliary Control/Status Register */
+#define BCM5221_INTR		26	/* Interrupt Register */
+
+/* --Bit definitions: BCM5221_BMCR */
+#define BCM5221_RESET		(1 << 15)	/* 1= Software Reset; 0=Normal Operation */
+#define BCM5221_LOOPBACK	(1 << 14)	/* 1=loopback Enabled; 0=Normal Operation */
+#define BCM5221_SPEED_SELECT	(1 << 13)	/* 1=100Mbps; 0=10Mbps */
+#define BCM5221_AUTONEG		(1 << 12)
+#define BCM5221_POWER_DOWN	(1 << 11)
+#define BCM5221_ISOLATE		(1 << 10)
+#define BCM5221_RESTART_AUTONEG	(1 << 9)
+#define BCM5221_DUPLEX_MODE	(1 << 8)
+#define BCM5221_COLLISION_TEST	(1 << 7)
+
+/*--Bit definitions: BCM5221_BMSR */
+#define BCM5221_100BASE_T4	(1 << 15)
+#define BCM5221_100BASE_TX_FD	(1 << 14)
+#define BCM5221_100BASE_TX_HD	(1 << 13)
+#define BCM5221_10BASE_T_FD	(1 << 12)
+#define BCM5221_10BASE_T_HD	(1 << 11)
+#define BCM5221_MF_PREAMB_SUPPR	(1 << 6)
+#define BCM5221_AUTONEG_COMP	(1 << 5)
+#define BCM5221_REMOTE_FAULT	(1 << 4)
+#define BCM5221_AUTONEG_ABILITY	(1 << 3)
+#define BCM5221_LINK_STATUS	(1 << 2)
+#define BCM5221_JABBER_DETECT	(1 << 1)
+#define BCM5221_EXTEND_CAPAB	(1 << 0)
+
+/*--definitions: BCM5221_PHYID1 */
+#define BCM5221_PHYID1_OUI	0x1018
+#define BCM5221_LSB_MASK	0x3F
+
+/*--Bit definitions: BCM5221_ANAR, BCM5221_ANLPAR */
+#define BCM5221_NP		(1 << 15)
+#define BCM5221_ACK		(1 << 14)
+#define BCM5221_RF		(1 << 13)
+#define BCM5221_FCS		(1 << 10)
+#define BCM5221_T4		(1 << 9)
+#define BCM5221_TX_FDX		(1 << 8)
+#define BCM5221_TX_HDX		(1 << 7)
+#define BCM5221_10_FDX		(1 << 6)
+#define BCM5221_10_HDX		(1 << 5)
+#define BCM5221_AN_IEEE_802_3	0x0001
+
+/*--Bit definitions: BCM5221_ANER */
+#define BCM5221_PDF		(1 << 4)
+#define BCM5221_LP_NP_ABLE	(1 << 3)
+#define BCM5221_NP_ABLE		(1 << 2)
+#define BCM5221_PAGE_RX		(1 << 1)
+#define BCM5221_LP_AN_ABLE	(1 << 0)
+
+/*--Bit definitions: BCM5221_ACSR */
+#define BCM5221_100		(1 << 1)
+#define BCM5221_FDX		(1 << 0)
+
+/*--Bit definitions: BCM5221_INTR */
+#define BCM5221_FDX_LED		(1 << 15)
+#define BCM5221_INTR_ENABLE	(1 << 14)
+#define BCM5221_FDX_MASK	(1 << 11)
+#define BCM5221_SPD_MASK	(1 << 10)
+#define BCM5221_LINK_MASK	(1 << 9)
+#define BCM5221_INTR_MASK	(1 << 8)
+#define BCM5221_FDX_CHG		(1 << 3)
+#define BCM5221_SPD_CHG		(1 << 2)
+#define BCM5221_LINK_CHG	(1 << 1)
+#define BCM5221_INTR_STATUS	(1 << 0)
+
+/******************  function prototypes **********************/
+unsigned int  bcm5221_IsPhyConnected(AT91PS_EMAC p_mac);
+unsigned char bcm5221_GetLinkSpeed(AT91PS_EMAC p_mac);
+unsigned char bcm5221_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
+unsigned char bcm5221_InitPhy(AT91PS_EMAC p_mac);
diff --git a/include/bedbug/bedbug.h b/include/bedbug/bedbug.h
new file mode 100755
index 0000000..471215e
--- /dev/null
+++ b/include/bedbug/bedbug.h
@@ -0,0 +1,42 @@
+/* $Id$ */
+
+#ifndef _BEDBUG_H
+#define _BEDBUG_H
+
+#ifndef NULL
+#define NULL	0
+#endif
+
+#define _USE_PROTOTYPES
+
+#ifndef isblank
+#define isblank(c) isspace((int)(c))
+#endif
+
+#ifndef __P
+#if defined(_USE_PROTOTYPES) && (defined(__STDC__) || defined(__cplusplus))
+#define __P(protos)	protos		/* full-blown ANSI C */
+#else
+#define __P(protos)	()		/* traditional C preprocessor */
+#endif
+#endif
+
+#define assert( condition ) if( (condition) ) _exit(0)
+
+#endif /* _BEDBUG_H */
+
+
+/*
+ * Copyright (c) 2001 William L. Pitts
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/include/bedbug/ppc.h b/include/bedbug/ppc.h
new file mode 100755
index 0000000..9cc8f9f
--- /dev/null
+++ b/include/bedbug/ppc.h
@@ -0,0 +1,413 @@
+/* $Id$ */
+
+#ifndef _PPC_H
+#define _PPC_H
+
+/*======================================================================
+ *
+ *  OPERANDS
+ *
+ *======================================================================*/
+
+enum OP_FIELD {
+  O_AA = 1, O_BD, O_BI, O_BO, O_crbD, O_crbA, O_crbB, O_CRM, O_d, O_frC, O_frD,
+  O_frS, O_IMM, O_LI, O_LK, O_MB, O_ME, O_NB, O_OE, O_rA, O_rB, O_Rc, O_rD,
+  O_rS, O_SH, O_SIMM, O_SR, O_TO, O_UIMM, O_crfD, O_crfS, O_L, O_spr, O_tbr,
+  O_cr2 };
+
+struct operand {
+  enum OP_FIELD	field;		/* The operand identifier from the
+				   enum above */
+
+  char *	name;		/* Symbolic name of this operand */
+
+  unsigned int	bits;		/* The number of bits used by this
+				   operand */
+
+  unsigned int	shift;		/* How far to the right the operand
+				   should be shifted so that it is
+				   aligned at the beginning of the
+				   word */
+
+  unsigned int	hint;		/* A bitwise-inclusive-OR of the
+				   values shown below.  These are used
+				   tell the disassembler how to print
+				   this operand */
+};
+
+/* Values for operand hint */
+#define OH_SILENT	0x01	/* dont print this operand */
+#define OH_ADDR		0x02	/* this operand is an address */
+#define OH_REG		0x04	/* this operand is a register */
+#define OH_SPR		0x08	/* this operand is an SPR */
+#define OH_TBR		0x10	/* this operand is a TBR */
+#define OH_OFFSET	0x20	/* this operand is an offset */
+#define OH_LITERAL      0x40    /* a literal string */
+
+
+/*======================================================================
+ *
+ *  OPCODES
+ *
+ *======================================================================*/
+
+/* From the MPCxxx instruction set documentation, all instructions are
+ * 32 bits long and word aligned.  Bits 0-5 always specify the primary
+ * opcode.  Many instructions also have an extended opcode.
+ */
+
+#define GET_OPCD(i) (((unsigned long)(i) >> 26) & 0x3f)
+#define MAKE_OPCODE(i) ((((unsigned long)(i)) & 0x3f) << 26)
+
+/* The MPC860 User's Manual, Appendix D.4 contains the definitions of the
+ * instruction forms
+ */
+
+
+/*-------------------------------------------------
+ *              I-Form Instructions:
+ * bX
+ *-------------------------------------------------
+ * OPCD |           LI                       |AA|LK
+ *-------------------------------------------------*/
+
+#define I_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
+#define I_MASK I_OPCODE(0x3f,0x1,0x1)
+
+
+/*-------------------------------------------------
+ *              B-Form Instructions:
+ * bcX
+ *-------------------------------------------------
+ * OPCD |    BO   |  BI  |   BD              |AA|LK
+ *-------------------------------------------------*/
+
+#define B_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
+#define B_MASK B_OPCODE(0x3f,0x1,0x1)
+
+
+/*-------------------------------------------------
+ *             SC-Form Instructions:
+ * sc
+ *-------------------------------------------------
+ * OPCD | 00000 | 00000 | 00000000000000       |1|0
+ *-------------------------------------------------*/
+
+#define SC_OPCODE(i) (MAKE_OPCODE(i) | 0x2)
+#define SC_MASK SC_OPCODE(0x3f)
+
+
+/*-------------------------------------------------
+ *             D-Form Instructions:
+ * addi addic addic. addis andi. andis. cmpi cmpli
+ * lbz lbzu lha lhau lhz lhzu lmw lwz lwzu mulli
+ * ori oris stb stbu sth sthu stmw stw stwu subfic
+ * twi xori xoris
+ *-------------------------------------------------
+ * OPCD |   D    |   A   |            d
+ * OPCD |   D    |   A   |           SIMM
+ * OPCD |   S    |   A   |            d
+ * OPCD |   S    |   A   |           UIMM
+ * OPCD |crfD|0|L|   A   |           SIMM
+ * OPCD |crfD|0|L|   A   |           UIMM
+ * OPCD |   TO   |   A   |           SIMM
+ *-------------------------------------------------*/
+
+#define D_OPCODE(i) MAKE_OPCODE(i)
+#define D_MASK MAKE_OPCODE(0x3f)
+
+
+/*-------------------------------------------------
+ *            DS-Form Instructions:
+ * (none supported by MPC860)
+ *-------------------------------------------------
+ * OPCD |   D    |   A   |          ds          |XO
+ * OPCD |   S    |   A   |          ds          |XO
+ *-------------------------------------------------*/
+
+#define DS_OPCODE(i,xo) (MAKE_OPCODE(i) | ((xo) & 0x3))
+#define DS_MASK DS_OPCODE(0x3f,0x1)
+
+
+/*---------------------------------------------------
+ *            X-Form Instructions:
+ * andX andcX cmp cmpl cntlzwX dcbf dcbi dcbst dcbt
+ * dcbtst dcbz eciwx ecowx eieio eqvX extsbX extshX
+ * icbi lbzux lbxz lhaux lhax lhbrx lhzux lhxz lswi
+ * lswx lwarx lwbrx lwzux lwxz mcrfs mcrxr mfcr
+ * mfmsr mfsr mfsrin mtmsr mtsr mtsrin nandX norX
+ * orX orcX slwX srawX srawiX srwX stbux stbx
+ * sthbrx sthuxsthx stswi stswx stwbrx stwcx. stwux
+ * stwx sync tlbie tlbld tlbli tlbsync tw xorX
+ *---------------------------------------------------
+ * OPCD |   D    |    A   |    B   |      XO      |0
+ * OPCD |   D    |    A   |   NB   |      XO      |0
+ * OPCD |   D    |  00000 |    B   |      XO      |0
+ * OPCD |   D    |  00000 |  00000 |      XO      |0
+ * OPCD |   D    |0|  SR  |  00000 |      XO      |0
+ * OPCD |   S    |    A   |    B   |      XO      |Rc
+ * OPCD |   S    |    A   |    B   |      XO      |1
+ * OPCD |   S    |    A   |    B   |      XO      |0
+ * OPCD |   S    |    A   |   NB   |      XO      |0
+ * OPCD |   S    |    A   |  00000 |      XO      |Rc
+ * OPCD |   S    |  00000 |    B   |      XO      |0
+ * OPCD |   S    |  00000 |  00000 |      XO      |0
+ * OPCD |   S    |0|  SR  |  00000 |      XO      |0
+ * OPCD |   S    |    A   |   SH   |      XO      |Rc
+ * OPCD |crfD|0|L|    A   |   SH   |      XO      |0
+ * OPCD |crfD |00|    A   |    B   |      XO      |0
+ * OPCD |crfD |00|crfS |00|  00000 |      XO      |0
+ * OPCD |crfD |00|  00000 |  00000 |      XO      |0
+ * OPCD |crfD |00|  00000 | IMM  |0|      XO      |Rc
+ * OPCD |   TO   |    A   |    B   |      XO      |0
+ * OPCD |   D    |  00000 |    B   |      XO      |Rc
+ * OPCD |   D    |  00000 |  00000 |      XO      |Rc
+ * OPCD |  crbD  |  00000 |  00000 |      XO      |Rc
+ * OPCD |  00000 |    A   |    B   |      XO      |0
+ * OPCD |  00000 |  00000 |    B   |      XO      |0
+ * OPCD |  00000 |  00000 |  00000 |      XO      |0
+ *---------------------------------------------------*/
+
+#define X_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			   ((rc) & 0x1))
+#define X_MASK X_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XL-Form Instructions:
+ * bcctrX bclrX crand crandc creqv crnand crnor cror
+ * croc crxorisync mcrf rfi
+ *---------------------------------------------------
+ * OPCD |   BO   |  BI    |  00000 |      XO      |LK
+ * OPCD |  crbD  | crbA   |  crbB  |      XO      |0
+ * OPCD |crfD |00|crfS |00|  00000 |      XO      |0
+ * OPCD |  00000 |  00000 |  00000 |      XO      |0
+ *---------------------------------------------------*/
+
+#define XL_OPCODE(i,xo,lk) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			    ((lk) & 0x1))
+#define XL_MASK XL_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XFX-Form Instructions:
+ * mfspr mftb mtcrf mtspr
+ *---------------------------------------------------
+ * OPCD |   D    |      spr        |      XO       |0
+ * OPCD |   D    |0|    CRM      |0|      XO       |0
+ * OPCD |   S    |      spr        |      XO       |0
+ * OPCD |   D    |      tbr        |      XO       |0
+ *---------------------------------------------------*/
+
+#define XFX_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			     ((rc) & 0x1))
+#define XFX_MASK XFX_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XFL-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |0|      FM     |0|   B    |      XO       |0
+ *---------------------------------------------------*/
+
+#define XFL_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			     ((rc) & 0x1))
+#define XFL_MASK XFL_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XS-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |   sh   |      XO   |sh|LK
+ *---------------------------------------------------*/
+
+#define XS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1ff) << 2) | \
+			     ((rc) & 0x1))
+#define XS_MASK XS_OPCODE(0x3f,0x1ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XO-Form Instructions:
+ * addX addcXaddeX addmeX addzeX divwX divwuX mulhwX
+ * mulhwuX mullwX negX subfX subfcX subfeX subfmeX
+ * subfzeX
+ *---------------------------------------------------
+ * OPCD |    D   |   A    |    B   |OE|     XO    |Rc
+ * OPCD |    D   |   A    |    B   |0 |     XO    |Rc
+ * OPCD |    D   |   A    |  00000 |OE|     XO    |Rc
+ *---------------------------------------------------*/
+
+#define XO_OPCODE(i,xo,oe,rc) (MAKE_OPCODE(i) | (((oe) & 0x1) << 10) | \
+			       (((xo) & 0x1ff) << 1) | ((rc) & 0x1))
+#define XO_MASK XO_OPCODE(0x3f,0x1ff,0x1,0x1)
+
+
+/*---------------------------------------------------
+ *            A-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    D   |   A    |    B   |00000|  XO    |Rc
+ * OPCD |    D   |   A    |    B   |  C  |  XO    |Rc
+ * OPCD |    D   |   A    |  00000 |  C  |  XO    |Rc
+ * OPCD |    D   |  00000 |    B   |00000|  XO    |Rc
+ *---------------------------------------------------*/
+
+#define A_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1f) << 1) | \
+			   ((rc) & 0x1))
+#define A_MASK A_OPCODE(0x3f,0x1f,0x1)
+
+
+/*---------------------------------------------------
+ *            M-Form Instructions:
+ * rlwimiX rlwinmX rlwnmX
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |    SH   |  MB |  ME   |Rc
+ * OPCD |    S   |   A    |     B   |  MB |  ME   |Rc
+ *---------------------------------------------------*/
+
+#define M_OPCODE(i,rc) (MAKE_OPCODE(i) | ((rc) & 0x1))
+#define M_MASK M_OPCODE(0x3f,0x1)
+
+
+/*---------------------------------------------------
+ *            MD-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |    sh   |  mb | XO |sh|Rc
+ * OPCD |    S   |   A    |    sh   |  me | XO |sh|Rc
+ *---------------------------------------------------*/
+
+#define MD_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x7) << 2) | \
+			   ((rc) & 0x1))
+#define MD_MASK MD_OPCODE(0x3f,0x7,0x1)
+
+
+/*---------------------------------------------------
+ *            MDS-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |    B    |  mb | XO    |Rc
+ * OPCD |    S   |   A    |    B    |  me | XO    |Rc
+ *---------------------------------------------------*/
+
+#define MDS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0xf) << 1) | \
+			   ((rc) & 0x1))
+#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1)
+
+#ifndef FALSE
+#define FALSE 0
+#define TRUE (!FALSE)
+#endif
+
+#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr))
+
+#define MAX_OPERANDS  8
+
+struct ppc_ctx;
+
+struct opcode {
+  unsigned long	opcode;		/* The complete opcode as produced by
+				   one of the XXX_OPCODE macros above */
+
+  unsigned long	mask;		/* The mask to use on an instruction
+				   before comparing with the opcode
+				   field to see if it matches */
+
+  enum OP_FIELD	fields[MAX_OPERANDS];
+				/* An array defining the operands for
+				   this opcode.  The values of the
+				   array are the operand identifiers */
+
+  int (*hfunc)(struct ppc_ctx *);
+  				/* Address of a function to handle the given
+				   mnemonic */
+
+  char *	name;		/* The symbolic name of this opcode */
+
+  unsigned int	hint;		/* A bitwise-inclusive-OR of the
+				   values shown below.  These are used
+				   tell the disassembler how to print
+				   some operands for this opcode */
+};
+
+/* values for opcode hints */
+#define H_RELATIVE	0x1	/* The address operand is relative */
+#define H_IMM_HIGH	0x2	/* [U|S]IMM field shifted high */
+#define H_RA0_IS_0	0x4	/* If rA = 0 then treat as literal 0 */
+
+struct ppc_ctx {
+  struct opcode *	op;
+  unsigned long		instr;
+  unsigned int		flags;
+  int			datalen;
+  char			data[ 256 ];
+  char			radix_fmt[ 8 ];
+  unsigned char *	virtual;
+};
+
+
+/*======================================================================
+ *
+ *  FUNCTIONS
+ *
+ *======================================================================*/
+
+/* Values for flags as passed to various ppc routines */
+#define F_RADOCTAL	0x1	/* output radix = unsigned octal */
+#define F_RADUDECIMAL	0x2	/* output radix = unsigned decimal */
+#define F_RADSDECIMAL	0x4	/* output radix = signed decimal */
+#define F_RADHEX	0x8	/* output radix = unsigned hex */
+#define F_SIMPLE	0x10	/* use simplified mnemonics */
+#define F_SYMBOL	0x20	/* use symbol lookups for addresses */
+#define F_INSTR		0x40	/* output the raw instruction */
+#define F_LOCALMEM	0x80	/* retrieve opcodes from local memory
+				   rather than from the HMI */
+#define F_LINENO	0x100	/* show line number info if available */
+#define F_VALIDONLY	0x200	/* cache: valid entries only */
+
+/* Values for assembler error codes */
+#define E_ASM_BAD_OPCODE	1
+#define E_ASM_NUM_OPERANDS	2
+#define E_ASM_BAD_REGISTER	3
+#define E_ASM_BAD_SPR		4
+#define E_ASM_BAD_TBR		5
+
+extern int disppc __P((unsigned char *,unsigned char *,int,
+		       int (*)(const char *), unsigned long));
+extern int print_source_line __P((char *,char *,int,
+				  int (*pfunc)(const char *)));
+extern int find_next_address __P((unsigned char *,int,struct pt_regs *));
+extern int handle_bc __P((struct ppc_ctx *));
+extern unsigned long asmppc __P((unsigned long,char*,int*));
+extern char *asm_error_str __P((int));
+
+/*======================================================================
+ *
+ *  GLOBAL VARIABLES
+ *
+ *======================================================================*/
+
+extern struct operand operands[];
+extern const unsigned int n_operands;
+extern struct opcode opcodes[];
+extern const unsigned int n_opcodes;
+
+#endif /* _PPC_H */
+
+
+/*
+ * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/include/bedbug/regs.h b/include/bedbug/regs.h
new file mode 100755
index 0000000..938e435
--- /dev/null
+++ b/include/bedbug/regs.h
@@ -0,0 +1,403 @@
+/* $Id$ */
+
+#ifndef _REGS_H
+#define _REGS_H
+
+/* Special Purpose Registers */
+
+#define SPR_CR		-1
+#define SPR_MSR		-2
+
+#define SPR_XER		1
+#define SPR_LR		8
+#define SPR_CTR		9
+#define SPR_DSISR	18
+#define SPR_DAR		19
+#define SPR_DEC		22
+#define SPR_SRR0	26
+#define SPR_SRR1	27
+#define SPR_EIE		80
+#define SPR_EID		81
+#define SPR_CMPA	144
+#define SPR_CMPB	145
+#define SPR_CMPC	146
+#define SPR_CMPD	147
+#define SPR_ICR		148
+#define SPR_DER		149
+#define SPR_COUNTA	150
+#define SPR_COUNTB	151
+#define SPR_CMPE	152
+#define SPR_CMPF	153
+#define SPR_CMPG	154
+#define SPR_CMPH	155
+#define SPR_LCTRL1	156
+#define SPR_LCTRL2	157
+#define SPR_ICTRL	158
+#define SPR_BAR		159
+#define SPR_USPRG0      256
+#define SPR_SPRG4_RO    260
+#define SPR_SPRG5_RO    261
+#define SPR_SPRG6_RO    262
+#define SPR_SPRG7_RO    263
+#define SPR_SPRG0	272
+#define SPR_SPRG1	273
+#define SPR_SPRG2	274
+#define SPR_SPRG3	275
+#define SPR_SPRG4       276
+#define SPR_SPRG5       277
+#define SPR_SPRG6       278
+#define SPR_SPRG7       279
+#define SPR_EAR         282	/* MPC603e core */
+#define SPR_TBL         284
+#define SPR_TBU         285
+#define SPR_PVR		287
+#define SPR_IC_CST	560
+#define SPR_IC_ADR	561
+#define SPR_IC_DAT	562
+#define SPR_DC_CST	568
+#define SPR_DC_ADR	569
+#define SPR_DC_DAT	570
+#define SPR_DPDR	630
+#define SPR_IMMR	638
+#define SPR_MI_CTR	784
+#define SPR_MI_AP	786
+#define SPR_MI_EPN	787
+#define SPR_MI_TWC	789
+#define SPR_MI_RPN	790
+#define SPR_MD_CTR	792
+#define SPR_M_CASID	793
+#define SPR_MD_AP	794
+#define SPR_MD_EPN	795
+#define SPR_M_TWB	796
+#define SPR_MD_TWC	797
+#define SPR_MD_RPN	798
+#define SPR_M_TW	799
+#define SPR_MI_DBCAM	816
+#define SPR_MI_DBRAM0	817
+#define SPR_MI_DBRAM1	818
+#define SPR_MD_DBCAM	824
+#define SPR_MD_DBRAM0	825
+#define SPR_MD_DBRAM1	826
+#define SPR_ZPR         944
+#define SPR_PID         945
+#define SPR_CCR0        947
+#define SPR_IAC3        948
+#define SPR_IAC4        949
+#define SPR_DVC1        950
+#define SPR_DVC2        951
+#define SPR_SGR         953
+#define SPR_DCWR        954
+#define SPR_SLER        955
+#define SPR_SU0R        956
+#define SPR_DBCR1       957
+#define SPR_ICDBDR      979
+#define SPR_ESR         980
+#define SPR_DEAR        981
+#define SPR_EVPR        982
+#define SPR_TSR         984
+#define SPR_TCR         986
+#define SPR_PIT         987
+#define SPR_SRR2        990
+#define SPR_SRR3        991
+#define SPR_DBSR        1008
+#define SPR_DBCR0       1010
+#define SPR_IABR        1010	/* MPC603e core */
+#define SPR_IAC1        1012
+#define SPR_IAC2        1013
+#define SPR_DAC1        1014
+#define SPR_DAC2        1015
+#define SPR_DCCR        1018
+#define SPR_ICCR        1019
+
+/* Bits for the DBCR0 register */
+#define DBCR0_EDM	0x80000000
+#define DBCR0_IDM	0x40000000
+#define DBCR0_RST	0x30000000
+#define DBCR0_IC	0x08000000
+#define DBCR0_BT	0x04000000
+#define DBCR0_EDE	0x02000000
+#define DBCR0_TDE	0x01000000
+#define DBCR0_IA1	0x00800000
+#define DBCR0_IA2	0x00400000
+#define DBCR0_IA12	0x00200000
+#define DBCR0_IA12X	0x00100000
+#define DBCR0_IA3	0x00080000
+#define DBCR0_IA4	0x00040000
+#define DBCR0_IA34	0x00020000
+#define DBCR0_IA34X	0x00010000
+#define DBCR0_IA12T	0x00008000
+#define DBCR0_IA34T	0x00004000
+#define DBCR0_FT	0x00000001
+
+/* Bits for the DBCR1 register */
+#define DBCR1_D1R	0x80000000
+#define DBCR1_D2R	0x40000000
+#define DBCR1_D1W	0x20000000
+#define DBCR1_D2W	0x10000000
+#define DBCR1_D1S	0x0C000000
+#define DBCR1_D2S	0x03000000
+#define DBCR1_DA12	0x00800000
+#define DBCR1_DA12X	0x00400000
+#define DBCR1_DV1M	0x000C0000
+#define DBCR1_DV2M	0x00030000
+#define DBCR1_DV1BE	0x0000F000
+#define DBCR1_DV2BE	0x00000F00
+
+/* Bits for the DBSR register */
+#define DBSR_IC		0x80000000
+#define DBSR_BT		0x40000000
+#define DBSR_EDE	0x20000000
+#define DBSR_TIE	0x10000000
+#define DBSR_UDE	0x08000000
+#define DBSR_IA1	0x04000000
+#define DBSR_IA2	0x02000000
+#define DBSR_DR1	0x01000000
+#define DBSR_DW1	0x00800000
+#define DBSR_DR2	0x00400000
+#define DBSR_DW2	0x00200000
+#define DBSR_IDE	0x00100000
+#define DBSR_IA3	0x00080000
+#define DBSR_IA4	0x00040000
+#define DBSR_MRR	0x00000300
+
+struct spr_info {
+  int  spr_val;
+  char spr_name[ 10 ];
+};
+
+extern struct spr_info spr_map[];
+extern const unsigned int n_sprs;
+
+
+#define SET_REGISTER( str, val ) \
+({ unsigned long __value = (val); \
+  asm volatile( str : : "r" (__value)); \
+  __value; })
+
+#define	GET_REGISTER( str ) \
+({ unsigned long __value; \
+  asm volatile( str : "=r" (__value) : ); \
+  __value; })
+
+#define	 GET_CR()	     GET_REGISTER( "mfcr %0" )
+#define	 SET_CR(val)	     SET_REGISTER( "mtcr %0", val )
+#define	 GET_MSR()	     GET_REGISTER( "mfmsr %0" )
+#define	 SET_MSR(val)	     SET_REGISTER( "mtmsr %0", val )
+#define	 GET_XER()	     GET_REGISTER( "mfspr %0,1" )
+#define	 SET_XER(val)	     SET_REGISTER( "mtspr 1,%0", val )
+#define	 GET_LR()	     GET_REGISTER( "mfspr %0,8" )
+#define	 SET_LR(val)	     SET_REGISTER( "mtspr 8,%0", val )
+#define	 GET_CTR()	     GET_REGISTER( "mfspr %0,9" )
+#define	 SET_CTR(val)	     SET_REGISTER( "mtspr 9,%0", val )
+#define	 GET_DSISR()	     GET_REGISTER( "mfspr %0,18" )
+#define	 SET_DSISR(val)	     SET_REGISTER( "mtspr 18,%0", val )
+#define	 GET_DAR()	     GET_REGISTER( "mfspr %0,19" )
+#define	 SET_DAR(val)	     SET_REGISTER( "mtspr 19,%0", val )
+#define	 GET_DEC()	     GET_REGISTER( "mfspr %0,22" )
+#define	 SET_DEC(val)	     SET_REGISTER( "mtspr 22,%0", val )
+#define	 GET_SRR0()	     GET_REGISTER( "mfspr %0,26" )
+#define	 SET_SRR0(val)       SET_REGISTER( "mtspr 26,%0", val )
+#define	 GET_SRR1()	     GET_REGISTER( "mfspr %0,27" )
+#define	 SET_SRR1(val)	     SET_REGISTER( "mtspr 27,%0", val )
+#define	 GET_EIE()	     GET_REGISTER( "mfspr %0,80" )
+#define	 SET_EIE(val)	     SET_REGISTER( "mtspr 80,%0", val )
+#define	 GET_EID()	     GET_REGISTER( "mfspr %0,81" )
+#define	 SET_EID(val)	     SET_REGISTER( "mtspr 81,%0", val )
+#define	 GET_CMPA()	     GET_REGISTER( "mfspr %0,144" )
+#define	 SET_CMPA(val)	     SET_REGISTER( "mtspr 144,%0", val )
+#define	 GET_CMPB()	     GET_REGISTER( "mfspr %0,145" )
+#define	 SET_CMPB(val)	     SET_REGISTER( "mtspr 145,%0", val )
+#define	 GET_CMPC()	     GET_REGISTER( "mfspr %0,146" )
+#define	 SET_CMPC(val)	     SET_REGISTER( "mtspr 146,%0", val )
+#define	 GET_CMPD()	     GET_REGISTER( "mfspr %0,147" )
+#define	 SET_CMPD(val)	     SET_REGISTER( "mtspr 147,%0", val )
+#define	 GET_ICR()	     GET_REGISTER( "mfspr %0,148" )
+#define	 SET_ICR(val)	     SET_REGISTER( "mtspr 148,%0", val )
+#define	 GET_DER()	     GET_REGISTER( "mfspr %0,149" )
+#define	 SET_DER(val)	     SET_REGISTER( "mtspr 149,%0", val )
+#define	 GET_COUNTA()	     GET_REGISTER( "mfspr %0,150" )
+#define	 SET_COUNTA(val)     SET_REGISTER( "mtspr 150,%0", val )
+#define	 GET_COUNTB()	     GET_REGISTER( "mfspr %0,151" )
+#define	 SET_COUNTB(val)     SET_REGISTER( "mtspr 151,%0", val )
+#define	 GET_CMPE()	     GET_REGISTER( "mfspr %0,152" )
+#define	 SET_CMPE(val)	     SET_REGISTER( "mtspr 152,%0", val )
+#define	 GET_CMPF()	     GET_REGISTER( "mfspr %0,153" )
+#define	 SET_CMPF(val)	     SET_REGISTER( "mtspr 153,%0", val )
+#define	 GET_CMPG()	     GET_REGISTER( "mfspr %0,154" )
+#define	 SET_CMPG(val)	     SET_REGISTER( "mtspr 154,%0", val )
+#define	 GET_CMPH()	     GET_REGISTER( "mfspr %0,155" )
+#define	 SET_CMPH(val)	     SET_REGISTER( "mtspr 155,%0", val )
+#define  GET_LCTRL1()	     GET_REGISTER( "mfspr %0,156" )
+#define	 SET_LCTRL1(val)     SET_REGISTER( "mtspr 156,%0", val )
+#define  GET_LCTRL2()	     GET_REGISTER( "mfspr %0,157" )
+#define	 SET_LCTRL2(val)     SET_REGISTER( "mtspr 157,%0", val )
+#define  GET_ICTRL()	     GET_REGISTER( "mfspr %0,158" )
+#define	 SET_ICTRL(val)	     SET_REGISTER( "mtspr 158,%0", val )
+#define  GET_BAR()	     GET_REGISTER( "mfspr %0,159" )
+#define	 SET_BAR(val)	     SET_REGISTER( "mtspr 159,%0", val )
+#define  GET_USPRG0()	     GET_REGISTER( "mfspr %0,256" )
+#define	 SET_USPRG0(val)     SET_REGISTER( "mtspr 256,%0", val )
+#define  GET_SPRG4_RO()	     GET_REGISTER( "mfspr %0,260" )
+#define	 SET_SPRG4_RO(val)   SET_REGISTER( "mtspr 260,%0", val )
+#define  GET_SPRG5_RO()	     GET_REGISTER( "mfspr %0,261" )
+#define	 SET_SPRG5_RO(val)   SET_REGISTER( "mtspr 261,%0", val )
+#define  GET_SPRG6_RO()	     GET_REGISTER( "mfspr %0,262" )
+#define	 SET_SPRG6_RO(val)   SET_REGISTER( "mtspr 262,%0", val )
+#define  GET_SPRG7_RO()	     GET_REGISTER( "mfspr %0,263" )
+#define	 SET_SPRG7_RO(val)   SET_REGISTER( "mtspr 263,%0", val )
+#define  GET_SPRG0()	     GET_REGISTER( "mfspr %0,272" )
+#define	 SET_SPRG0(val)	     SET_REGISTER( "mtspr 272,%0", val )
+#define  GET_SPRG1()	     GET_REGISTER( "mfspr %0,273" )
+#define	 SET_SPRG1(val)	     SET_REGISTER( "mtspr 273,%0", val )
+#define  GET_SPRG2()	     GET_REGISTER( "mfspr %0,274" )
+#define	 SET_SPRG2(val)	     SET_REGISTER( "mtspr 274,%0", val )
+#define  GET_SPRG3()	     GET_REGISTER( "mfspr %0,275" )
+#define	 SET_SPRG3(val)	     SET_REGISTER( "mtspr 275,%0", val )
+#define  GET_SPRG4()	     GET_REGISTER( "mfspr %0,276" )
+#define	 SET_SPRG4(val)      SET_REGISTER( "mtspr 276,%0", val )
+#define  GET_SPRG5()	     GET_REGISTER( "mfspr %0,277" )
+#define	 SET_SPRG5(val)	     SET_REGISTER( "mtspr 277,%0", val )
+#define  GET_SPRG6()	     GET_REGISTER( "mfspr %0,278" )
+#define	 SET_SPRG6(val)	     SET_REGISTER( "mtspr 278,%0", val )
+#define  GET_SPRG7()	     GET_REGISTER( "mfspr %0,279" )
+#define	 SET_SPRG7(val)	     SET_REGISTER( "mtspr 279,%0", val )
+#define  GET_EAR()	     GET_REGISTER( "mfspr %0,282" )
+#define	 SET_EAR(val)	     SET_REGISTER( "mtspr 282,%0", val )
+#define  GET_TBL()	     GET_REGISTER( "mfspr %0,284" )
+#define	 SET_TBL(val)	     SET_REGISTER( "mtspr 284,%0", val )
+#define  GET_TBU()	     GET_REGISTER( "mfspr %0,285" )
+#define	 SET_TBU(val)	     SET_REGISTER( "mtspr 285,%0", val )
+#define  GET_PVR()	     GET_REGISTER( "mfspr %0,287" )
+#define	 SET_PVR(val)	     SET_REGISTER( "mtspr 287,%0", val )
+#define  GET_IC_CST()	     GET_REGISTER( "mfspr %0,560" )
+#define	 SET_IC_CST(val)     SET_REGISTER( "mtspr 560,%0", val )
+#define  GET_IC_ADR()	     GET_REGISTER( "mfspr %0,561" )
+#define	 SET_IC_ADR(val)     SET_REGISTER( "mtspr 561,%0", val )
+#define  GET_IC_DAT()	     GET_REGISTER( "mfspr %0,562" )
+#define	 SET_IC_DAT(val)     SET_REGISTER( "mtspr 562,%0", val )
+#define  GET_DC_CST()	     GET_REGISTER( "mfspr %0,568" )
+#define	 SET_DC_CST(val)     SET_REGISTER( "mtspr 568,%0", val )
+#define  GET_DC_ADR()	     GET_REGISTER( "mfspr %0,569" )
+#define	 SET_DC_ADR(val)     SET_REGISTER( "mtspr 569,%0", val )
+#define  GET_DC_DAT()	     GET_REGISTER( "mfspr %0,570" )
+#define	 SET_DC_DAT(val)     SET_REGISTER( "mtspr 570,%0", val )
+#define  GET_DPDR()	     GET_REGISTER( "mfspr %0,630" )
+#define	 SET_DPDR(val)	     SET_REGISTER( "mtspr 630,%0", val )
+#define  GET_IMMR()	     GET_REGISTER( "mfspr %0,638" )
+#define	 SET_IMMR(val)	     SET_REGISTER( "mtspr 638,%0", val )
+#define  GET_MI_CTR()	     GET_REGISTER( "mfspr %0,784" )
+#define	 SET_MI_CTR(val)     SET_REGISTER( "mtspr 784,%0", val )
+#define  GET_MI_AP()	     GET_REGISTER( "mfspr %0,786" )
+#define	 SET_MI_AP(val)	     SET_REGISTER( "mtspr 786,%0", val )
+#define  GET_MI_EPN()	     GET_REGISTER( "mfspr %0,787" )
+#define	 SET_MI_EPN(val)     SET_REGISTER( "mtspr 787,%0", val )
+#define  GET_MI_TWC()	     GET_REGISTER( "mfspr %0,789" )
+#define	 SET_MI_TWC(val)     SET_REGISTER( "mtspr 789,%0", val )
+#define  GET_MI_RPN()	     GET_REGISTER( "mfspr %0,790" )
+#define	 SET_MI_RPN(val)     SET_REGISTER( "mtspr 790,%0", val )
+#define  GET_MD_CTR()	     GET_REGISTER( "mfspr %0,792" )
+#define	 SET_MD_CTR(val)     SET_REGISTER( "mtspr 792,%0", val )
+#define  GET_M_CASID()	     GET_REGISTER( "mfspr %0,793" )
+#define	 SET_M_CASID(val)    SET_REGISTER( "mtspr 793,%0", val )
+#define  GET_MD_AP()	     GET_REGISTER( "mfspr %0,794" )
+#define	 SET_MD_AP(val)	     SET_REGISTER( "mtspr ,794%0", val )
+#define  GET_MD_EPN()	     GET_REGISTER( "mfspr %0,795" )
+#define	 SET_MD_EPN(val)     SET_REGISTER( "mtspr 795,%0", val )
+#define  GET_M_TWB()	     GET_REGISTER( "mfspr %0,796" )
+#define	 SET_M_TWB(val)	     SET_REGISTER( "mtspr 796,%0", val )
+#define  GET_MD_TWC()	     GET_REGISTER( "mfspr %0,797" )
+#define	 SET_MD_TWC(val)     SET_REGISTER( "mtspr 797,%0", val )
+#define  GET_MD_RPN()	     GET_REGISTER( "mfspr %0,798" )
+#define	 SET_MD_RPN(val)     SET_REGISTER( "mtspr 798,%0", val )
+#define  GET_M_TW()	     GET_REGISTER( "mfspr %0,799" )
+#define	 SET_M_TW(val)	     SET_REGISTER( "mtspr 799,%0", val )
+#define  GET_MI_DBCAM()      GET_REGISTER( "mfspr %0,816" )
+#define	 SET_MI_DBCAM(val)   SET_REGISTER( "mtspr 816,%0", val )
+#define  GET_MI_DBRAM0()     GET_REGISTER( "mfspr %0,817" )
+#define	 SET_MI_DBRAM0(val)  SET_REGISTER( "mtspr 817,%0", val )
+#define  GET_MI_DBRAM1()     GET_REGISTER( "mfspr %0,818" )
+#define	 SET_MI_DBRAM1(val)  SET_REGISTER( "mtspr 818,%0", val )
+#define  GET_MD_DBCAM()      GET_REGISTER( "mfspr %0,824" )
+#define	 SET_MD_DBCA(val)    SET_REGISTER( "mtspr 824,%0", val )
+#define  GET_MD_DBRAM0()     GET_REGISTER( "mfspr %0,825" )
+#define	 SET_MD_DBRAM0(val)  SET_REGISTER( "mtspr 825,%0", val )
+#define  GET_MD_DBRAM1()     GET_REGISTER( "mfspr %0,826" )
+#define	 SET_MD_DBRAM1(val)  SET_REGISTER( "mtspr 826,%0", val )
+#define  GET_ZPR()           GET_REGISTER( "mfspr %0,944" )
+#define	 SET_ZPR(val)        SET_REGISTER( "mtspr 944,%0", val )
+#define  GET_PID()	     GET_REGISTER( "mfspr %0,945" )
+#define	 SET_PID(val)	     SET_REGISTER( "mtspr 945,%0", val )
+#define  GET_CCR0()	     GET_REGISTER( "mfspr %0,947" )
+#define	 SET_CCR0(val)	     SET_REGISTER( "mtspr 947,%0", val )
+#define	 GET_IAC3()	     GET_REGISTER( "mfspr %0,948" )
+#define	 SET_IAC3(val)	     SET_REGISTER( "mtspr 948,%0", val )
+#define	 GET_IAC4()	     GET_REGISTER( "mfspr %0,949" )
+#define	 SET_IAC4(val)	     SET_REGISTER( "mtspr 949,%0", val )
+#define	 GET_DVC1()	     GET_REGISTER( "mfspr %0,950" )
+#define	 SET_DVC1(val)	     SET_REGISTER( "mtspr 950,%0", val )
+#define	 GET_DVC2()	     GET_REGISTER( "mfspr %0,951" )
+#define	 SET_DVC2(val)	     SET_REGISTER( "mtspr 951,%0", val )
+#define	 GET_SGR()	     GET_REGISTER( "mfspr %0,953" )
+#define	 SET_SGR(val)	     SET_REGISTER( "mtspr 953,%0", val )
+#define	 GET_DCWR()	     GET_REGISTER( "mfspr %0,954" )
+#define	 SET_DCWR(val)	     SET_REGISTER( "mtspr 954,%0", val )
+#define	 GET_SLER()	     GET_REGISTER( "mfspr %0,955" )
+#define	 SET_SLER(val)	     SET_REGISTER( "mtspr 955,%0", val )
+#define	 GET_SU0R()	     GET_REGISTER( "mfspr %0,956" )
+#define	 SET_SU0R(val)	     SET_REGISTER( "mtspr 956,%0", val )
+#define	 GET_DBCR1()	     GET_REGISTER( "mfspr %0,957" )
+#define	 SET_DBCR1(val)	     SET_REGISTER( "mtspr 957,%0", val )
+#define	 GET_ICDBDR()	     GET_REGISTER( "mfspr %0,979" )
+#define	 SET_ICDBDR(val)     SET_REGISTER( "mtspr 979,%0", val )
+#define	 GET_ESR()	     GET_REGISTER( "mfspr %0,980" )
+#define	 SET_ESR(val)	     SET_REGISTER( "mtspr 980,%0", val )
+#define	 GET_DEAR()	     GET_REGISTER( "mfspr %0,981" )
+#define	 SET_DEAR(val)	     SET_REGISTER( "mtspr 981,%0", val )
+#define	 GET_EVPR()	     GET_REGISTER( "mfspr %0,982" )
+#define	 SET_EVPR(val)	     SET_REGISTER( "mtspr 982,%0", val )
+#define	 GET_TSR()	     GET_REGISTER( "mfspr %0,984" )
+#define	 SET_TSR(val)	     SET_REGISTER( "mtspr 984,%0", val )
+#define	 GET_TCR()	     GET_REGISTER( "mfspr %0,986" )
+#define	 SET_TCR(val)	     SET_REGISTER( "mtspr 986,%0", val )
+#define	 GET_PIT()	     GET_REGISTER( "mfspr %0,987" )
+#define	 SET_PIT(val)	     SET_REGISTER( "mtspr 987,%0", val )
+#define	 GET_SRR2()	     GET_REGISTER( "mfspr %0,990" )
+#define	 SET_SRR2(val)	     SET_REGISTER( "mtspr 990,%0", val )
+#define	 GET_SRR3()	     GET_REGISTER( "mfspr %0,991" )
+#define	 SET_SRR3(val)	     SET_REGISTER( "mtspr 991,%0", val )
+#define	 GET_DBSR()	     GET_REGISTER( "mfspr %0,1008" )
+#define	 SET_DBSR(val)	     SET_REGISTER( "mtspr 1008,%0", val )
+#define	 GET_DBCR0()	     GET_REGISTER( "mfspr %0,1010" )
+#define	 SET_DBCR0(val)	     SET_REGISTER( "mtspr 1010,%0", val )
+#define	 GET_IABR()	     GET_REGISTER( "mfspr %0,1010" )
+#define	 SET_IABR(val)	     SET_REGISTER( "mtspr 1010,%0", val )
+#define	 GET_IAC1()	     GET_REGISTER( "mfspr %0,1012" )
+#define	 SET_IAC1(val)	     SET_REGISTER( "mtspr 1012,%0", val )
+#define	 GET_IAC2()	     GET_REGISTER( "mfspr %0,1013" )
+#define	 SET_IAC2(val)	     SET_REGISTER( "mtspr 1013,%0", val )
+#define	 GET_DAC1()	     GET_REGISTER( "mfspr %0,1014" )
+#define	 SET_DAC1(val)	     SET_REGISTER( "mtspr 1014,%0", val )
+#define	 GET_DAC2()	     GET_REGISTER( "mfspr %0,1015" )
+#define	 SET_DAC2(val)	     SET_REGISTER( "mtspr 1015,%0", val )
+#define	 GET_DCCR()	     GET_REGISTER( "mfspr %0,1018" )
+#define	 SET_DCCR(val)	     SET_REGISTER( "mtspr 1018,%0", val )
+#define	 GET_ICCR()	     GET_REGISTER( "mfspr %0,1019" )
+#define	 SET_ICCR(val)	     SET_REGISTER( "mtspr 1019,%0", val )
+
+#endif /* _REGS_H */
+
+
+/*
+ * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/include/bedbug/tables.h b/include/bedbug/tables.h
new file mode 100755
index 0000000..66cf8ea
--- /dev/null
+++ b/include/bedbug/tables.h
@@ -0,0 +1,601 @@
+/* $Id$ */
+
+#ifndef TABLES_H
+#define TABLES_H
+
+/* This is only included by common/bedbug.c, and depends on the following
+ * files to already be included
+ *   common.h
+ *   bedbug/bedbug.h
+ *   bedbug/ppc.h
+ *   bedbug/regs.h
+ */
+
+struct operand operands[] = {
+  /*Field    Name     Bits  Shift  Hint 		   Position	*/
+  /*-----    ------   ----- -----  ---- 	           ------------ */
+  { O_AA,    "O_AA",    1,     1,  OH_SILENT },		/*   30 	*/
+  { O_BD,    "O_BD",   14,     2,  OH_ADDR },		/* 16-29	*/
+  { O_BI,    "O_BI",    5,    16,  0 },			/* 11-15	*/
+  { O_BO,    "O_BO",    5,    21,  0 },			/*  6-10	*/
+  { O_crbD,  "O_crbD",  5,    21,  0 },			/*  6-10	*/
+  { O_crbA,  "O_crbA",  5,    16,  0 },			/* 11-15	*/
+  { O_crbB,  "O_crbB",  5,    11,  0 },			/* 16-20	*/
+  { O_CRM,   "O_CRM",   8,    12,  0 },			/* 12-19	*/
+  { O_d,     "O_d",    15,     0,  OH_OFFSET },		/* 16-31	*/
+  { O_frC,   "O_frC",   5,     6,  0 },			/* 21-25	*/
+  { O_frD,   "O_frD",   5,    21,  0 },			/*  6-10	*/
+  { O_frS,   "O_frS",   5,    21,  0 },			/*  6-10	*/
+  { O_IMM,   "O_IMM",   4,    12,  0 },			/* 16-19	*/
+  { O_LI,    "O_LI",   24,     2,  OH_ADDR },		/*  6-29	*/
+  { O_LK,    "O_LK",    1,     0,  OH_SILENT },		/*   31		*/
+  { O_MB,    "O_MB",    5,     6,  0 },			/* 21-25	*/
+  { O_ME,    "O_ME",    5,     1,  0 },			/* 26-30	*/
+  { O_NB,    "O_NB",    5,    11,  0 },			/* 16-20	*/
+  { O_OE,    "O_OE",    1,    10,  OH_SILENT },		/*   21		*/
+  { O_rA,    "O_rA",    5,    16,  OH_REG },		/* 11-15	*/
+  { O_rB,    "O_rB",    5,    11,  OH_REG },		/* 16-20	*/
+  { O_Rc,    "O_Rc",    1,     0,  OH_SILENT },		/*   31		*/
+  { O_rD,    "O_rD",    5,    21,  OH_REG },		/*  6-10	*/
+  { O_rS,    "O_rS",    5,    21,  OH_REG },		/*  6-10	*/
+  { O_SH,    "O_SH",    5,    11,  0 },			/* 16-20	*/
+  { O_SIMM,  "O_SIMM", 16,     0,  0 },			/* 16-31	*/
+  { O_SR,    "O_SR",    4,    16,  0 },			/* 12-15	*/
+  { O_TO,    "O_TO",    5,    21,  0 },			/*  6-10	*/
+  { O_UIMM,  "O_UIMM", 16,     0,  0 },			/* 16-31	*/
+  { O_crfD,  "O_crfD",  3,    23,  0 },			/*  6- 8	*/
+  { O_crfS,  "O_crfS",  3,    18,  0 },			/* 11-13	*/
+  { O_L,     "O_L",     1,    21,  0 },			/*   10		*/
+  { O_spr,   "O_spr",  10,    11,  OH_SPR },		/* 11-20	*/
+  { O_tbr,   "O_tbr",  10,    11,  OH_TBR },		/* 11-20	*/
+  { O_cr2,   "O_cr2",   0,     0,  OH_LITERAL },        /* "cr2"        */
+};
+
+const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]);
+
+/* A note about the fields array in the opcodes structure:
+   The operands are listed in the order they appear in the output.
+
+   This table is arranged in numeric order of the opcode.  Note that some
+   opcodes have defined bits in odd places so not all forms of a command
+   will be in the same place.  This is done so that a binary search can be
+   done to find the opcodes.  Note that table D.2 in the MPC860 User's
+   Manual "Instructions Sorted by Opcode" does not account for these
+   bit locations */
+
+struct opcode opcodes[] = {
+  { D_OPCODE(3),           D_MASK,   {O_TO, O_rA, O_SIMM, 0},
+    0,               "twi",          0 },
+  { D_OPCODE(7),           D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,               "mulli",        0 },
+  { D_OPCODE(8),           D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,               "subfic",       0 },
+  { D_OPCODE(10),          D_MASK,   {O_crfD, O_L, O_rA, O_UIMM, 0},
+    0,               "cmpli",        0 },
+  { D_OPCODE(11),          D_MASK,   {O_crfD, O_L, O_rA, O_SIMM, 0},
+    0,               "cmpi",         0 },
+  { D_OPCODE(12),          D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,               "addic",        0 },
+  { D_OPCODE(13),          D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,               "addic.",       0 },
+  { D_OPCODE(14),          D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,               "addi",         H_RA0_IS_0 },
+  { D_OPCODE(15),          D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,               "addis",        H_RA0_IS_0|H_IMM_HIGH },
+  { B_OPCODE(16,0,0),      B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    handle_bc,       "bc",           H_RELATIVE },
+  { B_OPCODE(16,0,1),      B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,               "bcl",          H_RELATIVE },
+  { B_OPCODE(16,1,0),      B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,               "bca",          0 },
+  { B_OPCODE(16,1,1),      B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,               "bcla",         0 },
+  { SC_OPCODE(17),         SC_MASK,  {0},
+    0,               "sc",           0 },
+  { I_OPCODE(18,0,0),      I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,               "b",            H_RELATIVE },
+  { I_OPCODE(18,0,1),      I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,               "bl",           H_RELATIVE },
+  { I_OPCODE(18,1,0),      I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,               "ba",           0 },
+  { I_OPCODE(18,1,1),      I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,               "bla",          0 },
+  { XL_OPCODE(19,0,0),     XL_MASK,  {O_crfD, O_crfS},
+    0,               "mcrf",         0 },
+  { XL_OPCODE(19,16,0),    XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,               "bclr",         0 },
+  { XL_OPCODE(19,16,1),    XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,               "bclrl",        0 },
+  { XL_OPCODE(19,33,0),    XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,               "crnor",        0 },
+  { XL_OPCODE(19,50,0),    XL_MASK,  {0},
+    0,               "rfi",          0 },
+  { XL_OPCODE(19,129,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,               "crandc",       0 },
+  { XL_OPCODE(19,150,0),   XL_MASK,  {0},
+    0,               "isync",        0 },
+  { XL_OPCODE(19,193,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,               "crxor",        0 },
+  { XL_OPCODE(19,225,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,               "crnand",       0 },
+  { XL_OPCODE(19,257,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,               "crand",        0 },
+  { XL_OPCODE(19,289,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,               "creqv",        0 },
+  { XL_OPCODE(19,417,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,               "crorc",        0 },
+  { XL_OPCODE(19,449,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,               "cror",         0 },
+  { XL_OPCODE(19,528,0),   XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,               "bcctr",        0 },
+  { XL_OPCODE(19,528,1),   XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,               "bcctrl",       0 },
+  { M_OPCODE(20,0),        M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,               "rlwimi",       0 },
+  { M_OPCODE(20,1),        M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,               "rlwimi.",      0 },
+  { M_OPCODE(21,0),        M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,               "rlwinm",       0 },
+  { M_OPCODE(21,1),        M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,               "rlwinm.",      0 },
+  { M_OPCODE(23,0),        M_MASK,   {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
+    0,               "rlwnm",        0 },
+  { M_OPCODE(23,1),        M_MASK,   {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
+    0,               "rlwnm.",       0 },
+  { D_OPCODE(24),          D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,               "ori",          0 },
+  { D_OPCODE(25),          D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,               "oris",         H_IMM_HIGH },
+  { D_OPCODE(26),          D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,               "xori",         0 },
+  { D_OPCODE(27),          D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,               "xoris",        H_IMM_HIGH },
+  { D_OPCODE(28),          D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,               "andi.",        0 },
+  { D_OPCODE(29),          D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,               "andis.",       H_IMM_HIGH },
+  { X_OPCODE(31,0,0),      X_MASK,   {O_crfD, O_L, O_rA, O_rB, 0},
+    0,               "cmp",          0 },
+  { X_OPCODE(31,4,0),      X_MASK,   {O_TO, O_rA, O_rB, 0},
+    0,               "tw",           0 },
+  { XO_OPCODE(31,8,0,0),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "subfc",        0 },
+  { XO_OPCODE(31,8,0,1),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "subfc.",       0 },
+  { XO_OPCODE(31,10,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "addc",         0 },
+  { XO_OPCODE(31,10,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "addc.",        0 },
+  { XO_OPCODE(31,11,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,               "mulhwu",       0 },
+  { XO_OPCODE(31,11,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,               "mulhwu.",      0 },
+  { X_OPCODE(31,19,0),     X_MASK,   {O_rD, 0},
+    0,               "mfcr",         0 },
+  { X_OPCODE(31,20,0),     X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,               "lwarx",        H_RA0_IS_0 },
+  { X_OPCODE(31,23,0),     X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,               "lwzx",         H_RA0_IS_0 },
+  { X_OPCODE(31,24,0),     X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "slw",          0 },
+  { X_OPCODE(31,24,1),     X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "slw.",         0 },
+  { X_OPCODE(31,26,0),     X_MASK,   {O_rA, O_rS, O_Rc, 0 },
+    0,               "cntlzw",       0 },
+  { X_OPCODE(31,26,1),     X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,               "cntlzw.",      0 },
+  { X_OPCODE(31,28,0),     X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "and",          0 },
+  { X_OPCODE(31,28,1),     X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "and.",         0 },
+  { X_OPCODE(31,32,0),     X_MASK,   {O_crfD, O_L, O_rA, O_rB, 0},
+    0,               "cmpl",         0 },
+  { XO_OPCODE(31,40,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "subf",         0 },
+  { XO_OPCODE(31,40,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "subf.",        0 },
+  { X_OPCODE(31,54,0),     X_MASK,   {O_rA, O_rB, 0},
+    0,               "dcbst",        H_RA0_IS_0 },
+  { X_OPCODE(31,55,0),     X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,               "lwzux",        0 },
+  { X_OPCODE(31,60,0),     X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "andc",         0 },
+  { X_OPCODE(31,60,1),     X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "andc.",        0 },
+  { XO_OPCODE(31,75,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,               "mulhw",        0 },
+  { XO_OPCODE(31,75,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,               "mulhw.",       0 },
+  { X_OPCODE(31,83,0),     X_MASK,   {O_rD, 0},
+    0,               "mfmsr",        0 },
+  { X_OPCODE(31,86,0),     X_MASK,   {O_rA, O_rB, 0},
+    0,               "dcbf",         H_RA0_IS_0 },
+  { X_OPCODE(31,87,0),     X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,               "lbzx",         H_RA0_IS_0 },
+  { XO_OPCODE(31,104,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "neg",          0 },
+  { XO_OPCODE(31,104,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "neg.",         0 },
+  { X_OPCODE(31,119,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,               "lbzux",        0 },
+  { X_OPCODE(31,124,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "nor",          0 },
+  { X_OPCODE(31,124,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "nor.",         0 },
+  { XO_OPCODE(31,136,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "subfe",        0 },
+  { XO_OPCODE(31,136,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "subfe.",       0 },
+  { XO_OPCODE(31,138,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "adde",         0 },
+  { XO_OPCODE(31,138,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "adde.",        0 },
+  { XFX_OPCODE(31,144,0),  XFX_MASK, {O_CRM, O_rS, 0},
+    0,               "mtcrf",        0 },
+  { X_OPCODE(31,146,0),    X_MASK,   {O_rS, 0},
+    0,               "mtmsr",        0 },
+  { X_OPCODE(31,150,1),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,               "stwcx.",       0 },
+  { X_OPCODE(31,151,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,               "stwx",         0 },
+  { X_OPCODE(31,183,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,               "stwux",        0 },
+  { XO_OPCODE(31,200,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "subfze",       0 },
+  { XO_OPCODE(31,200,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "subfze.",      0 },
+  { XO_OPCODE(31,202,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "addze",        0 },
+  { XO_OPCODE(31,202,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "addze.",       0 },
+  { X_OPCODE(31,210,0),    X_MASK,   {O_SR, O_rS, 0},
+    0,               "mtsr",         0 },
+  { X_OPCODE(31,215,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,               "stbx",         H_RA0_IS_0 },
+  { XO_OPCODE(31,232,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "subfme",       0 },
+  { XO_OPCODE(31,232,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "subfme.",      0 },
+  { XO_OPCODE(31,234,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "addme",        0 },
+  { XO_OPCODE(31,234,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "addme.",       0 },
+  { XO_OPCODE(31,235,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "mullw",        0 },
+  { XO_OPCODE(31,235,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "mullw.",       0 },
+  { X_OPCODE(31,242,0),    X_MASK,   {O_rS, O_rB, 0},
+    0,               "mtsrin",       0 },
+  { X_OPCODE(31,246,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,               "dcbtst",       H_RA0_IS_0 },
+  { X_OPCODE(31,247,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,               "stbux",        0 },
+  { XO_OPCODE(31,266,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "add",          0 },
+  { XO_OPCODE(31,266,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "add.",         0 },
+  { X_OPCODE(31,278,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,               "dcbt",         H_RA0_IS_0 },
+  { X_OPCODE(31,279,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,               "lhzx",         H_RA0_IS_0 },
+  { X_OPCODE(31,284,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "eqv",          0 },
+  { X_OPCODE(31,284,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "eqv.",         0 },
+  { X_OPCODE(31,306,0),    X_MASK,   {O_rB, 0},
+    0,               "tlbie",        0 },
+  { X_OPCODE(31,310,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,               "eciwx",        H_RA0_IS_0 },
+  { X_OPCODE(31,311,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,               "lhzux",        0 },
+  { X_OPCODE(31,316,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "xor",          0 },
+  { X_OPCODE(31,316,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "xor.",         0 },
+  { XFX_OPCODE(31,339,0),  XFX_MASK, {O_rD, O_spr, 0},
+    0,               "mfspr",        0 },
+  { X_OPCODE(31,343,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,               "lhax",         H_RA0_IS_0 },
+  { X_OPCODE(31,370,0),    X_MASK,   {0},
+    0,               "tlbia",        0 },
+  { XFX_OPCODE(31,371,0),  XFX_MASK, {O_rD, O_tbr, 0},
+    0,               "mftb",         0 },
+  { X_OPCODE(31,375,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,               "lhaux",        0 },
+  { X_OPCODE(31,407,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,               "sthx",         H_RA0_IS_0 },
+  { X_OPCODE(31,412,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "orc",          0 },
+  { X_OPCODE(31,412,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "orc.",         0 },
+  { X_OPCODE(31,438,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,               "ecowx",        H_RA0_IS_0 },
+  { X_OPCODE(31,439,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,               "sthux",        0 },
+  { X_OPCODE(31,444,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "or",           0 },
+  { X_OPCODE(31,444,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "or.",          0 },
+  { XO_OPCODE(31,459,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "divwu",        0 },
+  { XO_OPCODE(31,459,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "divwu.",       0 },
+  { XFX_OPCODE(31,467,0),  XFX_MASK, {O_spr, O_rS, 0},
+    0,               "mtspr",        0 },
+  { X_OPCODE(31,470,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,               "dcbi",         H_RA0_IS_0 },
+  { X_OPCODE(31,476,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "nand",         0 },
+  { X_OPCODE(31,476,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc,0},
+    0,               "nand.",        0 },
+  { XO_OPCODE(31,491,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "divw",         0 },
+  { XO_OPCODE(31,491,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "divw.",        0 },
+  { X_OPCODE(31,512,0),    X_MASK,   {O_crfD, 0},
+    0,               "mcrxr",        0 },
+  { XO_OPCODE(31,8,1,0),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "subfco",       0 },
+  { XO_OPCODE(31,8,1,1),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "subfco.",      0 },
+  { XO_OPCODE(31,10,1,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "addco",        0 },
+  { XO_OPCODE(31,10,1,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "addco.",       0 },
+  { X_OPCODE(31,533,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,               "lswx",         H_RA0_IS_0 },
+  { X_OPCODE(31,534,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,               "lwbrx",        H_RA0_IS_0 },
+  { X_OPCODE(31,536,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "srw",          0 },
+  { X_OPCODE(31,536,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "srw.",         0 },
+  { XO_OPCODE(31,40,1,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "subfo",        0 },
+  { XO_OPCODE(31,40,1,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "subfo.",       0 },
+  { X_OPCODE(31,566,0),    X_MASK,   {0},
+    0,               "tlbsync",      0 },
+  { X_OPCODE(31,595,0),    X_MASK,   {O_rD, O_SR, 0},
+    0,               "mfsr",         0 },
+  { X_OPCODE(31,597,0),    X_MASK,   {O_rD, O_rA, O_NB, 0},
+    0,               "lswi",         H_RA0_IS_0 },
+  { X_OPCODE(31,598,0),    X_MASK,   {0},
+    0,               "sync",         0 },
+  { XO_OPCODE(31,104,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "nego",         0 },
+  { XO_OPCODE(31,104,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "nego.",        0 },
+  { XO_OPCODE(31,136,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "subfeo",       0 },
+  { XO_OPCODE(31,136,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "subfeo.",      0 },
+  { XO_OPCODE(31,138,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "addeo",        0 },
+  { XO_OPCODE(31,138,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "addeo.",       0 },
+  { X_OPCODE(31,659,0),    X_MASK,   {O_rD, O_rB, 0},
+    0,               "mfsrin",       0 },
+  { X_OPCODE(31,661,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,               "stswx",        H_RA0_IS_0 },
+  { X_OPCODE(31,662,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,               "stwbrx",       H_RA0_IS_0 },
+  { XO_OPCODE(31,200,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "subfzeo",      0 },
+  { XO_OPCODE(31,200,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "subfzeo.",     0 },
+  { XO_OPCODE(31,202,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "addzeo",       0 },
+  { XO_OPCODE(31,202,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "addzeo.",      0 },
+  { X_OPCODE(31,725,0),    X_MASK,   {O_rS, O_rA, O_NB, 0},
+    0,               "stswi",        H_RA0_IS_0 },
+  { XO_OPCODE(31,232,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "subfmeo",      0 },
+  { XO_OPCODE(31,232,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "subfmeo.",     0 },
+  { XO_OPCODE(31,234,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "addmeo",       0 },
+  { XO_OPCODE(31,234,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,               "addmeo.",      0 },
+  { XO_OPCODE(31,235,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "mullwo",       0 },
+  { XO_OPCODE(31,235,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "mullwo.",      0 },
+  { XO_OPCODE(31,266,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "addo",         0 },
+  { XO_OPCODE(31,266,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "addo.",        0 },
+  { X_OPCODE(31,790,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,               "lhbrx",        H_RA0_IS_0 },
+  { X_OPCODE(31,792,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "sraw",         0 },
+  { X_OPCODE(31,792,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,               "sraw.",        0 },
+  { X_OPCODE(31,824,0),    X_MASK,   {O_rA, O_rS, O_SH, O_Rc, 0},
+    0,               "srawi",        0 },
+  { X_OPCODE(31,824,1),    X_MASK,   {O_rA, O_rS, O_SH, O_Rc, 0},
+    0,               "srawi.",       0 },
+  { X_OPCODE(31,854,0),    X_MASK,   {0},
+    0,               "eieio",        0 },
+  { X_OPCODE(31,918,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,               "sthbrx",       H_RA0_IS_0 },
+  { X_OPCODE(31,922,0),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,               "extsh",        0 },
+  { X_OPCODE(31,922,1),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,               "extsh.",       0 },
+  { X_OPCODE(31,954,0),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,               "extsb",        0 },
+  { X_OPCODE(31,954,1),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,               "extsb.",       0 },
+  { XO_OPCODE(31,459,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "divwuo",       0 },
+  { XO_OPCODE(31,459,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "divwuo.",      0 },
+  { X_OPCODE(31,978,0),    X_MASK,   {O_rB, 0},
+    0,               "tlbld",        0 },
+  { X_OPCODE(31,982,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,               "icbi",         H_RA0_IS_0 },
+  { XO_OPCODE(31,491,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "divwo",        0 },
+  { XO_OPCODE(31,491,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,               "divwo.",       0 },
+  { X_OPCODE(31,1010,0),   X_MASK,   {O_rB, 0},
+    0,               "tlbli",        0 },
+  { X_OPCODE(31,1014,0),   X_MASK,   {O_rA, O_rB, 0},
+    0,               "dcbz",         H_RA0_IS_0 },
+  { D_OPCODE(32),          D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,               "lwz",          H_RA0_IS_0 },
+  { D_OPCODE(33),          D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,               "lwzu",         0 },
+  { D_OPCODE(34),          D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,               "lbz",          H_RA0_IS_0 },
+  { D_OPCODE(35),          D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,               "lbzu",         0 },
+  { D_OPCODE(36),          D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,               "stw",          H_RA0_IS_0 },
+  { D_OPCODE(37),          D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,               "stwu",         0 },
+  { D_OPCODE(38),          D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,               "stb",          H_RA0_IS_0 },
+  { D_OPCODE(39),          D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,               "stbu",         0 },
+  { D_OPCODE(40),          D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,               "lhz",          H_RA0_IS_0 },
+  { D_OPCODE(41),          D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,               "lhzu",         0 },
+  { D_OPCODE(42),          D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,               "lha",          H_RA0_IS_0 },
+  { D_OPCODE(43),          D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,               "lhau",         0 },
+  { D_OPCODE(44),          D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,               "sth",          H_RA0_IS_0 },
+  { D_OPCODE(45),          D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,               "sthu",         0 },
+  { D_OPCODE(46),          D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,               "lmw",          H_RA0_IS_0 },
+  { D_OPCODE(47),          D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,               "stmw",         H_RA0_IS_0 },
+};
+
+const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]);
+
+struct spr_info spr_map[] = {
+  { SPR_XER,	"XER" },
+  { SPR_LR,	"LR" },
+  { SPR_CTR,	"CTR" },
+  { SPR_DSISR,	"DSISR" },
+  { SPR_DAR,	"DAR" },
+  { SPR_DEC,	"DEC" },
+  { SPR_SRR0,	"SRR0" },
+  { SPR_SRR1,	"SRR1" },
+  { SPR_EIE,	"EIE" },
+  { SPR_EID,	"EID" },
+  { SPR_CMPA,	"CMPA" },
+  { SPR_CMPB,	"CMPB" },
+  { SPR_CMPC,	"CMPC" },
+  { SPR_CMPD,	"CMPD" },
+  { SPR_ICR,	"ICR" },
+  { SPR_DER,	"DER" },
+  { SPR_COUNTA,	"COUNTA" },
+  { SPR_COUNTB,	"COUNTB" },
+  { SPR_CMPE,	"CMPE" },
+  { SPR_CMPF,	"CMPF" },
+  { SPR_CMPG,	"CMPG" },
+  { SPR_CMPH,	"CMPH" },
+  { SPR_LCTRL1,	"LCTRL1" },
+  { SPR_LCTRL2,	"LCTRL2" },
+  { SPR_ICTRL,	"ICTRL" },
+  { SPR_BAR,	"BAR" },
+  { SPR_USPRG0,	"USPRG0" },
+  { SPR_SPRG4_RO,	"SPRG4_RO" },
+  { SPR_SPRG5_RO,	"SPRG5_RO" },
+  { SPR_SPRG6_RO,	"SPRG6_RO" },
+  { SPR_SPRG7_RO,	"SPRG7_RO" },
+  { SPR_SPRG0,	"SPRG0" },
+  { SPR_SPRG1,	"SPRG1" },
+  { SPR_SPRG2,	"SPRG2" },
+  { SPR_SPRG3,	"SPRG3" },
+  { SPR_SPRG4,	"SPRG4" },
+  { SPR_SPRG5,	"SPRG5" },
+  { SPR_SPRG6,	"SPRG6" },
+  { SPR_SPRG7,	"SPRG7" },
+  { SPR_EAR,	"EAR" },
+  { SPR_TBL,	"TBL" },
+  { SPR_TBU,	"TBU" },
+  { SPR_IC_CST,	"IC_CST" },
+  { SPR_IC_ADR,	"IC_ADR" },
+  { SPR_IC_DAT,	"IC_DAT" },
+  { SPR_DC_CST,	"DC_CST" },
+  { SPR_DC_ADR,	"DC_ADR" },
+  { SPR_DC_DAT,	"DC_DAT" },
+  { SPR_DPDR,	"DPDR" },
+  { SPR_IMMR,	"IMMR" },
+  { SPR_MI_CTR,	"MI_CTR" },
+  { SPR_MI_AP,	"MI_AP" },
+  { SPR_MI_EPN,	"MI_EPN" },
+  { SPR_MI_TWC,	"MI_TWC" },
+  { SPR_MI_RPN,	"MI_RPN" },
+  { SPR_MD_CTR,	"MD_CTR" },
+  { SPR_M_CASID,	"M_CASID" },
+  { SPR_MD_AP,	"MD_AP" },
+  { SPR_MD_EPN,	"MD_EPN" },
+  { SPR_M_TWB,	"M_TWB" },
+  { SPR_MD_TWC,	"MD_TWC" },
+  { SPR_MD_RPN,	"MD_RPN" },
+  { SPR_M_TW,	"M_TW" },
+  { SPR_MI_DBCAM,	"MI_DBCAM" },
+  { SPR_MI_DBRAM0,	"MI_DBRAM0" },
+  { SPR_MI_DBRAM1,	"MI_DBRAM1" },
+  { SPR_MD_DBCAM,	"MD_DBCAM" },
+  { SPR_MD_DBRAM0,	"MD_DBRAM0" },
+  { SPR_MD_DBRAM1,	"MD_DBRAM1" },
+  { SPR_ZPR,	"ZPR" },
+  { SPR_PID,	"PID" },
+  { SPR_CCR0,	"CCR0" },
+  { SPR_IAC3,	"IAC3" },
+  { SPR_IAC4,	"IAC4" },
+  { SPR_DVC1,	"DVC1" },
+  { SPR_DVC2,	"DVC2" },
+  { SPR_SGR,	"SGR" },
+  { SPR_DCWR,	"DCWR" },
+  { SPR_SLER,	"SLER" },
+  { SPR_SU0R,	"SU0R" },
+  { SPR_DBCR1,	"DBCR1" },
+  { SPR_ICDBDR,	"ICDBDR" },
+  { SPR_ESR,	"ESR" },
+  { SPR_DEAR,	"DEAR" },
+  { SPR_EVPR,	"EVPR" },
+  { SPR_TSR,	"TSR" },
+  { SPR_TCR,	"TCR" },
+  { SPR_PIT,	"PIT" },
+  { SPR_SRR2,	"SRR2" },
+  { SPR_SRR3,	"SRR3" },
+  { SPR_DBSR,	"DBSR" },
+  { SPR_DBCR0,	"DBCR0" },
+  { SPR_IAC1,	"IAC1" },
+  { SPR_IAC2,	"IAC2" },
+  { SPR_DAC1,	"DAC1" },
+  { SPR_DAC2,	"DAC2" },
+  { SPR_DCCR,	"DCCR" },
+  { SPR_ICCR,	"ICCR" },
+};
+
+const unsigned int n_sprs = sizeof(spr_map) / sizeof(spr_map[0]);
+
+#endif
+
+/*
+ * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/include/bedbug/type.h b/include/bedbug/type.h
new file mode 100755
index 0000000..38ee9de
--- /dev/null
+++ b/include/bedbug/type.h
@@ -0,0 +1,26 @@
+#ifndef _TYPE_BEDBUG_H
+#define _TYPE_BEDBUG_H
+
+/* Supporting routines */
+int bedbug_puts (const char *);
+void bedbug_init (void);
+void bedbug860_init (void);
+void do_bedbug_breakpoint (struct pt_regs *);
+void bedbug_main_loop (unsigned long, struct pt_regs *);
+
+
+typedef struct {
+	int hw_debug_enabled;
+	int stopped;
+	int current_bp;
+	struct pt_regs *regs;
+
+	void (*do_break) (cmd_tbl_t *, int, int, char *[]);
+	void (*break_isr) (struct pt_regs *);
+	int (*find_empty) (void);
+	int (*set) (int, unsigned long);
+	int (*clear) (int);
+} CPU_DEBUG_CTX;
+
+
+#endif /* _TYPE_BEDBUG_H  */
diff --git a/include/bmp_layout.h b/include/bmp_layout.h
new file mode 100755
index 0000000..d823de9
--- /dev/null
+++ b/include/bmp_layout.h
@@ -0,0 +1,77 @@
+/* (C) Copyright 2002
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************/
+/* ** Layout of a bmp file						*/
+/************************************************************************/
+
+#ifndef _BMP_H_
+#define _BMP_H_
+
+typedef struct bmp_color_table_entry {
+	__u8	blue;
+	__u8	green;
+	__u8	red;
+	__u8	reserved;
+} __attribute__ ((packed)) bmp_color_table_entry_t;
+
+/* When accessing these fields, remember that they are stored in little
+   endian format, so use linux macros, e.g. le32_to_cpu(width)          */
+
+typedef struct bmp_header {
+	/* Header */
+	char signature[2];
+	__u32	file_size;
+	__u32	reserved;
+	__u32	data_offset;
+	/* InfoHeader */
+	__u32	size;
+	__u32	width;
+	__u32	height;
+	__u16	planes;
+	__u16	bit_count;
+	__u32	compression;
+	__u32	image_size;
+	__u32	x_pixels_per_m;
+	__u32	y_pixels_per_m;
+	__u32	colors_used;
+	__u32	colors_important;
+	/* ColorTable */
+
+} __attribute__ ((packed)) bmp_header_t;
+
+typedef struct bmp_image {
+	bmp_header_t header;
+	/* We use a zero sized array just as a placeholder for variable
+	   sized array */
+	bmp_color_table_entry_t color_table[0];
+} bmp_image_t;
+
+/* Data in the bmp_image is aligned to this length */
+#define BMP_DATA_ALIGN	4
+
+/* Constants for the compression field */
+#define BMP_BI_RGB	0
+#define BMP_BI_RLE8	1
+#define BMP_BI_RLE4	2
+
+#endif							/* _BMP_H_ */
diff --git a/include/bmp_logo.h b/include/bmp_logo.h
new file mode 100755
index 0000000..9c924b8
--- /dev/null
+++ b/include/bmp_logo.h
@@ -0,0 +1,1948 @@
+/*
+ * Automatically generated by "tools/bmp_logo"
+ *
+ * DO NOT EDIT
+ *
+ */
+
+
+#ifndef __BMP_LOGO_H__
+#define __BMP_LOGO_H__
+
+#define BMP_LOGO_WIDTH		160
+#define BMP_LOGO_HEIGHT		96
+#define BMP_LOGO_COLORS		31
+#define BMP_LOGO_OFFSET		16
+
+unsigned short bmp_logo_palette[] = {
+	0x0343,  0x0454,  0x0565,  0x0565,  0x0676,  0x0787,  0x0898,  0x0999,
+	0x0AAA,  0x0ABA,  0x0BCB,  0x0CCC,  0x0DDD,  0x0EEE,  0x0FFF,  0x0FB3,
+	0x0FB4,  0x0FC4,  0x0FC5,  0x0FC6,  0x0FD7,  0x0FD8,  0x0FD9,  0x0FDA,
+	0x0FEA,  0x0FEB,  0x0FEC,  0x0FFD,  0x0FFE,  0x0FFF,  0x0FFF,
+};
+
+unsigned char bmp_logo_bitmap[] = {
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B,
+	0x1B, 0x1B, 0x1B, 0x1B, 0x1B, 0x1B, 0x1B, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x1B, 0x11, 0x10, 0x10, 0x10, 0x10,
+	0x14, 0x1E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x1B, 0x14, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x1B, 0x14, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x14, 0x1C, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x22, 0x2A, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x29, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x14,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x18, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x18, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x12, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x19,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x18, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2D, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x28, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x1C, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x19, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x12, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x1B, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x18,
+	0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x18, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x16, 0x2E, 0x17, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x19, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x2B, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2D, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x28, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x20, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x22, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x22, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x14, 0x17, 0x15, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x17, 0x1B, 0x2E, 0x1A, 0x14, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x17, 0x1B, 0x2E, 0x1B,
+	0x14, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1B, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2D, 0x29,
+	0x23, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x23, 0x2A,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x14, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x14, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x1B, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x15, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x17, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x12, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x19, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2B, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x24, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x12, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x14, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x1B, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x1E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x1A, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1C, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x16, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x11, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x11, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1E, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x1E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x1A, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2B, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x28, 0x2E, 0x2A, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x29, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x1E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x19, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x1E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x11, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x21, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x12, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x1D, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x14, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x1B, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x2A, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x14, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x1B, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x1B, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x23, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x17, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x20, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x22, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x18, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x23, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x17, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x23, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x2A, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x17,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x1E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x21, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x2D, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x1E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x12, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x1D, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x18, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x1D, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x22, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x20, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x16, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2D, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x1D, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x1C, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x1C, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x1E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x11, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x1E, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x17, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x16, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2D, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x21, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x24, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x1D, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x14, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x11, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x18,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x15, 0x2E, 0x2E, 0x2E, 0x19,
+	0x12, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x11, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x1E, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x1B, 0x2E, 0x2E, 0x1B, 0x16, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x19, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2D, 0x26,
+	0x22, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x22, 0x27,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x13, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x19, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2D, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2D, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x12, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x1C, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2A, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x20, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x13, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x2C, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2D, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x11, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x1C, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1C,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x11, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x12, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x1F, 0x2A, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2B, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x13, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1B,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x1D, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x12, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x20,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1A, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x11, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x15, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x1F,
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x2D, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x29, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x17, 0x14, 0x10, 0x11, 0x14,
+	0x1A, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x1B, 0x17, 0x17, 0x1A, 0x1B, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2B, 0x26,
+	0x2A, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2A, 0x26,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x17, 0x1B, 0x1B, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x16, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10,
+	0x1E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x12, 0x10, 0x10, 0x14, 0x14, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16,
+	0x10, 0x10, 0x14, 0x14, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x12, 0x10, 0x1B, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x17, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x13, 0x14, 0x13, 0x10, 0x10, 0x1C, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x2E,
+	0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x18, 0x10, 0x10, 0x17, 0x14, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10,
+	0x16, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x11,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x19, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x10,
+	0x1D, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x12,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x10, 0x10, 0x19, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x15,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x1B, 0x10, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x15, 0x10, 0x10, 0x10,
+	0x1D, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x1B,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x14, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x10,
+	0x19, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x10,
+	0x1B, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1E,
+	0x10, 0x10, 0x10, 0x17, 0x17, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x1B,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x1E, 0x12, 0x10,
+	0x2E, 0x2E, 0x2E, 0x18, 0x10, 0x2E, 0x17, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10,
+	0x1C, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x1B,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x15, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x17,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x14, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x1B,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x14,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10, 0x11, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x17, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x13, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x17,
+	0x10, 0x10, 0x10, 0x18, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x1B,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x17, 0x10, 0x10, 0x10, 0x10, 0x10, 0x19,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x17, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x17, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x13, 0x10, 0x1A, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x1E, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x19, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x19, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1C, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x16, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x15, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x17,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x1E, 0x10, 0x12, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x12,
+	0x11, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x1C, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1A, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x10, 0x1C,
+	0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x16, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x1A, 0x2E,
+	0x2E, 0x1D, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x14, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x1E, 0x10, 0x19, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x1A, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x13,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x17, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x13, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x17, 0x10, 0x1C, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x14, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x11, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x14,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x18,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x1D, 0x10, 0x15, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x14, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x19, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x14, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x19, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x14, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10,
+	0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1A, 0x10,
+	0x14, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x1B, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x1C, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x14, 0x10, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x1A, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x1C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x13, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x13, 0x10, 0x10, 0x10, 0x10, 0x10, 0x16, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x17, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x13, 0x10,
+	0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x11, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x1E, 0x10, 0x16, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x1A, 0x10, 0x19, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x11, 0x10, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x10, 0x10, 0x10, 0x11, 0x14,
+	0x10, 0x10, 0x10, 0x17, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x2E,
+	0x2E, 0x2E, 0x2E, 0x2E, 0x2E, 0x16, 0x10, 0x10,
+	0x10, 0x14, 0x13, 0x10, 0x10, 0x10, 0x2E, 0x2E,
+
+};
+
+#endif /* __BMP_LOGO_H__ */
diff --git a/include/bzlib.h b/include/bzlib.h
new file mode 100755
index 0000000..2d864d5
--- /dev/null
+++ b/include/bzlib.h
@@ -0,0 +1,329 @@
+/*
+ * This file is a modified version of bzlib.h from the bzip2-1.0.2
+ * distribution which can be found at http://sources.redhat.com/bzip2/
+ */
+
+/*-------------------------------------------------------------*/
+/*--- Public header file for the library.                   ---*/
+/*---                                               bzlib.h ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+  This file is a part of bzip2 and/or libbzip2, a program and
+  library for lossless, block-sorting data compression.
+
+  Copyright (C) 1996-2002 Julian R Seward.  All rights reserved.
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+  1. Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+  2. The origin of this software must not be misrepresented; you must
+     not claim that you wrote the original software.  If you use this
+     software in a product, an acknowledgment in the product
+     documentation would be appreciated but is not required.
+
+  3. Altered source versions must be plainly marked as such, and must
+     not be misrepresented as being the original software.
+
+  4. The name of the author may not be used to endorse or promote
+     products derived from this software without specific prior written
+     permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+  OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+  DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+  GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+  Julian Seward, Cambridge, UK.
+  jseward@acm.org
+  bzip2/libbzip2 version 1.0 of 21 March 2000
+
+  This program is based on (at least) the work of:
+     Mike Burrows
+     David Wheeler
+     Peter Fenwick
+     Alistair Moffat
+     Radford Neal
+     Ian H. Witten
+     Robert Sedgewick
+     Jon L. Bentley
+
+  For more information on these sources, see the manual.
+--*/
+
+
+#ifndef _BZLIB_H
+#define _BZLIB_H
+
+/* Configure for U-Boot environment */
+#define BZ_NO_STDIO
+#define BZ_NO_COMPRESS
+/* End of configuration for U-Boot environment */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BZ_RUN               0
+#define BZ_FLUSH             1
+#define BZ_FINISH            2
+
+#define BZ_OK                0
+#define BZ_RUN_OK            1
+#define BZ_FLUSH_OK          2
+#define BZ_FINISH_OK         3
+#define BZ_STREAM_END        4
+#define BZ_SEQUENCE_ERROR    (-1)
+#define BZ_PARAM_ERROR       (-2)
+#define BZ_MEM_ERROR         (-3)
+#define BZ_DATA_ERROR        (-4)
+#define BZ_DATA_ERROR_MAGIC  (-5)
+#define BZ_IO_ERROR          (-6)
+#define BZ_UNEXPECTED_EOF    (-7)
+#define BZ_OUTBUFF_FULL      (-8)
+#define BZ_CONFIG_ERROR      (-9)
+
+typedef
+   struct {
+      char *next_in;
+      unsigned int avail_in;
+      unsigned int total_in_lo32;
+      unsigned int total_in_hi32;
+
+      char *next_out;
+      unsigned int avail_out;
+      unsigned int total_out_lo32;
+      unsigned int total_out_hi32;
+
+      void *state;
+
+      void *(*bzalloc)(void *,int,int);
+      void (*bzfree)(void *,void *);
+      void *opaque;
+   }
+   bz_stream;
+
+
+#ifndef BZ_IMPORT
+#define BZ_EXPORT
+#endif
+
+#ifdef _WIN32
+#   include <windows.h>
+#   ifdef small
+      /* windows.h define small to char */
+#      undef small
+#   endif
+#   ifdef BZ_EXPORT
+#   define BZ_API(func) WINAPI func
+#   define BZ_EXTERN extern
+#   else
+   /* import windows dll dynamically */
+#   define BZ_API(func) (WINAPI * func)
+#   define BZ_EXTERN
+#   endif
+#else
+#   define BZ_API(func) func
+#   define BZ_EXTERN extern
+#endif
+
+
+/*-- Core (low-level) library functions --*/
+
+BZ_EXTERN int BZ_API(BZ2_bzCompressInit) (
+      bz_stream* strm,
+      int        blockSize100k,
+      int        verbosity,
+      int        workFactor
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzCompress) (
+      bz_stream* strm,
+      int action
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzCompressEnd) (
+      bz_stream* strm
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompressInit) (
+      bz_stream *strm,
+      int       verbosity,
+      int       small
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompress) (
+      bz_stream* strm
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompressEnd) (
+      bz_stream *strm
+   );
+
+
+/*-- High(er) level library functions --*/
+
+#ifndef BZ_NO_STDIO
+#define BZ_MAX_UNUSED 5000
+
+/* Need a definitition for FILE */
+#include <stdio.h>
+
+typedef void BZFILE;
+
+BZ_EXTERN BZFILE* BZ_API(BZ2_bzReadOpen) (
+      int*  bzerror,
+      FILE* f,
+      int   verbosity,
+      int   small,
+      void* unused,
+      int   nUnused
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzReadClose) (
+      int*    bzerror,
+      BZFILE* b
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzReadGetUnused) (
+      int*    bzerror,
+      BZFILE* b,
+      void**  unused,
+      int*    nUnused
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzRead) (
+      int*    bzerror,
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN BZFILE* BZ_API(BZ2_bzWriteOpen) (
+      int*  bzerror,
+      FILE* f,
+      int   blockSize100k,
+      int   verbosity,
+      int   workFactor
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWrite) (
+      int*    bzerror,
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWriteClose) (
+      int*          bzerror,
+      BZFILE*       b,
+      int           abandon,
+      unsigned int* nbytes_in,
+      unsigned int* nbytes_out
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWriteClose64) (
+      int*          bzerror,
+      BZFILE*       b,
+      int           abandon,
+      unsigned int* nbytes_in_lo32,
+      unsigned int* nbytes_in_hi32,
+      unsigned int* nbytes_out_lo32,
+      unsigned int* nbytes_out_hi32
+   );
+#endif
+
+
+/*-- Utility functions --*/
+
+BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffCompress) (
+      char*         dest,
+      unsigned int* destLen,
+      char*         source,
+      unsigned int  sourceLen,
+      int           blockSize100k,
+      int           verbosity,
+      int           workFactor
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffDecompress) (
+      char*         dest,
+      unsigned int* destLen,
+      char*         source,
+      unsigned int  sourceLen,
+      int           small,
+      int           verbosity
+   );
+
+
+/*--
+   Code contributed by Yoshioka Tsuneo
+   (QWF00133@niftyserve.or.jp/tsuneo-y@is.aist-nara.ac.jp),
+   to support better zlib compatibility.
+   This code is not _officially_ part of libbzip2 (yet);
+   I haven't tested it, documented it, or considered the
+   threading-safeness of it.
+   If this code breaks, please contact both Yoshioka and me.
+--*/
+
+BZ_EXTERN const char * BZ_API(BZ2_bzlibVersion) (
+      void
+   );
+
+#ifndef BZ_NO_STDIO
+BZ_EXTERN BZFILE * BZ_API(BZ2_bzopen) (
+      const char *path,
+      const char *mode
+   );
+
+BZ_EXTERN BZFILE * BZ_API(BZ2_bzdopen) (
+      int        fd,
+      const char *mode
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzread) (
+      BZFILE* b,
+      void* buf,
+      int len
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzwrite) (
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzflush) (
+      BZFILE* b
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzclose) (
+      BZFILE* b
+   );
+
+BZ_EXTERN const char * BZ_API(BZ2_bzerror) (
+      BZFILE *b,
+      int    *errnum
+   );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*-------------------------------------------------------------*/
+/*--- end                                           bzlib.h ---*/
+/*-------------------------------------------------------------*/
diff --git a/include/circbuf.h b/include/circbuf.h
new file mode 100755
index 0000000..e10ed95
--- /dev/null
+++ b/include/circbuf.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#ifndef __CIRCBUF_H__
+#define __CIRCBUF_H__
+
+typedef struct circbuf {
+	unsigned int size;	/* current number of bytes held */
+	unsigned int totalsize; /* number of bytes allocated */
+
+	char *top;		/* pointer to current buffer start */
+	char *tail;		/* pointer to space for next element */
+
+	char *data;		/* all data */
+	char *end;		/* end of data buffer */
+} circbuf_t;
+
+int buf_init (circbuf_t * buf, unsigned int size);
+int buf_free (circbuf_t * buf);
+int buf_pop (circbuf_t * buf, char *dest, unsigned int len);
+int buf_push (circbuf_t * buf, const char *src, unsigned int len);
+
+#endif
diff --git a/include/clps7111.h b/include/clps7111.h
new file mode 100755
index 0000000..d122d84
--- /dev/null
+++ b/include/clps7111.h
@@ -0,0 +1,276 @@
+/*
+ *  linux/include/asm-arm/hardware/clps7111.h
+ *
+ *  This file contains the hardware definitions of the CLPS7111 internal
+ *  registers.
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_HARDWARE_CLPS7111_H
+#define __ASM_HARDWARE_CLPS7111_H
+
+#define CLPS7111_PHYS_BASE	(0x80000000)
+
+#ifndef __ASSEMBLY__
+#define clps_readb(off)		__raw_readb(CLPS7111_BASE + (off))
+#define clps_readl(off)		__raw_readl(CLPS7111_BASE + (off))
+#define clps_writeb(val,off)	__raw_writeb(val, CLPS7111_BASE + (off))
+#define clps_writel(val,off)	__raw_writel(val, CLPS7111_BASE + (off))
+#endif
+
+#define PADR		(0x0000)
+#define PBDR		(0x0001)
+#define PDDR		(0x0003)
+#define PADDR		(0x0040)
+#define PBDDR		(0x0041)
+#define PDDDR		(0x0043)
+#define PEDR		(0x0080)
+#define PEDDR		(0x00c0)
+#define SYSCON1		(0x0100)
+#define SYSFLG1		(0x0140)
+#define MEMCFG1		(0x0180)
+#define MEMCFG2		(0x01c0)
+#define DRFPR		(0x0200)
+#define INTSR1		(0x0240)
+#define INTMR1		(0x0280)
+#define LCDCON		(0x02c0)
+#define TC1D		(0x0300)
+#define TC2D		(0x0340)
+#define RTCDR		(0x0380)
+#define RTCMR		(0x03c0)
+#define PMPCON		(0x0400)
+#define CODR		(0x0440)
+#define UARTDR1		(0x0480)
+#define UBRLCR1		(0x04c0)
+#define SYNCIO		(0x0500)
+#define PALLSW		(0x0540)
+#define PALMSW		(0x0580)
+#define STFCLR		(0x05c0)
+#define BLEOI		(0x0600)
+#define MCEOI		(0x0640)
+#define TEOI		(0x0680)
+#define TC1EOI		(0x06c0)
+#define TC2EOI		(0x0700)
+#define RTCEOI		(0x0740)
+#define UMSEOI		(0x0780)
+#define COEOI		(0x07c0)
+#define HALT		(0x0800)
+#define STDBY		(0x0840)
+
+#define FBADDR		(0x1000)
+#define SYSCON2		(0x1100)
+#define SYSFLG2		(0x1140)
+#define INTSR2		(0x1240)
+#define INTMR2		(0x1280)
+#define UARTDR2		(0x1480)
+#define UBRLCR2		(0x14c0)
+#define SS2DR		(0x1500)
+#define SRXEOF		(0x1600)
+#define SS2POP		(0x16c0)
+#define KBDEOI		(0x1700)
+
+/* common bits: SYSCON1 / SYSCON2 */
+#define SYSCON_UARTEN		(1 << 8)
+
+#define SYSCON1_KBDSCAN(x)	((x) & 15)
+#define SYSCON1_KBDSCANMASK	(15)
+#define SYSCON1_TC1M		(1 << 4)
+#define SYSCON1_TC1S		(1 << 5)
+#define SYSCON1_TC2M		(1 << 6)
+#define SYSCON1_TC2S		(1 << 7)
+#define SYSCON1_UART1EN		SYSCON_UARTEN
+#define SYSCON1_BZTOG		(1 << 9)
+#define SYSCON1_BZMOD		(1 << 10)
+#define SYSCON1_DBGEN		(1 << 11)
+#define SYSCON1_LCDEN		(1 << 12)
+#define SYSCON1_CDENTX		(1 << 13)
+#define SYSCON1_CDENRX		(1 << 14)
+#define SYSCON1_SIREN		(1 << 15)
+#define SYSCON1_ADCKSEL(x)	(((x) & 3) << 16)
+#define SYSCON1_ADCKSEL_MASK	(3 << 16)
+#define SYSCON1_EXCKEN		(1 << 18)
+#define SYSCON1_WAKEDIS		(1 << 19)
+#define SYSCON1_IRTXM		(1 << 20)
+
+/* common bits: SYSFLG1 / SYSFLG2 */
+#define SYSFLG_UBUSY		(1 << 11)
+#define SYSFLG_URXFE		(1 << 22)
+#define SYSFLG_UTXFF		(1 << 23)
+
+#define SYSFLG1_MCDR		(1 << 0)
+#define SYSFLG1_DCDET		(1 << 1)
+#define SYSFLG1_WUDR		(1 << 2)
+#define SYSFLG1_WUON		(1 << 3)
+#define SYSFLG1_CTS		(1 << 8)
+#define SYSFLG1_DSR		(1 << 9)
+#define SYSFLG1_DCD		(1 << 10)
+#define SYSFLG1_UBUSY		SYSFLG_UBUSY
+#define SYSFLG1_NBFLG		(1 << 12)
+#define SYSFLG1_RSTFLG		(1 << 13)
+#define SYSFLG1_PFFLG		(1 << 14)
+#define SYSFLG1_CLDFLG		(1 << 15)
+#define SYSFLG1_URXFE		SYSFLG_URXFE
+#define SYSFLG1_UTXFF		SYSFLG_UTXFF
+#define SYSFLG1_CRXFE		(1 << 24)
+#define SYSFLG1_CTXFF		(1 << 25)
+#define SYSFLG1_SSIBUSY		(1 << 26)
+#define SYSFLG1_ID		(1 << 29)
+
+#define SYSFLG2_SSRXOF		(1 << 0)
+#define SYSFLG2_RESVAL		(1 << 1)
+#define SYSFLG2_RESFRM		(1 << 2)
+#define SYSFLG2_SS2RXFE		(1 << 3)
+#define SYSFLG2_SS2TXFF		(1 << 4)
+#define SYSFLG2_SS2TXUF		(1 << 5)
+#define SYSFLG2_CKMODE		(1 << 6)
+#define SYSFLG2_UBUSY		SYSFLG_UBUSY
+#define SYSFLG2_URXFE		SYSFLG_URXFE
+#define SYSFLG2_UTXFF		SYSFLG_UTXFF
+
+#define LCDCON_GSEN		(1 << 30)
+#define LCDCON_GSMD		(1 << 31)
+
+#define SYSCON2_SERSEL		(1 << 0)
+#define SYSCON2_KBD6		(1 << 1)
+#define SYSCON2_DRAMZ		(1 << 2)
+#define SYSCON2_KBWEN		(1 << 3)
+#define SYSCON2_SS2TXEN		(1 << 4)
+#define SYSCON2_PCCARD1		(1 << 5)
+#define SYSCON2_PCCARD2		(1 << 6)
+#define SYSCON2_SS2RXEN		(1 << 7)
+#define SYSCON2_UART2EN		SYSCON_UARTEN
+#define SYSCON2_SS2MAEN		(1 << 9)
+#define SYSCON2_OSTB		(1 << 12)
+#define SYSCON2_CLKENSL		(1 << 13)
+#define SYSCON2_BUZFREQ		(1 << 14)
+
+/* common bits: UARTDR1 / UARTDR2 */
+#define UARTDR_FRMERR		(1 << 8)
+#define UARTDR_PARERR		(1 << 9)
+#define UARTDR_OVERR		(1 << 10)
+
+/* common bits: UBRLCR1 / UBRLCR2 */
+#define UBRLCR_BAUD_MASK	((1 << 12) - 1)
+#define UBRLCR_BREAK		(1 << 12)
+#define UBRLCR_PRTEN		(1 << 13)
+#define UBRLCR_EVENPRT		(1 << 14)
+#define UBRLCR_XSTOP		(1 << 15)
+#define UBRLCR_FIFOEN		(1 << 16)
+#define UBRLCR_WRDLEN5		(0 << 17)
+#define UBRLCR_WRDLEN6		(1 << 17)
+#define UBRLCR_WRDLEN7		(2 << 17)
+#define UBRLCR_WRDLEN8		(3 << 17)
+#define UBRLCR_WRDLEN_MASK	(3 << 17)
+
+#define SYNCIO_SMCKEN		(1 << 13)
+#define SYNCIO_TXFRMEN		(1 << 14)
+
+#define SYSCON3 0x2200  /* System Control register 3 ----------------------- */
+#define ADCCON  0x00000001  /* ADC configuration */
+#define CLKCTL  0x00000006  /* processor clock control */
+#define CLKCTL_18      0x0  /* 18.432 MHz */
+#define CLKCTL_36      0x2  /* 36.864 MHz */
+#define CLKCTL_49      0x4  /* 49.152 MHz */
+#define CLKCTL_73      0x6  /* 73.728 MHz */
+#define MCPSEL  0x00000008  /* MCP select */
+#define ADCCKNSEN 0x000010  /* ADC clock sense */
+#define VERSN   0x000000e0  /* additional version bits */
+#define VERSN_SHIFT     5
+#define FASTWAKE 0x0000100  /* Wakeup clock select: 0=8Hz, 1=4kHz */
+
+#define INTSR3  0x2240  /* Interrupt Status register 3 --------------------- */
+#define MCPINT  0x00000001  /* MCP interface interrupt (FIQ) */
+
+#define INTMR3  0x2280  /* Interrupt Mask register 3 ----------------------- */
+#define LEDFLSH 0x22C0  /* LED Flash control register ---------------------- */
+#define LEDFLSH_RATE       0x03  /* flash rate */
+#define LEDFLSH_RATE_SHIFT 0
+#define LEDFLSH_DUTY       0x3c  /* duty ratio */
+#define LEDFLSH_DUTY_SHIFT 2
+#define LEDFLSH_ENABLE     0x40  /* enable */
+
+#define IO_START	CLPS7111_PHYS_BASE
+
+#define IO(offset)	(IO_START + (offset))
+
+#define IO_BYTE(offset)	(*(volatile unsigned char *)(IO_START + (offset)))
+#define IO_WORD(offset)	(*(volatile unsigned long *)(IO_START + (offset)))
+
+#define IO_PADR		IO_BYTE(PADR)
+#define IO_PBDR		IO_BYTE(PBDR)
+#define IO_PDDR		IO_BYTE(PDDR)
+#define IO_PADDR	IO_BYTE(PADDR)
+#define IO_PBDDR	IO_BYTE(PBDDR)
+#define IO_PDDDR	IO_BYTE(PDDDR)
+#define IO_PEDR		IO_BYTE(PEDR)
+#define IO_PEDDR	IO_BYTE(PEDDR)
+#define IO_SYSCON	IO_WORD(SYSCON)
+#define	IO_SYSFLG	IO_WORD(SYSFLG)
+#define	IO_MEMCFG1	IO_WORD(MEMCFG1)
+#define	IO_MEMCFG2	IO_WORD(MEMCFG2)
+#define IO_DRFPR	IO_WORD(DRFPR)
+#define IO_INTSR	IO_WORD(INTSR)
+#define IO_INTMR	IO_WORD(INTMR)
+#define	IO_LCDCON	IO_WORD(LCDCON)
+#define IO_TC1D		IO_WORD(TC1D)
+#define IO_TC2D		IO_WORD(TC2D)
+#define IO_RTCDR	IO_WORD(RTCDR)
+#define IO_RTCMR	IO_WORD(RTCMR)
+#define IO_PMPCON	IO_WORD(PMPCON)
+#define IO_CODR 	IO_BYTE(CODR)
+#define IO_UARTDR	IO_WORD(UARTDR)
+#define IO_UBRLCR	IO_WORD(UBRLCR)
+#define IO_SYNCIO	IO_WORD(SYNCIO)
+#define	IO_PALLSW	IO_WORD(PALLSW)
+#define	IO_PALMSW	IO_WORD(PALMSW)
+#define IO_STFCLR	IO_WORD(STFCLR)
+#define IO_BLEOI	IO_WORD(BLEOI)
+#define IO_MCEOI	IO_WORD(MCEOI)
+#define IO_TEOI		IO_WORD(TEOI)
+#define IO_TC1EOI	IO_WORD(TC1EOI)
+#define IO_TC2EOI	IO_WORD(TC2EOI)
+#define IO_RTCEOI	IO_WORD(RTCEOI)
+#define IO_UMSEOI	IO_WORD(UMSEOI)
+#define IO_COEOI	IO_WORD(COEOI)
+#define IO_HALT		IO_WORD(HALT)
+#define IO_STDBY	IO_WORD(STDBY)
+#define IO_SYSCON1	IO_WORD(SYSCON1)
+#define IO_SYSFLG1	IO_WORD(SYSFLG1)
+#define IO_INTSR1	IO_WORD(INTSR1)
+#define IO_INTMR1	IO_WORD(INTMR1)
+#define IO_UARTDR1	IO_WORD(UARTDR1)
+#define IO_UBRLCR1	IO_WORD(UBRLCR1)
+#define IO_FRBADDR	IO_WORD(FRBADDR)
+#define IO_SYSCON2	IO_WORD(SYSCON2)
+#define IO_SYSFLG2	IO_WORD(SYSFLG2)
+#define IO_INTSR2	IO_WORD(INTSR2)
+#define IO_INTMR2	IO_WORD(INTMR2)
+#define IO_UARTDR2	IO_WORD(UARTDR2)
+#define IO_UBRLCR2	IO_WORD(UBRLCR2)
+#define IO_KBDEOI	IO_WORD(KBDEOI)
+
+#define IO_MCCR		IO_WORD(MCCR)
+#define IO_MCDR0	IO_WORD(MCDR0)
+#define IO_MCDR1	IO_WORD(MCDR1)
+#define IO_MCDR2	IO_WORD(MCDR2)
+#define IO_MCSR		IO_WORD(MCSR)
+#define IO_SYSCON3	IO_WORD(SYSCON3)
+#define IO_INTSR3	IO_WORD(INTSR3)
+#define IO_INTMR3	IO_WORD(INTMR3)
+#define IO_LEDFLSH	IO_WORD(LEDFLSH)
+
+#endif /* __ASM_HARDWARE_CLPS7111_H */
diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h
new file mode 100755
index 0000000..c32f2e0
--- /dev/null
+++ b/include/cmd_confdefs.h
@@ -0,0 +1,188 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+/*
+ * Definitions for Configuring the monitor commands
+ */
+#ifndef _CMD_CONFIG_H
+#define _CMD_CONFIG_H
+
+/*
+ * Configurable monitor commands
+ */
+#define CFG_CMD_BDI		0x00000001ULL	/* bdinfo			*/
+//#define CFG_CMD_LOADS		0x00000002ULL	/* loads			*/
+#define CFG_CMD_LOADB		0x00000004ULL	/* loadb			*/
+//#define CFG_CMD_IMI		0x00000008ULL	/* iminfo			*/
+#define CFG_CMD_CACHE		0x00000010ULL	/* icache, dcache		*/
+#define CFG_CMD_FLASH		0x00000020ULL	/* flinfo, erase, protect	*/
+#define CFG_CMD_MEMORY		0x00000040ULL	/* md, mm, nm, mw, cp, cmp,	*/
+						/* crc, base, loop, mtest	*/
+#define CFG_CMD_NET		0x00000080ULL	/* bootp, tftpboot, rarpboot	*/
+#define CFG_CMD_ENV		0x00000100ULL	/* saveenv			*/
+//#define CFG_CMD_KGDB		0x0000000000000200ULL	/* kgdb				*/
+//#define CFG_CMD_PCMCIA		0x00000400ULL	/* PCMCIA support		*/
+//#define CFG_CMD_IDE		0x00000800ULL	/* IDE harddisk support		*/
+//#define CFG_CMD_PCI		0x00001000ULL	/* pciinfo			*/
+//#define CFG_CMD_IRQ		0x00002000ULL	/* irqinfo			*/
+#define CFG_CMD_BOOTD		0x00004000ULL	/* bootd			*/
+#define CFG_CMD_CONSOLE		0x00008000ULL	/* coninfo			*/
+//#define CFG_CMD_EEPROM		0x00010000ULL	/* EEPROM read/write support	*/
+#define CFG_CMD_ASKENV		0x00020000ULL	/* ask for env variable		*/
+#define CFG_CMD_RUN		0x00040000ULL	/* run command in env variable	*/
+//#define CFG_CMD_ECHO		0x00080000ULL	/* echo arguments		*/
+//#define CFG_CMD_I2C		0x00100000ULL	/* I2C serial bus support	*/
+//#define CFG_CMD_REGINFO		0x00200000ULL	/* Register dump		*/
+#define CFG_CMD_IMMAP		0x00400000ULL	/* IMMR dump support		*/
+#define CFG_CMD_DATE		0x00800000ULL	/* support for RTC, date/time...*/
+//#define CFG_CMD_DHCP		0x01000000ULL	/* DHCP Support			*/
+//#define CFG_CMD_BEDBUG		0x02000000ULL	/* Include BedBug Debugger	*/
+//#define CFG_CMD_FDC		0x04000000ULL	/* Floppy Disk Support		*/
+#define CFG_CMD_SCSI		0x08000000ULL	/* SCSI Support			*/
+#define CFG_CMD_AUTOSCRIPT	0x10000000ULL	/* Autoscript Support		*/
+#define CFG_CMD_MII		0x20000000ULL	/* MII support			*/
+//#define CFG_CMD_SETGETDCR	0x40000000ULL	/* DCR support on 4xx		*/
+#define CFG_CMD_BSP		0x80000000ULL	/* Board Specific functions	*/
+
+//#define CFG_CMD_ELF	0x0000000100000000ULL	/* ELF (VxWorks) load/boot cmd	*/
+#define CFG_CMD_MISC	0x0000000200000000ULL	/* Misc functions like sleep etc*/
+#define CFG_CMD_USB	0x0000000400000000ULL	/* USB Support			*/
+//#define CFG_CMD_DOC	0x0000000800000000ULL	/* Disk-On-Chip Support		*/
+//#define CFG_CMD_JFFS2	0x0000001000000000ULL	/* JFFS2 Support		*/
+//#define CFG_CMD_DTT	0x0000002000000000ULL	/* Digital Therm and Thermostat */
+//#define CFG_CMD_SDRAM	0x0000004000000000ULL	/* SDRAM DIMM SPD info printout */
+//#define CFG_CMD_DIAG	0x0000008000000000ULL	/* Diagnostics			*/
+//#define CFG_CMD_FPGA	0x0000010000000000ULL	/* FPGA configuration Support	*/
+#define CFG_CMD_HWFLOW	0x0000020000000000ULL	/* RTS/CTS hw flow control	*/
+#define CFG_CMD_SAVES	0x0000040000000000ULL	/* save S record dump		*/
+//#define CFG_CMD_SPI	0x0000100000000000ULL	/* SPI utility			*/
+//#define CFG_CMD_FDOS	0x0000200000000000ULL	/* Floppy DOS support		*/
+#define CFG_CMD_VFD	0x0000400000000000ULL	/* VFD support (TRAB)		*/
+#define CFG_CMD_NAND	0x0000800000000000ULL	/* NAND support			*/
+#define CFG_CMD_BMP	0x0001000000000000ULL	/* BMP support			*/
+#define CFG_CMD_PORTIO	0x0002000000000000ULL	/* Port I/O			*/
+#define CFG_CMD_PING	0x0004000000000000ULL	/* ping support			*/
+#define CFG_CMD_MMC	0x0008000000000000ULL	/* MMC support			*/
+#define CFG_CMD_FAT	0x0010000000000000ULL	/* FAT support			*/
+//#define CFG_CMD_IMLS	0x0020000000000000ULL	/* List all found images	*/
+//#define CFG_CMD_ITEST	0x0040000000000000ULL	/* Integer (and string) test	*/
+//#define CFG_CMD_NFS	0x0080000000000000ULL	/* NFS support			*/
+//#define CFG_CMD_REISER	0x0100000000000000ULL	/* Reiserfs support		*/
+//#define CFG_CMD_CDP	0x0200000000000000ULL	/* Cisco Discovery Protocol 	*/
+//#define CFG_CMD_XIMG	0x0400000000000000ULL	/* Load part of Multi Image	*/
+#define CFG_CMD_UNIVERSE 0x0800000000000000ULL	/* Tundra Universe Support      */
+//#define CFG_CMD_EXT2	0x1000000000000000ULL	/* EXT2 Support			*/
+//#define CFG_CMD_SNTP	0x2000000000000000ULL	/* SNTP support			*/
+#define CFG_CMD_DISPLAY	0x4000000000000000ULL	/* Display support		*/
+
+//#define CFG_CMD_NANDRW	0x8000000000000000ULL
+
+#define CFG_CMD_ALL	0xFFFFFFFFFFFFFFFFULL	/* ALL commands			*/
+
+/*
+ * Commands that are considered "non-standard" for some reason
+ * (memory hogs, requires special hardware, not fully tested, etc.)
+ */
+#define CFG_CMD_NONSTD (CFG_CMD_ASKENV	| \
+			CFG_CMD_BEDBUG	| \
+			CFG_CMD_BMP	| \
+			CFG_CMD_BSP	| \
+			CFG_CMD_CACHE	| \
+			CFG_CMD_CDP	| \
+			CFG_CMD_DATE	| \
+			CFG_CMD_DHCP	| \
+			CFG_CMD_DIAG	| \
+			CFG_CMD_DISPLAY	| \
+			CFG_CMD_DOC	| \
+			CFG_CMD_DTT	| \
+			CFG_CMD_ECHO	| \
+			CFG_CMD_EEPROM	| \
+			CFG_CMD_ELF	| \
+			CFG_CMD_EXT2	| \
+			CFG_CMD_FDC	| \
+			CFG_CMD_FAT	| \
+			CFG_CMD_FDOS	| \
+			CFG_CMD_HWFLOW	| \
+			CFG_CMD_I2C	| \
+			CFG_CMD_IDE	| \
+			CFG_CMD_IMMAP	| \
+			CFG_CMD_IRQ	| \
+			CFG_CMD_JFFS2	| \
+			CFG_CMD_KGDB	| \
+			CFG_CMD_MII	| \
+			CFG_CMD_MMC	| \
+			CFG_CMD_NAND	| \
+			CFG_CMD_PCI	| \
+			CFG_CMD_PCMCIA	| \
+			CFG_CMD_PING	| \
+			CFG_CMD_PORTIO	| \
+			CFG_CMD_REGINFO | \
+			CFG_CMD_REISER	| \
+			CFG_CMD_SAVES	| \
+			CFG_CMD_SCSI	| \
+			CFG_CMD_SDRAM	| \
+			CFG_CMD_SNTP	| \
+			CFG_CMD_SPI	| \
+			CFG_CMD_UNIVERSE | \
+			CFG_CMD_USB	| \
+			CFG_CMD_VFD	| \
+			CFG_CMD_MMC)
+/*
+ * Default configuration
+ */
+#define CONFIG_CMD_DFL	(CFG_CMD_ALL & ~CFG_CMD_NONSTD)
+
+#ifndef CONFIG_COMMANDS
+#define CONFIG_COMMANDS CONFIG_CMD_DFL
+#endif
+
+/*
+ * optional BOOTP fields
+ */
+
+#define CONFIG_BOOTP_SUBNETMASK		0x00000001
+#define CONFIG_BOOTP_GATEWAY		0x00000002
+#define CONFIG_BOOTP_HOSTNAME		0x00000004
+#define CONFIG_BOOTP_NISDOMAIN		0x00000008
+#define CONFIG_BOOTP_BOOTPATH		0x00000010
+#define CONFIG_BOOTP_BOOTFILESIZE	0x00000020
+#define CONFIG_BOOTP_DNS		0x00000040
+#define CONFIG_BOOTP_DNS2		0x00000080
+#define CONFIG_BOOTP_SEND_HOSTNAME	0x00000100
+#define CONFIG_BOOTP_NTPSERVER		0x00000200
+#define CONFIG_BOOTP_TIMEOFFSET		0x00000400
+
+#define CONFIG_BOOTP_VENDOREX		0x80000000
+
+#define CONFIG_BOOTP_ALL		(~CONFIG_BOOTP_VENDOREX)
+
+#define CONFIG_BOOTP_DEFAULT		(CONFIG_BOOTP_SUBNETMASK | \
+					CONFIG_BOOTP_GATEWAY	 | \
+					CONFIG_BOOTP_HOSTNAME	 | \
+					CONFIG_BOOTP_BOOTPATH)
+
+#ifndef CONFIG_BOOTP_MASK
+#define CONFIG_BOOTP_MASK		CONFIG_BOOTP_DEFAULT
+#endif
+
+#endif	/* _CMD_CONFIG_H */
diff --git a/include/command.h b/include/command.h
new file mode 100755
index 0000000..a2936ad
--- /dev/null
+++ b/include/command.h
@@ -0,0 +1,107 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *  Definitions for Command Processor
+ */
+#ifndef __COMMAND_H
+#define __COMMAND_H
+
+#ifndef NULL
+#define NULL	0
+#endif
+
+#ifndef	__ASSEMBLY__
+/*
+ * Monitor Command Table
+ */
+
+struct cmd_tbl_s {
+	char		*name;		/* Command Name			*/
+	int		maxargs;	/* maximum number of arguments	*/
+	int		repeatable;	/* autorepeat allowed?		*/
+					/* Implementation function	*/
+	int		(*cmd)(struct cmd_tbl_s *, int, int, char *[]);
+	char		*usage;		/* Usage message	(short)	*/
+#ifdef	CFG_LONGHELP
+	char		*help;		/* Help  message	(long)	*/
+#endif
+#ifdef CONFIG_AUTO_COMPLETE
+	/* do auto completion on the arguments */
+	int		(*complete)(int argc, char *argv[], char last_char, int maxv, char *cmdv[]);
+#endif
+};
+
+typedef struct cmd_tbl_s	cmd_tbl_t;
+
+extern cmd_tbl_t  __u_boot_cmd_start;
+extern cmd_tbl_t  __u_boot_cmd_end;
+
+
+/* common/command.c */
+cmd_tbl_t *find_cmd(const char *cmd);
+
+#ifdef CONFIG_AUTO_COMPLETE
+extern void install_auto_complete(void);
+extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp);
+#endif
+
+/*
+ * Monitor Command
+ *
+ * All commands use a common argument format:
+ *
+ * void function (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+ */
+
+typedef	void 	command_t (cmd_tbl_t *, int, int, char *[]);
+
+#endif	/* __ASSEMBLY__ */
+
+/*
+ * Command Flags:
+ */
+#define CMD_FLAG_REPEAT		0x0001	/* repeat last command		*/
+#define CMD_FLAG_BOOTD		0x0002	/* command is from bootd	*/
+
+/*
+ * Configurable monitor commands definitions have been moved
+ * to include/cmd_confdefs.h
+ */
+
+
+#define Struct_Section  __attribute__ ((unused,section (".u_boot_cmd")))
+
+#ifdef  CFG_LONGHELP
+
+#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
+cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage, help}
+
+#else	/* no long help info */
+
+#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
+cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage}
+
+#endif	/* CFG_LONGHELP */
+
+#endif	/* __COMMAND_H */
diff --git a/include/common.h b/include/common.h
new file mode 100755
index 0000000..e0b8281
--- /dev/null
+++ b/include/common.h
@@ -0,0 +1,757 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __COMMON_H_
+#define __COMMON_H_	1
+
+#undef	_LINUX_CONFIG_H
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+typedef unsigned char		uchar;
+typedef volatile unsigned long	vu_long;
+typedef volatile unsigned short vu_short;
+typedef volatile unsigned char	vu_char;
+
+#include <config.h>
+#include <linux/bitops.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <asm/ptrace.h>
+#include <stdarg.h>
+#if defined(CONFIG_PCI) && defined(CONFIG_440)
+#include <pci.h>
+#endif
+#if defined(CONFIG_8xx)
+#include <asm/8xx_immap.h>
+#if defined(CONFIG_MPC852)	|| defined(CONFIG_MPC852T)	|| \
+    defined(CONFIG_MPC859)	|| defined(CONFIG_MPC859T)	|| \
+    defined(CONFIG_MPC859DSL)	|| \
+    defined(CONFIG_MPC866)	|| defined(CONFIG_MPC866T)	|| \
+    defined(CONFIG_MPC866P)
+# define CONFIG_MPC866_FAMILY 1
+#elif defined(CONFIG_MPC870) \
+   || defined(CONFIG_MPC875) \
+   || defined(CONFIG_MPC880) \
+   || defined(CONFIG_MPC885)
+# define CONFIG_MPC885_FAMILY   1
+#endif
+#if   defined(CONFIG_MPC860)	   \
+   || defined(CONFIG_MPC860T)	   \
+   || defined(CONFIG_MPC866_FAMILY) \
+   || defined(CONFIG_MPC885_FAMILY)
+# define CONFIG_MPC86x 1
+#endif
+#elif defined(CONFIG_5xx)
+#include <asm/5xx_immap.h>
+#elif defined(CONFIG_MPC5xxx)
+#include <mpc5xxx.h>
+#elif defined(CONFIG_MPC8220)
+#include <asm/immap_8220.h>
+#elif defined(CONFIG_8260)
+#if   defined(CONFIG_MPC8247) \
+   || defined(CONFIG_MPC8248) \
+   || defined(CONFIG_MPC8271) \
+   || defined(CONFIG_MPC8272)
+#define CONFIG_MPC8272_FAMILY	1
+#endif
+#if defined(CONFIG_MPC8272_FAMILY)
+#define CONFIG_MPC8260	1
+#endif
+#include <asm/immap_8260.h>
+#endif
+#ifdef CONFIG_MPC85xx
+#include <mpc85xx.h>
+#include <asm/immap_85xx.h>
+#endif
+#ifdef CONFIG_MPC83XX
+#include <mpc83xx.h>
+#include <asm/immap_83xx.h>
+#endif
+#ifdef	CONFIG_4xx
+#include <ppc4xx.h>
+#endif
+#ifdef CONFIG_HYMOD
+#include <board/hymod/hymod.h>
+#endif
+#ifdef CONFIG_ARM
+#define asmlinkage	/* nothing */
+#endif
+
+#include <part.h>
+#include <flash.h>
+#include <image.h>
+//#define DEBUG  1  //Charles
+#undef   DEBUG
+#ifdef	DEBUG
+#define debug(fmt,args...)	printf (fmt ,##args)
+#define debugX(level,fmt,args...) if (DEBUG>=level) printf(fmt,##args);
+#else
+#define debug(fmt,args...)
+#define debugX(level,fmt,args...)
+#endif	/* DEBUG */
+
+
+
+
+/*======rockpzhang======*/ 
+
+#ifdef DEBUG
+#define _DEBUG	1
+#else
+#define _DEBUG	0
+#endif
+
+
+/*
+ * An assertion is run-time check done in debug mode only. If DEBUG is not
+ * defined then it is skipped. If DEBUG is defined and the assertion fails,
+ * then it calls panic*( which may or may not reset/halt U-Boot (see
+ * CONFIG_PANIC_HANG), It is hoped that all failing assertions are found
+ * before release, and after release it is hoped that they don't matter. But
+ * in any case these failing assertions cannot be fixed with a reset (which
+ * may just do the same assertion again).
+ */
+void __assert_fail(const char *assertion, const char *file, unsigned line,
+		   const char *function);
+#define assert(x) \
+	({ if (!(x) && _DEBUG) \
+		__assert_fail(#x, __FILE__, __LINE__, __func__); })
+
+#define error(fmt, args...) do {					\
+		printf("ERROR: " fmt "\nat %s:%d/%s()\n",		\
+			##args, __FILE__, __LINE__, __func__);		\
+} while (0)
+
+int strcmp_compar(const void *, const void *);
+/*======*/
+
+
+
+
+
+
+
+typedef void (interrupt_handler_t)(void *);
+
+#include <asm/u-boot.h> /* boot information for Linux kernel */
+#include <asm/global_data.h>	/* global data used for startup functions */
+
+/*
+ * enable common handling for all TQM8xxL/M boards:
+ * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards
+ * - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards
+ */
+#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \
+    defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \
+    defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M)
+# ifndef CONFIG_TQM8xxM
+#  define CONFIG_TQM8xxM
+# endif
+#endif
+#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \
+    defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \
+    defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM)
+# ifndef CONFIG_TQM8xxL
+#  define CONFIG_TQM8xxL
+# endif
+#endif
+
+#ifndef CONFIG_SERIAL_MULTI
+
+#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) \
+ || defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
+ || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
+
+#define CONFIG_SERIAL_MULTI	1
+
+#endif
+
+#endif /* CONFIG_SERIAL_MULTI */
+
+/*
+ * General Purpose Utilities
+ */
+#define min(X, Y)				\
+	({ typeof (X) __x = (X), __y = (Y);	\
+		(__x < __y) ? __x : __y; })
+
+#define max(X, Y)				\
+	({ typeof (X) __x = (X), __y = (Y);	\
+		(__x > __y) ? __x : __y; })
+
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @ptr:	the pointer to the member.
+ * @type:	the type of the container struct this is embedded in.
+ * @member:	the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+/*
+ * Function Prototypes
+ */
+
+#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
+void	serial_buffered_init (void);
+void	serial_buffered_putc (const char);
+void	serial_buffered_puts (const char *);
+int	serial_buffered_getc (void);
+int	serial_buffered_tstc (void);
+#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
+
+void	hang		(void) __attribute__ ((noreturn));
+
+/* */
+long int initdram (int);
+int	display_options (void);
+void	print_size (ulong, const char *);
+
+/* common/main.c */
+void	main_loop	(void);
+int	run_command	(const char *cmd, int flag);
+int	readline	(const char *const prompt);
+void	init_cmd_timeout(void);
+void	reset_cmd_timeout(void);
+
+/* lib_$(ARCH)/board.c */
+void	board_init_f  (ulong);
+void	board_init_r  (gd_t *, ulong);
+int	checkboard    (void);
+int	checkflash    (void);
+int	checkdram     (void);
+char *	strmhz(char *buf, long hz);
+int	last_stage_init(void);
+extern ulong monitor_flash_len;
+
+/* common/flash.c */
+void flash_perror (int);
+
+/* common/cmd_autoscript.c */
+int	autoscript (ulong addr);
+
+/* common/cmd_bootm.c */
+void	print_image_hdr (image_header_t *hdr);
+
+extern ulong load_addr;		/* Default Load Address */
+
+/* common/cmd_nvedit.c */
+int	env_init     (void);
+void	env_relocate (void);
+char	*getenv	     (char *);
+int	getenv_r     (char *name, char *buf, unsigned len);
+int	saveenv	     (void);
+#ifdef CONFIG_PPC		/* ARM version to be fixed! */
+int inline setenv   (char *, char *);
+#else
+int	setenv	     (char *, char *);
+#endif /* CONFIG_PPC */
+#ifdef CONFIG_ARM
+# include <asm/mach-types.h>
+# include <asm/setup.h>
+# include <asm/u-boot-arm.h>	/* ARM version to be fixed! */
+#endif /* CONFIG_ARM */
+#ifdef CONFIG_I386		/* x86 version to be fixed! */
+# include <asm/u-boot-i386.h>
+#endif /* CONFIG_I386 */
+
+#ifdef CONFIG_AUTO_COMPLETE
+int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
+#endif
+
+void	pci_init      (void);
+void	pci_init_board(void);
+void	pciinfo	      (int, int);
+
+#if defined(CONFIG_PCI) && defined(CONFIG_440)
+#   if defined(CFG_PCI_PRE_INIT)
+    int	   pci_pre_init	       (struct pci_controller * );
+#   endif
+#   if defined(CFG_PCI_TARGET_INIT)
+	void	pci_target_init	     (struct pci_controller *);
+#   endif
+#   if defined(CFG_PCI_MASTER_INIT)
+	void	pci_master_init	     (struct pci_controller *);
+#   endif
+    int	    is_pci_host		(struct pci_controller *);
+#endif
+
+int	misc_init_f   (void);
+int	misc_init_r   (void);
+
+/* common/exports.c */
+void	jumptable_init(void);
+
+/* common/memsize.c */
+int	get_ram_size  (volatile long *, long);
+
+/* $(BOARD)/$(BOARD).c */
+void	reset_phy     (void);
+void	fdc_hw_init   (void);
+
+/* $(BOARD)/eeprom.c */
+void eeprom_init  (void);
+#ifndef CONFIG_SPI
+int  eeprom_probe (unsigned dev_addr, unsigned offset);
+#endif
+int  eeprom_read  (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
+int  eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
+#ifdef CONFIG_LWMON
+extern uchar pic_read  (uchar reg);
+extern void  pic_write (uchar reg, uchar val);
+#endif
+
+/*
+ * Set this up regardless of board
+ * type, to prevent errors.
+ */
+#if defined(CONFIG_SPI) || !defined(CFG_I2C_EEPROM_ADDR)
+# define CFG_DEF_EEPROM_ADDR 0
+#else
+# define CFG_DEF_EEPROM_ADDR CFG_I2C_EEPROM_ADDR
+#endif /* CONFIG_SPI || !defined(CFG_I2C_EEPROM_ADDR) */
+
+#if defined(CONFIG_SPI)
+extern void spi_init_f (void);
+extern void spi_init_r (void);
+extern ssize_t spi_read	 (uchar *, int, uchar *, int);
+extern ssize_t spi_write (uchar *, int, uchar *, int);
+#endif
+
+#ifdef CONFIG_RPXCLASSIC
+void rpxclassic_init (void);
+#endif
+
+void rpxlite_init (void);
+
+#ifdef CONFIG_MBX
+/* $(BOARD)/mbx8xx.c */
+void	mbx_init (void);
+void	board_serial_init (void);
+void	board_ether_init (void);
+#endif
+
+#if defined(CONFIG_RPXCLASSIC)	|| defined(CONFIG_MBX) || \
+    defined(CONFIG_IAD210)	|| defined(CONFIG_XPEDITE1K) || \
+    defined(CONFIG_METROBOX)    || defined(CONFIG_KAREF)
+void	board_get_enetaddr (uchar *addr);
+#endif
+
+#ifdef CONFIG_HERMES
+/* $(BOARD)/hermes.c */
+void hermes_start_lxt980 (int speed);
+#endif
+
+#ifdef CONFIG_EVB64260
+void  evb64260_init(void);
+void  debug_led(int, int);
+void  display_mem_map(void);
+void  perform_soft_reset(void);
+#endif
+
+void	load_sernum_ethaddr (void);
+
+/* $(BOARD)/$(BOARD).c */
+int board_early_init_f (void);
+int board_late_init (void);
+int board_postclk_init (void); /* after clocks/timebase, before env/serial */
+int board_early_init_r (void);
+void board_poweroff (void);
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void);
+#endif /* CFG_DRAM_TEST */
+
+/* $(CPU)/start.S */
+#if defined(CONFIG_5xx) || \
+    defined(CONFIG_8xx)
+uint	get_immr      (uint);
+#endif
+uint	get_pir	      (void);
+#if defined(CONFIG_MPC5xxx)
+uint	get_svr       (void);
+#endif
+uint	get_pvr	      (void);
+uint	get_svr	      (void);
+uint	rd_ic_cst     (void);
+void	wr_ic_cst     (uint);
+void	wr_ic_adr     (uint);
+uint	rd_dc_cst     (void);
+void	wr_dc_cst     (uint);
+void	wr_dc_adr     (uint);
+int	icache_status (void);
+void	icache_enable (void);
+void	icache_disable(void);
+int	dcache_status (void);
+void	dcache_enable (void);
+void	dcache_disable(void);
+void	relocate_code (ulong, gd_t *, ulong);
+ulong	get_endaddr   (void);
+void	trap_init     (ulong);
+#if defined (CONFIG_4xx)	|| \
+    defined (CONFIG_MPC5xxx)	|| \
+    defined (CONFIG_74xx_7xx)	|| \
+    defined (CONFIG_74x)	|| \
+    defined (CONFIG_75x)	|| \
+    defined (CONFIG_74xx)	|| \
+    defined (CONFIG_MPC8220)	|| \
+    defined(CONFIG_MPC85xx)
+unsigned char	in8(unsigned int);
+void		out8(unsigned int, unsigned char);
+unsigned short	in16(unsigned int);
+unsigned short	in16r(unsigned int);
+void		out16(unsigned int, unsigned short value);
+void		out16r(unsigned int, unsigned short value);
+unsigned long	in32(unsigned int);
+unsigned long	in32r(unsigned int);
+void		out32(unsigned int, unsigned long value);
+void		out32r(unsigned int, unsigned long value);
+void		ppcDcbf(unsigned long value);
+void		ppcDcbi(unsigned long value);
+void		ppcSync(void);
+void		ppcDcbz(unsigned long value);
+#endif
+
+#define out32r(addr, val)	(*(volatile unsigned int *)(addr)) = val
+//#define REG_GET32(addr)		(*(volatile unsigned int *)(addr))
+//#define REG_VAL32(addr)		(*(volatile unsigned int *)(addr))
+#define out16r(addr,  val)	(*(volatile unsigned short *)(addr)) = val
+#define in16r(addr)		(*(volatile unsigned short *)(addr))
+//#define REG_VAL16(addr)		(*(volatile unsigned short *)(addr))
+//#define REG_SET8(addr, val)	(*(volatile unsigned char *)(addr)) = val
+//#define REG_GET8(addr)		(*(volatile unsigned char *)(addr))
+//#define REG_VAL8(addr)		(*(volatile unsigned char *)(addr))
+/* $(CPU)/cpu.c */
+int	checkcpu      (void);
+int	checkicache   (void);
+int	checkdcache   (void);
+void	upmconfig     (unsigned int, unsigned int *, unsigned int);
+ulong	get_tbclk     (void);
+void	reset_cpu     (ulong addr);
+
+/* $(CPU)/serial.c */
+int	serial_init   (void);
+void	serial_addr   (unsigned int);
+void	serial_setbrg (void);
+void	serial_putc   (const char);
+void	serial_putc_raw(const char);
+void	serial_puts   (const char *);
+int	serial_getc   (void);
+int	serial_tstc   (void);
+
+void	_serial_setbrg (const int);
+void	_serial_putc   (const char, const int);
+void	_serial_putc_raw(const char, const int);
+void	_serial_puts   (const char *, const int);
+int	_serial_getc   (const int);
+int	_serial_tstc   (const int);
+
+/* $(CPU)/speed.c */
+int	get_clocks (void);
+int	get_clocks_866 (void);
+int	sdram_adjust_866 (void);
+int	adjust_sdram_tbs_8xx (void);
+#if defined(CONFIG_8260)
+int	prt_8260_clks (void);
+#elif defined(CONFIG_MPC83XX)
+int print_clock_conf(void);
+#elif defined(CONFIG_MPC5xxx)
+int	prt_mpc5xxx_clks (void);
+#endif
+#if defined(CONFIG_MPC8220)
+int	prt_mpc8220_clks (void);
+#endif
+#ifdef CONFIG_4xx
+ulong	get_OPB_freq (void);
+ulong	get_PCI_freq (void);
+#endif
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_LH7A40X)
+ulong	get_FCLK (void);
+ulong	get_HCLK (void);
+ulong	get_PCLK (void);
+ulong	get_UCLK (void);
+#endif
+#if defined(CONFIG_LH7A40X)
+ulong	get_PLLCLK (void);
+#endif
+#if defined CONFIG_INCA_IP
+uint	incaip_get_cpuclk (void);
+#endif
+#if defined(CONFIG_IMX)
+ulong get_systemPLLCLK(void);
+ulong get_FCLK(void);
+ulong get_HCLK(void);
+ulong get_BCLK(void);
+ulong get_PERCLK1(void);
+ulong get_PERCLK2(void);
+ulong get_PERCLK3(void);
+#endif
+ulong	get_bus_freq  (ulong);
+
+#if defined(CONFIG_MPC85xx)
+typedef MPC85xx_SYS_INFO sys_info_t;
+void	get_sys_info  ( sys_info_t * );
+#endif
+
+#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
+#  if defined(CONFIG_440)
+    typedef PPC440_SYS_INFO sys_info_t;
+#  else
+    typedef PPC405_SYS_INFO sys_info_t;
+#  endif
+void	get_sys_info  ( sys_info_t * );
+#endif
+
+/* $(CPU)/cpu_init.c */
+#if defined(CONFIG_8xx) || defined(CONFIG_8260)
+void	cpu_init_f    (volatile immap_t *immr);
+#endif
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2)
+void	cpu_init_f    (void);
+#endif
+
+int	cpu_init_r    (void);
+#if defined(CONFIG_8260)
+int	prt_8260_rsr  (void);
+#endif
+
+/* $(CPU)/interrupts.c */
+int	interrupt_init	   (void);
+void	timer_interrupt	   (struct pt_regs *);
+void	external_interrupt (struct pt_regs *);
+void	irq_install_handler(int, interrupt_handler_t *, void *);
+void	irq_free_handler   (int);
+void	reset_timer	   (void);
+ulong	get_timer	   (ulong base);
+void	set_timer	   (ulong t);
+void	enable_interrupts  (void);
+int	disable_interrupts (void);
+
+/* $(CPU)/.../commproc.c */
+int	dpram_init (void);
+uint	dpram_base(void);
+uint	dpram_base_align(uint align);
+uint	dpram_alloc(uint size);
+uint	dpram_alloc_align(uint size,uint align);
+void	post_word_store (ulong);
+ulong	post_word_load (void);
+void	bootcount_store (ulong);
+ulong	bootcount_load (void);
+#define BOOTCOUNT_MAGIC		0xB001C041
+
+/* $(CPU)/.../<eth> */
+void mii_init (void);
+
+/* $(CPU)/.../lcd.c */
+ulong	lcd_setmem (ulong);
+
+/* $(CPU)/.../vfd.c */
+ulong	vfd_setmem (ulong);
+
+/* $(CPU)/.../video.c */
+ulong	video_setmem (ulong);
+
+/* lib_$(ARCH)/cache.c */
+void	flush_cache   (unsigned long, unsigned long);
+
+
+/* lib_$(ARCH)/ticks.S */
+unsigned long long get_ticks(void);
+void	wait_ticks    (unsigned long);
+
+/* lib_$(ARCH)/time.c */
+void	udelay	      (unsigned long);
+ulong	usec2ticks    (unsigned long usec);
+ulong	ticks2usec    (unsigned long ticks);
+int	init_timebase (void);
+
+/* lib_generic/vsprintf.c */
+ulong	simple_strtoul(const char *cp,char **endp,unsigned int base);
+#ifdef CFG_64BIT_VSPRINTF
+unsigned long long	simple_strtoull(const char *cp,char **endp,unsigned int base);
+#endif
+long	simple_strtol(const char *cp,char **endp,unsigned int base);
+void	panic(const char *fmt, ...);
+int	sprintf(char * buf, const char *fmt, ...);
+int	vsprintf(char *buf, const char *fmt, va_list args);
+
+/* lib_generic/crc32.c */
+
+ulong crc32_no_comp (ulong, const unsigned char *, uint);
+
+/* common/console.c */
+int	console_init_f(void);	/* Before relocation; uses the serial  stuff	*/
+int	console_init_r(void);	/* After  relocation; uses the console stuff	*/
+int	console_assign (int file, char *devname);	/* Assign the console	*/
+int	ctrlc (void);
+int	had_ctrlc (void);	/* have we had a Control-C since last clear? */
+void	clear_ctrlc (void);	/* clear the Control-C condition */
+int	disable_ctrlc (int);	/* 1 to disable, 0 to enable Control-C detect */
+
+/*
+ * STDIO based functions (can always be used)
+ */
+
+/* serial stuff */
+void	serial_printf (const char *fmt, ...);
+
+/* stdin */
+int	getc(void);
+int	tstc(void);
+
+/* stdout */
+void	putc(const char c);
+void	puts(const char *s);
+int	printf(const char *fmt, ...);
+void	vprintf(const char *fmt, va_list args);
+
+/* stderr */
+#define eputc(c)		fputc(stderr, c)
+#define eputs(s)		fputs(stderr, s)
+#define eprintf(fmt,args...)	fprintf(stderr,fmt ,##args)
+
+/*
+ * FILE based functions (can only be used AFTER relocation!)
+ */
+
+#define stdin		0
+#define stdout		1
+#define stderr		2
+#define MAX_FILES	3
+#define NAND_WRITE 1
+#define NAND_READ 0
+
+void	fprintf(int file, const char *fmt, ...);
+void	fputs(int file, const char *s);
+void	fputc(int file, const char c);
+int	ftstc(int file);
+int	fgetc(int file);
+
+int	pcmcia_init (void);
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void	show_boot_progress (int status);
+#endif
+
+#ifdef CONFIG_INIT_CRITICAL
+#error CONFIG_INIT_CRITICAL is depracted!
+#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
+#endif
+
+/*
+ * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture.  It
+ * is used to align DMA buffers.
+ */
+#ifndef __ASSEMBLY__
+#include <asm/cache.h>
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#define ROUND(a,b)		(((a) + (b) - 1) & ~((b) - 1))
+#define DIV_ROUND(n,d)		(((n) + ((d)/2)) / (d))
+#define DIV_ROUND_UP(n,d)	(((n) + (d) - 1) / (d))
+#define roundup(x, y)		((((x) + ((y) - 1)) / (y)) * (y))
+
+#define ALIGN(x,a)		__ALIGN_MASK((x),(typeof(x))(a)-1)
+#define __ALIGN_MASK(x,mask)	(((x)+(mask))&~(mask))
+
+
+/*
+ * The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the
+ * stack that meets the minimum architecture alignment requirements for DMA.
+ * Such a buffer is useful for DMA operations where flushing and invalidating
+ * the cache before and after a read and/or write operation is required for
+ * correct operations.
+ *
+ * When called the macro creates an array on the stack that is sized such
+ * that:
+ *
+ * 1) The beginning of the array can be advanced enough to be aligned.
+ *
+ * 2) The size of the aligned portion of the array is a multiple of the minimum
+ *    architecture alignment required for DMA.
+ *
+ * 3) The aligned portion contains enough space for the original number of
+ *    elements requested.
+ *
+ * The macro then creates a pointer to the aligned portion of this array and
+ * assigns to the pointer the address of the first element in the aligned
+ * portion of the array.
+ *
+ * Calling the macro as:
+ *
+ *     ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024);
+ *
+ * Will result in something similar to saying:
+ *
+ *     uint32_t    buffer[1024];
+ *
+ * The following differences exist:
+ *
+ * 1) The resulting buffer is guaranteed to be aligned to the value of
+ *    ARCH_DMA_MINALIGN.
+ *
+ * 2) The buffer variable created by the macro is a pointer to the specified
+ *    type, and NOT an array of the specified type.  This can be very important
+ *    if you want the address of the buffer, which you probably do, to pass it
+ *    to the DMA hardware.  The value of &buffer is different in the two cases.
+ *    In the macro case it will be the address of the pointer, not the address
+ *    of the space reserved for the buffer.  However, in the second case it
+ *    would be the address of the buffer.  So if you are replacing hard coded
+ *    stack buffers with this macro you need to make sure you remove the & from
+ *    the locations where you are taking the address of the buffer.
+ *
+ * Note that the size parameter is the number of array elements to allocate,
+ * not the number of bytes.
+ *
+ * This macro can not be used outside of function scope, or for the creation
+ * of a function scoped static buffer.  It can not be used to create a cache
+ * line aligned global buffer.
+ */
+
+
+#define ALLOC_ALIGN_BUFFER(type, name, size, align)			\
+	char __##name[ROUND(size * sizeof(type), align) + (align - 1)];	\
+									\
+	type *name = (type *) ALIGN((unsigned long int)__##name, align)
+#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size)			\
+	ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
+
+/*
+ * DEFINE_CACHE_ALIGN_BUFFER() is similar to ALLOC_CACHE_ALIGN_BUFFER, but it's
+ * purpose is to allow allocating aligned buffers outside of function scope.
+ * Usage of this macro shall be avoided or used with extreme care!
+ */
+#define DEFINE_ALIGN_BUFFER(type, name, size, align)			\
+	static char __##name[roundup(size * sizeof(type), align)]	\
+			__attribute__((aligned(align)));				\
+									\
+	static type *name = (type *)__##name
+#define DEFINE_CACHE_ALIGN_BUFFER(type, name, size)			\
+	DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
+
+
+#endif	/* __COMMON_H_ */
diff --git a/include/commproc.h b/include/commproc.h
new file mode 100755
index 0000000..7900166
--- /dev/null
+++ b/include/commproc.h
@@ -0,0 +1,1811 @@
+/*
+ * MPC8xx Communication Processor Module.
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file contains structures and information for the communication
+ * processor channels.  Some CPM control and status is available
+ * throught the MPC8xx internal memory map.  See immap.h for details.
+ * This file only contains what I need for the moment, not the total
+ * CPM capabilities.  I (or someone else) will add definitions as they
+ * are needed.  -- Dan
+ *
+ * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
+ * bytes of the DP RAM and relocates the I2C parameter area to the
+ * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
+ * or other use.
+ */
+#ifndef __CPM_8XX__
+#define __CPM_8XX__
+
+#include <linux/config.h>
+#include <asm/8xx_immap.h>
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST		((ushort)0x8000)
+#define CPM_CR_OPCODE		((ushort)0x0f00)
+#define CPM_CR_CHAN		((ushort)0x00f0)
+#define CPM_CR_FLG		((ushort)0x0001)
+
+/* Some commands (there are more...later)
+*/
+#define CPM_CR_INIT_TRX		((ushort)0x0000)
+#define CPM_CR_INIT_RX		((ushort)0x0001)
+#define CPM_CR_INIT_TX		((ushort)0x0002)
+#define CPM_CR_HUNT_MODE	((ushort)0x0003)
+#define CPM_CR_STOP_TX		((ushort)0x0004)
+#define CPM_CR_RESTART_TX	((ushort)0x0006)
+#define CPM_CR_SET_GADDR	((ushort)0x0008)
+
+/* Channel numbers.
+*/
+#define CPM_CR_CH_SCC1		((ushort)0x0000)
+#define CPM_CR_CH_I2C		((ushort)0x0001)    /* I2C and IDMA1 */
+#define CPM_CR_CH_SCC2		((ushort)0x0004)
+#define CPM_CR_CH_SPI		((ushort)0x0005)    /* SPI/IDMA2/Timers */
+#define CPM_CR_CH_SCC3		((ushort)0x0008)
+#define CPM_CR_CH_SMC1		((ushort)0x0009)    /* SMC1 / DSP1 */
+#define CPM_CR_CH_SCC4		((ushort)0x000c)
+#define CPM_CR_CH_SMC2		((ushort)0x000d)    /* SMC2 / DSP2 */
+
+#define mk_cr_cmd(CH, CMD)	((CMD << 8) | (CH << 4))
+
+/*
+ * DPRAM defines and allocation functions
+ */
+
+/* The dual ported RAM is multi-functional.  Some areas can be (and are
+ * being) used for microcode.  There is an area that can only be used
+ * as data ram for buffer descriptors, which is all we use right now.
+ * Currently the first 512 and last 256 bytes are used for microcode.
+ */
+#ifdef  CFG_ALLOC_DPRAM
+
+#define CPM_DATAONLY_BASE	((uint)0x0800)
+#define CPM_DATAONLY_SIZE	((uint)0x0700)
+#define CPM_DP_NOSPACE		((uint)0x7fffffff)
+
+#else
+
+#define CPM_SERIAL_BASE		0x0800
+#define CPM_I2C_BASE		0x0820
+#define CPM_SPI_BASE		0x0840
+#define CPM_FEC_BASE		0x0860
+#define CPM_SERIAL2_BASE	0x08E0
+#define CPM_SCC_BASE		0x0900
+#define CPM_POST_BASE		0x0980
+#define CPM_WLKBD_BASE		0x0a00
+
+#endif
+
+#ifndef CFG_CPM_POST_WORD_ADDR
+#define CPM_POST_WORD_ADDR	0x07FC
+#else
+#define CPM_POST_WORD_ADDR	CFG_CPM_POST_WORD_ADDR
+#endif
+
+#ifndef CFG_CPM_BOOTCOUNT_ADDR
+#define CPM_BOOTCOUNT_ADDR	(CPM_POST_WORD_ADDR - 2*sizeof(ulong))
+#else
+#define CPM_BOOTCOUNT_ADDR	CFG_CPM_BOOTCOUNT_ADDR
+#endif
+
+#define BD_IIC_START	((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+extern	cpm8xx_t	*cpmp;		/* Pointer to comm processor */
+
+/* Buffer descriptors used by many of the CPM protocols.
+*/
+typedef struct cpm_buf_desc {
+	ushort	cbd_sc;		/* Status and Control */
+	ushort	cbd_datlen;	/* Data length in buffer */
+	uint	cbd_bufaddr;	/* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
+#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
+#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
+#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
+#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
+#define BD_SC_TC	((ushort)0x0400)	/* Transmit CRC */
+#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
+#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
+#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
+#define BD_SC_BR	((ushort)0x0020)	/* Break received */
+#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
+#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
+#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
+#define BD_SC_CD	((ushort)0x0001)	/* Carrier Detect lost */
+
+/* Parameter RAM offsets.
+*/
+#define PROFF_SCC1	((uint)0x0000)
+#define PROFF_IIC	((uint)0x0080)
+#define PROFF_SCC2	((uint)0x0100)
+#define PROFF_SPI	((uint)0x0180)
+#define PROFF_SCC3	((uint)0x0200)
+#define PROFF_SMC1	((uint)0x0280)
+#define PROFF_SCC4	((uint)0x0300)
+#define PROFF_SMC2	((uint)0x0380)
+
+/* Define enough so I can at least use the serial port as a UART.
+ * The MBX uses SMC1 as the host serial port.
+ */
+typedef struct smc_uart {
+	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
+	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
+	u_char	smc_rfcr;	/* Rx function code */
+	u_char	smc_tfcr;	/* Tx function code */
+	ushort	smc_mrblr;	/* Max receive buffer length */
+	uint	smc_rstate;	/* Internal */
+	uint	smc_idp;	/* Internal */
+	ushort	smc_rbptr;	/* Internal */
+	ushort	smc_ibc;	/* Internal */
+	uint	smc_rxtmp;	/* Internal */
+	uint	smc_tstate;	/* Internal */
+	uint	smc_tdp;	/* Internal */
+	ushort	smc_tbptr;	/* Internal */
+	ushort	smc_tbc;	/* Internal */
+	uint	smc_txtmp;	/* Internal */
+	ushort	smc_maxidl;	/* Maximum idle characters */
+	ushort	smc_tmpidl;	/* Temporary idle counter */
+	ushort	smc_brklen;	/* Last received break length */
+	ushort	smc_brkec;	/* rcv'd break condition counter */
+	ushort	smc_brkcr;	/* xmt break count register */
+	ushort	smc_rmask;	/* Temporary bit mask */
+} smc_uart_t;
+
+/* Function code bits.
+*/
+#define SMC_EB	((u_char)0x10)	/* Set big endian byte order */
+
+/* SMC uart mode register.
+*/
+#define	SMCMR_REN	((ushort)0x0001)
+#define SMCMR_TEN	((ushort)0x0002)
+#define SMCMR_DM	((ushort)0x000c)
+#define SMCMR_SM_GCI	((ushort)0x0000)
+#define SMCMR_SM_UART	((ushort)0x0020)
+#define SMCMR_SM_TRANS	((ushort)0x0030)
+#define SMCMR_SM_MASK	((ushort)0x0030)
+#define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
+#define SMCMR_REVD	SMCMR_PM_EVEN
+#define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
+#define SMCMR_BS	SMCMR_PEN
+#define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
+#define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
+#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)
+
+/* SMC2 as Centronics parallel printer.  It is half duplex, in that
+ * it can only receive or transmit.  The parameter ram values for
+ * each direction are either unique or properly overlap, so we can
+ * include them in one structure.
+ */
+typedef struct smc_centronics {
+	ushort	scent_rbase;
+	ushort	scent_tbase;
+	u_char	scent_cfcr;
+	u_char	scent_smask;
+	ushort	scent_mrblr;
+	uint	scent_rstate;
+	uint	scent_r_ptr;
+	ushort	scent_rbptr;
+	ushort	scent_r_cnt;
+	uint	scent_rtemp;
+	uint	scent_tstate;
+	uint	scent_t_ptr;
+	ushort	scent_tbptr;
+	ushort	scent_t_cnt;
+	uint	scent_ttemp;
+	ushort	scent_max_sl;
+	ushort	scent_sl_cnt;
+	ushort	scent_character1;
+	ushort	scent_character2;
+	ushort	scent_character3;
+	ushort	scent_character4;
+	ushort	scent_character5;
+	ushort	scent_character6;
+	ushort	scent_character7;
+	ushort	scent_character8;
+	ushort	scent_rccm;
+	ushort	scent_rccr;
+} smc_cent_t;
+
+/* Centronics Status Mask Register.
+*/
+#define SMC_CENT_F	((u_char)0x08)
+#define SMC_CENT_PE	((u_char)0x04)
+#define SMC_CENT_S	((u_char)0x02)
+
+/* SMC Event and Mask register.
+*/
+#define	SMCM_BRKE	((unsigned char)0x40)	/* When in UART Mode */
+#define	SMCM_BRK	((unsigned char)0x10)	/* When in UART Mode */
+#define	SMCM_TXE	((unsigned char)0x10)	/* When in Transparent Mode */
+#define	SMCM_BSY	((unsigned char)0x04)
+#define	SMCM_TX		((unsigned char)0x02)
+#define	SMCM_RX		((unsigned char)0x01)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST		((uint)0x00020000)
+#define CPM_BRG_EN		((uint)0x00010000)
+#define CPM_BRG_EXTC_INT	((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK2	((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK6	((uint)0x00008000)
+#define CPM_BRG_ATB		((uint)0x00002000)
+#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
+#define CPM_BRG_DIV16		((uint)0x00000001)
+
+/* SI Clock Route Register
+*/
+#define SICR_RCLK_SCC1_BRG1	((uint)0x00000000)
+#define SICR_TCLK_SCC1_BRG1	((uint)0x00000000)
+#define SICR_RCLK_SCC2_BRG2	((uint)0x00000800)
+#define SICR_TCLK_SCC2_BRG2	((uint)0x00000100)
+#define SICR_RCLK_SCC3_BRG3	((uint)0x00100000)
+#define SICR_TCLK_SCC3_BRG3	((uint)0x00020000)
+#define SICR_RCLK_SCC4_BRG4	((uint)0x18000000)
+#define SICR_TCLK_SCC4_BRG4	((uint)0x03000000)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP		((uint)0x00040000)
+#define SCC_GSMRH_GDE		((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
+#define SCC_GSMRH_REVD		((uint)0x00002000)
+#define SCC_GSMRH_TRX		((uint)0x00001000)
+#define SCC_GSMRH_TTX		((uint)0x00000800)
+#define SCC_GSMRH_CDP		((uint)0x00000400)
+#define SCC_GSMRH_CTSP		((uint)0x00000200)
+#define SCC_GSMRH_CDS		((uint)0x00000100)
+#define SCC_GSMRH_CTSS		((uint)0x00000080)
+#define SCC_GSMRH_TFL		((uint)0x00000040)
+#define SCC_GSMRH_RFW		((uint)0x00000020)
+#define SCC_GSMRH_TXSY		((uint)0x00000010)
+#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8		((uint)0x00000008)
+#define SCC_GSMRH_SYNL4		((uint)0x00000004)
+#define SCC_GSMRH_RTSM		((uint)0x00000002)
+#define SCC_GSMRH_RSYN		((uint)0x00000001)
+
+#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
+#define SCC_GSMRL_TCI		((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
+#define SCC_GSMRL_RINV		((uint)0x02000000)
+#define SCC_GSMRL_TINV		((uint)0x01000000)
+#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48	((uint)0x00800000)
+#define SCC_GSMRL_TPL_32	((uint)0x00600000)
+#define SCC_GSMRL_TPL_16	((uint)0x00400000)
+#define SCC_GSMRL_TPL_8		((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
+#define SCC_GSMRL_TPP_01	((uint)0x00100000)
+#define SCC_GSMRL_TPP_10	((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
+#define SCC_GSMRL_TEND		((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
+#define SCC_GSMRL_ENR		((uint)0x00000020)
+#define SCC_GSMRL_ENT		((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
+#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
+
+#define SCC_TODR_TOD		((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define	SCCM_TXE	((unsigned char)0x10)
+#define	SCCM_BSY	((unsigned char)0x04)
+#define	SCCM_TX		((unsigned char)0x02)
+#define	SCCM_RX		((unsigned char)0x01)
+
+typedef struct scc_param {
+	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
+	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
+	u_char	scc_rfcr;	/* Rx function code */
+	u_char	scc_tfcr;	/* Tx function code */
+	ushort	scc_mrblr;	/* Max receive buffer length */
+	uint	scc_rstate;	/* Internal */
+	uint	scc_idp;	/* Internal */
+	ushort	scc_rbptr;	/* Internal */
+	ushort	scc_ibc;	/* Internal */
+	uint	scc_rxtmp;	/* Internal */
+	uint	scc_tstate;	/* Internal */
+	uint	scc_tdp;	/* Internal */
+	ushort	scc_tbptr;	/* Internal */
+	ushort	scc_tbc;	/* Internal */
+	uint	scc_txtmp;	/* Internal */
+	uint	scc_rcrc;	/* Internal */
+	uint	scc_tcrc;	/* Internal */
+} sccp_t;
+
+/* Function code bits.
+*/
+#define SCC_EB	((u_char)0x10)	/* Set big endian byte order */
+
+/* CPM Ethernet through SCCx.
+ */
+typedef struct scc_enet {
+	sccp_t	sen_genscc;
+	uint	sen_cpres;	/* Preset CRC */
+	uint	sen_cmask;	/* Constant mask for CRC */
+	uint	sen_crcec;	/* CRC Error counter */
+	uint	sen_alec;	/* alignment error counter */
+	uint	sen_disfc;	/* discard frame counter */
+	ushort	sen_pads;	/* Tx short frame pad character */
+	ushort	sen_retlim;	/* Retry limit threshold */
+	ushort	sen_retcnt;	/* Retry limit counter */
+	ushort	sen_maxflr;	/* maximum frame length register */
+	ushort	sen_minflr;	/* minimum frame length register */
+	ushort	sen_maxd1;	/* maximum DMA1 length */
+	ushort	sen_maxd2;	/* maximum DMA2 length */
+	ushort	sen_maxd;	/* Rx max DMA */
+	ushort	sen_dmacnt;	/* Rx DMA counter */
+	ushort	sen_maxb;	/* Max BD byte count */
+	ushort	sen_gaddr1;	/* Group address filter */
+	ushort	sen_gaddr2;
+	ushort	sen_gaddr3;
+	ushort	sen_gaddr4;
+	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf0rba;	/* Internal */
+	uint	sen_tbuf0crc;	/* Internal */
+	ushort	sen_tbuf0bcnt;	/* Internal */
+	ushort	sen_paddrh;	/* physical address (MSB) */
+	ushort	sen_paddrm;
+	ushort	sen_paddrl;	/* physical address (LSB) */
+	ushort	sen_pper;	/* persistence */
+	ushort	sen_rfbdptr;	/* Rx first BD pointer */
+	ushort	sen_tfbdptr;	/* Tx first BD pointer */
+	ushort	sen_tlbdptr;	/* Tx last BD pointer */
+	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf1rba;	/* Internal */
+	uint	sen_tbuf1crc;	/* Internal */
+	ushort	sen_tbuf1bcnt;	/* Internal */
+	ushort	sen_txlen;	/* Tx Frame length counter */
+	ushort	sen_iaddr1;	/* Individual address filter */
+	ushort	sen_iaddr2;
+	ushort	sen_iaddr3;
+	ushort	sen_iaddr4;
+	ushort	sen_boffcnt;	/* Backoff counter */
+
+	/* NOTE: Some versions of the manual have the following items
+	 * incorrectly documented.  Below is the proper order.
+	 */
+	ushort	sen_taddrh;	/* temp address (MSB) */
+	ushort	sen_taddrm;
+	ushort	sen_taddrl;	/* temp address (LSB) */
+} scc_enet_t;
+
+/**********************************************************************
+ *
+ * Board specific configuration settings.
+ *
+ * Please note that we use the presence of a #define SCC_ENET and/or
+ * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
+ **********************************************************************/
+
+
+/***  ADS  *************************************************************/
+
+#if defined(CONFIG_MPC860) && defined(CONFIG_ADS)
+/* This ENET stuff is for the MPC860ADS with ethernet on SCC1.
+ */
+
+#define	PROFF_ENET	PROFF_SCC1
+#define	CPM_CR_ENET	CPM_CR_CH_SCC1
+#define	SCC_ENET	0
+
+#define PA_ENET_RXD	((ushort)0x0001)
+#define PA_ENET_TXD	((ushort)0x0002)
+#define PA_ENET_TCLK	((ushort)0x0100)
+#define PA_ENET_RCLK	((ushort)0x0200)
+
+#define PB_ENET_TENA	((uint)0x00001000)
+
+#define PC_ENET_CLSN	((ushort)0x0010)
+#define PC_ENET_RENA	((ushort)0x0020)
+
+#define SICR_ENET_MASK	((uint)0x000000ff)
+#define SICR_ENET_CLKRT	((uint)0x0000002c)
+
+/* 68160 PHY control */
+
+#define PC_ENET_ETHLOOP ((ushort)0x0800)
+#define PC_ENET_TPFLDL	((ushort)0x0400)
+#define PC_ENET_TPSQEL  ((ushort)0x0200)
+
+#endif	/* MPC860ADS */
+
+/***  AMX860  **********************************************/
+
+#if defined(CONFIG_AMX860)
+
+/* This ENET stuff is for the AMX860 with ethernet on SCC1.
+ */
+
+#define PROFF_ENET	PROFF_SCC1
+#define CPM_CR_ENET	CPM_CR_CH_SCC1
+#define SCC_ENET	0
+
+#define PA_ENET_RXD	((ushort)0x0001)
+#define PA_ENET_TXD	((ushort)0x0002)
+#define PA_ENET_TCLK	((ushort)0x0400)
+#define PA_ENET_RCLK	((ushort)0x0800)
+
+#define PB_ENET_TENA	((uint)0x00001000)
+
+#define PC_ENET_CLSN	((ushort)0x0010)
+#define PC_ENET_RENA	((ushort)0x0020)
+
+#define SICR_ENET_MASK	((uint)0x000000ff)
+#define SICR_ENET_CLKRT	((uint)0x0000003e)
+
+/* 68160 PHY control */
+
+#define PB_ENET_ETHLOOP	((uint)0x00020000)
+#define PB_ENET_TPFLDL	((uint)0x00010000)
+#define PB_ENET_TPSQEL	((uint)0x00008000)
+#define PD_ENET_ETH_EN	((ushort)0x0004)
+
+#endif	/* CONFIG_AMX860 */
+
+/***  BSEIP  **********************************************************/
+
+#ifdef CONFIG_BSEIP
+/* This ENET stuff is for the MPC823 with ethernet on SCC2.
+ * This is unique to the BSE ip-Engine board.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)
+#define PA_ENET_TXD	((ushort)0x0008)
+#define PA_ENET_TCLK	((ushort)0x0100)
+#define PA_ENET_RCLK	((ushort)0x0200)
+#define PB_ENET_TENA	((uint)0x00002000)
+#define PC_ENET_CLSN	((ushort)0x0040)
+#define PC_ENET_RENA	((ushort)0x0080)
+
+/* BSE uses port B and C bits for PHY control also.
+*/
+#define PB_BSE_POWERUP	((uint)0x00000004)
+#define PB_BSE_FDXDIS	((uint)0x00008000)
+#define PC_BSE_LOOPBACK	((ushort)0x0800)
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002c00)
+#endif	/* CONFIG_BSEIP */
+
+/***  BSEIP  **********************************************************/
+
+#ifdef CONFIG_FLAGADM
+/* Enet configuration for the FLAGADM */
+/* Enet on SCC2 */
+
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)
+#define PA_ENET_TXD	((ushort)0x0008)
+#define PA_ENET_TCLK	((ushort)0x0100)
+#define PA_ENET_RCLK	((ushort)0x0400)
+#define PB_ENET_TENA	((uint)0x00002000)
+#define PC_ENET_CLSN	((ushort)0x0040)
+#define PC_ENET_RENA	((ushort)0x0080)
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00003400)
+#endif	/* CONFIG_FLAGADM */
+
+/***  C2MON  **********************************************************/
+
+#ifdef CONFIG_C2MON
+
+# ifndef CONFIG_FEC_ENET	/* use SCC for 10Mbps Ethernet	*/
+#  error "Ethernet on SCC not supported on C2MON Board!"
+# else				/* Use FEC for Fast Ethernet */
+
+#undef	SCC_ENET
+#define FEC_ENET
+
+#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
+#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
+#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
+#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
+#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
+#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
+#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
+#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
+#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
+#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
+#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
+#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
+#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
+
+#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
+
+# endif	/* CONFIG_FEC_ENET */
+#endif	/* CONFIG_C2MON */
+
+/*********************************************************************/
+
+
+/***  CCM  and  PCU E  ***********************************************/
+
+/* The PCU E  and  CCM  use the FEC on a MPC860T for Ethernet */
+
+#if defined (CONFIG_PCU_E) || defined(CONFIG_CCM)
+
+#define	FEC_ENET	/* use FEC for EThernet */
+#undef	SCC_ENET
+
+#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
+#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
+#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
+#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
+#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
+#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
+#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
+#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
+#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
+#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
+#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
+#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
+#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
+
+#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
+
+#endif	/* CONFIG_PCU_E, CONFIG_CCM */
+
+/***  ELPT860 *********************************************************/
+
+#ifdef CONFIG_ELPT860
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.
+ */
+#  define PROFF_ENET        PROFF_SCC1
+#  define CPM_CR_ENET       CPM_CR_CH_SCC1
+#  define SCC_ENET          0
+
+#  define PA_ENET_RXD       ((ushort)0x0001)	/* PA 15 */
+#  define PA_ENET_TXD       ((ushort)0x0002)	/* PA 14 */
+#  define PA_ENET_RCLK      ((ushort)0x0100)	/* PA  7 */
+#  define PA_ENET_TCLK      ((ushort)0x0200)	/* PA  6 */
+
+#  define PC_ENET_TENA      ((ushort)0x0001)	/* PC 15 */
+#  define PC_ENET_CLSN      ((ushort)0x0010)	/* PC 11 */
+#  define PC_ENET_RENA      ((ushort)0x0020)	/* PC 10 */
+
+/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
+ * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+#  define SICR_ENET_MASK    ((uint)0x000000FF)
+#  define SICR_ENET_CLKRT   ((uint)0x00000025)
+#endif	/* CONFIG_ELPT860 */
+
+/***  ESTEEM 192E  **************************************************/
+#ifdef CONFIG_ESTEEM192E
+/* ESTEEM192E
+ * This ENET stuff is for the MPC850 with ethernet on SCC2. This
+ * is very similar to the RPX-Lite configuration.
+ * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
+ */
+
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+
+#define PA_ENET_RXD	((ushort)0x0004)
+#define PA_ENET_TXD	((ushort)0x0008)
+#define PA_ENET_TCLK	((ushort)0x0200)
+#define PA_ENET_RCLK	((ushort)0x0800)
+#define PB_ENET_TENA	((uint)0x00002000)
+#define PC_ENET_CLSN	((ushort)0x0040)
+#define PC_ENET_RENA	((ushort)0x0080)
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00003d00)
+
+#define PB_ENET_LOOPBACK ((uint)0x00004000)
+#define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
+
+#endif
+
+/***  FADS823  ********************************************************/
+
+#if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS)
+/* This ENET stuff is for the MPC823FADS with ethernet on SCC2.
+ */
+#ifdef CONFIG_SCC2_ENET
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define CPMVEC_ENET	CPMVEC_SCC2
+#endif
+
+#ifdef CONFIG_SCC1_ENET
+#define	PROFF_ENET	PROFF_SCC1
+#define	CPM_CR_ENET	CPM_CR_CH_SCC1
+#define	SCC_ENET	0
+#define CPMVEC_ENET	CPMVEC_SCC1
+#endif
+
+#define PA_ENET_RXD	((ushort)0x0004)
+#define PA_ENET_TXD	((ushort)0x0008)
+#define PA_ENET_TCLK	((ushort)0x0400)
+#define PA_ENET_RCLK	((ushort)0x0200)
+
+#define PB_ENET_TENA	((uint)0x00002000)
+
+#define PC_ENET_CLSN	((ushort)0x0040)
+#define PC_ENET_RENA	((ushort)0x0080)
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002e00)
+
+#endif	/* CONFIG_FADS823FADS */
+
+/***  FADS850SAR  ********************************************************/
+
+#if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS)
+/* This ENET stuff is for the MPC850SAR with ethernet on SCC2.  Some of
+ * this may be unique to the FADS850SAR configuration.
+ * Note TENA is on Port B.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0200)	/* PA 6 */
+#define PA_ENET_TCLK	((ushort)0x0800)	/* PA 4 */
+#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC 9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC 8 */
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002f00)	/* RCLK-CLK2, TCLK-CLK4 */
+#endif	/* CONFIG_FADS850SAR */
+
+/***  FADS860T********************************************************/
+
+#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x)
+/*
+ * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1.
+ */
+#ifdef CONFIG_SCC1_ENET
+
+#define	SCC_ENET	0
+
+#define	PROFF_ENET	PROFF_SCC1
+#define	CPM_CR_ENET	CPM_CR_CH_SCC1
+
+#define PA_ENET_RXD	((ushort)0x0001)
+#define PA_ENET_TXD	((ushort)0x0002)
+#define PA_ENET_TCLK	((ushort)0x0100)
+#define PA_ENET_RCLK	((ushort)0x0200)
+
+#define PB_ENET_TENA	((uint)0x00001000)
+
+#define PC_ENET_CLSN	((ushort)0x0010)
+#define PC_ENET_RENA	((ushort)0x0020)
+
+#define SICR_ENET_MASK	((uint)0x000000ff)
+#define SICR_ENET_CLKRT	((uint)0x0000002c)
+
+#endif	/* CONFIG_SCC1_ETHERNET */
+
+/*
+ * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
+ * with ethernet on FEC.
+ */
+
+#ifdef CONFIG_FEC_ENET
+#define	FEC_ENET	/* Use FEC for Ethernet */
+#endif	/* CONFIG_FEC_ENET */
+
+#endif	/* CONFIG_FADS && CONFIG_MPC86x */
+
+/***  FPS850L, FPS860L  ************************************************/
+
+#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PC_ENET_TENA	((ushort)0x0002)	/* PC 14 */
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
+
+/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
+ * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002600)
+#endif	/* CONFIG_FPS850L, CONFIG_FPS860L */
+
+/*** GEN860T **********************************************************/
+#if defined(CONFIG_GEN860T)
+#undef	SCC_ENET
+#define	FEC_ENET
+
+#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 	*/
+#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 	*/
+#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 	*/
+#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 	*/
+#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 	*/
+#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 	*/
+#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 	*/
+#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 	*/
+#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 	*/
+#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 	*/
+#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 	*/
+#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 	*/
+#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 	*/
+#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3-15	*/
+#endif	/* CONFIG_GEN860T */
+
+/***  GENIETV  ********************************************************/
+
+#if defined(CONFIG_GENIETV)
+/* Ethernet is only on SCC2 */
+
+#define CONFIG_SCC2_ENET
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define CPMVEC_ENET	CPMVEC_SCC2
+
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
+
+#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
+
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002e00)
+
+#endif	/* CONFIG_GENIETV */
+
+/*** GTH ******************************************************/
+
+#ifdef CONFIG_GTH
+#ifdef CONFIG_FEC_ENET
+#define	FEC_ENET	/* use FEC for EThernet */
+#endif	/* CONFIG_FEC_ETHERNET */
+
+/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
+#define	PROFF_ENET	PROFF_SCC1
+#define	CPM_CR_ENET	CPM_CR_CH_SCC1
+#define	SCC_ENET	0
+
+#define PA_ENET_RXD	((ushort)0x0001) /* PA15 */
+#define PA_ENET_TXD	((ushort)0x0002) /* PA14 */
+#define PA_ENET_TCLK	((ushort)0x0800) /* PA4 */
+#define PA_ENET_RCLK	((ushort)0x0400) /* PA5 */
+
+#define PB_ENET_TENA	((uint)0x00001000) /* PB19 */
+
+#define PC_ENET_CLSN	((ushort)0x0010) /* PC11 */
+#define PC_ENET_RENA	((ushort)0x0020) /* PC10 */
+
+/* NOTE. This is reset for 10Mbit port only */
+#define PC_ENET_RESET	((ushort)0x0100)	/* PC 7 */
+
+#define SICR_ENET_MASK	((uint)0x000000ff)
+
+/* TCLK PA4 -->CLK4, RCLK PA5 -->CLK3 */
+#define SICR_ENET_CLKRT	((uint)0x00000037)
+
+#endif	/* CONFIG_GTH */
+
+/*** HERMES-PRO ******************************************************/
+
+/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
+
+#ifdef CONFIG_HERMES
+
+#define	FEC_ENET	/* use FEC for EThernet */
+#undef	SCC_ENET
+
+
+#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
+#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
+#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
+#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
+#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
+#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
+#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
+#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
+#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
+#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
+#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
+#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
+#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
+
+#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
+
+#endif	/* CONFIG_HERMES */
+
+/***  IAD210  **********************************************************/
+
+/* The IAD210 uses the FEC on a MPC860P for Ethernet */
+
+#if defined(CONFIG_IAD210)
+
+# define  FEC_ENET    /* use FEC for Ethernet */
+# undef   SCC_ENET
+
+# define PD_MII_TXD1    ((ushort) 0x1000 )	/* PD  3 */
+# define PD_MII_TXD2    ((ushort) 0x0800 )	/* PD  4 */
+# define PD_MII_TXD3    ((ushort) 0x0400 )	/* PD  5 */
+# define PD_MII_RX_DV   ((ushort) 0x0200 )	/* PD  6 */
+# define PD_MII_RX_ERR  ((ushort) 0x0100 )	/* PD  7 */
+# define PD_MII_RX_CLK  ((ushort) 0x0080 )	/* PD  8 */
+# define PD_MII_TXD0    ((ushort) 0x0040 )	/* PD  9 */
+# define PD_MII_RXD0    ((ushort) 0x0020 )	/* PD 10 */
+# define PD_MII_TX_ERR  ((ushort) 0x0010 )	/* PD 11 */
+# define PD_MII_MDC     ((ushort) 0x0008 )	/* PD 12 */
+# define PD_MII_RXD1    ((ushort) 0x0004 )	/* PD 13 */
+# define PD_MII_RXD2    ((ushort) 0x0002 )	/* PD 14 */
+# define PD_MII_RXD3    ((ushort) 0x0001 )	/* PD 15 */
+
+# define PD_MII_MASK    ((ushort) 0x1FFF )   /* PD 3...15 */
+
+#endif	/* CONFIG_IAD210 */
+
+/*** ICU862  **********************************************************/
+
+#if defined(CONFIG_ICU862)
+
+#ifdef CONFIG_FEC_ENET
+#define FEC_ENET	/* use FEC for EThernet */
+#endif  /* CONFIG_FEC_ETHERNET */
+
+#endif /* CONFIG_ICU862 */
+
+/***  IP860  **********************************************************/
+
+#if defined(CONFIG_IP860)
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.
+ */
+#define	PROFF_ENET	PROFF_SCC1
+#define	CPM_CR_ENET	CPM_CR_CH_SCC1
+#define	SCC_ENET	0
+#define PA_ENET_RXD	((ushort)0x0001)	/* PA 15 */
+#define PA_ENET_TXD	((ushort)0x0002)	/* PA 14 */
+#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
+#define PA_ENET_TCLK	((ushort)0x0100)	/* PA  7 */
+
+#define PC_ENET_TENA	((ushort)0x0001)	/* PC 15 */
+#define PC_ENET_CLSN	((ushort)0x0010)	/* PC 11 */
+#define PC_ENET_RENA	((ushort)0x0020)	/* PC 10 */
+
+#define PB_ENET_RESET	(uint)0x00000008	/* PB 28 */
+#define PB_ENET_JABD	(uint)0x00000004	/* PB 29 */
+
+/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
+ * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x000000ff)
+#define SICR_ENET_CLKRT	((uint)0x0000002C)
+#endif	/* CONFIG_IP860 */
+
+/*** IVMS8  **********************************************************/
+
+/* The IVMS8 uses the FEC on a MPC860T for Ethernet */
+
+#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
+
+#define	FEC_ENET	/* use FEC for EThernet */
+#undef	SCC_ENET
+
+#define	PB_ENET_POWER	((uint)0x00010000)	/* PB 15 */
+
+#define PC_ENET_RESET	((ushort)0x0010)	/* PC 11 */
+
+#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
+#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
+#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
+#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
+#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
+#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
+#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
+#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
+#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
+#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
+#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
+#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
+#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
+
+#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
+
+#endif	/* CONFIG_IVMS8, CONFIG_IVML24 */
+
+/***  KUP4K, KUP4X ****************************************************/
+/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */
+
+#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
+
+#define	FEC_ENET	/* use FEC for EThernet */
+#undef	SCC_ENET
+
+#define	PB_ENET_POWER	((uint)0x00010000)	/* PB 15 */
+
+#define PC_ENET_RESET	((ushort)0x0010)	/* PC 11 */
+
+#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
+#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
+#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
+#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
+#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
+#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
+#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
+#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
+#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
+#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
+#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
+#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
+#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
+
+#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
+
+#endif	/* CONFIG_KUP4K */
+
+
+/***  LANTEC  *********************************************************/
+
+#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
+
+#define PC_ENET_LBK	((ushort)0x0010)	/* PC 11 */
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
+ * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x0000FF00)
+#define SICR_ENET_CLKRT	((uint)0x00002E00)
+#endif	/* CONFIG_LANTEC v2 */
+
+/***  LWMON  **********************************************************/
+
+#if defined(CONFIG_LWMON)
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0800)	/* PA  4 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
+
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
+ * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00003E00)
+#endif	/* CONFIG_LWMON */
+
+/***  NX823  ***********************************************/
+
+#if defined(CONFIG_NX823)
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.
+ */
+#define PROFF_ENET	PROFF_SCC2
+#define CPM_CR_ENET	CPM_CR_CH_SCC2
+#define SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)  /* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)  /* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0200)  /* PA  6 */
+#define PA_ENET_TCLK	((ushort)0x0800)  /* PA  4 */
+
+#define PB_ENET_TENA	((uint)0x00002000)   /* PB 18 */
+
+#define PC_ENET_CLSN	((ushort)0x0040)  /* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)  /* PC  8 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002f00)
+
+#endif   /* CONFIG_NX823 */
+
+/***  MBX  ************************************************************/
+
+#ifdef CONFIG_MBX
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.  The TCLK and RCLK seem unique
+ * to the MBX860 board.  Any two of the four available clocks could be
+ * used, and the MPC860 cookbook manual has an example using different
+ * clock pins.
+ */
+#define	PROFF_ENET	PROFF_SCC1
+#define	CPM_CR_ENET	CPM_CR_CH_SCC1
+#define	SCC_ENET	0
+#define PA_ENET_RXD	((ushort)0x0001)
+#define PA_ENET_TXD	((ushort)0x0002)
+#define PA_ENET_TCLK	((ushort)0x0200)
+#define PA_ENET_RCLK	((ushort)0x0800)
+#define PC_ENET_TENA	((ushort)0x0001)
+#define PC_ENET_CLSN	((ushort)0x0010)
+#define PC_ENET_RENA	((ushort)0x0020)
+
+/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
+ * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x000000ff)
+#define SICR_ENET_CLKRT	((uint)0x0000003d)
+#endif	/* CONFIG_MBX */
+
+/***  MHPC  ********************************************************/
+
+#if defined(CONFIG_MHPC)
+/* This ENET stuff is for the MHPC with ethernet on SCC2.
+ * Note TENA is on Port B.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0200)	/* PA 6 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA 5 */
+#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC 9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC 8 */
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002e00)	/* RCLK-CLK2, TCLK-CLK3 */
+#endif	/* CONFIG_MHPC */
+
+/***  NETVIA  *******************************************************/
+
+/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
+#if ( defined CONFIG_SVM_SC8xx )
+# ifndef CONFIG_FEC_ENET
+
+#define PROFF_ENET      PROFF_SCC2
+#define CPM_CR_ENET     CPM_CR_CH_SCC2
+#define SCC_ENET        1
+
+	/* Bits in parallel I/O port registers that have to be set/cleared
+	 *  *  *  * to configure the pins for SCC2 use.
+	 *   *   *   */
+#define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
+#define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
+#define PA_ENET_RCLK    ((ushort)0x0400)        /* PA  5 */
+#define PA_ENET_TCLK    ((ushort)0x0800)        /* PA  4 */
+
+#define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
+
+#define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
+#define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ *  *  *  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ *   *   *   */
+#define SICR_ENET_MASK  ((uint)0x0000ff00)
+#define SICR_ENET_CLKRT ((uint)0x00003700)
+
+# else                          /* Use FEC for Fast Ethernet */
+
+#undef  SCC_ENET
+#define FEC_ENET
+
+#define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
+#define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
+#define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
+#define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
+#define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
+#define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
+#define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
+#define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
+#define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
+#define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
+#define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
+#define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
+#define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
+
+#define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
+
+# endif /* CONFIG_FEC_ENET */
+#endif  /* CONFIG_SVM_SC8xx */
+
+
+#if defined(CONFIG_NETVIA)
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
+#define PA_ENET_TCLK	((ushort)0x0800)	/* PA  4 */
+
+#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
+# define PB_ENET_PDN	((ushort)0x4000)	/* PB 17 */
+#elif CONFIG_NETVIA_VERSION >= 2
+# define PC_ENET_PDN	((ushort)0x0008)	/* PC 12 */
+#endif
+
+#define PB_ENET_TENA	((ushort)0x2000)	/* PB 18 */
+
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002f00)
+
+#endif	/* CONFIG_NETVIA */
+
+/***  QS850/QS823  ***************************************************/
+
+#if defined(CONFIG_QS850) || defined(CONFIG_QS823)
+#undef FEC_ENET /* Don't use FEC for EThernet */
+
+#define PROFF_ENET		PROFF_SCC2
+#define CPM_CR_ENET		CPM_CR_CH_SCC2
+#define SCC_ENET		1
+
+#define PA_ENET_RXD		((ushort)0x0004)  /* RXD on PA13 (Pin D9) */
+#define PA_ENET_TXD		((ushort)0x0008)  /* TXD on PA12 (Pin D7) */
+#define PC_ENET_RENA		((ushort)0x0080)  /* RENA on PC8 (Pin D12) */
+#define PC_ENET_CLSN		((ushort)0x0040)  /* CLSN on PC9 (Pin C12) */
+#define PA_ENET_TCLK		((ushort)0x0200)  /* TCLK on PA6 (Pin D8) */
+#define PA_ENET_RCLK		((ushort)0x0800)  /* RCLK on PA4 (Pin D10) */
+#define PB_ENET_TENA		((uint)0x00002000)  /* TENA on PB18 (Pin D11) */
+#define PC_ENET_LBK		((ushort)0x0010)  /* Loopback control on PC11 (Pin B14) */
+#define PC_ENET_LI		((ushort)0x0020)  /* Link Integrity control PC10 (A15) */
+#define PC_ENET_SQE		((ushort)0x0100)  /* SQE Disable control PC7 (B15) */
+
+/* SCC2 TXCLK from CLK2
+ * SCC2 RXCLK from CLK4
+ * SCC2 Connected to NMSI */
+#define SICR_ENET_MASK		((uint)0x00007F00)
+#define SICR_ENET_CLKRT		((uint)0x00003D00)
+
+#endif /* CONFIG_QS850/QS823 */
+
+/***  QS860T  ***************************************************/
+
+#ifdef CONFIG_QS860T
+#ifdef CONFIG_FEC_ENET
+#define FEC_ENET /* use FEC for EThernet */
+#endif /* CONFIG_FEC_ETHERNET */
+
+/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
+#define PROFF_ENET		PROFF_SCC1
+#define CPM_CR_ENET		CPM_CR_CH_SCC1
+#define SCC_ENET		0
+
+#define PA_ENET_RXD		((ushort)0x0001) /* PA15 */
+#define PA_ENET_TXD		((ushort)0x0002) /* PA14 */
+#define PA_ENET_TCLK		((ushort)0x0800) /* PA4 */
+#define PA_ENET_RCLK		((ushort)0x0200) /* PA6 */
+#define PB_ENET_TENA		((uint)0x00001000) /* PB19 */
+#define PC_ENET_CLSN		((ushort)0x0010) /* PC11 */
+#define PC_ENET_RENA		((ushort)0x0020) /* PC10 */
+
+#define SICR_ENET_MASK		((uint)0x000000ff)
+/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */
+#define SICR_ENET_CLKRT		((uint)0x0000003D)
+
+#endif /* CONFIG_QS860T */
+
+/***  RPXCLASSIC  *****************************************************/
+
+#ifdef CONFIG_RPXCLASSIC
+
+#ifdef CONFIG_FEC_ENET
+
+# define FEC_ENET				/* use FEC for EThernet */
+# undef SCC_ENET
+
+#else	/* ! CONFIG_FEC_ENET */
+
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.
+ */
+#define	PROFF_ENET	PROFF_SCC1
+#define	CPM_CR_ENET	CPM_CR_CH_SCC1
+#define	SCC_ENET	0
+#define PA_ENET_RXD	((ushort)0x0001)
+#define PA_ENET_TXD	((ushort)0x0002)
+#define PA_ENET_TCLK	((ushort)0x0200)
+#define PA_ENET_RCLK	((ushort)0x0800)
+#define PB_ENET_TENA	((uint)0x00001000)
+#define PC_ENET_CLSN	((ushort)0x0010)
+#define PC_ENET_RENA	((ushort)0x0020)
+
+/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
+ * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x000000ff)
+#define SICR_ENET_CLKRT	((uint)0x0000003d)
+
+#endif	/* CONFIG_FEC_ENET */
+
+#endif	/* CONFIG_RPXCLASSIC */
+
+/***  RPXLITE  ********************************************************/
+
+#ifdef CONFIG_RPXLITE
+/* This ENET stuff is for the MPC850 with ethernet on SCC2.  Some of
+ * this may be unique to the RPX-Lite configuration.
+ * Note TENA is on Port B.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)
+#define PA_ENET_TXD	((ushort)0x0008)
+#define PA_ENET_TCLK	((ushort)0x0200)
+#define PA_ENET_RCLK	((ushort)0x0800)
+#if defined(CONFIG_RMU)
+#define PC_ENET_TENA	((uint)0x00000002)	/* PC14 */
+#else
+#define PB_ENET_TENA	((uint)0x00002000)
+#endif
+#define PC_ENET_CLSN	((ushort)0x0040)
+#define PC_ENET_RENA	((ushort)0x0080)
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00003d00)
+#endif	/* CONFIG_RPXLITE */
+
+/***  SM850  *********************************************************/
+
+/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
+
+#ifdef CONFIG_SM850
+#define PROFF_ENET	PROFF_SCC3		/* Ethernet on SCC3 */
+#define CPM_CR_ENET	CPM_CR_CH_SCC3
+#define SCC_ENET	2
+#define PB_ENET_RXD	((uint)0x00000004)	/* PB 29 */
+#define PB_ENET_TXD	((uint)0x00000002)	/* PB 30 */
+#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PC_ENET_LBK	((ushort)0x0008)	/* PC 12 */
+#define PC_ENET_TENA	((ushort)0x0004)	/* PC 13 */
+
+#define PC_ENET_RENA	((ushort)0x0800)	/* PC  4 */
+#define PC_ENET_CLSN	((ushort)0x0400)	/* PC  5 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC3.  Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x00FF0000)
+#define SICR_ENET_CLKRT	((uint)0x00260000)
+#endif	/* CONFIG_SM850 */
+
+/***  SPD823TS  ******************************************************/
+
+#ifdef CONFIG_SPD823TS
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define	PROFF_ENET	PROFF_SCC2		/* Ethernet on SCC2 */
+#define CPM_CR_ENET     CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_MDC	((ushort)0x0001)	/* PA 15 !!! */
+#define PA_ENET_MDIO	((ushort)0x0002)	/* PA 14 !!! */
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
+
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
+#define	PC_ENET_RESET	((ushort)0x0100)	/* PC  7 !!! */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
+ * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002E00)
+#endif	/* CONFIG_SPD823TS */
+
+/***  SXNI855T  ******************************************************/
+
+#if defined(CONFIG_SXNI855T)
+
+#ifdef CONFIG_FEC_ENET
+#define	FEC_ENET	/* use FEC for Ethernet */
+#endif	/* CONFIG_FEC_ETHERNET */
+
+#endif	/* CONFIG_SXNI855T */
+
+/***  MVS1, TQM823L/M, TQM850L/M, ETX094, R360MPI  *******************/
+
+#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
+    defined(CONFIG_R360MPI) || defined(CONFIG_RBC823)  || \
+    defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
+    defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
+    defined(CONFIG_ETX094)  || defined(CONFIG_RRVISION)|| \
+   (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
+
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
+#if defined(CONFIG_R360MPI)
+#define PC_ENET_LBK	((ushort)0x0008)	/* PC 12 */
+#endif   /* CONFIG_R360MPI */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002600)
+#endif	/* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
+
+/***  TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M  *********************/
+
+#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
+    defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
+    defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
+    defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
+
+# ifdef CONFIG_SCC1_ENET	/* use SCC for 10Mbps Ethernet	*/
+
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.
+ */
+#define	PROFF_ENET	PROFF_SCC1
+#define	CPM_CR_ENET	CPM_CR_CH_SCC1
+#define	SCC_ENET	0
+#define PA_ENET_RXD	((ushort)0x0001)	/* PA 15 */
+#define PA_ENET_TXD	((ushort)0x0002)	/* PA 14 */
+#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PC_ENET_TENA	((ushort)0x0001)	/* PC 15 */
+#define PC_ENET_CLSN	((ushort)0x0010)	/* PC 11 */
+#define PC_ENET_RENA	((ushort)0x0020)	/* PC 10 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x000000ff)
+#define SICR_ENET_CLKRT	((uint)0x00000026)
+
+# endif	/* CONFIG_SCC1_ENET */
+
+# ifdef CONFIG_FEC_ENET		/* Use FEC for Fast Ethernet */
+
+#define FEC_ENET
+
+#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
+#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
+#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
+#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
+#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
+#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
+#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
+#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
+#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
+#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
+#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
+#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
+#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
+
+#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
+
+# endif	/* CONFIG_FEC_ENET */
+#endif	/* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
+
+/***  V37  **********************************************************/
+
+#ifdef CONFIG_V37
+/* This ENET stuff is for the MPC823 with ethernet on SCC2.  Some of
+ * this may be unique to the Marel V37 configuration.
+ * Note TENA is on Port B.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)
+#define PA_ENET_TXD	((ushort)0x0008)
+#define PA_ENET_TCLK	((ushort)0x0400)
+#define PA_ENET_RCLK	((ushort)0x0200)
+#define PB_ENET_TENA	((uint)0x00002000)
+#define PC_ENET_CLSN	((ushort)0x0040)
+#define PC_ENET_RENA	((ushort)0x0080)
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002e00)
+#endif	/* CONFIG_V37 */
+
+
+/*********************************************************************/
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
+#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
+#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
+#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
+#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
+#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
+
+/* SCC Mode Register (PSMR) as used by Ethernet.
+*/
+#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
+#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
+#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
+#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
+#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
+#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
+#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
+#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
+#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
+#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
+#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
+#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
+#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+*/
+#define BD_ENET_RX_EMPTY	((ushort)0x8000)
+#define BD_ENET_RX_WRAP		((ushort)0x2000)
+#define BD_ENET_RX_INTR		((ushort)0x1000)
+#define BD_ENET_RX_LAST		((ushort)0x0800)
+#define BD_ENET_RX_FIRST	((ushort)0x0400)
+#define BD_ENET_RX_MISS		((ushort)0x0100)
+#define BD_ENET_RX_LG		((ushort)0x0020)
+#define BD_ENET_RX_NO		((ushort)0x0010)
+#define BD_ENET_RX_SH		((ushort)0x0008)
+#define BD_ENET_RX_CR		((ushort)0x0004)
+#define BD_ENET_RX_OV		((ushort)0x0002)
+#define BD_ENET_RX_CL		((ushort)0x0001)
+#define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+*/
+#define BD_ENET_TX_READY	((ushort)0x8000)
+#define BD_ENET_TX_PAD		((ushort)0x4000)
+#define BD_ENET_TX_WRAP		((ushort)0x2000)
+#define BD_ENET_TX_INTR		((ushort)0x1000)
+#define BD_ENET_TX_LAST		((ushort)0x0800)
+#define BD_ENET_TX_TC		((ushort)0x0400)
+#define BD_ENET_TX_DEF		((ushort)0x0200)
+#define BD_ENET_TX_HB		((ushort)0x0100)
+#define BD_ENET_TX_LC		((ushort)0x0080)
+#define BD_ENET_TX_RL		((ushort)0x0040)
+#define BD_ENET_TX_RCMASK	((ushort)0x003c)
+#define BD_ENET_TX_UN		((ushort)0x0002)
+#define BD_ENET_TX_CSL		((ushort)0x0001)
+#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+	sccp_t	scc_genscc;
+	uint	scc_res1;	/* Reserved */
+	uint	scc_res2;	/* Reserved */
+	ushort	scc_maxidl;	/* Maximum idle chars */
+	ushort	scc_idlc;	/* temp idle counter */
+	ushort	scc_brkcr;	/* Break count register */
+	ushort	scc_parec;	/* receive parity error counter */
+	ushort	scc_frmec;	/* receive framing error counter */
+	ushort	scc_nosec;	/* receive noise counter */
+	ushort	scc_brkec;	/* receive break condition counter */
+	ushort	scc_brkln;	/* last received break length */
+	ushort	scc_uaddr1;	/* UART address character 1 */
+	ushort	scc_uaddr2;	/* UART address character 2 */
+	ushort	scc_rtemp;	/* Temp storage */
+	ushort	scc_toseq;	/* Transmit out of sequence char */
+	ushort	scc_char1;	/* control character 1 */
+	ushort	scc_char2;	/* control character 2 */
+	ushort	scc_char3;	/* control character 3 */
+	ushort	scc_char4;	/* control character 4 */
+	ushort	scc_char5;	/* control character 5 */
+	ushort	scc_char6;	/* control character 6 */
+	ushort	scc_char7;	/* control character 7 */
+	ushort	scc_char8;	/* control character 8 */
+	ushort	scc_rccm;	/* receive control character mask */
+	ushort	scc_rccr;	/* receive control character register */
+	ushort	scc_rlbc;	/* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR		((ushort)0x1000)
+#define UART_SCCM_GLT		((ushort)0x0800)
+#define UART_SCCM_AB		((ushort)0x0200)
+#define UART_SCCM_IDL		((ushort)0x0100)
+#define UART_SCCM_GRA		((ushort)0x0080)
+#define UART_SCCM_BRKE		((ushort)0x0040)
+#define UART_SCCM_BRKS		((ushort)0x0020)
+#define UART_SCCM_CCR		((ushort)0x0008)
+#define UART_SCCM_BSY		((ushort)0x0004)
+#define UART_SCCM_TX		((ushort)0x0002)
+#define UART_SCCM_RX		((ushort)0x0001)
+
+/* The SCC PSMR when used as a UART.
+*/
+#define SCU_PSMR_FLC		((ushort)0x8000)
+#define SCU_PSMR_SL		((ushort)0x4000)
+#define SCU_PSMR_CL		((ushort)0x3000)
+#define SCU_PSMR_UM		((ushort)0x0c00)
+#define SCU_PSMR_FRZ		((ushort)0x0200)
+#define SCU_PSMR_RZS		((ushort)0x0100)
+#define SCU_PSMR_SYN		((ushort)0x0080)
+#define SCU_PSMR_DRT		((ushort)0x0040)
+#define SCU_PSMR_PEN		((ushort)0x0010)
+#define SCU_PSMR_RPM		((ushort)0x000c)
+#define SCU_PSMR_REVP		((ushort)0x0008)
+#define SCU_PSMR_TPM		((ushort)0x0003)
+#define SCU_PSMR_TEVP		((ushort)0x0003)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+	sccp_t	st_genscc;
+	uint	st_cpres;	/* Preset CRC */
+	uint	st_cmask;	/* Constant mask for CRC */
+} scc_trans_t;
+
+#define BD_SCC_TX_LAST		((ushort)0x0800)
+
+/* IIC parameter RAM.
+*/
+typedef struct iic {
+	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
+	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
+	u_char	iic_rfcr;	/* Rx function code */
+	u_char	iic_tfcr;	/* Tx function code */
+	ushort	iic_mrblr;	/* Max receive buffer length */
+	uint	iic_rstate;	/* Internal */
+	uint	iic_rdp;	/* Internal */
+	ushort	iic_rbptr;	/* Internal */
+	ushort	iic_rbc;	/* Internal */
+	uint	iic_rxtmp;	/* Internal */
+	uint	iic_tstate;	/* Internal */
+	uint	iic_tdp;	/* Internal */
+	ushort	iic_tbptr;	/* Internal */
+	ushort	iic_tbc;	/* Internal */
+	uint	iic_txtmp;	/* Internal */
+	uint	iic_res;	/* reserved */
+	ushort	iic_rpbase;	/* Relocation pointer */
+	ushort	iic_res2;	/* reserved */
+} iic_t;
+
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
+	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
+	u_char	spi_rfcr;	/* Rx function code */
+	u_char	spi_tfcr;	/* Tx function code */
+	ushort	spi_mrblr;	/* Max receive buffer length */
+	uint	spi_rstate;	/* Internal */
+	uint	spi_rdp;	/* Internal */
+	ushort	spi_rbptr;	/* Internal */
+	ushort	spi_rbc;	/* Internal */
+	uint	spi_rxtmp;	/* Internal */
+	uint	spi_tstate;	/* Internal */
+	uint	spi_tdp;	/* Internal */
+	ushort	spi_tbptr;	/* Internal */
+	ushort	spi_tbc;	/* Internal */
+	uint	spi_txtmp;	/* Internal */
+	uint	spi_res;
+	ushort	spi_rpbase;	/* Relocation pointer */
+	ushort	spi_res2;
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
+#define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
+#define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
+#define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
+#define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
+#define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
+#define SPMODE_EN	((ushort)0x0100)	/* Enable */
+#define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
+#define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
+
+#define SPMODE_LEN(x)	((((x)-1)&0xF)<<4)
+#define SPMODE_PM(x)	((x) &0xF)
+
+/* HDLC parameter RAM.
+*/
+
+typedef struct hdlc_pram_s {
+	/*
+	 * SCC parameter RAM
+	 */
+	ushort	rbase;		/* Rx Buffer descriptor base address */
+	ushort	tbase;		/* Tx Buffer descriptor base address */
+	uchar	rfcr;		/* Rx function code */
+	uchar	tfcr;		/* Tx function code */
+	ushort	mrblr;		/* Rx buffer length */
+	ulong	rstate;		/* Rx internal state */
+	ulong	rptr;		/* Rx internal data pointer */
+	ushort	rbptr;		/* rb BD Pointer */
+	ushort	rcount;		/* Rx internal byte count */
+	ulong	rtemp;		/* Rx temp */
+	ulong	tstate;		/* Tx internal state */
+	ulong	tptr;		/* Tx internal data pointer */
+	ushort	tbptr;		/* Tx BD pointer */
+	ushort	tcount;		/* Tx byte count */
+	ulong	ttemp;		/* Tx temp */
+	ulong	rcrc;		/* temp receive CRC */
+	ulong	tcrc;		/* temp transmit CRC */
+	/*
+	 * HDLC specific parameter RAM
+	 */
+	uchar	res[4];		/* reserved */
+	ulong	c_mask;		/* CRC constant */
+	ulong	c_pres;		/* CRC preset */
+	ushort	disfc;		/* discarded frame counter */
+	ushort	crcec;		/* CRC error counter */
+	ushort	abtsc;		/* abort sequence counter */
+	ushort	nmarc;		/* nonmatching address rx cnt */
+	ushort	retrc;		/* frame retransmission cnt */
+	ushort	mflr;		/* maximum frame length reg */
+	ushort	max_cnt;	/* maximum length counter */
+	ushort	rfthr;		/* received frames threshold */
+	ushort	rfcnt;		/* received frames count */
+	ushort	hmask;		/* user defined frm addr mask */
+	ushort	haddr1;		/* user defined frm address 1 */
+	ushort	haddr2;		/* user defined frm address 2 */
+	ushort	haddr3;		/* user defined frm address 3 */
+	ushort	haddr4;		/* user defined frm address 4 */
+	ushort	tmp;		/* temp */
+	ushort	tmp_mb;		/* temp */
+} hdlc_pram_t;
+
+/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
+ * channels or devices.  All of these are presented to the PPC core
+ * as a single interrupt.  The CPM interrupt handler dispatches its
+ * own handlers, in a similar fashion to the PPC core handler.  We
+ * use the table as defined in the manuals (i.e. no special high
+ * priority and SCC1 == SCCa, etc...).
+ */
+#define CPMVEC_NR		32
+#define CPMVEC_OFFSET           0x00010000
+#define CPMVEC_PIO_PC15		((ushort)0x1f | CPMVEC_OFFSET)
+#define CPMVEC_SCC1		((ushort)0x1e | CPMVEC_OFFSET)
+#define CPMVEC_SCC2		((ushort)0x1d | CPMVEC_OFFSET)
+#define CPMVEC_SCC3		((ushort)0x1c | CPMVEC_OFFSET)
+#define CPMVEC_SCC4		((ushort)0x1b | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC14		((ushort)0x1a | CPMVEC_OFFSET)
+#define CPMVEC_TIMER1		((ushort)0x19 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC13		((ushort)0x18 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC12		((ushort)0x17 | CPMVEC_OFFSET)
+#define CPMVEC_SDMA_CB_ERR	((ushort)0x16 | CPMVEC_OFFSET)
+#define CPMVEC_IDMA1		((ushort)0x15 | CPMVEC_OFFSET)
+#define CPMVEC_IDMA2		((ushort)0x14 | CPMVEC_OFFSET)
+#define CPMVEC_TIMER2		((ushort)0x12 | CPMVEC_OFFSET)
+#define CPMVEC_RISCTIMER	((ushort)0x11 | CPMVEC_OFFSET)
+#define CPMVEC_I2C		((ushort)0x10 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC11		((ushort)0x0f | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC10		((ushort)0x0e | CPMVEC_OFFSET)
+#define CPMVEC_TIMER3		((ushort)0x0c | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC9		((ushort)0x0b | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC8		((ushort)0x0a | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC7		((ushort)0x09 | CPMVEC_OFFSET)
+#define CPMVEC_TIMER4		((ushort)0x07 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC6		((ushort)0x06 | CPMVEC_OFFSET)
+#define CPMVEC_SPI		((ushort)0x05 | CPMVEC_OFFSET)
+#define CPMVEC_SMC1		((ushort)0x04 | CPMVEC_OFFSET)
+#define CPMVEC_SMC2		((ushort)0x03 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC5		((ushort)0x02 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC4		((ushort)0x01 | CPMVEC_OFFSET)
+#define CPMVEC_ERROR		((ushort)0x00 | CPMVEC_OFFSET)
+
+extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
+
+/* CPM interrupt configuration vector.
+*/
+#define	CICR_SCD_SCC4		((uint)0x00c00000)	/* SCC4 @ SCCd */
+#define	CICR_SCC_SCC3		((uint)0x00200000)	/* SCC3 @ SCCc */
+#define	CICR_SCB_SCC2		((uint)0x00040000)	/* SCC2 @ SCCb */
+#define	CICR_SCA_SCC1		((uint)0x00000000)	/* SCC1 @ SCCa */
+#define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrrupt */
+#define CICR_HP_MASK		((uint)0x00001f00)	/* Hi-pri int. */
+#define CICR_IEN		((uint)0x00000080)	/* Int. enable */
+#define CICR_SPS		((uint)0x00000001)	/* SCC Spread */
+#endif /* __CPM_8XX__ */
diff --git a/include/compiler.h b/include/compiler.h
new file mode 100755
index 0000000..4e047c7
--- /dev/null
+++ b/include/compiler.h
@@ -0,0 +1,129 @@
+/*
+ * Keep all the ugly #ifdef for system stuff here
+ */
+
+#ifndef __COMPILER_H__
+#define __COMPILER_H__
+
+#include <stddef.h>
+
+#ifdef USE_HOSTCC
+
+#if defined(__BEOS__)	 || \
+    defined(__NetBSD__)  || \
+    defined(__FreeBSD__) || \
+    defined(__sun__)	 || \
+    defined(__APPLE__)
+# include <inttypes.h>
+#elif defined(__linux__) || defined(__WIN32__) || defined(__MINGW32__)
+# include <stdint.h>
+#endif
+
+#include <errno.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#if !defined(__WIN32__) && !defined(__MINGW32__)
+# include <sys/mman.h>
+#endif
+
+/* Not all systems (like Windows) has this define, and yes
+ * we do replace/emulate mmap() on those systems ...
+ */
+#ifndef MAP_FAILED
+# define MAP_FAILED ((void *)-1)
+#endif
+
+#include <fcntl.h>
+#ifndef O_BINARY		/* should be define'd on __WIN32__ */
+#define O_BINARY	0
+#endif
+
+#ifdef __linux__
+# include <endian.h>
+# include <byteswap.h>
+#elif defined(__MACH__) || defined(__FreeBSD__)
+# include <machine/endian.h>
+typedef unsigned long ulong;
+#endif
+
+typedef uint8_t __u8;
+typedef uint16_t __u16;
+typedef uint32_t __u32;
+typedef unsigned int uint;
+
+#define uswap_16(x) \
+	((((x) & 0xff00) >> 8) | \
+	 (((x) & 0x00ff) << 8))
+#define uswap_32(x) \
+	((((x) & 0xff000000) >> 24) | \
+	 (((x) & 0x00ff0000) >>  8) | \
+	 (((x) & 0x0000ff00) <<  8) | \
+	 (((x) & 0x000000ff) << 24))
+#define _uswap_64(x, sfx) \
+	((((x) & 0xff00000000000000##sfx) >> 56) | \
+	 (((x) & 0x00ff000000000000##sfx) >> 40) | \
+	 (((x) & 0x0000ff0000000000##sfx) >> 24) | \
+	 (((x) & 0x000000ff00000000##sfx) >>  8) | \
+	 (((x) & 0x00000000ff000000##sfx) <<  8) | \
+	 (((x) & 0x0000000000ff0000##sfx) << 24) | \
+	 (((x) & 0x000000000000ff00##sfx) << 40) | \
+	 (((x) & 0x00000000000000ff##sfx) << 56))
+#if defined(__GNUC__)
+# define uswap_64(x) _uswap_64(x, ull)
+#else
+# define uswap_64(x) _uswap_64(x, )
+#endif
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+# define cpu_to_le16(x)		(x)
+# define cpu_to_le32(x)		(x)
+# define cpu_to_le64(x)		(x)
+# define le16_to_cpu(x)		(x)
+# define le32_to_cpu(x)		(x)
+# define le64_to_cpu(x)		(x)
+# define cpu_to_be16(x)		uswap_16(x)
+# define cpu_to_be32(x)		uswap_32(x)
+# define cpu_to_be64(x)		uswap_64(x)
+# define be16_to_cpu(x)		uswap_16(x)
+# define be32_to_cpu(x)		uswap_32(x)
+# define be64_to_cpu(x)		uswap_64(x)
+#else
+# define cpu_to_le16(x)		uswap_16(x)
+# define cpu_to_le32(x)		uswap_32(x)
+# define cpu_to_le64(x)		uswap_64(x)
+# define le16_to_cpu(x)		uswap_16(x)
+# define le32_to_cpu(x)		uswap_32(x)
+# define le64_to_cpu(x)		uswap_64(x)
+# define cpu_to_be16(x)		(x)
+# define cpu_to_be32(x)		(x)
+# define cpu_to_be64(x)		(x)
+# define be16_to_cpu(x)		(x)
+# define be32_to_cpu(x)		(x)
+# define be64_to_cpu(x)		(x)
+#endif
+
+#else /* !USE_HOSTCC */
+
+#include <linux/string.h>
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+/* Types for `void *' pointers. */
+#if __WORDSIZE == 64
+typedef unsigned long int       uintptr_t;
+#else
+typedef unsigned int            uintptr_t;
+#endif
+
+#endif
+
+/* compiler options */
+#define uninitialized_var(x)		x = x
+
+#define likely(x)	__builtin_expect(!!(x), 1)
+#define unlikely(x)	__builtin_expect(!!(x), 0)
+
+#endif
diff --git a/include/configs/A3000.h b/include/configs/A3000.h
new file mode 100755
index 0000000..ca9592c
--- /dev/null
+++ b/include/configs/A3000.h
@@ -0,0 +1,324 @@
+/*
+ * (C) Copyright 2001, 2002, 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Configuration settings for the A-3000 board (Artis Microsystems Inc.).
+ * http://artismicro.com
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8245		1
+#define CONFIG_A3000		1
+
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_BOOTDELAY	5
+
+#if 0
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
+				  CFG_CMD_BEDBUG | \
+				  CFG_CMD_BSP    | \
+				  CFG_CMD_ELF    | \
+				  CFG_CMD_I2C 	 | \
+				  CFG_CMD_FLASH | \
+				  CFG_CMD_BEDBUG | \
+				  CFG_CMD_NET    | \
+				  CFG_CMD_PCI )
+#endif
+
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) 	*/
+
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"A3000> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+/* Print Buffer Size
+ */
+#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS	8		/* Max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x00400000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
+#undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI      		/* include pci support          */
+#undef CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW    /* print pci devices @ startup  */
+
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support */
+
+/* #define CONFIG_TULIP */
+/* #define CONFIG_EEPRO100 */
+#define CONFIG_NATSEMI
+
+#define PCI_ENET0_IOADDR		0x80000000
+#define PCI_ENET0_MEMADDR		0x80000000
+#define PCI_ENET1_IOADDR		0x81000000
+#define PCI_ENET1_MEMADDR		0x81000000
+#define PCI_ENET2_IOADDR		0x82000000
+#define PCI_ENET2_MEMADDR		0x82000000
+#define PCI_ENET3_IOADDR		0x83000000
+#define PCI_ENET3_MEMADDR		0x83000000
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE	    0x00000000
+
+#define CFG_FLASH_BASE0_PRELIM      0xFF000000      /* FLASH bank on RCS#0 */
+#define CFG_FLASH_BASE1_PRELIM      0xFF000000      /* FLASH bank on RCS#1 */
+#define CFG_FLASH_BASE  			CFG_FLASH_BASE0_PRELIM
+#define CFG_FLASH_BANKS			{ CFG_FLASH_BASE0_PRELIM }
+
+/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
+ * reset vector is actually located at FFB00100, but the 8245
+ * takes care of us.
+ */
+#define CFG_RESET_ADDRESS   0xFFF00100
+
+#define CFG_EUMB_ADDR	    0xFC000000
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+
+#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+	/* Maximum amount of RAM.
+	 */
+#define CFG_MAX_RAM_SIZE    0x04000000	/* 0 .. 128 MB of (S)DRAM */
+
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	1
+
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
+#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+/* #define CFG_MONITOR_BASE        TEXT_BASE */
+/*#define CFG_GBL_DATA_SIZE    256*/
+#define CFG_GBL_DATA_SIZE      128
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x1000
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
+#define CFG_HZ		     1000
+
+	/* Bit-field values for MCCR1.
+	 */
+#define CFG_ROMNAL	    7
+#define CFG_ROMFAL	    11
+#define CFG_DBUS_SIZE       0x3
+
+	/* Bit-field values for MCCR2.
+	 */
+#define CFG_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
+#define CFG_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
+
+	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+	 */
+#define CFG_BSTOPRE	    121
+
+	/* Bit-field values for MCCR3.
+	 */
+#define CFG_REFREC	    8	    /* Refresh to activate interval */
+
+	/* Bit-field values for MCCR4.
+	 */
+#define CFG_PRETOACT	    3	    /* Precharge to activate interval FIXME: was 2	*/
+#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
+#define CFG_ACTORW	    3		/* FIXME was 2 */
+#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
+#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
+#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CFG_EXTROM	    1
+#define CFG_REGDIMM	    0
+
+#define CFG_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
+
+#define CFG_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CFG_BANK0_START	    0x00000000
+#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE    1
+#define CFG_BANK1_START	    0x3ff00000
+#define CFG_BANK1_END	    0x3fffffff
+#define CFG_BANK1_ENABLE    0
+#define CFG_BANK2_START	    0x3ff00000
+#define CFG_BANK2_END	    0x3fffffff
+#define CFG_BANK2_ENABLE    0
+#define CFG_BANK3_START	    0x3ff00000
+#define CFG_BANK3_END	    0x3fffffff
+#define CFG_BANK3_ENABLE    0
+#define CFG_BANK4_START	    0x3ff00000
+#define CFG_BANK4_END	    0x3fffffff
+#define CFG_BANK4_ENABLE    0
+#define CFG_BANK5_START	    0x3ff00000
+#define CFG_BANK5_END	    0x3fffffff
+#define CFG_BANK5_ENABLE    0
+#define CFG_BANK6_START	    0x3ff00000
+#define CFG_BANK6_END	    0x3fffffff
+#define CFG_BANK6_ENABLE    0
+#define CFG_BANK7_START	    0x3ff00000
+#define CFG_BANK7_END	    0x3fffffff
+#define CFG_BANK7_ENABLE    0
+
+#define CFG_ODCR	    0xff
+
+#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L  CFG_IBAT0L
+#define CFG_DBAT0U  CFG_IBAT0U
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+#define CFG_DBAT2L  CFG_IBAT2L
+#define CFG_DBAT2U  CFG_IBAT2U
+#define CFG_DBAT3L  CFG_IBAT3L
+#define CFG_DBAT3U  CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CFG_MAX_FLASH_SECT	128	/* Max number of sectors per flash	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+
+	/* Warining: environment is not EMBEDDED in the U-Boot code.
+	 * It's stored in flash separately.
+	 */
+#define CFG_ENV_IS_IN_FLASH	    1
+#define CFG_ENV_ADDR		0xFFFE0000
+#define CFG_ENV_SIZE		0x00020000 /* Size of the Environment		*/
+#define CFG_ENV_SECT_SIZE	0x00020000 /* Size of the Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h
new file mode 100755
index 0000000..821efe5
--- /dev/null
+++ b/include/configs/ADCIOP.h
@@ -0,0 +1,210 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_IOP480		1	/* This is a IOP480 CPU		*/
+#define CONFIG_ADCIOP		1	/* ...on a ADCIOP board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_CPUCLOCK		66
+#define CONFIG_BUSCLOCK		(CONFIG_CPUCLOCK)
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+#define CONFIG_BOOTCOMMAND	"bootm ffc00000" /* autoboot command	*/
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+
+#define CONFIG_IPADDR		10.0.18.222
+#define CONFIG_SERVERIP		10.0.18.190
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_ASKENV	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
+#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFD0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x0AA9	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x0556	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0002	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0000	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0004	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 1 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#define CFG_NVRAM_BASE_ADDR	0x10000000		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CFG_ENV_SIZE		0x0400		/* Size of Environment vars	*/
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
+#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x7800) /* VxWorks eth-addr*/
+
+#else /* Use FLASH for environment variables */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
+#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
+
+#define CFG_ENV_SECT_SIZE	0x8000	/* see README - env sector total size	*/
+
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ */
+#define CONFIG_PCI			/* include pci support			*/
+#undef CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/
+
+#define CONFIG_TULIP
+
+#define CFG_ETH_DEV_FN	     0x0000
+#define CFG_ETH_IOBASE	     0x0fff0000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		2048	/* For PLX IOP480			*/
+#define CFG_CACHELINE_SIZE	16	/* For AMCC 401/403 CPUs		*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFE00000	/* FLASH bank #1	*/
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h
new file mode 100755
index 0000000..2efca10
--- /dev/null
+++ b/include/configs/ADNPESC1.h
@@ -0,0 +1,694 @@
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/***********************************************************************
+ * Include the whole NIOS CPU configuration.
+ *
+ * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
+ *
+ ***********************************************************************/
+
+#if	defined(CONFIG_NIOS_BASE_32)
+#include <configs/ADNPESC1_base_32.h>
+#else
+#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
+#endif
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU -- TOP-LEVEL
+ *----------------------------------------------------------------------*/
+#define CONFIG_NIOS		1		/* NIOS-32 core		*/
+#define	CONFIG_ADNPESC1		1		/* SSV ADNP/ESC1 board	*/
+#define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/
+#define	CFG_HZ			1000		/* 1 msec time tick	*/
+#undef  CFG_CLKS_IN_HZ
+#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
+
+/*------------------------------------------------------------------------
+ * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_SDRAM_SIZE != 0)
+
+#define CFG_SDRAM_BASE		CFG_NIOS_CPU_SDRAM_BASE
+#define CFG_SDRAM_SIZE		CFG_NIOS_CPU_SDRAM_SIZE
+
+#else
+#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
+#endif
+
+#if	defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)
+
+#define	CFG_SRAM_BASE		CFG_NIOS_CPU_SRAM_BASE
+#define	CFG_SRAM_SIZE		CFG_NIOS_CPU_SRAM_SIZE
+
+#else
+
+#undef	CFG_SRAM_BASE
+#undef	CFG_SRAM_SIZE
+
+#endif
+
+#define CFG_VECT_BASE		CFG_NIOS_CPU_VEC_BASE
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION - For the most part, you can put things pretty
+ * much anywhere. This is pretty flexible for Nios. So here we make some
+ * arbitrary choices & assume that the monitor is placed at the end of
+ * a memory resource (so you must make sure TEXT_BASE is chosen
+ * appropriately -- this is very important if you plan to move your
+ * memory to another place as configured at this time !!!).
+ *
+ * 	-The heap is placed below the monitor.
+ * 	-Global data is placed below the heap.
+ * 	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
+#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
+
+#define CFG_FLASH_BASE		CFG_NIOS_CPU_FLASH_BASE
+#define CFG_FLASH_SIZE		CFG_NIOS_CPU_FLASH_SIZE
+#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size	*/
+
+#else
+#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
+#endif
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
+
+#define	CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+
+/* Mem addr of environment */
+#if	defined(CONFIG_NIOS_BASE_32)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+#else
+#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR
+#endif
+
+#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial/eth change Ok */
+
+#else
+#define	CFG_ENV_IS_NOWHERE	1		/* NO Environment	*/
+#endif
+
+/*------------------------------------------------------------------------
+ * NIOS APPLICATION CODE BASE AREA
+ *----------------------------------------------------------------------*/
+#if	((CFG_ENV_ADDR + CFG_ENV_SIZE) == 0x1050000)
+#define	CFG_ADNPESC1_UPDATE_LOAD_ADDR	"0x2000100"
+#define CFG_ADNPESC1_NIOS_APPL_ENTRY	"0x1050000"
+#define CFG_ADNPESC1_NIOS_APPL_IDENT	"0x105000c"
+#define	CFG_ADNPESC1_NIOS_APPL_END	"0x11fffff"
+#define CFG_ADNPESC1_FILESYSTEM_BASE	"0x1200000"
+#define	CFG_ADNPESC1_FILESYSTEM_END	"0x17fffff"
+#else
+#error *** CFG_ERROR: missing right appl.code base configuration, expand your config.h
+#endif
+#define CFG_ADNPESC1_NIOS_IDENTIFIER	"Nios"
+
+/*------------------------------------------------------------------------
+ * BOOT ENVIRONMENT
+ *----------------------------------------------------------------------*/
+#ifdef	CONFIG_DNPEVA2			/* DNP/EVA2 base board */
+#define	CFG_ADNPESC1_SLED_BOOT_OFF	"sled boot off; "
+#define	CFG_ADNPESC1_SLED_RED_BLINK	"sled red blink; "
+#else
+#define	CFG_ADNPESC1_SLED_BOOT_OFF
+#define	CFG_ADNPESC1_SLED_RED_BLINK
+#endif
+
+#define	CONFIG_BOOTDELAY	5
+#define	CONFIG_BOOTCOMMAND						\
+	"if itest.s *$appl_ident_addr == \"$appl_ident_str\"; "		\
+	"then "								\
+		"wd off; "						\
+		CFG_ADNPESC1_SLED_BOOT_OFF				\
+		"go $appl_entry_addr; "					\
+	"else "								\
+		CFG_ADNPESC1_SLED_RED_BLINK				\
+		"echo *** missing \"$appl_ident_str\" at $appl_ident_addr; "\
+		"echo *** invalid application at $appl_entry_addr; "	\
+		"echo *** stop bootup...; "				\
+	"fi"
+
+/*------------------------------------------------------------------------
+ * EXTRA ENVIRONMENT
+ *----------------------------------------------------------------------*/
+#ifdef	CONFIG_DNPEVA2			/* DNP/EVA2 base board */
+#define	CFG_ADNPESC1_SLED_YELLO_ON	"sled yellow on; "
+#define	CFG_ADNPESC1_SLED_YELLO_OFF	"sled yellow off; "
+#else
+#define	CFG_ADNPESC1_SLED_YELLO_ON
+#define	CFG_ADNPESC1_SLED_YELLO_OFF
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"update_allowed=0\0"						\
+	"update_load_addr="	CFG_ADNPESC1_UPDATE_LOAD_ADDR	"\0"	\
+	"appl_entry_addr="	CFG_ADNPESC1_NIOS_APPL_ENTRY	"\0"	\
+	"appl_end_addr="	CFG_ADNPESC1_NIOS_APPL_END	"\0"	\
+	"appl_ident_addr="	CFG_ADNPESC1_NIOS_APPL_IDENT	"\0"	\
+	"appl_ident_str="	CFG_ADNPESC1_NIOS_IDENTIFIER	"\0"	\
+	"appl_name=ADNPESC1/base32/linux.bin\0"				\
+	"appl_update="							\
+		"if itest.b $update_allowed != 0; "			\
+		"then "							\
+			CFG_ADNPESC1_SLED_YELLO_ON			\
+			"tftp $update_load_addr $appl_name; "		\
+			"protect off $appl_entry_addr $appl_end_addr; "	\
+			"era $appl_entry_addr $appl_end_addr; "		\
+			"cp.b $update_load_addr $appl_entry_addr $filesize; "\
+			CFG_ADNPESC1_SLED_YELLO_OFF			\
+		"else "							\
+			"echo *** update not allowed (update_allowed=$update_allowed); "\
+		"fi\0"							\
+	"fs_base_addr="		CFG_ADNPESC1_FILESYSTEM_BASE	"\0"	\
+	"fs_end_addr="		CFG_ADNPESC1_FILESYSTEM_END	"\0"	\
+	"fs_name=ADNPESC1/base32/romfs.img\0"				\
+	"fs_update="							\
+		"if itest.b $update_allowed != 0; "			\
+		"then "							\
+			CFG_ADNPESC1_SLED_YELLO_ON			\
+			"tftp $update_load_addr $fs_name; "		\
+			"protect off $fs_base_addr $fs_end_addr; "	\
+			"era $fs_base_addr $fs_end_addr; "		\
+			"cp.b $update_load_addr $fs_base_addr $filesize; "\
+			CFG_ADNPESC1_SLED_YELLO_OFF			\
+		"else "							\
+			"echo *** update not allowed (update_allowed=$update_allowed); "\
+		"fi\0"							\
+	"uboot_name=ADNPESC1/base32/u-boot.bin\0"			\
+	"uboot_loadnrun="						\
+		"if ping $serverip; "					\
+		"then "							\
+			CFG_ADNPESC1_SLED_YELLO_ON			\
+			"tftp $update_load_addr $uboot_name; "		\
+			"wd off; "					\
+			"go $update_load_addr; "			\
+		"else "							\
+			"echo *** missing connection to $serverip; "	\
+			"echo *** check your network and try again...; "\
+		"fi\0"
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_UART_NUMS != 0)
+
+#define CFG_NIOS_CONSOLE	CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
+
+#if	(CFG_NIOS_CPU_UART0_BR != 0)
+#define CFG_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		CFG_NIOS_CPU_UART0_BR
+#else
+#undef	CFG_NIOS_FIXEDBAUD
+#define CONFIG_BAUDRATE		115200
+#endif
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#else
+#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
+#endif
+
+/*------------------------------------------------------------------------
+ * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
+ * so an avalon bus timer is required.
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)
+
+#if	(CFG_NIOS_CPU_TICK_TIMER == 0)
+
+#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
+#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER0_IRQ
+
+#if	(CFG_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */
+
+#if	(CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
+#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
+#else
+#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#endif
+
+#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
+
+#elif	(CFG_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */
+
+#if	(CFG_HZ <= 1000)
+#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
+#else
+#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#endif
+
+#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
+
+#else
+#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
+#endif
+
+#elif	(CFG_NIOS_CPU_TICK_TIMER == 1)
+
+#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
+#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER1_IRQ
+
+#if	(CFG_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */
+
+#if	(CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
+#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
+#else
+#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#endif
+
+#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
+
+#elif	(CFG_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */
+
+#if	(CFG_HZ <= 1000)
+#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
+#else
+#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#endif
+
+#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
+
+#else
+#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
+#endif
+
+#endif	/* CFG_NIOS_CPU_TICK_TIMER */
+
+#else
+#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
+#endif
+
+/*------------------------------------------------------------------------
+ * WATCHDOG (or better MAX823 supervisory circuite access)
+ *----------------------------------------------------------------------*/
+#define	CONFIG_HW_WATCHDOG	1		/* board specific WD	*/
+
+#ifdef	CONFIG_HW_WATCHDOG
+
+/* MAX823 supervisor -- watchdog enable port at: */
+#if	(CFG_NIOS_CPU_WDENA_PIO == 0)
+#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO0	/* PIO0		*/
+#elif	(CFG_NIOS_CPU_WDENA_PIO == 1)
+#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO1	/* PIO1		*/
+#elif	(CFG_NIOS_CPU_WDENA_PIO == 2)
+#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO2	/* PIO2		*/
+#elif	(CFG_NIOS_CPU_WDENA_PIO == 3)
+#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO3	/* PIO3		*/
+#elif	(CFG_NIOS_CPU_WDENA_PIO == 4)
+#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO4	/* PIO4		*/
+#elif	(CFG_NIOS_CPU_WDENA_PIO == 5)
+#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO5	/* PIO5		*/
+#elif	(CFG_NIOS_CPU_WDENA_PIO == 6)
+#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO6	/* PIO6		*/
+#elif	(CFG_NIOS_CPU_WDENA_PIO == 7)
+#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO7	/* PIO7		*/
+#elif	(CFG_NIOS_CPU_WDENA_PIO == 8)
+#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO8	/* PIO8		*/
+#elif	(CFG_NIOS_CPU_WDENA_PIO == 9)
+#define	CONFIG_HW_WDENA_BASE	CFG_NIOS_CPU_PIO9	/* PIO9		*/
+#else
+#error *** CFG_ERROR: you have to setup at least one WDENA_PIO in NIOS CPU config
+#endif
+
+/* MAX823 supervisor -- watchdog trigger port at: */
+#if	(CFG_NIOS_CPU_WDTOG_PIO == 0)
+#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO0	/* PIO0		*/
+#elif	(CFG_NIOS_CPU_WDTOG_PIO == 1)
+#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO1	/* PIO1		*/
+#elif	(CFG_NIOS_CPU_WDTOG_PIO == 2)
+#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO2	/* PIO2		*/
+#elif	(CFG_NIOS_CPU_WDTOG_PIO == 3)
+#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO3	/* PIO3		*/
+#elif	(CFG_NIOS_CPU_WDTOG_PIO == 4)
+#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO4	/* PIO4		*/
+#elif	(CFG_NIOS_CPU_WDTOG_PIO == 5)
+#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO5	/* PIO5		*/
+#elif	(CFG_NIOS_CPU_WDTOG_PIO == 6)
+#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO6	/* PIO6		*/
+#elif	(CFG_NIOS_CPU_WDTOG_PIO == 7)
+#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO7	/* PIO7		*/
+#elif	(CFG_NIOS_CPU_WDTOG_PIO == 8)
+#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO8	/* PIO8		*/
+#elif	(CFG_NIOS_CPU_WDTOG_PIO == 9)
+#define	CONFIG_HW_WDTOG_BASE	CFG_NIOS_CPU_PIO9	/* PIO9		*/
+#else
+#error *** CFG_ERROR: you have to setup at least one WDTOG_PIO in NIOS CPU config
+#endif
+
+#if	defined(CONFIG_NIOS_BASE_32)		/* NIOS CPU specifics	*/
+#define	CONFIG_HW_WDENA_BIT		0	/* WD enable  @ Bit 0	*/
+#define	CONFIG_HW_WDTOG_BIT		0	/* WD trigger @ Bit 0	*/
+#define	CONFIG_HW_WDPORT_WRONLY	1	/* each WD port wr/only*/
+#else
+#error *** CFG_ERROR: missing watchdog bit configuration, expand your config.h
+#endif
+
+#endif	/* CONFIG_HW_WATCHDOG */
+
+/*------------------------------------------------------------------------
+ * SERIAL PERIPHAREL INTERFACE
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_SPI_NUMS == 1)
+
+#define	CONFIG_NIOS_SPI		1		/* SPI support active	*/
+#define	CFG_NIOS_SPIBASE	CFG_NIOS_CPU_SPI0
+#define	CFG_NIOS_SPIBITS	CFG_NIOS_CPU_SPI0_BITS
+
+#define	CONFIG_RTC_DS1306	1	/* Dallas 1306 real time clock	*/
+#define CFG_SPI_RTC_DEVID	0	/*        as 1st SPI device	*/
+
+#define	__SPI_CMD_OFF		0	/* allow default commands:	*/
+					/*	CFG_CMD_SPI		*/
+					/*	CFG_CMD_DATE		*/
+
+#else
+#undef	CONFIG_NIOS_SPI				/* NO SPI support	*/
+#define	__SPI_CMD_OFF	(	CFG_CMD_SPI	\
+			|	CFG_CMD_DATE	\
+			)
+#endif
+
+/*------------------------------------------------------------------------
+ * Ethernet -- needs work!
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_LAN_NUMS == 1)
+
+#if	(CFG_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/
+
+#define	CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
+#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
+#define	CONFIG_SMC91111_BASE	(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
+
+#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
+#define	CONFIG_SMC_USE_32_BIT	1
+#else	/* no */
+#undef	CONFIG_SMC_USE_32_BIT
+#endif
+
+#elif	(CFG_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/
+
+	/********************************************/
+	/* !!! CS8900 is __not__ tested on NIOS !!! */
+	/********************************************/
+#define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/
+#define	CS8900_BASE		(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
+
+#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
+#undef	CS8900_BUS16
+#define	CS8900_BUS32		1
+#else	/* no */
+#define	CS8900_BUS16		1
+#undef	CS8900_BUS32
+#endif
+
+#else
+#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
+#endif
+
+#define CONFIG_ETHADDR		02:80:ae:20:60:6f
+#define CONFIG_NETMASK		255.255.255.248
+#define CONFIG_IPADDR		192.168.161.84
+#define CONFIG_SERVERIP		192.168.161.85
+
+#else
+#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
+#endif
+
+/*------------------------------------------------------------------------
+ * STATUS LEDs
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)
+
+#if	(CFG_NIOS_CPU_LED_PIO == 0)
+
+#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO0
+#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO0_BITS
+#define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
+
+#if	(CFG_NIOS_CPU_PIO0_TYPE == 1)
+#define	STATUS_LED_WRONLY		1
+#else
+#undef	STATUS_LED_WRONLY
+#endif
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 1)
+
+#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO1
+#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO1_BITS
+#define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
+
+#if	(CFG_NIOS_CPU_PIO1_TYPE == 1)
+#define	STATUS_LED_WRONLY		1
+#else
+#undef	STATUS_LED_WRONLY
+#endif
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 2)
+
+#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO2
+#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO2_BITS
+#define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
+
+#if	(CFG_NIOS_CPU_PIO2_TYPE == 1)
+#define	STATUS_LED_WRONLY		1
+#else
+#undef	STATUS_LED_WRONLY
+#endif
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 3)
+
+#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 4)
+
+#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 5)
+
+#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 6)
+
+#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 7)
+
+#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 8)
+
+#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 9)
+
+#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
+
+#else
+#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
+#endif
+
+#define	CONFIG_STATUS_LED		1 /* enable status led driver */
+
+#define	STATUS_LED_BIT			(1 << 0)	/* LED[0] */
+#define	STATUS_LED_STATE		STATUS_LED_BLINKING
+#define	STATUS_LED_BOOT_STATE		STATUS_LED_OFF
+#define	STATUS_LED_PERIOD		(CFG_HZ / 2)	/* ca. 1 Hz */
+#define	STATUS_LED_BOOT			0		/* boot LED */
+
+#if	(STATUS_LED_BITS > 1)
+#define	STATUS_LED_BIT1			(1 << 1)	/* LED[1] */
+#define	STATUS_LED_STATE1		STATUS_LED_OFF
+#define	STATUS_LED_PERIOD1		(CFG_HZ / 10)	/* ca. 5 Hz */
+#define	STATUS_LED_RED			1		/* fail LED */
+#endif
+
+#if	(STATUS_LED_BITS > 2)
+#define	STATUS_LED_BIT2			(1 << 2)	/* LED[2] */
+#define	STATUS_LED_STATE2		STATUS_LED_OFF
+#define	STATUS_LED_PERIOD2		(CFG_HZ / 2)	/* ca. 1 Hz */
+#define	STATUS_LED_YELLOW		2		/* info LED */
+#endif
+
+#if	(STATUS_LED_BITS > 3)
+#define	STATUS_LED_BIT3			(1 << 3)	/* LED[3] */
+#define	STATUS_LED_STATE3		STATUS_LED_OFF
+#define	STATUS_LED_PERIOD3		(CFG_HZ / 2)	/* ca. 1 Hz */
+#define	STATUS_LED_GREEN		3		/* info LED */
+#endif
+
+#define	STATUS_LED_PAR			1 /* makes status_led.h happy */
+
+#endif	/* CFG_NIOS_CPU_PIO_NUMS */
+
+/*------------------------------------------------------------------------
+ * Diagnostics / Power On Self Tests
+ *----------------------------------------------------------------------*/
+#define	CONFIG_POST			CFG_POST_RTC
+#define	CFG_NIOS_POST_WORD_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
+				 CFG_CMD_ASKENV | \
+				 CFG_CMD_BEDBUG | \
+				 CFG_CMD_BMP	| \
+				 CFG_CMD_CACHE	| \
+				 CFG_CMD_DOC	| \
+				 CFG_CMD_DTT	| \
+				 CFG_CMD_EEPROM | \
+				 CFG_CMD_ELF    | \
+				 CFG_CMD_FAT	| \
+				 CFG_CMD_FDC	| \
+				 CFG_CMD_FDOS	| \
+				 CFG_CMD_HWFLOW	| \
+				 CFG_CMD_IDE	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_JFFS2	| \
+				 CFG_CMD_KGDB	| \
+				 CFG_CMD_NAND	| \
+				 CFG_CMD_NFS	| \
+				 CFG_CMD_MMC	| \
+				 CFG_CMD_MII	| \
+				 CFG_CMD_PCI	| \
+				 CFG_CMD_PCMCIA | \
+				 CFG_CMD_SCSI	| \
+				 CFG_CMD_VFD	| \
+				 CFG_CMD_USB	| \
+				 CFG_CMD_XIMG	| \
+				 __SPI_CMD_OFF	) )
+
+
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * KGDB
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	9600
+#endif
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define	CFG_LONGHELP			    /* undef to save memory	*/
+#define	CFG_HUSH_PARSER		1	    /* use "hush" command parser
+					       undef to save memory	*/
+#define	CFG_PROMPT		"ADNPESC1 > " /* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		1024	    /* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		64	    /* max number of command args*/
+#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */
+
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"[]> "
+#endif
+
+/* Default load address	*/
+#if	(CFG_SRAM_SIZE != 0)
+
+/* default in SRAM */
+#define	CFG_LOAD_ADDR		CFG_SRAM_BASE
+
+#elif	(CFG_SDRAM_SIZE != 0)
+
+/* default in SDRAM */
+#if	(CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
+#if 1
+#define	CFG_LOAD_ADDR		(CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
+#else
+#define	CFG_LOAD_ADDR		(CFG_SDRAM_BASE + 0x400000)
+#endif
+#else
+#define	CFG_LOAD_ADDR		CFG_SDRAM_BASE
+#endif
+
+#else
+#undef	CFG_LOAD_ADDR		/* force error break */
+#endif
+
+
+/* MEM test area */
+#if	(CFG_SDRAM_SIZE != 0)
+
+/* SDRAM begin to stack area (1MB stack) */
+#if	(CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
+#if 0
+#define	CFG_MEMTEST_START	(CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
+#else
+#define	CFG_MEMTEST_START	(CFG_SDRAM_BASE + 0x400000)
+#endif
+#else
+#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
+#endif
+
+#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024))
+#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024))
+
+#else
+#undef	CFG_MEMTEST_START	/* force error break */
+#undef	CFG_MEMTEST_END
+#endif
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		""
+#define MTDPARTS_DEFAULT	""
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ADNPESC1_base_32.h b/include/configs/ADNPESC1_base_32.h
new file mode 100755
index 0000000..55210eb
--- /dev/null
+++ b/include/configs/ADNPESC1_base_32.h
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_ADNPESC1_BASE_32_H
+#define __CONFIG_ADNPESC1_BASE_32_H
+
+/*
+ * NIOS CPU configuration. (PART OF configs/ADNPESC1.h)
+ *
+ * Here we must define CPU dependencies. Any unsupported option have to
+ * be undefined or defined with zero, example CPU without data cache / OCI:
+ *
+ *	#define	CFG_NIOS_CPU_ICACHE	4096
+ *	#define	CFG_NIOS_CPU_DCACHE	0
+ *	#undef	CFG_NIOS_CPU_OCI_BASE
+ *	#undef	CFG_NIOS_CPU_OCI_SIZE
+ */
+
+/* CPU core */
+#define	CFG_NIOS_CPU_CLK	50000000	/* NIOS CPU clock	*/
+#define	CFG_NIOS_CPU_ICACHE	(0)		/* instruction cache	*/
+#define	CFG_NIOS_CPU_DCACHE	(0)		/* data cache		*/
+#define	CFG_NIOS_CPU_REG_NUMS	512		/* number of register	*/
+#define	CFG_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_STACK	0x03000000	/* stack top	addr	*/
+#define	CFG_NIOS_CPU_VEC_BASE	0x02000000	/* IRQ vectors	addr	*/
+#define	CFG_NIOS_CPU_VEC_SIZE	256		/*		size	*/
+#define	CFG_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
+#define	CFG_NIOS_CPU_RST_VECT	0x00000000	/* RESET vector	addr	*/
+#define	CFG_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
+						/*		yes(1)	*/
+
+/* The offset address in flash to check for the Nios signature "Ni".
+ * (see GM_FlashExec in germs_monitor.s) */
+#define	CFG_NIOS_CPU_EXES_OFFS	0x0C
+
+/* on-chip extensions */
+#undef	CFG_NIOS_CPU_RAM_BASE			/* on chip RAM	addr	*/
+#undef	CFG_NIOS_CPU_RAM_SIZE			/* 64 KB	size	*/
+
+#define	CFG_NIOS_CPU_ROM_BASE	0x00000000	/* on chip ROM	addr	*/
+#define	CFG_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
+
+#undef	CFG_NIOS_CPU_OCI_BASE			/* OCI core	addr	*/
+#undef	CFG_NIOS_CPU_OCI_SIZE			/*		size	*/
+
+/* timer */
+#define	CFG_NIOS_CPU_TIMER_NUMS	1		/* number of timer	*/
+
+#define	CFG_NIOS_CPU_TIMER0	0x00000840	/* TIMER0	addr	*/
+#define	CFG_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
+#define	CFG_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
+#define	CFG_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
+						/*		yes(1)	*/
+
+/* serial i/o */
+#define	CFG_NIOS_CPU_UART_NUMS	2		/* number of uarts	*/
+
+#define	CFG_NIOS_CPU_UART0	0x00000800	/* UART0	addr	*/
+#define	CFG_NIOS_CPU_UART0_IRQ	17		/*		IRQ	*/
+#define	CFG_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
+#define	CFG_NIOS_CPU_UART0_DB	8		/*  data bit		*/
+#define	CFG_NIOS_CPU_UART0_SB	1		/*  stop bit		*/
+#define	CFG_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
+						/*		odd(1)	*/
+						/*		even(2)	*/
+#define	CFG_NIOS_CPU_UART0_HS	1		/*  handshake:	no(0)	*/
+						/*		crts(1)	*/
+#define	CFG_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
+						/*		yes(1)	*/
+
+#define	CFG_NIOS_CPU_UART1	0x00000820	/* UART1	addr	*/
+#define	CFG_NIOS_CPU_UART1_IRQ	18		/*		IRQ	*/
+#define	CFG_NIOS_CPU_UART1_BR	115200		/*  baudrate	var(0)	*/
+#define	CFG_NIOS_CPU_UART1_DB	8		/*  data bit		*/
+#define	CFG_NIOS_CPU_UART1_SB	1		/*  stop bit		*/
+#define	CFG_NIOS_CPU_UART1_PA	0		/*  parity	none(0)	*/
+						/*		odd(1)	*/
+						/*		even(2)	*/
+#define	CFG_NIOS_CPU_UART1_HS	0		/*  handshake:	no(0)	*/
+						/*		crts(1)	*/
+#define	CFG_NIOS_CPU_UART1_EOP	0		/*  eop reg:	no(0)	*/
+						/*		yes(1)	*/
+
+/* serial peripheral i/o */
+#define	CFG_NIOS_CPU_SPI_NUMS	1		/* number of spis	*/
+
+#define	CFG_NIOS_CPU_SPI0	0x000008c0	/* SPI0		addr	*/
+#define	CFG_NIOS_CPU_SPI0_IRQ	25		/*		IRQ	*/
+#define	CFG_NIOS_CPU_SPI0_BITS	16		/*  data bit		*/
+#define	CFG_NIOS_CPU_SPI0_MA	1		/*  is master:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_SPI0_SLN	1		/*  num slaves		*/
+#define	CFG_NIOS_CPU_SPI0_TCLK	250000		/*  clock (Hz)		*/
+#define	CFG_NIOS_CPU_SPI0_TDELAY 2		/*  delay (usec)	*/
+#define	CFG_NIOS_CPU_SPI0_FB	0		/*  first bit	msb(0)	*/
+						/*		lsb(1)	*/
+
+/* parallel i/o */
+#define	CFG_NIOS_CPU_PIO_NUMS	14		/* number of parports	*/
+
+#define	CFG_NIOS_CPU_PIO0	0x00000860	/* PIO0		addr	*/
+#undef	CFG_NIOS_CPU_PIO0_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO0_BITS	8		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO0_TYPE	0		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO0_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO0_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO0_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO1	0x00000870	/* PIO1		addr	*/
+#undef	CFG_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO1_BITS	8		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO1_TYPE	0		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO2	0x00000880	/* PIO2		addr	*/
+#undef	CFG_NIOS_CPU_PIO2_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO2_BITS	4		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO2_TYPE	0		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO2_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO2_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO2_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO3	0x00000890	/* PIO3		addr	*/
+#undef	CFG_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO3_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO3_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO3	0x00000890	/* PIO3		addr	*/
+#undef	CFG_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO3_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO3_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO4	0x000008a0	/* PIO4		addr	*/
+#undef	CFG_NIOS_CPU_PIO4_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO4_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO4_TYPE	1		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO4_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO4_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO4_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO5	0x000008b0	/* PIO5		addr	*/
+#undef	CFG_NIOS_CPU_PIO5_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO5_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO5_TYPE	1		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO5_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO5_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO5_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO6	0x00000900	/* PIO6		addr	*/
+#define	CFG_NIOS_CPU_PIO6_IRQ	20		/*		IRQ	*/
+#define	CFG_NIOS_CPU_PIO6_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO6_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO6_CAP	1		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO6_EDGE	2		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO6_ITYPE	1		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO7	0x00000910	/* PIO7		addr	*/
+#define	CFG_NIOS_CPU_PIO7_IRQ	31		/*		IRQ	*/
+#define	CFG_NIOS_CPU_PIO7_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO7_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO7_CAP	1		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO7_EDGE	2		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO7_ITYPE	1		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO8	0x00000920	/* PIO8		addr	*/
+#define	CFG_NIOS_CPU_PIO8_IRQ	32		/*		IRQ	*/
+#define	CFG_NIOS_CPU_PIO8_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO8_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO8_CAP	1		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO8_EDGE	2		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO8_ITYPE	1		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO9	0x00000930	/* PIO9		addr	*/
+#define	CFG_NIOS_CPU_PIO9_IRQ	33		/*		IRQ	*/
+#define	CFG_NIOS_CPU_PIO9_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO9_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO9_CAP	1		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO9_EDGE	2		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO9_ITYPE	1		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO10	0x00000940	/* PIO10	addr	*/
+#define	CFG_NIOS_CPU_PIO10_IRQ	34		/*		IRQ	*/
+#define	CFG_NIOS_CPU_PIO10_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO10_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO10_CAP	1		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO10_EDGE	2		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO10_ITYPE 1		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO11	0x00000950	/* PIO11	addr	*/
+#define	CFG_NIOS_CPU_PIO11_IRQ	35		/*		IRQ	*/
+#define	CFG_NIOS_CPU_PIO11_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO11_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO11_CAP	1		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO11_EDGE	2		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO11_ITYPE 1		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO12	0x00000960	/* PIO12	addr	*/
+#define	CFG_NIOS_CPU_PIO12_IRQ	36		/*		IRQ	*/
+#define	CFG_NIOS_CPU_PIO12_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO12_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO12_CAP	1		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO12_EDGE	2		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO12_ITYPE 1		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO13	0x00000970	/* PIO113	addr	*/
+#define	CFG_NIOS_CPU_PIO13_IRQ	37		/*		IRQ	*/
+#define	CFG_NIOS_CPU_PIO13_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO13_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO13_CAP	1		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO13_EDGE	2		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO13_ITYPE 1		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+/* IDE i/f */
+#define	CFG_NIOS_CPU_IDE_NUMS	2		/* number of IDE contr.	*/
+
+#define	CFG_NIOS_CPU_IDE0	0x00001000	/* IDE0		addr	*/
+#define	CFG_NIOS_CPU_IDE0_IRQ	36		/* 		IRQ	*/
+
+#define	CFG_NIOS_CPU_IDE1	0x00001020	/* IDE1		addr	*/
+#define	CFG_NIOS_CPU_IDE1_IRQ	37		/* 		IRQ	*/
+
+/* memory accessibility */
+#undef	CFG_NIOS_CPU_SRAM_BASE			/* board SRAM	addr	*/
+#undef	CFG_NIOS_CPU_SRAM_SIZE			/*  1 MB	size	*/
+
+#define	CFG_NIOS_CPU_SDRAM_BASE	0x02000000	/* board SDRAM	addr	*/
+#define	CFG_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
+
+#define	CFG_NIOS_CPU_FLASH_BASE	0x01000000	/* board Flash	addr	*/
+#define	CFG_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
+
+/* LAN */
+#define	CFG_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
+
+#define	CFG_NIOS_CPU_LAN0_BASE	0x00010000	/* LAN0		addr	*/
+#define	CFG_NIOS_CPU_LAN0_OFFS	(0)		/*		offset	*/
+#define	CFG_NIOS_CPU_LAN0_IRQ	20		/*		IRQ	*/
+#define	CFG_NIOS_CPU_LAN0_BUSW	16		/*	        buswidth*/
+#define	CFG_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
+						/*	cs8900(1)	*/
+						/* ex:	openmac(2)	*/
+						/* ex:	alteramac(3)	*/
+
+/* external extension */
+#define	CFG_NIOS_CPU_CS0_BASE	0x40000000	/* board EXT0	addr	*/
+#define	CFG_NIOS_CPU_CS0_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
+
+#define	CFG_NIOS_CPU_CS1_BASE	0x41000000	/* board EXT1	addr	*/
+#define	CFG_NIOS_CPU_CS1_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
+
+#define	CFG_NIOS_CPU_CS2_BASE	0x42000000	/* board EXT2	addr	*/
+#define	CFG_NIOS_CPU_CS2_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
+
+#define	CFG_NIOS_CPU_CS3_BASE	0x43000000	/* board EXT3	addr	*/
+#define	CFG_NIOS_CPU_CS3_SIZE	(16*1024*1024)	/*  max. 16 MB	size	*/
+
+/* symbolic redefinition (undef, if not present) */
+#define	CFG_NIOS_CPU_TICK_TIMER		0	/* TIMER0: tick (needed)*/
+#undef	CFG_NIOS_CPU_USER_TIMER			/* TIMERx: users choice	*/
+
+#define	CFG_NIOS_CPU_PORTA_PIO		0	/* PIO0: Port A		*/
+#define	CFG_NIOS_CPU_PORTB_PIO		1	/* PIO1: Port D		*/
+#define	CFG_NIOS_CPU_PORTC_PIO		2	/* PIO2: Port C		*/
+#define	CFG_NIOS_CPU_RCM_PIO		3	/* PIO3: RCM jumper	*/
+#define	CFG_NIOS_CPU_WDENA_PIO		4	/* PIO4: watchdog enable*/
+#define	CFG_NIOS_CPU_WDTOG_PIO		5	/* PIO5: watchdog trigg.*/
+
+/* PIOx: LED bar */
+#ifdef	CONFIG_DNPEVA2			/* DNP/EVA2 base board */
+#define	CFG_NIOS_CPU_LED_PIO		CFG_NIOS_CPU_PORTA_PIO
+#else
+#undef	CFG_NIOS_CPU_LED_PIO			/* no LED bar		*/
+#endif
+
+#endif	/* __CONFIG_ADNPESC1_BASE_32_H */
diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h
new file mode 100755
index 0000000..df20965
--- /dev/null
+++ b/include/configs/ADS860.h
@@ -0,0 +1,52 @@
+/*
+  * A collection of structures, addresses, and values associated with
+  * the Motorola 860 ADS board.	 Copied from the MBX stuff.
+  * Magnus Damm added defines for 8xxrom and extended bd_info.
+  * Helmut Buchsbaum added bitvalues for BCSRx
+  *
+  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+  *
+  * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
+  *
+  * Values common to all FADS family boards are in board/fads/fads.h
+  */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Board type */
+#define CONFIG_ADS		1	/* Old Motorola MPC821/860ADS */
+
+/* Processor type */
+#define CONFIG_MPC860		1
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1 */
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		38400	/* Console baudrate */
+
+#if 0
+#define CFG_8XX_FACT		1526	/* 32.768 kHz crystal on XTAL/EXTAL */
+#else
+#define CFG_8XX_FACT		12	/* 4 MHz oscillator on EXTCLK */
+#endif
+
+#define CFG_PLPRCR  (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+		PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+#define CONFIG_DRAM_50MHZ		1
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL   \
+			 | CFG_CMD_DHCP   \
+			 | CFG_CMD_IMMAP  \
+			 | CFG_CMD_PCMCIA \
+			 | CFG_CMD_PING   \
+			)
+
+
+#include "fads.h"
+
+#define CFG_PC_IDE_RESET	((ushort)0x0008)    /* PC 12	*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h
new file mode 100755
index 0000000..14d56bf
--- /dev/null
+++ b/include/configs/AMX860.h
@@ -0,0 +1,297 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1
+#define CONFIG_AMX860		1
+
+#undef	CONFIG_8xx_CONS_SMC1		/* Console is on SCC2		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#define	CONFIG_8xx_CONS_SCC2	1
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+
+#define MPC8XX_FACT		10		/* Multiply by 10	*/
+#define MPC8XX_XIN		5000000			/* 5 MHz in	*/
+#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_BOOTCOMMAND							\
+	"bootp;"								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm"				/* autoboot command */
+
+#undef CONFIG_BOOTARGS
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	1	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
+#endif
+
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_SCC1_ENET	1	/* use SCC1 ethernet */
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0200000	/* 1 ... 4 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR	 	0x00100000
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR			0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * U-Boot for AMX board supports two types of memory extension
+ * modules: one that provides 4 MB flash memory, and another one with
+ * 16 MB EDO DRAM.
+ *
+ * The flash module swaps the CS0 and CS1 signals: if the module is
+ * installed, CS0 is connected to Flash on the module and CS1 is
+ * connected to the on-board Flash. This means that you must intall
+ * U-Boot when the Flash module is plugged in, if you plan to use
+ * it.
+ *
+ * To enable support for the DRAM extension card, CONFIG_AMX_RAM_EXT
+ * must be defined. The DRAM module uses CS1.
+ *
+ * Only one of these modules may be installed at a time. If U-Boot
+ * is compiled with the CONFIG_AMX_RAM_EXT option set, it will not
+ * work if the Flash extension module is installed instead of the
+ * DRAM module.
+ */
+#define CONFIG_AMX_RAM_EXT	/* 16Mb Ext. DRAM module support */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ *
+ * Use 4 MB for without and 8 MB with 16 MB DRAM extension module
+ * (CONFIG_AMX_RAM_EXT)
+ */
+#ifdef CONFIG_AMX_RAM_EXT
+# define	CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
+#else
+# define	CFG_BOOTMAPSZ	(4 << 20)	/* Initial Memory map for Linux	*/
+#endif
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration					11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control (15-29)
+ */
+#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+
+#define CFG_DER		0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#ifndef CONFIG_AMX_RAM_EXT
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/
+#endif
+
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFFC00000	/* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
+/*				 0x00000800	0x00000400 0x00000100 0x00000030     0x00000004 */
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+
+#define CFG_OR0_PRELIM	0xFFC00954	/* Real values for the board */
+#define CFG_BR0_PRELIM	0x40000001	/* Real values for the board */
+
+#ifndef CONFIG_AMX_RAM_EXT
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	0xFFC00954	/* Real values for the board */
+#define CFG_BR1_PRELIM	0x60000001	/* Real values for the board */
+#endif
+
+/* DSP ("Glue") Xilinx */
+#define CFG_OR6_PRELIM	0xFFFF8000	/* 32kB, 15 waits, cs after addr, no bursts */
+#define CFG_BR6_PRELIM	0x60000401	/* use GPCM for CS generation, 8 bit port */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h
new file mode 100755
index 0000000..ba4b1a2
--- /dev/null
+++ b/include/configs/AP1000.h
@@ -0,0 +1,249 @@
+/*
+ * AMIRIX.h: AMIRIX specific config options
+ *
+ * Author : Frank Smith (smith at amirix dot com)
+ *
+ * Derived from : other configuration header files in this tree
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#undef DEBUG
+
+#define CONFIG_405	1		/* This is a PPC405 CPU	    */
+#define CONFIG_4xx	1		/* ...member of PPC4xx family	*/
+
+#define CONFIG_AP1000	1		/* ...on an AP1000 board    */
+
+#define CONFIG_PCI	1
+
+#define CFG_HUSH_PARSER 1		/* use "hush" command parser	*/
+#define CFG_PROMPT		"0> "
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#define CONFIG_COMMAND_EDIT	1
+#define CONFIG_COMMAND_HISTORY	1
+#define CONFIG_COMPLETE_ADDRESSES 1
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_FLASH_USE_BUFFER_WRITE
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#else
+#ifdef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_NVRAM
+#endif
+#endif
+
+#define CONFIG_BAUDRATE		57600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
+
+#define CONFIG_BOOTCOMMAND	""	/* autoboot command */
+
+/* Size (bytes) of interrupt driven serial port buffer.
+ * Set to 0 to use polling instead of interrupts.
+ * Setting to 0 will also disable RTS/CTS handshaking.
+ */
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+
+#define CONFIG_BOOTARGS		"console=ttyS0,57600"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MVENV	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	\
+			       )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled	    */
+
+#define CONFIG_SYS_CLK_FREQ	30000000
+
+#define CONFIG_SPD_EEPROM	1	/* use SPD EEPROM for setup    */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+/* usually: (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) */
+#define CFG_PBSIZE	(CFG_CBSIZE+4+16)	/* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_ALT_MEMTEST		1
+#define CFG_MEMTEST_START	0x00400000	/* memtest works on */
+#define CFG_MEMTEST_END		0x01000000	/* 4 ... 16 MB in DRAM	*/
+
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef	CFG_EXT_SERIAL_CLOCK		/* external serial clock */
+#undef	CFG_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
+
+#define CFG_NS16550_CLK		40000000
+#define CFG_DUART_CHAN		0
+#define CFG_NS16550_COM1	(0x4C000000 + 0x1000)
+#define CFG_NS16550_COM2	(0x4C800000 + 0x1000)
+#define CFG_NS16550_REG_SIZE	4
+#define CFG_NS16550		1
+#define CFG_INIT_CHAN1		1
+#define CFG_INIT_CHAN2		0
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CFG_LOAD_ADDR		0x00200000	/* default load address */
+#define CFG_EXTBDINFO		1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x20000000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI		1
+#define CFG_PROGFLASH_BASE	CFG_FLASH_BASE
+#define CFG_CONFFLASH_BASE	0x24000000
+
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	    */
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_PROTECTION	1	/* use hardware protection	    */
+
+/* BEG ENVIRONNEMENT FLASH */
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_OFFSET		0x00040000 /* Offset of Environment Sector	*/
+#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE	0x20000 /* see README - env sector total size	*/
+#endif
+/* END ENVIRONNEMENT FLASH */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars */
+#define CFG_ENV_ADDR	    \
+    (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value    */
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR	0xF0000500
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+#define CFG_INIT_RAM_ADDR	0x400000  /* inside of SDRAM			 */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS	0x50
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/* JFFS2 stuff */
+
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	1
+#define CFG_JFFS2_FIRST_SECTOR	1
+
+#define CONFIG_NET_MULTI
+#define CONFIG_E1000
+
+#define CFG_ETH_DEV_FN		0x0800
+#define CFG_ETH_IOBASE		0x31000000
+#define CFG_ETH_MEMBASE		0x32000000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
new file mode 100755
index 0000000..3df99a0
--- /dev/null
+++ b/include/configs/APC405.h
@@ -0,0 +1,387 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_APCG405		1	/* ...on a APC405 board 	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+
+#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_RAMBOOTCOMMAND							\
+	"setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm ffc00000 ffca0000"
+#define CONFIG_NFSBOOTCOMMAND							\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm ffc00000"
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_EEPROM  )
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address         */
+
+#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+
+#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#if 1 /* test-only */
+#define CFG_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */
+#else
+#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
+#define CFG_BASE_BAUD       691200
+#endif
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE      \
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/* Only interrupt boot if space is pressed */
+/* If a long serial cable is connected but */
+/* other end is dead, garbage will be read */
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
+#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define	CFG_ATA_BASE_ADDR	0xF0100000
+#define	CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MONITOR_BASE	0xFFF80000
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(2*1024*1024)	/* Reserve 2MB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#undef CFG_FLASH_PROTECTION		/* don't use hardware protection	*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_BASE		0xFE000000 /* test-only...*/
+#define CFG_FLASH_INCREMENT	0x01000000 /* test-only */
+
+#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+
+#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242		        /* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last	4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's   */
+					/* have only 8kB, 16kB is save here     */
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+#define FLASH0_BA       0xFF000000          /* FLASH 0 Base Address             */
+#define FLASH1_BA       0xFE000000          /* FLASH 1 Base Address             */
+#define CAN_BA          0xF0000000          /* CAN Base Address                 */
+#define DUART0_BA       0xF0000400          /* DUART Base Address               */
+#define DUART1_BA       0xF0000408          /* DUART Base Address               */
+#define RTC_BA          0xF0000500          /* RTC Base Address                 */
+#define PS2_BA          0xF0000600          /* PS/2 Base Address                */
+#define CF_BA           0xF0100000          /* CompactFlash Base Address        */
+#define FPGA_BA         0xF0100100          /* FPGA internal Base Address       */
+#define FUJI_BA         0xF0100200          /* Fuji internal Base Address       */
+#define PCMCIA1_BA      0x20000000          /* PCMCIA Slot 1 Base Address       */
+#define PCMCIA2_BA      0x28000000          /* PCMCIA Slot 2 Base Address       */
+#define VGA_BA          0xF1000000          /* Epson VGA Base Address           */
+
+#define CFG_FPGA_BASE_ADDR      FPGA_BA     /* FPGA internal Base Address       */
+
+/* Memory Bank 0 (Flash Bank 0) initialization                                  */
+#define CFG_EBC_PB0AP   0x92015480
+#define CFG_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 1 (Flash Bank 1) initialization                                  */
+#define CFG_EBC_PB1AP   0x92015480
+#define CFG_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization                           */
+#define CFG_EBC_PB2AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization               */
+#define CFG_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (PCMCIA Slot 1) initialization                                 */
+#define CFG_EBC_PB4AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB4CR   PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 5 (Epson VGA) initialization                                     */
+#define CFG_EBC_PB5AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
+#define CFG_EBC_PB5CR   VGA_BA | 0x5A000    /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 6 (PCMCIA Slot 2) initialization                                 */
+#define CFG_EBC_PB6AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB6CR   PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+
+/* FPGA internal regs */
+#define CFG_FPGA_CTRL           0x008
+#define CFG_FPGA_CTRL2          0x00a
+
+/* FPGA Control Reg */
+#define CFG_FPGA_CTRL_CF_RESET  0x0001
+#define CFG_FPGA_CTRL_WDI       0x0002
+#define CFG_FPGA_CTRL_PS2_RESET 0x0020
+
+#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE       80*1024     /* 80kByte is enough for XC2S50  */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * LCD Setup
+ */
+
+#define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
+#define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
+
+#define CONFIG_LCD_BIG          2           /* Epson S1D13806 used              */
+
+/* Image information... */
+#define CONFIG_LCD_USED         CONFIG_LCD_BIG
+#define CFG_LCD_HEADER_NAME     "../common/s1d13806_640_480_16bpp.h"
+#define CFG_LCD_LOGO_NAME       "logo_640_480_24bpp.c"
+
+#define CFG_LCD_MEM             CFG_LCD_BIG_MEM
+#define CFG_LCD_REG             CFG_LCD_BIG_REG
+
+#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/AR405.h b/include/configs/AR405.h
new file mode 100755
index 0000000..1cd0280
--- /dev/null
+++ b/include/configs/AR405.h
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_AR405		1	/* ...on a AR405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#if 1
+#define CONFIG_BOOTCOMMAND	"bootm fff00000" /* autoboot command	*/
+#else
+#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
+#endif
+
+#if 0
+#define CONFIG_BOOTARGS		"root=/dev/nfs "			\
+    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 "	\
+    "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
+#else
+#define CONFIG_BOOTARGS		"root=/dev/hda1 "			\
+    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
+
+#endif
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_BSP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0403	/* PCI Device ID: ARISTO405	*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xfff00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xfff00001	/* 1MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0xFFFB0000	/* Address of Environment Sector*/
+#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
+#define CFG_ENV_SIZE		0x04000	        /* Size of Environment 	        */
+
+#define CFG_ENV_ADDR_REDUND     0xFFFA0000
+#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (CAN0, 1, 2, 3) initialization					*/
+#define CFG_EBC_PB1AP		0x01000380  /* enable Ready, BEM=0		*/
+#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (Expension Bus) initialization					*/
+#define CFG_EBC_PB2AP		0x01000280  /* disable Ready, BEM=0		*/
+#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (16552) initialization						*/
+#define CFG_EBC_PB3AP		0x01000380  /* enable Ready, BEM=0		*/
+#define CFG_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 4 (FPGA regs) initialization					*/
+#define CFG_EBC_PB4AP		0x01005380  /* enable Ready, BEM=0		*/
+#define CFG_EBC_PB4CR		0xF031C000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
+
+/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization				*/
+#define CFG_EBC_PB5AP		0x92015480
+#define CFG_EBC_PB5CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h
new file mode 100755
index 0000000..9841893
--- /dev/null
+++ b/include/configs/ASH405.h
@@ -0,0 +1,387 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_ASH405		1	/* ...on a ASH405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33333300 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_EEPROM	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
+
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+#define CONFIG_MTD_NAND_VERIFY_WRITE 1  /* verify all writes!!!         */
+#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
+#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
+#define DUART2_BA	0xF0000410	    /* DUART Base Address		*/
+#define DUART3_BA	0xF0000418	    /* DUART Base Address		*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
+#define CFG_NAND_BASE	0xF4000000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+#define CFG_GPIO0_ISR1L		0x15555445
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FE0014
+
+#define CFG_DUART_RST		(0x80000000 >> 14)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/Adder.h b/include/configs/Adder.h
new file mode 100755
index 0000000..f807546
--- /dev/null
+++ b/include/configs/Adder.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Analogue&Micro Adder boards family.
+ * Tested on AdderII and Adder87x.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
+#define CONFIG_MPC875
+#endif
+
+#define CONFIG_ADDER				/* Analogue&Micro Adder board	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1		/* Console is on SMC1		*/
+#define CONFIG_BAUDRATE		38400
+
+#define	CONFIG_FEC_ENET				/* Ethernet is on FEC		*/
+#ifdef  CONFIG_FEC_ENET
+#define CFG_DISCOVER_PHY
+#define FEC_ENET
+#endif /* CONFIG_FEC_ENET */
+
+#define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK */
+#define CONFIG_8xx_CPUCLK_DEFAULT	50000000
+#define CFG_8xx_CPUCLK_MIN		40000000
+#ifdef CONFIG_MPC852T
+#define CFG_8xx_CPUCLK_MAX		50000000
+#else
+#define CFG_8xx_CPUCLK_MAX		120000000
+#endif /* CONFIG_MPC852T */
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL  \
+				| CFG_CMD_DHCP   \
+				| CFG_CMD_IMMAP  \
+				| CFG_CMD_MII    \
+				| CFG_CMD_PING   \
+				)
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5		/* Autoboot after 5 seconds	*/
+#define CONFIG_BOOTCOMMAND	"bootm fe040000"	/* Autoboot command	*/
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rw"
+
+#define CONFIG_BZIP2		/* Include support for bzip2 compressed images  */
+#undef	CONFIG_WATCHDOG		/* Disable platform specific watchdog		*/
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_LONGHELP				/* #undef to save memory	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)  /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* Max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* Default load address		*/
+
+#define CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * RAM configuration (note that CFG_SDRAM_BASE must be zero)
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_SIZE		0x00800000	/* 8 Mbyte			*/
+
+#define CFG_OR1_PRELIM  	(0xFF800000 | OR_CSNT_SAM | OR_ACS_DIV2)
+#define CFG_BR1_PRELIM  	(CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V)
+
+#define CFG_MAMR		0x00802114
+
+/*
+ * 2048	SDRAM rows
+ * 1000	factor s -> ms
+ * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4	Number of refresh cycles per period
+ * 64	Refresh cycle in ms per number of rows
+ */
+#define CFG_PTA_PER_CLK		((2048 * 64 * 1000) / (4 * 64))
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x00700000	/* 1 ... 7 MB in SDRAM		*/
+
+#define CFG_RESET_ADDRESS	0x09900000
+
+/*-----------------------------------------------------------------------
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 KB for Monitor   */
+#ifdef CONFIG_BZIP2
+#define CFG_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc() */
+#else
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
+#endif /* CONFIG_BZIP2 */
+
+/*-----------------------------------------------------------------------
+ * Flash organisation
+ */
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
+#define CFG_MAX_FLASH_BANKS	1		/* Max number of flash banks	*/
+#define CFG_MAX_FLASH_SECT	128		/* Max num of sects on one chip */
+
+/* Environment is in flash */
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000 	/* We use one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+
+#define CFG_OR0_PRELIM		0xFF000774
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
+
+#define	CFG_DIRECT_FLASH_TFTP
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Map Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128  /* Size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Configuration registers
+ */
+#ifdef CONFIG_WATCHDOG
+#define CFG_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
+				 SYPCR_SWF  | SYPCR_SWE | SYPCR_SWRI | \
+				 SYPCR_SWP)
+#else
+#define CFG_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
+				 SYPCR_SWF  | SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+#define CFG_SIUMCR		(SIUMCR_MLRC01 | SIUMCR_DBGC11)
+
+/* TBSCR - Time Base Status and Control Register */
+#define CFG_TBSCR		(TBSCR_TBF | TBSCR_TBE)
+
+/* PISCR - Periodic Interrupt Status and Control */
+#define CFG_PISCR       	(PISCR_PS | PISCR_PITF)
+
+/* PLPRCR - PLL, Low-Power, and Reset Control Register */
+/* #define CFG_PLPRCR      	PLPRCR_TEXPS */
+
+/* SCCR - System Clock and reset Control Register */
+#define SCCR_MASK       	SCCR_EBDF11
+#define CFG_SCCR		SCCR_RTSEL
+
+#define CFG_DER         	0
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx chips			*/
+
+/*-----------------------------------------------------------------------
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from flash	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h
new file mode 100755
index 0000000..c08b2c3
--- /dev/null
+++ b/include/configs/Alaska8220.h
@@ -0,0 +1,326 @@
+/*
+ * (C) Copyright 2004
+ * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC8220		1
+#define CONFIG_ALASKA8220	1	/* ... on Alaska board	*/
+
+/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
+   determine the CPU speed. */
+#define CFG_MPC8220_CLKIN	30000000/* ... running at 30MHz */
+#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	*/
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5   /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+
+/* Define this for PSC console
+#define CONFIG_PSC_CONSOLE	1
+*/
+
+#define CONFIG_EXTUART_CONSOLE	1
+
+#ifdef CONFIG_EXTUART_CONSOLE
+#   define CONFIG_CONS_INDEX	1
+#   define CFG_NS16550_SERIAL
+#   define CFG_NS16550
+#   define CFG_NS16550_REG_SIZE 1
+#   define CFG_NS16550_COM1	(CFG_CPLD_BASE + 0x1008)
+#   define CFG_NS16550_CLK	18432000
+#endif
+
+#define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_TIMESTAMP			/* Print image info with timestamp */
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BOOTD	| \
+				CFG_CMD_CACHE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO | \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_SNTP	)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_MII
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5    /* autoboot after 5 seconds */
+#define CONFIG_BOOTARGS		"root=/dev/ram rw"
+#define CONFIG_ETHADDR		00:e0:0c:bc:e0:60
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:e0:0c:bc:e0:61
+#define CONFIG_IPADDR		192.162.1.2
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP		192.162.1.1
+#define CONFIG_GATEWAYIP	192.162.1.1
+#define CONFIG_HOSTNAME		Alaska
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1
+#define CFG_I2C_MODULE		1
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x52	/* 1011000xb */
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+/*
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_ENV_OFFSET		0
+#define CFG_ENV_SIZE		256
+*/
+
+/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
+   else undefined it will boot from Intel Strata flash */
+#define CFG_AMD_BOOT		1
+
+/*
+ * Flexbus Chipselect configuration
+ */
+#if defined (CFG_AMD_BOOT)
+#define CFG_CS0_BASE		0xfff0
+#define CFG_CS0_MASK		0x00080000  /* 512 KB */
+#define CFG_CS0_CTRL		0x003f0d40
+
+#define CFG_CS1_BASE		0xfe00
+#define CFG_CS1_MASK		0x01000000  /* 16 MB */
+#define CFG_CS1_CTRL		0x003f1540
+#else
+#define CFG_CS0_BASE		0xff00
+#define CFG_CS0_MASK		0x01000000  /* 16 MB */
+#define CFG_CS0_CTRL		0x003f1540
+
+#define CFG_CS1_BASE		0xfe08
+#define CFG_CS1_MASK		0x00080000  /* 512 KB */
+#define CFG_CS1_CTRL		0x003f0d40
+#endif
+
+#define CFG_CS2_BASE		0xf100
+#define CFG_CS2_MASK		0x00040000
+#define CFG_CS2_CTRL		0x003f1140
+
+#define CFG_CS3_BASE		0xf200
+#define CFG_CS3_MASK		0x00040000
+#define CFG_CS3_CTRL		0x003f1100
+
+
+#define CFG_FLASH0_BASE		(CFG_CS0_BASE << 16)
+#define CFG_FLASH1_BASE		(CFG_CS1_BASE << 16)
+
+#if defined (CFG_AMD_BOOT)
+#define CFG_AMD_BASE		CFG_FLASH0_BASE
+#define CFG_INTEL_BASE		CFG_FLASH1_BASE + 0xf00000
+#define CFG_FLASH_BASE		CFG_AMD_BASE
+#else
+#define CFG_INTEL_BASE		CFG_FLASH0_BASE + 0xf00000
+#define CFG_AMD_BASE		CFG_FLASH1_BASE
+#define CFG_FLASH_BASE		CFG_INTEL_BASE
+#endif
+
+#define CFG_CPLD_BASE		(CFG_CS2_BASE << 16)
+#define CFG_FPGA_BASE		(CFG_CS3_BASE << 16)
+
+
+#define CFG_MAX_FLASH_BANKS	4	/* max num of memory banks	*/
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+
+#define PHYS_AMD_SECT_SIZE	0x00010000 /*  64 KB sectors (x2) */
+#define PHYS_INTEL_SECT_SIZE	0x00020000 /* 128 KB sectors (x2) */
+
+#define CFG_FLASH_CHECKSUM
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#if defined (CFG_AMD_BOOT)
+#define CFG_ENV_ADDR		(CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
+#define CFG_ENV_SIZE		PHYS_AMD_SECT_SIZE
+#define CFG_ENV_SECT_SIZE	PHYS_AMD_SECT_SIZE
+#define CFG_ENV1_ADDR		(CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
+#define CFG_ENV1_SIZE		PHYS_INTEL_SECT_SIZE
+#define CFG_ENV1_SECT_SIZE	PHYS_INTEL_SECT_SIZE
+#else
+#define CFG_ENV_ADDR		(CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
+#define CFG_ENV_SIZE		PHYS_INTEL_SECT_SIZE
+#define CFG_ENV_SECT_SIZE	PHYS_INTEL_SECT_SIZE
+#define CFG_ENV1_ADDR		(CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
+#define CFG_ENV1_SIZE		PHYS_AMD_SECT_SIZE
+#define CFG_ENV1_SECT_SIZE	PHYS_AMD_SECT_SIZE
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+#if defined CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_EEPROM
+#elif defined CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_EEPROM
+#elif defined CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#endif
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+#define CFG_SRAM_BASE		(CFG_MBAR + 0x20000)
+#define CFG_SRAM_SIZE		0x8000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	(CFG_MBAR + 0x20000)
+#define CFG_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
+#define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
+
+/* SDRAM configuration */
+#define CFG_SDRAM_TOTAL_BANKS		2
+#define CFG_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
+#define CFG_SDRAM_SPD_SIZE		0x40
+#define CFG_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */
+
+/* SDRAM drive strength register */
+#define CFG_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
+					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
+					 (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
+					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBD_SHIFT))
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC8220_FEC	1
+#define CONFIG_FEC_10MBIT	1 /* Workaround for FEC 100Mbit problem */
+#define CONFIG_PHY_ADDR		0x18
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			    /* undef to save memory	*/
+#define CFG_PROMPT		"=> "	    /* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	    /* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	    /* max number of command args   */
+#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START	0x00100000  /* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
+
+#define CFG_LOAD_ADDR		0x100000    /* default load address */
+
+#define CFG_HZ			1000	    /* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+
+/*
+ * JFFS2 partitions
+ */
+
+/* No command line, one static partition */
+/*
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0x00400000
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+*/
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=alaska-0"
+#define MTDPARTS_DEFAULT	"mtdparts=alaska-0:4m(user)"
+*/
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h
new file mode 100755
index 0000000..ea50f41
--- /dev/null
+++ b/include/configs/AmigaOneG3SE.h
@@ -0,0 +1,397 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * Configuration settings for the AmigaOneG3SE board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_AMIGAONEG3SE	1
+
+#define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_MISC_INIT_R	1
+
+#define CONFIG_VERY_BIG_RAM	1
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passed to Linux in Hz */
+
+#define CONFIG_BOOTARGS		"root=/dev/ram rw ramdisk=4096"
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_AMIGA_PARTITION
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
+				 CFG_CMD_ASKENV | \
+				 CFG_CMD_BSP	| \
+				 CFG_CMD_DATE	| \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_ELF	| \
+				 CFG_CMD_NET	| \
+				 CFG_CMD_IDE	| \
+				 CFG_CMD_FDC	| \
+				 CFG_CMD_CACHE	| \
+				 CFG_CMD_CONSOLE| \
+				 CFG_CMD_USB	| \
+				 CFG_CMD_BSP	| \
+				 CFG_CMD_PCI	)
+
+/*				    CFG_CMD_MII	   | \ */
+
+#define CONFIG_PCI		1
+/* #define CONFIG_PCI_SCAN_SHOW 1 */
+#define CONFIG_PCI_PNP		1	/* PCI plug-and-play */
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"] "		/* Monitor Command Prompt	*/
+
+#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+/* #undef CFG_HUSH_PARSER */
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+
+/* Print Buffer Size
+ */
+#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+#define CFG_MAXARGS	64		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x00500000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE	    0x00000000
+#define CFG_FLASH_BASE	    0xFFF00000
+#define CFG_FLASH_MAX_SIZE  0x00080000
+/* Maximum amount of RAM.
+ */
+#define CFG_MAX_RAM_SIZE    0x80000000	/* 2G			*/
+
+#define CFG_RESET_ADDRESS   0xFFF00100
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+
+#define CFG_MONITOR_LEN	    (768 << 10) /* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN	    (2500 << 10) /* Reserve 128 kB for malloc() */
+
+#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
+    CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM	*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+/* Size in bytes reserved for initial data
+ */
+/* HJF: used to be 0x400000 */
+#define CFG_INIT_RAM_ADDR	0x40000000
+#define CFG_INIT_RAM_END	0x8000
+#define CFG_GBL_DATA_SIZE	128
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_INIT_RAM_LOCK
+
+/*
+ * Temporary buffer for serial data until the real serial driver
+ * is initialised (memtest will destroy this buffer)
+ */
+#define CFG_SCONSOLE_ADDR     CFG_INIT_RAM_ADDR
+#define CFG_SCONSOLE_SIZE     0x0002000
+
+/* SDRAM 0 - 256MB
+ */
+
+/*HJF: #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT0U CFG_IBAT0U*/
+
+#define CFG_DBAT0L	      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U	      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+/* PCI Range
+ */
+#define CFG_DBAT1L	 (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT1U	 (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT1L	 (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U	 (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+/* HJF:
+#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW)
+#define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW )
+#define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP)
+*/
+
+/* Init RAM in the CPU DCache (no backing memory)
+ */
+#define CFG_DBAT2L	(CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_DBAT2U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+/* This used to be commented out */
+#define CFG_IBAT2L	  CFG_DBAT2L
+/* This here too */
+#define CFG_IBAT2U	  CFG_DBAT2U
+
+
+/* I/O and PCI memory at 0xf0000000
+ */
+#define CFG_DBAT3L	(0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U	(0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L	(0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	(0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ */
+#define CFG_HZ		1000
+#define CFG_BUS_HZ	133000000 /* bus speed - 100 mhz		*/
+#define CFG_CPU_CLK	133000000
+#define CFG_BUS_CLK	133000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CFG_MAX_FLASH_SECT	8	/* Max number of sectors in one bank	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+/*
+ * Environment is stored in NVRAM.
+ */
+#define CFG_ENV_IS_IN_NVRAM	1
+#define CFG_ENV_ADDR		0xFD0E0000 /* This should be 0xFD0E0000, but we skip bytes to
+					    * protect softex's settings for now.
+					    * Original 768 bytes where not enough.
+					    */
+#define CFG_ENV_SIZE		0x8000	   /* Size of the Environment. See comment above */
+
+#define CFG_CONSOLE_IS_IN_ENV	1 /* stdin/stdout/stderr are in environment */
+#define CFG_CONSOLE_OVERWRITE_ROUTINE	1
+#define CONFIG_ENV_OVERWRITE 1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * L2 cache
+ */
+#define CFG_L2
+#define L2_INIT	  (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+		   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#define L2_ENABLE (L2_INIT | L2CR_L2E)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+
+/*-----------------------------------------------------------------------
+ * IDE ATAPI Configuration
+ */
+
+#define CONFIG_ATAPI		1
+#define CFG_IDE_MAXBUS		2
+#define CFG_IDE_MAXDEVICE	4
+#define CONFIG_ISO_PARTITION	1
+
+#define CFG_ATA_BASE_ADDR	0xFE000000  /* was: via_get_base_addr() */
+#define CFG_ATA_IDE0_OFFSET	0x1F0
+#define CFG_ATA_IDE1_OFFSET	0x170
+
+#define CFG_ATA_REG_OFFSET	0
+#define CFG_ATA_DATA_OFFSET	0
+#define CFG_ATA_ALT_OFFSET	0x0200
+
+/*-----------------------------------------------------------------------
+ * Disk-On-Chip configuration
+ */
+
+#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+
+#define CFG_DOC_SUPPORT_2000
+#undef CFG_DOC_SUPPORT_MILLENNIUM
+
+/*-----------------------------------------------------------------------
+  RTC
+*/
+#define CONFIG_RTC_MC146818
+
+/*-----------------------------------------------------------------------
+ * NS16550 Configuration
+ */
+
+#define CFG_NS16550
+
+#define CFG_NS16550_COM1 0xFE0003F8
+#define CFG_NS16550_COM2 0xFE0002F8
+
+#define CFG_NS16550_REG_SIZE 1
+
+/* base address for ISA I/O
+ */
+#define CFG_ISA_IO_BASE_ADDRESS 0xFE000000
+
+/* ISA Interrupt stuff (taken from JWL) */
+
+#define ISA_INT1_OCW1		0x21
+#define ISA_INT2_OCW1		0xA1
+#define ISA_INT1_OCW2		0x20
+#define ISA_INT2_OCW2		0xA0
+#define ISA_INT1_OCW3		0x20
+#define ISA_INT2_OCW3		0xA0
+
+#define ISA_INT1_ICW1		0x20
+#define ISA_INT2_ICW1		0xA0
+#define ISA_INT1_ICW2		0x21
+#define ISA_INT2_ICW2		0xA1
+#define ISA_INT1_ICW3		0x21
+#define ISA_INT2_ICW3		0xA1
+#define ISA_INT1_ICW4		0x21
+#define ISA_INT2_ICW4		0xA1
+
+
+/*
+ * misc
+ */
+
+#define CONFIG_NET_MULTI
+#define CFG_BOARD_ASM_INIT
+#define CONFIG_LAST_STAGE_INIT
+
+/* #define CONFIG_ETHADDR	00:09:D2:10:00:76 */
+/* #define CONFIG_IPADDR	192.168.0.2 */
+/* #define CONFIG_NETMASK	255.255.255.240 */
+/* #define CONFIG_GATEWAYIP	192.168.0.3 */
+
+#define CONFIG_3COM
+/* #define CONFIG_BOOTP_RANDOM_DELAY */
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE)
+
+/*
+ * USB configuration
+ */
+#define CONFIG_USB_UHCI		1
+#define CONFIG_USB_STORAGE	1
+#define CONFIG_USB_KEYBOARD	1
+#define CFG_DEVICE_DEREGISTER	1 /* needed by CONFIG_USB_KEYBOARD */
+
+/*
+ * Autoboot stuff
+ */
+#define CONFIG_BOOTDELAY	5 /* Boot automatically after five seconds */
+#define CONFIG_PREBOOT		""
+#define CONFIG_BOOTCOMMAND	"fdcboot; diskboot"
+#define CONFIG_MENUPROMPT	"Press any key to interrupt autoboot: %2d "
+#define CONFIG_MENUKEY		' '
+#define CONFIG_MENUCOMMAND	"menu"
+/* #define CONFIG_AUTOBOOT_KEYED */
+
+/*
+ * Extra ENV stuff
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"stdout=vga\0"				\
+	"stdin=ps2kbd\0"			\
+	"ide_doreset=on\0"			\
+	"ide_maxbus=2\0"			\
+	"ide_cd_timeout=30\0"			\
+	"menucmd=menu\0"			\
+	"pci_irqa=9\0"				\
+	"pci_irqa_select=edge\0"		\
+	"pci_irqb=10\0"				\
+	"pci_irqb_select=edge\0"		\
+	"pci_irqc=11\0"				\
+	"pci_irqc_select=edge\0"		\
+	"pci_irqd=7\0"				\
+	"pci_irqd_select=edge\0"
+
+
+/* #define CONFIG_MII		1 */
+/* #define CONFIG_BITBANGMII	1 */
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/B2.h b/include/configs/B2.h
new file mode 100755
index 0000000..e55858d
--- /dev/null
+++ b/include/configs/B2.h
@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ *
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * Configuation settings for the B2 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7			1	/* This is a ARM7 CPU	*/
+#define CONFIG_B2			1	/* on an B2 Board      */
+#define CONFIG_ARM_THUMB	1	/* this is an ARM7TDMI */
+#undef  CONFIG_ARM7_REVD	 	/* disable ARM720 REV.D Workarounds */
+
+#define CONFIG_S3C44B0_CLOCK_SPEED	75 /* we have a 75Mhz S3C44B0*/
+
+
+#undef CONFIG_USE_IRQ			/* don't need them anymore */
+
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_ENV_SIZE		1024		/* 1024 bytes may be used for env vars*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024 )
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE		0x04000300 /* base address         */
+#define CONFIG_SMC_USE_32_BIT
+#undef  CONFIG_SHOW_ACTIVITY
+#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		1	/* we use Serial line 1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
+								CFG_CMD_DATE | \
+								CFG_CMD_ELF	| \
+								CFG_CMD_EEPROM	| \
+								CFG_CMD_I2C	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_ETHADDR	00:50:c2:1e:af:fb
+#define CONFIG_BOOTARGS  "setenv bootargs root=/dev/ram ip=192.168.0.70:::::eth0:off \
+							 ether=25,0,0,0,eth0 ethaddr=00:50:c2:1e:af:fb"
+#define CONFIG_NETMASK  255.255.0.0
+#define CONFIG_IPADDR   192.168.0.70
+#define CONFIG_SERVERIP	192.168.0.23
+#define CONFIG_BOOTFILE	"B2-rootfs/usr/B2-zImage.u-boot"
+#define CONFIG_BOOTCOMMAND	"bootm 20000 f0000"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"=>  "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0C400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x0c700000	/* default load address	*/
+
+#define	CFG_HZ				1000		/* 1 kHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks of DRAM */
+#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE		0x00400000 /* 4 MB */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x0	/* environment starts at the beginning of the EEPROM */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (STM24C02W6) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0xFE
+
+#define CFG_I2C_EEPROM_ADDR	0xA8	/* EEPROM STM24C02W6		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/* Flash banks JFFS2 should use */
+/*
+#define CFG_JFFS2_FIRST_BANK    0
+#define CFG_JFFS2_FIRST_SECTOR	2
+#define CFG_JFFS2_NUM_BANKS     1
+*/
+
+/*
+	Linux TAGs (see lib_arm/armlinux.c)
+*/
+#define CONFIG_CMDLINE_TAG
+#undef CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h
new file mode 100755
index 0000000..46bdfa2
--- /dev/null
+++ b/include/configs/BAB7xx.h
@@ -0,0 +1,467 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef  DEBUG
+#define GTREGREAD(x) 0xffffffff         /* needed for debug */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* these hardware addresses are pretty bogus, please change them to
+   suit your needs */
+
+/* first ethernet */
+#define CONFIG_ETHADDR          00:00:5b:ee:de:ad
+
+#define CONFIG_IPADDR           192.168.0.105
+#define CONFIG_SERVERIP         192.168.0.100
+
+#define CONFIG_BAB7xx           1       /* this is an BAB740/BAB750 board */
+
+#define CONFIG_BAUDRATE         9600    /* console baudrate */
+
+#undef  CONFIG_WATCHDOG
+
+#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#undef  CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND                                  \
+    "bootp 1000000; "                                       \
+    "setenv bootargs root=ramfs console=ttyS00,9600 "       \
+    "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:"    \
+    "${netmask}:${hostname}:eth0:none; "                    \
+    "bootm"
+
+#define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
+#define CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes */
+
+#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\
+				 CFG_CMD_SCSI   | CFG_CMD_IDE | CFG_CMD_DATE  |\
+				 CFG_CMD_FDC    | CFG_CMD_ELF)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                    /* undef to save memory */
+#define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
+
+/*
+ * choose between COM1 and COM2 as serial console
+ */
+#define CONFIG_CONS_INDEX       1
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE              1024        /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE              256         /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS             16          /* max number of command args    */
+#define CFG_BARGSIZE            CFG_CBSIZE  /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START       0x00000000  /* memtest works on    */
+#define CFG_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */
+
+#define CFG_LOAD_ADDR           0x1000000   /* default load address    */
+
+#define CFG_HZ                  1000        /* dec. freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define CFG_BOARD_ASM_INIT
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Choose the address mapping scheme for the MPC106 mem controller.
+ * Default is mapping B (CHRP), set this define to choose mapping A (PReP).
+ */
+#define CFG_ADDRESS_MAP_A
+#ifdef  CFG_ADDRESS_MAP_A
+
+#define CFG_PCI_MEMORY_BUS      0x80000000
+#define CFG_PCI_MEMORY_PHYS     0x00000000
+#define CFG_PCI_MEMORY_SIZE     0x80000000
+
+#define CFG_PCI_MEM_BUS         0x00000000
+#define CFG_PCI_MEM_PHYS        0xc0000000
+#define CFG_PCI_MEM_SIZE        0x3f000000
+
+#define CFG_ISA_MEM_BUS         0
+#define CFG_ISA_MEM_PHYS        0
+#define CFG_ISA_MEM_SIZE        0
+
+#define CFG_PCI_IO_BUS          0x1000
+#define CFG_PCI_IO_PHYS         0x81000000
+#define CFG_PCI_IO_SIZE         0x01000000-CFG_PCI_IO_BUS
+
+#define CFG_ISA_IO_BUS          0x00000000
+#define CFG_ISA_IO_PHYS         0x80000000
+#define CFG_ISA_IO_SIZE         0x00800000
+
+#else
+
+#define CFG_PCI_MEMORY_BUS      0x00000000
+#define CFG_PCI_MEMORY_PHYS     0x00000000
+#define CFG_PCI_MEMORY_SIZE     0x40000000
+
+#define CFG_PCI_MEM_BUS         0x80000000
+#define CFG_PCI_MEM_PHYS        0x80000000
+#define CFG_PCI_MEM_SIZE        0x7d000000
+
+#define CFG_ISA_MEM_BUS         0x00000000
+#define CFG_ISA_MEM_PHYS        0xfd000000
+#define CFG_ISA_MEM_SIZE        0x01000000
+
+#define CFG_PCI_IO_BUS          0x00800000
+#define CFG_PCI_IO_PHYS         0xfe800000
+#define CFG_PCI_IO_SIZE         0x00400000
+
+#define CFG_ISA_IO_BUS          0x00000000
+#define CFG_ISA_IO_PHYS         0xfe000000
+#define CFG_ISA_IO_SIZE         0x00800000
+
+#endif /*CFG_ADDRESS_MAP_A */
+
+#define CFG_60X_PCI_MEM_OFFSET  0x00000000
+
+/* driver defines FDC,IDE,... */
+#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
+#define CFG_ISA_IO              CFG_ISA_IO_PHYS
+#define CFG_60X_PCI_IO_OFFSET   CFG_ISA_IO_PHYS
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE          0x00000000
+#define CFG_FLASH_BASE          0xfff00000
+
+/*
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
+#define CFG_INIT_RAM_END        0x4000
+#define CFG_GBL_DATA_SIZE       64          /* size in bytes reserved for init data */
+#define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*
+ * Flash mapping/organization on the MPC10x.
+ */
+#define FLASH_BASE0_PRELIM      0xff800000
+#define FLASH_BASE1_PRELIM      0xffc00000
+
+#define CFG_MAX_FLASH_BANKS     2           /* max number of memory banks    */
+#define CFG_MAX_FLASH_SECT      67          /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support
+ *
+ * Note: fake mtd_id used, no linux mtd map file
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=bab7xx-0"
+#define MTDPARTS_DEFAULT	"mtdparts=bab7xx-0:-(jffs2)"
+*/
+
+#define CFG_MONITOR_BASE        CFG_FLASH_BASE
+#define CFG_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
+#undef  CFG_MEMTEST
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CFG_ENV_IS_IN_NVRAM     1           /* use NVRAM for environment vars */
+#define CFG_NVRAM_SIZE          0x1ff0      /* NVRAM size (8kB), we must protect the clock data (16 bytes) */
+#define CFG_ENV_SIZE            0x400       /* Size of Environment vars (1kB) */
+/*
+ * We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus,
+ * user applications can use the remaining space for other purposes.
+ */
+#define CFG_ENV_ADDR            (CFG_NVRAM_SIZE +0x10 -0x800)
+#define CFG_NV_SROM_COPY_ADDR   (CFG_NVRAM_SIZE +0x10 -0x400)
+#define CFG_NVRAM_ACCESS_ROUTINE            /* This board needs a special routine to access the NVRAM */
+#define CFG_SROM_SIZE           0x100       /* shadow of revision info is in nvram */
+
+/*
+ * Serial devices
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK         1843200
+#define CFG_NS16550_COM1        (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
+#define CFG_NS16550_COM2        (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
+
+/*
+ * PCI stuff
+ */
+#define CONFIG_PCI                                /* include pci support */
+#define CONFIG_PCI_PNP                            /* pci plug-and-play */
+#define CONFIG_PCI_HOST         PCI_HOST_AUTO
+#undef  CONFIG_PCI_SCAN_SHOW
+
+/*
+ * Video console (graphic: SMI LynxEM, keyboard: i8042)
+ */
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_I8042_KBD
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CONSOLE_TIME
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_CONSOLE_CURSOR
+#define CFG_CONSOLE_BLINK_COUNT         30000    /* approx. 2 HZ */
+
+/*
+ * IDE/SCSI globals
+ */
+#ifndef __ASSEMBLY__
+extern unsigned int    eltec_board;
+extern unsigned int    ata_reset_time;
+extern unsigned int    scsi_reset_time;
+extern unsigned short  scsi_dev_id;
+extern unsigned int    scsi_max_scsi_id;
+extern unsigned char   scsi_sym53c8xx_ccf;
+#endif
+
+/*
+ * ATAPI Support (experimental)
+ */
+#define CONFIG_ATAPI
+#define CFG_IDE_MAXBUS          1                       /* max. 2 IDE busses    */
+#define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2)      /* max. 2 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR       CFG_60X_PCI_IO_OFFSET   /* base address */
+#define CFG_ATA_IDE0_OFFSET     0x1F0                   /* default ide0 offste */
+#define CFG_ATA_IDE1_OFFSET     0x170                   /* default ide1 offset */
+#define CFG_ATA_DATA_OFFSET     0                       /* data reg offset    */
+#define CFG_ATA_REG_OFFSET      0                       /* reg offset */
+#define CFG_ATA_ALT_OFFSET      0x200                   /* alternate register offset */
+
+#define ATA_RESET_TIME          (ata_reset_time)
+
+#undef  CONFIG_IDE_PCMCIA                               /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                                  /* no led for ide supported */
+
+/*
+ * SCSI support (experimental) only SYM53C8xx supported
+ */
+#define CONFIG_SCSI_SYM53C8XX
+#define CONFIG_SCSI_DEV_ID      (scsi_dev_id)           /* 875 or 860 */
+#define CFG_SCSI_SYM53C8XX_CCF  (scsi_sym53c8xx_ccf)    /* value for none 40 mhz clocks */
+#define CFG_SCSI_MAX_LUN        8                       /* number of supported LUNs */
+#define CFG_SCSI_MAX_SCSI_ID    (scsi_max_scsi_id)      /* max SCSI ID (0-6) */
+#define CFG_SCSI_MAX_DEVICE     (15 * CFG_SCSI_MAX_LUN) /* max. Target devices */
+#define CFG_SCSI_SPIN_UP_TIME   (scsi_reset_time)
+
+/*
+ * Partion suppport
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * Winbond Configuration
+ */
+#define CFG_WINBOND_83C553      1                       /* has a winbond bridge */
+#define CFG_USE_WINBOND_IDE     0                       /* use winbond 83c553 internal ide */
+#define CFG_WINBOND_ISA_CFG_ADDR    0x80005800          /* pci-isa bridge config addr */
+#define CFG_WINBOND_IDE_CFG_ADDR    0x80005900          /* ide config addr */
+
+/*
+ * NS87308 Configuration
+ */
+#define CFG_NS87308                    /* Nat Semi super-io cntr on ISA bus */
+#define CFG_NS87308_BADDR_10    1
+#define CFG_NS87308_DEVS        (CFG_NS87308_UART1   | \
+				 CFG_NS87308_UART2   | \
+				 CFG_NS87308_KBC1    | \
+				 CFG_NS87308_MOUSE   | \
+				 CFG_NS87308_FDC     | \
+				 CFG_NS87308_RARP    | \
+				 CFG_NS87308_GPIO    | \
+				 CFG_NS87308_POWRMAN | \
+				 CFG_NS87308_RTC_APC )
+
+#define CFG_NS87308_PS2MOD
+#define CFG_NS87308_GPIO_BASE   0x0220
+#define CFG_NS87308_PWMAN_BASE  0x0460
+#define CFG_NS87308_PMC2        0x00        /* SuperI/O clock source is 24MHz via X1 */
+
+/*
+ * set up the NVRAM access registers
+ * NVRAM's controlled by the configurable CS line from the 87308
+ */
+#define CFG_NS87308_CS0_BASE    0x0076
+#define CFG_NS87308_CS0_CONF    0x40
+#define CFG_NS87308_CS1_BASE    0x0070
+#define CFG_NS87308_CS1_CONF    0x1C
+#define CFG_NS87308_CS2_BASE    0x0071
+#define CFG_NS87308_CS2_CONF    0x1C
+
+#define CONFIG_RTC_MK48T59
+
+/*
+ * Initial BATs
+ */
+#if 1
+
+#define CFG_IBAT0L 0
+#define CFG_IBAT0U 0
+#define CFG_DBAT0L CFG_IBAT1L
+#define CFG_DBAT0U CFG_IBAT1U
+
+#define CFG_IBAT1L 0
+#define CFG_IBAT1U 0
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+
+#define CFG_IBAT2L 0
+#define CFG_IBAT2U 0
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+
+#define CFG_IBAT3L 0
+#define CFG_IBAT3U 0
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+#else
+
+/* SDRAM */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L CFG_IBAT1L
+#define CFG_DBAT0U CFG_IBAT1U
+
+/* address range for flashes */
+#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+
+/* ISA IO space */
+#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+
+/* ISA memory space */
+#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+#endif
+
+/*
+ * Speed settings are board specific
+ */
+#ifndef __ASSEMBLY__
+extern  unsigned long           bab7xx_get_bus_freq (void);
+extern  unsigned long           bab7xx_get_gclk_freq (void);
+#endif
+#define CFG_BUS_HZ              bab7xx_get_bus_freq()
+#define CFG_BUS_CLK             CFG_BUS_HZ
+#define CFG_CPU_CLK             bab7xx_get_gclk_freq()
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */
+
+/*
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT        5    /* log base 2 of the above value */
+#endif
+
+/*
+ * L2 Cache Configuration is board specific for BAB740/BAB750
+ * Init values read from revision srom.
+ */
+#undef  CFG_L2
+#define L2_INIT     (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+		     L2CR_L2OH_5   | L2CR_L2CTL   | L2CR_L2WT)
+#define L2_ENABLE   (L2_INIT | L2CR_L2E)
+
+#define CFG_L2_BAB7xx
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM           0x02    /* Software reboot */
+
+
+#define CONFIG_NET_MULTI                /* Multi ethernet cards support */
+#define CONFIG_TULIP
+#define CONFIG_TULIP_SELECT_MEDIA
+
+#endif    /* __CONFIG_H */
diff --git a/include/configs/BMW.h b/include/configs/BMW.h
new file mode 100755
index 0000000..050054d
--- /dev/null
+++ b/include/configs/BMW.h
@@ -0,0 +1,305 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * Configuration settings for the CU824 board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8245		1
+#define CONFIG_BMW		1
+
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/
+
+#define CONFIG_BCM570x		1	/* Use Broadcom BCM570x Ethernet Driver */
+#define	CONFIG_TIGON3		1
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz	*/
+
+#define CONFIG_BOOTCOMMAND	"bootm FF820000"	/* autoboot command	*/
+#define CONFIG_BOOTDELAY	5
+
+#define CFG_MAX_DOC_DEVICE      1 /* Only use Onboard TSOP-16MB device */
+#define DOC_PASSIVE_PROBE       1
+#define CFG_DOC_SUPPORT_2000    1
+#define CFG_DOC_SUPPORT_MILLENNIUM 1
+#define CFG_DOC_SHORT_TIMEOUT    1
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DOC	| \
+				CFG_CMD_ELF	| \
+				0 )
+#if 0
+#define CONFIG_COMMANDS	        (CONFIG_CMD_DFL	| CFG_CMD_DHCP | \
+				 CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE)
+
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1	/* PCI plug-and-play */
+#endif
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=>"	        /* Monitor Command Prompt	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+/* Print Buffer Size
+ */
+#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+#define CFG_MAXARGS	8		/* Max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE	    0x00000000
+
+#define CFG_FLASH_BASE0_PRELIM      0xFFF00000      /* FLASH bank on RCS#0 */
+#define CFG_FLASH_BASE1_PRELIM      0xFF800000      /* FLASH bank on RCS#1 */
+#define CFG_FLASH_BASE  CFG_MONITOR_BASE
+#define CFG_FLASH_BANKS		{ CFG_FLASH_BASE0_PRELIM , CFG_FLASH_BASE1_PRELIM }
+
+/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
+ * reset vector is actually located at FFB00100, but the 8245
+ * takes care of us.
+ */
+#define CFG_RESET_ADDRESS   0xFFF00100
+
+#define CFG_EUMB_ADDR	    0xFC000000
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+
+#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN	    (2048 << 10) /* Reserve 2MB for malloc()	*/
+
+#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CFG_MEMTEST_END	    0x04000000	/* 0 ... 32 MB in DRAM		*/
+
+	/* Maximum amount of RAM.
+	 */
+#define CFG_MAX_RAM_SIZE    0x04000000	/* 0 .. 64 MB of (S)DRAM */
+
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN
+#define CFG_INIT_RAM_END   0x2F00  /* End of used area in DPRAM  */
+#define CFG_GBL_DATA_SIZE  128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET  CFG_GBL_DATA_OFFSET
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
+#define CFG_HZ		     1000
+
+#define CFG_ETH_DEV_FN	     0x7800
+#define CFG_ETH_IOBASE	     0x00104000
+
+	/* Bit-field values for MCCR1.
+	 */
+#define CFG_ROMNAL	    0xf
+#define CFG_ROMFAL	    0x1f
+#define CFG_DBUS_SIZE       0x3
+
+	/* Bit-field values for MCCR2.
+	 */
+#define CFG_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
+#define CFG_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
+
+	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+	 */
+#define CFG_BSTOPRE	    0		/* FIXME: was 192 */
+
+	/* Bit-field values for MCCR3.
+	 */
+#define CFG_REFREC	    2	    /* Refresh to activate interval */
+
+	/* Bit-field values for MCCR4.
+	 */
+#define CFG_PRETOACT	    2	    /* Precharge to activate interval FIXME: was 2	*/
+#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
+#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
+#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
+#define CFG_SDMODE_BURSTLEN 3	    /* SDMODE Burst length */
+#define CFG_ACTORW	    0xa		/* FIXME was 2 */
+#define CFG_REGISTERD_TYPE_BUFFER 1
+
+#define CFG_PGMAX           0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
+
+#define CFG_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CFG_BANK0_START	    0x00000000
+#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE    1
+#define CFG_BANK1_START	    0x3ff00000
+#define CFG_BANK1_END	    0x3fffffff
+#define CFG_BANK1_ENABLE    0
+#define CFG_BANK2_START	    0x3ff00000
+#define CFG_BANK2_END	    0x3fffffff
+#define CFG_BANK2_ENABLE    0
+#define CFG_BANK3_START	    0x3ff00000
+#define CFG_BANK3_END	    0x3fffffff
+#define CFG_BANK3_ENABLE    0
+#define CFG_BANK4_START	    0x3ff00000
+#define CFG_BANK4_END	    0x3fffffff
+#define CFG_BANK4_ENABLE    0
+#define CFG_BANK5_START	    0x3ff00000
+#define CFG_BANK5_END	    0x3fffffff
+#define CFG_BANK5_ENABLE    0
+#define CFG_BANK6_START	    0x3ff00000
+#define CFG_BANK6_END	    0x3fffffff
+#define CFG_BANK6_ENABLE    0
+#define CFG_BANK7_START	    0x3ff00000
+#define CFG_BANK7_END	    0x3fffffff
+#define CFG_BANK7_ENABLE    0
+
+#define CFG_ODCR	    0xff
+
+#define CONFIG_PCI              1 /* Include PCI support */
+#undef CONFIG_PCI_PNP
+
+/* PCI Memory space(s) */
+#define PCI_MEM_SPACE1_START	0x80000000
+#define PCI_MEM_SPACE2_START	0xfd000000
+
+/* ROM Spaces */
+#include "../board/bmw/bmw.h"
+
+/* BAT configuration */
+#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L  (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U  (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L  CFG_IBAT0L
+#define CFG_DBAT0U  CFG_IBAT0U
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+#define CFG_DBAT2L  CFG_IBAT2L
+#define CFG_DBAT2U  CFG_IBAT2U
+#define CFG_DBAT3L  CFG_IBAT3L
+#define CFG_DBAT3U  CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	0	/* Max number of flash banks	    */
+#define CFG_MAX_FLASH_SECT	64	/* Max number of sectors per  flash */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+/*
+ * Warining: environment is not EMBEDDED in the U-Boot code.
+ * It's stored in flash separately.
+ */
+#define CFG_ENV_IS_IN_NVRAM      1
+#define CONFIG_ENV_OVERWRITE     1
+#define CFG_NVRAM_ACCESS_ROUTINE 1
+#define CFG_ENV_ADDR		0x7c004000 /* right at the start of NVRAM  */
+#define CFG_ENV_SIZE		0x1ff0	/* Size of the Environment - 8K	   */
+#define CFG_ENV_OFFSET		0	/* starting right at the beginning */
+
+/*
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value   */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot		    */
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h
new file mode 100755
index 0000000..e0262a8
--- /dev/null
+++ b/include/configs/CANBT.h
@@ -0,0 +1,227 @@
+/*
+ * (C) Copyright 2001
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405CR		1	/* This is a PPC405CR CPU	*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_CANBT		1	/* ...on a CANBT board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw console=ttyS0,115200; "	\
+	"bootm ffe00000 ffe80000"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
+
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+
+#define CONFIG_COMMANDS	     (( CONFIG_CMD_DFL	|	\
+				CFG_CMD_IRQ	|	\
+				CFG_CMD_EEPROM	    ) & \
+			       ~CFG_CMD_NET)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFE0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* Use FLASH for environment variables */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
+#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
+
+#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
+
+#else /* Use EEPROM for environment variables */
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
+				   /* total size of a CAT24WC08 is 1024 bytes */
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (CAN/USB) initialization					*/
+#define CFG_EBC_PB1AP		0x010053C0  /* enable Ready, BEM=1		*/
+#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (Misc-IO/LEDs) initialization					*/
+#define CFG_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
+#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (CAN Features) initialization					*/
+#define CFG_EBC_PB3AP		0x80000040  /* no Ready, BEM=1			*/
+#define CFG_EBC_PB3CR		0xF021C000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in RAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x00ef0000 /* inside of SDRAM			*/
+#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
new file mode 100755
index 0000000..ffe89cb
--- /dev/null
+++ b/include/configs/CATcenter.h
@@ -0,0 +1,787 @@
+/*
+ * ueberarbeitet durch Christoph Seyfert
+ *
+ * (C) Copyright 2004-2005 DENX Software Engineering,
+ *     Wolfgang Grandegger <wg@denx.de>
+ * (C) Copyright 2003
+ *     DAVE Srl
+ *
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * Credits: Stefan Roese, Wolfgang Denk
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PPCHAMELEON_MODULE_BA	0	/* Basic    Model */
+#define CONFIG_PPCHAMELEON_MODULE_ME	1	/* Medium   Model */
+#define CONFIG_PPCHAMELEON_MODULE_HI	2	/* High-End Model */
+#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
+#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
+#endif
+
+/* Only one of the following two symbols must be defined (default is 25 MHz)
+ * CONFIG_PPCHAMELEON_CLK_25
+ * CONFIG_PPCHAMELEON_CLK_33
+ */
+#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
+#define CONFIG_PPCHAMELEON_CLK_25
+#endif
+
+#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
+#error "* Two external frequencies (SysClk) are defined! *"
+#endif
+
+#undef CONFIG_PPCHAMELEON_SMI712
+
+/*
+ * Debug stuff
+ */
+#undef	__DEBUG_START_FROM_SRAM__
+#define __DISABLE_MACHINE_EXCEPTION__
+
+#ifdef __DEBUG_START_FROM_SRAM__
+#define CFG_DUMMY_FLASH_SIZE		1024*1024*4
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_PPCHAMELEONEVB	1	/* ...on a PPChameleonEVB board */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#ifdef CONFIG_PPCHAMELEON_CLK_25
+# define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll   */
+#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
+#else
+# error "* External frequency (SysClk) not defined! *"
+#endif
+
+#define CONFIG_UART1_CONSOLE	1	/* Use second UART		*/
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_VERSION_VARIABLE	1	/* add version variable		*/
+#define CONFIG_IDENT_STRING	"1"
+
+#undef	CONFIG_BOOTARGS
+
+/* Ethernet stuff */
+#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
+#define CONFIG_ETHADDR	00:50:C2:1E:AF:FE
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+
+#undef CONFIG_EXT_PHY
+#define CONFIG_NET_MULTI	1
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#ifndef	 CONFIG_EXT_PHY
+#define CONFIG_PHY_ADDR		1	/* EMAC0 PHY address		*/
+#define CONFIG_PHY1_ADDR	16	/* EMAC1 PHY address		*/
+#else
+#define CONFIG_PHY_ADDR		2	/* PHY address			*/
+#endif
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#define	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK		/* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD		691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_NAND0_BASE 0xFF400000
+#define CFG_NAND1_BASE 0xFF000000
+
+/* For CATcenter there is only NAND on the module */
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+#define NAND_NO_RB
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
+#define CFG_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
+#define CFG_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
+#define CFG_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
+
+#define CFG_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
+#define CFG_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
+#define CFG_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
+#define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
+
+
+#define NAND_DISABLE_CE(nand) do \
+{ \
+	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
+		break; \
+	} \
+} while(0)
+
+#define NAND_ENABLE_CE(nand) do \
+{ \
+	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
+		break; \
+	} \
+} while(0)
+
+
+#define NAND_CTL_CLRALE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
+		break; \
+	} \
+} while(0)
+
+#define NAND_CTL_SETALE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
+		break; \
+	} \
+} while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
+		break; \
+	} \
+} while(0)
+
+#define NAND_CTL_SETCLE(nandptr) do { \
+	switch((unsigned long)nandptr) { \
+	case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
+		break; \
+	case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
+		break; \
+	} \
+} while(0)
+
+#ifdef NAND_NO_RB
+/* constant delay (see also tR in the datasheet) */
+#define NAND_WAIT_READY(nand) do { \
+	udelay(12); \
+} while (0)
+#else
+/* use the R/B pin */
+/* TBD */
+#endif
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#if 0	/* No PCI on CATcenter */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	 /* select pci host function	 */
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* PCI Vendor ID: IBM	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: ---	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#endif	/* No PCI */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define CFG_ENV_ADDR		0xFFFF8000	/* environment starts at the first small sector */
+#define CFG_ENV_SECT_SIZE	0x2000	/* 8196 bytes may be used for env vars*/
+#define CFG_ENV_ADDR_REDUND	0xFFFFA000
+#define CFG_ENV_SIZE_REDUND	0x2000
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (External SRAM) initialization					*/
+/* Since this must replace NOR Flash, we use the same settings for CS0		*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB2AP		0x92015480
+#define CFG_EBC_PB2CR		0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB3AP		0x92015480
+#define CFG_EBC_PB3CR		0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit	*/
+
+#ifdef CONFIG_PPCHAMELEON_SMI712
+/*
+ * Video console (graphic: SMI LynxEM)
+ */
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_VIDEO_BMP_LOGO*/
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
+#define CFG_ISA_IO 0xE8000000
+/* see also drivers/videomodes.c */
+#define CFG_DEFAULT_VIDEO_MODE 0x303
+#endif
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CFG_FPGA_MODE		0x00
+#define CFG_FPGA_STATUS		0x02
+#define CFG_FPGA_TS		0x04
+#define CFG_FPGA_TS_LOW		0x06
+#define CFG_FPGA_TS_CAP0	0x10
+#define CFG_FPGA_TS_CAP0_LOW	0x12
+#define CFG_FPGA_TS_CAP1	0x14
+#define CFG_FPGA_TS_CAP1_LOW	0x16
+#define CFG_FPGA_TS_CAP2	0x18
+#define CFG_FPGA_TS_CAP2_LOW	0x1a
+#define CFG_FPGA_TS_CAP3	0x1c
+#define CFG_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CFG_FPGA_MODE_CF_RESET	0x0001
+#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CFG_FPGA_MODE_TS_CLEAR	0x2000
+
+/* FPGA Status Reg */
+#define CFG_FPGA_STATUS_DIP0	0x0001
+#define CFG_FPGA_STATUS_DIP1	0x0002
+#define CFG_FPGA_STATUS_DIP2	0x0004
+#define CFG_FPGA_STATUS_FLASH	0x0008
+#define CFG_FPGA_STATUS_TS_IRQ	0x1000
+
+#define CFG_FPGA_SPARTAN2	1		/* using Xilinx Spartan 2 now	*/
+#define CFG_FPGA_MAX_SIZE	128*1024	/* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000	/* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000	/* FPGA clk pin (ppc output)	*/
+#define CFG_FPGA_DATA		0x01000000	/* FPGA data pin (ppc output)	*/
+#define CFG_FPGA_INIT		0x00010000	/* FPGA init pin (ppc input)	*/
+#define CFG_FPGA_DONE		0x00008000	/* FPGA done pin (ppc input)	*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30]	- EMAC0 input
+ * GPIO0[31]	- EMAC1 reject packet as output
+ */
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+/*#define CFG_GPIO0_ISR1L	0x15555445*/
+#define CFG_GPIO0_ISR1L		0x15555444
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FF8014
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+
+#define CONFIG_NO_SERIAL_EEPROM
+
+/*--------------------------------------------------------------------*/
+
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*
+!-----------------------------------------------------------------------
+! Defines for entry options.
+! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
+!	are plugged in the board will be utilized as non-ECC DIMMs.
+!-----------------------------------------------------------------------
+*/
+#undef		AUTO_MEMORY_CONFIG
+#define		DIMM_READ_ADDR 0xAB
+#define		DIMM_WRITE_ADDR 0xAA
+
+#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register		*/
+#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register	*/
+#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register		*/
+#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register	*/
+#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register		*/
+#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register		*/
+#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register		*/
+#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register			*/
+#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR				*/
+#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register		*/
+
+/* Defines for CPC0_PLLMR1 Register fields */
+#define PLL_ACTIVE		0x80000000
+#define CPC0_PLLMR1_SSCS	0x80000000
+#define PLL_RESET		0x40000000
+#define CPC0_PLLMR1_PLLR	0x40000000
+    /* Feedback multiplier */
+#define PLL_FBKDIV		0x00F00000
+#define CPC0_PLLMR1_FBDV	0x00F00000
+#define PLL_FBKDIV_16		0x00000000
+#define PLL_FBKDIV_1		0x00100000
+#define PLL_FBKDIV_2		0x00200000
+#define PLL_FBKDIV_3		0x00300000
+#define PLL_FBKDIV_4		0x00400000
+#define PLL_FBKDIV_5		0x00500000
+#define PLL_FBKDIV_6		0x00600000
+#define PLL_FBKDIV_7		0x00700000
+#define PLL_FBKDIV_8		0x00800000
+#define PLL_FBKDIV_9		0x00900000
+#define PLL_FBKDIV_10		0x00A00000
+#define PLL_FBKDIV_11		0x00B00000
+#define PLL_FBKDIV_12		0x00C00000
+#define PLL_FBKDIV_13		0x00D00000
+#define PLL_FBKDIV_14		0x00E00000
+#define PLL_FBKDIV_15		0x00F00000
+    /* Forward A divisor */
+#define PLL_FWDDIVA		0x00070000
+#define CPC0_PLLMR1_FWDVA	0x00070000
+#define PLL_FWDDIVA_8		0x00000000
+#define PLL_FWDDIVA_7		0x00010000
+#define PLL_FWDDIVA_6		0x00020000
+#define PLL_FWDDIVA_5		0x00030000
+#define PLL_FWDDIVA_4		0x00040000
+#define PLL_FWDDIVA_3		0x00050000
+#define PLL_FWDDIVA_2		0x00060000
+#define PLL_FWDDIVA_1		0x00070000
+    /* Forward B divisor */
+#define PLL_FWDDIVB		0x00007000
+#define CPC0_PLLMR1_FWDVB	0x00007000
+#define PLL_FWDDIVB_8		0x00000000
+#define PLL_FWDDIVB_7		0x00001000
+#define PLL_FWDDIVB_6		0x00002000
+#define PLL_FWDDIVB_5		0x00003000
+#define PLL_FWDDIVB_4		0x00004000
+#define PLL_FWDDIVB_3		0x00005000
+#define PLL_FWDDIVB_2		0x00006000
+#define PLL_FWDDIVB_1		0x00007000
+    /* PLL tune bits */
+#define PLL_TUNE_MASK		0x000003FF
+#define PLL_TUNE_2_M_3		0x00000133	/*  2 <= M <= 3			*/
+#define PLL_TUNE_4_M_6		0x00000134	/*  3 <	 M <= 6			*/
+#define PLL_TUNE_7_M_10		0x00000138	/*  6 <	 M <= 10		*/
+#define PLL_TUNE_11_M_14	0x0000013C	/* 10 <	 M <= 14		*/
+#define PLL_TUNE_15_M_40	0x0000023E	/* 14 <	 M <= 40		*/
+#define PLL_TUNE_VCO_LOW	0x00000000	/* 500MHz <= VCO <=  800MHz	*/
+#define PLL_TUNE_VCO_HI		0x00000080	/* 800MHz <  VCO <= 1000MHz	*/
+
+/* Defines for CPC0_PLLMR0 Register fields */
+    /* CPU divisor */
+#define PLL_CPUDIV		0x00300000
+#define CPC0_PLLMR0_CCDV	0x00300000
+#define PLL_CPUDIV_1		0x00000000
+#define PLL_CPUDIV_2		0x00100000
+#define PLL_CPUDIV_3		0x00200000
+#define PLL_CPUDIV_4		0x00300000
+    /* PLB divisor */
+#define PLL_PLBDIV		0x00030000
+#define CPC0_PLLMR0_CBDV	0x00030000
+#define PLL_PLBDIV_1		0x00000000
+#define PLL_PLBDIV_2		0x00010000
+#define PLL_PLBDIV_3		0x00020000
+#define PLL_PLBDIV_4		0x00030000
+    /* OPB divisor */
+#define PLL_OPBDIV		0x00003000
+#define CPC0_PLLMR0_OPDV	0x00003000
+#define PLL_OPBDIV_1		0x00000000
+#define PLL_OPBDIV_2		0x00001000
+#define PLL_OPBDIV_3		0x00002000
+#define PLL_OPBDIV_4		0x00003000
+    /* EBC divisor */
+#define PLL_EXTBUSDIV		0x00000300
+#define CPC0_PLLMR0_EPDV	0x00000300
+#define PLL_EXTBUSDIV_2		0x00000000
+#define PLL_EXTBUSDIV_3		0x00000100
+#define PLL_EXTBUSDIV_4		0x00000200
+#define PLL_EXTBUSDIV_5		0x00000300
+    /* MAL divisor */
+#define PLL_MALDIV		0x00000030
+#define CPC0_PLLMR0_MPDV	0x00000030
+#define PLL_MALDIV_1		0x00000000
+#define PLL_MALDIV_2		0x00000010
+#define PLL_MALDIV_3		0x00000020
+#define PLL_MALDIV_4		0x00000030
+    /* PCI divisor */
+#define PLL_PCIDIV		0x00000003
+#define CPC0_PLLMR0_PPFD	0x00000003
+#define PLL_PCIDIV_1		0x00000000
+#define PLL_PCIDIV_2		0x00000001
+#define PLL_PCIDIV_3		0x00000002
+#define PLL_PCIDIV_4		0x00000003
+
+#ifdef CONFIG_PPCHAMELEON_CLK_25
+/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
+#define PPCHAMELEON_PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_8	|  \
+			      PLL_FWDDIVA_6 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8  |  \
+			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
+			      PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
+			      PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
+
+/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
+#define PPCHAMELEON_PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_4	|  \
+				  PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
+				  PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
+				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
+				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#else
+#error "* External frequency (SysClk) not defined! *"
+#endif
+
+#if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
+/* Model HI */
+#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_333_111_37_55_55
+#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_333_111_37_55_55
+#define CFG_OPB_FREQ	55555555
+/* Model ME */
+#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
+#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_266_133_33_66_33
+#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_266_133_33_66_33
+#define CFG_OPB_FREQ	66666666
+#else
+/* Model BA (default) */
+#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_133_133_33_66_33
+#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_133_133_33_66_33
+#define CFG_OPB_FREQ	66666666
+#endif
+
+#endif /* CONFIG_NO_SERIAL_EEPROM */
+
+#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
+#define NAND_CACHE_PAGES 16			/* size of nand cache in 512 bytes pages */
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nand"
+#define CONFIG_JFFS2_PART_SIZE		0x00200000
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support
+ *
+ * Note: fake mtd_id used, no linux mtd map file
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=catcenter"
+#define MTDPARTS_DEFAULT	"mtdparts=catcenter:2m(nand)"
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CCM.h b/include/configs/CCM.h
new file mode 100755
index 0000000..e8994ff
--- /dev/null
+++ b/include/configs/CCM.h
@@ -0,0 +1,478 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * configuration options, board specific, for Siemens Card Controller Module
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef	CCM_80MHz			/* define for 80 MHz CPU only */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860           1   /* This is a MPC860 CPU ... */
+#define CONFIG_CCM              1   /* on a Card Controller Module  */
+
+#define CONFIG_8xx_CONS_SMC1    1   /* Console is on SMC1       */
+#undef  CONFIG_8xx_CONS_SMC2
+#undef  CONFIG_8xx_CONS_NONE
+
+/*  ENVIRONMENT */
+
+#define CONFIG_BAUDRATE         19200         /* console baudrate in bps    */
+#define CONFIG_BOOTDELAY        2             /* autoboot after 2 seconds   */
+
+#define CONFIG_IPADDR           192.168.0.42
+#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_GATEWAYIP        0.0.0.0
+#define CONFIG_SERVERIP         192.168.0.254
+
+#define CONFIG_HOSTNAME         CCM
+
+#define CONFIG_LOADADDR         40180000
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_BOOTCOMMAND      "setenv bootargs " \
+				"mem=${mem} " \
+				"root=/dev/ram rw ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
+				"wt_8xx=timeout:3600; " \
+				"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE	/* don't allow baudrate change	*/
+
+#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
+
+#undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
+
+#define	CONFIG_PRAM		512	/* reserve 512kB "protected RAM"*/
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define	CONFIG_SPI			/* enable SPI driver		*/
+#define	CONFIG_SPI_X			/* 16 bit EEPROM addressing	*/
+
+/* ----------------------------------------------------------------
+ * Offset to initial SPI buffers in DPRAM (used if the environment
+ * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
+ * use at an early stage. It is used between the two initialization
+ * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
+ * far enough from the start of the data area (as well as from the
+ * stack pointer).
+ * ---------------------------------------------------------------- */
+#define CFG_SPI_INIT_OFFSET		0xB00
+
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 32-byte page size	*/
+
+
+#define CONFIG_MAC_PARTITION		/* nod used yet			*/
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+
+/* Ethernet hardware configuration done using port pins */
+#define CFG_PA_ETH_RESET 	0x0200		/* PA  6	*/
+#define CFG_PA_ETH_MDDIS	0x4000		/* PA  1	*/
+#define CFG_PB_ETH_POWERDOWN	0x00000800	/* PB 20	*/
+#define CFG_PB_ETH_CFG1		0x00000400	/* PB 21	*/
+#define CFG_PB_ETH_CFG2		0x00000200	/* PB 22	*/
+#define CFG_PB_ETH_CFG3		0x00000100	/* PB 23	*/
+
+/* Ethernet settings:
+ * MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex
+ */
+#define CFG_ETH_MDDIS_VALUE	0
+#define CFG_ETH_CFG1_VALUE	1
+#define CFG_ETH_CFG2_VALUE	1
+#define CFG_ETH_CFG3_VALUE	1
+
+/* PUMA configuration */
+#define CFG_PC_PUMA_PROG	0x0200		/* PC  6        */
+#define CFG_PC_PUMA_DONE	0x0008		/* PC 12	*/
+#define CFG_PC_PUMA_INIT	0x0004		/* PC 13	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Address accessed to reset the board - must not be mapped/assigned
+ */
+#define	CFG_RESET_ADDRESS	0xFEFFFFFF
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#if 1
+/* Start port with environment in flash; switch to SPI EEPROM later */
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#else
+/* Final version: environment in EEPROM */
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_ENV_OFFSET		2048
+#define CFG_ENV_SIZE		2048
+#endif
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+						  SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * we must activate GPL5 in the SIUMCR for CAN
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#ifdef	CCM_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_PLPRCR							\
+		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else			/* up to 50 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif	/* CCM_80MHz */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#ifdef	CCM_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_SCCR	(/* SCCR_TBS  | */ \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#else			/* up to 50 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif	/* CCM_80MHz */
+
+/*-----------------------------------------------------------------------
+ *
+ * Interrupt Levels
+ *-----------------------------------------------------------------------
+ */
+#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+				 OR_SCY_5_CLK | OR_EHTR)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2 and OR2 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR3 and OR3 (CAN Controller)
+ */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+
+/*
+ * BR4/OR4: PUMA Config
+ *
+ * Memory controller will be used in 2 modes:
+ *
+ * - "read" mode:
+ *	BR4: 0x10100801		OR4: 0xffff8520
+ * - "load" mode (chip select on UPM B):
+ *	BR4: 0x101004c1		OR4: 0xffff8600
+ *
+ * Default initialization is in "read" mode
+ */
+#define PUMA_CONF_BASE		0x10100000	/* PUMA Config */
+#define PUMA_CONF_OR_AM		0xFFFF8000	/* 32 kB */
+#define	PUMA_CONF_LOAD_TIMING	(OR_ACS_DIV2	 | OR_SCY_2_CLK)
+#define PUMA_CONF_READ_TIMING	(OR_G5LA | OR_BI | OR_SCY_2_CLK)
+
+#define PUMA_CONF_BR_LOAD	((PUMA_CONF_BASE & BR_BA_MSK) | \
+					BR_PS_8  | BR_MS_UPMB | BR_V)
+#define PUMA_CONF_OR_LOAD	(PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
+
+#define PUMA_CONF_BR_READ	((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define PUMA_CONF_OR_READ	(PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
+
+#define CFG_BR4_PRELIM		PUMA_CONF_BR_READ
+#define CFG_OR4_PRELIM		PUMA_CONF_OR_READ
+
+/*
+ * BR5/OR5: PUMA: SMA Bus 8 Bit
+ *	BR5: 0x10200401		OR5: 0xffe0010a
+ */
+#define PUMA_SMA8_BASE		0x10200000	/* PUMA SMA Bus 8 Bit */
+#define PUMA_SMA8_OR_AM		0xFFE00000	/* 2 MB */
+#define PUMA_SMA8_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
+
+#define CFG_BR5_PRELIM		((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CFG_OR5_PRELIM		(PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
+
+/*
+ * BR6/OR6: PUMA: SMA Bus 16 Bit
+ *	BR6: 0x10600801		OR6: 0xffe0010a
+ */
+#define PUMA_SMA16_BASE		0x10600000	/* PUMA SMA Bus 16 Bit */
+#define PUMA_SMA16_OR_AM	0xFFE00000	/* 2 MB */
+#define PUMA_SMA16_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
+
+#define CFG_BR6_PRELIM		((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CFG_OR6_PRELIM		(PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
+
+/*
+ * BR7/OR7: PUMA: external Flash
+ *	BR7: 0x10a00801		OR7: 0xfe00010a
+ */
+#define PUMA_FLASH_BASE		0x10A00000	/* PUMA external Flash */
+#define PUMA_FLASH_OR_AM	0xFE000000	/* 32 MB */
+#define PUMA_FLASH_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
+
+#define CFG_BR7_PRELIM		((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CFG_OR7_PRELIM		(PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
new file mode 100755
index 0000000..6025886
--- /dev/null
+++ b/include/configs/CMS700.h
@@ -0,0 +1,393 @@
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CMS700.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_VOM405		1	/* ...on a VOM405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_NET_MULTI	1
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_DNS | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME )
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_EEPROM	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+#undef  CONFIG_PRAM			/* no "protected RAM"           */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#define	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * RTC stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_RTC_DS1337
+#define CFG_I2C_RTC_ADDR	0x68
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
+
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CFG_RAMBOOT		1
+#else
+# undef CFG_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#define CFG_EEPROM_WREN         1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+#define CFG_PLD_BASE            0xf0000000
+#define CFG_NAND_BASE	        0xF4000000  /* NAND FLASH Base Address		*/
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
+#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
+#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+/* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
+/* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
+/* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
+/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
+#define CFG_GPIO0_OSRH		0x40000500  /*	0 ... 15 */
+#define CFG_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
+#define CFG_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
+#define CFG_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
+#define CFG_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
+#define CFG_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
+#define CFG_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
+
+#define CFG_EEPROM_WP		(0x80000000 >> 8)    /* GPIO8 */
+#define CFG_PLD_RESET		(0x80000000 >> 12)   /* GPIO12 */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
new file mode 100755
index 0000000..b882f7a
--- /dev/null
+++ b/include/configs/CPC45.h
@@ -0,0 +1,513 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * Configuration settings for the CPC45 board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8245		1
+#define CONFIG_CPC45		1
+
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_EXT2	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_FLASH	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_SNTP	)
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+#if 1
+#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+/* Print Buffer Size
+ */
+#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+
+#define CFG_SDRAM_BASE		0x00000000
+
+#if defined(CONFIG_BOOT_ROM)
+#define CFG_FLASH_BASE		0xFF000000
+#else
+#define CFG_FLASH_BASE		0xFF800000
+#endif
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#define CFG_EUMB_ADDR		0xFCE00000
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+#define CFG_MEMTEST_START	0x00004000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+/* Maximum amount of RAM.
+ */
+#define CFG_MAX_RAM_SIZE	0x10000000
+
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+/* Size in bytes reserved for initial data
+ */
+#define CFG_GBL_DATA_SIZE	128
+
+#define CFG_INIT_RAM_ADDR	0x40000000
+#define CFG_INIT_RAM_END	0x1000
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	1
+
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
+#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
+#define DUART_DCR		(CFG_EUMB_ADDR + 0x4511)
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR	0x51
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x58
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ	33000000
+#define CFG_HZ			1000
+
+
+/* Bit-field values for MCCR1.
+ */
+#define CFG_ROMNAL		0
+#define CFG_ROMFAL		8
+
+#define CFG_BANK0_ROW		0	/* SDRAM bank 7-0 row address */
+#define CFG_BANK1_ROW		0
+#define CFG_BANK2_ROW		0
+#define CFG_BANK3_ROW		0
+#define CFG_BANK4_ROW		0
+#define CFG_BANK5_ROW		0
+#define CFG_BANK6_ROW		0
+#define CFG_BANK7_ROW		0
+
+/* Bit-field values for MCCR2.
+ */
+
+#define CFG_REFINT		0x2ec
+
+/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+ */
+#define CFG_BSTOPRE		160
+
+/* Bit-field values for MCCR3.
+ */
+#define CFG_REFREC		2	/* Refresh to activate interval		*/
+#define CFG_RDLAT		0	/* Data latancy from read command	*/
+
+/* Bit-field values for MCCR4.
+ */
+#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
+#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CFG_SDMODE_CAS_LAT	2	/* SDMODE CAS latancy			*/
+#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length			*/
+#define CFG_ACTORW		2
+#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CFG_EXTROM		0
+#define CFG_REGDIMM		0
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CFG_BANK0_START		0x00000000
+#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE	1
+#define CFG_BANK1_START		0x3ff00000
+#define CFG_BANK1_END		0x3fffffff
+#define CFG_BANK1_ENABLE	0
+#define CFG_BANK2_START		0x3ff00000
+#define CFG_BANK2_END		0x3fffffff
+#define CFG_BANK2_ENABLE	0
+#define CFG_BANK3_START		0x3ff00000
+#define CFG_BANK3_END		0x3fffffff
+#define CFG_BANK3_ENABLE	0
+#define CFG_BANK4_START		0x3ff00000
+#define CFG_BANK4_END		0x3fffffff
+#define CFG_BANK4_ENABLE	0
+#define CFG_BANK5_START		0x3ff00000
+#define CFG_BANK5_END		0x3fffffff
+#define CFG_BANK5_ENABLE	0
+#define CFG_BANK6_START		0x3ff00000
+#define CFG_BANK6_END		0x3fffffff
+#define CFG_BANK6_ENABLE	0
+#define CFG_BANK7_START		0x3ff00000
+#define CFG_BANK7_END		0x3fffffff
+#define CFG_BANK7_ENABLE	0
+
+#define CFG_ODCR		0xff
+#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L  CFG_IBAT0L
+#define CFG_DBAT0U  CFG_IBAT0U
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+#define CFG_DBAT2L  CFG_IBAT2L
+#define CFG_DBAT2U  CFG_IBAT2U
+#define CFG_DBAT3L  CFG_IBAT3L
+#define CFG_DBAT3U  CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CFG_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
+#define INTEL_ID_28F160F3T	0x88F388F3	/*  16M = 1M x 16 top boot sector	*/
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+	/* Warining: environment is not EMBEDDED in the ppcboot code.
+	 * It's stored in flash separately.
+	 */
+#define CFG_ENV_IS_IN_FLASH	    1
+
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x7F8000)
+#define CFG_ENV_SIZE		0x4000	/* Size of the Environment		*/
+#define CFG_ENV_OFFSET		0	/* starting right at the beginning	*/
+#define CFG_ENV_SECT_SIZE	0x8000 /* Size of the Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+
+#define SRAM_BASE		0x80000000	/* SRAM base address	*/
+#define SRAM_END		0x801FFFFF
+
+/*----------------------------------------------------------------------*/
+/* CPC45 Memory Map							*/
+/*----------------------------------------------------------------------*/
+#define SRAM_BASE	0x80000000	/* SRAM base address		*/
+#define ST16552_A_BASE	0x80200000	/* ST16552 channel A		*/
+#define ST16552_B_BASE	0x80400000	/* ST16552 channel A		*/
+#define BCSR_BASE	0x80600000	/* board control / status registers */
+#define DISPLAY_BASE	0x80600040	/* DISPLAY base			*/
+#define PCMCIA_MEM_BASE 0x83000000	/* PCMCIA memory window base	*/
+#define PCMCIA_IO_BASE	0xFE000000	/* PCMCIA IO window base	*/
+
+
+/*---------------------------------------------------------------------*/
+/* CPC45 Control/Status Registers				       */
+/*---------------------------------------------------------------------*/
+#define IRQ_ENA_1		*((volatile uchar*)(BCSR_BASE + 0x00))
+#define IRQ_STAT_1		*((volatile uchar*)(BCSR_BASE + 0x01))
+#define IRQ_ENA_2		*((volatile uchar*)(BCSR_BASE + 0x02))
+#define IRQ_STAT_2		*((volatile uchar*)(BCSR_BASE + 0x03))
+#define BOARD_CTRL		*((volatile uchar*)(BCSR_BASE + 0x04))
+#define BOARD_STAT		*((volatile uchar*)(BCSR_BASE + 0x05))
+#define WDG_START		*((volatile uchar*)(BCSR_BASE + 0x06))
+#define WDG_PRESTOP		*((volatile uchar*)(BCSR_BASE + 0x06))
+#define WDG_STOP		*((volatile uchar*)(BCSR_BASE + 0x06))
+#define BOARD_REV		*((volatile uchar*)(BCSR_BASE + 0x07))
+
+/* IRQ_ENA_1 bit definitions */
+#define I_ENA_1_IERA	0x80		/* INTA enable			*/
+#define I_ENA_1_IERB	0x40		/* INTB enable			*/
+#define I_ENA_1_IERC	0x20		/* INTC enable			*/
+#define I_ENA_1_IERD	0x10		/* INTD enable			*/
+
+/* IRQ_STAT_1 bit definitions */
+#define I_STAT_1_INTA	0x80		/* INTA status			*/
+#define I_STAT_1_INTB	0x40		/* INTB status			*/
+#define I_STAT_1_INTC	0x20		/* INTC status			*/
+#define I_STAT_1_INTD	0x10		/* INTD status			*/
+
+/* IRQ_ENA_2 bit definitions */
+#define I_ENA_2_IEAB	0x80		/* ABORT IRQ enable		*/
+#define I_ENA_2_IEK1	0x40		/* KEY1 IRQ enable		*/
+#define I_ENA_2_IEK2	0x20		/* KEY2 IRQ enable		*/
+#define I_ENA_2_IERT	0x10		/* RTC IRQ enable		*/
+#define I_ENA_2_IESM	0x08		/* LM81 IRQ enable		*/
+#define I_ENA_2_IEDG	0x04		/* DEGENERATING IRQ enable	*/
+#define I_ENA_2_IES2	0x02		/* ST16552/B IRQ enable		*/
+#define I_ENA_2_IES1	0x01		/* ST16552/A IRQ enable		*/
+
+/* IRQ_STAT_2 bit definitions */
+#define I_STAT_2_ABO	0x80		/* ABORT IRQ status		*/
+#define I_STAT_2_KY1	0x40		/* KEY1 IRQ status		*/
+#define I_STAT_2_KY2	0x20		/* KEY2 IRQ status		*/
+#define I_STAT_2_RTC	0x10		/* RTC IRQ status		*/
+#define I_STAT_2_SMN	0x08		/* LM81 IRQ status		*/
+#define I_STAT_2_DEG	0x04		/* DEGENERATING IRQ status	*/
+#define I_STAT_2_SIO2	0x02		/* ST16552/B IRQ status		*/
+#define I_STAT_2_SIO1	0x01		/* ST16552/A IRQ status		*/
+
+/* BOARD_CTRL bit definitions */
+#define USER_LEDS		2			/* 2 user LEDs	*/
+
+#if (USER_LEDS == 4)
+#define B_CTRL_WRSE		0x80
+#define B_CTRL_KRSE		0x40
+#define B_CTRL_FWRE		0x20		/* Flash write enable		*/
+#define B_CTRL_FWPT		0x10		/* Flash write protect		*/
+#define B_CTRL_LED3		0x08		/* LED 3 control		*/
+#define B_CTRL_LED2		0x04		/* LED 2 control		*/
+#define B_CTRL_LED1		0x02		/* LED 1 control		*/
+#define B_CTRL_LED0		0x01		/* LED 0 control		*/
+#else
+#define B_CTRL_WRSE		0x80
+#define B_CTRL_KRSE		0x40
+#define B_CTRL_FWRE_1		0x20		/* Flash write enable		*/
+#define B_CTRL_FWPT_1		0x10		/* Flash write protect		*/
+#define B_CTRL_LED1		0x08		/* LED 1 control		*/
+#define B_CTRL_LED0		0x04		/* LED 0 control		*/
+#define B_CTRL_FWRE_0		0x02		/* Flash write enable		*/
+#define B_CTRL_FWPT_0		0x01		/* Flash write protect		*/
+#endif
+
+/* BOARD_STAT bit definitions */
+#define B_STAT_WDGE		0x80
+#define B_STAT_WDGS		0x40
+#define B_STAT_WRST		0x20
+#define B_STAT_KRST		0x10
+#define B_STAT_CSW3		0x08		/* sitch bit 3 status		*/
+#define B_STAT_CSW2		0x04		/* sitch bit 2 status		*/
+#define B_STAT_CSW1		0x02		/* sitch bit 1 status		*/
+#define B_STAT_CSW0		0x01		/* sitch bit 0 status		*/
+
+/*---------------------------------------------------------------------*/
+/* Display addresses						       */
+/*---------------------------------------------------------------------*/
+#define DISP_UDC_RAM	(DISPLAY_BASE + 0x08)	/* UDC RAM	       */
+#define DISP_CHR_RAM	(DISPLAY_BASE + 0x18)	/* character Ram       */
+#define DISP_FLASH	(DISPLAY_BASE + 0x20)	/* Flash Ram	       */
+
+#define DISP_UDC_ADR	*((volatile uchar*)(DISPLAY_BASE + 0x00))	/* UDC Address Reg.    */
+#define DISP_CWORD	*((volatile uchar*)(DISPLAY_BASE + 0x10))	/* Control Word Reg.   */
+
+#define DISP_DIG0	*((volatile uchar*)(DISP_CHR_RAM + 0x00))	/* Digit 0 address     */
+#define DISP_DIG1	*((volatile uchar*)(DISP_CHR_RAM + 0x01))	/* Digit 0 address     */
+#define DISP_DIG2	*((volatile uchar*)(DISP_CHR_RAM + 0x02))	/* Digit 0 address     */
+#define DISP_DIG3	*((volatile uchar*)(DISP_CHR_RAM + 0x03))	/* Digit 0 address     */
+#define DISP_DIG4	*((volatile uchar*)(DISP_CHR_RAM + 0x04))	/* Digit 0 address     */
+#define DISP_DIG5	*((volatile uchar*)(DISP_CHR_RAM + 0x05))	/* Digit 0 address     */
+#define DISP_DIG6	*((volatile uchar*)(DISP_CHR_RAM + 0x06))	/* Digit 0 address     */
+#define DISP_DIG7	*((volatile uchar*)(DISP_CHR_RAM + 0x07))	/* Digit 0 address     */
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI			/* include pci support			*/
+#undef	CONFIG_PCI_PNP
+#undef	CONFIG_PCI_SCAN_SHOW
+
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/
+
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+
+#define PCI_ENET0_IOADDR	0x82000000
+#define PCI_ENET0_MEMADDR	0x82000000
+#define PCI_PLX9030_IOADDR	0x82100000
+#define PCI_PLX9030_MEMADDR	0x82100000
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_I82365
+
+#define CFG_PCMCIA_MEM_ADDR	PCMCIA_MEM_BASE
+#define CFG_PCMCIA_MEM_SIZE	0x1000
+
+#define CONFIG_PCMCIA_SLOT_A
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for IDE not supported	*/
+#define	CONFIG_IDE_LED			/* LED   for IDE is  supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+#define CFG_ATA_DATA_OFFSET	CFG_PCMCIA_MEM_SIZE
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x400)
+
+#define CONFIG_DOS_PARTITION
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
new file mode 100755
index 0000000..756bb8c
--- /dev/null
+++ b/include/configs/CPCI2DP.h
@@ -0,0 +1,272 @@
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+
+#define CONFIG_COMMANDS	      ( (CONFIG_CMD_DFL	& ~CFG_CMD_NET) | \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_EEPROM	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x040b  /* PCI Device ID: CPCI-2DP      */
+#define CFG_PCI_CLASSCODE       0x0280	/* PCI Class Code: Network/Other*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA	0xef000000	/* point to internal regs + PB0/1 */
+#define CFG_PCI_PTM2MS  0xff000001      /* 16MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#define CFG_EEPROM_WREN         1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0               /* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (PB0) initialization					*/
+#define CFG_EBC_PB2AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
+#define CFG_EBC_PB2CR		0xEF018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (PB1) initialization				*/
+#define CFG_EBC_PB3AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
+#define CFG_EBC_PB3CR		0xEF118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * GPIO definitions
+ */
+#define CFG_EEPROM_WP		(0x80000000 >> 13)   /* GPIO13 */
+#define CFG_PB_LED		(0x80000000 >> 16)   /* GPIO16 */
+#define CFG_INTA_FAKE		(0x80000000 >> 23)   /* GPIO23 */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
new file mode 100755
index 0000000..d49020d
--- /dev/null
+++ b/include/configs/CPCI405.h
@@ -0,0 +1,337 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_DNS | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME )
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_EEPROM	)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
+
+#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFD0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+
+#if 1 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
+
+#else /* Use EEPROM for environment variables */
+
+#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars */
+				   /* total size of a CAT24WC08 is 1024 bytes */
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization			*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (NVRAM) initialization						*/
+#define CFG_EBC_PB4AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
+#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 5 (Quart) initialization						*/
+#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#if 1 /* test-only */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#else
+#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
+#endif
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
new file mode 100755
index 0000000..13dbe80
--- /dev/null
+++ b/include/configs/CPCI4052.h
@@ -0,0 +1,422 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
+#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_DNS | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME )
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_EEPROM	)
+
+#if 0 /* test-only */
+#define CONFIG_NETCONSOLE
+#define CONFIG_NET_MULTI
+
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_PHY1_ADDR	1	/* PHY address: for NetConsole	*/
+#endif
+#endif
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#if 0 /* test-only */
+#define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+
+/*
+ * JFFS2 partitions
+ */
+
+/* No command line, one static partition, use whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=cpci4052-0"
+#define MTDPARTS_DEFAULT	"mtdparts=cpci4052-0:-(jffs2)"
+*/
+
+#if 0 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#define CFG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))	/* Env	*/
+
+#else /* Use EEPROM for environment variables */
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+#endif
+
+#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CFG_LED_ADDR		0xF0000380
+
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (NVRAM/RTC) initialization					*/
+/*#define CFG_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
+#define CFG_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
+#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 5 (optional Quart) initialization				*/
+#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 6 (FPGA internal) initialization					*/
+#define CFG_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CFG_FPGA_BASE_ADDR	0xF0400000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CFG_FPGA_MODE		0x00
+#define CFG_FPGA_STATUS		0x02
+#define CFG_FPGA_TS		0x04
+#define CFG_FPGA_TS_LOW		0x06
+#define CFG_FPGA_TS_CAP0	0x10
+#define CFG_FPGA_TS_CAP0_LOW	0x12
+#define CFG_FPGA_TS_CAP1	0x14
+#define CFG_FPGA_TS_CAP1_LOW	0x16
+#define CFG_FPGA_TS_CAP2	0x18
+#define CFG_FPGA_TS_CAP2_LOW	0x1a
+#define CFG_FPGA_TS_CAP3	0x1c
+#define CFG_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CFG_FPGA_MODE_CF_RESET	    0x0001
+#define CFG_FPGA_MODE_DUART_RESET   0x0002
+#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
+#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CFG_FPGA_MODE_TS_CLEAR	    0x2000
+
+/* FPGA Status Reg */
+#define CFG_FPGA_STATUS_DIP0	0x0001
+#define CFG_FPGA_STATUS_DIP1	0x0002
+#define CFG_FPGA_STATUS_DIP2	0x0004
+#define CFG_FPGA_STATUS_FLASH	0x0008
+#define CFG_FPGA_STATUS_TS_IRQ	0x1000
+
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
new file mode 100755
index 0000000..aaaafa9
--- /dev/null
+++ b/include/configs/CPCI405AB.h
@@ -0,0 +1,398 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
+#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
+#define CONFIG_CPCI405AB	1	/* ...and special AB version	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#undef	CONFIG_LOADS_ECHO		/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_DNS | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME )
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_EEPROM	)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=cpci405ab-0"
+#define MTDPARTS_DEFAULT	"mtdparts=cpci405ab-0:-(jffs2)"
+*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC32) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CFG_I2C_MULTI_EEPROMS   1       /* more than one eeprom used!   */
+#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+					/* 32 byte page write mode using*/
+					/* last 5 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/* Use EEPROM for environment variables */
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC32 is 4096 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CFG_LED_ADDR		0xF0000380
+
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (NVRAM/RTC) initialization					*/
+/*#define CFG_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
+#define CFG_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
+#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 5 (optional Quart) initialization				*/
+#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 6 (FPGA internal) initialization					*/
+#define CFG_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CFG_FPGA_BASE_ADDR	0xF0400000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CFG_FPGA_MODE		0x00
+#define CFG_FPGA_STATUS		0x02
+#define CFG_FPGA_TS		0x04
+#define CFG_FPGA_TS_LOW		0x06
+#define CFG_FPGA_TS_CAP0	0x10
+#define CFG_FPGA_TS_CAP0_LOW	0x12
+#define CFG_FPGA_TS_CAP1	0x14
+#define CFG_FPGA_TS_CAP1_LOW	0x16
+#define CFG_FPGA_TS_CAP2	0x18
+#define CFG_FPGA_TS_CAP2_LOW	0x1a
+#define CFG_FPGA_TS_CAP3	0x1c
+#define CFG_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CFG_FPGA_MODE_CF_RESET	    0x0001
+#define CFG_FPGA_MODE_DUART_RESET   0x0002
+#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
+#define CFG_FPGA_MODE_1WIRE_DIR     0x0100     /* dir=1 -> output */
+#define CFG_FPGA_MODE_SIM_OK_DIR    0x0200
+#define CFG_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400
+#define CFG_FPGA_MODE_1WIRE         0x1000
+#define CFG_FPGA_MODE_SIM_OK        0x2000     /* wired-or net from all devices */
+#define CFG_FPGA_MODE_TESTRIG_FAIL  0x4000
+
+/* FPGA Status Reg */
+#define CFG_FPGA_STATUS_DIP0    0x0001
+#define CFG_FPGA_STATUS_DIP1    0x0002
+#define CFG_FPGA_STATUS_DIP2    0x0004
+#define CFG_FPGA_STATUS_FLASH   0x0008
+#define CFG_FPGA_STATUS_1WIRE   0x1000
+#define CFG_FPGA_STATUS_SIM_OK  0x2000
+
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S30 */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
new file mode 100755
index 0000000..5cd9aba
--- /dev/null
+++ b/include/configs/CPCI405DT.h
@@ -0,0 +1,425 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
+#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_DNS | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME )
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_EEPROM	)
+
+#if 0 /* test-only */
+#define CONFIG_NETCONSOLE
+#define CONFIG_NET_MULTI
+
+#ifdef CONFIG_NET_MULTI
+#define CONFIG_PHY1_ADDR	1	/* PHY address: for NetConsole	*/
+#endif
+#endif
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#undef  CONFIG_AUTO_UPDATE              /* autoupdate via compactflash  */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/* Only interrupt boot if special string is typed */
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n"
+#undef  CONFIG_AUTOBOOT_DELAY_STR
+#undef  CONFIG_AUTOBOOT_STOP_STR        /* defined via environment var  */
+#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=cpci405dt-0"
+#define MTDPARTS_DEFAULT	"mtdparts=cpci405dt-0:-(jffs2)"
+*/
+
+#if 0 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#define CFG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))	/* Env	*/
+
+#else /* Use EEPROM for environment variables */
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+#endif
+
+#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CFG_LED_ADDR		0xF0000380
+
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (NVRAM/RTC) initialization					*/
+/*#define CFG_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
+#define CFG_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
+#define CFG_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 5 (optional Quart) initialization				*/
+#define CFG_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CFG_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 6 (FPGA internal) initialization					*/
+#define CFG_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CFG_FPGA_BASE_ADDR	0xF0400000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CFG_FPGA_MODE		0x00
+#define CFG_FPGA_STATUS		0x02
+#define CFG_FPGA_TS		0x04
+#define CFG_FPGA_TS_LOW		0x06
+#define CFG_FPGA_TS_CAP0	0x10
+#define CFG_FPGA_TS_CAP0_LOW	0x12
+#define CFG_FPGA_TS_CAP1	0x14
+#define CFG_FPGA_TS_CAP1_LOW	0x16
+#define CFG_FPGA_TS_CAP2	0x18
+#define CFG_FPGA_TS_CAP2_LOW	0x1a
+#define CFG_FPGA_TS_CAP3	0x1c
+#define CFG_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CFG_FPGA_MODE_CF_RESET	    0x0001
+#define CFG_FPGA_MODE_DUART_RESET   0x0002
+#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
+#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CFG_FPGA_MODE_TS_CLEAR	    0x2000
+
+/* FPGA Status Reg */
+#define CFG_FPGA_STATUS_DIP0	0x0001
+#define CFG_FPGA_STATUS_DIP1	0x0002
+#define CFG_FPGA_STATUS_DIP2	0x0004
+#define CFG_FPGA_STATUS_FLASH	0x0008
+#define CFG_FPGA_STATUS_TS_IRQ	0x1000
+
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h
new file mode 100755
index 0000000..a5bc773
--- /dev/null
+++ b/include/configs/CPCI440.h
@@ -0,0 +1,296 @@
+/*
+ * (C) Copyright 2002
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * board/config_CPCI440.h - configuration for esd CPCI-440 board
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_EBONY		1	    /* Board is ebony		*/
+#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
+#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
+#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
+#if 1
+#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
+#else
+#define CFG_MONITOR_BASE    0x01fc0000	    /* start of monitor		*/
+#endif
+#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
+#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
+
+#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
+#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE  128		    /* num bytes initial data	*/
+
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    (192 * 1024)    /* Reserve 192 kB for Mon	*/
+#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#undef CFG_EXT_SERIAL_CLOCK /*	 (1843200 * 6)	 / * Ext clk @ 11.059 MHz */
+#define CONFIG_BAUDRATE		9600
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#if 1 /* test-only */
+
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_FLASH_INCREMENT	0	/* there is only one bank		*/
+#define CFG_FLASH_PROTECTION	1	/* use hardware protection		*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#undef CFG_FLASH_BASE
+#define CFG_FLASH_BASE		0xFF800000 /* test-only...*/
+
+#else /* test-only */
+
+#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
+#define CFG_MAX_FLASH_SECT	32		    /* sectors per device   */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#if 0 /* test-only */
+#define CFG_ENV_IS_IN_NVRAM	1	    /* Environment uses NVRAM	*/
+#undef	CFG_ENV_IS_IN_FLASH		    /* ... not in flash		*/
+#undef	CFG_ENV_IS_IN_EEPROM		    /* ... not in EEPROM	*/
+
+#define CFG_ENV_SIZE		0x1000	    /* Size of Environment vars */
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
+#else
+
+#if 0 /* test-only */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x010	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+#else
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#endif
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+#define CONFIG_BAUDRATE		9600
+
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#if 0 /* test-only */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_KGDB	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_ELF	)
+#else
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_EEPROM	)
+/* test-only: support fehlt bisher... */
+/*				CFG_CMD_IDE	| \*/
+/*				CFG_CMD_PCI	| \*/
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#undef CONFIG_SPD_EEPROM       /* don't use SPD EEPROM for setup    */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#if 0 /* test-only */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#if 0
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		32768	/* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR	0xF0000500
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS	0x50
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
new file mode 100755
index 0000000..8bfd0ee
--- /dev/null
+++ b/include/configs/CPCI750.h
@@ -0,0 +1,598 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+/*************************************************************************
+ * (c) 2004 esd gmbh Hannover
+ *
+ *
+ * from db64360.h file
+ * by Reinhard Arlt reinhard.arlt@esd-electronics.com
+ *
+  ************************************************************************/
+
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* This define must be before the core.h include */
+#define CONFIG_CPCI750		1	/* this is an CPCI750 board	*/
+
+#ifndef __ASSEMBLY__
+#include <../board/Marvell/include/core.h>
+#endif
+/*-----------------------------------------------------*/
+
+#include "../board/esd/cpci750/local.h"
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_750FX			/* we have a 750FX (override local.h) */
+
+#define CONFIG_CPCI750		1	/* this is an CPCI750 board	*/
+
+#define CONFIG_BAUDRATE		9600 	/* console baudrate = 9600	*/
+
+#undef	CONFIG_ECC			/* enable ECC support */
+
+/* which initialization functions to call for this board */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+#define CFG_BOARD_NAME		"CPCI750"
+#define CONFIG_IDENT_STRING	"Marvell 64360 + IBM750FX"
+
+/*#define CFG_HUSH_PARSER*/
+#undef CFG_HUSH_PARSER
+
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+/* Define which ETH port will be used for connecting the network */
+#define CFG_ETH_PORT		ETH_0
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * what to do:
+ * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
+ * cable onto the second DUART channel, change the CFG_DUART port from 1
+ * to 0 below.
+ *
+ * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
+ * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
+ */
+#define	CONFIG_MPSC
+#define CONFIG_MPSC_PORT	0
+
+/* to change the default ethernet port, use this define (options: 0, 1, 2) */
+#define CONFIG_NET_MULTI
+#define MV_ETH_DEVS             1
+#define CONFIG_ETHER_PORT	0
+
+#undef CONFIG_ETHER_PORT_MII	/* use RMII */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot disabled		*/
+
+#define CONFIG_RTC_M48T35A	1	/* ST Electronics M48 timekeeper */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+
+#undef	CONFIG_BOOTARGS
+
+/* -----------------------------------------------------------------------------
+ * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus
+ */
+
+#define CONFIG_IPADDR		"192.168.0.185"
+
+#define CONFIG_SERIAL		"AA000001"
+#define CONFIG_SERVERIP		"10.0.0.79"
+#define CONFIG_ROOTPATH	        "/export/nfs_cpci750/%s"
+
+#define CONFIG_TESTDRAMDATA	y
+#define CONFIG_TESTDRAMADDRESS  n
+#define CONFIG_TESETDRAMWALK	n
+
+/* ----------------------------------------------------------------------------- */
+
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#define	CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_ALTIVEC                  /* undef to disable             */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE)
+
+
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL    \
+			 | CFG_CMD_ASKENV  \
+			 | CFG_CMD_I2C     \
+			 | CFG_CMD_CACHE   \
+			 | CFG_CMD_EEPROM  \
+			 | CFG_CMD_PCI     \
+			 | CFG_CMD_ELF	   \
+			 | CFG_CMD_DATE	   \
+			 | CFG_CMD_NET     \
+			 | CFG_CMD_PING    \
+			 | CFG_CMD_IDE     \
+			 | CFG_CMD_FAT     \
+			 | CFG_CMD_EXT2    \
+					)
+
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_SPEED   80000		/* I2C speed default */
+
+#define CFG_GT_DUAL_CPU			/* also for JTAG even with one cpu */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/*#define CFG_MEMTEST_START	0x00400000*/	/* memtest works on	*/
+/*#define CFG_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
+/*#define CFG_MEMTEST_END		0x07c00000*/	/* 4 ... 124 MB in DRAM	*/
+
+/*
+#define CFG_DRAM_TEST
+ * DRAM tests
+ *   CFG_DRAM_TEST - enables the following tests.
+ *
+ *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
+ *                        Environment variable 'test_dram_data' must be
+ *                        set to 'y'.
+ *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
+ *                        addressable. Environment variable
+ *                        'test_dram_address' must be set to 'y'.
+ *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
+ *                        This test takes about 6 minutes to test 64 MB.
+ *                        Environment variable 'test_dram_walk' must be
+ *                        set to 'y'.
+ */
+#define CFG_DRAM_TEST
+#if defined(CFG_DRAM_TEST)
+#define CFG_MEMTEST_START		0x00400000	/* memtest works on	*/
+/*#define CFG_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
+#define CFG_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM	*/
+#define CFG_DRAM_TEST_DATA
+#define CFG_DRAM_TEST_ADDRESS
+#define CFG_DRAM_TEST_WALK
+#endif /* CFG_DRAM_TEST */
+
+#define CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
+#undef CFG_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
+
+#define	CFG_LOAD_ADDR		0x00300000	/* default load address	*/
+
+#define	CFG_HZ			1000		/* decr freq: 1ms ticks	*/
+#define CFG_BUS_HZ		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)	 	*/
+#define CFG_BUS_CLK		CFG_BUS_HZ
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_TCLK		133000000
+
+/*#define CFG_750FX_HID0		0x8000c084*/
+#define CFG_750FX_HID0		0x80008484
+#define CFG_750FX_HID1		0x54800000
+#define CFG_750FX_HID2		0x00000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+ /*
+ * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
+ * To an unused memory region. The stack will remain in cache until RAM
+ * is initialized
+*/
+#undef    CFG_INIT_RAM_LOCK
+/* #define CFG_INIT_RAM_ADDR	0x40000000*/ /* unused memory region */
+/* #define CFG_INIT_RAM_ADDR	0xfba00000*/ /* unused memory region */
+#define CFG_INIT_RAM_ADDR	0xf1080000 /* unused memory region */
+#define CFG_INIT_RAM_END	0x1000
+#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define RELOCATE_INTERNAL_RAM_ADDR
+#ifdef RELOCATE_INTERNAL_RAM_ADDR
+/*#define CFG_INTERNAL_RAM_ADDR	0xfba00000*/
+#define CFG_INTERNAL_RAM_ADDR	0xf1080000
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+/* Dummies for BAT 4-7 */
+#define	CFG_SDRAM1_BASE		0x10000000	/* each 256 MByte */
+#define	CFG_SDRAM2_BASE		0x20000000
+#define	CFG_SDRAM3_BASE		0x30000000
+#define	CFG_SDRAM4_BASE		0x40000000
+#define CFG_RESET_ADDRESS	0xfff00100
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE	0xfff00000
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 256 kB for malloc */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+
+#define CFG_FLASH_CFI		1	   /* Flash is CFI conformant		*/
+#define CFG_MAX_FLASH_SECT	128	   /* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	4	   /* max number of memory banks	*/
+#define CFG_FLASH_INCREMENT	0x01000000 /* there is only one bank		*/
+#define CFG_FLASH_PROTECTION	1	   /* use hardware protection		*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	   /* use buffered writes (20x faster)	*/
+#define CFG_FLASH_BASE		0xfc000000 /* start of flash banks              */
+
+/* areas to map different things with the GT in physical space */
+#define CFG_DRAM_BANKS		4
+
+/* What to put in the bats. */
+#define CFG_MISC_REGION_BASE	0xf0000000
+
+/* Peripheral Device section */
+
+/*******************************************************/
+/* We have on the cpci750 Board :                      */
+/* GT-Chipset Register Area                            */
+/* GT-Chipset internal SRAM 256k                       */
+/* SRAM on external device module                      */
+/* Real time clock on external device module           */
+/* dobble UART on external device module               */
+/* Data flash on external device module                */
+/* Boot flash on external device module                */
+/*******************************************************/
+#define CFG_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
+#define  CFG_CPCI750_RESET_ADDR	0x14000000				/* After power on Reset the CPCI750 is here */
+
+#undef 	MARVEL_STANDARD_CFG
+#ifndef 	MARVEL_STANDARD_CFG
+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+#define CFG_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
+/*#define CFG_DEV_BASE		0xfc000000*/				/* GT Devices CS start here */
+#define CFG_INT_SRAM_BASE	0xf1080000				/* GT offers 256k internal fast SRAM */
+
+#define CFG_BOOT_SPACE		0xff000000				/* BOOT_CS0 flash 0    */
+#define CFG_DEV0_SPACE		0xfc000000				/* DEV_CS0 flash 1     */
+#define CFG_DEV1_SPACE		0xfd000000				/* DEV_CS1 flash 2     */
+#define CFG_DEV2_SPACE		0xfe000000				/* DEV_CS2 flash 3     */
+#define CFG_DEV3_SPACE		0xf0000000				/* DEV_CS3 nvram/can   */
+
+#define CFG_BOOT_SIZE		_16M 					/* cpci750 flash 0     */
+#define CFG_DEV0_SIZE		_16M 					/* cpci750 flash 1     */
+#define CFG_DEV1_SIZE		_16M 					/* cpci750 flash 2     */
+#define CFG_DEV2_SIZE		_16M 					/* cpci750 flash 3     */
+#define CFG_DEV3_SIZE		_16M 					/* cpci750 nvram/can   */
+
+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+#endif
+
+/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
+#define CFG_DEV0_PAR		0x8FDFFFFF				/* 16 bit flash */
+#define CFG_DEV1_PAR		0x8FDFFFFF				/* 16 bit flash */
+#define CFG_DEV2_PAR		0x8FDFFFFF				/* 16 bit flash */
+#define CFG_DEV3_PAR		0x8FCFFFFF				/* nvram/can    */
+#define CFG_BOOT_PAR		0x8FDFFFFF				/* 16 bit flash */
+
+	/*   c    4    a      8     2     4    1      c		*/
+	/* 33 22|2222|22 22|111 1|11 11|1 1  |    |		*/
+	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
+	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
+	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
+
+
+/* MPP Control MV64360 Appendix P P. 632*/
+#define CFG_MPP_CONTROL_0	0x00002222	/*                                   */
+#define CFG_MPP_CONTROL_1	0x11110000	/*                                   */
+#define CFG_MPP_CONTROL_2	0x11111111	/*                                   */
+#define CFG_MPP_CONTROL_3	0x00001111     	/*                                   */
+/* #define CFG_SERIAL_PORT_MUX	0x00000102*/	/*                                   */
+
+
+#define CFG_GPP_LEVEL_CONTROL	0xffffffff	/* 1111 1111 1111 1111 1111 1111 1111 1111*/
+
+/* setup new config_value for MV64360 DDR-RAM To_do !! */
+/*# define CFG_SDRAM_CONFIG	0xd8e18200*/	/* 0x448 */
+/*# define CFG_SDRAM_CONFIG	0xd8e14400*/	/* 0x1400 */
+				/* GB has high prio.
+				   idma has low prio
+				   MPSC has low prio
+				   pci has low prio 1 and 2
+				   cpu has high prio
+				   Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices
+				   ECC disable
+				   non registered DRAM */
+				/* 31:26   25:22  21:20 19 18 17 16 */
+				/* 100001 0000   010   0   0   0  0 */
+				/* refresh_count=0x400
+				   phisical interleaving disable
+				   virtual interleaving enable */
+				/* 15 14 13:0 */
+				/* 0  1  0x400 */
+# define CFG_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI                      /* include pci support          */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
+#define CONFIG_PCI_SCAN_SHOW            /* show devices on bus          */
+
+/* PCI MEMORY MAP section */
+#define CFG_PCI0_MEM_BASE	0x80000000
+#define CFG_PCI0_MEM_SIZE	_128M
+#define CFG_PCI1_MEM_BASE	0x88000000
+#define CFG_PCI1_MEM_SIZE	_128M
+
+#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
+#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+
+/* PCI I/O MAP section */
+#define CFG_PCI0_IO_BASE	0xfa000000
+#define CFG_PCI0_IO_SIZE	_16M
+#define CFG_PCI1_IO_BASE	0xfb000000
+#define CFG_PCI1_IO_SIZE	_16M
+
+#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
+#define CFG_PCI0_IO_SPACE_PCI	0x00000000
+#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
+#define CFG_PCI1_IO_SPACE_PCI	0x00000000
+
+#if defined (CONFIG_750CX)
+#define CFG_PCI_IDSEL 0x0
+#else
+#define CFG_PCI_IDSEL 0x30
+#endif
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#define CONFIG_IDE_RESET                /* no reset for ide supported   */
+#define CONFIG_IDE_PREINIT              /* check for units              */
+
+#define CFG_IDE_MAXBUS          2               /* max. 1 IDE busses    */
+#define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR       0
+#define CFG_ATA_IDE0_OFFSET     0
+#define CFG_ATA_IDE1_OFFSET     0
+
+#define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O                  */
+#define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses  */
+#define CFG_ATA_ALT_OFFSET      0x0000  /* Offset for alternate registers       */
+
+
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+
+/* SDRAM */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT0U CFG_IBAT0U
+
+/* init ram */
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+
+/* PCI0, PCI1 in one BAT */
+#define CFG_IBAT2L BATL_NO_ACCESS
+#define CFG_IBAT2U CFG_DBAT2U
+#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U CFG_IBAT3U
+
+/*
+ * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
+ * IBAT4 and DBAT4
+ * FIXME: ingo disable BATs for Linux Kernel
+ */
+#undef SETUP_HIGH_BATS_FX750		/* don't initialize BATS 4-7 */
+/*#define SETUP_HIGH_BATS_FX750*/		/* initialize BATS 4-7 */
+
+#ifdef SETUP_HIGH_BATS_FX750
+#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U CFG_IBAT4U
+
+/* IBAT5 and DBAT5 */
+#define CFG_IBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT5U (CFG_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT5U CFG_IBAT5U
+
+/* IBAT6 and DBAT6 */
+#define CFG_IBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT6U (CFG_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT6U CFG_IBAT6U
+
+/* IBAT7 and DBAT7 */
+#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT7U CFG_IBAT7U
+
+#else		/* set em out of range for Linux !!!!!!!!!!! */
+#define CFG_IBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT4U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT4U CFG_IBAT4U
+
+/* IBAT5 and DBAT5 */
+#define CFG_IBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT5U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT5U CFG_IBAT4U
+
+/* IBAT6 and DBAT6 */
+#define CFG_IBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT6U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT6U CFG_IBAT4U
+
+/* IBAT7 and DBAT7 */
+#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT7U CFG_IBAT4U
+
+#endif
+/* FIXME: ingo end: disable BATs for Linux Kernel */
+
+/* I2C addresses for the two DIMM SPD chips */
+#define DIMM0_I2C_ADDR	0x51
+#define DIMM1_I2C_ADDR	0x52
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_BOOT_FLASH_WIDTH	2	/* 16 bit */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
+
+#if 0
+#define	CFG_ENV_IS_IN_FLASH	0
+#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CFG_ENV_ADDR		0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
+/* #define CFG_ENV_ADDR    (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
+#endif
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_EEPROM_PAGE_WRITE_BITS 5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+#define CFG_I2C_EEPROM_ADDR     0x050
+#define CFG_ENV_OFFSET		0x200	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x600	/* 2048 bytes may be used for env vars*/
+
+#define CFG_NVRAM_BASE_ADDR	0xf0000000		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/mpc74xx.h for the defines used here
+ */
+
+/*#define CFG_L2*/
+#undef CFG_L2
+
+/*    #ifdef CONFIG_750CX*/
+#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
+#define L2_INIT 0
+#else
+#define L2_INIT  	(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#endif
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		    */
+
+#define CFG_BOARD_ASM_INIT      1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
new file mode 100755
index 0000000..93d49f3
--- /dev/null
+++ b/include/configs/CPCIISER4.h
@@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_CPCIISER4	1	/* ...on a CPCIISER4 board	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND	"bootm fff00000"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_EEPROM	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_EXT_SERIAL_CLOCK	1843200	 /* use external serial clock	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffe00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
+				   /* total size of a CAT24WC08 is 1024 bytes */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Uart 8bit) initialization					*/
+#define CFG_EBC_PB1AP		0x01000480  /* TWT=2,TH=2,no Ready,BEM=0,SOR=1	*/
+#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (Uart 32bit) initialization					*/
+#define CFG_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
+#define CFG_EBC_PB2CR		0xF011C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
+
+/* Memory Bank 3 (FPGA Reset) initialization					*/
+#define CFG_EBC_PB3AP		0x010004C0  /* no Ready, BEM=1			*/
+#define CFG_EBC_PB3CR		0xF021A000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
new file mode 100755
index 0000000..16a9ea5
--- /dev/null
+++ b/include/configs/CPU86.h
@@ -0,0 +1,656 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
+#define CONFIG_CPU86		1	/* ...on a CPU86 board	*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#undef  CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else*/
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ *
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define	CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
+
+/*
+ * - Rx-CLK is CLK11
+ * - Tx-CLK is CLK12
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	64000000	/* in Hz */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_PREBOOT								\
+	"echo; "								\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS; "	\
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+/*-----------------------------------------------------------------------
+ * I2C/EEPROM/RTC configuration
+ */
+#define	CONFIG_SOFT_I2C			/* Software I2C support enabled	*/
+
+# define CFG_I2C_SPEED		50000
+# define CFG_I2C_SLAVE		0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR	0x51
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*-----------------------------------------------------------------------
+ * Disk-On-Chip configuration
+ */
+
+#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
+
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configuration options
+ */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DOC	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CFG_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Flash configuration
+ */
+
+#define CFG_BOOTROM_BASE	0xFF800000
+#define CFG_BOOTROM_SIZE	0x00080000
+#define CFG_FLASH_BASE		0xFF000000
+#define CFG_FLASH_SIZE		0x00800000
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+/*-----------------------------------------------------------------------
+ * Other areas to be mapped
+ */
+
+/* CS3: Dual ported SRAM */
+#define CFG_DPSRAM_BASE		0x40000000
+#define CFG_DPSRAM_SIZE		0x00020000
+
+/* CS4: DiskOnChip */
+#define CFG_DOC_BASE		0xF4000000
+#define CFG_DOC_SIZE		0x00100000
+
+/* CS5: FDC37C78 controller */
+#define CFG_FDC37C78_BASE	0xF1000000
+#define CFG_FDC37C78_SIZE	0x00100000
+
+/* CS6: Board configuration registers */
+#define CFG_BCRS_BASE		0xF2000000
+#define CFG_BCRS_SIZE		0x00010000
+
+/* CS7: VME Extended Access Range */
+#define CFG_VMEEAR_BASE		0x80000000
+#define CFG_VMEEAR_SIZE		0x01000000
+
+/* CS8: VME Standard Access Range */
+#define CFG_VMESAR_BASE		0xFE000000
+#define CFG_VMESAR_SIZE		0x01000000
+
+/* CS9: VME Short I/O Access Range */
+#define CFG_VMESIOAR_BASE	0xFD000000
+#define CFG_VMESIOAR_SIZE	0x01000000
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#if defined(CONFIG_BOOT_ROM)
+#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
+				 HRCW_BPS01 | HRCW_CS10PC01)
+#else
+#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
+#endif
+
+/* no slaves so just fill with zeros */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CFG_SDRAM_BASE.
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT
+#endif
+
+#if 0
+/* environment is in Flash */
+#define CFG_ENV_IS_IN_FLASH	1
+#ifdef CONFIG_BOOT_ROM
+# define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x70000)
+# define CFG_ENV_SIZE		0x10000
+# define CFG_ENV_SECT_SIZE	0x10000
+#endif
+#else
+/* environment is in EEPROM */
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	1
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CFG_ENV_OFFSET		512
+#define CFG_ENV_SIZE		(2048 - 512)
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
+			 HID0_DCI|HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CFG_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR         RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#define BCR_APD01	0x10000000
+#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
+			 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR        SCCR_DFBRG01
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR        0
+
+#define CFG_MIN_AM_MASK	0xC0000000
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Refresh Timer Prescaler Register              10-18
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MPTPR       0x1F00
+
+/*-----------------------------------------------------------------------
+ * PSRT - Refresh Timer Register                                10-16
+ *-----------------------------------------------------------------------
+ */
+#define CFG_PSRT        0x0f
+
+/*-----------------------------------------------------------------------
+ * PSRT - SDRAM Mode Register                                   10-10
+ *-----------------------------------------------------------------------
+ */
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A9		|\
+			 ORxS_NUMR_12)
+
+#define CFG_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
+			 PSDMR_BSMA_A14_A16		|\
+			 PSDMR_SDA10_PBI0_A10		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_1W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A7		|\
+			 ORxS_NUMR_13)
+
+#define CFG_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
+			 PSDMR_BSMA_A13_A15		|\
+			 PSDMR_SDA10_PBI0_A9		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_1W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    8  bit  Boot ROM
+ *  1   60x     GPCM    64 bit  FLASH
+ *  2   60x     SDRAM   64 bit  SDRAM
+ *
+ */
+
+#define CFG_MRS_OFFS	0x00000000
+
+#ifdef CONFIG_BOOT_ROM
+/* Bank 0 - Boot ROM
+ */
+#define CFG_BR0_PRELIM  ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_BOOTROM_SIZE)   |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 1 - FLASH
+ */
+#define CFG_BR1_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
+
+#else /* CONFIG_BOOT_ROM */
+/* Bank 0 - FLASH
+ */
+#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 1 - Boot ROM
+ */
+#define CFG_BR1_PRELIM  ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_BOOTROM_SIZE)   |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
+
+#endif /* CONFIG_BOOT_ROM */
+
+
+/* Bank 2 - 60x bus SDRAM
+ */
+#ifndef CFG_RAMBOOT
+#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CFG_OR2_PRELIM	 CFG_OR2_9COL
+
+#define CFG_PSDMR	 CFG_PSDMR_9COL
+#endif /* CFG_RAMBOOT */
+
+/* Bank 3 - Dual Ported SRAM
+ */
+#define CFG_BR3_PRELIM  ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR3_PRELIM  (P2SZ_TO_AM(CFG_DPSRAM_SIZE)    |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_5_CLK                 |\
+			 ORxG_SETA)
+
+/* Bank 4 - DiskOnChip
+ */
+#define CFG_BR4_PRELIM  ((CFG_DOC_BASE & BRx_BA_MSK)    |\
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR4_PRELIM  (P2SZ_TO_AM(CFG_DOC_SIZE)       |\
+			 ORxG_ACS_DIV2                  |\
+			 ORxG_SCY_5_CLK                 |\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 5 - FDC37C78 controller
+ */
+#define CFG_BR5_PRELIM  ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
+			 BRx_PS_8                         |\
+			 BRx_MS_GPCM_P                    |\
+			 BRx_V)
+
+#define CFG_OR5_PRELIM  (P2SZ_TO_AM(CFG_FDC37C78_SIZE)    |\
+			 ORxG_ACS_DIV2                    |\
+			 ORxG_SCY_8_CLK                   |\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 6 - Board control registers
+ */
+#define CFG_BR6_PRELIM  ((CFG_BCRS_BASE & BRx_BA_MSK)   |\
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR6_PRELIM  (P2SZ_TO_AM(CFG_BCRS_SIZE)      |\
+			 ORxG_CSNT                      |\
+			 ORxG_SCY_5_CLK)
+
+/* Bank 7 - VME Extended Access Range
+ */
+#define CFG_BR7_PRELIM  ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
+			 BRx_PS_32                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR7_PRELIM  (P2SZ_TO_AM(CFG_VMEEAR_SIZE)    |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_5_CLK                 |\
+			 ORxG_SETA)
+
+/* Bank 8 - VME Standard Access Range
+ */
+#define CFG_BR8_PRELIM  ((CFG_VMESAR_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR8_PRELIM  (P2SZ_TO_AM(CFG_VMESAR_SIZE)    |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_5_CLK                 |\
+			 ORxG_SETA)
+
+/* Bank 9 - VME Short I/O Access Range
+ */
+#define CFG_BR9_PRELIM  ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16                        |\
+			 BRx_MS_GPCM_P                    |\
+			 BRx_V)
+
+#define CFG_OR9_PRELIM  (P2SZ_TO_AM(CFG_VMESIOAR_SIZE)    |\
+			 ORxG_CSNT                        |\
+			 ORxG_ACS_DIV1                    |\
+			 ORxG_SCY_5_CLK                   |\
+			 ORxG_SETA)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
new file mode 100755
index 0000000..a23d7e5
--- /dev/null
+++ b/include/configs/CPU87.h
@@ -0,0 +1,682 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
+#define CONFIG_CPU87		1	/* ...on a CPU87 board	*/
+#define CONFIG_PCI
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else*/
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ *
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
+#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
+
+#define	CONFIG_HAS_ETH1		1
+#define	CONFIG_HAS_ETH2		1
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
+
+/*
+ * - Rx-CLK is CLK11
+ * - Tx-CLK is CLK12
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	100000000	/* in Hz */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_PREBOOT								\
+	"echo; "								\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS; "	\
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+/*-----------------------------------------------------------------------
+ * I2C/EEPROM/RTC configuration
+ */
+#define CONFIG_SOFT_I2C			/* Software I2C support enabled */
+
+# define CFG_I2C_SPEED		50000
+# define CFG_I2C_SLAVE		0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else	iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else	iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR	0x51
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*-----------------------------------------------------------------------
+ * Disk-On-Chip configuration
+ */
+
+#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
+
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configuration options
+ */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#ifdef CONFIG_PCI
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
+				 CFG_CMD_BEDBUG | \
+				 CFG_CMD_DATE	| \
+				 CFG_CMD_DOC	| \
+				 CFG_CMD_EEPROM | \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_PCI)
+#else	/* ! PCI */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
+				 CFG_CMD_BEDBUG | \
+				 CFG_CMD_DATE	| \
+				 CFG_CMD_DOC	| \
+				 CFG_CMD_EEPROM | \
+				 CFG_CMD_I2C	)
+#endif	/* CONFIG_PCI */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END 0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
+
+#define CONFIG_LOOPW
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Flash configuration
+ */
+
+#define CFG_BOOTROM_BASE	0xFF800000
+#define CFG_BOOTROM_SIZE	0x00080000
+#define CFG_FLASH_BASE		0xFF000000
+#define CFG_FLASH_SIZE		0x00800000
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
+#define CFG_MAX_FLASH_SECT	135	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Other areas to be mapped
+ */
+
+/* CS3: Dual ported SRAM */
+#define CFG_DPSRAM_BASE		0x40000000
+#define CFG_DPSRAM_SIZE		0x00100000
+
+/* CS4: DiskOnChip */
+#define CFG_DOC_BASE		0xF4000000
+#define CFG_DOC_SIZE		0x00100000
+
+/* CS5: FDC37C78 controller */
+#define CFG_FDC37C78_BASE	0xF1000000
+#define CFG_FDC37C78_SIZE	0x00100000
+
+/* CS6: Board configuration registers */
+#define CFG_BCRS_BASE		0xF2000000
+#define CFG_BCRS_SIZE		0x00010000
+
+/* CS7: VME Extended Access Range */
+#define CFG_VMEEAR_BASE		0x60000000
+#define CFG_VMEEAR_SIZE		0x01000000
+
+/* CS8: VME Standard Access Range */
+#define CFG_VMESAR_BASE		0xFE000000
+#define CFG_VMESAR_SIZE		0x01000000
+
+/* CS9: VME Short I/O Access Range */
+#define CFG_VMESIOAR_BASE	0xFD000000
+#define CFG_VMESIOAR_SIZE	0x01000000
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#if defined(CONFIG_BOOT_ROM)
+#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
+				 HRCW_BPS01 | HRCW_CS10PC01)
+#else
+#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
+#endif
+
+/* no slaves so just fill with zeros */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CFG_SDRAM_BASE.
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT
+#endif
+
+#ifdef	CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+#endif
+
+#if 0
+/* environment is in Flash */
+#define CFG_ENV_IS_IN_FLASH	1
+#ifdef CONFIG_BOOT_ROM
+# define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x70000)
+# define CFG_ENV_SIZE		0x10000
+# define CFG_ENV_SECT_SIZE	0x10000
+#endif
+#else
+/* environment is in EEPROM */
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CFG_ENV_OFFSET		512
+#define CFG_ENV_SIZE		(2048 - 512)
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot		   */
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|\
+			 HID0_DCI|HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL	(HID0_IFEM|HID0_ABE)
+#define CFG_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register					 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR		RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define BCR_APD01	0x10000000
+#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR	(SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
+			 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				 4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR	SCCR_DFBRG01
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR	0
+
+#define CFG_MIN_AM_MASK 0xC0000000
+
+/*
+ * we use the same values for 32 MB and 128 MB SDRAM
+ * refresh rate = 7.68 uS (100 MHz Bus Clock)
+ */
+
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Refresh Timer Prescaler Register		10-18
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MPTPR	0x2000
+
+/*-----------------------------------------------------------------------
+ * PSRT - Refresh Timer Register				10-16
+ *-----------------------------------------------------------------------
+ */
+#define CFG_PSRT	0x16
+
+/*-----------------------------------------------------------------------
+ * PSRT - SDRAM Mode Register					10-10
+ *-----------------------------------------------------------------------
+ */
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A9		|\
+			 ORxS_NUMR_12)
+
+#define CFG_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
+			 PSDMR_BSMA_A14_A16		|\
+			 PSDMR_SDA10_PBI0_A10		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A7		|\
+			 ORxS_NUMR_13)
+
+#define CFG_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
+			 PSDMR_BSMA_A13_A15		|\
+			 PSDMR_SDA10_PBI0_A9		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus	Machine PortSz	Device
+ * ---- ---	------- ------	------
+ *  0	60x	GPCM	8  bit	Boot ROM
+ *  1	60x	GPCM	64 bit	FLASH
+ *  2	60x	SDRAM	64 bit	SDRAM
+ *
+ */
+
+#define CFG_MRS_OFFS	0x00000000
+
+#ifdef CONFIG_BOOT_ROM
+/* Bank 0 - Boot ROM
+ */
+#define CFG_BR0_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 1 - FLASH
+ */
+#define CFG_BR1_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_64			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxU_EHTR_8IDLE)
+
+#else /* CONFIG_BOOT_ROM */
+/* Bank 0 - FLASH
+ */
+#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_64			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 1 - Boot ROM
+ */
+#define CFG_BR1_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxU_EHTR_8IDLE)
+
+#endif /* CONFIG_BOOT_ROM */
+
+
+/* Bank 2 - 60x bus SDRAM
+ */
+#ifndef CFG_RAMBOOT
+#define CFG_BR2_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+#define CFG_OR2_PRELIM	 CFG_OR2_9COL
+
+#define CFG_PSDMR	 CFG_PSDMR_9COL
+#endif /* CFG_RAMBOOT */
+
+/* Bank 3 - Dual Ported SRAM
+ */
+#define CFG_BR3_PRELIM	((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR3_PRELIM	(P2SZ_TO_AM(CFG_DPSRAM_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_7_CLK			|\
+			 ORxG_SETA)
+
+/* Bank 4 - DiskOnChip
+ */
+#define CFG_BR4_PRELIM	((CFG_DOC_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR4_PRELIM	(P2SZ_TO_AM(CFG_DOC_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV2			|\
+			 ORxG_SCY_9_CLK			|\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 5 - FDC37C78 controller
+ */
+#define CFG_BR5_PRELIM	((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
+			 BRx_PS_8			  |\
+			 BRx_MS_GPCM_P			  |\
+			 BRx_V)
+
+#define CFG_OR5_PRELIM	(P2SZ_TO_AM(CFG_FDC37C78_SIZE)	  |\
+			 ORxG_ACS_DIV2			  |\
+			 ORxG_SCY_10_CLK		  |\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 6 - Board control registers
+ */
+#define CFG_BR6_PRELIM	((CFG_BCRS_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR6_PRELIM	(P2SZ_TO_AM(CFG_BCRS_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_SCY_7_CLK)
+
+/* Bank 7 - VME Extended Access Range
+ */
+#define CFG_BR7_PRELIM	((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
+			 BRx_PS_32			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR7_PRELIM	(P2SZ_TO_AM(CFG_VMEEAR_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_7_CLK			|\
+			 ORxG_SETA)
+
+/* Bank 8 - VME Standard Access Range
+ */
+#define CFG_BR8_PRELIM	((CFG_VMESAR_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR8_PRELIM	(P2SZ_TO_AM(CFG_VMESAR_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_7_CLK			|\
+			 ORxG_SETA)
+
+/* Bank 9 - VME Short I/O Access Range
+ */
+#define CFG_BR9_PRELIM	((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16			  |\
+			 BRx_MS_GPCM_P			  |\
+			 BRx_V)
+
+#define CFG_OR9_PRELIM	(P2SZ_TO_AM(CFG_VMESIOAR_SIZE)	  |\
+			 ORxG_CSNT			  |\
+			 ORxG_ACS_DIV1			  |\
+			 ORxG_SCY_7_CLK			  |\
+			 ORxG_SETA)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h
new file mode 100755
index 0000000..63d7a92
--- /dev/null
+++ b/include/configs/CRAYL1.h
@@ -0,0 +1,247 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * David Updegraff, Cray, Inc.  dave@cray.com: our 405 is walnut-lite..
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_CRAYL1
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU	*/
+#define CONFIG_4xx		    1   /* ...member of PPC405 family */
+#define CONFIG_SYS_CLK_FREQ 25000000
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#define CONFIG_MII		    1	/* MII PHY management */
+#define	CONFIG_PHY_ADDR		1	/* PHY address; handling of ENET */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* early setup for 405gp */
+#define CONFIG_MISC_INIT_R	1	/* so that a misc_init_r() is called */
+
+/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
+ * keep possible initrd ramdisk decompression out.  This is in k (1024 bytes)
+ #define CONFIG_PRAM			16
+ */
+#define	CONFIG_LOADADDR		0x100000	/* where TFTP images go */
+#undef CONFIG_BOOTARGS
+
+/* Bootcmd is overridden by the bootscript in board/cray/L1
+ */
+#define	CFG_AUTOLOAD		"no"
+#define CONFIG_BOOTCOMMAND	"dhcp"
+
+/*
+ * ..during experiments..
+ #define CONFIG_SERVERIP         10.0.0.1
+ #define CONFIG_ETHADDR          00:40:a6:80:14:5
+ */
+#define CONFIG_HARD_I2C         1		/* hardware support for i2c */
+#define CONFIG_SDRAM_BANK0		1
+#define CFG_I2C_SPEED		    400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		    0x7F
+#define CFG_I2C_EEPROM_ADDR     0x57
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_IDENT_STRING     "Cray L1"
+#define CONFIG_ENV_OVERWRITE     1
+#define	CFG_HZ		             1000	/* decrementer freq: 1 ms ticks	*/
+#define CFG_HUSH_PARSER			1
+#define CFG_PROMPT_HUSH_PS2		"> "
+#define CONFIG_AUTOSCRIPT		1
+
+
+#define CONFIG_COMMANDS	 (\
+	CFG_CMD_BDI|\
+	CFG_CMD_IMI|\
+	CFG_CMD_FLASH|\
+	CFG_CMD_MEMORY|\
+	CFG_CMD_NET|\
+	CFG_CMD_ENV|\
+	CFG_CMD_CONSOLE|\
+	CFG_CMD_ASKENV|\
+	CFG_CMD_ECHO|\
+	CFG_CMD_IMMAP|\
+	CFG_CMD_REGINFO|\
+	CFG_CMD_DHCP|\
+	CFG_CMD_DATE|\
+	CFG_CMD_RUN|\
+	CFG_CMD_I2C|\
+	CFG_CMD_EEPROM|\
+	CFG_CMD_DIAG|\
+	CFG_CMD_AUTOSCRIPT|\
+	CFG_CMD_SETGETDCR)
+
+/*
+ * optional BOOTP / DHCP fields
+ */
+#define CONFIG_BOOTP_MASK (\
+	CONFIG_BOOTP_VENDOREX|\
+	CONFIG_BOOTP_SUBNETMASK|\
+	CONFIG_BOOTP_GATEWAY|\
+	CONFIG_BOOTP_DNS|\
+	CONFIG_BOOTP_HOSTNAME|\
+	CONFIG_BOOTP_BOOTFILESIZE|\
+	CONFIG_BOOTP_BOOTPATH)
+
+/*
+ * how many time to fail & restart a net-TFTP before giving up & resetting
+ * the board hoping that a reset of net interface might help..
+ */
+#define CONFIG_NET_RESET 5
+
+/*
+ * bauds.  Just to make it compile; in our case, I read the base_baud
+ * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
+ * drives the system clock.
+ */
+#define CFG_BASE_BAUD       403225
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_PROMPT	"=> "			/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE	256				/* Console I/O Buffer Size	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16				/* max number of command args	*/
+
+
+#define CFG_LOAD_ADDR   	0x100000/* where to load what we get from TFTP */
+#define CFG_TFTP_LOADADDR	CFG_LOAD_ADDR
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CFG_DRAM_TEST		1
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFC00000
+#define CFG_MONITOR_BASE	TEXT_BASE
+
+
+#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	 1		/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	 64		/* max number of sectors on one chip	*/
+#define CFG_FLASH_ERASE_TOUT 120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT 500	/* Timeout for Flash Write (in ms)	*/
+
+/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector  */
+#define CFG_ENV_OFFSET		0x3c8000
+#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define	CFG_ENV_SIZE		0x1000	 /* Total Size of Environment area	*/
+#define CFG_ENV_SECT_SIZE	0x10000	 /* see README - env sector total size	*/
+
+/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
+ * 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
+ */
+#define CFG_SDRAM_SIZE		32		/* megs of ram */
+#define CFG_MEMTEST_START	0x2000  /* memtest works from the end of */
+									/* the exception vector table */
+									/* to the end of the DRAM  */
+									/* less monitor and malloc area */
+#define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
+#define CFG_MALLOC_LEN		(128 << 10)	/* 128k for malloc space */
+#define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \
+				+ CFG_MALLOC_LEN \
+				+ CFG_ENV_SECT_SIZE \
+				+ CFG_STACK_USAGE )
+
+#define CFG_MEMTEST_END		(CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE)
+/* END ENVIRONNEMENT FLASH */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration.  Only used to ..?? clear it, I guess..
+ */
+#define CFG_DCACHE_SIZE		16384
+#define CFG_CACHELINE_SIZE	32
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in OnChipMem )
+ */
+#if 1
+/* On Chip Memory location */
+#define CFG_TEMP_STACK_OCM	1
+#define CFG_OCM_DATA_ADDR	0xF0000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE      256  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+#else
+#define CFG_OCM_DATA_ADDR	0xF0000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR 	/* inside of On Chip SRAM    */
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	     */
+#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#endif
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ */
+#define EEPROM_WRITE_ADDRESS 0xA0
+#define EEPROM_READ_ADDRESS  0xA1
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/CU824.h b/include/configs/CU824.h
new file mode 100755
index 0000000..acc8484
--- /dev/null
+++ b/include/configs/CU824.h
@@ -0,0 +1,312 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * Configuration settings for the CU824 board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8240		1
+#define CONFIG_CU824		1
+
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#define CONFIG_BOOTCOMMAND	"bootm FE020000"	/* autoboot command	*/
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BEDBUG  | \
+				0 /* CFG_CMD_DATE */	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+#if 1
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+/* Print Buffer Size
+ */
+#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE	    0x00000000
+#define CFG_FLASH_BASE	    0xFF000000
+
+#define CFG_RESET_ADDRESS   0xFFF00100
+
+#define CFG_EUMB_ADDR	    0xFCE00000
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+
+#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+
+#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+	/* Maximum amount of RAM.
+	 */
+#define CFG_MAX_RAM_SIZE    0x10000000
+
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+	/* Size in bytes reserved for initial data
+	 */
+#define CFG_GBL_DATA_SIZE    128
+
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x1000
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	4
+
+#define CFG_NS16550_CLK		(14745600 / 2)
+
+#define CFG_NS16550_COM1	0xFE800080
+#define CFG_NS16550_COM2	0xFE8000C0
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33000000
+#define CFG_HZ		     1000
+
+	/* Bit-field values for MCCR1.
+	 */
+#define CFG_ROMNAL	    0
+#define CFG_ROMFAL	    7
+
+	/* Bit-field values for MCCR2.
+	 */
+#define CFG_REFINT	    430	    /* Refresh interval			*/
+
+	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+	 */
+#define CFG_BSTOPRE	    192
+
+	/* Bit-field values for MCCR3.
+	 */
+#define CFG_REFREC	    2	    /* Refresh to activate interval	*/
+#define CFG_RDLAT	    3	    /* Data latancy from read command	*/
+
+	/* Bit-field values for MCCR4.
+	 */
+#define CFG_PRETOACT	    2	    /* Precharge to activate interval	*/
+#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
+#define CFG_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
+#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
+#define CFG_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
+#define CFG_ACTORW	    2
+#define CFG_REGISTERD_TYPE_BUFFER 1
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CFG_BANK0_START	    0x00000000
+#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE    1
+#define CFG_BANK1_START	    0x3ff00000
+#define CFG_BANK1_END	    0x3fffffff
+#define CFG_BANK1_ENABLE    0
+#define CFG_BANK2_START	    0x3ff00000
+#define CFG_BANK2_END	    0x3fffffff
+#define CFG_BANK2_ENABLE    0
+#define CFG_BANK3_START	    0x3ff00000
+#define CFG_BANK3_END	    0x3fffffff
+#define CFG_BANK3_ENABLE    0
+#define CFG_BANK4_START	    0x3ff00000
+#define CFG_BANK4_END	    0x3fffffff
+#define CFG_BANK4_ENABLE    0
+#define CFG_BANK5_START	    0x3ff00000
+#define CFG_BANK5_END	    0x3fffffff
+#define CFG_BANK5_ENABLE    0
+#define CFG_BANK6_START	    0x3ff00000
+#define CFG_BANK6_END	    0x3fffffff
+#define CFG_BANK6_ENABLE    0
+#define CFG_BANK7_START	    0x3ff00000
+#define CFG_BANK7_END	    0x3fffffff
+#define CFG_BANK7_ENABLE    0
+
+#define CFG_ODCR	    0xff
+
+#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L  CFG_IBAT0L
+#define CFG_DBAT0U  CFG_IBAT0U
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+#define CFG_DBAT2L  CFG_IBAT2L
+#define CFG_DBAT2U  CFG_IBAT2U
+#define CFG_DBAT3L  CFG_IBAT3L
+#define CFG_DBAT3U  CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
+#define CFG_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+	/* Warining: environment is not EMBEDDED in the U-Boot code.
+	 * It's stored in flash separately.
+	 */
+#define CFG_ENV_IS_IN_FLASH	    1
+#if 0
+#define CFG_ENV_ADDR		0xFF008000
+#define CFG_ENV_SIZE		0x8000	/* Size of the Environment Sector	*/
+#else
+#define CFG_ENV_ADDR		0xFFFC0000
+#define CFG_ENV_SIZE		0x4000	/* Size of the Environment		*/
+#define CFG_ENV_OFFSET		0	/* starting right at the beginning	*/
+#define CFG_ENV_SECT_SIZE	0x40000 /* Size of the Environment Sector	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI			/* include pci support			*/
+#undef CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support 	*/
+
+#define CONFIG_TULIP
+#define CONFIG_TULIP_USE_IO
+
+#define CFG_ETH_DEV_FN	     0x7800
+#define CFG_ETH_IOBASE	     0x00104000
+
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define PCI_ENET0_IOADDR	0x00104000
+#define PCI_ENET0_MEMADDR	0x80000000
+#endif	/* __CONFIG_H */
diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h
new file mode 100755
index 0000000..997e1ba
--- /dev/null
+++ b/include/configs/DASA_SIM.h
@@ -0,0 +1,208 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_IOP480		1	/* This is a IOP480 CPU		*/
+#define CONFIG_DASA_SIM		1	/* ...on a DASA_SIM board	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_CPUCLOCK		66
+#define CONFIG_BUSCLOCK		(CONFIG_CPUCLOCK)
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
+#define CONFIG_BOOTCOMMAND	"bootm ffe00000" /* autoboot command	*/
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_IPADDR		10.0.18.222
+#define CONFIG_SERVERIP		10.0.18.190
+
+#if 0
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_ELF	)
+#else
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BSP	)
+#endif
+
+#if 0 /* Does not appear to be used?!  If it is used, needs to be fixed */
+#define CONFIG_SOFT_I2C			/* Software I2C support enabled */
+#endif
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
+#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFD0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 128 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x0AA9	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x0556	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0002	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0000	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0004	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
+#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
+
+#if 0
+#define CFG_ENV_SECT_SIZE	0x8000	/* see README - env sector total size	*/
+#else
+#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ */
+#define CONFIG_PCI			/* include pci support			*/
+#undef CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/
+
+#define CONFIG_TULIP
+
+#define CFG_ETH_DEV_FN	     0x0000
+#define CFG_ETH_IOBASE	     0x0fff0000
+#define CFG_PCI9054_DEV_FN   0x0800
+#define CFG_PCI9054_IOBASE   0x0eff0000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		2048	/* For PLX IOP480			*/
+#define CFG_CACHELINE_SIZE	16	/* For AMCC 401/403 CPUs		*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0	*/
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h
new file mode 100755
index 0000000..bd7aff1
--- /dev/null
+++ b/include/configs/DB64360.h
@@ -0,0 +1,596 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+/*************************************************************************
+ * (c) 2002 Datentechnik AG - Project: Dino
+ *
+ *
+ * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $
+ *
+  ************************************************************************/
+
+/*************************************************************************
+ *
+ * History:
+ *
+ *	$Log: DB64360.h,v $
+ *	Revision 1.3  2003/04/26 04:58:13  brad
+ *	Cosmetic changes and compiler warning cleanups
+ *
+ *	Revision 1.2  2003/04/23 15:48:15  ingo
+ *	mem. map output added
+ *
+ *	Revision 1.1  2003/04/17 09:31:42  ias
+ *	keymile changes 17_04_2003
+ *
+ *	Revision 1.10  2003/03/06 12:25:04  ias
+ *	750 FX CPU HID settings updated
+ *
+ *	Revision 1.9  2003/03/03 16:14:36  ias
+ *	cleanup compiler warnings of printf fuctions
+ *
+ *	Revision 1.8  2003/03/03 15:11:44  ias
+ *	Marvell MPSC-UART is working
+ *
+ *	Revision 1.7  2003/02/26 12:15:45  ssu
+ *	adapted default parameters to new board flash address
+ *
+ *	Revision 1.6  2003/02/25 14:55:42  ssu
+ *	changed default environment parameters
+ *
+ *	Revision 1.5  2003/02/21 17:14:23  ias
+ *	added extended SPD handling
+ *
+ *	Revision 1.4  2003/01/14 09:16:08  ias
+ *	PPCBoot for Marvel Beta 0.9
+ *
+ *	Revision 1.3  2002/12/03 13:56:26  ias
+ *	Environment in flash support added
+ *
+ *	Revision 1.2  2002/11/29 16:53:29  ias
+ *	Flash support for STM added
+ *
+ *	Revision 1.1  2002/11/29 13:36:31  ias
+ *	Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board
+ *	- working DDRRAM (only 32MByte of 128MB Modul)
+ *	- working I2C Driver for SPD EEPROM read
+ *	- working DUART 16650 for Serial Console
+ *	- working "console"
+ *
+ *
+ *
+ ************************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* This define must be before the core.h include */
+#define CONFIG_DB64360		1	/* this is an DB64360 board	*/
+
+#ifndef __ASSEMBLY__
+#include "../board/Marvell/include/core.h"
+#endif
+
+/*-----------------------------------------------------*/
+/*    #include "../board/db64360/local.h"	      */
+#ifndef __LOCAL_H
+#define __LOCAL_H
+
+/* first ethernet */
+#define CONFIG_ETHADDR		64:36:00:00:00:01
+											     /* next two ethernet hwaddrs */
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		64:36:00:00:00:02
+/* in the atlantis 64360 we have only 2 ETH port on the board,
+if we use PCI it has its own MAC addr */
+
+#define CONFIG_ENV_OVERWRITE
+#endif	/* __CONFIG_H */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_74xx			/* we have a 750FX (override local.h) */
+
+#define CONFIG_DB64360		1	/* this is an DB64360 board	*/
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115000	*/
+/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
+	DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
+	so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
+	see sdram_init.c   */
+#undef CONFIG_ECC	 /* enable ECC support */
+#define CONFIG_MV64360_ECC
+
+/* which initialization functions to call for this board */
+#define CONFIG_MISC_INIT_R     /* initialize the icache L1 */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CFG_BOARD_NAME		"DB64360"
+#define CONFIG_IDENT_STRING	"Marvell DB64360 (1.1)"
+
+/*#define CFG_HUSH_PARSER */
+#undef CFG_HUSH_PARSER
+
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * what to do:
+ * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
+ * cable onto the second DUART channel, change the CFG_DUART port from 1
+ * to 0 below.
+ *
+ * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
+ * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
+ */
+
+#define CONFIG_MPSC_PORT	0
+
+/* to change the default ethernet port, use this define (options: 0, 1, 2) */
+#define CONFIG_NET_MULTI
+#define MV_ETH_DEVS 2
+
+/* #undef CONFIG_ETHER_PORT_MII	 */
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+
+#undef	CONFIG_BOOTARGS
+/*#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
+
+/* ronen - autoboot using tftp */
+#if (CONFIG_BOOTDELAY >= 0)
+#define CONFIG_BOOTCOMMAND	"tftpboot 0x400000 uImage;\
+ setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
+ ip=${ipaddr}:${serverip}${bootargs_end};  bootm 0x400000; "
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200"
+
+#endif
+
+/* ronen - the u-boot.bin should be ~0x30000 bytes */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+     "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
+cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
+      "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
+cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
+      "bootargs_root=root=/dev/nfs rw\0" \
+      "bootargs_end=:::DB64360:eth0:none \0"\
+      "ethprime=mv_enet0\0"\
+      "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
+ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
+
+/* --------------------------------------------------------------------------------------------------------------- */
+/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */
+
+#define CONFIG_IPADDR		10.2.40.90
+
+#define CONFIG_SERIAL		"No. 1"
+#define CONFIG_SERVERIP		10.2.1.126
+#define CONFIG_ROOTPATH /mnt/yellow_dog_mini
+
+
+#define CONFIG_TESTDRAMDATA	y
+#define CONFIG_TESTDRAMADDRESS	n
+#define CONFIG_TESETDRAMWALK	n
+
+/* --------------------------------------------------------------------------------------------------------------- */
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
+#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_ALTIVEC			/* undef to disable		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor1"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor1=db64360-1"
+#define MTDPARTS_DEFAULT	"mtdparts=db64360-1:-(jffs2)"
+*/
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+			 | CFG_CMD_ASKENV \
+			 | CFG_CMD_I2C \
+			 | CFG_CMD_EEPROM \
+			 | CFG_CMD_CACHE \
+			 | CFG_CMD_JFFS2 \
+			 | CFG_CMD_PCI \
+			 | CFG_CMD_NET )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_SPEED	40000		/* I2C speed default */
+
+/* #define CFG_GT_DUAL_CPU	 also for JTAG even with one cpu */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/*#define CFG_MEMTEST_START	0x00400000	 memtest works on	*/
+/*#define CFG_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
+/*#define CFG_MEMTEST_END		0x07c00000	 4 ... 124 MB in DRAM	*/
+
+/*
+#define CFG_DRAM_TEST
+ * DRAM tests
+ *   CFG_DRAM_TEST - enables the following tests.
+ *
+ *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
+ *			  Environment variable 'test_dram_data' must be
+ *			  set to 'y'.
+ *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
+ *			  addressable. Environment variable
+ *			  'test_dram_address' must be set to 'y'.
+ *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
+ *			  This test takes about 6 minutes to test 64 MB.
+ *			  Environment variable 'test_dram_walk' must be
+ *			  set to 'y'.
+ */
+#define CFG_DRAM_TEST
+#if defined(CFG_DRAM_TEST)
+#define CFG_MEMTEST_START		0x00400000	/* memtest works on	*/
+/* #define CFG_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
+#define CFG_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
+#define CFG_DRAM_TEST_DATA
+#define CFG_DRAM_TEST_ADDRESS
+#define CFG_DRAM_TEST_WALK
+#endif /* CFG_DRAM_TEST */
+
+#undef CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
+#undef CFG_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
+
+#define CFG_LOAD_ADDR		0x00400000	/* default load address */
+
+#define CFG_HZ			1000		/* decr freq: 1ms ticks */
+/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
+#define CFG_BUS_HZ		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
+#define CFG_BUS_CLK		CFG_BUS_HZ
+
+#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
+#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */
+
+/*ronen - this is the Tclk (MV64360 core) */
+#define CFG_TCLK		133000000
+
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_750FX_HID0		0x8000c084
+#define CFG_750FX_HID1		0x54800000
+#define CFG_750FX_HID2		0x00000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+/*
+ * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
+ * To an unused memory region. The stack will remain in cache until RAM
+ * is initialized
+*/
+#define CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR	0x40000000 /* unused memory region */
+#define CFG_INIT_RAM_END	0x1000
+#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define RELOCATE_INTERNAL_RAM_ADDR
+#ifdef RELOCATE_INTERNAL_RAM_ADDR
+	#define CFG_INTERNAL_RAM_ADDR	0xf8000000
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+/* Dummies for BAT 4-7 */
+#define CFG_SDRAM1_BASE		0x10000000	/* each 256 MByte */
+#define CFG_SDRAM2_BASE		0x20000000
+#define CFG_SDRAM3_BASE		0x30000000
+#define CFG_SDRAM4_BASE		0x40000000
+#define CFG_FLASH_BASE			0xfff00000
+
+#define CFG_DFL_BOOTCS_BASE	0xff800000
+#define CONFIG_VERY_BIG_RAM		/* we will use up to 256M memory for cause we are short of BATS*/
+
+#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
+#define UART_BASE_BOOTM	      0xfbb00000 /* in order to be sync with the kernel parameters. */
+#define PCI0_IO_BASE_BOOTM    0xfd000000
+
+#define CFG_RESET_ADDRESS		0xfff00100
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+
+/* areas to map different things with the GT in physical space */
+#define CFG_DRAM_BANKS		4
+
+/* What to put in the bats. */
+#define CFG_MISC_REGION_BASE	0xf0000000
+
+/* Peripheral Device section */
+
+/*******************************************************/
+/* We have on the db64360 Board :		   */
+/* GT-Chipset Register Area				*/
+/* GT-Chipset internal SRAM 256k		    */
+/* SRAM on external device module		   */
+/* Real time clock on external device module	  */
+/* dobble UART on external device module	 */
+/* Data flash on external device module		    */
+/* Boot flash on external device module		    */
+/*******************************************************/
+#define CFG_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
+#define	 CFG_DB64360_RESET_ADDR 0x14000000				/* After power on Reset the DB64360 is here */
+
+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+#define CFG_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
+#define CFG_DEV_BASE		0xfc000000				/* GT Devices CS start here */
+
+#define CFG_DEV0_SPACE		CFG_DEV_BASE				/* DEV_CS0 device modul sram */
+#define CFG_DEV1_SPACE		(CFG_DEV0_SPACE + CFG_DEV0_SIZE)	/* DEV_CS1 device modul real time clock (rtc) */
+#define CFG_DEV2_SPACE		(CFG_DEV1_SPACE + CFG_DEV1_SIZE)	/* DEV_CS2 device modul doubel uart (duart) */
+#define CFG_DEV3_SPACE		(CFG_DEV2_SPACE + CFG_DEV2_SIZE)	/* DEV_CS3 device modul large flash */
+
+#define CFG_DEV0_SIZE		 _8M					/* db64360 sram	 @ 0xfc00.0000 */
+#define CFG_DEV1_SIZE		 _8M					/* db64360 rtc	 @ 0xfc80.0000 */
+#define CFG_DEV2_SIZE		_16M					/* db64360 duart @ 0xfd00.0000 */
+#define CFG_DEV3_SIZE		_16M					/* db64360 flash @ 0xfe00.0000 */
+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+
+/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
+#define CFG_DEV0_PAR		0x8FEFFFFF				/* 32Bit  sram */
+#define CFG_DEV1_PAR		0x8FCFFFFF				/* 8Bit	 rtc */
+#define CFG_DEV2_PAR		0x8FCFFFFF				/* 8Bit duart */
+#define CFG_8BIT_BOOT_PAR	0x8FCFFFFF				/* 8Bit flash */
+#define CFG_32BIT_BOOT_PAR	0x8FEFFFFF				/* 32Bit flash */
+
+	/*   c	  4    a      8	    2	  4    1      c		*/
+	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
+	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
+	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
+	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
+
+
+/* ronen - update MPP Control MV64360*/
+#define CFG_MPP_CONTROL_0	0x02222222
+#define CFG_MPP_CONTROL_1	0x11333011
+#define CFG_MPP_CONTROL_2	0x40431111
+#define CFG_MPP_CONTROL_3	0x00000044
+
+/*# define CFG_SERIAL_PORT_MUX	0x00000102	 0=hiZ	1=MPSC0 2=ETH 0 and 2 RMII */
+
+
+# define CFG_GPP_LEVEL_CONTROL	0x2c600000	/* 1111 1001 0000 1111 1100 0000 0000 0000*/
+							/* gpp[31]		gpp[30]		gpp[29]		gpp[28] */
+				/* gpp[27]			gpp[24]*/
+							/* gpp[19:14] */
+
+/* setup new config_value for MV64360 DDR-RAM !! */
+# define CFG_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
+
+#define CFG_DUART_IO		CFG_DEV2_SPACE
+#define CFG_DUART_CHAN		1		/* channel to use for console */
+#define CFG_INIT_CHAN1
+#define CFG_INIT_CHAN2
+
+#define SRAM_BASE		CFG_DEV0_SPACE
+#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_EEPRO100			/* ronen - Support for Intel 82557/82559/82559ER chips */
+
+/* PCI MEMORY MAP section */
+#define CFG_PCI0_MEM_BASE	0x80000000
+#define CFG_PCI0_MEM_SIZE	_128M
+#define CFG_PCI1_MEM_BASE	0x88000000
+#define CFG_PCI1_MEM_SIZE	_128M
+
+#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
+#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+
+/* PCI I/O MAP section */
+#define CFG_PCI0_IO_BASE	0xfa000000
+#define CFG_PCI0_IO_SIZE	_16M
+#define CFG_PCI1_IO_BASE	0xfb000000
+#define CFG_PCI1_IO_SIZE	_16M
+
+#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
+#define CFG_PCI0_IO_SPACE_PCI	(CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
+#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
+#define CFG_PCI1_IO_SPACE_PCI	(CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
+
+#if defined (CONFIG_750CX)
+#define CFG_PCI_IDSEL 0x0
+#else
+#define CFG_PCI_IDSEL 0x30
+#endif
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+
+/* SDRAM */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT0U CFG_IBAT0U
+
+/* init ram */
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+
+/* PCI0, PCI1 in one BAT */
+#define CFG_IBAT2L BATL_NO_ACCESS
+#define CFG_IBAT2U CFG_DBAT2U
+#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U CFG_IBAT3U
+
+/* I2C addresses for the two DIMM SPD chips */
+#define DIMM0_I2C_ADDR	0x56
+#define DIMM1_I2C_ADDR	0x54
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+
+#define CFG_EXTRA_FLASH_DEVICE	DEVICE3 /* extra flash at device 3 */
+#define CFG_EXTRA_FLASH_WIDTH	4	/* 32 bit */
+#define CFG_BOOT_FLASH_WIDTH	1	/* 8 bit */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
+#define CFG_FLASH_CFI		1
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CFG_ENV_ADDR	      0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
+/* #define CFG_ENV_ADDR	   (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/mpc74xx.h for the defines used here
+ */
+
+#define CFG_L2
+
+
+#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
+#define L2_INIT 0
+#else
+
+#define L2_INIT		0
+/*
+#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+*/
+#endif
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		    */
+
+#define CFG_BOARD_ASM_INIT	1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h
new file mode 100755
index 0000000..4b72e9b
--- /dev/null
+++ b/include/configs/DB64460.h
@@ -0,0 +1,534 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* This define must be before the core.h include */
+#define CONFIG_DB64460		1	/* this is an DB64460 board	*/
+
+#ifndef __ASSEMBLY__
+#include "../board/Marvell/include/core.h"
+#endif
+
+/*-----------------------------------------------------*/
+/*    #include "../board/db64460/local.h"	      */
+#ifndef __LOCAL_H
+#define __LOCAL_H
+
+#define CONFIG_ETHADDR		64:46:00:00:00:01
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		64:46:00:00:00:02
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR		64:46:00:00:00:03
+
+#define CONFIG_ENV_OVERWRITE
+#endif	/* __CONFIG_H */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_74xx			/* we have a 750FX (override local.h) */
+
+#define CONFIG_DB64460		1	/* this is an DB64460 board	*/
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115000	*/
+/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
+	DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
+	so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
+	see sdram_init.c   */
+#undef CONFIG_ECC	 /* enable ECC support */
+#define CONFIG_MV64460_ECC
+
+/* which initialization functions to call for this board */
+#define CONFIG_MISC_INIT_R     /* initialize the icache L1 */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CFG_BOARD_NAME		"DB64460"
+#define CONFIG_IDENT_STRING	"Marvell DB64460 (1.0)"
+
+/*#define CFG_HUSH_PARSER */
+#undef CFG_HUSH_PARSER
+
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * what to do:
+ * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
+ * cable onto the second DUART channel, change the CFG_DUART port from 1
+ * to 0 below.
+ *
+ * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
+ * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
+ */
+
+#define CONFIG_MPSC_PORT	0
+
+/* to change the default ethernet port, use this define (options: 0, 1, 2) */
+#define CONFIG_NET_MULTI
+#define MV_ETH_DEVS 3
+
+/* #undef CONFIG_ETHER_PORT_MII	 */
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+
+#undef	CONFIG_BOOTARGS
+/*#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
+
+/* ronen - autoboot using tftp */
+#if (CONFIG_BOOTDELAY >= 0)
+#define CONFIG_BOOTCOMMAND	"tftpboot 0x400000 uImage;\
+ setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
+ ip=${ipaddr}:${serverip}${bootargs_end};  bootm 0x400000; "
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200"
+
+#endif
+
+/* ronen - the u-boot.bin should be ~0x30000 bytes */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+     "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
+cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
+      "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
+cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
+      "bootargs_root=root=/dev/nfs rw\0" \
+      "bootargs_end=:::DB64460:eth0:none \0"\
+      "ethprime=mv_enet0\0"\
+      "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
+ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
+
+/* --------------------------------------------------------------------------------------------------------------- */
+/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */
+
+#define CONFIG_IPADDR		10.2.40.90
+
+#define CONFIG_SERIAL		"No. 1"
+#define CONFIG_SERVERIP		10.2.1.126
+#define CONFIG_ROOTPATH /mnt/yellow_dog_mini
+
+
+#define CONFIG_TESTDRAMDATA	y
+#define CONFIG_TESTDRAMADDRESS	n
+#define CONFIG_TESETDRAMWALK	n
+
+/* --------------------------------------------------------------------------------------------------------------- */
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
+#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_ALTIVEC			/* undef to disable		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor1"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor1=db64460-1"
+#define MTDPARTS_DEFAULT	"mtdparts=db64460-1:-(jffs2)"
+*/
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+			 | CFG_CMD_ASKENV \
+			 | CFG_CMD_I2C \
+			 | CFG_CMD_EEPROM \
+			 | CFG_CMD_CACHE \
+			 | CFG_CMD_JFFS2 \
+			 | CFG_CMD_PCI \
+			 | CFG_CMD_NET )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_SPEED	40000		/* I2C speed default */
+
+/* #define CFG_GT_DUAL_CPU	 also for JTAG even with one cpu */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/*#define CFG_MEMTEST_START	0x00400000	 memtest works on	*/
+/*#define CFG_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
+/*#define CFG_MEMTEST_END		0x07c00000	 4 ... 124 MB in DRAM	*/
+
+/*
+#define CFG_DRAM_TEST
+ * DRAM tests
+ *   CFG_DRAM_TEST - enables the following tests.
+ *
+ *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
+ *			  Environment variable 'test_dram_data' must be
+ *			  set to 'y'.
+ *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
+ *			  addressable. Environment variable
+ *			  'test_dram_address' must be set to 'y'.
+ *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
+ *			  This test takes about 6 minutes to test 64 MB.
+ *			  Environment variable 'test_dram_walk' must be
+ *			  set to 'y'.
+ */
+#define CFG_DRAM_TEST
+#if defined(CFG_DRAM_TEST)
+#define CFG_MEMTEST_START		0x00400000	/* memtest works on	*/
+/* #define CFG_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
+#define CFG_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
+#define CFG_DRAM_TEST_DATA
+#define CFG_DRAM_TEST_ADDRESS
+#define CFG_DRAM_TEST_WALK
+#endif /* CFG_DRAM_TEST */
+
+#undef CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
+#undef CFG_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
+
+#define CFG_LOAD_ADDR		0x00400000	/* default load address */
+
+#define CFG_HZ			1000		/* decr freq: 1ms ticks */
+/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
+#define CFG_BUS_HZ		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
+#define CFG_BUS_CLK		CFG_BUS_HZ
+
+#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
+#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */
+
+/*ronen - this is the Tclk (MV64460 core) */
+#define CFG_TCLK		133000000
+
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_750FX_HID0		0x8000c084
+#define CFG_750FX_HID1		0x54800000
+#define CFG_750FX_HID2		0x00000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+/*
+ * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
+ * To an unused memory region. The stack will remain in cache until RAM
+ * is initialized
+*/
+#define CFG_INIT_RAM_LOCK
+#define CFG_INIT_RAM_ADDR	0x40000000 /* unused memory region */
+#define CFG_INIT_RAM_END	0x1000
+#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#define RELOCATE_INTERNAL_RAM_ADDR
+#ifdef RELOCATE_INTERNAL_RAM_ADDR
+	#define CFG_INTERNAL_RAM_ADDR	0xf8000000
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+/* Dummies for BAT 4-7 */
+#define CFG_SDRAM1_BASE		0x10000000	/* each 256 MByte */
+#define CFG_SDRAM2_BASE		0x20000000
+#define CFG_SDRAM3_BASE		0x30000000
+#define CFG_SDRAM4_BASE		0x40000000
+#define CFG_FLASH_BASE			0xfff00000
+
+#define CFG_DFL_BOOTCS_BASE	0xff800000
+#define CONFIG_VERY_BIG_RAM		/* we will use up to 256M memory for cause we are short of BATS*/
+
+#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
+#define UART_BASE_BOOTM	      0xfbb00000 /* in order to be sync with the kernel parameters. */
+#define PCI0_IO_BASE_BOOTM    0xfd000000
+
+#define CFG_RESET_ADDRESS		0xfff00100
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+
+/* areas to map different things with the GT in physical space */
+#define CFG_DRAM_BANKS		4
+
+/* What to put in the bats. */
+#define CFG_MISC_REGION_BASE	0xf0000000
+
+/* Peripheral Device section */
+
+/*******************************************************/
+/* We have on the db64460 Board :		   */
+/* GT-Chipset Register Area				*/
+/* GT-Chipset internal SRAM 256k		    */
+/* SRAM on external device module		   */
+/* Real time clock on external device module	  */
+/* dobble UART on external device module	 */
+/* Data flash on external device module		    */
+/* Boot flash on external device module		    */
+/*******************************************************/
+#define CFG_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
+#define	 CFG_DB64460_RESET_ADDR 0x14000000				/* After power on Reset the DB64460 is here */
+
+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+#define CFG_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
+#define CFG_DEV_BASE		0xfc000000				/* GT Devices CS start here */
+
+#define CFG_DEV0_SPACE		CFG_DEV_BASE				/* DEV_CS0 device modul sram */
+#define CFG_DEV1_SPACE		(CFG_DEV0_SPACE + CFG_DEV0_SIZE)	/* DEV_CS1 device modul real time clock (rtc) */
+#define CFG_DEV2_SPACE		(CFG_DEV1_SPACE + CFG_DEV1_SIZE)	/* DEV_CS2 device modul doubel uart (duart) */
+#define CFG_DEV3_SPACE		(CFG_DEV2_SPACE + CFG_DEV2_SIZE)	/* DEV_CS3 device modul large flash */
+
+#define CFG_DEV0_SIZE		 _8M					/* db64460 sram	 @ 0xfc00.0000 */
+#define CFG_DEV1_SIZE		 _8M					/* db64460 rtc	 @ 0xfc80.0000 */
+#define CFG_DEV2_SIZE		_16M					/* db64460 duart @ 0xfd00.0000 */
+#define CFG_DEV3_SIZE		_16M					/* db64460 flash @ 0xfe00.0000 */
+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+
+/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
+#define CFG_DEV0_PAR		0x8FEFFFFF				/* 32Bit  sram */
+#define CFG_DEV1_PAR		0x8FCFFFFF				/* 8Bit	 rtc */
+#define CFG_DEV2_PAR		0x8FCFFFFF				/* 8Bit duart */
+#define CFG_8BIT_BOOT_PAR	0x8FCFFFFF				/* 8Bit flash */
+#define CFG_32BIT_BOOT_PAR	0x8FEFFFFF				/* 32Bit flash */
+
+	/*   c	  4    a      8	    2	  4    1      c		*/
+	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
+	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
+	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
+	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
+
+
+/* ronen - update MPP Control MV64460*/
+#define CFG_MPP_CONTROL_0	0x02222222
+#define CFG_MPP_CONTROL_1	0x11333011
+#define CFG_MPP_CONTROL_2	0x40431111
+#define CFG_MPP_CONTROL_3	0x00000044
+
+/*# define CFG_SERIAL_PORT_MUX	0x00000102	 0=hiZ	1=MPSC0 2=ETH 0 and 2 RMII */
+
+
+# define CFG_GPP_LEVEL_CONTROL	0x2c600000	/* 1111 1001 0000 1111 1100 0000 0000 0000*/
+							/* gpp[31]		gpp[30]		gpp[29]		gpp[28] */
+				/* gpp[27]			gpp[24]*/
+							/* gpp[19:14] */
+
+/* setup new config_value for MV64460 DDR-RAM !! */
+# define CFG_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
+
+#define CFG_DUART_IO		CFG_DEV2_SPACE
+#define CFG_DUART_CHAN		1		/* channel to use for console */
+#define CFG_INIT_CHAN1
+#define CFG_INIT_CHAN2
+
+#define SRAM_BASE		CFG_DEV0_SPACE
+#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_EEPRO100			/* ronen - Support for Intel 82557/82559/82559ER chips */
+
+/* PCI MEMORY MAP section */
+#define CFG_PCI0_MEM_BASE	0x80000000
+#define CFG_PCI0_MEM_SIZE	_128M
+#define CFG_PCI1_MEM_BASE	0x88000000
+#define CFG_PCI1_MEM_SIZE	_128M
+
+#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
+#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+
+/* PCI I/O MAP section */
+#define CFG_PCI0_IO_BASE	0xfa000000
+#define CFG_PCI0_IO_SIZE	_16M
+#define CFG_PCI1_IO_BASE	0xfb000000
+#define CFG_PCI1_IO_SIZE	_16M
+
+#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
+#define CFG_PCI0_IO_SPACE_PCI	(CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
+#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
+#define CFG_PCI1_IO_SPACE_PCI	(CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
+
+#if defined (CONFIG_750CX)
+#define CFG_PCI_IDSEL 0x0
+#else
+#define CFG_PCI_IDSEL 0x30
+#endif
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+
+/* SDRAM */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT0U CFG_IBAT0U
+
+/* init ram */
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+
+/* PCI0, PCI1 in one BAT */
+#define CFG_IBAT2L BATL_NO_ACCESS
+#define CFG_IBAT2U CFG_DBAT2U
+#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U CFG_IBAT3U
+
+/* I2C addresses for the two DIMM SPD chips */
+#define DIMM0_I2C_ADDR	0x56
+#define DIMM1_I2C_ADDR	0x54
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+
+#define CFG_EXTRA_FLASH_DEVICE	DEVICE3 /* extra flash at device 3 */
+#define CFG_EXTRA_FLASH_WIDTH	4	/* 32 bit */
+#define CFG_BOOT_FLASH_WIDTH	1	/* 8 bit */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
+#define CFG_FLASH_CFI		1
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CFG_ENV_ADDR	      0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
+/* #define CFG_ENV_ADDR	   (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/mpc74xx.h for the defines used here
+ */
+
+#define CFG_L2
+
+
+#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
+#define L2_INIT 0
+#else
+
+#define L2_INIT		0
+/*
+#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+*/
+#endif
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		    */
+
+#define CFG_BOARD_ASM_INIT	1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h
new file mode 100755
index 0000000..b58846d
--- /dev/null
+++ b/include/configs/DK1C20.h
@@ -0,0 +1,556 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * CompactFlash/IDE:
+ * (C) Copyright 2004, Shlomo Kut <skut@vyyo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/***********************************************************************
+ * Include the whole NIOS CPU configuration.
+ *
+ * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
+ *
+ ***********************************************************************/
+
+#if	defined(CONFIG_NIOS_SAFE_32)
+#include <configs/DK1C20_safe_32.h>
+#elif	defined(CONFIG_NIOS_STANDARD_32)
+#include <configs/DK1C20_standard_32.h>
+#else
+#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
+#endif
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU -- TOP-LEVEL
+ *----------------------------------------------------------------------*/
+#define CONFIG_NIOS		1		/* NIOS-32 core		*/
+#define	CONFIG_DK1C20		1		/* Cyclone DK-1C20 board*/
+#define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/
+#define	CFG_HZ			1000		/* 1 msec time tick	*/
+#undef  CFG_CLKS_IN_HZ
+#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
+
+/*------------------------------------------------------------------------
+ * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_SDRAM_SIZE != 0)
+
+#define CFG_SDRAM_BASE		CFG_NIOS_CPU_SDRAM_BASE
+#define CFG_SDRAM_SIZE		CFG_NIOS_CPU_SDRAM_SIZE
+
+#else
+#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
+#endif
+
+#define CFG_SRAM_BASE		CFG_NIOS_CPU_SRAM_BASE
+#define CFG_SRAM_SIZE		CFG_NIOS_CPU_SRAM_SIZE
+#define CFG_VECT_BASE		CFG_NIOS_CPU_VEC_BASE
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION - For the most part, you can put things pretty
+ * much anywhere. This is pretty flexible for Nios. So here we make some
+ * arbitrary choices & assume that the monitor is placed at the end of
+ * a memory resource (so you must make sure TEXT_BASE is chosen
+ * appropriately).
+ *
+ * 	-The heap is placed below the monitor.
+ * 	-Global data is placed below the heap.
+ * 	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
+#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
+
+#define CFG_FLASH_BASE		CFG_NIOS_CPU_FLASH_BASE
+#define CFG_FLASH_SIZE		CFG_NIOS_CPU_FLASH_SIZE
+#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
+
+#else
+#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
+#endif
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
+
+#define	CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+#define CFG_ENV_ADDR		CFG_FLASH_BASE	/* Mem addr of env	*/
+#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial/eth change Ok */
+
+#else
+#define	CFG_ENV_IS_NOWHERE	1		/* NO Environment	*/
+#endif
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_UART_NUMS != 0)
+
+#define CFG_NIOS_CONSOLE	CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
+
+#if	(CFG_NIOS_CPU_UART0_BR != 0)
+#define CFG_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		CFG_NIOS_CPU_UART0_BR
+#else
+#undef	CFG_NIOS_FIXEDBAUD
+#define CONFIG_BAUDRATE		115200
+#endif
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#else
+#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
+#endif
+
+/*------------------------------------------------------------------------
+ * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
+ * so an avalon bus timer is required.
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_TIMER_NUMS != 0)
+
+#if	(CFG_NIOS_CPU_TICK_TIMER == 0)
+
+#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
+#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER0_IRQ
+
+#if	(CFG_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */
+
+#if	(CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
+#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
+#else
+#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#endif
+
+#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
+
+#elif	(CFG_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */
+
+#if	(CFG_HZ <= 1000)
+#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
+#else
+#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#endif
+
+#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
+
+#else
+#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
+#endif
+
+#elif	(CFG_NIOS_CPU_TICK_TIMER == 1)
+
+#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
+#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER1_IRQ
+
+#if	(CFG_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */
+
+#if	(CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
+#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
+#else
+#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#endif
+
+#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
+
+#elif	(CFG_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */
+
+#if	(CFG_HZ <= 1000)
+#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
+#else
+#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#endif
+
+#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
+
+#else
+#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
+#endif
+
+#endif	/* CFG_NIOS_CPU_TICK_TIMER */
+
+#else
+#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
+#endif
+
+/*------------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_LAN_NUMS == 1)
+
+#if	(CFG_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/
+
+#define	CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
+#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
+#define	CONFIG_SMC91111_BASE	(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
+
+#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
+#define	CONFIG_SMC_USE_32_BIT	1
+#else	/* no */
+#undef	CONFIG_SMC_USE_32_BIT
+#endif
+
+#elif	(CFG_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/
+
+	/********************************************/
+	/* !!! CS8900 is __not__ tested on NIOS !!! */
+	/********************************************/
+#define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/
+#define	CS8900_BASE		(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
+
+#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
+#undef	CS8900_BUS16
+#define	CS8900_BUS32		1
+#else	/* no */
+#define	CS8900_BUS16		1
+#undef	CS8900_BUS32
+#endif
+
+#else
+#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
+#endif
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.2.21
+#define CONFIG_SERVERIP		192.168.2.16
+
+#else
+#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
+#endif
+
+/*------------------------------------------------------------------------
+ * STATUS LEDs
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_PIO_NUMS != 0)
+
+#if	(CFG_NIOS_CPU_LED_PIO == 0)
+
+#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 1)
+
+#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 2)
+
+#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO2
+#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO2_BITS
+#define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
+
+#if	(CFG_NIOS_CPU_PIO2_TYPE == 1)
+#define	STATUS_LED_WRONLY		1
+#else
+#undef	STATUS_LED_WRONLY
+#endif
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 3)
+
+#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 4)
+
+#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 5)
+
+#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 6)
+
+#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 7)
+
+#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 8)
+
+#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 9)
+
+#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
+
+#else
+#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
+#endif
+
+#define	CONFIG_STATUS_LED		1 /* enable status led driver */
+
+#define	STATUS_LED_BIT			(1 << 0)	/* LED[0] */
+#define	STATUS_LED_STATE		STATUS_LED_BLINKING
+#define	STATUS_LED_BOOT_STATE		STATUS_LED_OFF
+#define	STATUS_LED_PERIOD		(CFG_HZ / 10)	/* ca. 1 Hz */
+#define	STATUS_LED_BOOT			0		/* boot LED */
+
+#if	(STATUS_LED_BITS > 1)
+#define	STATUS_LED_BIT1			(1 << 1)	/* LED[1] */
+#define	STATUS_LED_STATE1		STATUS_LED_OFF
+#define	STATUS_LED_PERIOD1		(CFG_HZ / 50)	/* ca. 5 Hz */
+#define	STATUS_LED_RED			1		/* fail LED */
+#endif
+
+#if	(STATUS_LED_BITS > 2)
+#define	STATUS_LED_BIT2			(1 << 2)	/* LED[2] */
+#define	STATUS_LED_STATE2		STATUS_LED_OFF
+#define	STATUS_LED_PERIOD2		(CFG_HZ / 10)	/* ca. 1 Hz */
+#define	STATUS_LED_YELLOW		2		/* info LED */
+#endif
+
+#if	(STATUS_LED_BITS > 3)
+#define	STATUS_LED_BIT3			(1 << 3)	/* LED[3] */
+#define	STATUS_LED_STATE3		STATUS_LED_OFF
+#define	STATUS_LED_PERIOD3		(CFG_HZ / 10)	/* ca. 1 Hz */
+#define	STATUS_LED_GREEN		3		/* info LED */
+#endif
+
+#define	STATUS_LED_PAR			1 /* makes status_led.h happy */
+
+#endif	/* CFG_NIOS_CPU_PIO_NUMS */
+
+/*------------------------------------------------------------------------
+ * SEVEN SEGMENT LED DISPLAY
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_PIO_NUMS != 0)
+
+#if	(CFG_NIOS_CPU_SEVENSEG_PIO == 0)
+
+#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 1)
+
+#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 2)
+
+#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 3)
+
+#define	SEVENSEG_BASE			CFG_NIOS_CPU_PIO3
+#define	SEVENSEG_BITS			CFG_NIOS_CPU_PIO3_BITS
+#define	SEVENSEG_ACTIVE			0 /* LED on for bit == 1 */
+
+#if	(CFG_NIOS_CPU_PIO3_TYPE == 1)
+#define	SEVENSEG_WRONLY			1
+#else
+#undef	SEVENSEG_WRONLY
+#endif
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 4)
+
+#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 5)
+
+#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 6)
+
+#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 7)
+
+#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 8)
+
+#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 9)
+
+#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h
+
+#else
+#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
+#endif
+
+#define	CONFIG_SEVENSEG			1 /* enable seven segment led driver */
+
+/*
+ * Dual 7-Segment Display pin assignment -- read more in your
+ * "Nios Development Board Reference Manual"
+ *
+ *
+ *    (U8) HI:D[15..8]     (U9) LO:D[7..0]
+ *         ______               ______
+ *        |  D14 |             |  D6  |
+ *        |      |             |      |
+ *      D9|      |D13        D1|      |D5
+ *        |______|             |______|                  ___
+ *        |  D8  |             |  D0  |                 | A |
+ *        |      |             |      |                F|___|B
+ *     D10|      |D12        D2|      |D4               | G |
+ *        |______|             |______|                E|___|C
+ *           D11  *               D3   *                  D  *
+ *                D15                  D7                    DP
+ *
+ */
+#define	SEVENSEG_DIGIT_HI_LO_EQUAL	1	/* high nibble equal low nibble */
+#define	SEVENSEG_DIGIT_A		(1 << 6) /* bit 6 is segment A */
+#define	SEVENSEG_DIGIT_B		(1 << 5) /* bit 5 is segment B */
+#define	SEVENSEG_DIGIT_C		(1 << 4) /* bit 4 is segment C */
+#define	SEVENSEG_DIGIT_D		(1 << 3) /* bit 3 is segment D */
+#define	SEVENSEG_DIGIT_E		(1 << 2) /* bit 2 is segment E */
+#define	SEVENSEG_DIGIT_F		(1 << 1) /* bit 1 is segment F */
+#define	SEVENSEG_DIGIT_G		(1 << 0) /* bit 0 is segment G */
+#define	SEVENSEG_DIGIT_DP		(1 << 7) /* bit 7 is decimal point */
+
+#endif	/* CFG_NIOS_CPU_PIO_NUMS */
+
+/*------------------------------------------------------------------------
+ * ASMI - Active Serial Memory Interface.
+ *
+ * ASMI is for Cyclone devices only and only works when the configuration
+ * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details.
+ *----------------------------------------------------------------------*/
+#define CONFIG_NIOS_ASMI			   /* Enable ASMI	*/
+#define CFG_NIOS_ASMIBASE	CFG_NIOS_CPU_ASMI0 /* ASMI base address	*/
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
+				 CFG_CMD_ASKENV | \
+				 CFG_CMD_BEDBUG | \
+				 CFG_CMD_BMP	| \
+				 CFG_CMD_BSP	| \
+				 CFG_CMD_CACHE	| \
+				 CFG_CMD_DATE	| \
+				 CFG_CMD_DOC	| \
+				 CFG_CMD_DTT	| \
+				 CFG_CMD_EEPROM | \
+				 CFG_CMD_ELF    | \
+				 CFG_CMD_FDC	| \
+				 CFG_CMD_FDOS	| \
+				 CFG_CMD_HWFLOW	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_JFFS2	| \
+				 CFG_CMD_KGDB	| \
+				 CFG_CMD_NAND	| \
+				 CFG_CMD_NFS	| \
+				 CFG_CMD_MMC	| \
+				 CFG_CMD_MII	| \
+				 CFG_CMD_PCI	| \
+				 CFG_CMD_PCMCIA | \
+				 CFG_CMD_REISER	| \
+				 CFG_CMD_SCSI	| \
+				 CFG_CMD_SPI	| \
+				 CFG_CMD_VFD	| \
+				 CFG_CMD_USB	| \
+				 CFG_CMD_XIMG	) )
+
+
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * COMPACT FLASH
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define CONFIG_IDE_PREINIT			/* Implement id_preinit	*/
+#define CFG_IDE_MAXBUS		1		/* 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1		/* 1 drive per IDE bus	*/
+
+#define CFG_ATA_BASE_ADDR	0x00920a00	/* IDE/ATA base addr	*/
+#define CFG_ATA_IDE0_OFFSET	0x0000		/* IDE0 offset		*/
+#define CFG_ATA_DATA_OFFSET	0x0040		/* Data IO offset	*/
+#define CFG_ATA_REG_OFFSET	0x0040		/* Register offset	*/
+#define CFG_ATA_ALT_OFFSET	0x0100		/* Alternate reg offset	*/
+#define CFG_ATA_STRIDE          4		/* Width betwix addrs	*/
+#define CONFIG_DOS_PARTITION
+
+/* Board-specific cf regs */
+#define CFG_CF_PRESENT		0x009209b0	/* CF Present PIO base	*/
+#define CFG_CF_POWER		0x009209c0	/* CF Power FET PIO base*/
+#define CFG_CF_ATASEL		0x009209d0	/* CF ATASEL PIO base	*/
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */
+
+/*------------------------------------------------------------------------
+ * KGDB
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	9600
+#endif
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define	CFG_LONGHELP			    /* undef to save memory	*/
+#define	CFG_PROMPT		"DK1C20 > " /* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	    /* max number of command args*/
+#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */
+
+#if	(CFG_SRAM_SIZE != 0)
+#define	CFG_LOAD_ADDR		CFG_SRAM_BASE	/* Default load address	*/
+#else
+#undef	CFG_LOAD_ADDR
+#endif
+
+#if	(CFG_SDRAM_SIZE != 0)
+#define	CFG_MEMTEST_START	CFG_SDRAM_BASE	/* SDRAM til stack area */
+#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */
+#else
+#undef	CFG_MEMTEST_START
+#undef	CFG_MEMTEST_END
+#endif
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		""
+#define MTDPARTS_DEFAULT	""
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/DK1C20_safe_32.h b/include/configs/DK1C20_safe_32.h
new file mode 100755
index 0000000..a483e87
--- /dev/null
+++ b/include/configs/DK1C20_safe_32.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_DK1C20_SAFE_32_H
+#define __CONFIG_DK1C20_SAFE_32_H
+
+/*
+ * NIOS CPU configuration. (PART OF configs/DK1C20.h)
+ *
+ * !!! TODO !!! TODO !!!
+ */
+#error *** CFG_ERROR: DK1C20_safe_32 have to be defined (use DK1C20_standard_32 as template)
+
+#endif	/* __CONFIG_DK1C20_SAFE_32_H */
diff --git a/include/configs/DK1C20_standard_32.h b/include/configs/DK1C20_standard_32.h
new file mode 100755
index 0000000..ed08121
--- /dev/null
+++ b/include/configs/DK1C20_standard_32.h
@@ -0,0 +1,279 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_DK1C20_STANDARD_32_H
+#define __CONFIG_DK1C20_STANDARD_32_H
+
+/*
+ * NIOS CPU configuration. (PART OF configs/DK1C20.h)
+ *
+ * Here we must define CPU dependencies. Any unsupported option have to
+ * be defined with zero, example CPU without data cache / OCI:
+ *
+ *	#define	CFG_NIOS_CPU_ICACHE	4096
+ *	#define	CFG_NIOS_CPU_DCACHE	0
+ *	#define	CFG_NIOS_CPU_OCI_BASE	0
+ *	#define	CFG_NIOS_CPU_OCI_SIZE	0
+ */
+
+/* CPU core */
+#define	CFG_NIOS_CPU_CLK	50000000	/* NIOS CPU clock	*/
+#define	CFG_NIOS_CPU_ICACHE	(4 * 1024)	/* instruction cache	*/
+#define	CFG_NIOS_CPU_DCACHE	(4 * 1024)	/* data cache		*/
+#define	CFG_NIOS_CPU_REG_NUMS	256		/* number of register	*/
+#define	CFG_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_STACK	0x008fff00	/* stack top	addr	*/
+#define	CFG_NIOS_CPU_VEC_BASE	0x008fff00	/* IRQ vectors	addr	*/
+#define	CFG_NIOS_CPU_VEC_SIZE	256		/*		size	*/
+#define	CFG_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
+#define	CFG_NIOS_CPU_RST_VECT	0x00920000	/* RESET vector	addr	*/
+#define	CFG_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
+						/*		yes(1)	*/
+
+/* on-chip extensions */
+#define	CFG_NIOS_CPU_RAM_BASE	0		/* on chip RAM	addr	*/
+#define	CFG_NIOS_CPU_RAM_SIZE	0		/*		size	*/
+
+#define	CFG_NIOS_CPU_ROM_BASE	0x00920000	/* on chip ROM	addr	*/
+#define	CFG_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
+
+#define	CFG_NIOS_CPU_OCI_BASE	0x00920800	/* OCI core	addr	*/
+#define	CFG_NIOS_CPU_OCI_SIZE	256		/*		size	*/
+
+/* timer */
+#define	CFG_NIOS_CPU_TIMER_NUMS	2		/* number of timer	*/
+
+#define	CFG_NIOS_CPU_TIMER0	0x00920940	/* TIMER0	addr	*/
+#define	CFG_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
+#define	CFG_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
+#define	CFG_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
+						/*		yes(1)	*/
+
+#define	CFG_NIOS_CPU_TIMER1	0x009209e0	/* TIMER1	addr	*/
+#define	CFG_NIOS_CPU_TIMER1_IRQ	50		/*		IRQ	*/
+#define	CFG_NIOS_CPU_TIMER1_PER	10000		/*  periode	usec	*/
+#define	CFG_NIOS_CPU_TIMER1_AR	1		/*  always run:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_TIMER1_FP	1		/*  fixed per:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_TIMER1_SS	0		/*  snaphot:	no(0)	*/
+						/*		yes(1)	*/
+
+/* serial i/o */
+#define	CFG_NIOS_CPU_UART_NUMS	1		/* number of uarts	*/
+
+#define	CFG_NIOS_CPU_UART0	0x00920900	/* UART0	addr	*/
+#define	CFG_NIOS_CPU_UART0_IRQ	25		/*		IRQ	*/
+#define	CFG_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
+#define	CFG_NIOS_CPU_UART0_DB	8		/*  data bit		*/
+#define	CFG_NIOS_CPU_UART0_SB	1		/*  stop bit		*/
+#define	CFG_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
+						/*		odd(1)	*/
+						/*		even(2)	*/
+#define	CFG_NIOS_CPU_UART0_HS	0		/*  handshake:	no(0)	*/
+						/*		crts(1)	*/
+#define	CFG_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
+						/*		yes(1)	*/
+
+/* parallel i/o */
+#define	CFG_NIOS_CPU_PIO_NUMS	8		/* number of parports	*/
+
+#define	CFG_NIOS_CPU_PIO0	0x00920960	/* PIO0		addr	*/
+#define	CFG_NIOS_CPU_PIO0_IRQ	40		/*		IRQ	*/
+#define	CFG_NIOS_CPU_PIO0_BITS	4		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO0_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO0_CAP	1		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO0_EDGE	3		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO0_ITYPE	2		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO1	0x00920970	/* PIO1		addr	*/
+#undef	CFG_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO1_BITS	11		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO1_TYPE	0		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO2	0x00920980	/* PIO2		addr	*/
+#undef	CFG_NIOS_CPU_PIO2_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO2_BITS	8		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO2_TYPE	1		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO2_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO2_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO2_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO3	0x00920990	/* PIO3		addr	*/
+#undef	CFG_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO3_BITS	16		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO3_TYPE	1		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO4	0x009209a0	/* PIO4		addr	*/
+#undef	CFG_NIOS_CPU_PIO4_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO4_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO4_TYPE	0		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO4_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO4_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO4_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO5	0x009209b0	/* PIO5		addr	*/
+#define	CFG_NIOS_CPU_PIO5_IRQ	35		/*		IRQ	*/
+#define	CFG_NIOS_CPU_PIO5_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO5_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO5_CAP	1		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO5_EDGE	3		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO5_ITYPE	2		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO6	0x009209c0	/* PIO6		addr	*/
+#undef	CFG_NIOS_CPU_PIO6_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO6_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO6_TYPE	1		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO6_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO6_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO6_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO7	0x009209d0	/* PIO7		addr	*/
+#undef	CFG_NIOS_CPU_PIO7_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO7_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO7_TYPE	1		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO7_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO7_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO7_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+/* IDE i/f */
+#define	CFG_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
+#define	CFG_NIOS_CPU_IDE0	0x00920a00	/* IDE0		addr	*/
+
+/* active serial memory i/f */
+#define	CFG_NIOS_CPU_ASMI_NUMS	1		/* number of ASMI	*/
+#define	CFG_NIOS_CPU_ASMI0	0x00920b00	/* ASMI0	addr	*/
+#define	CFG_NIOS_CPU_ASMI0_IRQ	45		/*		IRQ	*/
+
+/* memory accessibility */
+#define	CFG_NIOS_CPU_SRAM_BASE	0x00800000	/* board SRAM	addr	*/
+#define	CFG_NIOS_CPU_SRAM_SIZE	(1024 * 1024)	/*  1 MB	size	*/
+
+#define	CFG_NIOS_CPU_SDRAM_BASE	0x01000000	/* board SDRAM	addr	*/
+#define	CFG_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
+
+#define	CFG_NIOS_CPU_FLASH_BASE	0x00000000	/* board Flash	addr	*/
+#define	CFG_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
+
+/* LAN */
+#define	CFG_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
+
+#define	CFG_NIOS_CPU_LAN0_BASE	0x00910000	/* LAN0		addr	*/
+#define	CFG_NIOS_CPU_LAN0_OFFS	0x0300		/*		offset	*/
+#define	CFG_NIOS_CPU_LAN0_IRQ	30		/*		IRQ	*/
+#define	CFG_NIOS_CPU_LAN0_BUSW	32		/*	        buswidth*/
+#define	CFG_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
+						/*	cs8900(1)	*/
+						/* ex:	alteramac(2)	*/
+
+/* symbolic redefinition (undef, if not present) */
+#define	CFG_NIOS_CPU_USER_TIMER		0	/* TIMER0: users choice	*/
+#define	CFG_NIOS_CPU_TICK_TIMER		1	/* TIMER1: tick (needed)*/
+
+#define	CFG_NIOS_CPU_BUTTON_PIO		0	/* PIO0: buttons	*/
+#define	CFG_NIOS_CPU_LCD_PIO		1	/* PIO1: ASCII LCD	*/
+#define	CFG_NIOS_CPU_LED_PIO		2	/* PIO2: LED bar	*/
+#define	CFG_NIOS_CPU_SEVENSEG_PIO	3	/* PIO3: 7-seg. display	*/
+#define	CFG_NIOS_CPU_RECONF_PIO		4	/* PIO4: reconf pin	*/
+#define	CFG_NIOS_CPU_CFPRESENT_PIO	5	/* PIO5: CF present IRQ	*/
+#define	CFG_NIOS_CPU_CFPOWER_PIO	6	/* PIO6: CF power/sw.	*/
+#define	CFG_NIOS_CPU_CFATASEL_PIO	7	/* PIO7: CF ATA select	*/
+
+#endif	/* __CONFIG_DK1C20_STANDARD_32_H */
diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h
new file mode 100755
index 0000000..3e3803c
--- /dev/null
+++ b/include/configs/DK1S10.h
@@ -0,0 +1,565 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/***********************************************************************
+ * Include the whole NIOS CPU configuration.
+ *
+ * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
+ *
+ ***********************************************************************/
+
+#if	defined(CONFIG_NIOS_SAFE_32)
+#include <configs/DK1S10_safe_32.h>
+#elif	defined(CONFIG_NIOS_STANDARD_32)
+#include <configs/DK1S10_standard_32.h>
+#elif	defined(CONFIG_NIOS_MTX_LDK_20)
+#include <configs/DK1S10_mtx_ldk_20.h>
+#else
+#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
+#endif
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU -- TOP-LEVEL
+ *----------------------------------------------------------------------*/
+#define CONFIG_NIOS		1		/* NIOS-32 core		*/
+#define	CONFIG_DK1S10		1		/* Stratix DK-1S10 board*/
+#define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/
+#define	CFG_HZ			1000		/* 1 msec time tick	*/
+#undef  CFG_CLKS_IN_HZ
+#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
+
+/*------------------------------------------------------------------------
+ * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_SDRAM_SIZE != 0)
+
+#define CFG_SDRAM_BASE		CFG_NIOS_CPU_SDRAM_BASE
+#define CFG_SDRAM_SIZE		CFG_NIOS_CPU_SDRAM_SIZE
+
+#else
+#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
+#endif
+
+#if	defined(CFG_NIOS_CPU_SRAM_BASE) && defined(CFG_NIOS_CPU_SRAM_SIZE)
+
+#define	CFG_SRAM_BASE		CFG_NIOS_CPU_SRAM_BASE
+#define	CFG_SRAM_SIZE		CFG_NIOS_CPU_SRAM_SIZE
+
+#else
+
+#undef	CFG_SRAM_BASE
+#undef	CFG_SRAM_SIZE
+
+#endif
+
+#define CFG_VECT_BASE		CFG_NIOS_CPU_VEC_BASE
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION - For the most part, you can put things pretty
+ * much anywhere. This is pretty flexible for Nios. So here we make some
+ * arbitrary choices & assume that the monitor is placed at the end of
+ * a memory resource (so you must make sure TEXT_BASE is chosen
+ * appropriately).
+ *
+ * 	-The heap is placed below the monitor.
+ * 	-Global data is placed below the heap.
+ * 	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
+#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
+
+#define CFG_FLASH_BASE		CFG_NIOS_CPU_FLASH_BASE
+#define CFG_FLASH_SIZE		CFG_NIOS_CPU_FLASH_SIZE
+#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
+
+#else
+#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
+#endif
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)
+
+#define	CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+
+#if	defined(CONFIG_NIOS_STANDARD_32)
+#define CFG_ENV_ADDR		CFG_FLASH_BASE	/* Mem addr of env	*/
+#elif	defined(CONFIG_NIOS_MTX_LDK_20)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+#else
+#error *** CFG_ERROR: you have to setup the environment base address CFG_ENV_ADDR
+#endif
+
+#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial/eth change Ok */
+
+#else
+#define	CFG_ENV_IS_NOWHERE	1		/* NO Environment	*/
+#endif
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_UART_NUMS != 0)
+
+#define CFG_NIOS_CONSOLE	CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
+#define CONFIG_LOADS_ECHO	1	 /* echo on for serial download */
+
+#if	(CFG_NIOS_CPU_UART0_BR != 0)
+#define CFG_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		CFG_NIOS_CPU_UART0_BR
+#else
+#undef	CFG_NIOS_FIXEDBAUD
+#define CONFIG_BAUDRATE		115200
+#endif
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#else
+#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
+#endif
+
+/*------------------------------------------------------------------------
+ * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
+ * so an avalon bus timer is required.
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_TIMER_NUMS != 0) && defined(CFG_NIOS_CPU_TICK_TIMER)
+
+#if	(CFG_NIOS_CPU_TICK_TIMER == 0)
+
+#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/
+#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER0_IRQ
+
+#if	(CFG_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */
+
+#if	(CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
+#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
+#else
+#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#endif
+
+#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
+
+#elif	(CFG_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */
+
+#if	(CFG_HZ <= 1000)
+#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
+#else
+#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#endif
+
+#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
+
+#else
+#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
+#endif
+
+#elif	(CFG_NIOS_CPU_TICK_TIMER == 1)
+
+#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/
+#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER1_IRQ
+
+#if	(CFG_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */
+
+#if	(CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
+#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
+#else
+#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#endif
+
+#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */
+
+#elif	(CFG_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */
+
+#if	(CFG_HZ <= 1000)
+#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)
+#else
+#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#endif
+
+#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)
+
+#else
+#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
+#endif
+
+#endif	/* CFG_NIOS_CPU_TICK_TIMER */
+
+#else
+#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
+#endif
+
+/*------------------------------------------------------------------------
+ * Ethernet -- needs work!
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_LAN_NUMS == 1)
+
+#if	(CFG_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/
+
+#define	CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
+#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
+#define	CONFIG_SMC91111_BASE	(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
+
+#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
+#define	CONFIG_SMC_USE_32_BIT	1
+#else	/* no */
+#undef	CONFIG_SMC_USE_32_BIT
+#endif
+
+#elif	(CFG_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/
+
+	/********************************************/
+	/* !!! CS8900 is __not__ tested on NIOS !!! */
+	/********************************************/
+#define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/
+#define	CS8900_BASE		(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
+
+#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)
+#undef	CS8900_BUS16
+#define	CS8900_BUS32		1
+#else	/* no */
+#define	CS8900_BUS16		1
+#undef	CS8900_BUS32
+#endif
+
+#else
+#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
+#endif
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.2.21
+#define CONFIG_SERVERIP		192.168.2.16
+
+#else
+#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
+#endif
+
+/*------------------------------------------------------------------------
+ * STATUS LEDs
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_LED_PIO)
+
+#if	(CFG_NIOS_CPU_LED_PIO == 0)
+
+#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 1)
+
+#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 2)
+
+#define	STATUS_LED_BASE			CFG_NIOS_CPU_PIO2
+#define	STATUS_LED_BITS			CFG_NIOS_CPU_PIO2_BITS
+#define	STATUS_LED_ACTIVE		1 /* LED on for bit == 1 */
+
+#if	(CFG_NIOS_CPU_PIO2_TYPE == 1)
+#define	STATUS_LED_WRONLY		1
+#else
+#undef	STATUS_LED_WRONLY
+#endif
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 3)
+
+#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 4)
+
+#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 5)
+
+#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 6)
+
+#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 7)
+
+#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 8)
+
+#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_LED_PIO == 9)
+
+#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
+
+#else
+#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
+#endif
+
+#define	CONFIG_STATUS_LED		1 /* enable status led driver */
+
+#define	STATUS_LED_BIT			(1 << 0)	/* LED[0] */
+#define	STATUS_LED_STATE		STATUS_LED_BLINKING
+#define	STATUS_LED_BOOT_STATE		STATUS_LED_OFF
+#define	STATUS_LED_PERIOD		(CFG_HZ / 10)	/* ca. 1 Hz */
+#define	STATUS_LED_BOOT			0		/* boot LED */
+
+#if	(STATUS_LED_BITS > 1)
+#define	STATUS_LED_BIT1			(1 << 1)	/* LED[1] */
+#define	STATUS_LED_STATE1		STATUS_LED_OFF
+#define	STATUS_LED_PERIOD1		(CFG_HZ / 50)	/* ca. 5 Hz */
+#define	STATUS_LED_RED			1		/* fail LED */
+#endif
+
+#if	(STATUS_LED_BITS > 2)
+#define	STATUS_LED_BIT2			(1 << 2)	/* LED[2] */
+#define	STATUS_LED_STATE2		STATUS_LED_OFF
+#define	STATUS_LED_PERIOD2		(CFG_HZ / 10)	/* ca. 1 Hz */
+#define	STATUS_LED_YELLOW		2		/* info LED */
+#endif
+
+#if	(STATUS_LED_BITS > 3)
+#define	STATUS_LED_BIT3			(1 << 3)	/* LED[3] */
+#define	STATUS_LED_STATE3		STATUS_LED_OFF
+#define	STATUS_LED_PERIOD3		(CFG_HZ / 10)	/* ca. 1 Hz */
+#define	STATUS_LED_GREEN		3		/* info LED */
+#endif
+
+#define	STATUS_LED_PAR			1 /* makes status_led.h happy */
+
+#endif	/* CFG_NIOS_CPU_PIO_NUMS */
+
+/*------------------------------------------------------------------------
+ * SEVEN SEGMENT LED DISPLAY
+ *----------------------------------------------------------------------*/
+#if	(CFG_NIOS_CPU_PIO_NUMS != 0) && defined(CFG_NIOS_CPU_SEVENSEG_PIO)
+
+#if	(CFG_NIOS_CPU_SEVENSEG_PIO == 0)
+
+#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 1)
+
+#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 2)
+
+#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 3)
+
+#define	SEVENSEG_BASE			CFG_NIOS_CPU_PIO3
+#define	SEVENSEG_BITS			CFG_NIOS_CPU_PIO3_BITS
+#define	SEVENSEG_ACTIVE			0 /* LED on for bit == 1 */
+
+#if	(CFG_NIOS_CPU_PIO3_TYPE == 1)
+#define	SEVENSEG_WRONLY			1
+#else
+#undef	SEVENSEG_WRONLY
+#endif
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 4)
+
+#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 5)
+
+#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 6)
+
+#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 7)
+
+#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 8)
+
+#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h
+
+#elif	(CFG_NIOS_CPU_SEVENSEG_PIO == 9)
+
+#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h
+
+#else
+#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
+#endif
+
+#define	CONFIG_SEVENSEG			1 /* enable seven segment led driver */
+
+/*
+ * Dual 7-Segment Display pin assignment -- read more in your
+ * "Nios Development Board Reference Manual"
+ *
+ *
+ *    (U8) HI:D[15..8]     (U9) LO:D[7..0]
+ *         ______               ______
+ *        |  D14 |             |  D6  |
+ *        |      |             |      |
+ *      D9|      |D13        D1|      |D5
+ *        |______|             |______|                  ___
+ *        |  D8  |             |  D0  |                 | A |
+ *        |      |             |      |                F|___|B
+ *     D10|      |D12        D2|      |D4               | G |
+ *        |______|             |______|                E|___|C
+ *           D11  *               D3   *                  D  *
+ *                D15                  D7                    DP
+ *
+ */
+#define	SEVENSEG_DIGIT_HI_LO_EQUAL	1	/* high nibble equal low nibble */
+#define	SEVENSEG_DIGIT_A		(1 << 6) /* bit 6 is segment A */
+#define	SEVENSEG_DIGIT_B		(1 << 5) /* bit 5 is segment B */
+#define	SEVENSEG_DIGIT_C		(1 << 4) /* bit 4 is segment C */
+#define	SEVENSEG_DIGIT_D		(1 << 3) /* bit 3 is segment D */
+#define	SEVENSEG_DIGIT_E		(1 << 2) /* bit 2 is segment E */
+#define	SEVENSEG_DIGIT_F		(1 << 1) /* bit 1 is segment F */
+#define	SEVENSEG_DIGIT_G		(1 << 0) /* bit 0 is segment G */
+#define	SEVENSEG_DIGIT_DP		(1 << 7) /* bit 7 is decimal point */
+
+#endif	/* CFG_NIOS_CPU_PIO_NUMS */
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
+				 CFG_CMD_ASKENV | \
+				 CFG_CMD_BEDBUG | \
+				 CFG_CMD_BMP	| \
+				 CFG_CMD_BSP	| \
+				 CFG_CMD_CACHE	| \
+				 CFG_CMD_DATE	| \
+				 CFG_CMD_DOC	| \
+				 CFG_CMD_DTT	| \
+				 CFG_CMD_EEPROM | \
+				 CFG_CMD_ELF    | \
+				 CFG_CMD_FAT	| \
+				 CFG_CMD_FDC	| \
+				 CFG_CMD_FDOS	| \
+				 CFG_CMD_HWFLOW	| \
+				 CFG_CMD_IDE	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_JFFS2	| \
+				 CFG_CMD_KGDB	| \
+				 CFG_CMD_NAND	| \
+				 CFG_CMD_NFS	| \
+				 CFG_CMD_MMC	| \
+				 CFG_CMD_MII	| \
+				 CFG_CMD_PCI	| \
+				 CFG_CMD_PCMCIA | \
+				 CFG_CMD_SCSI	| \
+				 CFG_CMD_SPI	| \
+				 CFG_CMD_VFD	| \
+				 CFG_CMD_USB	| \
+				 CFG_CMD_XIMG	) )
+
+
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * KGDB
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	9600
+#endif
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define	CFG_LONGHELP			    /* undef to save memory	*/
+#define	CFG_PROMPT		"DK1S10 > " /* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	    /* max number of command args*/
+#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size */
+
+/* Default load address	*/
+#if	(CFG_SRAM_SIZE != 0)
+
+/* default in SRAM */
+#define	CFG_LOAD_ADDR		CFG_SRAM_BASE
+
+#elif	(CFG_SDRAM_SIZE != 0)
+
+/* default in SDRAM */
+#if	(CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
+#define	CFG_LOAD_ADDR		(CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
+#else
+#define	CFG_LOAD_ADDR		CFG_SDRAM_BASE
+#endif
+
+#else
+#undef	CFG_LOAD_ADDR		/* force error break */
+#endif
+
+
+/* MEM test area */
+#if	(CFG_SDRAM_SIZE != 0)
+
+/* SDRAM begin to stack area (1MB stack) */
+#if	(CFG_SDRAM_BASE == CFG_NIOS_CPU_VEC_BASE)
+#define	CFG_MEMTEST_START	(CFG_SDRAM_BASE + CFG_NIOS_CPU_VEC_SIZE)
+#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024))
+#else
+#define	CFG_MEMTEST_START	CFG_SDRAM_BASE
+#define	CFG_MEMTEST_END		(CFG_INIT_SP - (1024 * 1024))
+#endif
+
+#else
+#undef	CFG_MEMTEST_START	/* force error break */
+#undef	CFG_MEMTEST_END
+#endif
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		""
+#define MTDPARTS_DEFAULT	""
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/DK1S10_mtx_ldk_20.h b/include/configs/DK1S10_mtx_ldk_20.h
new file mode 100755
index 0000000..4eb9629
--- /dev/null
+++ b/include/configs/DK1S10_mtx_ldk_20.h
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_DK1S10_MTX_LDK_20_H
+#define __CONFIG_DK1S10_MTX_LDK_20_H
+
+/*
+ * NIOS CPU configuration. (PART OF configs/DK1S10.h)
+ *
+ * Here we must define CPU dependencies. Any unsupported option have to
+ * be defined with zero, example CPU without data cache / OCI:
+ *
+ *	#define	CFG_NIOS_CPU_ICACHE	4096
+ *	#define	CFG_NIOS_CPU_DCACHE	0
+ *	#define	CFG_NIOS_CPU_OCI_BASE	0
+ *	#define	CFG_NIOS_CPU_OCI_SIZE	0
+ */
+
+/* CPU core */
+#define	CFG_NIOS_CPU_CLK	75000000	/* NIOS CPU clock	*/
+#define	CFG_NIOS_CPU_ICACHE	(0)		/* instruction cache	*/
+#define	CFG_NIOS_CPU_DCACHE	(0)		/* data cache		*/
+#define	CFG_NIOS_CPU_REG_NUMS	512		/* number of register	*/
+#define	CFG_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_STACK	0x02000000	/* stack top	addr	*/
+#define	CFG_NIOS_CPU_VEC_BASE	0x01000000	/* IRQ vectors	addr	*/
+#define	CFG_NIOS_CPU_VEC_SIZE	256		/*		size	*/
+#define	CFG_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
+#define	CFG_NIOS_CPU_RST_VECT	0x00000000	/* RESET vector	addr	*/
+#define	CFG_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
+						/*		yes(1)	*/
+
+/* The offset address in flash to check for the Nios signature "Ni".
+ * (see GM_FlashExec in germs_monitor.s) */
+#define	CFG_NIOS_CPU_EXES_OFFS	0x0C
+
+/* on-chip extensions */
+#undef	CFG_NIOS_CPU_RAM_BASE			/* on chip RAM	addr	*/
+#undef	CFG_NIOS_CPU_RAM_SIZE			/* 64 KB	size	*/
+
+#define	CFG_NIOS_CPU_ROM_BASE	0x00000000	/* on chip ROM	addr	*/
+#define	CFG_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
+
+#undef	CFG_NIOS_CPU_OCI_BASE			/* OCI core	addr	*/
+#undef	CFG_NIOS_CPU_OCI_SIZE			/*		size	*/
+
+/* timer */
+#define	CFG_NIOS_CPU_TIMER_NUMS	1		/* number of timer	*/
+
+#define	CFG_NIOS_CPU_TIMER0	0x00000840	/* TIMER0	addr	*/
+#define	CFG_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
+#define	CFG_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
+#define	CFG_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
+						/*		yes(1)	*/
+
+/* serial i/o */
+#define	CFG_NIOS_CPU_UART_NUMS	2		/* number of uarts	*/
+
+#define	CFG_NIOS_CPU_UART0	0x00000800	/* UART0	addr	*/
+#define	CFG_NIOS_CPU_UART0_IRQ	17		/*		IRQ	*/
+#define	CFG_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
+#define	CFG_NIOS_CPU_UART0_DB	8		/*  data bit		*/
+#define	CFG_NIOS_CPU_UART0_SB	2		/*  stop bit		*/
+#define	CFG_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
+						/*		odd(1)	*/
+						/*		even(2)	*/
+#define	CFG_NIOS_CPU_UART0_HS	0		/*  handshake:	no(0)	*/
+						/*		crts(1)	*/
+#define	CFG_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
+						/*		yes(1)	*/
+
+#define	CFG_NIOS_CPU_UART1	0x000008a0	/* UART1	addr	*/
+#define	CFG_NIOS_CPU_UART1_IRQ	18		/*		IRQ	*/
+#define	CFG_NIOS_CPU_UART1_BR	115200		/*  baudrate	var(0)	*/
+#define	CFG_NIOS_CPU_UART1_DB	8		/*  data bit		*/
+#define	CFG_NIOS_CPU_UART1_SB	1		/*  stop bit		*/
+#define	CFG_NIOS_CPU_UART1_PA	0		/*  parity	none(0)	*/
+						/*		odd(1)	*/
+						/*		even(2)	*/
+#define	CFG_NIOS_CPU_UART1_HS	0		/*  handshake:	no(0)	*/
+						/*		crts(1)	*/
+#define	CFG_NIOS_CPU_UART1_EOP	0		/*  eop reg:	no(0)	*/
+						/*		yes(1)	*/
+
+/* parallel i/o */
+#define	CFG_NIOS_CPU_PIO_NUMS	2		/* number of parports	*/
+
+#define	CFG_NIOS_CPU_PIO0	0x00000860	/* PIO0		addr	*/
+#undef	CFG_NIOS_CPU_PIO0_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO0_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO0_TYPE	1		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO0_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO0_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO0_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO1	0x00000870	/* PIO1		addr	*/
+#undef	CFG_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO1_BITS	4		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO1_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+/* IDE i/f */
+#define	CFG_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
+#define	CFG_NIOS_CPU_IDE0	0x00000900	/* IDE0		addr	*/
+#define	CFG_NIOS_CPU_IDE0_IRQ	25		/* 		IRQ	*/
+
+/* memory accessibility */
+#undef	CFG_NIOS_CPU_SRAM_BASE			/* board SRAM	addr	*/
+#undef	CFG_NIOS_CPU_SRAM_SIZE			/*  1 MB	size	*/
+
+#define	CFG_NIOS_CPU_SDRAM_BASE	0x01000000	/* board SDRAM	addr	*/
+#define	CFG_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
+
+#define	CFG_NIOS_CPU_FLASH_BASE	0x00800000	/* board Flash	addr	*/
+#define	CFG_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
+
+/* LAN */
+#define	CFG_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
+
+#define	CFG_NIOS_CPU_LAN0_BASE	0x00010000	/* LAN0		addr	*/
+#define	CFG_NIOS_CPU_LAN0_OFFS	0x0300		/*		offset	*/
+#define	CFG_NIOS_CPU_LAN0_IRQ	20		/*		IRQ	*/
+#define	CFG_NIOS_CPU_LAN0_BUSW	32		/*	        buswidth*/
+#define	CFG_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
+						/*	cs8900(1)	*/
+						/* ex:	openmac(2)	*/
+						/* ex:	alteramac(3)	*/
+
+/* symbolic redefinition (undef, if not present) */
+#define	CFG_NIOS_CPU_TICK_TIMER		0	/* TIMER0: tick (needed)*/
+#undef	CFG_NIOS_CPU_USER_TIMER			/* TIMERx: users choice	*/
+
+#define	CFG_NIOS_CPU_CFPOWER_PIO	0	/* PIO0: CF power/sw.	*/
+#define	CFG_NIOS_CPU_BUTTON_PIO		1	/* PIO1: buttons	*/
+#undef	CFG_NIOS_CPU_LCD_PIO			/* PIOx: ASCII LCD	*/
+#undef	CFG_NIOS_CPU_LED_PIO			/* PIOx: LED bar	*/
+#undef	CFG_NIOS_CPU_SEVENSEG_PIO		/* PIOx: 7-seg. display	*/
+#undef	CFG_NIOS_CPU_RECONF_PIO			/* PIOx: reconf pin	*/
+#undef	CFG_NIOS_CPU_CFPRESENT_PIO		/* PIOx: CF present IRQ	*/
+#undef	CFG_NIOS_CPU_CFATASEL_PIO		/* PIOx: CF ATA select	*/
+
+#endif	/* __CONFIG_DK1S10_MTX_LDK_20_H */
diff --git a/include/configs/DK1S10_safe_32.h b/include/configs/DK1S10_safe_32.h
new file mode 100755
index 0000000..8541a11
--- /dev/null
+++ b/include/configs/DK1S10_safe_32.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_DK1S10_SAFE_32_H
+#define __CONFIG_DK1S10_SAFE_32_H
+
+/*
+ * NIOS CPU configuration. (PART OF configs/DK1S10.h)
+ *
+ * !!! TODO !!! TODO !!!
+ */
+#error *** CFG_ERROR: DK1S10_safe_32 have to be defined (use DK1S10_standard_32 as template)
+
+#endif	/* __CONFIG_DK1S10_SAFE_32_H */
diff --git a/include/configs/DK1S10_standard_32.h b/include/configs/DK1S10_standard_32.h
new file mode 100755
index 0000000..b83c315
--- /dev/null
+++ b/include/configs/DK1S10_standard_32.h
@@ -0,0 +1,274 @@
+/*
+ * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
+ * Stephan Linz <linz@li-pro.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_DK1S10_STANDARD_32_H
+#define __CONFIG_DK1S10_STANDARD_32_H
+
+/*
+ * NIOS CPU configuration. (PART OF configs/DK1S10.h)
+ *
+ * Here we must define CPU dependencies. Any unsupported option have to
+ * be defined with zero, example CPU without data cache / OCI:
+ *
+ *	#define	CFG_NIOS_CPU_ICACHE	4096
+ *	#define	CFG_NIOS_CPU_DCACHE	0
+ *	#define	CFG_NIOS_CPU_OCI_BASE	0
+ *	#define	CFG_NIOS_CPU_OCI_SIZE	0
+ */
+
+/* CPU core */
+#define	CFG_NIOS_CPU_CLK	50000000	/* NIOS CPU clock	*/
+#define	CFG_NIOS_CPU_ICACHE	(4 * 1024)	/* instruction cache	*/
+#define	CFG_NIOS_CPU_DCACHE	(4 * 1024)	/* data cache		*/
+#define	CFG_NIOS_CPU_REG_NUMS	256		/* number of register	*/
+#define	CFG_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_STACK	0x008fff00	/* stack top	addr	*/
+#define	CFG_NIOS_CPU_VEC_BASE	0x008fff00	/* IRQ vectors	addr	*/
+#define	CFG_NIOS_CPU_VEC_SIZE	256		/*		size	*/
+#define	CFG_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
+#define	CFG_NIOS_CPU_RST_VECT	0x00920000	/* RESET vector	addr	*/
+#define	CFG_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
+						/*		yes(1)	*/
+
+/* on-chip extensions */
+#define	CFG_NIOS_CPU_RAM_BASE	0x00900000	/* on chip RAM	addr	*/
+#define	CFG_NIOS_CPU_RAM_SIZE	(64 * 1024)	/* 64 KB	size	*/
+
+#define	CFG_NIOS_CPU_ROM_BASE	0x00920000	/* on chip ROM	addr	*/
+#define	CFG_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/
+
+#define	CFG_NIOS_CPU_OCI_BASE	0x00920800	/* OCI core	addr	*/
+#define	CFG_NIOS_CPU_OCI_SIZE	256		/*		size	*/
+
+/* timer */
+#define	CFG_NIOS_CPU_TIMER_NUMS	2		/* number of timer	*/
+
+#define	CFG_NIOS_CPU_TIMER0	0x00920940	/* TIMER0	addr	*/
+#define	CFG_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
+#define	CFG_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
+#define	CFG_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
+						/*		yes(1)	*/
+
+#define	CFG_NIOS_CPU_TIMER1	0x009209e0	/* TIMER1	addr	*/
+#define	CFG_NIOS_CPU_TIMER1_IRQ	50		/*		IRQ	*/
+#define	CFG_NIOS_CPU_TIMER1_PER	10000		/*  periode	usec	*/
+#define	CFG_NIOS_CPU_TIMER1_AR	1		/*  always run:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_TIMER1_FP	1		/*  fixed per:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_TIMER1_SS	0		/*  snaphot:	no(0)	*/
+						/*		yes(1)	*/
+
+/* serial i/o */
+#define	CFG_NIOS_CPU_UART_NUMS	1		/* number of uarts	*/
+
+#define	CFG_NIOS_CPU_UART0	0x00920900	/* UART0	addr	*/
+#define	CFG_NIOS_CPU_UART0_IRQ	25		/*		IRQ	*/
+#define	CFG_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
+#define	CFG_NIOS_CPU_UART0_DB	8		/*  data bit		*/
+#define	CFG_NIOS_CPU_UART0_SB	1		/*  stop bit		*/
+#define	CFG_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
+						/*		odd(1)	*/
+						/*		even(2)	*/
+#define	CFG_NIOS_CPU_UART0_HS	0		/*  handshake:	no(0)	*/
+						/*		crts(1)	*/
+#define	CFG_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
+						/*		yes(1)	*/
+
+/* parallel i/o */
+#define	CFG_NIOS_CPU_PIO_NUMS	8		/* number of parports	*/
+
+#define	CFG_NIOS_CPU_PIO0	0x00920960	/* PIO0		addr	*/
+#define	CFG_NIOS_CPU_PIO0_IRQ	40		/*		IRQ	*/
+#define	CFG_NIOS_CPU_PIO0_BITS	4		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO0_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO0_CAP	1		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO0_EDGE	3		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO0_ITYPE	2		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO1	0x00920970	/* PIO1		addr	*/
+#undef	CFG_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO1_BITS	11		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO1_TYPE	0		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO2	0x00920980	/* PIO2		addr	*/
+#undef	CFG_NIOS_CPU_PIO2_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO2_BITS	8		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO2_TYPE	1		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO2_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO2_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO2_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO3	0x00920990	/* PIO3		addr	*/
+#undef	CFG_NIOS_CPU_PIO3_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO3_BITS	16		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO3_TYPE	1		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO3_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO3_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO3_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO4	0x009209a0	/* PIO4		addr	*/
+#undef	CFG_NIOS_CPU_PIO4_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO4_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO4_TYPE	0		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO4_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO4_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO4_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO5	0x009209b0	/* PIO5		addr	*/
+#define	CFG_NIOS_CPU_PIO5_IRQ	35		/*		IRQ	*/
+#define	CFG_NIOS_CPU_PIO5_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO5_TYPE	2		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO5_CAP	1		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO5_EDGE	3		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO5_ITYPE	2		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO6	0x009209c0	/* PIO6		addr	*/
+#undef	CFG_NIOS_CPU_PIO6_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO6_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO6_TYPE	1		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO6_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO6_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO6_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+#define	CFG_NIOS_CPU_PIO7	0x009209d0	/* PIO7		addr	*/
+#undef	CFG_NIOS_CPU_PIO7_IRQ			/*		w/o IRQ	*/
+#define	CFG_NIOS_CPU_PIO7_BITS	1		/*  number  of  bits	*/
+#define	CFG_NIOS_CPU_PIO7_TYPE	1		/*  io type:	tris(0)	*/
+						/*		out(1)	*/
+						/*		in(2)	*/
+#define	CFG_NIOS_CPU_PIO7_CAP	0		/*  capture:	no(0)	*/
+						/*		yes(1)	*/
+#define	CFG_NIOS_CPU_PIO7_EDGE	0		/*  edge type:	none(0)	*/
+						/*		fall(1)	*/
+						/*		rise(2)	*/
+						/*		any(3)	*/
+#define	CFG_NIOS_CPU_PIO7_ITYPE	0		/*  IRQ type:	none(0)	*/
+						/*		level(1)*/
+						/*		edge(2)	*/
+
+/* IDE i/f */
+#define	CFG_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
+#define	CFG_NIOS_CPU_IDE0	0x00920a00	/* IDE0		addr	*/
+
+/* memory accessibility */
+#define	CFG_NIOS_CPU_SRAM_BASE	0x00800000	/* board SRAM	addr	*/
+#define	CFG_NIOS_CPU_SRAM_SIZE	(1024 * 1024)	/*  1 MB	size	*/
+
+#define	CFG_NIOS_CPU_SDRAM_BASE	0x01000000	/* board SDRAM	addr	*/
+#define	CFG_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/
+
+#define	CFG_NIOS_CPU_FLASH_BASE	0x00000000	/* board Flash	addr	*/
+#define	CFG_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/
+
+/* LAN */
+#define	CFG_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/
+
+#define	CFG_NIOS_CPU_LAN0_BASE	0x00910000	/* LAN0		addr	*/
+#define	CFG_NIOS_CPU_LAN0_OFFS	0x0300		/*		offset	*/
+#define	CFG_NIOS_CPU_LAN0_IRQ	30		/*		IRQ	*/
+#define	CFG_NIOS_CPU_LAN0_BUSW	32		/*	        buswidth*/
+#define	CFG_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
+						/*	cs8900(1)	*/
+						/* ex:	alteramac(2)	*/
+
+/* symbolic redefinition (undef, if not present) */
+#define	CFG_NIOS_CPU_USER_TIMER		0	/* TIMER0: users choice	*/
+#define	CFG_NIOS_CPU_TICK_TIMER		1	/* TIMER1: tick (needed)*/
+
+#define	CFG_NIOS_CPU_BUTTON_PIO		0	/* PIO0: buttons	*/
+#define	CFG_NIOS_CPU_LCD_PIO		1	/* PIO1: ASCII LCD	*/
+#define	CFG_NIOS_CPU_LED_PIO		2	/* PIO2: LED bar	*/
+#define	CFG_NIOS_CPU_SEVENSEG_PIO	3	/* PIO3: 7-seg. display	*/
+#define	CFG_NIOS_CPU_RECONF_PIO		4	/* PIO4: reconf pin	*/
+#define	CFG_NIOS_CPU_CFPRESENT_PIO	5	/* PIO5: CF present IRQ	*/
+#define	CFG_NIOS_CPU_CFPOWER_PIO	6	/* PIO6: CF power/sw.	*/
+#define	CFG_NIOS_CPU_CFATASEL_PIO	7	/* PIO7: CF ATA select	*/
+
+#endif	/* __CONFIG_DK1S10_STANDARD_32_H */
diff --git a/include/configs/DP405.h b/include/configs/DP405.h
new file mode 100755
index 0000000..2ae794d
--- /dev/null
+++ b/include/configs/DP405.h
@@ -0,0 +1,341 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_DP405		1	/* ...on a DP405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33333300 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_EEPROM	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+#define CONFIG_PRAM		2	/* reserve 2 kB "protected RAM" */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CFG_RAMBOOT		1
+#else
+# undef CFG_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+#if 0 /* test-only */
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+#endif
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
+#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
+#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+/* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
+/* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
+/* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
+/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
+#define CFG_GPIO0_OSRH		0x40000540  /*	0 ... 15 */
+#define CFG_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
+#define CFG_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
+#define CFG_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
+#define CFG_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
+#define CFG_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
+#define CFG_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/DU405.h b/include/configs/DU405.h
new file mode 100755
index 0000000..5489a53
--- /dev/null
+++ b/include/configs/DU405.h
@@ -0,0 +1,315 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_IDENT_STRING     " $Name:  $"
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_DU405		1	/* ...on a DU405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+
+#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND	"bootm fff00000"
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_EEPROM	)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* BQ3285 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000080 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_EXT_SERIAL_CLOCK	11059200  /* use external serial clock	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffe00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
+
+#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFD0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
+				   /* total size of a CAT24WC08 is 1024 bytes */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+#define FLASH0_BA	0xFFC00000	    /* FLASH 0 Base Address		*/
+#define FLASH1_BA	0xFF800000	    /* FLASH 1 Base Address		*/
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART_BA	0xF0300000	    /* DUART Base Address		*/
+#define CF_BA		0xF0100000	    /* CompactFlash Base Address	*/
+#define SRAM_BA		0xF0200000	    /* SRAM Base Address		*/
+#define DURAG_IO_BA	0xF0400000	    /* DURAG Bus IO Base Address	*/
+#define DURAG_MEM_BA	0xF0500000	    /* DURAG Bus Mem Base Address	*/
+
+#define FPGA_MODE_REG	(DUART_BA+0x80)	    /* FPGA Mode Register		*/
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP	0x92015480
+#define CFG_EBC_PB0CR	FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP	0x92015480
+#define CFG_EBC_PB1CR	FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0) initialization						*/
+#define CFG_EBC_PB2AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (DUART) initialization						*/
+#define CFG_EBC_PB3AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR	DUART_BA | 0x18000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 4 (CompactFlash IDE) initialization				*/
+#define CFG_EBC_PB4AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB4CR	CF_BA | 0x1A000	    /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 5 (SRAM) initialization						*/
+#define CFG_EBC_PB5AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB5CR	SRAM_BA | 0x1A000   /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 6 (DURAG Bus IO Space) initialization				*/
+#define CFG_EBC_PB6AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB6CR	DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
+
+/* Memory Bank 7 (DURAG Bus Mem Space) initialization				*/
+#define CFG_EBC_PB7AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB7CR	DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h
new file mode 100755
index 0000000..2c99b4b
--- /dev/null
+++ b/include/configs/ELPPC.h
@@ -0,0 +1,352 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef  DEBUG
+#define GTREGREAD(x) 0xffffffff         /* needed for debug */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* these hardware addresses are pretty bogus, please change them to
+   suit your needs */
+
+/* first ethernet */
+#define CONFIG_ETHADDR          00:00:5b:ee:de:ad
+
+#define CONFIG_IPADDR           192.168.0.105
+#define CONFIG_SERVERIP         192.168.0.100
+
+#define CONFIG_ELPPC            1       /* this is an BAB740/BAB750 board */
+
+#define CONFIG_BAUDRATE         9600    /* console baudrate */
+
+#undef  CONFIG_WATCHDOG
+
+#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#undef  CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND                                  \
+    "bootp 1000000; "                                       \
+    "setenv bootargs root=ramfs console=ttyS00,9600 "       \
+    "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:"    \
+    "${netmask}:${hostname}:eth0:none; "                    \
+    "bootm"
+
+#define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
+#define CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes */
+
+#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                    /* undef to save memory */
+#define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
+
+/*
+ * choose between COM1 and COM2 as serial console
+ */
+#define CONFIG_CONS_INDEX       1
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE              1024        /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE              256         /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS             16          /* max number of command args    */
+#define CFG_BARGSIZE            CFG_CBSIZE  /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START       0x00000000  /* memtest works on    */
+#define CFG_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */
+
+#define CFG_LOAD_ADDR           0x1000000   /* default load address    */
+
+#define CFG_HZ                  1000        /* dec. freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define CFG_BOARD_ASM_INIT
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
+ */
+#undef  CFG_ADDRESS_MAP_A
+
+#define CFG_PCI_MEMORY_BUS      0x00000000
+#define CFG_PCI_MEMORY_PHYS     0x00000000
+#define CFG_PCI_MEMORY_SIZE     0x40000000
+
+#define CFG_PCI_MEM_BUS         0x80000000
+#define CFG_PCI_MEM_PHYS        0x80000000
+#define CFG_PCI_MEM_SIZE        0x7d000000
+
+#define CFG_ISA_MEM_BUS         0x00000000
+#define CFG_ISA_MEM_PHYS        0xfd000000
+#define CFG_ISA_MEM_SIZE        0x01000000
+
+#define CFG_PCI_IO_BUS          0x00800000
+#define CFG_PCI_IO_PHYS         0xfe800000
+#define CFG_PCI_IO_SIZE         0x00400000
+
+#define CFG_ISA_IO_BUS          0x00000000
+#define CFG_ISA_IO_PHYS         0xfe000000
+#define CFG_ISA_IO_SIZE         0x00800000
+
+/* driver defines FDC,IDE,... */
+#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
+#define CFG_ISA_IO              CFG_ISA_IO_PHYS
+#define CFG_60X_PCI_IO_OFFSET   CFG_ISA_IO_PHYS
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE          0x00000000
+
+#define CFG_USR_LED_BASE        0x78000000
+#define CFG_NVRAM_BASE          0xff000000
+#define CFG_UART_BASE           0xff400000
+#define CFG_FLASH_BASE          0xfff00000
+
+#define MPC107_EUMB_ADDR        0xfce00000
+#define MPC107_EUMB_PI          0xfce41090
+#define MPC107_EUMB_GCR         0xfce41020
+#define MPC107_EUMB_IACKR       0xfce600a0
+#define MPC107_I2C_ADDR         0xfce03000
+
+/*
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
+#define CFG_INIT_RAM_END        0x4000
+#define CFG_GBL_DATA_SIZE       64          /* size in bytes reserved for init data */
+#define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*
+ * Flash mapping/organization on the MPC10x.
+ */
+#define FLASH_BASE0_PRELIM      0xff800000
+#define FLASH_BASE1_PRELIM      0xffc00000
+
+#define CFG_MAX_FLASH_BANKS     2           /* max number of memory banks    */
+#define CFG_MAX_FLASH_SECT      67          /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=elppc-0,nor1=elppc-1"
+#define MTDPARTS_DEFAULT	"mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
+*/
+
+#define CFG_MONITOR_BASE        CFG_FLASH_BASE
+#define CFG_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
+#undef  CFG_MEMTEST
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CFG_ENV_IS_IN_NVRAM     1           /* use NVRAM for environment vars */
+#define CFG_NVRAM_SIZE          0x800       /* NVRAM size (2kB) */
+#define CFG_ENV_SIZE            0x400       /* Size of Environment vars (1kB) */
+#define CFG_ENV_ADDR            0x0
+#define CFG_ENV_MAP_ADRS        0xff000000
+#define CFG_NV_SROM_COPY_ADDR   (CFG_ENV_ADDR + CFG_ENV_SIZE)
+#define CFG_NVRAM_ACCESS_ROUTINE            /* only byte accsess alowed */
+#define CFG_SROM_SIZE           0x100       /* shadow of revision info is in nvram */
+
+/*
+ * Serial devices
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK         24000000
+#define CFG_NS16550_COM1        (CFG_UART_BASE + 0)
+#define CFG_NS16550_COM2        (CFG_UART_BASE + 8)
+
+/*
+ * PCI stuff
+ */
+#define CONFIG_PCI                                /* include pci support */
+#define CONFIG_PCI_PNP                            /* pci plug-and-play */
+#define CONFIG_PCI_HOST         PCI_HOST_AUTO
+#undef  CONFIG_PCI_SCAN_SHOW
+
+/*
+ * Optional Video console (graphic: SMI LynxEM)
+ */
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define VIDEO_KBD_INIT_FCT    (simple_strtol (getenv("console"), NULL, 10))
+#define VIDEO_TSTC_FCT        serial_tstc
+#define VIDEO_GETC_FCT        serial_getc
+
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+
+/*
+ * Initial BATs
+ */
+#if 1
+
+#define CFG_IBAT0L 0
+#define CFG_IBAT0U 0
+#define CFG_DBAT0L CFG_IBAT1L
+#define CFG_DBAT0U CFG_IBAT1U
+
+#define CFG_IBAT1L 0
+#define CFG_IBAT1U 0
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+
+#define CFG_IBAT2L 0
+#define CFG_IBAT2U 0
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+
+#define CFG_IBAT3L 0
+#define CFG_IBAT3U 0
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+#else
+
+/* SDRAM */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L CFG_IBAT1L
+#define CFG_DBAT0U CFG_IBAT1U
+
+/* address range for flashes */
+#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+
+/* ISA IO space */
+#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+
+/* ISA memory space */
+#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+#endif
+
+/*
+ * Speed settings are board specific
+ */
+#define CFG_BUS_HZ              100000000
+#define CFG_CPU_CLK             400000000
+#define CFG_BUS_CLK             CFG_BUS_HZ
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */
+
+/*
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT        5    /* log base 2 of the above value */
+#endif
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/74xx_7xx.h for the defines used here
+ */
+
+#define CFG_L2
+
+#if 1
+#define L2_INIT     0       /* cpu 750 CXe*/
+#else
+#define L2_INIT     (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+		     L2CR_L2OH_5   | L2CR_L2CTL | L2CR_L2WT)
+#endif
+#define L2_ENABLE   (L2_INIT | L2CR_L2E)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM           0x02    /* Software reboot */
+
+#define CONFIG_NET_MULTI        /* Multi ethernet cards support */
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_EEPRO100_SROM_WRITE
+
+#endif    /* __CONFIG_H */
diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h
new file mode 100755
index 0000000..e73bcec
--- /dev/null
+++ b/include/configs/ELPT860.h
@@ -0,0 +1,390 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* It's a MPC860, in fact a 860T CPU */
+#define CONFIG_MPC860T		1
+#define CONFIG_ELPT860		1	/* ...on a LEOX's ELPT860 CPU board */
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		    */
+#undef	  CONFIG_8xx_CONS_SMC2
+#undef	  CONFIG_8xx_CONS_NONE
+
+#define CONFIG_CLOCKS_IN_MHZ	1  /* Clock passed to Linux (<2.4.5) in MHz */
+#define CONFIG_8xx_GCLK_FREQ	50000000       /* MPC860T runs at 50MHz */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+/* BOOT arguments */
+#define CONFIG_PREBOOT							   \
+     "echo;"								   \
+     "echo Type \"run nfsboot\" to mount root filesystem over NFS;"	   \
+     "echo"
+
+#undef	  CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+    "ramargs=setenv bootargs root=/dev/ram rw\0"			\
+    "rootargs=setenv rootpath /tftp/${ipaddr}\0"			\
+    "nfsargs=setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=${serverip}:${rootpath}\0"				\
+    "addip=setenv bootargs ${bootargs} "				\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"		\
+	":${hostname}:eth0:off panic=1\0"				\
+    "ramboot=tftp 400000 /home/paugaml/pMulti;"				\
+	"run ramargs;bootm\0"						\
+    "nfsboot=tftp 400000 /home/paugaml/uImage;"				\
+	"run rootargs;run nfsargs;run addip;bootm\0"			\
+    ""
+#define CONFIG_BOOTCOMMAND	"run ramboot"
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#undef	  CONFIG_WATCHDOG		/* watchdog disabled		*/
+#undef	  CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+#undef	  CONFIG_RTC_MPC8xx		/* internal RTC MPC8xx unused	*/
+#define CONFIG_RTC_DS164x	1	/* RTC is a Dallas DS1646	*/
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	  CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
+				  CFG_CMD_ASKENV | \
+				  CFG_CMD_DATE	 )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT     "LEOX_elpt860: " /* Monitor Command Prompt	*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#  define CFG_CBSIZE	 256		/* Console I/O Buffer Size	*/
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	  16		/* max number of command args	*/
+#define CFG_BARGSIZE	  CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x00100000	/* default load address */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+/*
+ * Environment Variables and Storages
+ */
+#define CONFIG_ENV_OVERWRITE	1  /* Allow Overwrite of serial# & ethaddr */
+
+#undef	  CFG_ENV_IS_IN_NVRAM	       /* Environment is in NVRAM	*/
+#undef	  CFG_ENV_IS_IN_EEPROM	       /* Environment is in I2C EEPROM	*/
+#define CFG_ENV_IS_IN_FLASH	1      /* Environment is in FLASH	*/
+
+#define CONFIG_BAUDRATE		9600   /* console baudrate = 9600 bps	*/
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_ETHADDR		00:01:77:00:60:40
+#define CONFIG_IPADDR		192.168.0.30
+#define CONFIG_NETMASK		255.255.255.0
+
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_GATEWAYIP	192.168.0.1
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x02000000
+#define CFG_NVRAM_BASE		0x03000000
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#  if defined(DEBUG)
+#    define CFG_MONITOR_LEN	(320 << 10)  /* Reserve 320 kB for Monitor  */
+#  else
+#    define CFG_MONITOR_LEN	(256 << 10)  /* Reserve 256 kB for Monitor  */
+#  endif
+#else
+#  if defined(DEBUG)
+#    define CFG_MONITOR_LEN	(256 << 10)  /* Reserve 256 kB for Monitor  */
+#  else
+#    define CFG_MONITOR_LEN	(192 << 10)  /* Reserve 192 kB for Monitor  */
+#  endif
+#endif
+
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(128 << 10)  /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)    /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	     */
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)   */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)   */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#  define CFG_ENV_OFFSET	0x10000 /* Offset   of Environment Sector    */
+#  define CFG_ENV_SIZE		0x10000 /* Total Size of Environment Sector  */
+#endif
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR	CFG_NVRAM_BASE /* Base address of NVRAM area */
+#define CFG_NVRAM_SIZE		((128*1024)-8) /* clock regs resident in the */
+					       /*   8 top NVRAM locations    */
+
+#if defined(CFG_ENV_IS_IN_NVRAM)
+#  define CFG_ENV_ADDR		CFG_NVRAM_BASE /* Base address of NVRAM area */
+#  define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector  */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs		     */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	 4	/* log base 2 of the above value     */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT	 | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI | SYPCR_SWP)
+#else
+#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT	 | SYPCR_BME | SYPCR_SWF | \
+						   SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC11)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
+ *  enabled
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	 SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler
+ *-----------------------------------------------------------------------
+ *
+ */
+#ifdef DEBUG
+#  define CFG_DER		0xFFE7400F	/* Debug Enable Register */
+#else
+#  define CFG_DER		0
+#endif
+
+/*
+ * Init Memory Controller:
+ * ~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	  */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_PRELIM_OR_AM	0xFF000000	/* 16 MB between each CSx */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0	  */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR1 and OR1 (SDRAM)
+ *
+ */
+#define SDRAM_BASE1_PRELIM	CFG_SDRAM_BASE	/* SDRAM bank #0	*/
+#define SDRAM_MAX_SIZE		0x02000000	/* 32 MB MAX for CS1	*/
+
+/* SDRAM timing:							*/
+#define CFG_OR_TIMING_SDRAM	0x00000000
+
+#define CFG_OR1_PRELIM	((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM )
+#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR2 and OR2 (NVRAM)
+ *
+ */
+#define NVRAM_BASE1_PRELIM	CFG_NVRAM_BASE	/* NVRAM bank #0	*/
+#define NVRAM_MAX_SIZE		0x00020000	/* 128 KB MAX for CS2	*/
+
+#define CFG_OR2_PRELIM		0xFFF80160
+#define CFG_BR2_PRELIM	((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA		97     /* start with divider for 100 MHz */
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16	  /* setting for 2 banks */
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32	  /* setting for 1 bank	 */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit	 */
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8	  /* setting for 2 banks */
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16	  /* setting for 1 bank	 */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    | \
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    | \
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/*-----------------------------------------------------------------------
+ * Internal Definitions
+ *-----------------------------------------------------------------------
+ *
+ */
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		 /* Software reboot		     */
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h
new file mode 100755
index 0000000..c203aea
--- /dev/null
+++ b/include/configs/ERIC.h
@@ -0,0 +1,372 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_ERIC		1	/* ...on a ERIC board	*/
+
+#define	CONFIG_BOARD_EARLY_INIT_F 1	/* run board_early_init_f() */
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
+
+#if 1
+#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/
+#endif
+#if 0
+#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#endif
+#if 0
+#define CFG_ENV_IS_IN_EEPROM	1	/* use I2C RTC X1240 for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars */
+#endif					/* total size of a X1240 is 2048 bytes */
+
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x57	/* X1240 has two I2C slave addresses, one for EEPROM */
+#define CFG_I2C_EEPROM_ADDR_LEN	2	/* address length for the eeprom */
+#define CONFIG_I2C_RTC		1	/* we have a Xicor X1240 RTC */
+#define CFG_I2C_RTC_ADDR	0x6F	/*                                and one for RTC */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_EEPROM
+#else
+#ifdef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_EEPROM
+#else
+#ifdef CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#endif
+#endif
+#endif
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#if 1
+#define CONFIG_BOOTCOMMAND	"bootm ffc00000" /* autoboot command	*/
+#else
+#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
+#endif
+
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/nfs "	\
+				"nfsroot=192.168.1.2:/eric_root_devel "	\
+				"ip=192.168.1.22:192.168.1.2"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ENV	| \
+				CFG_CMD_FLASH)
+
+/*
+ * #define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | \
+ *				 CFG_CMD_KGDB | CFG_CMD_I2C | CFG_CMD_EEPROM | \
+ *				 CFG_CMD_ENV | CFG_CMD_FLASH)
+ */
+
+/* CFG_CMD_ENV est definie */
+/*	((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_KGDB) & ~(CFG_CMD_ENV))
+ */
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef	CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	 CFG_EXT_SERIAL_CLOCK	 14318180
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
+#undef  CONFIG_PCI_PNP			/* no pci plug-and-play         */
+					/* resource configuration       */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1743	/* PCI Vendor ID: Peppercon AG	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: 405GP		*/
+#define CFG_PCI_PTM1LA	0xFFFC0000	/* point to flash		*/
+#define CFG_PCI_PTM1MS	0xFFFFF001	/* 4kB, enable hard-wired to 1	*/
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * External peripheral base address
+ *-----------------------------------------------------------------------
+ */
+/*	Bank 0 - Flash/SRAM	       0xFF000000 16MB	16 Bit */
+/*	Bank 1 - NVRAM/RTC	       0xF0000000  1MB	 8 Bit */
+/*	Bank 2 - A/D converter	       0xF0100000  1MB	 8 Bit */
+/*	Bank 3 - Ethernet PHY Reset    0xF0200000  1MB	 8 Bit */
+/*	Bank 4 - PC-MIP PRSNT1#	       0xF0300000  1MB	 8 Bit */
+/*	Bank 5 - PC-MIP PRSNT2#	       0xF0400000  1MB	 8 Bit */
+/*	Bank 6 - CPU LED0	       0xF0500000  1MB	 8 Bit */
+/*	Bank 7 - CPU LED1	       0xF0600000  1MB	 8 Bit */
+
+/* ----------------------------------------------------------------------- */
+/*  Memory Bank 0 (Flash) initialization */
+/* ----------------------------------------------------------------------- */
+#define CS0_AP	0x9B015480
+#define CS0_CR	0xFF87A000 /*  BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */
+/* ----------------------------------------------------------------------- */
+/*  Memory Bank 1 (NVRAM/RTC) initialization */
+/* ----------------------------------------------------------------------- */
+#define CS1_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
+#define CS1_CR	0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
+ /* ----------------------------------------------------------------------- */
+ /*  Memory Bank 2 (A/D converter) initialization */
+ /* ----------------------------------------------------------------------- */
+#define CS2_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
+#define CS2_CR	0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
+/* ----------------------------------------------------------------------- */
+/*  Memory Bank 3 (Ethernet PHY Reset) initialization */
+/* ----------------------------------------------------------------------- */
+#define CS3_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
+#define CS3_CR	0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
+/* ----------------------------------------------------------------------- */
+/*  Memory Bank 4 (PC-MIP PRSNT1#) initialization */
+/* ----------------------------------------------------------------------- */
+#define CS4_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
+#define CS4_CR	0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
+/* ----------------------------------------------------------------------- */
+/*  Memory Bank 5 (PC-MIP PRSNT2#) initialization */
+/* ----------------------------------------------------------------------- */
+#define CS5_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
+#define CS5_CR	0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
+/* ----------------------------------------------------------------------- */
+/*  Memory Bank 6 (CPU LED0) initialization */
+/* ----------------------------------------------------------------------- */
+#define CS6_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
+#define CS6_CR	0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
+/* ----------------------------------------------------------------------- */
+/*  Memory Bank 7 (CPU LED1) initialization */
+/* ----------------------------------------------------------------------- */
+#define CS7_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
+#define CS7_CR	0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
+
+#define CFG_NVRAM_REG_BASE_ADDR	 0xF0000000
+#define CFG_RTC_REG_BASE_ADDR	 (0xF0000000 + 0x7F8)
+#define CFG_ADC_REG_BASE_ADDR	 0xF0100000
+#define CFG_PHYRES_REG_BASE_ADDR 0xF0200000
+#define CFG_PRSNT1_REG_BASE_ADDR 0xF0300000
+#define CFG_PRSNT2_REG_BASE_ADDR 0xF0400000
+#define CFG_LED0_REG_BASE_ADDR	 0xF0500000
+#define CFG_LED1_REG_BASE_ADDR	 0xF0600000
+
+
+/*  SDRAM CONFIG */
+#define CFG_SDRAM_MANUALLY    1
+#define CFG_SDRAM_SINGLE_BANK 1
+
+#ifdef CFG_SDRAM_MANUALLY
+/*-----------------------------------------------------------------------
+ * Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2)
+ *----------------------------------------------------------------------*/
+#define MB0CF	0x00062001 /*  32MB @ 0 */
+/*-----------------------------------------------------------------------
+ * Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2)
+ *----------------------------------------------------------------------*/
+#ifdef CFG_SDRAM_SINGLE_BANK
+#define MB1CF	0x0 /*  0MB @ 32MB */
+#else
+#define MB1CF	0x02062001 /*  32MB @ 32MB */
+#endif
+/*-----------------------------------------------------------------------
+ * Set MB2CF for bank 2. off
+ *----------------------------------------------------------------------*/
+#define MB2CF	0x0 /*  0MB */
+/*-----------------------------------------------------------------------
+ * Set MB3CF for bank 3. off
+ *----------------------------------------------------------------------*/
+#define MB3CF	0x0 /*  0MB */
+
+#define SDTR_100    0x0086400D
+#define RTR_100     0x05F0
+#define SDTR_66     0x00854006	/* orig U-Boot-wallnut says 0x00854006 */
+#define RTR_66      0x03f8
+
+#endif   /* CFG_SDRAM_MANUALLY */
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_SIZE		32
+#define CFG_FLASH_BASE		0xFF800000      /* 8 MByte Flash */
+#define CFG_MONITOR_BASE	0xFFFE0000      /* last 128kByte within Flash */
+/*#define CFG_MONITOR_LEN		(192 * 1024)*/	/* Reserve 196 kB for Monitor	*/
+#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CFG_FLASH_16BIT		1	/* Rom 16 bit data bus			*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/* BEG ENVIRONNEMENT FLASH */
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE       (128*1024)
+
+#if 0  /* force ENV to be NOT embedded */
+#define CFG_ENV_ADDR            0xfffa0000
+#else  /* force ENV to be embedded */
+#define	CFG_ENV_SIZE		(2 * 1024) /* Total Size of Environment Sector 2k */
+#define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN - CFG_ENV_SIZE - 0x10) /* let space for reset vector */
+/* #define CFG_ENV_ADDR            (CFG_MONITOR_BASE)*/
+#define CFG_ENV_OFFSET          (CFG_ENV_ADDR - CFG_FLASH_BASE)
+#endif
+
+#endif
+/* END ENVIRONNEMENT FLASH */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR	CFG_NVRAM_REG_BASE_ADDR	/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		0x7F8		/* NVRAM size 2kByte - 8 Byte for RTC */
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE		0x7F8		/* Size of Environment vars	*/
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0 8MB 	*/
+#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
+
+
+/* Configuration Port location */
+/*  #define CONFIG_PORT_ADDR	0xF0000500 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x00df0000  /* inside of SDRAM		       */
+#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS      0x50
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h
new file mode 100755
index 0000000..b176c6f
--- /dev/null
+++ b/include/configs/ESTEEM192E.h
@@ -0,0 +1,320 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_ESTEEM192E	1	/* ...on a EST ESTEEM192E	*/
+
+#define CONFIG_FLASH_16BIT	1	/* Rom 16 bit data bus		*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef  CONFIG_8xx_CONS_NONE
+
+#define MPC8XX_FACT	10		/* Multiply by 10		*/
+#define MPC8XX_XIN	4915200	/* 4.915200 MHz in	- ??? - XXX	*/
+#define CFG_PLPRCR_MF	((MPC8XX_FACT-1) << 20)
+#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz	*/
+
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ	/* Force it - dont measure it */
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BAUDRATE		9600
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_BOOTCOMMAND	"bootm 40030000" /* autoboot command	*/
+
+#define CONFIG_BOOTARGS		"root=/dev/ram rw ramdisk=8192 "			\
+				"ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 "
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"BOOT: "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE	256			/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	8			/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000		/* decrementer freq: 1 ms ticks	*/
+
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+  /*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#ifdef	DEBUG
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * SUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+
+/* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */
+
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CFG_PLPRCR	(CFG_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+#define CFG_PCMCIA_INTERRUPT	SIU_LEVEL6
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0
+/*#define CFG_DER	0x02002000 */
+
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	0x00000160
+				/*(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+				 OR_SCY_5_CLK | OR_EHTR) */
+
+#define CFG_OR0_REMAP	0x80000160     /*(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)*/
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	( FLASH_BASE0_PRELIM | 0x00000801 )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	( FLASH_BASE1_PRELIM | 0x00000801 )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x04000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x02000000	/* max 32 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	0xFC000E00
+#define CFG_BR2_PRELIM	(SDRAM_BASE2_PRELIM | 0x00000081)
+
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	(SDRAM_BASE3_PRELIM | 0x00000081)
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	0x18803112
+#define CFG_MAMR_9COL	0x18803112	/* same as 8 column because its just easier to port with*/
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h
new file mode 100755
index 0000000..d55eb7d
--- /dev/null
+++ b/include/configs/ETX094.h
@@ -0,0 +1,355 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_ETX094		1	/* ...on a ETX_094 board	*/
+
+#define	CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		57600
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define	CONFIG_FLASH_16BIT		/* for board with 16bit wide flash	*/
+#undef	SB_ETX094			/* only for SB-Board with 16MB SDRAM 	*/
+#define	CONFIG_BOOTP_RANDOM_DELAY	/* graceful BOOTP recovery mode		*/
+
+#define CONFIG_ETHADDR 08:00:06:00:00:00
+
+#ifdef	CONFIG_ETHADDR
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1	/* default MAC can be overwritten once	*/
+#endif
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_RAMBOOTCOMMAND							\
+	"bootp; "								\
+	"setenv bootargs root=/dev/ram rw ramdisk_size=4690 "			\
+	"U-Boot_version=U-Boot-1.0.x-Date "					\
+	"panic=1 "								\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+#define CONFIG_NFSBOOTCOMMAND							\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#ifdef	DEBUG
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#ifdef CONFIG_FLASH_16BIT
+#define CFG_ENV_OFFSET		0x8000	/* Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x8000	/* Total Size of Environment Sector	*/
+#else
+#define CFG_ENV_OFFSET		0x8000	/* Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif	/* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0	*/
+#define CFG_OR_TIMING_FLASH    (OR_ACS_DIV2 | OR_BI | \
+			       OR_SCY_2_CLK | OR_TRLX )
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+
+#ifdef CONFIG_FLASH_16BIT	/* 16 bit data port */
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
+#else				/* 32 bit data port */
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
+#endif	/* CONFIG_FLASH_16BIT */
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	23		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_1X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_1X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h
new file mode 100755
index 0000000..78e5716
--- /dev/null
+++ b/include/configs/EVB64260.h
@@ -0,0 +1,425 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifndef __ASSEMBLY__
+#include <galileo/core.h>
+#endif
+
+#include "../board/evb64260/local.h"
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_EVB64260		1	/* this is an EVB64260 board	*/
+#define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
+
+#define CONFIG_BAUDRATE		38400 	/* console baudrate = 38400	*/
+
+#undef	CONFIG_ECC			/* enable ECC support */
+/* #define CONFIG_EVB64260_750CX  1 */      /* Support the EVB-64260-750CX Board */
+
+/* which initialization functions to call for this board */
+#define CONFIG_MISC_INIT_R	1
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+#ifndef CONFIG_EVB64260_750CX
+#define CFG_BOARD_NAME		"EVB64260"
+#else
+#define CFG_BOARD_NAME         "EVB64260-750CX"
+#endif
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * what to do:
+ * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
+ * cable onto the second DUART channel, change the CFG_DUART port from 1
+ * to 0 below.
+ *
+ * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
+ * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
+ */
+#define	CONFIG_MPSC
+#define CONFIG_MPSC_PORT	0
+
+#define CONFIG_NET_MULTI        /* attempt all available adapters */
+
+/* define this if you want to enable GT MAC filtering */
+#define CONFIG_GT_USE_MAC_HASH_TABLE
+
+#undef CONFIG_ETHER_PORT_MII	/* use RMII */
+
+#if 1
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND						     \
+	"bootp && " 						     \
+	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
+	"ip=$ipaddr:$serverip:$gatewayip:" \
+	"$netmask:$hostname:eth0:none; && " \
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#define	CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_ALTIVEC                  /* undef to disable             */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE)
+
+
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_ASKENV)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x00300000	/* default load address	*/
+
+#define	CFG_HZ			1000		/* decr freq: 1ms ticks	*/
+#define CFG_BUS_HZ		100000000	/* 100 MHz		*/
+#define CFG_BUS_CLK		CFG_BUS_HZ
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#ifdef CONFIG_EVB64260_750CX
+#define CONFIG_750CX
+#define CFG_BROKEN_CL2
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_RAM_ADDR	0x40000000
+#define	CFG_INIT_RAM_END	0x1000
+#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_RAM_LOCK
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xfff00000
+#define CFG_RESET_ADDRESS	0xfff00100
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+
+/* areas to map different things with the GT in physical space */
+#define CFG_DRAM_BANKS		4
+#define CFG_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
+
+/* What to put in the bats. */
+#define CFG_MISC_REGION_BASE	0xf0000000
+
+/* Peripheral Device section */
+#define CFG_GT_REGS		0xf8000000
+#define CFG_DEV_BASE		0xfc000000
+
+#define CFG_DEV0_SPACE		CFG_DEV_BASE
+#define CFG_DEV1_SPACE		(CFG_DEV0_SPACE + CFG_DEV0_SIZE)
+#define CFG_DEV2_SPACE		(CFG_DEV1_SPACE + CFG_DEV1_SIZE)
+#define CFG_DEV3_SPACE		(CFG_DEV2_SPACE + CFG_DEV2_SIZE)
+
+#define CFG_DEV0_SIZE		 _8M /* evb64260 sram  @ 0xfc00.0000 */
+#define CFG_DEV1_SIZE		 _8M /* evb64260 rtc   @ 0xfc80.0000 */
+#define CFG_DEV2_SIZE		_16M /* evb64260 duart @ 0xfd00.0000 */
+#define CFG_DEV3_SIZE		_16M /* evb64260 flash @ 0xfe00.0000 */
+
+#define CFG_DEV0_PAR		0x20205093
+#define CFG_DEV1_PAR		0xcfcfffff
+#define CFG_DEV2_PAR		0xc0059bd4
+#define CFG_8BIT_BOOT_PAR	0xc00b5e7c
+#define CFG_32BIT_BOOT_PAR	0xc4a8241c
+	/*   c    4    a      8     2     4    1      c		*/
+	/* 33 22|2222|22 22|111 1|11 11|1 1  |    |		*/
+	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
+	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
+	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
+
+#if 0 /* Wrong?? NTL */
+#define CFG_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
+						/* DMAAck[1:0] GNT0[1:0] */
+#else
+#define CFG_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
+						/* REQ0[1:0] GNT0[1:0] */
+#endif
+#define CFG_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
+						/* DMAReq[4] DMAAck[4] WDNMI WDE */
+#if 0 /* Wrong?? NTL */
+#define CFG_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
+						/* DMAAck[1:0] GNT1[1:0] */
+#else
+#define CFG_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
+						/* GPP[22] (RS232IntB or PCI1Int) */
+						/* GPP[21] (RS323IntA) */
+						/* BClkIn */
+						/* REQ1[1:0] GNT1[1:0] */
+#endif
+
+#if 0 /* Wrong?? NTL */
+# define CFG_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
+						/* GPP[27:26] Int[1:0] */
+#else
+# define CFG_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
+						/* GPP[29]    (PCI1Int) */
+						/* BClkOut0 */
+						/* GPP[27]    (PCI0Int) */
+						/* GPP[26]    (RtcInt or PCI1Int) */
+						/* CPUInt[25:24] */
+#endif
+
+# define CFG_SERIAL_PORT_MUX	0x00000102	/* 0=hiZ  1=MPSC0 2=ETH 0 and 2 RMII */
+
+#if 0 /* Wrong?? - NTL */
+# define CFG_GPP_LEVEL_CONTROL	0x000002c6
+#else
+# define CFG_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
+						/* gpp[29] */
+						/* gpp[27:26] */
+						/* gpp[22:21] */
+
+# define CFG_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
+				/* idmas use buffer 1,1
+				   comm use buffer 0
+				   pci use buffer 1,1
+				   cpu use buffer 0
+				   normal load (see also ifdef HVL)
+				   standard SDRAM (see also ifdef REG)
+				   non staggered refresh */
+				/* 31:26  25 23  20 19 18 16 */
+				/* 110110 00 111 0  0  00 1 */
+				/* refresh_count=0x200
+				   phisical interleaving disable
+				   virtual interleaving enable */
+				/* 15 14 13:0 */
+				/* 1  0  0x200 */
+#endif
+
+#define CFG_DUART_IO		CFG_DEV2_SPACE
+#define CFG_DUART_CHAN		1		/* channel to use for console */
+#define CFG_INIT_CHAN1
+#define CFG_INIT_CHAN2
+
+#define SRAM_BASE		CFG_DEV0_SPACE
+#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI                      /* include pci support          */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
+
+/* PCI MEMORY MAP section */
+#define CFG_PCI0_MEM_BASE	0x80000000
+#define CFG_PCI0_MEM_SIZE	_128M
+#define CFG_PCI1_MEM_BASE	0x88000000
+#define CFG_PCI1_MEM_SIZE	_128M
+
+#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
+#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+
+
+/* PCI I/O MAP section */
+#define CFG_PCI0_IO_BASE	0xfa000000
+#define CFG_PCI0_IO_SIZE	_16M
+#define CFG_PCI1_IO_BASE	0xfb000000
+#define CFG_PCI1_IO_SIZE	_16M
+
+#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
+#define CFG_PCI0_IO_SPACE_PCI	0x00000000
+#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
+#define CFG_PCI1_IO_SPACE_PCI	0x00000000
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+
+#define CFG_NS16550_REG_SIZE	-4
+
+#define CFG_NS16550_CLK		3686400
+
+#define CFG_NS16550_COM1	(CFG_DUART_IO + 0)
+#define CFG_NS16550_COM2	(CFG_DUART_IO + 0x20)
+
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+
+/* SDRAM */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT0U CFG_IBAT0U
+
+/* init ram */
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+
+/* PCI0, PCI1 in one BAT */
+#define CFG_IBAT2L BATL_NO_ACCESS
+#define CFG_IBAT2U CFG_DBAT2U
+#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U CFG_IBAT3U
+
+/* I2C speed and slave address (for compatability) defaults */
+#define CFG_I2C_SPEED	400000
+#define CFG_I2C_SLAVE	0x7F
+
+/* I2C addresses for the two DIMM SPD chips */
+#ifndef CONFIG_EVB64260_750CX
+#define DIMM0_I2C_ADDR	0x56
+#define DIMM1_I2C_ADDR	0x54
+#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
+#define DIMM0_I2C_ADDR  0x54
+#define DIMM1_I2C_ADDR	0x54
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+
+#define CFG_EXTRA_FLASH_DEVICE	DEVICE3	/* extra flash at device 3 */
+#define CFG_EXTRA_FLASH_WIDTH	4	/* 32 bit */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_CFI		1
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CFG_ENV_ADDR    (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/74xx_7xx.h for the defines used here
+ */
+
+#define CFG_L2
+
+#ifdef CONFIG_750CX
+#define L2_INIT 0
+#else
+#define L2_INIT  	(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#endif
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		    */
+
+#define CFG_BOARD_ASM_INIT      1
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h
new file mode 100755
index 0000000..d85be42
--- /dev/null
+++ b/include/configs/EXBITGEN.h
@@ -0,0 +1,213 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405GP CPU     	*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_EXBITGEN		1	/* on a Exbit Generic board     */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
+
+/* I2C configuration */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#define CFG_I2C_SPEED		40000	/* I2C speed			*/
+#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+
+/* environment is in EEPROM */
+#define CFG_ENV_IS_IN_EEPROM    1
+#undef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_NVRAM
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_I2C_EEPROM_ADDR		0x56    /* 1010110 */
+#define CFG_I2C_EEPROM_ADDR_LEN		1	/* 8-bit internal addressing */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	1	/* ... and 1 bit in I2C address */
+#define CFG_EEPROM_PAGE_WRITE_BITS	3	/* 4 bytes per page */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	40	/* write takes up to 40 msec */
+#define CFG_ENV_OFFSET		4	/* Offset of Environment Sector	*/
+#define	CFG_ENV_SIZE		350	/* that is 350 bytes only!	*/
+#endif
+
+#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds	*/
+/* Explanation:
+   autbooting is altogether disabled and cannot be
+   enabled if CONFIG_BOOTDELAY is negative.
+   If you want shorter bootdelay, then
+   - "setenv bootdelay <delay>" to the proper value
+*/
+
+#define CONFIG_BOOTCOMMAND	"bootm 20400000 20800000"
+
+#define CONFIG_BOOTARGS		"root=/dev/ram "  \
+				"ramdisk_size=32768 " \
+				"console=ttyS0,115200 " \
+				"ram=128M debug"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+/* UART configuration */
+#define CFG_BASE_BAUD		691200
+
+/* Default baud rate */
+#define CONFIG_BAUDRATE		115200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE      \
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#undef CONFIG_PCI			/* no pci support	        */
+
+/*-----------------------------------------------------------------------
+ * External peripheral base address
+ *-----------------------------------------------------------------------
+ */
+#undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
+
+#define	CFG_KEY_REG_BASE_ADDR	0xF0100000
+#define	CFG_IR_REG_BASE_ADDR	0xF0200000
+#define	CFG_FPGA_REG_BASE_ADDR	0xF0300000
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH0_BASE		0xFFF80000
+#define CFG_FLASH0_SIZE		0x00080000
+#define CFG_FLASH1_BASE		0x20000000
+#define CFG_FLASH1_SIZE		0x02000000
+#define CFG_FLASH_BASE		CFG_FLASH0_BASE
+#define CFG_FLASH_SIZE		CFG_FLASH0_SIZE
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+#if CFG_MONITOR_BASE < CFG_FLASH0_BASE
+#define CFG_RAMSTART
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	5	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_OFFSET		0x00060000 /* Offset of Environment Sector      */
+#define	CFG_ENV_SIZE		0x00010000 /* Total Size of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	0x00010000 /* see README - env sector total size */
+#endif
+
+/* On Chip Memory location/size */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+/* Global info and initial stack */
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of on-chip SRAM	*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/* Cache configuration */
+#define CFG_DCACHE_SIZE		8192
+#define CFG_CACHELINE_SIZE	32
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h
new file mode 100755
index 0000000..1b562d6
--- /dev/null
+++ b/include/configs/FADS823.h
@@ -0,0 +1,464 @@
+ /*
+  * A collection of structures, addresses, and values associated with
+  * the Motorola 860T FADS board.  Copied from the MBX stuff.
+  * Magnus Damm added defines for 8xxrom and extended bd_info.
+  * Helmut Buchsbaum added bitvalues for BCSRx
+  *
+  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+  */
+
+/*
+ * 1999-nov-26: The FADS is using the following physical memorymap:
+ *
+ * ff020000 -> ff02ffff : pcmcia     io remapping
+ * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by U-Boot
+ * ff000000 -> ff00ffff : IMAP       internal in the cpu
+ * e0000000 -> f3ffffff : pcmcia     memory remapping by m8xx_pcmcia
+ * fe000000 -> fe1fffff : flash      connected to CS0, setup by U-Boot
+ * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
+*/
+
+#define CFG_PCMCIA_IO_ADDR	0xff020000
+#define CFG_PCMCIA_IO_SIZE	0x10000
+#define CFG_PCMCIA_MEM_ADDR	0xe0000000
+#define CFG_PCMCIA_MEM_SIZE	0x10000
+#define CFG_IMMR		0xFF000000
+#define	CFG_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x02800000
+#define BCSR_ADDR		((uint) 0xff010000)
+#define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0	*/
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define	CONFIG_ETHADDR		08:00:22:50:70:63	/* Ethernet address */
+#define CONFIG_ENV_OVERWRITE	1	/* Overwrite the environment */
+
+#define CONFIG_VIDEO		1	/* To enable video controller support */
+#define CONFIG_HARD_I2C		1	/* To I2C with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+/*Now included by CFG_CMD_PCMCIA */
+/*#define CONFIG_PCMCIA		1	/ * To enable PCMCIA support */
+
+/* Video related */
+
+#define CONFIG_VIDEO_LOGO			1	/* Show the logo */
+#define CONFIG_VIDEO_ENCODER_AD7176		1	/* Enable this encoder */
+#define CONFIG_VIDEO_ENCODER_AD7176_ADDR	0x54	/* Default on fads */
+#define CONFIG_VIDEO_SIZE			(2*1024*1024)
+/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */
+
+/* Wireless 56Khz 4PPM keyboard on SMCx */
+
+/*#define CONFIG_KEYBOARD		1 */
+#define CONFIG_WL_4PPM_KEYBOARD_SMC	0	/* SMC to use (0 indexed) */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC823		1
+#define CONFIG_MPC823FADS	1
+#define CONFIG_FADS		1
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200
+
+/* Set the CPU speed to 50Mhz on the FADS */
+
+#if 0
+#define MPC8XX_FACT	10			/* Multiply by 10		*/
+#define MPC8XX_XIN	5000000			/* 5 MHz in	*/
+#else
+#define MPC8XX_FACT	10			/* Multiply by 10 */
+#define MPC8XX_XIN	5000000			/* 5 MHz in */
+#define CFG_PLPRCR_MF	(MPC8XX_FACT-1) << 20	/* From 0 to 4095 */
+#endif
+#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#if 1
+#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
+#define CONFIG_LOADS_ECHO	0	/* Dont echoes received characters */
+#define CONFIG_BOOTARGS		""
+#define CONFIG_BOOTCOMMAND							\
+"bootp ;" 									\
+"setenv bootargs console=tty0 console=ttyS0 " 					\
+"root=/dev/nfs nfsroot=${serverip}:${rootpath} " 				\
+"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" 	\
+"bootm"
+#else
+#define CONFIG_BOOTDELAY	0	/* autoboot disabled		*/
+#endif
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_ALL
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x01000000	/* 0 ... 16 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x00100000	/* default load address */
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
+ */
+#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#if 0
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define	CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration						11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer  *
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR       (SCCR_TBS     | \
+				SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+				SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+				SCCR_DFALCD00)
+
+ /*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently.  Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register.  For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+/* the other CS:s are determined by looking at parameters in BCSRx */
+
+#define BCSR_SIZE		((uint)(64 * 1024))
+
+#define FLASH_BASE1_PRELIM	0x00000000	/* FLASH bank #1	*/
+
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFFE00000	/* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+/* BCSRx - Board Control and Status Registers */
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	0xffff8110									/* 64Kbyte address space */
+#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA		97		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CFG_MAMR		0x13a01114
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD			0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM			0x02		/* Software reboot			*/
+
+/* values according to the manual */
+
+#define	BCSR0			((uint) (BCSR_ADDR + 00))
+#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
+#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
+#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
+#define	BCSR4			((uint) (BCSR_ADDR + 0x10))
+
+/* FADS bitvalues by Helmut Buchsbaum
+ * see MPC8xxADS User's Manual for a proper description
+ * of the following structures
+ */
+
+#define BCSR0_ERB       ((uint)0x80000000)
+#define BCSR0_IP        ((uint)0x40000000)
+#define BCSR0_BDIS      ((uint)0x10000000)
+#define BCSR0_BPS_MASK  ((uint)0x0C000000)
+#define BCSR0_ISB_MASK  ((uint)0x01800000)
+#define BCSR0_DBGC_MASK ((uint)0x00600000)
+#define BCSR0_DBPC_MASK ((uint)0x00180000)
+#define BCSR0_EBDF_MASK ((uint)0x00060000)
+
+#define BCSR1_FLASH_EN           ((uint)0x80000000)
+#define BCSR1_DRAM_EN            ((uint)0x40000000)
+#define BCSR1_ETHEN              ((uint)0x20000000)
+#define BCSR1_IRDEN              ((uint)0x10000000)
+#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
+#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
+#define BCSR1_BCSR_EN            ((uint)0x02000000)
+#define BCSR1_RS232EN_1          ((uint)0x01000000)
+#define BCSR1_PCCEN              ((uint)0x00800000)
+#define BCSR1_PCCVCC0            ((uint)0x00400000)
+#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
+#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
+#define BCSR1_RS232EN_2          ((uint)0x00040000)
+#define BCSR1_SDRAM_EN           ((uint)0x00020000)
+#define BCSR1_PCCVCC1            ((uint)0x00010000)
+
+#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
+#define BCSR2_FLASH_PD_SHIFT	 28
+#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
+#define BCSR2_DRAM_PD_SHIFT      23
+#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
+#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
+
+#define BCSR3_DBID_MASK          ((ushort)0x3800)
+#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
+#define BCSR3_BREVNR0            ((ushort)0x0080)
+#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
+#define BCSR3_BREVN1             ((ushort)0x0008)
+#define BCSR3_BREVN2_MASK        ((ushort)0x0003)
+
+#define BCSR4_ETHLOOP            ((uint)0x80000000)
+#define BCSR4_TFPLDL             ((uint)0x40000000)
+#define BCSR4_TPSQEL             ((uint)0x20000000)
+#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
+#ifdef CONFIG_MPC823
+#define BCSR4_USB_EN             ((uint)0x08000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860SAR
+#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
+#endif /* CONFIG_MPC860SAR */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETH_EN            ((uint)0x08000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_USB_SPEED          ((uint)0x04000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHCFG0           ((uint)0x04000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VCCO               ((uint)0x02000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHFDE            ((uint)0x02000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VIDEO_ON           ((uint)0x00800000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC823
+#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHCFG1           ((uint)0x00400000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VIDEO_RST          ((uint)0x00200000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHRST            ((uint)0x00200000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_MODEM_EN           ((uint)0x00100000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC823
+#define BCSR4_DATA_VOICE         ((uint)0x00080000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC850
+#define BCSR4_DATA_VOICE         ((uint)0x00080000)
+#endif /* CONFIG_MPC850 */
+
+#define CONFIG_DRAM_50MHZ		1
+#define CONFIG_SDRAM_50MHZ
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS	0
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_fads)
+
+/*
+ * MPC8xx CPM Options
+ */
+#define CONFIG_SCC_ENET 1
+#define CONFIG_SCC2_ENET 1
+#undef  CONFIG_FEC_ENET
+#undef  CONFIG_CPM_IIC
+#undef  CONFIG_UCODE_PATCH
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+/* PCMCIA configuration */
+
+#define PCMCIA_MAX_SLOTS    1
+
+#ifdef CONFIG_MPC860
+#define PCMCIA_SLOT_A 1
+#endif
+
+#define CFG_DAUGHTERBOARD
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h
new file mode 100755
index 0000000..2a986f0
--- /dev/null
+++ b/include/configs/FADS850SAR.h
@@ -0,0 +1,416 @@
+ /*
+  * A collection of structures, addresses, and values associated with
+  * the Motorola 860T FADS board.  Copied from the MBX stuff.
+  * Magnus Damm added defines for 8xxrom and extended bd_info.
+  * Helmut Buchsbaum added bitvalues for BCSRx
+  *
+  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+  */
+
+/*
+ * 1999-nov-26: The FADS is using the following physical memorymap:
+ *
+ * ff020000 -> ff02ffff : pcmcia
+ * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxrom
+ * ff000000 -> ff00ffff : IMAP       internal in the cpu
+ * fe000000 -> ffnnnnnn : flash      connected to CS0, setup by 8xxrom
+ * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC850		1
+#define CONFIG_MPC850SAR	1
+#define CONFIG_FADS			1
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600
+
+#if 0
+#define MPC8XX_FACT	10				/* Multiply by 10		*/
+#define MPC8XX_XIN	50000000		/* 50 MHz in	*/
+#else
+#define MPC8XX_FACT	12				/* Multiply by 12 */
+#define MPC8XX_XIN	4000000			/* 4 MHz in */
+#endif
+#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#if 1
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_BOOTCOMMAND	"bootm 02880000"	/* autoboot command */
+#define CONFIG_BOOTARGS		" "
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00800000	/* 0 ... 8 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x00100000	/* default load address */
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR			0xFF000000
+#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define	CFG_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
+#define CFG_FLASH_BASE		0x02800000
+#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#if 0
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 128 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define	CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration						11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer  *
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CFG_PLPRCR	(((MPC8XX_FACT-1) << 20) | \
+				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR       (SCCR_TBS     | \
+				SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+				SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+				SCCR_DFALCD00)
+
+ /*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently.  Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register.  For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+/* the other CS:s are determined by looking at parameters in BCSRx */
+
+
+#define BCSR_ADDR		((uint) 0x02100000)
+#define BCSR_SIZE		((uint)(64 * 1024))
+
+#define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x00000000	/* FLASH bank #1	*/
+
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFFE00000	/* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+/* BCSRx - Board Control and Status Registers */
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	0xffff8110									/* 64Kbyte address space */
+#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA		97		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CFG_MAMR		0x13a01114
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD			0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM			0x02		/* Software reboot			*/
+
+
+/* values according to the manual */
+
+
+#define PCMCIA_MEM_ADDR		((uint)0xff020000)
+#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
+
+#define	BCSR0			((uint) (BCSR_ADDR + 00))
+#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
+#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
+#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
+#define	BCSR4			((uint) (BCSR_ADDR + 0x10))
+
+/* FADS bitvalues by Helmut Buchsbaum
+ * see MPC8xxADS User's Manual for a proper description
+ * of the following structures
+ */
+
+#define BCSR0_ERB       ((uint)0x80000000)
+#define BCSR0_IP        ((uint)0x40000000)
+#define BCSR0_BDIS      ((uint)0x10000000)
+#define BCSR0_BPS_MASK  ((uint)0x0C000000)
+#define BCSR0_ISB_MASK  ((uint)0x01800000)
+#define BCSR0_DBGC_MASK ((uint)0x00600000)
+#define BCSR0_DBPC_MASK ((uint)0x00180000)
+#define BCSR0_EBDF_MASK ((uint)0x00060000)
+
+#define BCSR1_FLASH_EN           ((uint)0x80000000)
+#define BCSR1_DRAM_EN            ((uint)0x40000000)
+#define BCSR1_ETHEN              ((uint)0x20000000)
+#define BCSR1_IRDEN              ((uint)0x10000000)
+#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
+#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
+#define BCSR1_BCSR_EN            ((uint)0x02000000)
+#define BCSR1_RS232EN_1          ((uint)0x01000000)
+#define BCSR1_PCCEN              ((uint)0x00800000)
+#define BCSR1_PCCVCC0            ((uint)0x00400000)
+#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
+#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
+#define BCSR1_RS232EN_2          ((uint)0x00040000)
+#define BCSR1_SDRAM_EN           ((uint)0x00020000)
+#define BCSR1_PCCVCC1            ((uint)0x00010000)
+
+#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
+#define BCSR2_FLASH_PD_SHIFT	 28
+#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
+#define BCSR2_DRAM_PD_SHIFT      23
+#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
+#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
+
+#define BCSR3_DBID_MASK          ((ushort)0x3800)
+#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
+#define BCSR3_BREVNR0            ((ushort)0x0080)
+#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
+#define BCSR3_BREVN1             ((ushort)0x0008)
+#define BCSR3_BREVN2_MASK        ((ushort)0x0003)
+
+#define BCSR4_ETHLOOP            ((uint)0x80000000)
+#define BCSR4_TFPLDL             ((uint)0x40000000)
+#define BCSR4_TPSQEL             ((uint)0x20000000)
+#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
+#ifdef CONFIG_MPC823
+#define BCSR4_USB_EN             ((uint)0x08000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860SAR
+#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
+#endif /* CONFIG_MPC860SAR */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETH_EN            ((uint)0x08000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_USB_SPEED          ((uint)0x04000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHCFG0           ((uint)0x04000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VCCO               ((uint)0x02000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHFDE            ((uint)0x02000000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VIDEO_ON           ((uint)0x00800000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC823
+#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHCFG1           ((uint)0x00400000)
+#endif /* CONFIG_MPC860T */
+#ifdef CONFIG_MPC823
+#define BCSR4_VIDEO_RST          ((uint)0x00200000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETHRST            ((uint)0x00200000)
+#endif /* CONFIG_MPC860T */
+#define BCSR4_MODEM_EN           ((uint)0x00100000)
+#define BCSR4_DATA_VOICE         ((uint)0x00080000)
+
+#define CONFIG_DRAM_50MHZ		1
+#define CONFIG_SDRAM_50MHZ
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS	0
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_fads)
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+
+/* PCMCIA configuration */
+
+#define PCMCIA_MAX_SLOTS    2
+
+#ifdef CONFIG_MPC860
+#define PCMCIA_SLOT_A 1
+#endif
+
+#define CFG_DAUGHTERBOARD
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/FADS860T.h b/include/configs/FADS860T.h
new file mode 100755
index 0000000..18de6b0
--- /dev/null
+++ b/include/configs/FADS860T.h
@@ -0,0 +1,56 @@
+/*
+  * A collection of structures, addresses, and values associated with
+  * the Motorola 860T FADS board.  Copied from the MBX stuff.
+  * Magnus Damm added defines for 8xxrom and extended bd_info.
+  * Helmut Buchsbaum added bitvalues for BCSRx
+  *
+  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+  *
+  * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
+  *
+  * Values common to all FADS family boards are in board/fads/fads.h
+  */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* board type */
+#define CONFIG_FADS		1       /* old/new FADS + new ADS */
+
+/* processor type */
+#define CONFIG_MPC860T		1       /* 860T */
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+
+#if 0 /* old FADS */
+# define CFG_8XX_FACT		12	/* 4 MHz oscillator on EXTCLK */
+#else /* new FADS */
+# define CFG_8XX_FACT		10	/* 5 MHz oscillator on EXTCLK */
+#endif
+
+#define CFG_PLPRCR  (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+		PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+#define CONFIG_DRAM_50MHZ		1
+#define CONFIG_SDRAM_50MHZ              1
+
+#include "fads.h"
+
+#ifdef USE_REAL_FLASH_VALUES
+/*
+ * These values fit our FADS860T ...
+ * The "default" behaviour with 1Mbyte initial doesn't work for us!
+ */
+#undef CFG_OR0_PRELIM
+#undef CFG_BR0_PRELIM
+#define CFG_OR0_PRELIM	0x0FFC00D34 /* Real values for the board */
+#define CFG_BR0_PRELIM	0x02800001  /* Real values for the board */
+#endif
+
+#define CFG_DAUGHTERBOARD /* FADS has processor-specific daughterboard */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h
new file mode 100755
index 0000000..8babee1
--- /dev/null
+++ b/include/configs/FLAGADM.h
@@ -0,0 +1,302 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_FLAGADM		1	/* ...on a FLAGA DM	*/
+#define CONFIG_8xx_GCLK_FREQ 48000000	/*48MHz*/
+
+#undef	CONFIG_8xx_CONS_SMC1		/* Console is on SMC1		*/
+#define CONFIG_8xx_CONS_SMC2	1
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
+
+#undef	CONFIG_CLOCKS_IN_MHZ
+
+#if 0
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=bootp"
+#define CONFIG_BOOTCOMMAND							\
+   "setenv bootargs root=/dev/ram ip=off panic=1;"     \
+   "bootm 40040000 400e0000"
+#else
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=bootp panic=1"
+#define CONFIG_BOOTCOMMAND	"bootp 0x400000; bootm 0x400000"
+#endif /* 0|1*/
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+/*#define	CONFIG_WATCHDOG*/	/* watchdog enabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS (CFG_CMD_BDI | CFG_CMD_IMI | CFG_CMD_CACHE | \
+		CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_LOADS | \
+		CFG_CMD_ENV | CFG_CMD_REGINFO | CFG_CMD_IMMAP | CFG_CMD_NET)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"EEG> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x40040000	/* default load address */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_ENV_IS_IN_FLASH	1
+/* This is a litlebit wasteful, but one sector is 128kb and we have to
+ * assigne a whole sector for the environment, so that we can safely
+ * erase and write it without disturbing the boot sector
+ */
+#define CFG_ENV_OFFSET		0x20000 /*   Offset   of Environment Sector	*/
+#define CFG_ENV_SIZE		0x20000 /* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#ifdef CONFIG_WATCHDOG
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \
+							SIUMCR_MLRC01 | SIUMCR_GB5E)
+#define CFG_SIUMCR (CFG_PRE_SIUMCR | SIUMCR_DLK)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit miltiplier of 0x00b i.e. operation clock is
+ * 4MHz * (0x00b+1) = 4MHz * 12 =  48MHz
+ */
+#define CFG_PLPRCR	(0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	( SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+#define CFG_DER 0
+
+/*
+ * In the Flaga DM we have:
+ * Flash on BR0/OR0/CS0a at 0x40000000
+ * Display on BR1/OR1/CS1 at 0x20000000
+ * SDRAM on BR2/OR2/CS2 at 0x00000000
+ * Free BR3/OR3/CS3
+ * DSP1 on BR4/OR4/CS4 at 0x80000000
+ * DSP2 on BR5/OR5/CS5 at 0xa0000000
+ *
+ * For now we just configure the Flash and the SDRAM and leave the others
+ * untouched.
+*/
+
+#define CFG_FLASH_PROTECTION 0
+
+#define FLASH_BASE0		0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_OR_AM		0xff000000	/* OR addr mask */
+#define CFG_OR_ATM		0x00006000
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | \
+				 OR_SCY_3_CLK | OR_TRLX | OR_EHTR )
+
+#define CFG_OR0_PRELIM	(CFG_OR_AM | CFG_OR_ATM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/*
+ * BR2 and OR2 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2			0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	( 0x00000800 )
+
+#define CFG_OR2_PRELIM	(CFG_OR_AM | CFG_OR_TIMING_SDRAM)
+#define CFG_BR2_PRELIM	((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#define CFG_BR2			CFG_BR2_PRELIM
+#define CFG_OR2			CFG_OR2_PRELIM
+
+/*
+ * MAMR settings for SDRAM
+ */
+#define CFG_MAMR_48_SDR (CFG_MAMR_PTA |	 MAMR_WLFA_1X | MAMR_RLFA_1X  \
+					| MAMR_G0CLA_A11)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	0x0F000000
+
+/*
+   * BR4 and OR4 (DSP1)
+   *
+   * We do not wan't preliminary setup of the DSP, anyway we need the
+   * UPMB setup correctly before we can access the DSP.
+   *
+*/
+#define DSP_BASE 0x80000000
+
+#define CFG_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS)
+#define CFG_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V )
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h
new file mode 100755
index 0000000..0dd21bc
--- /dev/null
+++ b/include/configs/FPS850L.h
@@ -0,0 +1,362 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_FPS850L		1	/* ...on a FingerPrint Sensor	*/
+
+#undef	CONFIG_8xx_CONS_SMC1
+#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		19200
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_BOOTCOMMAND	"bootm 40020000" /* autoboot command	*/
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
+				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
+				"nfsaddrs=10.0.0.99:10.0.0.2"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_ALL
+
+#define CONFIG_COMMANDS	    ( CONFIG_CMD_DFL &		~( \
+					CFG_CMD_CONSOLE	| \
+					CFG_CMD_BDI	| \
+					CFG_CMD_LOADS	| \
+					CFG_CMD_LOADB	| \
+					CFG_CMD_CACHE	) )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h
new file mode 100755
index 0000000..423d74e
--- /dev/null
+++ b/include/configs/FPS860L.h
@@ -0,0 +1,330 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
+#define CONFIG_FPS860L		1	/* ...on a FingerPrint Sensor	*/
+
+#undef	CONFIG_8xx_CONS_SMC1
+#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_BOOTCOMMAND	"bootm 40040000" /* autoboot command	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
+				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
+				"nfsaddrs=10.0.0.99:10.0.0.2"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_ALL
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+				 OR_SCY_5_CLK | OR_EHTR)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/G2000.h b/include/configs/G2000.h
new file mode 100755
index 0000000..db42fd0
--- /dev/null
+++ b/include/configs/G2000.h
@@ -0,0 +1,426 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_G2000		1	/* ...on a PLU405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+
+#if 0 /* test-only */
+#define CONFIG_BAUDRATE		115200
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+#define CONFIG_PREBOOT
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0"				\
+	"addmisc=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate} "				\
+		"panic=1\0"						\
+	"flash_nfs=run nfsargs addip addmisc;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addmisc;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};"				\
+		"run nfsargs addip addmisc;bootm\0"			\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/g2000/pImage\0"				\
+	"kernel_addr=ff800000\0"				        \
+	"ramdisk_addr=ff900000\0"				        \
+	"pciconfighost=yes\0"				                \
+	""
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_NET_MULTI	1
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY1_ADDR	1	/* PHY address			*/
+
+#if 0 /* test-only */
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+#endif
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_EEPROM	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#if 0 /* test-only */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*----------------------------------------------------------------------------*/
+/* adding Ethernet setting:  FTS OUI 00:11:0B */
+/*----------------------------------------------------------------------------*/
+#define CONFIG_ETHADDR          00:11:0B:00:00:01
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR         00:11:0B:00:00:02
+#define CONFIG_IPADDR		10.48.8.178
+#define CONFIG_IP1ADDR		10.48.8.188
+#define CONFIG_NETMASK		255.255.255.128
+#define CONFIG_SERVERIP		10.48.8.138
+
+/*-----------------------------------------------------------------------
+ * RTC stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_RTC_DS1337
+#define CFG_I2C_RTC_ADDR	0x68
+
+#if 0 /* test-only */
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
+
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#if 0 /* APC405 */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#undef CFG_FLASH_PROTECTION		/* don't use hardware protection	*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_BASE		0xFE000000 /* test-only...*/
+#define CFG_FLASH_INCREMENT	0x01000000 /* test-only */
+#else /* G2000 */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#undef CFG_FLASH_PROTECTION		/* don't use hardware protection	*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_BASE		0xFF800000 /* test-only...*/
+#define CFG_FLASH_INCREMENT	0x01000000 /* test-only */
+#endif
+
+#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+
+#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MONITOR_BASE	0xFFFC0000
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#if 1 /* test-only */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#else	/* DEFAULT: environment in flash, using redundand flash sectors */
+
+#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define CFG_ENV_ADDR		0xFFFA0000 /* environment starts before u-boot */
+#define CFG_ENV_SECT_SIZE	0x20000	/* 128k bytes may be used for env vars*/
+
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
+/* CAT24WC08/16... */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Intel Strata Flash) initialization                            */
+#define CFG_EBC_PB0AP   0x92015480
+#define CFG_EBC_PB0CR   0xFF87A000          /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 1 ( Power TAU) initialization               */
+/* #define CFG_EBC_PB1AP           0x04041000 */
+/* #define CFG_EBC_PB1CR           0xF0018000   */  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+#define CFG_EBC_PB1AP           0x00000000
+#define CFG_EBC_PB1CR           0x00000000
+
+/* Memory Bank 2 (Intel Flash) initialization                 */
+#define CFG_EBC_PB2AP           0x00000000
+#define CFG_EBC_PB2CR           0x00000000
+
+/* Memory Bank 3 (NAND) initialization                        */
+#define CFG_EBC_PB3AP           0x92015480
+#define CFG_EBC_PB3CR           0xF40B8000  /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */
+
+/* Memory Bank 4 (FPGA regs) initialization                                     */
+#define CFG_EBC_PB4AP           0x00000000
+#define CFG_EBC_PB4CR           0x00000000  /* leave it blank  */
+
+#define CFG_NAND_BASE   0xF4000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]     - External Bus Controller BLAST output
+ * GPIO0[1-9]   - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ *
+ * following GPIO setting changed for G20000, 080304
+ */
+#define CFG_GPIO0_OSRH          0x40005555
+#define CFG_GPIO0_OSRL          0x40000110
+#define CFG_GPIO0_ISR1H         0x00000000
+#define CFG_GPIO0_ISR1L         0x15555445
+#define CFG_GPIO0_TSRH          0x00000000
+#define CFG_GPIO0_TSRL          0x00000000
+#define CFG_GPIO0_TCR           0xF7FF8014
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_266_66_33_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_66_33_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h
new file mode 100755
index 0000000..de8f7ae
--- /dev/null
+++ b/include/configs/GEN860T.h
@@ -0,0 +1,766 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config_GEN860T.h - board specific configuration options
+ */
+
+#ifndef __CONFIG_GEN860T_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC860
+#define CONFIG_GEN860T
+
+/*
+ * Identify the board
+ */
+#if !defined(CONFIG_SC)
+#define CONFIG_IDENT_STRING				" B2"
+#else
+#define CONFIG_IDENT_STRING				" SC"
+#endif
+
+/*
+ * Don't depend on the RTC clock to determine clock frequency -
+ * the 860's internal rtc uses a 32.768 KHz clock which is
+ * generated by the DS1337 - and the DS1337 clock can be turned off.
+ */
+#if !defined(CONFIG_SC)
+#define	CONFIG_8xx_GCLK_FREQ			66600000
+#else
+#define	CONFIG_8xx_GCLK_FREQ			48000000
+#endif
+
+/*
+ * The RS-232 console port is on SMC1
+ */
+#define	CONFIG_8xx_CONS_SMC1
+#define CONFIG_BAUDRATE					38400
+
+/*
+ * Set allowable console baud rates
+ */
+#define CFG_BAUDRATE_TABLE				{ 9600,		\
+							 		 	  19200,	\
+							 		 	  38400,	\
+									 	  57600,	\
+									 	  115200,	\
+										}
+
+/*
+ * Print console information
+ */
+#undef	 CFG_CONSOLE_INFO_QUIET
+
+/*
+ * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
+ */
+#define CONFIG_BOOTDELAY				5
+
+/*
+ * Pass the clock frequency to the Linux kernel in units of MHz
+ */
+#define	CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_PREBOOT		\
+	"echo;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND	\
+	"bootp;" \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+	"bootm"
+
+/*
+ * Turn off echo for serial download by default.  Allow baud rate to be changed
+ * for downloads
+ */
+#undef	CONFIG_LOADS_ECHO
+#define	CFG_LOADS_BAUD_CHANGE
+
+/*
+ * Set default load address for tftp network downloads
+ */
+#define	CFG_TFTP_LOADADDR				0x01000000
+
+/*
+ * Turn off the watchdog timer
+ */
+#undef	CONFIG_WATCHDOG
+
+/*
+ * Do not reboot if a panic occurs
+ */
+#define CONFIG_PANIC_HANG
+
+/*
+ * Enable the status LED
+ */
+#define	CONFIG_STATUS_LED
+
+/*
+ * Reset address. We pick an address such that when an instruction
+ * is executed at that address, a machine check exception occurs
+ */
+#define CFG_RESET_ADDRESS				((ulong) -1)
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_MASK				( CONFIG_BOOTP_DEFAULT		| \
+									  	  CONFIG_BOOTP_BOOTFILESIZE   \
+										)
+
+/*
+ * The GEN860T network interface uses the on-chip 10/100 FEC with
+ * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
+ * MII address is hardwired on the board to zero.
+ */
+#define CONFIG_FEC_ENET
+#define CFG_DISCOVER_PHY
+#define CONFIG_MII
+#define CONFIG_PHY_ADDR         		0
+
+/*
+ * Set default IP stuff just to get bootstrap entries into the
+ * environment so that we can autoscript the full default environment.
+ */
+#define CONFIG_ETHADDR					9a:52:63:15:85:25
+#define CONFIG_SERVERIP					10.0.4.201
+#define CONFIG_IPADDR					10.0.4.111
+
+/*
+ * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
+ * the MPC860T I2C interface.
+ */
+#define CFG_I2C_EEPROM_ADDR				0x50
+#define CFG_EEPROM_PAGE_WRITE_BITS		6		/* 64 byte pages		*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	12		/* 10 mS w/ 20% margin	*/
+#define	CFG_I2C_EEPROM_ADDR_LEN			2		/* need 16 bit address	*/
+#define CFG_ENV_EEPROM_SIZE				(32 * 1024)
+
+/*
+ * Enable I2C and select the hardware/software driver
+ */
+#define CONFIG_HARD_I2C		1				/* CPM based I2C			*/
+#undef	CONFIG_SOFT_I2C        				/* Bit-banged I2C			*/
+
+#ifdef CONFIG_HARD_I2C
+#define	CFG_I2C_SPEED		100000			/* clock speed in Hz		*/
+#define CFG_I2C_SLAVE		0xFE			/* I2C slave address		*/
+#endif
+
+#ifdef CONFIG_SOFT_I2C
+#define PB_SCL				0x00000020		/* PB 26					*/
+#define PB_SDA				0x00000010		/* PB 27 					*/
+#define I2C_INIT			(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE			(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE		(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ			((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+								else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+								else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY			udelay(5)		/* 1/4 I2C clock duration	*/
+#endif
+
+/*
+ * Allow environment overwrites by anyone
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if !defined(CONFIG_SC)
+/*
+ * The MPC860's internal RTC is horribly broken in rev D masks. Three
+ * internal MPC860T circuit nodes were inadvertently left floating; this
+ * causes KAPWR current in power down mode to be three orders of magnitude
+ * higher than specified in the datasheet (from 10 uA to 10 mA).  No
+ * reasonable battery can keep that kind RTC running during powerdown for any
+ * length of time, so we use an external RTC on the I2C bus instead.
+ */
+#define CONFIG_RTC_DS1337
+#define CFG_I2C_RTC_ADDR				0x68
+
+#else
+/*
+ * No external RTC on SC variant, so we're stuck with the internal one.
+ */
+#define	CONFIG_RTC_MPC8xx
+#endif
+
+/*
+ * Power On Self Test support
+ */
+#define CONFIG_POST			  ( CFG_POST_CACHE		| \
+								CFG_POST_MEMORY		| \
+								CFG_POST_CPU		| \
+								CFG_POST_UART		| \
+								CFG_POST_SPR )
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+#else
+#define CFG_CMD_POST_DIAG		0
+#endif
+
+/*
+ * List of available monitor commands.  Use the system default list
+ * plus add some of the "non-standard" commands back in.
+ * See ./cmd_confdefs.h
+ */
+#define BASE_CONFIG_COMMANDS	( CONFIG_CMD_DFL	| \
+								CFG_CMD_ASKENV	| \
+								CFG_CMD_DHCP	| \
+								CFG_CMD_I2C		| \
+								CFG_CMD_EEPROM	| \
+								CFG_CMD_REGINFO	| \
+								CFG_CMD_IMMAP	| \
+								CFG_CMD_ELF		| \
+								CFG_CMD_DATE	| \
+								CFG_CMD_FPGA	| \
+								CFG_CMD_MII 	| \
+								CFG_CMD_BEDBUG	| \
+								CFG_CMD_POST_DIAG )
+
+#if !defined(CONFIG_SC)
+#define	CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC )
+#else
+#define CONFIG_COMMANDS	BASE_CONFIG_COMMANDS
+#endif
+
+/*
+ * There is no IDE/PCMCIA hardware support on the board.
+ */
+#undef  CONFIG_IDE_PCMCIA
+#undef  CONFIG_IDE_LED
+#undef  CONFIG_IDE_RESET
+
+/*
+ * Enable the call to misc_init_r() for miscellaneous platform
+ * dependent initialization.
+ */
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Enable call to last_stage_init() so we can twiddle some LEDS :)
+ */
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * Virtex2 FPGA configuration support
+ */
+#define CONFIG_FPGA_COUNT		1
+#define CONFIG_FPGA				CFG_XILINX_VIRTEX2
+#define CFG_FPGA_PROG_FEEDBACK
+
+
+/************************************************************************
+ * This must be included AFTER the definition of any CONFIG_COMMANDS
+ */
+#include <cmd_confdefs.h>
+
+/*
+ * Verbose help from command monitor.
+ */
+#define	CFG_LONGHELP
+#if !defined(CONFIG_SC)
+#define	CFG_PROMPT			"B2> "
+#else
+#define	CFG_PROMPT			"SC> "
+#endif
+
+
+/*
+ * Use the "hush" command parser
+ */
+#define	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+
+/*
+ * Set buffer size for console I/O
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE			1024
+#else
+#define	CFG_CBSIZE			256
+#endif
+
+/*
+ * Print buffer size
+ */
+#define	CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+/*
+ * Maximum number of arguments that a command can accept
+ */
+#define	CFG_MAXARGS			16
+
+/*
+ * Boot argument buffer size
+ */
+#define CFG_BARGSIZE		CFG_CBSIZE
+
+/*
+ * Default memory test range
+ */
+#define CFG_MEMTEST_START	0x0100000
+#define CFG_MEMTEST_END		(CFG_MEMTEST_START  + (128 * 1024))
+
+/*
+ * Select the more full-featured memory test
+ */
+#define	CFG_ALT_MEMTEST
+
+/*
+ * Default load address
+ */
+#define	CFG_LOAD_ADDR		0x01000000
+
+/*
+ * Set decrementer frequency (1 ms ticks)
+ */
+#define	CFG_HZ				1000
+
+/*
+ * Device memory map (after SDRAM remap to 0x0):
+ *
+ * CS		Device				Base Addr	Size
+ * ----------------------------------------------------
+ * CS0*		Flash				0x40000000	64 M
+ * CS1*		SDRAM				0x00000000	16 M
+ * CS2*		Disk-On-Chip		0x50000000	32 K
+ * CS3*		FPGA				0x60000000	64 M
+ * CS4*		SelectMap			0x70000000	32 K
+ * CS5*		Mil-Std 1553 I/F	0x80000000	32 K
+ * CS6*		Unused
+ * CS7*		Unused
+ * IMMR		860T Registers		0xfff00000
+ */
+
+/*
+ * Base addresses and block sizes
+ */
+#define CFG_IMMR			0xFF000000
+
+#define SDRAM_BASE			0x00000000
+#define SDRAM_SIZE			(64 * 1024 * 1024)
+
+#define FLASH_BASE			0x40000000
+#define FLASH_SIZE			(16 * 1024 * 1024)
+
+#define DOC_BASE			0x50000000
+#define DOC_SIZE			(32 * 1024)
+
+#define FPGA_BASE			0x60000000
+#define FPGA_SIZE			(64 * 1024 * 1024)
+
+#define SELECTMAP_BASE		0x70000000
+#define SELECTMAP_SIZE		(32 * 1024)
+
+#define M1553_BASE			0x80000000
+#define M1553_SIZE			(64 * 1024)
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR		CFG_IMMR
+#define	CFG_INIT_RAM_END		0x2F00	/* End of used area in DPRAM		*/
+#define	CFG_INIT_DATA_SIZE		64  	/* # bytes reserved for initial data*/
+#define CFG_GBL_DATA_OFFSET		(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET		CFG_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE			SDRAM_BASE
+
+/*
+ * FLASH organization
+ */
+#define CFG_FLASH_BASE			FLASH_BASE
+#define CFG_FLASH_SIZE			FLASH_SIZE
+#define CFG_FLASH_SECT_SIZE		(128 * 1024)
+#define CFG_MAX_FLASH_BANKS		1
+#define CFG_MAX_FLASH_SECT		128
+
+/*
+ * The timeout values are for an entire chip and are in milliseconds.
+ * Yes I know that the write timeout is huge.  Accroding to the
+ * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
+ * case VCC and temp after 100K programming cycles.  It works out
+ * to 280 minutes (might as well be forever).
+ */
+#define CFG_FLASH_ERASE_TOUT	(CFG_MAX_FLASH_SECT * 5000)
+#define CFG_FLASH_WRITE_TOUT	(CFG_MAX_FLASH_SECT * 128 * 1024 * 1)
+
+/*
+ * Allow direct writes to FLASH from tftp transfers (** dangerous **)
+ */
+#define	CFG_DIRECT_FLASH_TFTP
+
+/*
+ * Reserve memory for U-Boot.
+ */
+#define CFG_MAX_UBOOT_SECTS		4
+#define	CFG_MONITOR_LEN			(CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE)
+#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+
+/*
+ * Select environment placement.  NOTE that u-boot.lds must
+ * be edited if this is changed!
+ */
+#undef	CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_IN_EEPROM
+
+#if defined(CFG_ENV_IS_IN_EEPROM)
+#define CFG_ENV_SIZE			(2 * 1024)
+#define CFG_ENV_OFFSET			(CFG_ENV_EEPROM_SIZE - (8 * 1024))
+#else
+#define CFG_ENV_SIZE			0x1000
+#define CFG_ENV_SECT_SIZE		CFG_FLASH_SECT_SIZE
+
+/*
+ * This ultimately gets passed right into the linker script, so we have to
+ * use a number :(
+ */
+#define CFG_ENV_OFFSET			0x060000
+#endif
+
+/*
+ * Reserve memory for malloc()
+ */
+#define	CFG_MALLOC_LEN		(128 * 1024)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/*
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE		16	/* For all MPC8xx CPUs				*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT		4	/* log base 2 of above value		*/
+#endif
+
+/*------------------------------------------------------------------------
+ * SYPCR - System Protection Control							UM 11-9
+ * -----------------------------------------------------------------------
+ * SYPCR can only be written once after reset!
+ *
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	( SYPCR_SWTC	| \
+					  SYPCR_BMT 	| \
+					  SYPCR_BME 	| \
+					  SYPCR_SWF 	| \
+					  SYPCR_SWE 	| \
+					  SYPCR_SWRI	| \
+					  SYPCR_SWP		  \
+					)
+#else
+#define CFG_SYPCR	( SYPCR_SWTC	| \
+					  SYPCR_BMT 	| \
+					  SYPCR_BME 	| \
+					  SYPCR_SWF 	| \
+					  SYPCR_SWP		  \
+					)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration							UM 11-6
+ *-----------------------------------------------------------------------
+ * Set debug pin mux, enable SPKROUT and GPLB5*.
+ */
+#define CFG_SIUMCR	( SIUMCR_DBGC11 | \
+					  SIUMCR_DBPC11 | \
+					  SIUMCR_MLRC11	| \
+					  SIUMCR_GB5E	  \
+					)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control							UM 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freeze enabled
+ */
+#define CFG_TBSCR	( TBSCR_REFA | \
+					  TBSCR_REFB | \
+					  TBSCR_TBF	   \
+					)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register			UM 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	( RTCSC_SEC	| \
+					  RTCSC_ALR | \
+					  RTCSC_RTF | \
+					  RTCSC_RTE	  \
+					)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control				UM 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	( PISCR_PS		| \
+					  PISCR_PITF	  \
+					)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register			UM 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit. Set MF for 1:2:1 mode.
+ */
+#define CFG_PLPRCR	( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)	| \
+					  PLPRCR_SPLSS	| \
+					  PLPRCR_TEXPS	| \
+					  PLPRCR_TMIST	  \
+					)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register				UM 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK   SCCR_EBDF11
+
+#if !defined(CONFIG_SC)
+#define CFG_SCCR	( SCCR_TBS			| 	/* timebase = GCLK/2	*/ \
+					  SCCR_COM00   		| 	/* full strength CLKOUT	*/ \
+					  SCCR_DFSYNC00 	| 	/* SYNCLK / 1 (normal)	*/ \
+					  SCCR_DFBRG00		| 	/* BRGCLK / 1 (normal)	*/ \
+					  SCCR_DFNL000		| \
+					  SCCR_DFNH000		  \
+					)
+#else
+#define CFG_SCCR	( SCCR_TBS			| 	/* timebase = GCLK/2	*/ \
+					  SCCR_COM00   		| 	/* full strength CLKOUT	*/ \
+					  SCCR_DFSYNC00 	| 	/* SYNCLK / 1 (normal)	*/ \
+					  SCCR_DFBRG00		| 	/* BRGCLK / 1 (normal)	*/ \
+					  SCCR_DFNL000		| \
+					  SCCR_DFNH000		| \
+					  SCCR_RTDIV		| \
+					  SCCR_RTSEL		  \
+					)
+#endif
+
+/*-----------------------------------------------------------------------
+ * DER - Debug Enable Register									UM 37-46
+ *-----------------------------------------------------------------------
+ * Mask all events that can cause entry into debug mode
+ */
+#define CFG_DER				0
+
+/*
+ * Initialize Memory Controller:
+ *
+ * BR0 and OR0 (FLASH memory)
+ */
+#define FLASH_BASE0_PRELIM	FLASH_BASE
+
+/*
+ * Flash address mask
+ */
+#define CFG_PRELIM_OR_AM	0xfe000000
+
+/*
+ * FLASH timing:
+ * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
+ */
+#define CFG_OR_TIMING_FLASH	( OR_CSNT_SAM	| \
+							  OR_ACS_DIV2	| \
+							  OR_BI			| \
+							  OR_SCY_2_CLK	| \
+							  OR_TRLX		| \
+							  OR_EHTR		  \
+							)
+
+#define CFG_OR0_PRELIM	( CFG_PRELIM_OR_AM		| \
+						  CFG_OR_TIMING_FLASH	  \
+						)
+
+#define CFG_BR0_PRELIM	( (FLASH_BASE0_PRELIM & BR_BA_MSK)	| \
+						  BR_MS_GPCM						| \
+						  BR_PS_8							| \
+						  BR_V 								  \
+						)
+
+/*
+ * SDRAM configuration
+ */
+#define CFG_OR1_AM	0xfc000000
+#define CFG_OR1		( (CFG_OR1_AM & OR_AM_MSK)	| \
+					  OR_CSNT_SAM				  \
+					)
+
+#define CFG_BR1		( (SDRAM_BASE & BR_BA_MSK)	| \
+					  BR_MS_UPMA 				| \
+					  BR_PS_32	 				| \
+					  BR_V 						  \
+					)
+
+/*
+ * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
+ * of 256 MBit SDRAM
+ */
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16
+
+/*
+ * Periodic timer for refresh @ 33 MHz system clock
+ */
+#define CFG_MAMR_PTA	64
+
+/*
+ * MAMR settings for SDRAM
+ */
+#define CFG_MAMR_8COL	( (CFG_MAMR_PTA << MAMR_PTA_SHIFT)	| \
+						  MAMR_PTAE	    			| \
+						  MAMR_AMA_TYPE_1			| \
+						  MAMR_DSA_1_CYCL 			| \
+						  MAMR_G0CLA_A10			| \
+						  MAMR_RLFA_1X				| \
+						  MAMR_WLFA_1X				| \
+						  MAMR_TLFA_4X				  \
+						)
+
+/*
+ * CS2* configuration for Disk On Chip:
+ * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
+ * no burst.
+ */
+#define CFG_OR2_PRELIM 	( (0xffff0000 & OR_AM_MSK)	| \
+						  OR_CSNT_SAM				| \
+						  OR_ACS_DIV2				| \
+						  OR_BI						| \
+						  OR_SCY_2_CLK				| \
+						  OR_TRLX					| \
+						  OR_EHTR					  \
+						)
+
+#define CFG_BR2_PRELIM	( (DOC_BASE & BR_BA_MSK)	| \
+						  BR_PS_8					| \
+						  BR_MS_GPCM				| \
+						  BR_V						  \
+						)
+
+/*
+ * CS3* configuration for FPGA:
+ * 33 MHz bus with SCY=15, no burst.
+ * The FPGA uses TA and TEA to terminate bus cycles, but we
+ * clear SETA and set the cycle length to a large number so that
+ * the cycle will still complete even if there is a configuration
+ * error that prevents TA from asserting on FPGA accesss.
+ */
+#define CFG_OR3_PRELIM	( (0xfc000000 & OR_AM_MSK)  | \
+						  OR_SCY_15_CLK				| \
+						  OR_BI 					  \
+						)
+
+#define CFG_BR3_PRELIM	( (FPGA_BASE & BR_BA_MSK)	| \
+						  BR_PS_32					| \
+						  BR_MS_GPCM				| \
+						  BR_V		  				  \
+						)
+/*
+ * CS4* configuration for FPGA SelectMap configuration interface.
+ * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
+ * of GCLK1_50
+ */
+#define CFG_OR4_PRELIM	( (0xffff0000 & OR_AM_MSK)  	| \
+						  OR_G5LS						| \
+						  OR_BI							  \
+						)
+
+#define CFG_BR4_PRELIM	( (SELECTMAP_BASE & BR_BA_MSK)	| \
+						  BR_PS_8						| \
+						  BR_MS_UPMB					| \
+						  BR_V			  				  \
+						)
+
+/*
+ * CS5* configuration for Mil-Std 1553 databus interface.
+ * 33 MHz bus, GPCM, no burst.
+ * The 1553 interface  uses TA and TEA to terminate bus cycles,
+ * but we clear SETA and set the cycle length to a large number so that
+ * the cycle will still complete even if there is a configuration
+ * error that prevents TA from asserting on FPGA accesss.
+ */
+#define CFG_OR5_PRELIM	( (0xffff0000 & OR_AM_MSK)  | \
+						  OR_SCY_15_CLK				| \
+						  OR_EHTR					| \
+						  OR_TRLX					| \
+						  OR_CSNT_SAM				| \
+						  OR_BI						  \
+						)
+
+#define CFG_BR5_PRELIM	( (M1553_BASE & BR_BA_MSK)	| \
+						  BR_PS_16					| \
+						  BR_MS_GPCM				| \
+						  BR_V			  			  \
+						)
+
+/*
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02	/* Software reboot					*/
+
+/*
+ * Disk On Chip (millenium) configuration
+ */
+#if !defined(CONFIG_SC)
+#define CFG_MAX_DOC_DEVICE	1
+#undef	CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+#undef	CFG_DOC_PASSIVE_PROBE
+#endif
+
+/*
+ * FEC interrupt assignment
+ */
+#define FEC_INTERRUPT   SIU_LEVEL1
+
+/*
+ * Sanity checks
+ */
+#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
+#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
+#endif
+
+#endif	/* __CONFIG_GEN860T_H */
+
+/* vim: set ts=4 tw=78 ai shiftwidth=4: */
diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h
new file mode 100755
index 0000000..8c01d97
--- /dev/null
+++ b/include/configs/GENIETV.h
@@ -0,0 +1,354 @@
+ /*
+  * A collection of structures, addresses, and values associated with
+  * the Motorola 860T FADS board.  Copied from the MBX stuff.
+  * Magnus Damm added defines for 8xxrom and extended bd_info.
+  * Helmut Buchsbaum added bitvalues for BCSRx
+  *
+  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+  */
+
+/*
+ * The GENIETV is using the following physical memorymap (copied from
+ * the FADS configuration):
+ *
+ * ff020000 -> ff02ffff : pcmcia
+ * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxROM
+ * ff000000 -> ff00ffff : IMAP       internal in the cpu
+ * 30000000 -> 300fffff : flash      connected to CS0
+ * 00000000 -> nnnnnnnn : sdram      setup by U-Boot
+ *
+ * CS pins are connected as follows:
+ *
+ * CS0 -512Kb boot flash
+ * CS1 - SDRAM #1
+ * CS2 - SDRAM #2
+ * CS3 - Flash #1
+ * CS4 - Flash #2
+ * CS5 - Lon (if present)
+ * CS6 - PCMCIA #1
+ * CS7 - PCMCIA #2
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define	CONFIG_ETHADDR		08:00:22:50:70:63	/* Ethernet address */
+#define CONFIG_ENV_OVERWRITE	1	/* Overwrite the environment */
+
+#define CFG_ALLOC_DPRAM			/* Use dynamic DPRAM allocation */
+
+#define CFG_AUTOLOAD		"n"	/* No autoload */
+
+/*#define CONFIG_VIDEO		1	/  To enable the video initialization */
+/*#define CONFIG_VIDEO_ADDR	0x00200000 */
+/*#define CONFIG_HARD_I2C	1	/  I2C with hardware support */
+/*#define CONFIG_PCMCIA		1	/  To enable the PCMCIA initialization */
+
+/*#define CFG_PCMCIA_IO_ADDR	0xff020000 */
+/*#define CFG_PCMCIA_IO_SIZE	0x10000 */
+/*#define CFG_PCMCIA_MEM_ADDR	0xe0000000 */
+/*#define CFG_PCMCIA_MEM_SIZE	0x10000 */
+
+/* Video related */
+
+/*#define CONFIG_VIDEO_LOGO			1	/  Show the logo */
+/*#define CONFIG_VIDEO_ENCODER_AD7177		1	/  Enable this encoder */
+/*#define CONFIG_VIDEO_ENCODER_AD7177_ADDR	0xF4	/  ALSB to ground */
+
+/* Wireless 56Khz 4PPM keyboard on SMCx */
+
+/*#define CONFIG_KEYBOARD		0 */
+/*#define CONFIG_WL_4PPM_KEYBOARD_SMC	0	/  SMC to use (0 indexed) */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#include <mpc8xx_irq.h>
+
+#define CONFIG_GENIETV		1
+#define CONFIG_MPC823		1
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600
+
+#define MPC8XX_FACT	12 			/* Multiply by 12	*/
+#define MPC8XX_XIN	5000000			/* 4 MHz clock 		*/
+
+#define MPC8XX_HZ 	((MPC8XX_XIN) * (MPC8XX_FACT))
+#define CFG_PLPRCR_MF	((MPC8XX_FACT-1) << 20)
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ	/* Force it - dont measure it */
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#if 1
+#define CONFIG_BOOTDELAY	1	/* autoboot after 2 seconds	*/
+#define CONFIG_LOADS_ECHO	0	/* Dont echoes received characters */
+#define CONFIG_BOOTARGS		""
+#define CONFIG_BOOTCOMMAND							\
+"bootp; tftp; "									\
+"setenv bootargs console=tty0 console=ttyS0 " 					\
+"root=/dev/nfs nfsroot=${serverip}:${rootpath} " 				\
+"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" 	\
+"bootm "
+#else
+#define CONFIG_BOOTDELAY	0	/* autoboot disabled		*/
+#endif
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		8		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00800000	/* 0 ... 8 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x00100000	/* default load address */
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 4800, 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x02800000
+#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#if 0
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 128 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x10000	/* Offset of Environment Sector 	*/
+#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector (64k)*/
+
+/* values according to the manual */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration						11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ *
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC10)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer  *
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ *
+ * #define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR       (SCCR_TBS     | \
+				SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+				SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+				SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently.  Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register.  For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0(FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0		*/
+
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask 	*/
+#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask (512Kb) */
+
+/* FLASH timing */
+#define CFG_OR_TIMING_FLASH 	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+				OR_SCY_15_CLK | OR_TRLX )
+
+/*#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH) */
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) 		/* 0xfff80ff4 */
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)	/* 0x02800401 */
+
+/*
+ * BR1/2 and OR1/2 (SDRAM)
+*/
+
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define SDRAM_MAX_SIZE		0x04000000	/* 64Mb bank */
+#define SDRAM_BASE1_PRELIM	0x00000000	/* First bank */
+#define SDRAM_BASE2_PRELIM	0x10000000	/* Second bank */
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MBMR_PTB		0x5d		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32
+/*
+ * MBMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
+			MAMR_G0CLA_A11 | MAMR_RLFA_1X | MAMR_WLFA_1X \
+			| MAMR_TLFA_4X)	/* 0x5d802114 */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD			0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM			0x02		/* Software reboot			*/
+
+/* values according to the manual */
+
+#define CONFIG_DRAM_50MHZ		1
+#define CONFIG_SDRAM_50MHZ
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS	0
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_fads)
+
+/*
+ * MPC8xx CPM Options
+ */
+#define CONFIG_SCC_ENET 1
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+/* PCMCIA configuration */
+
+#define PCMCIA_MAX_SLOTS    1
+#define PCMCIA_SLOT_B 1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/GTH.h b/include/configs/GTH.h
new file mode 100755
index 0000000..03b9659
--- /dev/null
+++ b/include/configs/GTH.h
@@ -0,0 +1,374 @@
+/*
+  * Parameters for GTH board
+  * Based on FADS860T
+  * by thomas.lange@corelatus.com
+
+  * A collection of structures, addresses, and values associated with
+  * the Motorola 860T FADS board.  Copied from the MBX stuff.
+  * Magnus Damm added defines for 8xxrom and extended bd_info.
+  * Helmut Buchsbaum added bitvalues for BCSRx
+  *
+  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+  */
+
+/*
+ * ff000000 -> ff00ffff : IMAP       internal in the cpu
+ * e0000000 -> ennnnnnn : pcmcia
+ * 98000000 -> 983nnnnn : FPGA 4MB
+ * 90000000 -> 903nnnnn : FPGA 4MB
+ * 80000000 -> 80nnnnnn : flash      connected to CS0, final ( real ) location
+ * 00000000 -> nnnnnnnn : sdram
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#include <mpc8xx_irq.h>
+
+#define CONFIG_MPC860		1
+#define CONFIG_MPC860T		1
+#define CONFIG_GTH		1
+
+#define CONFIG_MISC_INIT_R      1
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+
+#define MPC8XX_FACT		3		/* Multiply by 3 */
+#define MPC8XX_XIN		16384000	/* 16.384 MHz */
+#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
+
+#define CONFIG_BOOTDELAY	1	/* autoboot after 0 seconds	*/
+
+#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */
+
+#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */
+
+#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */
+
+/* Only interrupt boot if space is pressed */
+/* If a long serial cable is connected but */
+/* other end is dead, garbage will be read */
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n"
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+#if 0
+/* Net boot */
+/* Loads a tftp image and starts it */
+#define CONFIG_BOOTCOMMAND	"bootp;bootm 100000"	/* autoboot command */
+#define CONFIG_BOOTARGS		"panic=1"
+#else
+/* Compact flash boot */
+#define CONFIG_BOOTARGS "panic=1 root=/dev/hda7"
+#define CONFIG_BOOTCOMMAND "disk 100000 0:5;bootm 100000"
+#endif
+
+/* Enable watchdog */
+#define CONFIG_WATCHDOG 1
+
+/* choose SCC1 ethernet (10BASET on motherboard)
+ * or FEC ethernet (10/100 on daughterboard)
+ */
+#if 1
+#define	CONFIG_SCC1_ENET	1	/* use SCC1 ethernet */
+#undef	CONFIG_FEC_ENET			/* disable FEC ethernet  */
+#define CFG_DISCOVER_PHY
+#else
+#undef	CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
+#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
+#define CFG_DISCOVER_PHY
+#endif
+#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
+#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
+#endif
+
+#define CONFIG_COMMANDS               (CONFIG_CMD_DFL | CFG_CMD_IDE)
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_PROMPT		"=>"	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+
+/* Default location to load data from net */
+#define CFG_LOAD_ADDR	 	0x100000
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR			0xFF000000
+#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+
+#define CFG_FLASH_BASE		0x80000000
+
+#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+
+#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+
+#define CFG_MONITOR_BASE TEXT_BASE
+
+#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH 1
+#undef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_OFFSET		0x000E0000
+#define	CFG_ENV_SIZE		 0x4000 	/* Total Size of Environment Sector	*/
+
+#define CFG_ENV_SECT_SIZE	0x50000	/* see README - env sector total size	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration					11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+
+/*FIXME dont use for now */
+/*#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+/*#define CFG_RTCSC	(RTCSC_RTF) */
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+/* PITE */
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control (15-29)
+ */
+#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+
+/* FIXME check values */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS|SCCR_RTSEL|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+
+ /*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently.  Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register.  For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+/* the other CS:s are determined by looking at parameters in BCSRx */
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+
+#define CFG_REMAP_OR_AM		0xFF800000	/* 4 MB OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+
+#define FPGA_2_BASE 0x90000000
+#define FPGA_3_BASE 0x98000000
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16 )
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_ETHADDR          DE:AD:BE:EF:00:01    /* Ethernet address */
+
+#ifdef CONFIG_MPC860T
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
+
+#endif /* CONFIG_MPC860T */
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS	0
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_gth)
+
+#ifdef CONFIG_MPC860
+#define PCMCIA_SLOT_A 1
+#define CONFIG_PCMCIA_SLOT_A 1
+#endif
+
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+#define CONFIG_IDE_8xx_PCCARD       1       /* Use IDE with PC Card Adapter */
+#undef  CONFIG_IDE_8xx_DIRECT               /* Direct IDE    not supported  */
+#undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
+#undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
+
+#define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
+#define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
+
+#define CFG_ATA_IDE0_OFFSET     0x0000
+#define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
+/* Offset for data I/O                  */
+#define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
+/* Offset for normal register accesses  */
+#define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+/* Offset for alternate registers       */
+#define CFG_ATA_ALT_OFFSET      0x0100
+
+#define CONFIG_8xx_GCLK_FREQ   MPC8XX_HZ       /* Force it - dont measure it */
+
+#define PA_FRONT_LED ((u16)0x4) /* PA 13 */
+#define PA_FL_CONFIG ((u16)0x20) /* PA 10 */
+#define PA_FL_CE     ((u16)0x1000) /* PA 3 */
+
+#define PB_ID_GND    ((u32)1) /* PB 31 */
+#define PB_REV_1     ((u32)2) /* PB 30 */
+#define PB_REV_0     ((u32)4) /* PB 29 */
+#define PB_BLUE_LED  ((u32)0x400) /* PB 21 */
+#define PB_EEPROM    ((u32)0x800) /* PB 20 */
+#define PB_ID_3      ((u32)0x2000) /* PB 18 */
+#define PB_ID_2      ((u32)0x4000) /* PB 17 */
+#define PB_ID_1      ((u32)0x8000) /* PB 16 */
+#define PB_ID_0      ((u32)0x10000) /* PB 15 */
+
+/* NOTE. This is reset for 100Mbit port only */
+#define PC_ENET100_RESET	((ushort)0x0080) /* PC 8 */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
new file mode 100755
index 0000000..131c215
--- /dev/null
+++ b/include/configs/HH405.h
@@ -0,0 +1,527 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_HH405		1	/* ...on a HH405 board 	        */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+
+#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT	        "autoupd"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"pciconfighost=1\0"						\
+	""
+
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+/*
+ * Video console
+ */
+#define CONFIG_VIDEO			/* for sm501 video support	*/
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501
+#if 0
+#define CONFIG_VIDEO_SM501_32BPP
+#else
+#define CONFIG_VIDEO_SM501_16BPP
+#endif
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CFG_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP		/* gzip compressed bmp images	*/
+#define CFG_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* for decompressed img */
+
+#define ADD_BMP_CMD		CFG_CMD_BMP
+#else
+#define ADD_BMP_CMD		0
+#endif /* CONFIG_VIDEO */
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_EXT2	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				ADD_BMP_CMD	| \
+				CFG_CMD_EEPROM  )
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
+#undef CONFIG_AUTO_UPDATE_SHOW          /* use board show routine       */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef  CONFIG_BZIP2	 /* include support for bzip2 compressed images */
+#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+
+#undef  CFG_CONSOLE_INFO_QUIET          /* print console @ startup	*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
+#define CFG_BASE_BAUD       691200
+#define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE      \
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * RTC stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_RTC_DS1338
+#define CFG_I2C_RTC_ADDR	0x68
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */
+
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define	CFG_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
+#define	CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define	CFG_ATA_BASE_ADDR	0xF0100000
+#define	CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define	CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
+#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
+#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
+#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
+#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+
+#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFF80000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc()	*/
+
+#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CFG_RAMBOOT		1
+#else
+# undef CFG_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF4080000		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		0x8000		        /* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#if 0 /* test-only */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#else
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
+#endif
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
+#define CFG_EEPROM_WREN         1
+
+#if 1 /* test-only */
+/* CAT24WC08/16... */
+#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last	4 bits of the address	*/
+#else
+/* CAT24WC32/64... */
+#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+					/* 32 byte page write mode using*/
+					/* last	5 bits of the address	*/
+#endif
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's    */
+					/* have only 8kB, 16kB is save here     */
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+#define CAN_BA          0xF0000000          /* CAN Base Address                 */
+#define LCD_BA          0xF1000000          /* Epson LCD Base Address           */
+#define CFG_NAND_BASE   0xF4000000          /* NAND FLASH Base Address          */
+#define CFG_NVRAM_BASE  0xF4080000          /* NVRAM Base Address               */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
+#define CFG_EBC_PB0AP           0x92015480
+#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization              */
+#define CFG_EBC_PB1AP           0x92015480
+#define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
+#define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
+#define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (Epson LCD) initialization                                     */
+#define CFG_EBC_PB4AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
+#define CFG_EBC_PB4CR   LCD_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * LCD Setup
+ */
+
+#define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
+#define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
+#define CFG_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
+#define CFG_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
+
+/*-----------------------------------------------------------------------
+ * Universal Interrupt Controller (UIC) Setup
+ */
+
+/*
+ * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
+ */
+#define CFG_UIC0_POLARITY       (0xFFFFFF80 | UIC_EXT6)
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+
+#define CFG_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address       */
+
+/* FPGA internal regs */
+#define CFG_FPGA_CTRL           0x000
+
+/* FPGA Control Reg */
+#define CFG_FPGA_CTRL_REV0      0x0001
+#define CFG_FPGA_CTRL_REV1      0x0002
+#define CFG_FPGA_CTRL_VGA0_BL   0x0004
+#define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008
+#define CFG_FPGA_CTRL_CF_RESET  0x0040
+#define CFG_FPGA_CTRL_PS2_PWR   0x0080
+#define CFG_FPGA_CTRL_CF_PWR    0x0100      /* low active                    */
+#define CFG_FPGA_CTRL_CF_BUS_EN 0x0200
+#define CFG_FPGA_CTRL_LCD_CLK   0x7000      /* Mask for lcd clock            */
+
+#define LCD_CLK_OFF             0x0000      /* Off                           */
+#define LCD_CLK_02083           0x1000      /* 2.083 MHz                     */
+#define LCD_CLK_03135           0x2000      /* 3.135 MHz                     */
+#define LCD_CLK_04165           0x3000      /* 4.165 MHz                     */
+#define LCD_CLK_06250           0x4000      /* 6.250 MHz                     */
+#define LCD_CLK_08330           0x5000      /* 8.330 MHz                     */
+#define LCD_CLK_12500           0x6000      /* 12.50 MHz                     */
+#define LCD_CLK_25000           0x7000      /* 25.00 MHz                     */
+
+#define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]     - External Bus Controller BLAST output
+ * GPIO0[1-9]   - Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+#define CFG_GPIO0_ISR1L		0x15555440
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FE0017
+
+#define CFG_LCD_ENDIAN		(0x80000000 >> 7)
+#define CFG_EEPROM_WP		(0x80000000 >> 8)   /* GPIO8 */
+#define CFG_TOUCH_RST		(0x80000000 >> 9)   /* GPIO9 */
+#define CFG_LCD0_RST		(0x80000000 >> 30)
+#define CFG_LCD1_RST		(0x80000000 >> 31)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h
new file mode 100755
index 0000000..6864740
--- /dev/null
+++ b/include/configs/HIDDEN_DRAGON.h
@@ -0,0 +1,387 @@
+/*
+ * (C) Copyright 2004
+ * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
+ *
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8245		1
+#define CONFIG_HIDDEN_DRAGON	1
+
+#if 0
+#define USE_DINK32		1
+#else
+#undef USE_DINK32
+#endif
+
+#define CONFIG_CONS_INDEX	3		/* set to '3' for on-chip DUART */
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_DRAM_SPEED	100		/* MHz				*/
+
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
+				  CFG_CMD_EEPROM | \
+				  CFG_CMD_ELF	| \
+				  CFG_CMD_I2C	| \
+				  CFG_CMD_NET	| \
+				  CFG_CMD_PCI	| \
+				  CFG_CMD_PING	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		1		/* undef to save memory		*/
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI				/* include pci support		*/
+#undef CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI			/* Multi ethernet cards support */
+
+#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+
+#define PCI_ENET0_IOADDR	0x80000000
+#define PCI_ENET0_MEMADDR	0x80000000
+#define PCI_ENET1_IOADDR	0x81000000
+#define PCI_ENET1_MEMADDR	0x81000000
+
+#define CONFIG_RTL8139
+#define _IO_BASE	    0x00000000
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x)	    (x)
+/* Make sure the ethaddr can be overwritten
+   TODO: Remove this on final product
+*/
+#define CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MAX_RAM_SIZE	0x02000000
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#if defined (USE_DINK32)
+#define CFG_MONITOR_LEN		0x00030000
+#define CFG_MONITOR_BASE	0x00090000
+#define CFG_RAMBOOT		1
+#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_INIT_RAM_END	0x10000
+#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#else
+#undef	CFG_RAMBOOT
+#define CFG_MONITOR_LEN		0x00030000
+#define CFG_MONITOR_BASE	TEXT_BASE
+
+#define CFG_GBL_DATA_SIZE	128
+
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x1000
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#endif
+
+#define CFG_FLASH_BASE		0xFFE00000
+#define CFG_FLASH_SIZE		(2 * 1024 * 1024)	/* Unity has onboard 1MByte flash */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
+#define CFG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
+
+#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+#define CFG_EUMB_ADDR		0xFC000000
+
+#define CFG_ISA_MEM		0xFD000000
+#define CFG_ISA_IO		0xFE000000
+
+#define CFG_FLASH_RANGE_BASE	0xFFE00000	/* flash memory address range	*/
+#define CFG_FLASH_RANGE_SIZE	0x00200000
+#define FLASH_BASE0_PRELIM	0xFFE00000	/* processor board flash	*/
+
+/*
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
+#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#ifdef CONFIG_SOFT_I2C
+#error "Soft I2C is not configured properly.  Please review!"
+#define I2C_PORT		3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
+#define I2C_READ		((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
+				else	iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
+				else	iop->pdat &= ~0x00020000
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1		/* Bytes of address		*/
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM }
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+
+#define CFG_WINBOND_83C553	1	/*has a winbond bridge			*/
+#define CFG_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
+#define CFG_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
+#define CFG_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
+
+#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+/* TODO: Change this to VIA686A */
+
+/*
+ * NS87308 Configuration
+ */
+#define CFG_NS87308			/* Nat Semi super-io controller on ISA bus */
+
+#define CFG_NS87308_BADDR_10	1
+
+#define CFG_NS87308_DEVS	( CFG_NS87308_UART1   | \
+				  CFG_NS87308_UART2   | \
+				  CFG_NS87308_POWRMAN | \
+				  CFG_NS87308_RTC_APC )
+
+#undef	CFG_NS87308_PS2MOD
+
+#define CFG_NS87308_CS0_BASE	0x0076
+#define CFG_NS87308_CS0_CONF	0x30
+#define CFG_NS87308_CS1_BASE	0x0075
+#define CFG_NS87308_CS1_CONF	0x30
+#define CFG_NS87308_CS2_BASE	0x0074
+#define CFG_NS87308_CS2_CONF	0x30
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	1
+
+#if (CONFIG_CONS_INDEX > 2)
+#define CFG_NS16550_CLK		CONFIG_DRAM_SPEED*1000000
+#else
+#define CFG_NS16550_CLK		1843200
+#endif
+
+#define CFG_NS16550_COM1	(CFG_ISA_IO + CFG_NS87308_UART1_BASE)
+#define CFG_NS16550_COM2	(CFG_ISA_IO + CFG_NS87308_UART2_BASE)
+#define CFG_NS16550_COM3	(CFG_EUMB_ADDR + 0x4500)
+#define CFG_NS16550_COM4	(CFG_EUMB_ADDR + 0x4600)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
+
+#define CFG_ROMNAL		7	/*rom/flash next access time		*/
+#define CFG_ROMFAL		11	/*rom/flash access time			*/
+
+#define CFG_REFINT	430	/* no of clock cycles between CBR refresh cycles */
+
+/* the following are for SDRAM only*/
+#define CFG_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
+#define CFG_REFREC		8	/* Refresh to activate interval		*/
+#define CFG_RDLAT		4	/* data latency from read command	*/
+#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
+#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CFG_ACTORW		3	/* Activate to R/W			*/
+#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#if 0
+#define CFG_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
+#endif
+
+#define CFG_REGISTERD_TYPE_BUFFER   1
+#define CFG_EXTROM 1
+#define CFG_REGDIMM 0
+
+
+/* memory bank settings*/
+/*
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CFG_BANK0_START		0x00000000
+#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE	1
+#define CFG_BANK1_START		0x3ff00000
+#define CFG_BANK1_END		0x3fffffff
+#define CFG_BANK1_ENABLE	0
+#define CFG_BANK2_START		0x3ff00000
+#define CFG_BANK2_END		0x3fffffff
+#define CFG_BANK2_ENABLE	0
+#define CFG_BANK3_START		0x3ff00000
+#define CFG_BANK3_END		0x3fffffff
+#define CFG_BANK3_ENABLE	0
+#define CFG_BANK4_START		0x00000000
+#define CFG_BANK4_END		0x00000000
+#define CFG_BANK4_ENABLE	0
+#define CFG_BANK5_START		0x00000000
+#define CFG_BANK5_END		0x00000000
+#define CFG_BANK5_ENABLE	0
+#define CFG_BANK6_START		0x00000000
+#define CFG_BANK6_END		0x00000000
+#define CFG_BANK6_ENABLE	0
+#define CFG_BANK7_START		0x00000000
+#define CFG_BANK7_END		0x00000000
+#define CFG_BANK7_ENABLE	0
+/*
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CFG_BANK_ENABLE		0x01
+
+#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+					/* see 8240 book for bit definitions	*/
+#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+/* SDRAM 0 - 256MB */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#if defined(USE_DINK32)
+#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
+#else
+#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#endif
+
+/* PCI memory */
+#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	36	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+/* values according to the manual */
+#define CONFIG_DRAM_50MHZ	1
+#define CONFIG_SDRAM_50MHZ
+
+#undef	NR_8259_INTS
+#define NR_8259_INTS		1
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h
new file mode 100755
index 0000000..7cce876
--- /dev/null
+++ b/include/configs/HMI10.h
@@ -0,0 +1,493 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_HMI10
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_TQM823L		1	/* ...on a TQM8xxL module	*/
+
+#define CONFIG_LCD
+#define CONFIG_NEC_NL6448BC33_54	/* NEC NL6448BC33_54 display	*/
+
+#ifdef	CONFIG_LCD			/* with LCD controller ?	*/
+#define CONFIG_SPLASH_SCREEN		/* ... with splashscreen support*/
+#endif
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
+#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
+#define CONFIG_PS2SERIAL	2	/* .. on COM3			*/
+#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/HMI10/uImage\0"				\
+	"kernel_addr=40040000\0"					\
+	"ramdisk_addr=40100000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define	CONFIG_BOARD_EARLY_INIT_R 1
+#define CONFIG_MISC_INIT_R	  1
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+
+#define CFG_I2C_SPEED		40000	/* 40 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+/* Software (bit-bang) I2C driver configuration */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#define CONFIG_CAN_DRIVER	1	/* CAN Driver support enabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
+#define CFG_I2C_RTC_ADDR 0x68		/* at address 0x68		*/
+
+#ifdef	CONFIG_SPLASH_SCREEN
+# define CONFIG_COMMANDS      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_BMP	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+#else
+# define CONFIG_COMMANDS      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0100000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4100000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8100000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC100000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define PCMCIA_MEM_WIN_NO	5
+#define NSCU_OE_INV		1		/* PCMCIA_GCRX_CXOE is inverted */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+#ifndef CONFIG_STATUS_LED		/* Status and IDE LED's are mutually exclusive */
+#define CONFIG_IDE_LED		1	/* LED   for ide supported	*/
+#endif
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096	 Rows from SDRAM example configuration
+ * 1000	 factor s -> ms
+ *   32	 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4	 Number of refresh cycles per period
+ *   64	 Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
new file mode 100755
index 0000000..eb627e8
--- /dev/null
+++ b/include/configs/HUB405.h
@@ -0,0 +1,392 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_HUB405		1	/* ...on a HUB405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_EEPROM	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/* Ethernet stuff */
+#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
+#define CONFIG_ETHADDR	00:50:C2:1E:AF:FE
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
+
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#undef	CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (8 Bit Peripheral: UART) initialization			*/
+#if 0
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#else
+#define CFG_EBC_PB2AP		0x92015480
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#endif
+
+#define DUART0_BA	0xF0000000	    /* DUART Base Address		*/
+#define DUART1_BA	0xF0000008	    /* DUART Base Address		*/
+#define DUART2_BA	0xF0000010	    /* DUART Base Address		*/
+#define DUART3_BA	0xF0000018	    /* DUART Base Address		*/
+#define CFG_NAND_BASE	0xF4000000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+#define CFG_GPIO0_ISR1L		0x15555445
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FE0014
+
+#define CFG_DUART_RST           (0x80000000 >> 14)
+#define CFG_UART2_RS232         (0x80000000 >> 5)
+#define CFG_UART3_RS232         (0x80000000 >> 6)
+#define CFG_UART4_RS232         (0x80000000 >> 7)
+#define CFG_UART5_RS232         (0x80000000 >> 8)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h
new file mode 100755
index 0000000..35d84ae
--- /dev/null
+++ b/include/configs/IAD210.h
@@ -0,0 +1,379 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <mpc8xx_irq.h>
+
+
+# ifdef DEBUG
+#  warning DEBUG Defined
+# endif /* DEBUG */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC860		1
+#define CONFIG_IAD210		1	/* ...on a IAD210  module	*/
+#define CONFIG_MPC860T		1
+#define CONFIG_MPC862		1
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+
+#undef  CONFIG_8xx_CONS_SMC1
+#undef  CONFIG_8xx_CONS_SMC2
+#define CONFIG_8xx_CONS_SCC2   /* V24 on SCC2 */
+#undef  CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600
+
+
+# define MPC8XX_FACT            16
+# define CONFIG_8xx_GCLK_FREQ   (64000000L)  /* define if can't use get_gclk_freq */
+# define CONFIG_CLOCKS_IN_MHZ	1            /* clocks passsed to Linux in MHz */
+
+#if 0
+# define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+# define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+/* using this define saves us updating another source file */
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+#undef	CONFIG_BOOTARGS
+/* #define CONFIG_BOOTCOMMAND							\
+ 	"bootp;" 								\
+ 	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+ 	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" 	\
+ 	"bootm"
+*/
+
+#define CONFIG_BOOTCOMMAND	\
+	"setenv bootargs root=/dev/nfs" 	\
+	"ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " 	\
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/* #define	CONFIG_STATUS_LED	1*/	/* Status LED enabled		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+# undef  CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
+# define CONFIG_FEC_ENET    1	/* use FEC ethernet  */
+# define CONFIG_MII         1
+# define CFG_DISCOVER_PHY   1
+# define CONFIG_FEC_UTOPIA  1
+# define CONFIG_ETHADDR     08:00:06:26:A2:6D
+# define CONFIG_IPADDR      192.168.28.128
+# define CONFIG_SERVERIP    139.10.137.138
+# define CFG_DISCOVER_PHY   1
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support    */
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged               */
+# define CFG_I2C_SPEED		50000
+# define CFG_I2C_SLAVE		0xDD
+# define CFG_I2C_EEPROM_ADDR	0x50
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DATE	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR	 	0x00100000
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x08000000
+#define CFG_FLASH_SIZE		((uint)(4 * 1024 * 1024))	/* max 16Mbyte */
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#if defined(DEBUG)
+# define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+# define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+
+# define CFG_MONITOR_BASE	CFG_FLASH_BASE
+# define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x8000
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration					11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control (15-29)
+ */
+#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+
+#define CFG_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
+			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
+			 SCCR_DFLCD000	|SCCR_DFALCD00	)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register		19-4
+ *-----------------------------------------------------------------------
+ */
+/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
+#define CFG_RCCR 0x0020
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCMCIA_MEM_ADDR		((uint)0xff020000)
+#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently.  Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register.  For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0xF8000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xF8000000	/* OR addr mask */
+
+/* FLASH timing:
+ TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | \
+				 OR_SCY_3_CLK | OR_EHTR)
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | OR_CSNT_SAM  | OR_BI | OR_ACS_DIV4)
+#define CFG_BR2_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	124		/* start with divider for 64 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR	        MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_8X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#ifdef CONFIG_MPC860T
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
+
+#endif /* CONFIG_MPC860T */
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h
new file mode 100755
index 0000000..cd17935
--- /dev/null
+++ b/include/configs/ICU862.h
@@ -0,0 +1,456 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <mpc8xx_irq.h>
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC860		1
+#define CONFIG_MPC860T		1
+#define CONFIG_ICU862		1
+#define CONFIG_MPC862		1
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+
+#ifdef CONFIG_100MHz
+#define MPC8XX_FACT		24		/* Multiply by 24	*/
+#define MPC8XX_XIN		4165000		/* 4.165 MHz in		*/
+#define CONFIG_8xx_GCLK_FREQ	(MPC8XX_FACT * MPC8XX_XIN)
+				    /* define if cant' use get_gclk_freq */
+#else
+#if 1				/* for 50MHz version of processor	*/
+#define MPC8XX_FACT		12		/* Multiply by 12	*/
+#define MPC8XX_XIN		4000000		/* 4 MHz in		*/
+#define CONFIG_8xx_GCLK_FREQ	48000000 /* define if cant use get_gclk_freq */
+#else				/* for 80MHz version of processor	*/
+#define MPC8XX_FACT		20		/* Multiply by 20	*/
+#define MPC8XX_XIN		4000000		/* 4 MHz in		*/
+#define CONFIG_8xx_GCLK_FREQ    80000000 /* define if cant use get_gclk_freq */
+#endif
+#endif
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp;" 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" 	\
+	"bootm"
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#undef	CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
+#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
+#define	CONFIG_MII		1
+#if 1
+#define CFG_DISCOVER_PHY	1
+#else
+#undef	CFG_DISCOVER_PHY
+#endif
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+# define CFG_I2C_SPEED		50000
+# define CFG_I2C_SLAVE		0xFE
+# define CFG_I2C_EEPROM_ADDR	0x50
+# define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CFG_EEPROM_X40430		/* Use a Xicor X40430 EEPROM	*/
+#define CFG_EEPROM_PAGE_WRITE_BITS  4	/* 16 bytes page write mode	*/
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR	 	0x00100000
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define CFG_FLASH_SIZE		((uint)(16 * 1024 * 1024))	/* max 16Mbyte */
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#if 0
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#else
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#endif
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
+
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00F40000
+
+#define CFG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Used Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration					11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control (15-29)
+ */
+#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#ifdef CONFIG_100MHz	/* for 100 MHz, external bus is half CPU clock */
+#define SCCR_MASK	0
+#define CFG_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
+			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
+			 SCCR_DFLCD000	|SCCR_DFALCD00	| SCCR_EBDF01)
+#else			/* up to 50 MHz we use a 1:1 clock */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
+			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
+			 SCCR_DFLCD000	|SCCR_DFALCD00	)
+#endif	/* CONFIG_100MHz */
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register		19-4
+ *-----------------------------------------------------------------------
+ */
+/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
+#define CFG_RCCR 0x0020
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * PCMCIA Power Switch
+ *
+ * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to
+ * control the voltages on the PCMCIA slot which is connected to Port B
+ *-----------------------------------------------------------------------
+ */
+			/* Output pins */
+#define TPS2205_VCC5	0x00008000	/* PB.16:  5V Voltage Control	*/
+#define TPS2205_VCC3	0x00004000	/* PB.17:  3V Voltage Control	*/
+#define TPS2205_VPP_PGM	0x00002000	/* PB.18: PGM Voltage Control	*/
+#define TPS2205_VPP_VCC	0x00001000	/* PB.19: VPP Voltage Control	*/
+#define TPS2205_SHDN	0x00000200	/* PB.22: Shutdown		*/
+#define TPS2205_OUTPUTS ( TPS2205_VCC5    | TPS2205_VCC3    | \
+			  TPS2205_VPP_PGM | TPS2205_VPP_VCC | \
+			  TPS2205_SHDN)
+
+			/* Input pins */
+#define TPS2205_OC	0x00000100	/* PB.23: Over-Current		*/
+#define TPS2205_INPUTS	( TPS2205_OC )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+
+ /*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently.  Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register.  For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x0		/* FLASH bank #1	*/
+
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+
+#define CFG_OR0_PRELIM	0xFF000954		/* Real values for the board */
+#define CFG_BR0_PRELIM	0x40000001		/* Real values for the board */
+
+/*
+ * BR1 and OR1 (SDRAM)
+ */
+#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank		*/
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+#define CFG_OR_TIMING_SDRAM	0x00000800	/* BIH is not set	*/
+
+#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
+#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA		97	/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CFG_MAMR		0x13a01114
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#ifdef CONFIG_MPC860T
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
+
+#endif /* CONFIG_MPC860T */
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
new file mode 100755
index 0000000..aaa44c5
--- /dev/null
+++ b/include/configs/IDS8247.h
@@ -0,0 +1,525 @@
+/*
+ * (C) Copyright 2005
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
+#define CONFIG_MPC8272_FAMILY	1
+#define CONFIG_IDS8247		1
+#define CPU_ID_STR		"MPC8247"
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw "			\
+	"console=ttyS0,115200\0"					\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/IDS8247/uImage\0"				\
+	"kernel_addr=ff800000\0"					\
+	"ramdisk_addr=ffa00000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_MISC_INIT_R	1
+
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+
+#define I2C_PORT	0		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00000080)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00000080)
+#define I2C_READ	((iop->pdat & 0x00000080) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00000080; \
+			else    iop->pdat &= ~0x00000080
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00000100; \
+			else    iop->pdat &= ~0x00000100
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#if 0
+#define CFG_I2C_EEPROM_ADDR	0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CONFIG_I2C_X
+#endif
+
+/*
+ * select serial console configuration
+ * use the extern UART for the console
+ */
+#define	CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE    1
+
+#define CFG_NS16550_CLK         14745600
+
+#define	CFG_UART_BASE	0xE0000000
+#define CFG_UART_SIZE	0x10000
+
+#define CFG_NS16550_COM1        (CFG_UART_BASE + 0x8000)
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ *
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define	CONFIG_ETHER_INDEX    2		/* which SCC/FCC channel for ethernet */
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
+ * The main FLASH is whichever is connected to *CS0.
+ */
+#define CFG_FLASH0_BASE 0xFFF00000
+#define CFG_FLASH0_SIZE 8
+
+/* Flash bank size (for preliminary settings)
+ */
+#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+/* Environment in flash */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x60000)
+#define CFG_ENV_SIZE		0x20000
+#define CFG_ENV_SECT_SIZE	0x20000
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_NAND0_BASE 0xE1000000
+
+#define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
+#define SECTORSIZE 512
+#define NAND_NO_RB
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN     0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define NAND_DISABLE_CE(nand) do \
+{ \
+	*(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \
+} while(0)
+
+#define NAND_ENABLE_CE(nand) do \
+{ \
+	*(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \
+} while(0)
+
+#define NAND_CTL_CLRALE(nandptr) do \
+{ \
+	*(((volatile __u8 *)nandptr) + 0x8) = 0; \
+} while(0)
+
+#define NAND_CTL_SETALE(nandptr) do \
+{ \
+	*(((volatile __u8 *)nandptr) + 0x9) = 0; \
+} while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) do \
+{ \
+	*(((volatile __u8 *)nandptr) + 0x8) = 0; \
+} while(0)
+
+#define NAND_CTL_SETCLE(nandptr) do \
+{ \
+	*(((volatile __u8 *)nandptr) + 0xa) = 0; \
+} while(0)
+
+#ifdef NAND_NO_RB
+/* constant delay (see also tR in the datasheet) */
+#define NAND_WAIT_READY(nand) do { \
+	udelay(12); \
+} while (0)
+#else
+/* use the R/B pin */
+#endif
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0)))
+
+#endif /* CFG_CMD_NAND */
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#define CFG_HRCW_MASTER	(HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
+
+/* no slaves so just fill with zeros */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2000  /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CFG_SDRAM_BASE
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		CFG_FLASH0_BASE
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+
+#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
+#define CFG_HID0_FINAL  0
+#define CFG_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR         0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR		0
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR        (0x00000028 | SCCR_DFBRG01)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    16 bit  FLASH
+ *  1   60x     GPCM     8 bit  NAND
+ *  2   60x     SDRAM   32 bit  SDRAM
+ *  3   60x     GPCM     8 bit  UART
+ *
+ */
+
+#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+
+/* Minimum mask to separate preliminary
+ * address ranges for CS[0:2]
+ */
+#define CFG_GLOBAL_SDRAM_LIMIT	(32<<20)	/* less than 32 MB */
+
+#define CFG_MPTPR       0x6600
+
+/*-----------------------------------------------------------------------------
+ * Address for Mode Register Set (MRS) command
+ *-----------------------------------------------------------------------------
+ */
+#define CFG_MRS_OFFS	0x00000110
+
+
+/* Bank 0 - FLASH
+ */
+#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
+			 ORxG_SCY_6_CLK                 )
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+/* Bank 1 - NAND Flash
+*/
+#define	CFG_NAND_BASE		CFG_NAND0_BASE
+#define	CFG_NAND_SIZE		0x8000
+
+#define CFG_OR_TIMING_NAND	0x000036
+
+#define CFG_BR1_PRELIM  ((CFG_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
+#define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_NAND_SIZE) | CFG_OR_TIMING_NAND )
+#endif
+
+/* Bank 2 - 60x bus SDRAM
+ */
+#define CFG_PSRT        0x20
+#define CFG_LSRT        0x20
+
+#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_32                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CFG_OR2_PRELIM	CFG_OR2
+
+
+/* SDRAM initialization values
+*/
+#define CFG_OR2    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A10             |\
+			 ORxS_NUMR_12)
+
+#define CFG_PSDMR  (PSDMR_SDAM_A13_IS_A5 |\
+			 PSDMR_BSMA_A15_A17           |\
+			 PSDMR_SDA10_PBI0_A11         |\
+			 PSDMR_RFRC_5_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_2C              |\
+			 PSDMR_WRC_3C                   |\
+			 PSDMR_CL_3)
+
+/* Bank 3 - UART
+*/
+
+#define CFG_BR3_PRELIM  ((CFG_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
+#define CFG_OR3_PRELIM  (((-CFG_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/IP860.h b/include/configs/IP860.h
new file mode 100755
index 0000000..0e20e56
--- /dev/null
+++ b/include/configs/IP860.h
@@ -0,0 +1,462 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
+#define CONFIG_IP860		1	/* ...on a IP860 board		*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \
+"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+
+# define CFG_I2C_SPEED		50000
+# define CFG_I2C_SLAVE		0xFE
+# define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM X24C16		*/
+# define CFG_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec */
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+/*----------------------------------------------------------------------*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+
+#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF1000000	/* Non-standard value!!	*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x10000000
+#ifdef	DEBUG
+#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#else
+#if 0 /* need more space for I2C tests */
+#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(256 << 10)
+#endif
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	124	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#undef	CFG_ENV_IS_IN_FLASH
+#undef	CFG_ENV_IS_IN_NVRAM
+#undef  CFG_ENV_IS_IN_NVRAM
+#undef	DEBUG_I2C
+#define	CFG_ENV_IS_IN_EEPROM
+
+#ifdef	CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_ADDR		0x20000000	/* use SRAM	*/
+#define CFG_ENV_SIZE		(16<<10)	/* use 16 kB	*/
+#endif	/* CFG_ENV_IS_IN_NVRAM */
+
+#ifdef	CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_OFFSET		 512	/* Leave 512 bytes free for other data	*/
+#define CFG_ENV_SIZE		1536	/* Use remaining space			*/
+#endif	/* CFG_ENV_IS_IN_EEPROM */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ * +0x0004
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * +0x0000 => 0x80600800
+ */
+#define CFG_SIUMCR	(SIUMCR_EARB   | SIUMCR_EARP0 | \
+			 SIUMCR_DBGC11 | SIUMCR_MLRC10)
+
+/*-----------------------------------------------------------------------
+ * Clock Setting - get clock frequency from Board Revision Register
+ *-----------------------------------------------------------------------
+ */
+#ifndef __ASSEMBLY__
+extern  unsigned long           ip860_get_clk_freq (void);
+#endif
+#define	CONFIG_8xx_GCLK_FREQ	ip860_get_clk_freq()
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ * +0x0200 => 0x00C2
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ * +0x0240 => 0x0082
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* +0x0286 => was: 0x0000D000 */
+#define CFG_PLPRCR							\
+		(	PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
+			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
+			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
+		)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
+			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
+			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
+			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
+			 SCCR_DFNH000)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/* +0x0220 => 0x00C3 */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register		19-4
+ *-----------------------------------------------------------------------
+ */
+/* +0x09C4 => TIMEP=1 */
+#define CFG_RCCR 0x0100
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMDS 0
+
+/*-----------------------------------------------------------------------
+ * DER - Debug Event Register
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ */
+
+/*
+ * MAMR settings for SDRAM	- 16-14
+ * => 0xC3804114
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	0xC3
+
+#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/*
+ * BR1 and OR1 (FLASH)
+ */
+#define FLASH_BASE		0x10000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+/* allow for max 8 MB of Flash */
+#define CFG_REMAP_OR_AM		0xFF800000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+/* 16 bit, bank valid */
+#define CFG_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
+
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	CFG_BR0_PRELIM
+
+/*
+ * BR2/OR2 - SDRAM
+ */
+#define SDRAM_BASE		0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+#define SDRAM_TIMING		0x00000A00	/* SDRAM-Timing */
+
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
+
+#define CFG_OR2		(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CFG_BR2		((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR3/OR3 - SRAM (16 bit)
+ */
+#define	SRAM_BASE	0x20000000
+#define CFG_OR3		0xFFF00130		/* BI/SCY = 5/TRLX (internal) */
+#define CFG_BR3		((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define SRAM_SIZE	(1 + (~(CFG_OR3 & BR_BA_MSK)))
+#define CFG_OR3_PRELIM	CFG_OR3			/* Make sure to map early */
+#define CFG_BR3_PRELIM	CFG_BR3			/* in case it's used for ENV */
+
+/*
+ * BR4/OR4 - Board Control & Status (8 bit)
+ */
+#define	BCSR_BASE	0xFC000000
+#define CFG_OR4		0xFFFF0120		/* BI (internal) */
+#define CFG_BR4		((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+
+/*
+ * BR5/OR5 - IP Slot A/B (16 bit)
+ */
+#define	IP_SLOT_BASE	0x40000000
+#define CFG_OR5		0xFE00010C		/* SETA/TRLX/BI/ SCY=0 (external) */
+#define CFG_BR5		((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+
+/*
+ * BR6/OR6 - VME STD  (16 bit)
+ */
+#define	VME_STD_BASE	0xFE000000
+#define CFG_OR6		0xFF00010C		/* SETA/TRLX/BI/SCY=0  (external) */
+#define CFG_BR6		((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+
+/*
+ * BR7/OR7 - SHORT I/O + RTC + IACK  (16 bit)
+ */
+#define VME_SHORT_BASE	0xFF000000
+#define CFG_OR7		0xFF00010C		/* SETA/TRLX/BI/ SCY=0 (external) */
+#define CFG_BR7		((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+
+/*-----------------------------------------------------------------------
+ * Board Control and Status Region:
+ *-----------------------------------------------------------------------
+ */
+#ifndef __ASSEMBLY__
+typedef	struct ip860_bcsr_s {
+	unsigned char	shmem_addr;	/* +00 shared memory address register	*/
+	unsigned char	reserved0;
+	unsigned char	mbox_addr;	/* +02 mailbox address register		*/
+	unsigned char	reserved1;
+	unsigned char	vme_int_mask;	/* +04 VME Bus interrupt mask register	*/
+	unsigned char	reserved2;
+	unsigned char	vme_int_pend;	/* +06 VME interrupt pending register	*/
+	unsigned char	reserved3;
+	unsigned char	bd_int_mask;	/* +08 board interrupt mask register	*/
+	unsigned char	reserved4;
+	unsigned char	bd_int_pend;	/* +0A board interrupt pending register	*/
+	unsigned char	reserved5;
+	unsigned char	bd_ctrl;	/* +0C board control register		*/
+	unsigned char	reserved6;
+	unsigned char	bd_status;	/* +0E board status  register		*/
+	unsigned char	reserved7;
+	unsigned char	vme_irq;	/* +10 VME interrupt request register	*/
+	unsigned char	reserved8;
+	unsigned char	vme_ivec;	/* +12 VME interrupt vector register	*/
+	unsigned char	reserved9;
+	unsigned char	cli_mbox;	/* +14 clear mailbox irq		*/
+	unsigned char	reservedA;
+	unsigned char	rtc;		/* +16 RTC control register		*/
+	unsigned char	reservedB;
+	unsigned char	mbox_data;	/* +18 mailbox read/write register	*/
+	unsigned char	reservedC;
+	unsigned char	wd_trigger;	/* +1A Watchdog trigger register	*/
+	unsigned char	reservedD;
+	unsigned char	rmw_req;	/* +1C RMW request register		*/
+	unsigned char	reservedE;
+	unsigned char	bd_rev;		/* +1E Board Revision register		*/
+} ip860_bcsr_t;
+#endif	/* __ASSEMBLY__ */
+
+/*-----------------------------------------------------------------------
+ * Board Control Register: bd_ctrl (Offset 0x0C)
+ *-----------------------------------------------------------------------
+ */
+#define BD_CTRL_IPLSE	0x80	/* IP Slot Long Select Enable		*/
+#define BD_CTRL_WDOGE	0x40	/* Watchdog Enable			*/
+#define BD_CTRL_FLWE	0x20	/* Flash Write Enable			*/
+#define BD_CTRL_RWDN	0x10	/* VMEBus Requester Release When Done Enable */
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h
new file mode 100755
index 0000000..c1565fc
--- /dev/null
+++ b/include/configs/IPHASE4539.h
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
+ *
+ * This file is based on similar values for other boards found in
+ * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG				/* General debug */
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
+#define CONFIG_IPHASE4539	1	/* ...on a Interphase 4539 PMC */
+
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/*-----------------------------------------------------------------------
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define	CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else */
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+
+/*-----------------------------------------------------------------------
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC   */
+#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX	3	/* which channel for ether  */
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
+
+/*-----------------------------------------------------------------------
+ * - Rx-CLK is CLK14
+ * - Tx-CLK is CLK16
+ * - Select bus for bd/buffers (see 28-13)
+ * - Half duplex
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#endif	/* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+/* other options */
+
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+#define CONFIG_BAUDRATE		19200
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+/*
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#ifdef CONFIG_SOFT_I2C
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+#define CONFIG_COMMANDS		CONFIG_CMD_DFL
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND	"bootm 100000"	/* autoboot command */
+#define CONFIG_BOOTARGS		"root=/dev/ram rw"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passed to Linux in MHz */
+					/* for versions < 2.4.5-pre5	 */
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_RESET_ADDRESS	0x04400000
+
+#define CONFIG_MISC_INIT_R	1	/* We need misc_init_r()	*/
+
+/*-----------------------------------------------------------------------
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration (Setup by the
+ * startup code). Please note that CFG_SDRAM_BASE _must_ start at 0.
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFF800000
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 << 10)     /* Reserve 256 kB for Monitor  */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CFG_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+#define CFG_MAX_FLASH_SIZE	(CFG_MAX_FLASH_SECT * 0x10000)	/* 4 MB */
+
+#define CFG_FLASH_ERASE_TOUT	2400000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+/* Environment in FLASH, there is little space left in Serial EEPROM */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	0x10000 /* We use one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x10000) /* 2. sector */
+
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#define CFG_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM )		|\
+			  ( HRCW_L2CPC10 | HRCW_ISB110 )	|\
+			  ( HRCW_MMR11 | HRCW_APPC10 )		|\
+			  ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )	 \
+			) /* 0x14863245 */
+
+/* no slaves */
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000 /* We keep original value */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	  /* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02	  /* Software reboot			*/
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32     /* For MPC8260 CPU		*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5      /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers		2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+ 			 HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL	(HID0_IFEM|HID0_ABE)
+#define CFG_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register					 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR		RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR		0xA01C0000
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR	0X4205C000
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				 4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined (CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ *-----------------------------------------------------------------------
+ */
+#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR	0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR	0
+
+/*-----------------------------------------------------------------------
+ * Init Memory Controller:
+ *
+ * Bank Bus	Machine PortSz	Device
+ * ---- ---	------- ------	------
+ *  0	60x	GPCM	64 bit	FLASH
+ *  1	60x	SDRAM	64 bit	SDRAM
+ */
+
+#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK) | 0x0801)
+#define CFG_OR0_PRELIM	0xFF800882
+#define CFG_BR1_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
+#define CFG_OR1_PRELIM	0xF8002CD0
+
+#define CFG_PSDMR	0x404A241A
+#define CFG_MPTPR	0x00007400
+#define CFG_PSRT	0x00000007
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h
new file mode 100755
index 0000000..65056a2
--- /dev/null
+++ b/include/configs/ISPAN.h
@@ -0,0 +1,347 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Interphase iSPAN Communications Controllers
+ * (453x and others). Tested on 4532.
+ *
+ * Derived from iSPAN 4539 port (iphase4539) by
+ * Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC8260			/* This is an MPC8260 CPU               */
+#define CONFIG_ISPAN			/* ...on one of Interphase iSPAN boards */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/*-----------------------------------------------------------------------
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * If CONFIG_CONS_NONE is defined, then the serial console routines must be
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Define if console on SMC		*/
+#undef	CONFIG_CONS_ON_SCC		/* Define if console on SCC		*/
+#undef	CONFIG_CONS_NONE		/* Define if console on something else	*/
+#define CONFIG_CONS_INDEX	1	/* Which serial channel for console	*/
+
+/*-----------------------------------------------------------------------
+ * Select Ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC).
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
+ * be defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* Define if Ethernet on SCC		*/
+#define CONFIG_ETHER_ON_FCC		/* Define if Ethernet on FCC		*/
+#undef	CONFIG_ETHER_NONE		/* Define if Ethernet on something else */
+#define CONFIG_ETHER_INDEX	3	/* Which channel for Ethernrt		*/
+
+#ifdef CONFIG_ETHER_ON_FCC
+
+#if CONFIG_ETHER_INDEX == 3
+
+#define CFG_PHY_ADDR		0
+#define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
+#define CFG_CMXFCR_MASK		(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+
+#endif /* CONFIG_ETHER_INDEX == 3 */
+
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#define CONFIG_MII				/* MII PHY management		*/
+#define CONFIG_BITBANGMII			/* Bit-bang MII PHY management	*/
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT		3		/* Port D */
+
+#define CFG_MDIO_PIN		0x00040000	/* PD13 */
+#define CFG_MDC_PIN		0x00080000	/* PD12 */
+
+#define MDIO_ACTIVE		(iop->pdir |=  CFG_MDIO_PIN)
+#define MDIO_TRISTATE		(iop->pdir &= ~CFG_MDIO_PIN)
+#define MDIO_READ		((iop->pdat &  CFG_MDIO_PIN) != 0)
+
+#define MDIO(bit)		if(bit) iop->pdat |=  CFG_MDIO_PIN; \
+				else	iop->pdat &= ~CFG_MDIO_PIN
+
+#define MDC(bit)		if(bit) iop->pdat |=  CFG_MDC_PIN; \
+				else	iop->pdat &= ~CFG_MDC_PIN
+
+#define MIIDELAY		udelay(1)
+
+#endif /* CONFIG_ETHER_ON_FCC */
+
+#define CONFIG_8260_CLKIN	65536000	/* in Hz */
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL  \
+				| CFG_CMD_ASKENV  \
+				| CFG_CMD_DHCP    \
+				| CFG_CMD_ECHO    \
+				| CFG_CMD_IMMAP   \
+				| CFG_CMD_MII     \
+				| CFG_CMD_PING    \
+				| CFG_CMD_REGINFO \
+				)
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds	*/
+#define CONFIG_BOOTCOMMAND	"bootm fe010000"	/* autoboot command	*/
+#define CONFIG_BOOTARGS		"root=/dev/ram rw"
+
+#define CONFIG_BZIP2		/* Include support for bzip2 compressed images  */
+#undef	CONFIG_WATCHDOG		/* Disable platform specific watchdog		*/
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_LONGHELP				/* #undef to save memory	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)  /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* Max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x03B00000	/* 1 ... 59 MB in SDRAM		*/
+
+#define CFG_LOAD_ADDR		0x100000	/* Default load address		*/
+
+#define CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_RESET_ADDRESS	0x09900000
+
+#define CONFIG_MISC_INIT_R			/* We need misc_init_r()	*/
+
+/*-----------------------------------------------------------------------
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor   */
+#ifdef CONFIG_BZIP2
+#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()    */
+#else
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
+#endif /* CONFIG_BZIP2 */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
+#define CFG_MAX_FLASH_BANKS	1		/* Max num of memory banks	*/
+#define CFG_MAX_FLASH_SECT	142		/* Max num of sects on one chip */
+
+/* Environment is in flash, there is little space left in Serial EEPROM */
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000 	/* We use one complete sector	*/
+#define CFG_ENV_SIZE		(CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * If you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+/* 0x1686B245 */
+#define CFG_HRCW_MASTER (HRCW_EBM      | HRCW_BPS01       | HRCW_CIP    |\
+			 HRCW_L2CPC10  | HRCW_ISB110                    |\
+			 HRCW_BMS      | HRCW_MMR11       | HRCW_APPC10 |\
+			 HRCW_CS10PC01 | HRCW_MODCK_H0101                \
+			)
+/* No slaves */
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0F00000
+#ifdef CFG_REV_B
+#define CFG_DEFAULT_IMMR	0xFF000000
+#endif /* CFG_REV_B */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128  /* Size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from flash	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU			*/
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers		2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT		(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL		(HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CFG_HID2		0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register					 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR			RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR			0xA01C0000
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR		0x42250000/* 0x4205C000 */
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				 4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined (CONFIG_WATCHDOG)
+#define CFG_SYPCR		(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+				SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR		(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+				SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ *-----------------------------------------------------------------------
+ */
+#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR		SCCR_DFBRG01
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR		0
+
+/*-----------------------------------------------------------------------
+ * Init Memory Controller:
+ *
+ * Bank Bus	Machine PortSize                        Device
+ * ---- ---	------- -----------------------------   ------
+ *  0	60x	GPCM	 8 bit (Rev.B)/16 bit (Rev.D)   Flash
+ *  1	60x	SDRAM	64 bit                          SDRAM
+ *  2	Local	SDRAM	32 bit	                        SDRAM
+ */
+#define CFG_USE_FIRMWARE	/* If defined - do not initialise memory
+				   controller, rely on initialisation
+				   performed by the Interphase boot firmware.
+				 */
+
+#define CFG_OR0_PRELIM		0xFE000882
+#ifdef CFG_REV_B
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BRx_PS_8  | BRx_V)
+#else  /* Rev. D */
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BRx_PS_16 | BRx_V)
+#endif /* CFG_REV_B */
+
+#define CFG_MPTPR		0x7F00
+
+/* Please note that 60x SDRAM MUST start at 0 */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_60x_BR		0x00000041
+#define CFG_60x_OR		0xF0002CD0
+#define CFG_PSDMR		0x0049929A
+#define CFG_PSRT		0x07
+
+#define CFG_LSDRAM_BASE		0xF7000000
+#define CFG_LOC_BR		0x00001861
+#define CFG_LOC_OR		0xFF803280
+#define CFG_LSDMR		0x8285A552
+#define CFG_LSRT		0x07
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h
new file mode 100755
index 0000000..a0cb1dd
--- /dev/null
+++ b/include/configs/IVML24.h
@@ -0,0 +1,474 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
+#define CONFIG_IVML24		1	/* ...on a IVML24 board		*/
+
+#if defined (CONFIG_IVML24_16M)
+# define CONFIG_IDENT_STRING     " IVML24"
+#elif defined (CONFIG_IVML24_32M)
+# define CONFIG_IDENT_STRING     " IVML24_128"
+#elif defined (CONFIG_IVML24_64M)
+# define CONFIG_IDENT_STRING     " IVML24_256"
+#endif
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_8xx_GCLK_FREQ    50331648
+
+#define	CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs	*/
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
+
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
+				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
+				"nfsaddrs=10.0.0.99:10.0.0.2"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_IDE)
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_BOOTP_MASK \
+    ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+
+#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+#define CFG_PB_12V_ENABLE	0x00002000		/* PB 18	*/
+#define CFG_PB_ILOCK_SWITCH	0x00004000		/* PB 17	*/
+#define CFG_PB_SDRAM_CLKE	0x00008000		/* PB 16	*/
+#define CFG_PB_ETH_POWERDOWN	0x00010000		/* PB 15	*/
+#define CFG_PB_IDE_MOTOR	0x00020000		/* PB 14	*/
+
+#define CFG_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
+#define CFG_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000 /* was: 0xFF000000 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+
+#if defined (CONFIG_IVML24_16M)
+# define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#elif defined (CONFIG_IVML24_32M)
+# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#elif defined (CONFIG_IVML24_64M)
+# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#endif
+
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFF000000
+#ifdef	DEBUG
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x7A000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+
+# if defined (CONFIG_IVML24_16M)
+#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+# elif defined (CONFIG_IVML24_32M)
+#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWP)
+# elif defined (CONFIG_IVML24_64M)
+#  define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWP)
+# endif
+
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+/* EARB, DBGC and DBPC are initialised by the HCW */
+/* => 0x000000C0 */
+#define CFG_SIUMCR	(SIUMCR_BSC | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* 0x00B0C0C0 */
+#define CFG_PLPRCR							\
+		(	(11 << PLPRCR_MF_SHIFT) |			\
+			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/	\
+			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
+			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
+		)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* 0x01800014 */
+#define CFG_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
+			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\
+			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
+			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
+			 SCCR_DFNH000	|   SCCR_DFLCD101 |	\
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/* 0x00C3 */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register		19-4
+ *-----------------------------------------------------------------------
+ */
+/* TIMEP=2 */
+#define CFG_RCCR 0x0200
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMDS 0
+
+/*-----------------------------------------------------------------------
+ *
+ * Interrupt Levels
+ *-----------------------------------------------------------------------
+ */
+#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* The IVML24 has only 1 IDE bus*/
+#define CFG_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/
+
+#define CFG_ATA_BASE_ADDR	0xFE100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#undef	CFG_ATA_IDE1_OFFSET		/* only one IDE bus available	*/
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CFG_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+/* EPROMs are 512kb */
+#define CFG_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	(OR_SCY_5_CLK | OR_EHTR)
+
+#define CFG_OR0_REMAP	( CFG_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \
+				CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \
+				CFG_OR_TIMING_FLASH)
+/* 16 bit, bank valid */
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/*
+ * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
+ *
+ * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
+ */
+#define ELIC_SACCO_BASE		0xFE000000
+#define ELIC_SACCO_OR_AM	0xFFFF8000
+#define ELIC_SACCO_TIMING	(OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
+
+#define CFG_OR1	(ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
+			ELIC_SACCO_TIMING)
+#define CFG_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
+ *
+ * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
+ */
+#define ELIC_EPIC_BASE		0xFE008000
+#define ELIC_EPIC_OR_AM		0xFFFF8000
+#define ELIC_EPIC_TIMING	(OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
+
+#define CFG_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
+			ELIC_EPIC_TIMING)
+#define CFG_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR3/OR3: SDRAM
+ *
+ * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+#define SDRAM_TIMING		OR_SCY_0_CLK	/* SDRAM-Timing */
+
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
+
+#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
+
+/*
+ * BR4/OR4 - HDLC Address
+ *
+ *  AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0
+ */
+#define HDLC_ADDR_BASE		0xFE108000	/* HDLC Address area */
+#define HDLC_ADDR_OR_AM		0xFFFF8000
+#define HDLC_ADDR_TIMING	OR_SCY_1_CLK
+
+#define CFG_OR4	(HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING)
+#define CFG_BR4	((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V )
+
+/*
+ * BR5/OR5: SHARC ADSP-2165L
+ *
+ * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
+ */
+#define SHARC_BASE		0xFE400000
+#define SHARC_OR_AM		0xFFC00000
+#define SHARC_TIMING		OR_SCY_0_CLK
+
+#define CFG_OR5	(SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING )
+#define CFG_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MBMR_PTB	204
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+
+#if defined (CONFIG_IVML24_16M)
+# define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#elif defined (CONFIG_IVML24_32M)
+# define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#elif defined (CONFIG_IVML24_64M)
+# define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/
+#endif
+
+
+/*
+ * MBMR settings for SDRAM
+ */
+
+#if defined (CONFIG_IVML24_16M)
+ /* 8 column SDRAM */
+# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+ 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
+ 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+#elif defined (CONFIG_IVML24_32M)
+/* 128 MBit SDRAM */
+# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+#elif defined (CONFIG_IVML24_64M)
+/* 128 MBit SDRAM */
+# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h
new file mode 100755
index 0000000..46b4d53
--- /dev/null
+++ b/include/configs/IVMS8.h
@@ -0,0 +1,458 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
+#define CONFIG_IVMS8		1	/* ...on a IVMS8 board		*/
+
+#if defined (CONFIG_IVMS8_16M)
+# define CONFIG_IDENT_STRING     " IVMS8"
+#elif defined (CONFIG_IVMS8_32M)
+# define CONFIG_IDENT_STRING     " IVMS8_128"
+#elif defined (CONFIG_IVMS8_64M)
+# define CONFIG_IDENT_STRING     " IVMS8_256"
+#endif
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_8xx_GCLK_FREQ    50331648
+
+#define	CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs	*/
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
+
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
+				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
+				"nfsaddrs=10.0.0.99:10.0.0.2"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_IDE)
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_BOOTP_MASK \
+    ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+
+#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+#define CFG_PB_SDRAM_CLKE	0x00008000		/* PB 16	*/
+#define CFG_PB_ETH_POWERDOWN	0x00010000		/* PB 15	*/
+#define CFG_PB_IDE_MOTOR	0x00020000		/* PB 14	*/
+
+#define CFG_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
+#define CFG_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000 /* was: 0xFF000000 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#if defined (CONFIG_IVMS8_16M)
+# define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#elif defined (CONFIG_IVMS8_32M)
+# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#elif defined (CONFIG_IVMS8_64M)
+# define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#endif
+
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFF000000
+#ifdef	DEBUG
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x7A000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+# if defined (CONFIG_IVMS8_16M)
+#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#  elif defined (CONFIG_IVMS8_32M)
+#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWP)
+#  elif defined (CONFIG_IVMS8_64M)
+#   define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWP)
+#  endif
+#else
+# define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+/* EARB, DBGC and DBPC are initialised by the HCW */
+/* => 0x000000C0 */
+#define CFG_SIUMCR	(SIUMCR_BSC | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* 0x00B0C0C0 */
+#define CFG_PLPRCR							\
+		(	(11 << PLPRCR_MF_SHIFT) |			\
+			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/	\
+			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
+			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
+		)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* 0x01800014 */
+#define CFG_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
+			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\
+			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
+			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
+			 SCCR_DFNH000	|   SCCR_DFLCD101 |	\
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/* 0x00C3 */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register		19-4
+ *-----------------------------------------------------------------------
+ */
+/* TIMEP=2 */
+#define CFG_RCCR 0x0200
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMDS 0
+
+/*-----------------------------------------------------------------------
+ *
+ * Interrupt Levels
+ *-----------------------------------------------------------------------
+ */
+#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* The IVMS8 has only 1 IDE bus	*/
+#define CFG_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/
+
+#define CFG_ATA_BASE_ADDR	0xFE100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#undef	CFG_ATA_IDE1_OFFSET		/* only one IDE bus available	*/
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CFG_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+/* EPROMs are 512kb */
+#define CFG_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	(/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
+				 OR_SCY_5_CLK | OR_EHTR)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+/* 16 bit, bank valid */
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/*
+ * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
+ *
+ * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
+ */
+#define ELIC_SACCO_BASE		0xFE000000
+#define ELIC_SACCO_OR_AM	0xFFFF8000
+#define ELIC_SACCO_TIMING	0x00000F26
+
+#define CFG_OR1	(ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
+#define CFG_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
+ *
+ * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
+ */
+#define ELIC_EPIC_BASE		0xFE008000
+#define ELIC_EPIC_OR_AM		0xFFFF8000
+#define ELIC_EPIC_TIMING	0x00000F26
+
+#define CFG_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
+#define CFG_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR3/OR3: SDRAM
+ *
+ * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+#define SDRAM_TIMING		0x00000A00	/* SDRAM-Timing */
+
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
+
+#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
+
+/*
+ * BR4/OR4: not used
+ */
+
+/*
+ * BR5/OR5: SHARC ADSP-2165L
+ *
+ * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
+ */
+#define SHARC_BASE		0xFE400000
+#define SHARC_OR_AM		0xFFC00000
+#define SHARC_TIMING		0x00000700
+
+#define CFG_OR5	(SHARC_OR_AM | SHARC_TIMING )
+#define CFG_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MBMR_PTB	204
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#if defined (CONFIG_IVMS8_16M)
+ #define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#elif defined (CONFIG_IVMS8_32M)
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#elif defined (CONFIG_IVMS8_64M)
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/
+#endif
+
+
+/*
+ * MBMR settings for SDRAM
+ */
+
+#if defined (CONFIG_IVMS8_16M)
+ /* 8 column SDRAM */
+# define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+ 			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
+ 			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+#elif defined (CONFIG_IVMS8_32M)
+/* 128 MBit SDRAM */
+#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+#elif defined (CONFIG_IVMS8_64M)
+/* 128 MBit SDRAM */
+#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
new file mode 100755
index 0000000..afba5c6
--- /dev/null
+++ b/include/configs/IceCube.h
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_ICECUBE		1	/* ... on IceCube board */
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CFG_XLB_PIPELINING	1
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_MII		1
+#define CONFIG_EEPRO100		1
+#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X		1
+
+#define ADD_PCI_CMD 		CFG_CMD_PCI
+
+#else	/* MPC5100 */
+
+#define CONFIG_MII		1
+#define ADD_PCI_CMD		0  /* no CFG_CMD_PCI */
+
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* USB */
+#if 1
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD             0
+#endif
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	| \
+				ADD_PCI_CMD	| \
+				ADD_USB_CMD	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
+#   define CFG_LOWBOOT	        1
+#   define CFG_LOWBOOT16	1
+#endif
+#if (TEXT_BASE == 0xFF800000)		/* Boot low with  8 MB Flash */
+#   define CFG_LOWBOOT	        1
+#   define CFG_LOWBOOT08	1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/MPC5200/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#endif
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		0xFF000000
+#define CFG_FLASH_SIZE		0x01000000
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00740000 + 0x00800000)
+#else	/* CFG_LOWBOOT */
+#if defined(CFG_LOWBOOT08)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000 + 0x00800000)
+#endif
+#if defined(CFG_LOWBOOT16)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
+#endif
+#endif	/* CFG_LOWBOOT */
+#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks      */
+
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */
+
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x10000
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ */
+#ifdef CONFIG_MPC5200_DDR
+#define CFG_GPS_PORT_CONFIG	0x90000004
+#else
+#define CFG_GPS_PORT_CONFIG	0x10000004
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#ifdef CONFIG_MPC5200_DDR
+
+#define CFG_BOOTCS_START	(CFG_CS1_START + CFG_CS1_SIZE)
+#define CFG_BOOTCS_SIZE		0x00800000
+#define CFG_BOOTCS_CFG		0x00047801
+#define CFG_CS1_START		CFG_FLASH_BASE
+#define CFG_CS1_SIZE		0x00800000
+#define CFG_CS1_CFG		0x00047800
+
+#else /* !CONFIG_MPC5200_DDR */
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x00047801
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#endif /* CONFIG_MPC5200_DDR */
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers                                                */
+#define CFG_ATA_STRIDE          4
+
+#define CONFIG_ATAPI            1
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/JSE.h b/include/configs/JSE.h
new file mode 100755
index 0000000..ccd1f19
--- /dev/null
+++ b/include/configs/JSE.h
@@ -0,0 +1,304 @@
+/*
+ * (C) Copyright 2003 Picture Elements, Inc.
+ * Stephen Williams <steve@icarus.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options for the JSE board
+ * (Theoretically easy to change, but the board is fixed.)
+ */
+
+#define CONFIG_JSE 1
+  /* JSE has a PPC405GPr */
+#define CONFIG_405GP 1
+  /* ... which is a 4xxx series */
+#define CONFIG_4xx   1
+  /* ... with a 33MHz OSC. connected to the SysCLK input */
+#define CONFIG_SYS_CLK_FREQ	33333333
+  /* ... with on-chip memory here (4KBytes) */
+#define CFG_OCM_DATA_ADDR 0xF4000000
+#define CFG_OCM_DATA_SIZE 0x00001000
+  /* Do not set up locked dcache as init ram. */
+#undef CFG_INIT_DCACHE_CS
+
+  /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
+#define CONFIG_SYSTEMACE 1
+#define CFG_SYSTEMACE_BASE 0xf0000000
+#define CONFIG_DOS_PARTITION 1
+
+  /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
+#define CFG_TEMP_STACK_OCM 1
+  /* ... place INIT RAM in the OCM address */
+# define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR
+  /* ... give it the whole init ram */
+# define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE
+  /* ... Shave a bit off the end for global data */
+# define CFG_GBL_DATA_SIZE	128
+# define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+  /* ... and place the stack pointer at the top of what's left. */
+# define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+  /* Enable board_pre_init function */
+#define CONFIG_BOARD_PRE_INIT	1
+#define CONFIG_BOARD_EARLY_INIT_F 1
+  /* Disable post-clk setup init function */
+#undef CONFIG_BOARD_POSTCLK_INIT
+  /* Disable call to post_init_f: late init function. */
+#undef CONFIG_POST
+  /* Enable DRAM test. */
+#define CFG_DRAM_TEST 1
+  /* Enable misc_init_r function. */
+#define CONFIG_MISC_INIT_R 1
+
+  /* JSE has EEPROM chips that are good for environment. */
+#undef	CFG_ENV_IS_IN_NVRAM
+#undef	CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_IS_IN_EEPROM 1
+#undef	CFG_ENV_IS_NOWHERE
+
+  /* This is the 7bit address of the device, not including P. */
+#define CFG_I2C_EEPROM_ADDR 0x50
+  /* After the device address, need one more address byte. */
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+  /* The EEPROM is 512 bytes. */
+#define CFG_EEPROM_SIZE 512
+  /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
+#define CFG_EEPROM_PAGE_WRITE_BITS 4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+  /* Put the environment in the second half. */
+#define CFG_ENV_OFFSET	0x00
+#define CFG_ENV_SIZE	512
+
+
+  /* The JSE connects UART1 to the console tap connector. */
+#define CONFIG_UART1_CONSOLE	1
+  /* Set console baudrate to 9600 */
+#define CONFIG_BAUDRATE		9600
+
+/* Size (bytes) of interrupt driven serial port buffer.
+ * Set to 0 to use polling instead of interrupts.
+ * Setting to 0 will also disable RTS/CTS handshaking.
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/*
+ * Configuration related to auto-boot.
+ *
+ * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait
+ * before resorting to autoboot. This value can be overridden by the
+ * bootdelay environment variable.
+ *
+ * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the
+ * user that an autoboot will happen.
+ *
+ * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will
+ * execute to boot the JSE. This loads the uimage and initrd.img files
+ * from CompactFlash into memory, then boots them from memory.
+ *
+ * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get
+ * it going on the JSE.
+ */
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOTARGS		"root=/dev/ram0 init=/linuxrc rw"
+#define CONFIG_BOOTCOMMAND	"fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000"
+
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_FLASH	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+  /* watchdog disabled */
+#undef CONFIG_WATCHDOG
+  /* SPD EEPROM (sdram speed config) disabled */
+#undef CONFIG_SPD_EEPROM
+#undef SPD_EEPROM_ADDRESS
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#define CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef	CFG_EXT_SERIAL_CLOCK	       /* external serial clock */
+#undef	CFG_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * External peripheral base address
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
+
+#define CFG_KEY_REG_BASE_ADDR	0xF0100000
+#define CFG_IR_REG_BASE_ADDR	0xF0200000
+#define CFG_FPGA_REG_BASE_ADDR	0xF0300000
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFF80000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405GPr CPUs	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
+
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR	0xF0000500
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h
new file mode 100755
index 0000000..7bbceb0
--- /dev/null
+++ b/include/configs/KAREF.h
@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2004 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
+ *		    design.
+ ***********************************************************************/
+
+/*
+ * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_KAREF	     1		/* Board is Kamino Ref Variant */
+#define CONFIG_440GX		  1	     /* Specifc GX support	*/
+#define CONFIG_4xx		  1	     /* ... PPC4xx family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
+#define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
+#define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/
+#undef	CFG_DRAM_TEST			     /* Disable-takes long time!*/
+#define CONFIG_SYS_CLK_FREQ	  66666666   /* external freq to pll	*/
+
+#define CONFIG_VERY_BIG_RAM 1
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
+#define CFG_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
+#define CFG_MONITOR_BASE       0xfff80000    /* start of monitor	*/
+#define CFG_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
+#define CFG_PERIPHERAL_BASE    0xe0000000    /* internal peripherals	*/
+#define CFG_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
+#define CFG_PCI_BASE	       0xd0000000    /* internal PCI regs	*/
+
+#define CFG_NVRAM_BASE_ADDR   (CFG_PERIPHERAL_BASE + 0x08000000)
+#define CFG_KAREF_FPGA_BASE   (CFG_PERIPHERAL_BASE + 0x08200000)
+#define CFG_OFEM_FPGA_BASE    (CFG_PERIPHERAL_BASE + 0x08400000)
+#define CFG_BME32_BASE	      (CFG_PERIPHERAL_BASE + 0x08500000)
+#define CFG_GPIO_BASE	      (CFG_PERIPHERAL_BASE + 0x00000700)
+
+/* Here for completeness */
+#define CFG_OFEMAC_BASE	      (CFG_PERIPHERAL_BASE + 0x08600000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM    1
+#define CFG_OCM_DATA_ADDR     CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR     CFG_ISRAM_BASE /* Initial RAM address	*/
+#define CFG_INIT_RAM_END      0x2000	     /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE     128	     /* num bytes initial data	*/
+
+#define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR    (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET    CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
+#define CFG_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SERIAL_MULTI   1
+#define CONFIG_BAUDRATE	      9600
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
+#define CONFIG_RTC_DS174x     1		     /* DS1743 RTC		*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS   1		     /* number of banks		*/
+#define CFG_MAX_FLASH_SECT    8		     /* sectors per device	*/
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
+#define CFG_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM     1		     /* Use SPD EEPROM for setup*/
+#define SPD_EEPROM_ADDRESS    {0x53}	     /* SPD i2c spd addresses	*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C	      1		     /* I2C hardware support	*/
+#undef	CONFIG_SOFT_I2C			     /* I2C !bit-banged		*/
+#define CFG_I2C_SPEED	      400000	     /* I2C speed 400kHz	*/
+#define CFG_I2C_SLAVE	      0x7F	     /* I2C slave address	*/
+#define CFG_I2C_NOPROBES      {0x69}	     /* Don't probe these addrs */
+#define CONFIG_I2C_BUS1	      1		     /* Include i2c bus 1 supp	*/
+
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_NVRAM   1		     /* Environment uses NVRAM	*/
+#undef	CFG_ENV_IS_IN_FLASH		     /* ... not in flash	*/
+#undef	CFG_ENV_IS_IN_EEPROM		     /* ... not in EEPROM	*/
+#define CONFIG_ENV_OVERWRITE  1		     /* allow env overwrite	*/
+
+#define CFG_ENV_SIZE	      0x1000	     /* Size of Env vars	*/
+#define CFG_ENV_ADDR	      (CFG_NVRAM_BASE_ADDR)
+
+#define CONFIG_BOOTDELAY      5		    /* 5 second autoboot */
+
+#define CONFIG_LOADS_ECHO     1		     /* echo on for serial dnld */
+#define CFG_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/
+
+/*-----------------------------------------------------------------------
+ * Networking
+ *----------------------------------------------------------------------*/
+#define CONFIG_MII	      1		     /* MII PHY management	*/
+#define CONFIG_NET_MULTI      1
+#define CONFIG_PHY_ADDR	      0xff	     /* no phy on EMAC0		*/
+#define CONFIG_PHY1_ADDR      0xff	     /* no phy on EMAC1		*/
+#define CONFIG_PHY2_ADDR      0x08	     /* PHY addr, MGMT, EMAC2	*/
+#define CONFIG_PHY3_ADDR      0x18	     /* PHY addr, LCL, EMAC3	*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_PHY_RESET      1              /* reset phy upon startup  */
+#define CONFIG_CIS8201_PHY    1		     /* RGMII mode for Cicada	*/
+#define CONFIG_CIS8201_SHORT_ETCH 1	     /* Use short etch mode	*/
+#define CONFIG_PHY_GIGE	      1		     /* GbE speed/duplex detect */
+#define CONFIG_PHY_RESET_DELAY 1000
+#define CONFIG_NETMASK	      255.255.0.0
+#define CONFIG_ETHADDR	      00:00:00:00:00:00 /* No EMAC 0 support	*/
+#define CONFIG_ETH1ADDR	      00:00:00:00:00:00 /* No EMAC 1 support	*/
+#define CFG_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/
+
+
+/*-----------------------------------------------------------------------
+ * Console/Commands/Parser
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT)
+
+/* Include NetConsole support */
+#define CONFIG_NETCONSOLE
+
+/* Include auto complete with tabs */
+#define CONFIG_AUTO_COMPLETE 1
+#define CFG_AUTO_COMPLETE    1
+#define CFG_ALT_MEMTEST	     1	     /* use real memory test	 */
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_LONGHELP			     /* undef to save memory	*/
+#define CFG_PROMPT	      "KaRefDes=> "  /* Monitor Command Prompt	*/
+
+#define CFG_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
+#define CFG_PROMPT_HUSH_PS2    "> "
+
+
+/*-----------------------------------------------------------------------
+ * Console Buffer
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	      1024	     /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE	      256	     /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+					     /* Print Buffer Size	*/
+#define CFG_MAXARGS	      16	     /* max number of cmd args	*/
+#define CFG_BARGSIZE	      CFG_CBSIZE     /* Boot Arg Buffer Size	*/
+
+/*-----------------------------------------------------------------------
+ * Memory Test
+ *----------------------------------------------------------------------*/
+#define CFG_MEMTEST_START     0x0400000	     /* memtest works on	*/
+#define CFG_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/
+
+/*-----------------------------------------------------------------------
+ * Compact Flash (in true IDE mode)
+ *----------------------------------------------------------------------*/
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	0xF0000000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
+#define CFG_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */
+
+#define CFG_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
+					    to get to the correct offset */
+#define CONFIG_DOS_PARTITION  1		     /* Include dos partition	*/
+
+/*-----------------------------------------------------------------------
+ * PCI
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI			     /* include pci support	*/
+#define CONFIG_PCI_PNP			     /* do pci plug-and-play	*/
+#define CONFIG_PCI_SCAN_SHOW		     /* show pci devices	*/
+#define CFG_PCI_TARGBASE      (CFG_PCI_MEMBASE)
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT		     /* enable board pci_pre_init*/
+#define CFG_PCI_TARGET_INIT		     /* let board init pci target*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE	      8192	     /* For AMCC 405 CPUs	*/
+#define CFG_CACHELINE_SIZE    32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT   5		     /* log base 2 of the above */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	      0x01	     /* Normal PowerOn: Boot from FLASH */
+#define BOOTFLAG_WARM	      0x02	     /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE  230400	     /* kgdb serial port baud	*/
+#define CONFIG_KGDB_SER_INDEX 2		     /* kgdb serial port	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#undef CONFIG_WATCHDOG			     /* watchdog disabled	*/
+#define CFG_LOAD_ADDR	      0x8000000	     /* default load address	*/
+#define CFG_EXTBDINFO	      1		     /* use extended board_info */
+
+#define CFG_HZ		      100	     /* decr freq: 1 ms ticks	*/
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h
new file mode 100755
index 0000000..9b950fc
--- /dev/null
+++ b/include/configs/KUP4K.h
@@ -0,0 +1,489 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ * Derived from ../tqm8xx/tqm8xx.c
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
+#define CONFIG_KUP4K		1	/* ...on a KUP4K module */
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/
+#endif
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+
+#undef	CONFIG_BOOTARGS
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS						\
+"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
+ "run addhw; diskboot 200000 0:1; bootm 200000\0"				\
+"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
+ "run addhw; diskboot 200000 2:1; bootm 200000\0"				\
+"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0"			\
+"panic_boot=echo No Bootdevice !!! reset\0"					\
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
+"ramargs=setenv bootargs root=/dev/ram rw\0"					\
+"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}"	\
+ ":${netmask}:${hostname}:${netdev}:off\0"					\
+"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0"		\
+"netdev=eth0\0"									\
+"contrast=55\0"									\
+"silent=1\0"									\
+"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0"		\
+"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};"		\
+ "cp.b 200000 40050000 14000\0"
+
+#define CONFIG_BOOTCOMMAND  \
+    "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
+
+
+#define CONFIG_MISC_INIT_R	1
+#define CONFIG_MISC_INIT_F	1
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#define	CONFIG_WATCHDOG	1		/* watchdog enabled		*/
+
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+
+/*
+ * enable I2C and select the hardware/software driver
+ */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
+
+#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SOFT_I2C */
+
+
+/*-----------------------------------------------------------------------
+ * I2C Configuration
+ */
+
+#define CFG_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander			*/
+#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
+
+
+/* List of I2C addresses to be verified by POST */
+
+#define I2C_ADDR_LIST	{CFG_I2C_PICIO_ADDR,	\
+			CFG_I2C_RTC_ADDR,	\
+			}
+
+
+#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
+
+#define CFG_DISCOVER_PHY
+#define CONFIG_MII
+
+#if 0
+#define CONFIG_ETHADDR                  00:0B:64:00:00:00 /* our OUI from IEEE */
+#endif
+#define CONFIG_KUP4K_LOGO               0x40050000  /* Address of logo bitmap */
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#if 1
+/* POST support */
+
+#define CONFIG_POST		(CFG_POST_CPU	   | \
+				 CFG_POST_RTC	   | \
+				 CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+#endif
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_POST_DIAG	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x000400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x002C00000	/* 4 ... 44 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x200000	/* default load address */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }
+
+#define CFG_CONSOLE_INFO_QUIET 1
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
+#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000
+
+/* Address and size of Redundant Environment Sector	*/
+#if 0
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#if 1
+#define CFG_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#define CFG_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+#define CFG_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+
+/* KUP4K use both slots, SLOT_A as "primary". */
+#define CONFIG_PCMCIA_SLOT_A 1
+
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+#define PCMCIA_SOCKETS_NO 2
+#define PCMCIA_MEM_WIN_NO 8
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#define CONFIG_IDE_LED		1	/* LED	 for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		2
+#define CFG_IDE_MAXDEVICE	4
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_IDE1_OFFSET	(4 * CFG_PCMCIA_MEM_SIZE)
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096	 Rows from SDRAM example configuration
+ * 1000	 factor s -> ms
+ *   32	 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4	 Number of refresh cycles per period
+ *   64	 Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#if   defined(CONFIG_80MHz)
+#define CFG_MAMR_PTA		156
+#elif defined(CONFIG_66MHz)
+#define CFG_MAMR_PTA		129
+#else		/*   50 MHz */
+#define CFG_MAMR_PTA		 98
+#endif	/*CONFIG_??MHz */
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR 0x400
+
+/*
+ * MAMR settings for SDRAM
+ */
+#define CFG_MAMR 0x80802114
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+
+#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
+#if 0
+#define CONFIG_AUTOBOOT_PROMPT		"Boote in %d Sekunden - stop mit \"2\"\n"
+#endif
+#define CONFIG_AUTOBOOT_STOP_STR	"." /* easy to stop for now */
+#define CONFIG_SILENT_CONSOLE	1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h
new file mode 100755
index 0000000..cd38b0f
--- /dev/null
+++ b/include/configs/KUP4X.h
@@ -0,0 +1,458 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ * Derived from ../tqm8xx/tqm8xx.c
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC859T		1	/* This is a MPC859T CPU		*/
+#define CONFIG_KUP4X		1	/* ...on a KUP4X module			*/
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1			*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate			*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled			*/
+#else
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second		*/
+#endif
+
+#define CONFIG_BOARD_TYPES	1	/* support board types			*/
+
+#define CFG_8XX_FACT		8	/* Multiply by 8			*/
+#define CFG_8XX_XIN		16000000	/* 16 MHz in			*/
+
+
+#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
+
+/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
+/* in general, we always know this for FADS+new ADS anyway */
+#define CONFIG_8xx_GCLK_FREQ	 MPC8XX_HZ
+
+
+#undef	CONFIG_BOOTARGS
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS						\
+"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
+  "run addhw;diskboot 200000 0:1;bootm 200000\0"				\
+"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\
+ run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\
+ usb stop; bootm 200000\0"      \
+"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0"				\
+"panic_boot=echo No Bootdevice !!! reset\0"					\
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
+"ramargs=setenv bootargs root=/dev/ram rw\0"					\
+"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}"	\
+ ":${netmask}:${hostname}:${netdev}:off\0"					\
+"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0"		\
+"netdev=eth0\0"									\
+"silent=1\0"									\
+"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0"		\
+"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};"		\
+ "cp.b 200000 40040000 14000\0"
+
+#define CONFIG_BOOTCOMMAND  \
+    "run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot"
+
+
+#define CONFIG_MISC_INIT_R	1
+#define CONFIG_MISC_INIT_F	1
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
+
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/*
+ * enable I2C and select the hardware/software driver
+ */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
+
+#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SOFT_I2C */
+
+
+/*-----------------------------------------------------------------------
+ * I2C Configuration
+ */
+
+#define CFG_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander			*/
+#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
+
+
+/* List of I2C addresses to be verified by POST */
+
+#define I2C_ADDR_LIST	{CFG_I2C_PICIO_ADDR,	\
+			CFG_I2C_RTC_ADDR,	\
+			}
+
+
+#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
+
+#define CFG_DISCOVER_PHY
+#define CONFIG_MII
+
+#if 0
+#define CONFIG_ETHADDR                  00:0B:64:80:00:00 /* our OUI from IEEE */
+#endif
+#undef CONFIG_KUP4K_LOGO
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+
+#if 1
+/* POST support */
+
+#define CONFIG_POST		(CFG_POST_CPU	   | \
+				 CFG_POST_RTC	   | \
+				 CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+#endif
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_POST_DIAG	| \
+				CFG_CMD_SNTP	| \
+				CFG_CMD_USB	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x000400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x003C00000	/* 4 ... 60 MB in DRAM	*/
+#define CFG_LOAD_ADDR		0x200000	/* default load address */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }
+
+#define CFG_CONSOLE_INFO_QUIET 1
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
+#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000
+
+/* Address and size of Redundant Environment Sector	*/
+#if 0
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#if 1
+#define CFG_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control (15-29)
+ */
+#define CFG_PLPRCR	((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) |	\
+				PLPRCR_SPLSS | PLPRCR_TEXPS)
+
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+#define CFG_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+
+/* KUP4K use both slots, SLOT_A as "primary". */
+#define CONFIG_PCMCIA_SLOT_A 1
+
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+#define PCMCIA_SOCKETS_NO 1
+#define PCMCIA_MEM_WIN_NO 8
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#define CONFIG_IDE_LED			1   /* LED   for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1
+#define CFG_IDE_MAXDEVICE	2
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_IDE1_OFFSET	(4 * CFG_PCMCIA_MEM_SIZE)
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+
+#define CFG_MPTPR 0x400
+
+/*
+ * MAMR settings for SDRAM
+ */
+#define CFG_MAMR 0x80802114
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+
+#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot	*/
+#if 0
+#define CONFIG_AUTOBOOT_PROMPT		"Boote in %d Sekunden - stop mit \"2\"\n"
+#endif
+#define CONFIG_AUTOBOOT_STOP_STR	"."	/* easy to stop for now		*/
+#define CONFIG_SILENT_CONSOLE	1
+
+#define CONFIG_USB_STORAGE	1
+#define CONFIG_USB_SL811HS	1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h
new file mode 100755
index 0000000..e44f1cc
--- /dev/null
+++ b/include/configs/LANTEC.h
@@ -0,0 +1,377 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2001
+ * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
+ * Bruno Achauer, Exet AG, bruno@exet-ag.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ * [derived from config_TQM850L.h]
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_LANTEC		2	/* ...on a Lantec rev.2 board	*/
+
+/*
+ *  Port assignments (CONFIG_LANTEC == 1):
+ *  - SMC1: J11 (MDB) ?
+ *  - SMC2: J6  (Feature connector)
+ *  - SCC2: J9  (RJ45)
+ *  - SCC3: J8  (Sub-D9)
+ *
+ *  Port assignments (CONFIG_LANTEC == 2): TBD
+ */
+
+
+#undef CONFIG_8xx_CONS_SMC2           /* Console is on SMC2           */
+#define	CONFIG_8xx_CONS_SCC3
+#undef  CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE         38400   /* console baudrate = 38.4kbps  */
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_CMD_MINIMAL	0
+#define CONFIG_CMD_TINY		(CFG_CMD_FLASH  | \
+				 CFG_CMD_MEMORY | \
+				 CFG_CMD_LOADS  | \
+				 CFG_CMD_LOADB)
+#define CONFIG_CMD_NORMAL	(CONFIG_CMD_DFL & ~CFG_CMD_BOOTD & ~CFG_CMD_REISER)
+#define CONFIG_CMD_GDB		(CONFIG_CMD_NORMAL | CFG_CMD_KGDB)
+#define CONFIG_CMD_FULL		(CFG_CMD_ALL & ~CFG_CMD_BEDBUG	\
+					     & ~CFG_CMD_BMP	\
+					     & ~CFG_CMD_BSP	\
+					     & ~CFG_CMD_DISPLAY	\
+					     & ~CFG_CMD_DOC	\
+					     & ~CFG_CMD_DTT	\
+					     & ~CFG_CMD_EEPROM	\
+					     & ~CFG_CMD_ELF	\
+					     & ~CFG_CMD_EXT2	\
+					     & ~CFG_CMD_FDC	\
+					     & ~CFG_CMD_FDOS	\
+					     & ~CFG_CMD_HWFLOW	\
+					     & ~CFG_CMD_I2C	\
+					     & ~CFG_CMD_IDE	\
+					     & ~CFG_CMD_IRQ	\
+					     & ~CFG_CMD_JFFS2	\
+					     & ~CFG_CMD_KGDB	\
+					     & ~CFG_CMD_MII	\
+					     & ~CFG_CMD_MMC	\
+					     & ~CFG_CMD_NAND	\
+					     & ~CFG_CMD_PCI	\
+					     & ~CFG_CMD_PCMCIA	\
+					     & ~CFG_CMD_REISER	\
+					     & ~CFG_CMD_SCSI	\
+					     & ~CFG_CMD_SPI	\
+					     & ~CFG_CMD_UNIVERSE\
+					     & ~CFG_CMD_USB	\
+					     & ~CFG_CMD_VFD	\
+					     & ~CFG_CMD_XIMG	)
+
+#if CONFIG_LANTEC >= 2
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+#endif
+
+#if CONFIG_LANTEC >= 2
+# define CONFIG_COMMANDS	CONFIG_CMD_FULL
+#else
+# define CONFIG_COMMANDS	(CONFIG_CMD_FULL & ~CFG_CMD_DATE & ~CFG_CMD_NET)
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK)
+
+/*-----------------------------------------------------------------------
+ * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX]
+ *-----------------------------------------------------------------------
+ */
+#define	CONFIG_8xx_GCLK_FREQ	33000000
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+			/* up to 50 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+			/* up to 50 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/5 and OR0/5 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE5_PRELIM	0x60000000	/* FLASH bank #1	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing */
+#define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | \
+				 OR_SCY_5_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR5_REMAP   CFG_OR0_REMAP
+#define CFG_OR5_PRELIM  CFG_OR0_PRELIM
+#define CFG_BR5_PRELIM  ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank #0        */
+#define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
+
+/* SDRAM timing: Multiplexed addresses					*/
+#define CFG_OR_TIMING_SDRAM     (OR_CSNT_SAM)
+
+#define CFG_OR3_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL \
+			((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		""
+#define MTDPARTS_DEFAULT	""
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
new file mode 100755
index 0000000..5fd6a95
--- /dev/null
+++ b/include/configs/M5272C3.h
@@ -0,0 +1,189 @@
+/*
+ * Configuation settings for the Motorola MC5272C3 board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5272C3_H
+#define _M5272C3_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF52x2			/* define processor family */
+#define CONFIG_M5272			/* define processor type */
+
+#define FEC_ENET
+
+#define CONFIG_BAUDRATE		19200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#define CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
+
+#define CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_ENV_OFFSET		0x4000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_IS_EMBEDDED	1
+#else
+#define CFG_ENV_ADDR		0xffe04000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#endif
+
+#define CONFIG_COMMANDS	 ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) | \
+			   CFG_CMD_MII)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#define CONFIG_BOOTDELAY	5
+
+#define CFG_PROMPT		"-> "
+#define CFG_LONGHELP				/* undef to save memory		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_LOAD_ADDR		0x20000
+
+#define CFG_MEMTEST_START	0x400
+#define CFG_MEMTEST_END		0x380000
+
+#define CFG_HZ			1000
+#define CFG_CLK			66000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_MBAR		0x10000000	/* Register Base Addrs */
+
+#define CFG_SCR			0x0003;
+#define CFG_SPR			0xffff;
+
+#define CFG_DISCOVER_PHY
+#define CFG_ENET_BD_BASE	0x380000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x20000000
+#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
+#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_SIZE		4		/* SDRAM size in MB */
+#define CFG_FLASH_BASE		0xffe00000
+
+#ifdef	CONFIG_MONITOR_IS_IN_RAM
+#define CFG_MONITOR_BASE	0x20000
+#else
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#endif
+
+#define CFG_MONITOR_LEN		0x20000
+#define CFG_MALLOC_LEN		(256 << 10)
+#define CFG_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	11	/* max number of sectors on one chip	*/
+#define CFG_FLASH_ERASE_TOUT	1000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+#define CFG_BR0_PRELIM		0xFFE00201
+#define CFG_OR0_PRELIM		0xFFE00014
+
+#define CFG_BR1_PRELIM		0
+#define CFG_OR1_PRELIM		0
+
+#define CFG_BR2_PRELIM		0x30000001
+#define CFG_OR2_PRELIM		0xFFF80000
+
+#define CFG_BR3_PRELIM		0
+#define CFG_OR3_PRELIM		0
+
+#define CFG_BR4_PRELIM		0
+#define CFG_OR4_PRELIM		0
+
+#define CFG_BR5_PRELIM		0
+#define CFG_OR5_PRELIM		0
+
+#define CFG_BR6_PRELIM		0
+#define CFG_OR6_PRELIM		0
+
+#define CFG_BR7_PRELIM		0x00000701
+#define CFG_OR7_PRELIM		0xFFC0007C
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CFG_PACNT		0x00000000
+#define CFG_PADDR		0x0000
+#define CFG_PADAT		0x0000
+#define CFG_PBCNT		0x55554155		/* Ethernet/UART configuration */
+#define CFG_PBDDR		0x0000
+#define CFG_PBDAT		0x0000
+#define CFG_PDCNT		0x00000000
+
+#endif	/* _M5272C3_H */
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
new file mode 100755
index 0000000..cbb3e3b
--- /dev/null
+++ b/include/configs/M5282EVB.h
@@ -0,0 +1,151 @@
+/*
+ * Configuation settings for the Motorola MC5282EVB board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _CONFIG_M5282EVB_H
+#define _CONFIG_M5282EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define	CONFIG_MCF52x2			/* define processor family */
+#define CONFIG_M5282			/* define processor type */
+
+#define FEC_ENET
+
+#define CONFIG_BAUDRATE 19200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#define	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CFG_ENV_ADDR		0xffe04000
+#define CFG_ENV_SIZE		0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+
+
+#define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#define CONFIG_BOOTDELAY	5
+
+#define CFG_PROMPT		"-> "
+#define	CFG_LONGHELP				/* undef to save memory		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_LOAD_ADDR		0x20000
+
+#define CFG_MEMTEST_START	0x400
+#define CFG_MEMTEST_END		0x380000
+
+#define CFG_HZ			1000000
+#define	CFG_CLK			64000000
+
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define	CFG_MBAR		0x40000000
+
+#undef	CFG_DISCOVER_PHY
+#define	CFG_ENET_BD_BASE	0x380000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR       0x20000000
+#define CFG_INIT_RAM_END	0x10000		/* End of used area in internal SRAM	*/
+#define CFG_GBL_DATA_SIZE	64      	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define	CFG_SDRAM_SIZE		4		/* SDRAM size in MB */
+#define CFG_FLASH_BASE		0xffe00000
+#define	CFG_INT_FLASH_BASE	0xf0000000
+
+/* If M5282 port is fully implemented the monitor base will be behind
+ * the vector table. */
+/* #define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400) */
+#define CFG_MONITOR_BASE	0x20000
+
+#define CFG_MONITOR_LEN		0x20000
+#define CFG_MALLOC_LEN		(256 << 10)
+#define CFG_BOOTPARAMS_LEN	64*1024
+
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define	CFG_MAX_FLASH_SECT	35
+#define	CFG_MAX_FLASH_BANKS	1
+#define	CFG_FLASH_ERASE_TOUT	10000000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16
+
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+
+
+#endif	/* _CONFIG_M5282EVB_H */
diff --git a/include/configs/MBX.h b/include/configs/MBX.h
new file mode 100755
index 0000000..d6e3fb8
--- /dev/null
+++ b/include/configs/MBX.h
@@ -0,0 +1,307 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the MBX8xx board.
+ *
+ * -----------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * Changed 2002-10-01
+ * Added PCMCIA defines mostly taken from other U-Boot boards that
+ * have PCMCIA already working.  If you find any bugs, incorrect assumptions
+ * feel free to fix them yourself and submit a patch.
+ * Rod Boyce <rod_boyce@stratexnet.com.
+ */
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
+#define CONFIG_MBX		1	/* ...on an MBX module		*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600
+/* Define this to use the PCI bus */
+#undef CONFIG_USE_PCI
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_8xx_GCLK_FREQ    (50000000UL)
+#if 1
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_BOOTCOMMAND	"bootm 20000" /* autoboot command	*/
+
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
+				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
+				"nfsaddrs=10.0.0.99:10.0.0.2"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE   /* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_COMMANDS		( CFG_CMD_NET | CONFIG_CMD_DFL | CFG_CMD_SDRAM | \
+			      CFG_CMD_PCMCIA | CFG_CMD_IDE )
+
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#undef	CFG_HUSH_PARSER			/* Hush parse for U-Boot	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Physical memory map as defined by the MBX PGM
+ */
+#define CFG_IMMR		0xFA200000 /* Internal Memory Mapped Register*/
+#define CFG_NVRAM_BASE		0xFA000000 /* NVRAM			     */
+#define CFG_NVRAM_OR		0xffe00000 /* w/o speed dependent flags!!    */
+#define CFG_CSR_BASE		0xFA100000 /* Control/Status Registers	     */
+#define CFG_PCIMEM_BASE		0x80000000 /* PCI I/O and Memory Spaces	     */
+#define CFG_PCIMEM_OR		0xA0000108
+#define CFG_PCIBRIDGE_BASE	0xFA210000 /* PCI-Bus Bridge Registers	     */
+#define CFG_PCIBRIDGE_OR	0xFFFF0108
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2f00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
+#define CFG_INIT_VPD_OFFSET	(CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
+#define CFG_INIT_SP_OFFSET	(CFG_INIT_VPD_OFFSET-8)
+
+/*-----------------------------------------------------------------------
+ * Offset in DPMEM where we keep the VPD data
+ */
+#define CFG_DPRAMVPD		(CFG_INIT_VPD_OFFSET - 0x2000)
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xfe000000
+#ifdef	DEBUG
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#endif
+#undef	CFG_MONITOR_BASE	/* 0x200000	   to run U-Boot from RAM */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	16	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * NVRAM Configuration
+ *
+ * Note: the MBX is special because there is already a firmware on this
+ * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
+ * access the NVRAM at the offset 0x1000.
+ */
+#define CFG_ENV_IS_IN_NVRAM	1	/* turn on NVRAM env feature */
+#define CFG_ENV_ADDR		(CFG_NVRAM_BASE + 0x1000)
+#define CFG_ENV_SIZE		0x1000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+/* #define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC )
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)
+#define CFG_SCCR	SCCR_TBS
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+#define CFG_PCMCIA_INTERRUPT	SIU_LEVEL6
+
+#define CONFIG_PCMCIA_SLOT_A	1
+
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ * Debug Entry Mode
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MBX860T.h b/include/configs/MBX860T.h
new file mode 100755
index 0000000..0ca0970
--- /dev/null
+++ b/include/configs/MBX860T.h
@@ -0,0 +1,407 @@
+ /*
+  * A collection of structures, addresses, and values associated with
+  * the Motorola 860T MBX board.
+  * Copied from the FADS stuff, which was originally copied from the MBX stuff!
+  * Magnus Damm added defines for 8xxrom and extended bd_info.
+  * Helmut Buchsbaum added bitvalues for BCSRx
+  * Rob Taylor coverted it back to MBX
+  *
+  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+  */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#include <mpc8xx_irq.h>
+
+#define CONFIG_MPC860		1
+#define CONFIG_MPC860T		1
+#define CONFIG_MBX		1
+
+#define CONFIG_8xx_CPUCLOCK	40
+#define CONFIG_8xx_BUSCLOCK	(CONFIG_8xx_CPUCLOCK)
+#define TARGET_SYSTEM_FREQUENCY 40
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#define CONFIG_BAUDRATE		9600
+
+#define MPC8XX_FACT	10				/* Multiply by 10		*/
+#define MPC8XX_XIN	40000000		/* 50 MHz in	*/
+#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#if 1
+#define CONFIG_8xx_BOOTDELAY	-1	/* autoboot disabled		*/
+#define CONFIG_8xx_TFTP_MODE
+#else
+#define CONFIG_8xx_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#undef	CONFIG_8xx_TFTP_MODE
+#endif
+
+#define CONFIG_DRAM_SPEED	(CONFIG_8xx_BUSCLOCK)	/* MHz		*/
+#define CONFIG_BOOTCOMMAND	"bootm FE020000"	/* autoboot command */
+#define CONFIG_BOOTARGS		" "
+/*
+ * Miscellaneous configurable options
+ */
+#undef	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0800000	/* 4 ... 8 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR			0xFFA00000
+#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+#define CFG_NVRAM_BASE		0xFA000000 /* NVRAM                          */
+#define CFG_NVRAM_OR		0xffe00000 /* w/o speed dependent flags!!    */
+#define CFG_CSR_BASE		0xFA100000 /* Control/Status Registers       */
+#define CFG_PCIMEM_BASE		0x80000000 /* PCI I/O and Memory Spaces      */
+#define CFG_PCIMEM_OR		0xA0000108
+#define CFG_PCIBRIDGE_BASE	0xFA210000 /* PCI-Bus Bridge Registers       */
+#define CFG_PCIBRIDGE_OR	0xFFFF0108
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2f00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
+#define CFG_INIT_VPD_OFFSET	(CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
+#define	CFG_INIT_SP_OFFSET	(CFG_INIT_VPD_OFFSET-8)
+
+/*-----------------------------------------------------------------------
+ * Offset in DPMEM where we keep the VPD data
+ */
+#define CFG_DPRAMVPD		(CFG_INIT_VPD_OFFSET - 0x2000)
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x00000000
+/*0xFE000000*/
+#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_HWINFO_ADDR		(CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_HWINFO_LEN)
+#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	16	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * NVRAM Configuration
+ *
+ * Note: the MBX is special because there is already a firmware on this
+ * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
+ * access the NVRAM at the offset 0x1000.
+ */
+#define CFG_ENV_IS_IN_NVRAM	1	/* turn on NVRAM env feature */
+#define CFG_ENV_ADDR		(CFG_NVRAM_BASE + 0x1000)
+#define CFG_ENV_SIZE		0x1000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)
+#define CFG_SCCR	SCCR_TBS
+
+ /*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently.  Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register.  For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+/* the other CS:s are determined by looking at parameters in BCSRx */
+
+
+#define BCSR_ADDR		((uint) 0xFF010000)
+#define BCSR_SIZE		((uint)(64 * 1024))
+
+#define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFF010000	/* FLASH bank #0	*/
+
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFFF00000	/* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
+#define CFG_BR0_PRELIM	(0xFE000000 | BR_V )
+
+/* BCSRx - Board Control and Status Registers */
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	0xFFC00000 | OR_ACS_DIV4
+#define CFG_BR1_PRELIM	(0x00000000 | BR_MS_UPMA | BR_V )
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA		97		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CFG_MAMR		0x13821000
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD			0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM			0x02		/* Software reboot			*/
+
+
+/* values according to the manual */
+
+
+#define PCMCIA_MEM_ADDR		((uint)0xff020000)
+#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
+
+#define	BCSR0			((uint) (BCSR_ADDR + 00))
+#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
+#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
+#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
+#define	BCSR4			((uint) (BCSR_ADDR + 0x10))
+
+/* FADS bitvalues by Helmut Buchsbaum
+ * see MPC8xxADS User's Manual for a proper description
+ * of the following structures
+ */
+
+#define BCSR0_ERB       ((uint)0x80000000)
+#define BCSR0_IP        ((uint)0x40000000)
+#define BCSR0_BDIS      ((uint)0x10000000)
+#define BCSR0_BPS_MASK  ((uint)0x0C000000)
+#define BCSR0_ISB_MASK  ((uint)0x01800000)
+#define BCSR0_DBGC_MASK ((uint)0x00600000)
+#define BCSR0_DBPC_MASK ((uint)0x00180000)
+#define BCSR0_EBDF_MASK ((uint)0x00060000)
+
+#define BCSR1_FLASH_EN           ((uint)0x80000000)
+#define BCSR1_DRAM_EN            ((uint)0x40000000)
+#define BCSR1_ETHEN              ((uint)0x20000000)
+#define BCSR1_IRDEN              ((uint)0x10000000)
+#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
+#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
+#define BCSR1_BCSR_EN            ((uint)0x02000000)
+#define BCSR1_RS232EN_1          ((uint)0x01000000)
+#define BCSR1_PCCEN              ((uint)0x00800000)
+#define BCSR1_PCCVCC0            ((uint)0x00400000)
+#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
+#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
+#define BCSR1_RS232EN_2          ((uint)0x00040000)
+#define BCSR1_SDRAM_EN           ((uint)0x00020000)
+#define BCSR1_PCCVCC1            ((uint)0x00010000)
+
+#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
+#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
+#define BCSR2_DRAM_PD_SHIFT      (23)
+#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
+#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
+
+#define BCSR3_DBID_MASK          ((ushort)0x3800)
+#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
+#define BCSR3_BREVNR0            ((ushort)0x0080)
+#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
+#define BCSR3_BREVN1             ((ushort)0x0008)
+#define BCSR3_BREVN2_MASK        ((ushort)0x0003)
+
+#define BCSR4_ETHLOOP            ((uint)0x80000000)
+#define BCSR4_TFPLDL             ((uint)0x40000000)
+#define BCSR4_TPSQEL             ((uint)0x20000000)
+#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
+#ifdef CONFIG_MPC823
+#define BCSR4_USB_EN             ((uint)0x08000000)
+#endif /* CONFIG_MPC823 */
+#ifdef CONFIG_MPC860SAR
+#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
+#endif /* CONFIG_MPC860SAR */
+#ifdef CONFIG_MPC860T
+#define BCSR4_FETH_EN            ((uint)0x08000000)
+#endif /* CONFIG_MPC860T */
+#define BCSR4_USB_SPEED          ((uint)0x04000000)
+#define BCSR4_VCCO               ((uint)0x02000000)
+#define BCSR4_VIDEO_ON           ((uint)0x00800000)
+#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
+#define BCSR4_VIDEO_RST          ((uint)0x00200000)
+#define BCSR4_MODEM_EN           ((uint)0x00100000)
+#define BCSR4_DATA_VOICE         ((uint)0x00080000)
+
+#define CONFIG_DRAM_40MHZ		1
+
+#ifdef CONFIG_MPC860T
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
+
+#endif /* CONFIG_MPC860T */
+
+/* We don't use the 8259.
+*/
+#define NR_8259_INTS	0
+
+/* Machine type
+*/
+#define _MACH_8xx (_MACH_fads)
+
+/*
+ * MPC8xx CPM Options
+ */
+#define CONFIG_SCC_ENET 1
+#define CONFIG_SCC1_ENET 1
+#define CONFIG_FEC_ENET 1
+#undef  CONFIG_CPM_IIC
+#undef  CONFIG_UCODE_PATCH
+
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+
+/* PCMCIA configuration */
+
+#define PCMCIA_MAX_SLOTS    2
+
+#ifdef CONFIG_MPC860
+#define PCMCIA_SLOT_A 1
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h
new file mode 100755
index 0000000..b965571
--- /dev/null
+++ b/include/configs/METROBOX.h
@@ -0,0 +1,378 @@
+/*
+ * (C) Copyright 2004 Sandburst Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * METROBOX.h - configuration Sandburst MetroBox
+ ***********************************************************************/
+
+/*
+ * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $
+ *
+ *
+ * $Log: METROBOX.h,v $
+ * Revision 1.21  2005/06/03 15:05:25  tsawyer
+ * MB rev 2.0.3 KA rev 0.0.7.  Add CONFIG_VERSION_VARIABLE, Add fakeled to MB
+ *
+ * Revision 1.20  2005/04/11 20:51:11  tsawyer
+ * fix ethernet
+ *
+ * Revision 1.19  2005/04/06 15:13:36  tsawyer
+ * Update appropriate files to coincide with u-boot 1.1.3
+ *
+ * Revision 1.18  2005/03/10 14:16:02  tsawyer
+ * add def'n for cis8201 short etch option.
+ *
+ * Revision 1.17  2005/03/09 19:49:51  tsawyer
+ * Remove KGDB to allow use of 2nd serial port
+ *
+ * Revision 1.16  2004/12/02 19:00:23  tsawyer
+ * Add misc_init_f to turn on i2c-1 and all four fans before sdram init
+ *
+ * Revision 1.15  2004/09/15 18:04:12  tsawyer
+ * add multiple serial port support
+ *
+ * Revision 1.14  2004/09/03 15:27:51  tsawyer
+ * All metrobox boards are at 66.66 sys clock
+ *
+ * Revision 1.13  2004/08/05 20:27:46  tsawyer
+ * Remove system ace definitions, add net console support
+ *
+ * Revision 1.12  2004/07/29 20:00:13  tsawyer
+ * Add i2c bus 1
+ *
+ * Revision 1.11  2004/07/21 13:44:18  tsawyer
+ * SystemACE is out, CF direct to local bus is in
+ *
+ * Revision 1.10  2004/06/29 19:08:55  tsawyer
+ * Add CONFIG_MISC_INIT_R
+ *
+ * Revision 1.9	 2004/06/28 21:30:53  tsawyer
+ * Fix default BOOTARGS
+ *
+ * Revision 1.8	 2004/06/17 15:51:08  tsawyer
+ * auto complete
+ *
+ * Revision 1.7	 2004/06/17 15:08:49  tsawyer
+ * Add autocomplete
+ *
+ * Revision 1.6	 2004/06/15 12:33:57  tsawyer
+ * debugging checkpoint
+ *
+ * Revision 1.5	 2004/06/12 19:48:28  tsawyer
+ * Debugging checkpoint
+ *
+ * Revision 1.4	 2004/06/02 13:03:06  tsawyer
+ * Fix eth addrs
+ *
+ * Revision 1.3	 2004/05/18 19:56:10  tsawyer
+ * Change default bootcommand to pImage.metrobox
+ *
+ * Revision 1.2	 2004/05/18 14:13:44  tsawyer
+ * Add bringup values for bootargs and bootcommand.
+ * Remove definition of ipaddress and serverip addresses.
+ *
+ * Revision 1.1	 2004/04/16 15:08:54  tsawyer
+ * Initial Revision
+ *
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_METROBOX		  1	     /* Board is Metrobox	*/
+#define CONFIG_440GX		  1	     /* Specifc GX support	*/
+#define CONFIG_4xx		  1	     /* ... PPC4xx family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
+#define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
+#define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/
+#undef	CFG_DRAM_TEST			     /* Disable-takes long time!*/
+#define CONFIG_SYS_CLK_FREQ	  66666666   /* external freq to pll	*/
+
+#define CONFIG_VERY_BIG_RAM 1
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_IDENT_STRING " Sandburst Metrobox"
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
+#define CFG_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
+#define CFG_MONITOR_BASE       0xfff80000    /* start of monitor	*/
+#define CFG_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
+#define CFG_PERIPHERAL_BASE    0xe0000000    /* internal peripherals	*/
+#define CFG_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
+#define CFG_PCI_BASE	       0xd0000000    /* internal PCI regs	*/
+
+#define CFG_NVRAM_BASE_ADDR   (CFG_PERIPHERAL_BASE + 0x08000000)
+#define CFG_FPGA_BASE	      (CFG_PERIPHERAL_BASE + 0x08200000)
+#define CFG_BME32_BASE	      (CFG_PERIPHERAL_BASE + 0x08500000)
+#define CFG_GPIO_BASE	      (CFG_PERIPHERAL_BASE + 0x00000700)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM    1
+#define CFG_OCM_DATA_ADDR     CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR     CFG_ISRAM_BASE /* Initial RAM address	*/
+#define CFG_INIT_RAM_END      0x2000	     /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE     128	     /* num bytes initial data	*/
+
+#define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR    (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET    CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
+#define CFG_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SERIAL_MULTI   1
+#define CONFIG_BAUDRATE	      9600
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
+#define CONFIG_RTC_DS174x     1		     /* DS1743 RTC		*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS   1		     /* number of banks		*/
+#define CFG_MAX_FLASH_SECT    8		     /* sectors per device	*/
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
+#define CFG_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM     1		     /* Use SPD EEPROM for setup*/
+#define SPD_EEPROM_ADDRESS    {0x53}	     /* SPD i2c spd addresses	*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C	      1		     /* I2C hardware support	*/
+#undef	CONFIG_SOFT_I2C			     /* I2C !bit-banged		*/
+#define CFG_I2C_SPEED	      400000	     /* I2C speed 400kHz	*/
+#define CFG_I2C_SLAVE	      0x7F	     /* I2C slave address	*/
+#define CFG_I2C_NOPROBES      {0x69}	     /* Don't probe these addrs */
+#define CONFIG_I2C_BUS1	      1		     /* Include i2c bus 1 supp	*/
+
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_NVRAM   1		     /* Environment uses NVRAM	*/
+#undef	CFG_ENV_IS_IN_FLASH		     /* ... not in flash	*/
+#undef	CFG_ENV_IS_IN_EEPROM		     /* ... not in EEPROM	*/
+#define CONFIG_ENV_OVERWRITE  1		     /* allow env overwrite	*/
+
+#define CFG_ENV_SIZE	      0x1000	     /* Size of Env vars	*/
+#define CFG_ENV_ADDR	      (CFG_NVRAM_BASE_ADDR)
+
+#define CONFIG_BOOTARGS	      "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none "
+#define CONFIG_BOOTCOMMAND    "tftp 8000000 pImage.metrobox;bootm 8000000"
+#define CONFIG_BOOTDELAY      5		    /* disable autoboot */
+
+#define CONFIG_LOADS_ECHO     1		     /* echo on for serial dnld */
+#define CFG_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/
+
+/*-----------------------------------------------------------------------
+ * Networking
+ *----------------------------------------------------------------------*/
+#define CONFIG_MII	      1		     /* MII PHY management	*/
+#define CONFIG_NET_MULTI      1
+#define CONFIG_PHY_ADDR	      0xff	     /* no phy on EMAC0		*/
+#define CONFIG_PHY1_ADDR      0xff	     /* no phy on EMAC1		*/
+#define CONFIG_PHY2_ADDR      0x08	     /* PHY addr, MGMT, EMAC2	*/
+#define CONFIG_PHY3_ADDR      0x18	     /* PHY addr, LCL, EMAC3	*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_PHY_RESET      1              /* reset phy upon startup  */
+#define CONFIG_CIS8201_PHY    1		     /* RGMII mode for Cicada	*/
+#define CONFIG_CIS8201_SHORT_ETCH 1	     /* Use short etch mode	*/
+#define CONFIG_PHY_GIGE	      1		     /* GbE speed/duplex detect */
+#define CONFIG_PHY_RESET_DELAY 1000
+#define CONFIG_NETMASK	      255.255.0.0
+#define CONFIG_ETHADDR	      00:00:00:00:00:00 /* No EMAC 0 support	*/
+#define CONFIG_ETH1ADDR	      00:00:00:00:00:00 /* No EMAC 1 support	*/
+#define CFG_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/
+
+
+/*-----------------------------------------------------------------------
+ * Console/Commands/Parser
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT)
+
+/* tbs 09-March-2005 Removed to be able to use 2nd serial */
+/*				  CFG_CMD_KGDB	  | \ */
+
+
+/* Include NetConsole support */
+#define CONFIG_NETCONSOLE
+
+/* Include auto complete with tabs */
+#define CONFIG_AUTO_COMPLETE 1
+#define CFG_AUTO_COMPLETE    1
+#define CFG_ALT_MEMTEST	     1	     /* use real memory test	 */
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_LONGHELP			     /* undef to save memory	*/
+#define CFG_PROMPT	      "MetroBox=> "  /* Monitor Command Prompt	*/
+
+#define CFG_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
+#define CFG_PROMPT_HUSH_PS2    "> "
+
+
+/*-----------------------------------------------------------------------
+ * Console Buffer
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	      1024	     /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE	      256	     /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+					     /* Print Buffer Size	*/
+#define CFG_MAXARGS	      16	     /* max number of cmd args	*/
+#define CFG_BARGSIZE	      CFG_CBSIZE     /* Boot Arg Buffer Size	*/
+
+/*-----------------------------------------------------------------------
+ * Memory Test
+ *----------------------------------------------------------------------*/
+#define CFG_MEMTEST_START     0x0400000	     /* memtest works on	*/
+#define CFG_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/
+
+/*-----------------------------------------------------------------------
+ * Compact Flash (in true IDE mode)
+ *----------------------------------------------------------------------*/
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	0xF0000000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
+#define CFG_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */
+
+#define CFG_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
+					    to get to the correct offset */
+#define CONFIG_DOS_PARTITION  1		     /* Include dos partition	*/
+
+/*-----------------------------------------------------------------------
+ * PCI
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI			     /* include pci support	*/
+#define CONFIG_PCI_PNP			     /* do pci plug-and-play	*/
+#define CONFIG_PCI_SCAN_SHOW		     /* show pci devices	*/
+#define CFG_PCI_TARGBASE      (CFG_PCI_MEMBASE)
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT		     /* enable board pci_pre_init*/
+#define CFG_PCI_TARGET_INIT		     /* let board init pci target*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE	      8192	     /* For AMCC 405 CPUs	*/
+#define CFG_CACHELINE_SIZE    32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT   5		     /* log base 2 of the above */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	      0x01	     /* Normal PowerOn: Boot from FLASH */
+#define BOOTFLAG_WARM	      0x02	     /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE  230400	     /* kgdb serial port baud	*/
+#define CONFIG_KGDB_SER_INDEX 2		     /* kgdb serial port	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#undef CONFIG_WATCHDOG			     /* watchdog disabled	*/
+#define CFG_LOAD_ADDR	      0x8000000	     /* default load address	*/
+#define CFG_EXTBDINFO	      1		     /* use extended board_info */
+
+#define CFG_HZ		      100	     /* decr freq: 1 ms ticks	*/
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h
new file mode 100755
index 0000000..53684ca
--- /dev/null
+++ b/include/configs/MHPC.h
@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2001
+ * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Configuation settings for the miniHiPerCam.
+ *
+ * -----------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_MHPC		1	/* on a miniHiPerCam		*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* do special hardware init.	*/
+#define CONFIG_MISC_INIT_R	1
+
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_SPEED
+#undef	CONFIG_8xx_CONS_SMC1
+#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ETHADDR		00:00:5b:ee:de:ad
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND	\
+	"bootp;"								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#undef	CONFIG_UCODE_PATCH
+
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CFG_I2C_SPEED			50000
+#define CFG_I2C_SLAVE			0xFE
+#define CFG_I2C_EEPROM_ADDR		0x50	/* EEPROM X24C04		*/
+#define CFG_I2C_EEPROM_ADDR_LEN		1	/* bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#define LCD_VIDEO_ADDR		(SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
+#define LCD_VIDEO_SIZE		SDRAM_RES_SIZE	/* 2MB */
+#define LCD_VIDEO_COLS		640
+#define LCD_VIDEO_ROWS		480
+#define LCD_VIDEO_FG		255
+#define LCD_VIDEO_BG		0
+
+#undef	CONFIG_VIDEO				/* test only ! s.a devices.c and 8xx */
+#define CONFIG_CFB_CONSOLE			/* framebuffer console with std input */
+#define CONFIG_VIDEO_LOGO
+
+#define VIDEO_KBD_INIT_FCT	0		/* no KBD dev on MHPC - use serial */
+#define VIDEO_TSTC_FCT		serial_tstc
+#define VIDEO_GETC_FCT		serial_getc
+
+#define CONFIG_BR0_WORKAROUND	1
+
+#define CONFIG_COMMANDS	     ( CONFIG_CMD_DFL  | \
+			       CFG_CMD_DATE    | \
+			       CFG_CMD_EEPROM  | \
+			       CFG_CMD_ELF     | \
+			       CFG_CMD_I2C     | \
+			       CFG_CMD_JFFS2   | \
+			       CFG_CMD_REGINFO )
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x300000	/* default load address */
+
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Physical memory map
+ */
+#define CFG_IMMR		0xFFF00000 /* Internal Memory Mapped Register*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xfe000000
+
+#define CFG_MONITOR_LEN		0x40000		/* Reserve 256 kB for Monitor	*/
+#undef	CFG_MONITOR_BASE		    /* to run U-Boot from RAM */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=mhpc-0"
+#define MTDPARTS_DEFAULT	"mtdparts=mhpc-0:-(jffs2)"
+*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map- for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		CFG_MONITOR_LEN /* Offset of Environment */
+#define CFG_ENV_SIZE		0x20000 /* Total Size of Environment	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_SEME)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		12-18
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define MPC8XX_SPEED	50000000L
+#define MPC8XX_XIN	5000000L      /* ref clk */
+#define MPC8XX_FACT	(MPC8XX_SPEED/MPC8XX_XIN)
+#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
+			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+
+#define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)     /* SCCR_EBDF11 */
+#define CFG_SCCR	(SCCR_TBS | SCCR_DFLCD001)
+
+
+/*-----------------------------------------------------------------------
+ * MAMR settings for SDRAM	- 16-14
+ * => 0xC080200F
+ *-----------------------------------------------------------------------
+ * periodic timer for refresh
+ */
+#define CFG_MAMR_PTA	0xC0
+#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
+
+/*
+ * BR0 and OR0 (FLASH) used to re-map FLASH
+ */
+
+/* allow for max 8 MB of Flash */
+#define FLASH_BASE		0xFE000000	/* FLASH bank #0*/
+#define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0*/
+#define CFG_REMAP_OR_AM		0xFF800000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
+
+/*
+ * BR1 and OR1 (SDRAM)
+ */
+#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_MAX_SIZE		0x01000000	/* max 16 MB		*/
+#define SDRAM_RES_SIZE		0x00200000	/* 2 MB for framebuffer */
+
+/* SDRAM timing: drive GPL5 high on first cycle */
+#define CFG_OR_TIMING_SDRAM	(OR_G5LS)
+
+#define CFG_OR1_PRELIM	((~(SDRAM_MAX_SIZE)+1)| CFG_OR_TIMING_SDRAM )
+#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR2/OR2 - DIMM
+ */
+#define CFG_OR2		(OR_ACS_DIV4)
+#define CFG_BR2		(BR_MS_UPMA)
+
+/*
+ * BR3/OR3 - DIMM
+ */
+#define CFG_OR3		(OR_ACS_DIV4)
+#define CFG_BR3		(BR_MS_UPMA)
+
+/*
+ * BR4/OR4
+ */
+#define CFG_OR4		0
+#define CFG_BR4		0
+
+/*
+ * BR5/OR5
+ */
+#define CFG_OR5		0
+#define CFG_BR5		0
+
+/*
+ * BR6/OR6
+ */
+#define CFG_OR6		0
+#define CFG_BR6		0
+
+/*
+ * BR7/OR7
+ */
+#define CFG_OR7		0
+#define CFG_BR7		0
+
+
+/*-----------------------------------------------------------------------
+ * Debug Entry Mode
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
new file mode 100755
index 0000000..db2147b
--- /dev/null
+++ b/include/configs/MIP405.h
@@ -0,0 +1,456 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/***********************************************************
+ * High Level Configuration Options
+ * (easy to change)
+ ***********************************************************/
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_MIP405		1	/* ...on a MIP405 board		*/
+/***********************************************************
+ * Note that it may also be a MIP405T board which is a subset of the
+ * MIP405
+ ***********************************************************/
+/***********************************************************
+ * WARNING:
+ * CONFIG_BOOT_PCI is only used for first boot-up and should
+ * NOT be enabled for production bootloader
+ ***********************************************************/
+/*#define        CONFIG_BOOT_PCI         1*/
+/***********************************************************
+ * Clock
+ ***********************************************************/
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll   */
+
+/***********************************************************
+ * Command definitions
+ ***********************************************************/
+#define MIP405_COMMON_CMDS \
+		       (CONFIG_CMD_DFL	| \
+			CFG_CMD_CACHE	| \
+			CFG_CMD_DATE	| \
+			CFG_CMD_DHCP	| \
+			CFG_CMD_ECHO	| \
+			CFG_CMD_EEPROM	| \
+			CFG_CMD_ELF	| \
+			CFG_CMD_FAT	| \
+			CFG_CMD_I2C	| \
+			CFG_CMD_IDE	| \
+			CFG_CMD_IRQ	| \
+			CFG_CMD_JFFS2	| \
+			CFG_CMD_MII	| \
+			CFG_CMD_PCI	| \
+			CFG_CMD_PING	| \
+			CFG_CMD_REGINFO | \
+			CFG_CMD_SAVES	| \
+			CFG_CMD_BSP	)
+
+#if defined(CONFIG_MIP405T)
+#define CONFIG_COMMANDS		\
+			MIP405_COMMON_CMDS
+#else
+#define CONFIG_COMMANDS		\
+			(MIP405_COMMON_CMDS | \
+			CFG_CMD_USB	| \
+			CFG_CMD_DOC	)
+
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS  (if any) */
+#include <cmd_confdefs.h>
+
+#define	 CFG_HUSH_PARSER
+#define	 CFG_PROMPT_HUSH_PS2 "> "
+/**************************************************************
+ * I2C Stuff:
+ * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
+ * 0x53.
+ * The Atmel EEPROM uses 16Bit addressing.
+ ***************************************************************/
+
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		50000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x53	/* EEPROM 24C128/256		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#define CFG_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
+					/* 64 byte page write mode using*/
+					/* last	6 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_ENABLE	/* enable Page write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x00000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x00800	/* 2k bytes may be used for env vars */
+
+/***************************************************************
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ ***************************************************************/
+/*#define SDRAM_EEPROM_WRITE_ADDRESS	0xA0
+#define SDRAM_EEPROM_READ_ADDRESS 	0xA1
+*/
+/**************************************************************
+ * Environment definitions
+ **************************************************************/
+#define CONFIG_BAUDRATE		9600	/* STD Baudrate */
+#define CONFIG_BOOTDELAY	5
+/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
+/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
+#define CONFIG_ZERO_BOOTDELAY_CHECK  	/* check console even if bootdelay = 0 */
+
+#define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
+#define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
+
+#define CONFIG_IPADDR		10.0.0.100
+#define CONFIG_SERVERIP		10.0.0.1
+#define CONFIG_PREBOOT
+/***************************************************************
+ * defines if the console is stored in the environment
+ ***************************************************************/
+#define CFG_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
+/***************************************************************
+ * defines if an overwrite_console function exists
+ *************************************************************/
+#define CFG_CONSOLE_OVERWRITE_ROUTINE
+#define CFG_CONSOLE_INFO_QUIET
+/***************************************************************
+ * defines if the overwrite_console should be stored in the
+ * environment
+ **************************************************************/
+#undef CFG_CONSOLE_ENV_OVERWRITE
+
+/**************************************************************
+ * loads config
+ *************************************************************/
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MISC_INIT_R
+/***********************************************************
+ * Miscellaneous configurable options
+ **********************************************************/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_BASE_BAUD       916667
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x400000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
+#define CONFIG_PCI_PNP			/* pci plug-and-play		*/
+					/* resource configuration	*/
+#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFF80000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=mip405-0"
+#define MTDPARTS_DEFAULT	"mtdparts=mip405-0:-(jffs2)"
+*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		0x4000	/* For AMCC 405GPr CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Logbuffer Configuration
+ */
+#undef CONFIG_LOGBUFFER 	/* supported but not enabled */
+/*-----------------------------------------------------------------------
+ * Bootcountlimit Configuration
+ */
+#undef CONFIG_BOOTCOUNT_LIMIT	/* supported but not enabled */
+
+/*-----------------------------------------------------------------------
+ * POST Configuration
+ */
+#if 0 /* enable this if POST is desired (is supported but not enabled) */
+#define CONFIG_POST		(CFG_POST_MEMORY	| \
+				 CFG_POST_CPU 		| \
+				 CFG_POST_RTC 		| \
+				 CFG_POST_I2C)
+
+#endif
+/*
+ * Init Memory Controller:
+ */
+#define FLASH_MAX_SIZE		0x00800000		/* 8MByte max */
+#define FLASH_BASE_PRELIM	0xFF800000  /* open the flash CS */
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+/* Peripheral Bus Mapping */
+#define PER_PLD_ADDR		0xF4000000 /* smallest window is 1MByte 0x10 0000*/
+#define PER_UART0_ADDR		0xF4100000 /* smallest window is 1MByte 0x10 0000*/
+#define PER_UART1_ADDR		0xF4200000 /* smallest window is 1MByte 0x10 0000*/
+
+#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
+#define CONFIG_PORT_ADDR 	PER_PLD_ADDR + 5
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in On Chip SRAM)
+ */
+#define CFG_TEMP_STACK_OCM      1
+#define CFG_OCM_DATA_ADDR	0xF0000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR 	/* inside of On Chip SRAM    */
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
+#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+/* reserve some memory for POST and BOOT limit info */
+#define CFG_INIT_SP_OFFSET	(CFG_GBL_DATA_OFFSET - 32)
+
+#ifdef  CONFIG_POST		/* reserve one word for POST Info */
+#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 4)
+#endif
+
+#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
+#define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 12)
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+
+/***********************************************************************
+ * External peripheral base address
+ ***********************************************************************/
+#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
+
+/***********************************************************************
+ * Last Stage Init
+ ***********************************************************************/
+#define CONFIG_LAST_STAGE_INIT
+/************************************************************
+ * Ethernet Stuff
+ ***********************************************************/
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
+#define CONFIG_PHY_RESET_DELAY	300	/* Intel LXT971A needs this */
+#define CONFIG_PHY_CMD_DELAY	40	/* Intel LXT971A needs this */
+/************************************************************
+ * RTC
+ ***********************************************************/
+#define CONFIG_RTC_MC146818
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/************************************************************
+ * IDE/ATA stuff
+ ************************************************************/
+#if defined(CONFIG_MIP405T)
+#define CFG_IDE_MAXBUS		1   /* MIP405T has only one IDE bus	*/
+#else
+#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#endif
+
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	CFG_ISA_IO_BASE_ADDRESS /* base address */
+#define CFG_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */
+#define CFG_ATA_IDE1_OFFSET	0x0170		/* ide1 offset */
+#define CFG_ATA_DATA_OFFSET	0		/* data reg offset	*/
+#define CFG_ATA_REG_OFFSET 	0		/* reg offset */
+#define CFG_ATA_ALT_OFFSET	0x200		/* alternate register offset */
+
+#undef	CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED	       /* no led for ide supported     */
+#define CONFIG_IDE_RESET       /* reset for ide supported...	*/
+#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
+#define CONFIG_SUPPORT_VFAT
+/************************************************************
+ * ATAPI support (experimental)
+ ************************************************************/
+#define CONFIG_ATAPI			/* enable ATAPI Support */
+
+/************************************************************
+ * DISK Partition support
+ ************************************************************/
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION /* Experimental */
+
+/************************************************************
+ * Disk-On-Chip configuration
+ ************************************************************/
+#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+#define CFG_DOC_SHORT_TIMEOUT
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+/************************************************************
+ * Keyboard support
+ ************************************************************/
+#undef CONFIG_ISA_KEYBOARD
+
+/************************************************************
+ * Video support
+ ************************************************************/
+#define CONFIG_VIDEO			/*To enable video controller support */
+#define CONFIG_VIDEO_CT69000
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#undef CONFIG_VIDEO_ONBOARD
+/************************************************************
+ * USB support EXPERIMENTAL
+ ************************************************************/
+#if !defined(CONFIG_MIP405T)
+#define CONFIG_USB_UHCI
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_USB_STORAGE
+
+/* Enable needed helper functions */
+#define CFG_DEVICE_DEREGISTER		/* needs device_deregister */
+#endif
+/************************************************************
+ * Debug support
+ ************************************************************/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/************************************************************
+ * support BZIP2 compression
+ ************************************************************/
+#define CONFIG_BZIP2		1
+
+/************************************************************
+ * Ident
+ ************************************************************/
+
+#define VERSION_TAG "released"
+#if !defined(CONFIG_MIP405T)
+#define CONFIG_ISO_STRING "MEV-10072-001"
+#else
+#define CONFIG_ISO_STRING "MEV-10082-001"
+#endif
+
+#if !defined(CONFIG_BOOT_PCI)
+#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
+#else
+#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
+#endif
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ML2.h b/include/configs/ML2.h
new file mode 100755
index 0000000..d8805ea
--- /dev/null
+++ b/include/configs/ML2.h
@@ -0,0 +1,262 @@
+/*
+ * ML2.h: ML2 specific config options
+ *
+ * Copyright 2002 Mind NV
+ *
+ * http://www.mind.be/
+ *
+ * Author : Peter De Schrijver (p2@mind.be)
+ *
+ * Derived from : other configuration header files in this tree
+ *
+ * This software may be used and distributed according to the terms of
+ * the GNU General Public License (GPL) version 2, incorporated herein by
+ * reference. Drivers based on or derived from this code fall under the GPL
+ * and must retain the authorship, copyright and this license notice. This
+ * file is not a complete program and may only be used when the entire
+ * program is licensed under the GPL.
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_ML2	1	/* ...on a ML2 board	*/
+
+
+#define CFG_ENV_IS_IN_FLASH     1
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#else
+#ifdef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_NVRAM
+#endif
+#endif
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#if 1
+#define CONFIG_BOOTCOMMAND	"bootm" /* autoboot command	*/
+#else
+#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
+#endif
+
+#define CONFIG_PREBOOT		"fsload 0x00100000 /boot/image"
+
+/* Size (bytes) of interrupt driven serial port buffer.
+ * Set to 0 to use polling instead of interrupts.
+ * Setting to 0 will also disable RTS/CTS handshaking.
+ */
+#if 0
+#define CONFIG_SERIAL_SOFTWARE_FIFO 4000
+#else
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#endif
+
+#if 0
+#define CONFIG_BOOTARGS		"root=/dev/nfs "                        \
+    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 "        \
+    "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
+#else
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 "			\
+   "console=ttyS0 console=tty"
+
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+
+#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL & \
+				     ~( CFG_CMD_NET | \
+					CFG_CMD_RTC | \
+					CFG_CMD_PCI | \
+					CFG_CMD_I2C   \
+				      ) ) | \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_KGDB	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_JFFS2	  )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SYS_CLK_FREQ 50000000
+
+#define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef  CFG_EXT_SERIAL_CLOCK           /* external serial clock */
+#undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
+
+#define CFG_BASE_BAUD       (3125000*16)
+#define CFG_NS16550_CLK CFG_BASE_BAUD
+#define CFG_DUART_CHAN		0
+#define CFG_NS16550_COM1	0xa0001003
+#define CFG_NS16550_COM2	0xa0011003
+#define CFG_NS16550_REG_SIZE -4
+#define CFG_NS16550 1
+#define CFG_INIT_CHAN1	 1
+#define CFG_INIT_CHAN2	 1
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x18000000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/* BEG ENVIRONNEMENT FLASH */
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_OFFSET		0x00050000 /* Offset of Environment Sector  */
+#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000	/* see README - env sector total size	*/
+#endif
+/* END ENVIRONNEMENT FLASH */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
+
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR	0xF0000500
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+#define CFG_INIT_RAM_ADDR       0x800000  /* inside of SDRAM                     */
+#define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS      0x50
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00080000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=ml2-0"
+#define MTDPARTS_DEFAULT	"mtdparts=ml2-0:-@512k(jffs2)"
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h
new file mode 100755
index 0000000..6ad2feb
--- /dev/null
+++ b/include/configs/MOUSSE.h
@@ -0,0 +1,329 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * James F. Dougherty (jfd@cs.stanford.edu)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * Configuration settings for the MOUSSE board.
+ * See also: http://www.vooha.com/
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X      1
+#define CONFIG_MPC8240      1
+#define CONFIG_MOUSSE       1
+#define CFG_ADDR_MAP_B      1
+#define CONFIG_CONS_INDEX   1
+#define CONFIG_BAUDRATE     9600
+#if 1
+#define CONFIG_BOOTCOMMAND  "tftp 100000 vmlinux.img;bootm"    /* autoboot command */
+#else
+#define CONFIG_BOOTCOMMAND  "bootm ffe10000"
+#endif
+#define CONFIG_BOOTARGS      "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
+#define CONFIG_BOOTDELAY     3
+#define CONFIG_COMMANDS      (CONFIG_CMD_DFL|CFG_CMD_ASKENV|CFG_CMD_DATE)
+#define CONFIG_ENV_OVERWRITE 1
+#define CONFIG_ETH_ADDR      "00:10:18:10:00:06"
+
+#define CONFIG_DOS_PARTITION  1 /* MSDOS bootable partitiion support */
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+#include <cmd_confdefs.h>
+#include "../board/mousse/mousse.h"
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef CFG_LONGHELP                /* undef to save memory     */
+#define CFG_PROMPT      "=>"  /* Monitor Command Prompt   */
+#define CFG_CBSIZE      256        /* Console I/O Buffer Size  */
+#define CFG_PBSIZE      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS     8           /* Max number of command args   */
+
+#define CFG_BARGSIZE    CFG_CBSIZE  /* Boot Argument Buffer Size    */
+#define CFG_LOAD_ADDR   0x00100000  /* Default load address         */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE      0x00000000
+
+#ifdef DEBUG
+#define CFG_MONITOR_BASE    CFG_SDRAM_BASE
+#else
+#define CFG_MONITOR_BASE    CFG_FLASH_BASE
+#endif
+
+#ifdef DEBUG
+#define CFG_MONITOR_LEN     (4 << 20)	/* lots of mem ... */
+#else
+#define CFG_MONITOR_LEN     (512 << 10)	/* 512K PLCC bootrom */
+#endif
+#define CFG_MALLOC_LEN      (2*(4096 << 10))    /* 2*4096kB for malloc()  */
+
+#define CFG_MEMTEST_START   0x00004000	/* memtest works on      */
+#define CFG_MEMTEST_END     0x02000000	/* 0 ... 32 MB in DRAM   */
+
+
+#define CFG_EUMB_ADDR       0xFC000000
+
+#define CFG_ISA_MEM         0xFD000000
+#define CFG_ISA_IO          0xFE000000
+
+#define CFG_FLASH_BASE      0xFFF00000
+#define CFG_FLASH_SIZE      ((uint)(512 * 1024))
+#define CFG_RESET_ADDRESS   0xFFF00100
+#define FLASH_BASE0_PRELIM  0xFFF00000  /* 512K PLCC FLASH/AM29F040*/
+#define FLASH_BASE0_SIZE    0x80000     /* 512K */
+#define FLASH_BASE1_PRELIM  0xFFE10000  /* AMD 29LV160DB
+					   1MB - 64K FLASH0 SEG =960K
+					   (size=0xf0000)*/
+
+#define CFG_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	1
+
+#define CFG_NS16550_CLK		18432000
+
+#define CFG_NS16550_COM1	0xFFE08080
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN
+#define CFG_INIT_RAM_END   0x2F00  /* End of used area in DPRAM  */
+#define CFG_GBL_DATA_SIZE  64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET  CFG_GBL_DATA_OFFSET
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
+#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2
+#define CFG_HZ               1000
+
+#define CFG_ETH_DEV_FN       0x00
+#define CFG_ETH_IOBASE       0x00104000
+
+
+	/* Bit-field values for MCCR1.
+	 */
+#define CFG_ROMNAL          8
+#define CFG_ROMFAL          8
+
+	/* Bit-field values for MCCR2.
+	 */
+#define CFG_REFINT          0xf5     /* Refresh interval               */
+
+	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+	 */
+#define CFG_BSTOPRE         0x79
+
+#ifdef INCLUDE_ECC
+#define USE_ECC				1
+#else /* INCLUDE_ECC */
+#define USE_ECC				0
+#endif /* INCLUDE_ECC */
+
+
+	/* Bit-field values for MCCR3.
+	 */
+#define CFG_REFREC          8       /* Refresh to activate interval   */
+#define CFG_RDLAT           (4+USE_ECC)   /* Data latancy from read command */
+
+	/* Bit-field values for MCCR4.
+	 */
+#define CFG_PRETOACT        3       /* Precharge to activate interval */
+#define CFG_ACTTOPRE        5       /* Activate to Precharge interval */
+#define CFG_SDMODE_CAS_LAT  3       /* SDMODE CAS latancy             */
+#define CFG_SDMODE_WRAP     0       /* SDMODE wrap type               */
+#define CFG_SDMODE_BURSTLEN 2       /* SDMODE Burst length            */
+#define CFG_ACTORW          2
+#define CFG_REGISTERD_TYPE_BUFFER (1-USE_ECC)
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+#define CFG_RAM_SIZE        0x04000000  /* 64MB */
+
+
+#define CFG_BANK0_START     0x00000000
+#define CFG_BANK0_END       (CFG_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE    1
+#define CFG_BANK1_START     0x3ff00000
+#define CFG_BANK1_END       0x3fffffff
+#define CFG_BANK1_ENABLE    0
+#define CFG_BANK2_START     0x3ff00000
+#define CFG_BANK2_END       0x3fffffff
+#define CFG_BANK2_ENABLE    0
+#define CFG_BANK3_START     0x3ff00000
+#define CFG_BANK3_END       0x3fffffff
+#define CFG_BANK3_ENABLE    0
+#define CFG_BANK4_START     0x3ff00000
+#define CFG_BANK4_END       0x3fffffff
+#define CFG_BANK4_ENABLE    0
+#define CFG_BANK5_START     0x3ff00000
+#define CFG_BANK5_END       0x3fffffff
+#define CFG_BANK5_ENABLE    0
+#define CFG_BANK6_START     0x3ff00000
+#define CFG_BANK6_END       0x3fffffff
+#define CFG_BANK6_ENABLE    0
+#define CFG_BANK7_START     0x3ff00000
+#define CFG_BANK7_END       0x3fffffff
+#define CFG_BANK7_ENABLE    0
+
+#define CFG_ODCR            0x7f
+
+
+#define CFG_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory
+				    see 8240 book for details*/
+#define PCI_MEM_SPACE1_START	0x80000000
+#define PCI_MEM_SPACE2_START	0xfd000000
+
+/* IBAT/DBAT Configuration */
+/* Ram: 64MB, starts at address-0, r/w instruction/data */
+#define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+#define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U      CFG_IBAT0U
+#define CFG_DBAT0L      CFG_IBAT0L
+
+/* MPLD/Port-X I/O Space : data and instruction read/write,  cache-inhibit */
+#define CFG_IBAT1U      (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
+#if 0
+#define CFG_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10  | BATL_MEMCOHERENCE |\
+			 BATL_WRITETHROUGH | BATL_CACHEINHIBIT)
+#else
+#define CFG_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
+#endif
+#define CFG_DBAT1U  	CFG_IBAT1U
+#define CFG_DBAT1L  	CFG_IBAT1L
+
+/* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
+#define CFG_IBAT2U  	(PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
+#define CFG_IBAT2L 	(PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
+#define CFG_DBAT2U      CFG_IBAT2U
+#define CFG_DBAT2L      CFG_IBAT2L
+
+/* PCI Memory region 2: PCI Devices in 0xFD space */
+#define CFG_IBAT3U  	(PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L 	(PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
+#define CFG_DBAT3U      CFG_IBAT3U
+#define CFG_DBAT3L      CFG_IBAT3L
+
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ       (8 << 20)   /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS     3       /* Max number of flash banks         */
+#define CFG_MAX_FLASH_SECT      64      /* Max number of sectors in one bank */
+
+#define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)   */
+#define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)   */
+
+#if 0
+#define	CFG_ENV_IS_IN_FLASH	    1
+#define CFG_ENV_OFFSET          0x8000  /* Offset of the Environment Sector	 */
+#define CFG_ENV_SIZE            0x4000  /* Size of the Environment Sector    */
+#else
+#define CFG_ENV_IS_IN_NVRAM          1
+#define CFG_ENV_ADDR            NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/
+#define CFG_ENV_OFFSET          CFG_ENV_ADDR
+#define CFG_ENV_SIZE            NV_U_BOOT_ENV_SIZE /* 2K */
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE  16
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM           0x02    /* Software reboot                  */
+
+/* Localizations */
+#if 0
+#define CONFIG_ETHADDR          0:0:0:0:1:d
+#define CONFIG_IPADDR           172.16.40.113
+#define CONFIG_SERVERIP         172.16.40.111
+#else
+#define CONFIG_ETHADDR          0:0:0:0:1:d
+#define CONFIG_IPADDR           209.128.93.138
+#define CONFIG_SERVERIP         209.128.93.133
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI			/* include pci support			*/
+#undef CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support 	*/
+
+#define CONFIG_TULIP
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
new file mode 100755
index 0000000..6195bca
--- /dev/null
+++ b/include/configs/MPC8260ADS.h
@@ -0,0 +1,509 @@
+/*
+ * (C) Copyright 2001
+ * Stuart Hughes <stuarth@lineo.com>
+ * This file is based on similar values for other boards found in other
+ * U-Boot config files, and some that I found in the mpc8260ads manual.
+ *
+ * Note: my board is a PILOT rev.
+ * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
+ *
+ * (C) Copyright 2003-2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
+ * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
+ * Ported to MPC8272ADS board.
+ *
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ * Added support for PCI bridge on MPC8272ADS
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260ADS	1	/* Motorola PQ2 ADS family board */
+
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/*
+ * Figure out if we are booting low via flash HRCW or high via the BCSR.
+ */
+#if (TEXT_BASE != 0xFFF00000)		/* Boot low (flash HRCW) */
+#   define CFG_LOWBOOT		1
+#endif
+
+/* ADS flavours */
+#define CFG_8260ADS		1	/* MPC8260ADS */
+#define CFG_8266ADS		2	/* MPC8266ADS */
+#define CFG_PQ2FADS		3	/* PQ2FADS-ZU or PQ2FADS-VR */
+#define CFG_8272ADS		4	/* MPC8272ADS */
+
+#ifndef CONFIG_ADSTYPE
+#define CONFIG_ADSTYPE		CFG_8260ADS
+#endif /* CONFIG_ADSTYPE */
+
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CONFIG_MPC8272		1
+#else
+#define CONFIG_MPC8260		1
+#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+/* allow serial and ethaddr to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else */
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC   */
+#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+
+#ifdef CONFIG_ETHER_ON_FCC
+
+#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
+
+#if   CONFIG_ETHER_INDEX == 1
+
+# define CFG_PHY_ADDR		0
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
+# define CFG_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+
+#elif CONFIG_ETHER_INDEX == 2
+
+#if CONFIG_ADSTYPE == CFG_8272ADS	/* RxCLK is CLK15, TxCLK is CLK16 */
+# define CFG_PHY_ADDR		3
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
+#else					/* RxCLK is CLK13, TxCLK is CLK14 */
+# define CFG_PHY_ADDR		0
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+
+#endif	/* CONFIG_ETHER_INDEX */
+
+#define CFG_CPMFCR_RAMTYPE	0		/* BDs and buffers on 60x bus */
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)  /* Full duplex */
+
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT	2		/* Port C */
+
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CFG_MDIO_PIN	0x00002000	/* PC18 */
+#define CFG_MDC_PIN	0x00001000	/* PC19 */
+#else
+#define CFG_MDIO_PIN	0x00400000	/* PC9	*/
+#define CFG_MDC_PIN	0x00200000	/* PC10 */
+#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+
+#define MDIO_ACTIVE	(iop->pdir |=  CFG_MDIO_PIN)
+#define MDIO_TRISTATE	(iop->pdir &= ~CFG_MDIO_PIN)
+#define MDIO_READ	((iop->pdat &  CFG_MDIO_PIN) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  CFG_MDIO_PIN; \
+			else	iop->pdat &= ~CFG_MDIO_PIN
+
+#define MDC(bit)	if(bit) iop->pdat |=  CFG_MDC_PIN; \
+			else	iop->pdat &= ~CFG_MDC_PIN
+
+#define MIIDELAY	udelay(1)
+
+#endif /* CONFIG_ETHER_ON_FCC */
+
+#if CONFIG_ADSTYPE >= CFG_PQ2FADS
+#undef CONFIG_SPD_EEPROM	/* On new boards, SDRAM is soldered */
+#else
+#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
+#define CONFIG_SPD_ADDR		0x50
+#endif
+#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
+
+/*PCI*/
+#ifdef CONFIG_MPC8272
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_BOOTDELAY 0
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+#ifndef CONFIG_SDRAM_PBI
+#define CONFIG_SDRAM_PBI	0 /* By default, use bank-based interleaving */
+#endif
+
+#ifndef CONFIG_8260_CLKIN
+#if CONFIG_ADSTYPE >= CFG_PQ2FADS
+#define CONFIG_8260_CLKIN	100000000	/* in Hz */
+#else
+#define CONFIG_8260_CLKIN	66000000	/* in Hz */
+#endif
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_EXCLUDE		CFG_CMD_BEDBUG	| \
+				CFG_CMD_BMP	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DISPLAY | \
+				CFG_CMD_DOC	| \
+				CFG_CMD_DTT	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_EXT2	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_FDC	| \
+				CFG_CMD_FDOS	| \
+				CFG_CMD_HWFLOW	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_KGDB	| \
+				CFG_CMD_MMC	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_PCMCIA	| \
+				CFG_CMD_REISER	| \
+				CFG_CMD_SCSI	| \
+				CFG_CMD_SPI	| \
+				CFG_CMD_SNTP	| \
+				CFG_CMD_UNIVERSE | \
+				CFG_CMD_USB	| \
+				CFG_CMD_VFD	| \
+				CFG_CMD_XIMG
+
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
+			         CFG_CMD_SDRAM	| \
+				 CFG_CMD_I2C	| \
+				 CFG_EXCLUDE	) )
+#elif CONFIG_ADSTYPE >= CFG_PQ2FADS
+#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
+				 CFG_CMD_SDRAM	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_PCI	| \
+				 CFG_EXCLUDE	) )
+#else
+#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
+				 CMD_CFG_PCI 	| \
+				 CFG_EXCLUDE 	) )
+#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND	"bootm fff80000"	/* autoboot command */
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock2"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
+#undef	CONFIG_WATCHDOG /* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE	256			/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS	16			/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x400000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_FLASH_BASE		0xff800000
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
+#define CFG_FLASH_SIZE		8
+#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
+#define CFG_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
+#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+
+/*
+ * JFFS2 partitions
+ *
+ * Note: fake mtd_id used, no linux mtd map file
+ */
+#define MTDIDS_DEFAULT		"nor0=mpc8260ads-0"
+#define MTDPARTS_DEFAULT	"mtdparts=mpc8260ads-0:-@1m(jffs2)"
+#define CFG_JFFS2_SORT_FRAGMENTS
+
+/* this is stuff came out of the Motorola docs */
+#ifndef CFG_LOWBOOT
+#define CFG_DEFAULT_IMMR	0x0F010000
+#endif
+
+#define CFG_IMMR		0xF0000000
+#define CFG_BCSR		0xF4500000
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CFG_PCI_INT		0xF8200000
+#endif
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_LSDRAM_BASE		0xFD000000
+
+#define RS232EN_1		0x02000002
+#define RS232EN_2		0x01000001
+#define FETHIEN1		0x08000008
+#define FETH1_RST		0x04000004
+#define FETHIEN2		0x10000000
+#define FETH2_RST		0x08000000
+#define BCSR_PCI_MODE		0x01000000
+
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#ifdef CFG_LOWBOOT
+/* PQ2FADS flash HRCW = 0x0EB4B645 */
+#define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )			    |\
+			    ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 )    |\
+			    ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
+			    ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )	     \
+			)
+#else
+/* PQ2FADS BCSR HRCW = 0x0CB23645 */
+#define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )			    |\
+			    ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
+			    ( HRCW_BMS | HRCW_APPC10 )			    |\
+			    ( HRCW_MODCK_H0101 )			     \
+			)
+#endif
+/* no slaves */
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
+
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM	0x02	/* Software reboot	     */
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#ifdef CONFIG_BZIP2
+#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#else
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()	*/
+#endif /* CONFIG_BZIP2 */
+
+#ifndef CFG_RAMBOOT
+#  define CFG_ENV_IS_IN_FLASH	1
+#  define CFG_ENV_SECT_SIZE	0x40000
+#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
+#else
+#  define CFG_ENV_IS_IN_NVRAM	1
+#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#  define CFG_ENV_SIZE		0x200
+#endif /* CFG_RAMBOOT */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )
+
+#define CFG_HID2		0
+
+#define CFG_SYPCR		0xFFFFFFC3
+#define CFG_BCR			0x100C0000
+#define CFG_SIUMCR		0x0A200000
+#define CFG_SCCR		SCCR_DFBRG01
+#define CFG_BR0_PRELIM		CFG_FLASH_BASE | 0x00001801
+#define CFG_OR0_PRELIM		0xFF800876
+#define CFG_BR1_PRELIM		CFG_BCSR | 0x00001801
+#define CFG_OR1_PRELIM		0xFFFF8010
+
+/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
+
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CFG_BR3_PRELIM	(CFG_PCI_INT | 0x1801)	/* PCI interrupt controller */
+#define CFG_OR3_PRELIM	0xFFFF8010
+#endif
+
+#define CFG_RMR			RMR_CSRE
+#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CFG_RCCR		0
+
+#if (CONFIG_ADSTYPE == CFG_8266ADS) || (CONFIG_ADSTYPE == CFG_8272ADS)
+#undef CFG_LSDRAM_BASE		/* No local bus SDRAM on these boards */
+#endif /* CONFIG_ADSTYPE == CFG_8266ADS */
+
+#if CONFIG_ADSTYPE == CFG_PQ2FADS
+#define CFG_OR2			0xFE002EC0
+#define CFG_PSDMR		0x824B36A3
+#define CFG_PSRT		0x13
+#define CFG_LSDMR		0x828737A3
+#define CFG_LSRT		0x13
+#define CFG_MPTPR		0x2800
+#elif CONFIG_ADSTYPE == CFG_8272ADS
+#define CFG_OR2			0xFC002CC0
+#define CFG_PSDMR		0x834E24A3
+#define CFG_PSRT		0x13
+#define CFG_MPTPR		0x2800
+#else
+#define CFG_OR2			0xFF000CA0
+#define CFG_PSDMR		0x016EB452
+#define CFG_PSRT		0x21
+#define CFG_LSDMR		0x0086A522
+#define CFG_LSRT		0x21
+#define CFG_MPTPR		0x1900
+#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
+
+#define CFG_RESET_ADDRESS	0x04400000
+
+#if CONFIG_ADSTYPE == CFG_8272ADS
+
+/* PCI Memory map (if different from default map */
+#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
+#define CFG_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
+#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+				 PICMR_PREFETCH_EN)
+
+/*
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
+ * these windows.
+ */
+
+/*
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
+#define CFG_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
+#define	CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CFG_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
+#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/*
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
+#define CFG_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
+#define CFG_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
+#define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
+#define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
+
+/*
+ * Master window that allows the CPU to access PCI IO space.
+ * This window will be setup with the first set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
+#define CFG_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
+#define CFG_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
+#define CFG_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
+#define CFG_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
+
+
+/* PCIBR0 - for PCI IO*/
+#define CFG_PCI_MSTR0_LOCAL		CFG_PCI_MSTR_IO_LOCAL		/* Local base */
+#define CFG_PCIMSK0_MASK		~(CFG_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
+/* PCIBR1 - prefetch and non-prefetch regions joined together */
+#define CFG_PCI_MSTR1_LOCAL		CFG_PCI_MSTR_MEM_LOCAL
+#define CFG_PCIMSK1_MASK		~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
+
+#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
+
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CONFIG_HAS_ETH1
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
new file mode 100755
index 0000000..4953b70
--- /dev/null
+++ b/include/configs/MPC8266ADS.h
@@ -0,0 +1,594 @@
+/*
+ * (C) Copyright 2001
+ * Stuart Hughes <stuarth@lineo.com>
+ * This file is based on similar values for other boards found in other
+ * U-Boot config files, and some that I found in the mpc8260ads manual.
+ *
+ * Note: my board is a PILOT rev.
+ * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
+ */
+
+/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+   !!								      !!
+   !!  This configuration requires JP3 to be in position 1-2 to work  !!
+   !!  To make it work for the default, the TEXT_BASE define in	      !!
+   !!  board/mpc8266ads/config.mk must be changed from 0xfe000000 to  !!
+   !!  0xfff00000						      !!
+   !!  The CFG_HRCW_MASTER define below must also be changed to match !!
+   !!								      !!
+   !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
+#define CONFIG_MPC8266ADS	1	/* ...on motorola ADS board	*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+/* allow serial and ethaddr to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else */
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC   */
+#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX	2	/* which channel for ether  */
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+/*
+ * Port pins used for bit-banged MII communictions (if applicable).
+ */
+#define MDIO_PORT	2	/* Port C */
+#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
+#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
+			else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
+			else	iop->pdat &= ~0x00200000
+
+#define MIIDELAY	udelay(1)
+
+#if (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Half duplex
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif	/* CONFIG_ETHER_INDEX */
+
+/* other options */
+#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+
+/* PCI */
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_BOOTDELAY 0
+#undef CONFIG_PCI_SCAN_SHOW
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS	0x50
+
+
+#define CONFIG_8260_CLKIN	66000000	/* in Hz */
+#define CONFIG_BAUDRATE		115200
+
+
+#define CONFIG_COMMANDS	      ( CFG_CMD_ALL & ~( \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_BMP	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DISPLAY | \
+				CFG_CMD_DOC	| \
+				CFG_CMD_DTT	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_EXT2	| \
+				CFG_CMD_FDC	| \
+				CFG_CMD_FDOS	| \
+				CFG_CMD_HWFLOW	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_KGDB	| \
+				CFG_CMD_MMC	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_PCMCIA	| \
+				CFG_CMD_REISER	| \
+				CFG_CMD_SCSI	| \
+				CFG_CMD_SPI	| \
+				CFG_CMD_SNTP	| \
+				CFG_CMD_VFD	| \
+				CFG_CMD_UNIVERSE | \
+				CFG_CMD_USB	| \
+				CFG_CMD_XIMG	) )
+
+/* Define a command string that is automatically executed when no character
+ * is read on the console interface withing "Boot Delay" after reset.
+ */
+#undef	CONFIG_BOOT_ROOT_INITRD		/* Use ram disk for the root file system */
+#define CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
+
+#ifdef CONFIG_BOOT_ROOT_INITRD
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/ram0 rw " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_INITRD */
+
+#ifdef CONFIG_BOOT_ROOT_NFS
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_NFS */
+
+/* Add support for a few extra bootp options like:
+ *	- File size
+ *	- DNS
+ */
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE | \
+				 CONFIG_BOOTP_DNS)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE	256			/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS	16			/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */
+					/* for versions < 2.4.5-pre5	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_FLASH_BASE		0xFE000000
+#define FLASH_BASE		0xFE000000
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
+#define CFG_FLASH_SIZE		8
+#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
+#define CFG_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
+
+#undef	CFG_FLASH_CHECKSUM
+
+/* this is stuff came out of the Motorola docs */
+/* Only change this if you also change the Hardware configuration Word */
+#define CFG_DEFAULT_IMMR	0x0F010000
+
+/* Set IMMR to 0xF0000000 or above to boot Linux  */
+#define CFG_IMMR		0xF0000000
+#define CFG_BCSR		0xF8000000
+#define CFG_PCI_INT		0xF8200000	/* PCI interrupt controller */
+
+/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
+ */
+/*#define CONFIG_VERY_BIG_RAM	1*/
+
+/* What should be the base address of SDRAM DIMM and how big is
+ * it (in Mbytes)?  This will normally auto-configure via the SPD.
+*/
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_SDRAM_SIZE 16
+
+#define SDRAM_SPD_ADDR 0x50
+
+
+/*-----------------------------------------------------------------------
+ * BR2,BR3 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR2,OR3 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 2,3 - SDRAM DIMM
+ */
+
+/* The BR2 is configured as follows:
+ *
+ *     - Base address of 0x00000000
+ *     - 64 bit port size (60x bus only)
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - SDRAM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR2_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+#define CFG_BR3_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+/* With a 64 MB DIMM, the OR2 is configured as follows:
+ *
+ *     - 64 MB
+ *     - 4 internal banks per device
+ *     - Row start address bit is A8 with PSDMR[PBI] = 0
+ *     - 12 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+#if (CFG_SDRAM_SIZE == 64)
+#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM_SIZE)	|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A8		|\
+			 ORxS_NUMR_12)
+#elif (CFG_SDRAM_SIZE == 16)
+#define CFG_OR2_PRELIM	(0xFF000C80)
+#else
+#error "INVALID SDRAM CONFIGURATION"
+#endif
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x Bus SDRAM Mode Register
+ *     Ref: Section 10.3.3 on page 10-21
+ *-----------------------------------------------------------------------
+ */
+
+#if (CFG_SDRAM_SIZE == 64)
+/* With a 64 MB DIMM, the PSDMR is configured as follows:
+ *
+ *     - Bank Based Interleaving,
+ *     - Refresh Enable,
+ *     - Address Multiplexing where A5 is output on A14 pin
+ *	 (A6 on A15, and so on),
+ *     - use address pins A14-A16 as bank select,
+ *     - A9 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *	 is 3 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *	 2 clocks,
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - CAS Latency is 2.
+ */
+#define CFG_PSDMR	(PSDMR_RFEN	      |\
+			 PSDMR_SDAM_A14_IS_A5 |\
+			 PSDMR_BSMA_A14_A16   |\
+			 PSDMR_SDA10_PBI0_A9  |\
+			 PSDMR_RFRC_7_CLK     |\
+			 PSDMR_PRETOACT_3W    |\
+			 PSDMR_ACTTORW_2W     |\
+			 PSDMR_LDOTOPRE_1C    |\
+			 PSDMR_WRC_1C	      |\
+			 PSDMR_CL_2)
+#elif (CFG_SDRAM_SIZE == 16)
+/* With a 16 MB DIMM, the PSDMR is configured as follows:
+ *
+ *   configuration parameters found in Motorola documentation
+ */
+#define CFG_PSDMR	(0x016EB452)
+#else
+#error "INVALID SDRAM CONFIGURATION"
+#endif
+
+
+#define RS232EN_1		0x02000002
+#define RS232EN_2		0x01000001
+#define FETHIEN			0x08000008
+#define FETH_RST		0x04000004
+
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2)  */
+/* 0x0EB2B645 */
+#define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP )				|\
+			 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 )		|\
+			 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 )	|\
+			 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )			\
+			)
+
+/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3)  */
+/* #define CFG_HRCW_MASTER 0x0cb23645 */
+
+/* This value should actually be situated in the first 256 bytes of the FLASH
+	which on the standard MPC8266ADS board is at address 0xFF800000
+	The linker script places it at 0xFFF00000 instead.
+
+	It still works, however, as long as the ADS board jumper JP3 is set to
+	position 2-3 so the board is using the BCSR as Hardware Configuration Word
+
+	If you want to use the one defined here instead, ust copy the first 256 bytes from
+	0xfff00000 to 0xff800000  (for 8MB flash)
+
+	- Rune
+
+*/
+
+/* no slaves */
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
+
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM	0x02	/* Software reboot	     */
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#ifndef CFG_RAMBOOT
+#  define CFG_ENV_IS_IN_FLASH	1
+#    define CFG_ENV_ADDR	(CFG_MONITOR_BASE + 0x40000)
+#    define CFG_ENV_SECT_SIZE	0x40000
+#else
+#  define CFG_ENV_IS_IN_NVRAM	1
+#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#  define CFG_ENV_SIZE		0x200
+#endif /* CFG_RAMBOOT */
+
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+/*#define CFG_HID0_INIT		0 */
+#define CFG_HID0_INIT	(HID0_ICE  |\
+			 HID0_DCE  |\
+			 HID0_ICFI |\
+			 HID0_DCI  |\
+			 HID0_IFEM |\
+			 HID0_ABE)
+
+#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )
+
+#define CFG_HID2		0
+
+#define CFG_SYPCR		0xFFFFFFC3
+#define CFG_BCR			0x004C0000
+#define CFG_SIUMCR		0x4E64C000
+#define CFG_SCCR		0x00000000
+
+/*	local bus memory map
+ *
+ *	0x00000000-0x03FFFFFF	 64MB	SDRAM
+ *	0x80000000-0x9FFFFFFF	512MB	outbound prefetchable PCI memory window
+ *	0xA0000000-0xBFFFFFFF	512MB	outbound non-prefetchable PCI memory window
+ *	0xF0000000-0xF001FFFF	128KB	MPC8266 internal memory
+ *	0xF4000000-0xF7FFFFFF	 64MB	outbound PCI I/O window
+ *	0xF8000000-0xF8007FFF	 32KB	BCSR
+ *	0xF8100000-0xF8107FFF	 32KB	ATM UNI
+ *	0xF8200000-0xF8207FFF	 32KB	PCI interrupt controller
+ *	0xF8300000-0xF8307FFF	 32KB	EEPROM
+ *	0xFE000000-0xFFFFFFFF	 32MB	flash
+ */
+#define CFG_BR0_PRELIM	0xFE001801		/* flash */
+#define CFG_OR0_PRELIM	0xFE000836
+#define CFG_BR1_PRELIM	(CFG_BCSR | 0x1801)	/* BCSR */
+#define CFG_OR1_PRELIM	0xFFFF8010
+#define CFG_BR4_PRELIM	0xF8300801		/* EEPROM */
+#define CFG_OR4_PRELIM	0xFFFF8846
+#define CFG_BR5_PRELIM	0xF8100801		/* PM5350 ATM UNI */
+#define CFG_OR5_PRELIM	0xFFFF8E36
+#define CFG_BR8_PRELIM	(CFG_PCI_INT | 0x1801)	/* PCI interrupt controller */
+#define CFG_OR8_PRELIM	0xFFFF8010
+
+#define CFG_RMR			0x0001
+#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CFG_RCCR		0
+#define CFG_MPTPR		0x00001900
+#define CFG_PSRT		0x00000021
+
+/* This address must not exist */
+#define CFG_RESET_ADDRESS	0xFCFFFF00
+
+/* PCI Memory map (if different from default map */
+#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE		/* Local base */
+#define CFG_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
+#define CFG_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+				 PICMR_PREFETCH_EN)
+
+/*
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
+ * these windows.
+ */
+
+/* PCIBR0 */
+#define CFG_PCI_MSTR0_LOCAL		0x80000000		/* Local base */
+#define CFG_PCIMSK0_MASK		PCIMSK_1GB		/* Size of window */
+/* PCIBR1 */
+#define CFG_PCI_MSTR1_LOCAL		0xF4000000		/* Local base */
+#define CFG_PCIMSK1_MASK		PCIMSK_64MB		/* Size of window */
+
+/*
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the first set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEM_LOCAL	0x80000000			/* Local base */
+#define CFG_PCI_MSTR_MEM_BUS	0x80000000			/* PCI base   */
+#define CFG_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CFG_PCI_MSTR_MEM_SIZE	0x20000000			/* 512MB */
+#define CFG_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/*
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEMIO_LOCAL    0xA0000000			/* Local base */
+#define CFG_PCI_MSTR_MEMIO_BUS	    0xA0000000			/* PCI base   */
+#define CFG_CPU_PCI_MEMIO_START	    PCI_MSTR_MEMIO_LOCAL
+#define CFG_PCI_MSTR_MEMIO_SIZE	    0x20000000			/* 512MB */
+#define CFG_POCMR1_MASK_ATTRIB	    (POCMR_MASK_512MB | POCMR_ENABLE)
+
+/*
+ * Master window that allows the CPU to access PCI IO space.
+ * This window will be setup with the third set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_IO_LOCAL	    0xF4000000			/* Local base */
+#define CFG_PCI_MSTR_IO_BUS	    0xF4000000			/* PCI base   */
+#define CFG_CPU_PCI_IO_START	    PCI_MSTR_IO_LOCAL
+#define CFG_PCI_MSTR_IO_SIZE	    0x04000000			/* 64MB */
+#define CFG_POCMR2_MASK_ATTRIB	    (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		""
+#define MTDPARTS_DEFAULT	""
+*/
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h
new file mode 100755
index 0000000..d6d2fab
--- /dev/null
+++ b/include/configs/MPC8349ADS.h
@@ -0,0 +1,584 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8349ads board configuration file
+ *
+ * Please refer to doc/README.mpc83xxads for more info.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+#define CONFIG_MII
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC83XX		1	/* MPC83XX family */
+#define CONFIG_MPC8349		1	/* MPC8349 specific */
+#define CONFIG_MPC8349ADS	1	/* MPC8349ADS board specific */
+
+/* FIXME: Real PCI support will come in a follow-up update. */
+#undef CONFIG_PCI
+
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+
+#define PCI_66M
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#else
+#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef PCI_66M
+#define CONFIG_SYS_CLK_FREQ	66000000
+#else
+#define CONFIG_SYS_CLK_FREQ	33000000
+#endif
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_pre_init */
+
+#define CFG_IMMRBAR		0xE0000000
+
+#undef CFG_DRAM_TEST                   /* memory test, takes time */
+#define CFG_MEMTEST_START       0x00000000      /* memtest region */
+#define CFG_MEMTEST_END         0x00100000
+
+/*
+ * DDR Setup
+ */
+
+#define CFG_DDR_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#undef  CONFIG_DDR_2T_TIMING
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+
+#if defined(CONFIG_SPD_EEPROM)
+	/*
+	 * Determine DDR configuration from I2C interface.
+	 */
+	#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#else
+	/*
+	 * Manually set up DDR parameters
+	 */
+	#define CFG_DDR_SIZE	    256		/* Mb */
+	#define CFG_DDR_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
+	#define CFG_DDR_TIMING_1	0x37344321
+	#define CFG_DDR_TIMING_2	0x00000800  /* P9-45,may need tuning */
+	#define CFG_DDR_CONTROL 	0xc2000000  /* unbuffered,no DYN_PWR */
+	#define CFG_DDR_MODE    	0x00000062  /* DLL,normal,seq,4/2.5 */
+	#define CFG_DDR_INTERVAL	0x05200100  /* autocharge,no open page */
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI			/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CFG_FLASH_SIZE		8		/* FLASH size in MB */
+/* #define CFG_FLASH_USE_BUFFER_WRITE */
+
+#define CFG_BR0_PRELIM	(CFG_FLASH_BASE |	/* Flash Base address */ \
+			(2 << BR_PS_SHIFT) |	/* 32 bit port size */	 \
+			BR_V)			/* valid */
+#define CFG_OR0_PRELIM		0xff806ff7	/* 16Mb Flash size*/
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE	/* Window base at flash base */
+#define CFG_LBLAWAR0_PRELIM  0x80000016		/* 16Mb window size */
+
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MID_FLASH_JUMP      0x7F000000
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+/*
+ * BCSR register on local bus 32KB, 8-bit wide for ADS config reg
+ */
+#define CFG_BCSR             0xF8000000
+#define CFG_LBLAWBAR1_PRELIM CFG_BCSR	/* Access window base at BCSR base */
+#define CFG_LBLAWAR1_PRELIM  0x8000000E		/* Access window size 32K */
+#define CFG_BR1_PRELIM	  (CFG_BCSR|0x00000801)	/* Port-size=8bit, MSEL=GPCM */
+#define CFG_OR1_PRELIM		0xFFFFE8f0	/* length 32K */
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR	0xe4010000   /* Initial RAM address */
+#define CFG_INIT_RAM_END    	0x1000	     /* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE  	0x100     /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ *    LCRR:  DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
+#define CFG_LBC_LBCR	0x00000000
+
+#define CFG_LB_SDRAM	/* if board has SRDAM on local bus */
+
+#ifdef CFG_LB_SDRAM
+/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM		0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/
+#define CFG_LBLAWBAR2_PRELIM	0xF0000000
+#define CFG_LBLAWAR2_PRELIM	0x80000019 /*64M*/
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM	0xfc006901
+
+#define CFG_LBC_LSRT	0x32000000    /* LB sdram refresh timer, about 6us */
+#define CFG_LBC_MRTPR	0x20000000    /* LB refresh timer prescal, 266MHz/32*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR8	(5 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT6	(5 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC3	(3 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
+#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON    ( CFG_LBC_LSDMR_RFEN            \
+				| CFG_LBC_LSDMR_BSMA1516	\
+				| CFG_LBC_LSDMR_RFCR8		\
+				| CFG_LBC_LSDMR_PRETOACT6	\
+				| CFG_LBC_LSDMR_ACTTORW3	\
+				| CFG_LBC_LSDMR_BL8		\
+				| CFG_LBC_LSDMR_WRC3		\
+				| CFG_LBC_LSDMR_CL3		\
+				)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_NORMAL)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_IMMRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_IMMRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+#define CFG_I2C_OFFSET      0x3000
+#define CFG_I2C2_OFFSET      0x3100
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
+
+/* IO Configuration */
+#define CFG_IO_CONF (\
+	IO_CONF_UART |\
+	IO_CONF_TSEC1 |\
+	IO_CONF_IRQ0 |\
+	IO_CONF_IRQ1 |\
+	IO_CONF_IRQ2 |\
+	IO_CONF_IRQ3 |\
+	IO_CONF_IRQ4 |\
+	IO_CONF_IRQ5 |\
+	IO_CONF_IRQ6 |\
+	IO_CONF_IRQ7 )
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xe2000000
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#define CFG_PCI2_MEM_BASE	0xA0000000
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI2_IO_BASE	0x00000000
+#define CFG_PCI2_IO_PHYS	0xe3000000
+#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+#if defined(CONFIG_PCI)
+
+#define PCI_ALL_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	0xFIXME
+	#define PCI_ENET0_MEMADDR	0xFIXME
+	#define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_GMII		1	/* MII PHY management */
+#define CONFIG_MPC83XX_TSEC1	1
+#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC83XX_TSEC2	1
+#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+	#define CFG_ENV_SIZE		0x2000
+#else
+	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_PCI		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+#else
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PCI		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C       \
+				| CFG_CMD_MII       \
+				)
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#if defined(PCI_64BIT)
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_64_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#else
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#endif
+
+#define CFG_HID0_INIT 0x000000000
+
+#define CFG_HID0_FINAL CFG_HID0_INIT
+
+/* #define CFG_HID0_FINAL		(\
+	HID0_ENABLE_INSTRUCTION_CACHE |\
+	HID0_ENABLE_M_BIT |\
+	HID0_ENABLE_ADDRESS_BROADCAST ) */
+
+#define CFG_HID2 0x000000000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR   00:04:9f:11:22:33
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:7D:01
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME	 unknown
+#define CONFIG_ROOTPATH	 /nfsroot
+#define CONFIG_BOOTFILE	 your.uImage
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	 115200
+
+
+#define	CONFIG_EXTRA_ENV_SETTINGS			\
+	"netdev=eth0\0"					\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=400000\0"				\
+	"ramdiskfile=ramfs.83xx\0"
+
+#define CONFIG_NFSBOOTCOMMAND				\
+	"setenv bootargs root=/dev/nfs rw "		\
+	"nfsroot=$serverip:$rootpath "			\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
new file mode 100755
index 0000000..131c832
--- /dev/null
+++ b/include/configs/MPC8540ADS.h
@@ -0,0 +1,520 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8540ads board configuration file
+ *
+ * Please refer to doc/README.mpc85xx for more info.
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
+#define CONFIG_MPC8540		1	/* MPC8540 specific */
+#define CONFIG_MPC8540ADS	1	/* MPC8540ADS board specific */
+
+#ifndef CONFIG_HAS_FEC
+#define CONFIG_HAS_FEC		1	/* 8540 has FEC */
+#endif
+
+#define CONFIG_PCI
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ *    33000000
+ *    66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz.  In any event, this value
+ * must match the settings of some switches.  Details can be found
+ * in the README.mpc85xxads.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	33000000
+#endif
+
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00200000	/* memtest region */
+#define CFG_MEMTEST_END		0x00400000
+
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#if defined(CONFIG_SPD_EEPROM)
+    /*
+     * Determine DDR configuration from I2C interface.
+     */
+    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+#else
+    /*
+     * Manually set up DDR parameters
+     */
+    #define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
+    #define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+    #define CFG_DDR_CS0_CONFIG	0x80000002
+    #define CFG_DDR_TIMING_1	0x37344321
+    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+    #define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
+    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
+    #define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
+#endif
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 16M */
+#define CFG_BR0_PRELIM		0xff001801	/* port size 32bit */
+
+#define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM		0xf0001861
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM		0xfc006901
+
+#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
+#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
+#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_BSMA1516	\
+				| CFG_LBC_LSDMR_RFCR5		\
+				| CFG_LBC_LSDMR_PRETOACT3	\
+				| CFG_LBC_LSDMR_ACTTORW3	\
+				| CFG_LBC_LSDMR_BL8		\
+				| CFG_LBC_LSDMR_WRC2		\
+				| CFG_LBC_LSDMR_CL3		\
+				| CFG_LBC_LSDMR_RFEN		\
+				)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_NORMAL)
+
+
+/*
+ * 32KB, 8-bit wide for ADS config reg
+ */
+#define CFG_BR4_PRELIM          0xf8000801
+#define CFG_OR4_PRELIM		0xffffe1f1
+#define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+
+/* RapidIO MMU */
+#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
+#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0xe2000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR	0xe0000000
+    #define PCI_ENET0_MEMADDR	0xe0000000
+    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+
+#if CONFIG_HAS_FEC
+#define CONFIG_MPC85XX_FEC	1
+#define CONFIG_MPC85XX_FEC_NAME		"FEC"
+#define FEC_PHY_ADDR		3
+#define FEC_PHYIDX		0
+#endif
+
+/* Options are: TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+  #define CFG_ENV_IS_IN_FLASH	1
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+  #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+  #define CFG_ENV_SIZE		0x2000
+#else
+  #define CFG_NO_FLASH		1	/* Flash is not usable now */
+  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_PCI		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+  #else
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+  #endif
+#else
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PCI		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+  #else
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+  #endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		/nfsroot
+#define CONFIG_BOOTFILE		your.uImage
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS0\0"                                                 \
+   "ramdiskaddr=400000\0"						\
+   "ramdiskfile=your.ramdisk.u-boot\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h
new file mode 100755
index 0000000..1af9231
--- /dev/null
+++ b/include/configs/MPC8540EVAL.h
@@ -0,0 +1,347 @@
+/*
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Modified by Lunsheng Wang, lunsheng@sohu.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* mpc8540eval board configuration file */
+/* please refer to doc/README.mpc85xxads for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	    /* BOOKE 			*/
+#define CONFIG_E500		1	    /* BOOKE e500 family	*/
+#define CONFIG_MPC85xx		1	    /* MPC8540/MPC8560		*/
+#define CONFIG_MPC8540		1	    /* MPC8540 specific	        */
+#define CONFIG_MPC8540EVAL	1	    /* MPC8540EVAL board specific */
+
+#undef  CONFIG_PCI	         	    /* pci ethernet support	*/
+#define CONFIG_TSEC_ENET 		    /* tsec ethernet support  */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM                   /* Use SPD EEPROM for DDR setup */
+#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
+#define CONFIG_DDR_DLL                      /* possible DLL fix needed */
+
+/* Using Localbus SDRAM to emulate flash before we can program the flash,
+ * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
+ * Not availabe for EVAL board
+ */
+#undef CONFIG_RAM_AS_FLASH
+
+/* sysclk for MPC8540EVAL */
+#if defined(CONFIG_SYSCLK_66M)
+	/*
+	 * the oscillator on board is 66Mhz
+	 * can also get 66M clock from external PCI
+	 */
+	#define CONFIG_SYS_CLK_FREQ   66000000
+#else
+	#define CONFIG_SYS_CLK_FREQ   33000000   /* most pci cards are 33Mhz */
+#endif
+
+/* below can be toggled for performance analysis. otherwise use default */
+#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
+#undef  CONFIG_BTB			    /* toggle branch predition */
+#undef  CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
+
+#define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/
+
+#undef	CFG_DRAM_TEST			    /* memory test, takes time  */
+#define CFG_MEMTEST_START	0x00200000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00400000
+
+#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
+#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
+#endif
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR 	*/
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CFG_SDRAM_SIZE		256             /* DDR is now 256MB     */
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
+#else
+#define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
+#endif
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 0MB	*/
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_FLASH_BASE          0xf8000000      /* start of FLASH  16M  */
+#define CFG_BR0_PRELIM          0xf8001801      /* port size 32bit */
+#else /* Boot from real Flash */
+#define CFG_FLASH_BASE		0xff800000	/* start of FLASH 8M    */
+#define CFG_BR0_PRELIM		0xff801001	/* port size 16bit	*/
+#endif
+
+#define	CFG_OR0_PRELIM		0xff806f67	/* 8MB Flash		*/
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
+#define CFG_MAX_FLASH_SECT	64		/* sectors per device   */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)*/
+#define CFG_FLASH_CFI		1
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+/* Here some DDR setting should be added */
+
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/* local bus definitions */
+#define CFG_BR2_PRELIM		0xf0001861	/* 64MB localbus SDRAM  */
+#define CFG_OR2_PRELIM		0xfc006901
+#define CFG_LBC_LCRR		0x00030004	/* local bus freq divider*/
+#define CFG_LBC_LBCR		0x00000000
+#define CFG_LBC_LSRT		0x20000000
+#define CFG_LBC_MRTPR		0x20000000
+#define CFG_LBC_LSDMR_1		0x2861b723
+#define CFG_LBC_LSDMR_2		0x0861b723
+#define CFG_LBC_LSDMR_3		0x0861b723
+#define CFG_LBC_LSDMR_4		0x1861b723
+#define CFG_LBC_LSDMR_5		0x4061b723
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
+#else
+#define CFG_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
+#endif
+#define CFG_OR4_PRELIM          0xffffe1f1
+#define CFG_BCSR                (CFG_BR4_PRELIM & 0xffff8000)
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR   	0x40000000 	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_BAUDRATE	 	115200
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+
+/* General PCI */
+#define CFG_PCI_MEM_BASE	0x80000000
+#define CFG_PCI_MEM_PHYS	0x80000000
+#define CFG_PCI_MEM_SIZE	0x20000000
+#define CFG_PCI_IO_BASE         0xe2000000
+
+#if defined(CONFIG_PCI)
+#define CONFIG_NET_MULTI
+#undef CONFIG_EEPRO100
+#define CONFIG_TULIP
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+#if !defined(CONFIG_PCI_PNP)
+#define PCI_ENET0_IOADDR      0xe0000000
+#define PCI_ENET0_MEMADDR     0xe0000000
+#define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
+#endif
+#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0008
+#elif defined(CONFIG_TSEC_ENET)
+#define CONFIG_NET_MULTI 	1
+#define CONFIG_MII		1	/* MII PHY management	*/
+#define CONFIG_MPC85XX_TSEC1    1
+#define CONFIG_MPC85XX_TSEC1_NAME      "TSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME      "TSEC1"
+#define CONFIG_MPC85XX_FEC      1
+#define CONFIG_MPC85XX_FEC_NAME                "FEC"
+#define TSEC1_PHY_ADDR          7
+#define	TSEC2_PHY_ADDR		4
+#define FEC_PHY_ADDR            2
+#define TSEC1_PHYIDX            0
+#define TSEC2_PHYIDX            0
+#define FEC_PHYIDX              0
+/* Options are: TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME                "TSEC0"
+
+#define CONFIG_PHY_M88E1011     1       /* GigaBit Ether PHY    */
+#define INTEL_LXT971_PHY	1
+#endif
+
+#undef DEBUG
+
+/* Environment */
+#ifndef CFG_RAMBOOT
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_ENV_IS_NOWHERE
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x100000)
+#define CFG_ENV_SIZE		0x2000
+#else
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#endif
+#define CFG_ENV_SIZE		0x2000
+#else
+/* #define CFG_NO_FLASH		1 */	/* Flash is not usable now	*/
+#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_BOOTARGS	"root=/dev/ram rw console=ttyS0,115200"
+#define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xffa00000"
+#define CONFIG_BOOTDELAY	3 	/* -1 disable autoboot */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PING \
+				| CFG_CMD_PCI | CFG_CMD_I2C ) & \
+				 ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
+#else
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PING \
+				| CFG_CMD_I2C ) & \
+				 ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
+#endif
+#else
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI \
+				| CFG_CMD_PING | CFG_CMD_I2C )
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C )
+#endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_LOAD_ADDR   0x2000000       /* default load address */
+#define CFG_PROMPT	"MPC8540EVAL=> "/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux */
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE	32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*****************************/
+/* Environment Configuration */
+/*****************************/
+/* The mac addresses for all ethernet interface */
+/* NOTE: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR  00:01:af:07:9b:8a
+#define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
+#define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
+#endif
+
+#define CONFIG_ROOTPATH  /nfsroot
+#define CONFIG_BOOTFILE  your.uImage
+
+#define CONFIG_SERVERIP         192.168.101.1
+#define CONFIG_IPADDR           192.168.101.11
+#define CONFIG_GATEWAYIP        192.168.101.0
+#define CONFIG_NETMASK          255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /* default location for tftp and bootm */
+
+#define CONFIG_HOSTNAME         MPC8540EVAL
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
new file mode 100755
index 0000000..c96b98b
--- /dev/null
+++ b/include/configs/MPC8541CDS.h
@@ -0,0 +1,505 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8541cds board configuration file
+ *
+ * Please refer to doc/README.mpc85xxcds for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41 */
+#define CONFIG_CPM2		1	/* has CPM2 */
+#define CONFIG_MPC8541		1	/* MPC8541 specific */
+#define CONFIG_MPC8541CDS	1	/* MPC8541CDS board specific */
+
+#define CONFIG_PCI
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the CDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
+#define CONFIG_BTB			    /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ */
+
+#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 8M */
+
+#define CFG_BR0_PRELIM		0xff801001
+#define CFG_BR1_PRELIM		0xff001001
+
+#define	CFG_OR0_PRELIM		0xff806e65
+#define	CFG_OR1_PRELIM		0xff806e65
+
+#define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
+#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM          0xf0001861
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM		0xfc006901
+
+#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
+#define CFG_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ *                  or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFCR16		\
+				| CFG_LBC_LSDMR_PRETOACT7	\
+				| CFG_LBC_LSDMR_ACTTORW7	\
+				| CFG_LBC_LSDMR_BL8		\
+				| CFG_LBC_LSDMR_WRC4		\
+				| CFG_LBC_LSDMR_CL3		\
+				| CFG_LBC_LSDMR_RFEN		\
+				)
+
+/*
+ * The CADMUS registers are connected to CS3 on CDS.
+ * The new memory map places CADMUS at 0xf8000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ *    port-size = 8-bits  = BR[19:20] = 01
+ *    no parity checking  = BR[21:22] = 00
+ *    GPMC for MSEL       = BR[24:26] = 000
+ *    Valid               = BR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
+ *    disable buffer ctrl OR[19]    = 0
+ *    CSNT                OR[20]    = 1
+ *    ACS                 OR[21:22] = 11
+ *    XACS                OR[23]    = 1
+ *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
+ *    SETA                OR[28]    = 0
+ *    TRLX                OR[29]    = 1
+ *    EHTR                OR[30]    = 1
+ *    EAD extra time      OR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+
+#define CADMUS_BASE_ADDR 0xf8000000
+#define CFG_BR3_PRELIM   0xf8000801
+#define CFG_OR3_PRELIM   0xfff00ff7
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CFG_INIT_RAM_END    	0x4000	    /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128	    /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     2
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR	0x57
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0xe2000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#define CFG_PCI2_MEM_BASE	0xa0000000
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI2_IO_BASE	0xe3000000
+#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
+#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR      0xe0000000
+    #define PCI_ENET0_MEMADDR     0xe0000000
+    #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#undef CONFIG_MPC85XX_FEC
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define FEC_PHY_ADDR		3
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define FEC_PHYIDX		0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#define CFG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PCI \
+				| CFG_CMD_PING \
+				| CFG_CMD_I2C \
+				| CFG_CMD_MII)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_I2C \
+				| CFG_CMD_MII)
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE	32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME  unknown
+#define CONFIG_ROOTPATH  /nfsroot
+#define CONFIG_BOOTFILE  your.uImage
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS1\0"                                                 \
+   "ramdiskaddr=400000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
new file mode 100755
index 0000000..4ca8bc3
--- /dev/null
+++ b/include/configs/MPC8548CDS.h
@@ -0,0 +1,521 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8548cds board configuration file
+ *
+ * Please refer to doc/README.mpc85xxcds for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548		1	/* MPC8548 specific */
+#define CONFIG_MPC8548CDS	1	/* MPC8548CDS board specific */
+
+#undef CONFIG_PCI
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the CDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
+#define CONFIG_BTB			    /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ */
+
+#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 8M */
+
+#define CFG_BR0_PRELIM		0xff801001
+#define CFG_BR1_PRELIM		0xff001001
+
+#define	CFG_OR0_PRELIM		0xff806e65
+#define	CFG_OR1_PRELIM		0xff806e65
+
+#define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
+#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM          0xf0001861
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM		0xfc006901
+
+#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
+#define CFG_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ *                  or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFCR16		\
+				| CFG_LBC_LSDMR_PRETOACT7	\
+				| CFG_LBC_LSDMR_ACTTORW7	\
+				| CFG_LBC_LSDMR_BL8		\
+				| CFG_LBC_LSDMR_WRC4		\
+				| CFG_LBC_LSDMR_CL3		\
+				| CFG_LBC_LSDMR_RFEN		\
+				)
+
+/*
+ * The CADMUS registers are connected to CS3 on CDS.
+ * The new memory map places CADMUS at 0xf8000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ *    port-size = 8-bits  = BR[19:20] = 01
+ *    no parity checking  = BR[21:22] = 00
+ *    GPMC for MSEL       = BR[24:26] = 000
+ *    Valid               = BR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
+ *    disable buffer ctrl OR[19]    = 0
+ *    CSNT                OR[20]    = 1
+ *    ACS                 OR[21:22] = 11
+ *    XACS                OR[23]    = 1
+ *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
+ *    SETA                OR[28]    = 0
+ *    TRLX                OR[29]    = 1
+ *    EHTR                OR[30]    = 1
+ *    EAD extra time      OR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+
+#define CADMUS_BASE_ADDR 0xf8000000
+#define CFG_BR3_PRELIM   0xf8000801
+#define CFG_OR3_PRELIM   0xfff00ff7
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CFG_INIT_RAM_END    	0x4000	    /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128	    /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     2
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR	0x57
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0xe2000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#define CFG_PCI2_MEM_BASE	0xa0000000
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI2_IO_BASE	0xe3000000
+#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
+#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR      0xe0000000
+    #define PCI_ENET0_MEMADDR     0xe0000000
+    #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"eTSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"eTSEC1"
+#define CONFIG_MPC85XX_TSEC3	1
+#define CONFIG_MPC85XX_TSEC3_NAME	"eTSEC2"
+#define CONFIG_MPC85XX_TSEC4	1
+#define CONFIG_MPC85XX_TSEC4_NAME	"eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC3_PHY_ADDR		2
+#define TSEC4_PHY_ADDR		3
+#define FEC_PHY_ADDR		3
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC4_PHYIDX		0
+#define FEC_PHYIDX		0
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#define CFG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PCI \
+				| CFG_CMD_PING \
+				| CFG_CMD_I2C \
+				| CFG_CMD_MII)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_I2C \
+				| CFG_CMD_MII)
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE	32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME  unknown
+#define CONFIG_ROOTPATH  /nfsroot
+#define CONFIG_BOOTFILE  your.uImage
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS1\0"                                                 \
+   "ramdiskaddr=400000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
new file mode 100755
index 0000000..a44e3ec
--- /dev/null
+++ b/include/configs/MPC8555CDS.h
@@ -0,0 +1,505 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8555cds board configuration file
+ *
+ * Please refer to doc/README.mpc85xxcds for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41 */
+#define CONFIG_CPM2		1	/* has CPM2 */
+#define CONFIG_MPC8555		1	/* MPC8555 specific */
+#define CONFIG_MPC8555CDS	1	/* MPC8555CDS board specific */
+
+#define CONFIG_PCI
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+#undef CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the CDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
+#define CONFIG_BTB			    /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ */
+
+#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 8M */
+
+#define CFG_BR0_PRELIM		0xff801001
+#define CFG_BR1_PRELIM		0xff001001
+
+#define	CFG_OR0_PRELIM		0xff806e65
+#define	CFG_OR1_PRELIM		0xff806e65
+
+#define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE}
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
+#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM          0xf0001861
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM		0xfc006901
+
+#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
+#define CFG_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ *                  or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFCR16		\
+				| CFG_LBC_LSDMR_PRETOACT7	\
+				| CFG_LBC_LSDMR_ACTTORW7	\
+				| CFG_LBC_LSDMR_BL8		\
+				| CFG_LBC_LSDMR_WRC4		\
+				| CFG_LBC_LSDMR_CL3		\
+				| CFG_LBC_LSDMR_RFEN		\
+				)
+
+/*
+ * The CADMUS registers are connected to CS3 on CDS.
+ * The new memory map places CADMUS at 0xf8000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ *    port-size = 8-bits  = BR[19:20] = 01
+ *    no parity checking  = BR[21:22] = 00
+ *    GPMC for MSEL       = BR[24:26] = 000
+ *    Valid               = BR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
+ *    disable buffer ctrl OR[19]    = 0
+ *    CSNT                OR[20]    = 1
+ *    ACS                 OR[21:22] = 11
+ *    XACS                OR[23]    = 1
+ *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
+ *    SETA                OR[28]    = 0
+ *    TRLX                OR[29]    = 1
+ *    EHTR                OR[30]    = 1
+ *    EAD extra time      OR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+
+#define CADMUS_BASE_ADDR 0xf8000000
+#define CFG_BR3_PRELIM   0xf8000801
+#define CFG_OR3_PRELIM   0xfff00ff7
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CFG_INIT_RAM_END    	0x4000	    /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128	    /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     2
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE    1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_EEPROM_ADDR	0x57
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0xe2000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#define CFG_PCI2_MEM_BASE	0xa0000000
+#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
+#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI2_IO_BASE	0xe3000000
+#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
+#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */
+
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR      0xe0000000
+    #define PCI_ENET0_MEMADDR     0xe0000000
+    #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#undef CONFIG_MPC85XX_FEC
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define FEC_PHY_ADDR		3
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define FEC_PHYIDX		0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#define CFG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PCI \
+				| CFG_CMD_PING \
+				| CFG_CMD_I2C \
+				| CFG_CMD_MII)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
+				| CFG_CMD_PING \
+				| CFG_CMD_I2C \
+				| CFG_CMD_MII)
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE	32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME  unknown
+#define CONFIG_ROOTPATH  /nfsroot
+#define CONFIG_BOOTFILE  your.uImage
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS1\0"                                                 \
+   "ramdiskaddr=400000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
new file mode 100755
index 0000000..2d5031b
--- /dev/null
+++ b/include/configs/MPC8560ADS.h
@@ -0,0 +1,561 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8560ads board configuration file
+ *
+ * Please refer to doc/README.mpc85xx for more info.
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
+#define CONFIG_CPM2		1	/* has CPM2 */
+#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific */
+
+#define CONFIG_PCI
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#undef CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
+#define  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ *    33000000
+ *    66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz.  In any event, this value
+ * must match the settings of some switches.  Details can be found
+ * in the README.mpc85xxads.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	33000000
+#endif
+
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#define CFG_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00200000	/* memtest region */
+#define CFG_MEMTEST_END		0x00400000
+
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#if defined(CONFIG_SPD_EEPROM)
+    /*
+     * Determine DDR configuration from I2C interface.
+     */
+    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+#else
+    /*
+     * Manually set up DDR parameters
+     */
+    #define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
+    #define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+    #define CFG_DDR_CS0_CONFIG	0x80000002
+    #define CFG_DDR_TIMING_1	0x37344321
+    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+    #define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
+    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
+    #define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
+#endif
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 16M */
+#define CFG_BR0_PRELIM		0xff001801	/* port size 32bit */
+
+#define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CFG_BR2_PRELIM		0xf0001861
+
+/*
+ * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CFG_OR2_PRELIM		0xfc006901
+
+#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
+#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
+
+/*
+ * LSDMR masks
+ */
+#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
+#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
+#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
+#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
+#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
+#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
+#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
+#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
+#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
+#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
+#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
+#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
+#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
+#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))
+
+#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))
+
+#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_BSMA1516	\
+				| CFG_LBC_LSDMR_RFCR5		\
+				| CFG_LBC_LSDMR_PRETOACT3	\
+				| CFG_LBC_LSDMR_ACTTORW3	\
+				| CFG_LBC_LSDMR_BL8		\
+				| CFG_LBC_LSDMR_WRC2		\
+				| CFG_LBC_LSDMR_CL3		\
+				| CFG_LBC_LSDMR_RFEN		\
+				)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_PCHALL)
+#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_ARFRSH)
+#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_MRW)
+#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
+				| CFG_LBC_LSDMR_OP_NORMAL)
+
+
+/*
+ * 32KB, 8-bit wide for ADS config reg
+ */
+#define CFG_BR4_PRELIM          0xf8000801
+#define CFG_OR4_PRELIM		0xffffe1f1
+#define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_ON_SCC	/* define if console on SCC */
+#undef  CONFIG_CONS_NONE	/* define if console on something else */
+#define CONFIG_CONS_INDEX       1  /* which serial channel for console */
+
+#define CONFIG_BAUDRATE	 	115200
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+
+/* RapidIO MMU */
+#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
+#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0xe2000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR	0xe0000000
+    #define PCI_ENET0_MEMADDR	0xe0000000
+    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#undef CONFIG_MPC85XX_FEC
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
+
+#define CONFIG_ETHER_ON_FCC	/* define if ether on FCC   */
+#undef  CONFIG_ETHER_NONE	/* define if ether on something else */
+#define CONFIG_ETHER_INDEX      2       /* which channel for ether */
+
+#if (CONFIG_ETHER_INDEX == 2)
+  /*
+   * - Rx-CLK is CLK13
+   * - Tx-CLK is CLK14
+   * - Select bus for bd/buffers
+   * - Full duplex
+   */
+  #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+  #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+  #define CFG_CPMFCR_RAMTYPE    0
+  #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
+  #define FETH2_RST		0x01
+#elif (CONFIG_ETHER_INDEX == 3)
+  /* need more definitions here for FE3 */
+  #define FETH3_RST		0x80
+#endif  				/* CONFIG_ETHER_INDEX */
+
+#define CONFIG_MII			/* MII PHY management */
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
+
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT	2		/* Port C */
+#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
+#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
+			else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
+			else	iop->pdat &= ~0x00200000
+
+#define MIIDELAY	udelay(1)
+
+#endif
+
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+  #define CFG_ENV_IS_IN_FLASH	1
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+  #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+  #define CFG_ENV_SIZE		0x2000
+#else
+  #define CFG_NO_FLASH		1	/* Flash is not usable now */
+  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_PCI		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+  #elif defined(CONFIG_TSEC_ENET)
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)		\
+				& ~(CFG_CMD_ENV))
+  #elif defined(CONFIG_ETHER_ON_FCC)
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_MII		\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_I2C)		\
+				& ~(CFG_CMD_ENV))
+  #endif
+#else
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PCI		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+  #elif defined(CONFIG_TSEC_ENET)
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+  #elif defined(CONFIG_ETHER_ON_FCC)
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_MII		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+  #endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x1000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		/nfsroot
+#define CONFIG_BOOTFILE		your.uImage
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS0\0"                                                 \
+   "ramdiskaddr=400000\0"						\
+   "ramdiskfile=your.ramdisk.u-boot\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h
new file mode 100755
index 0000000..565f9bb
--- /dev/null
+++ b/include/configs/MPC86xADS.h
@@ -0,0 +1,46 @@
+/*
+  * A collection of structures, addresses, and values associated with
+  * the Motorola MPC8xxADS board.  Copied from the FADS config.
+  *
+  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+  *
+  * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
+  *
+  * Values common to all FADS family boards are in board/fads/fads.h
+  */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* board type */
+#define CONFIG_MPC86xADS        1       /* new ADS */
+#define CONFIG_FADS		1       /* We are FADS compatible (more or less) */
+
+/* New MPC86xADS - pick one of these */
+#define CONFIG_MPC866T 		1
+#undef CONFIG_MPC866P
+#undef CONFIG_MPC859T
+#undef CONFIG_MPC859DSL
+#undef CONFIG_MPC852T
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_8xx_OSCLK	10000000 /* 10MHz oscillator on EXTCLK  */
+
+#define CONFIG_DRAM_50MHZ       1
+#define CONFIG_SDRAM_50MHZ      1
+
+#include "fads.h"
+
+#define CFG_OR5_PRELIM		0xFFFF8110	/* 64Kbyte address space */
+#define CFG_BR5_PRELIM		(CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h
new file mode 100755
index 0000000..74318e5
--- /dev/null
+++ b/include/configs/MPC885ADS.h
@@ -0,0 +1,47 @@
+/*
+ * A collection of structures, addresses, and values associated with
+ * the Motorola DUET ADS board. Values common to all FADS family boards
+ * are in board/fads/fads.h
+ *
+ * Copyright (C) 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Board type */
+#define CONFIG_MPC885ADS	        1	/* Duet (MPC87x/88x) ADS */
+#define CONFIG_FADS		1	/* We are FADS compatible (more or less) */
+
+#define CONFIG_MPC885 		1	/* MPC885 CPU (Duet family) */
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_8xx_OSCLK	10000000 /* 10 MHz oscillator on EXTCLK  */
+
+#define CFG_PLPRCR		((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS)
+
+#define CONFIG_SDRAM_50MHZ      1
+
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL   \
+			 | CFG_CMD_DHCP   \
+			 | CFG_CMD_IMMAP  \
+			 | CFG_CMD_MII    \
+			 | CFG_CMD_PING   \
+			)
+
+#include "fads.h"
+
+#undef CFG_SCCR
+#define CFG_SCCR	(SCCR_TBS|SCCR_EBDF11)
+
+#define CFG_OR5_PRELIM		0xFFFF8110	/* 64Kbyte address space */
+#define CFG_BR5_PRELIM		(CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)
+
+#define CONFIG_HAS_ETH1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h
new file mode 100755
index 0000000..da52e0e
--- /dev/null
+++ b/include/configs/MUSENKI.h
@@ -0,0 +1,295 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * Configuration settings for the MUSENKI board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8245		1
+#define CONFIG_MUSENKI		1
+
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) 	*/
+
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+/* Print Buffer Size
+ */
+#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS	8		/* Max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI      		/* include pci support          */
+#undef CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support */
+
+#define CONFIG_TULIP
+
+#define PCI_ENET0_IOADDR		0x80000000
+#define PCI_ENET0_MEMADDR		0x80000000
+#define PCI_ENET1_IOADDR		0x81000000
+#define PCI_ENET1_MEMADDR		0x81000000
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE	    0x00000000
+
+#define CFG_FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank on RCS#0 */
+#define CFG_FLASH_BASE1_PRELIM      0xFF000000      /* FLASH bank on RCS#1 */
+#define CFG_FLASH_BASE  CFG_FLASH_BASE0_PRELIM
+
+/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
+ * reset vector is actually located at FFB00100, but the 8245
+ * takes care of us.
+ */
+#define CFG_RESET_ADDRESS   0xFFF00100
+
+#define CFG_EUMB_ADDR	    0xFC000000
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+
+#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+	/* Maximum amount of RAM.
+	 */
+#define CFG_MAX_RAM_SIZE    0x08000000	/* 0 .. 128 MB of (S)DRAM */
+
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	1
+
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
+#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+/* #define CFG_MONITOR_BASE        TEXT_BASE */
+/*#define CFG_GBL_DATA_SIZE    256*/
+#define CFG_GBL_DATA_SIZE      128
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x1000
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
+#define CFG_HZ		     1000
+
+	/* Bit-field values for MCCR1.
+	 */
+#define CFG_ROMNAL	    7
+#define CFG_ROMFAL	    11
+#define CFG_DBUS_SIZE       0x3
+
+	/* Bit-field values for MCCR2.
+	 */
+#define CFG_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
+#define CFG_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
+
+	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+	 */
+#define CFG_BSTOPRE	    121
+
+	/* Bit-field values for MCCR3.
+	 */
+#define CFG_REFREC	    8	    /* Refresh to activate interval */
+
+	/* Bit-field values for MCCR4.
+	 */
+#define CFG_PRETOACT	    3	    /* Precharge to activate interval FIXME: was 2	*/
+#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
+#define CFG_ACTORW	    3		/* FIXME was 2 */
+#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
+#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
+#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CFG_EXTROM	    1
+#define CFG_REGDIMM	    0
+
+#define CFG_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
+
+#define CFG_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CFG_BANK0_START	    0x00000000
+#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE    1
+#define CFG_BANK1_START	    0x3ff00000
+#define CFG_BANK1_END	    0x3fffffff
+#define CFG_BANK1_ENABLE    0
+#define CFG_BANK2_START	    0x3ff00000
+#define CFG_BANK2_END	    0x3fffffff
+#define CFG_BANK2_ENABLE    0
+#define CFG_BANK3_START	    0x3ff00000
+#define CFG_BANK3_END	    0x3fffffff
+#define CFG_BANK3_ENABLE    0
+#define CFG_BANK4_START	    0x3ff00000
+#define CFG_BANK4_END	    0x3fffffff
+#define CFG_BANK4_ENABLE    0
+#define CFG_BANK5_START	    0x3ff00000
+#define CFG_BANK5_END	    0x3fffffff
+#define CFG_BANK5_ENABLE    0
+#define CFG_BANK6_START	    0x3ff00000
+#define CFG_BANK6_END	    0x3fffffff
+#define CFG_BANK6_ENABLE    0
+#define CFG_BANK7_START	    0x3ff00000
+#define CFG_BANK7_END	    0x3fffffff
+#define CFG_BANK7_ENABLE    0
+
+#define CFG_ODCR	    0xff
+
+#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L  CFG_IBAT0L
+#define CFG_DBAT0U  CFG_IBAT0U
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+#define CFG_DBAT2L  CFG_IBAT2L
+#define CFG_DBAT2U  CFG_IBAT2U
+#define CFG_DBAT3L  CFG_IBAT3L
+#define CFG_DBAT3U  CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
+#define CFG_MAX_FLASH_SECT	64	/* Max number of sectors per flash	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+
+	/* Warining: environment is not EMBEDDED in the U-Boot code.
+	 * It's stored in flash separately.
+	 */
+#define CFG_ENV_IS_IN_FLASH	    1
+#define CFG_ENV_ADDR		0xFFFF0000
+#define CFG_ENV_SIZE		0x00010000 /* Size of the Environment		*/
+#define CFG_ENV_SECT_SIZE	0x20000 /* Size of the Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
new file mode 100755
index 0000000..88eefa1
--- /dev/null
+++ b/include/configs/MVBLUE.h
@@ -0,0 +1,325 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define MV_VERSION	"v0.2.0"
+
+/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
+#define ERR_NONE			0
+#define ERR_ENV 			1
+#define ERR_BOOTM_BADMAGIC 	2
+#define ERR_BOOTM_BADCRC   	3
+#define ERR_BOOTM_GUNZIP   	4
+#define ERR_BOOTP_TIMEOUT	5
+#define ERR_DHCP			6
+#define ERR_TFTP			7
+#define ERR_NOLAN 			8
+#define ERR_LANDRV 			9
+
+#define CONFIG_BOARD_TYPES	1
+#define MVBLUE_BOARD_BOX	1
+#define MVBLUE_BOARD_LYNX	2
+
+#if 0
+#define ERR_LED(code)	do { if (code) \
+								*(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
+							 else \
+								*(volatile char *)(0xff000003) = ( 1 ); \
+						} while(0)
+#else
+#define ERR_LED(code)
+#endif
+
+#undef DEBUG
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8245		1
+#define CONFIG_MVBLUE		1
+
+#define CONFIG_CLOCKS_IN_MHZ	1
+
+#define CONFIG_BOARD_TYPES    1
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOT_RETRY_TIME	-1
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds (stop with 's')...\n"
+#define CONFIG_AUTOBOOT_STOP_STR	"s"
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_RESET_TO_RETRY		60
+
+#define CONFIG_COMMANDS		( CFG_CMD_ASKENV | CFG_CMD_BOOTD | CFG_CMD_CACHE | CFG_CMD_DHCP	| \
+				  CFG_CMD_ECHO	 | CFG_CMD_ENV   | CFG_CMD_FLASH | CFG_CMD_IMI	| \
+				  CFG_CMD_IRQ	 | CFG_CMD_NET	 | CFG_CMD_PCI	 | CFG_CMD_RUN   )
+
+
+#define CONFIG_BOOTP_MASK   ( 0xffffffff )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) 	*/
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory		*/
+#define CFG_PROMPT	"=> "	/* Monitor Command Prompt	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS		16			/* Max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x00100000	/* Default load address			*/
+
+#define CONFIG_BOOTCOMMAND  	"run nfsboot"
+#define CONFIG_BOOTARGS			"root=/dev/mtdblock5 ro rootfstype=jffs2"
+
+#define CONFIG_NFSBOOTCOMMAND  	"bootp; run nfsargs addcons;bootm"
+
+#define CONFIG_EXTRA_ENV_SETTINGS			\
+	"console_nr=0\0"				\
+    "dhcp_client_id=mvBOX-XP\0"				\
+    "dhcp_vendor-class-identifier=mvBOX\0"		\
+    "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
+    "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
+    "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0"	\
+    "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+			"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"	\
+	"addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
+    "mv_version=" MV_VERSION "\0"	\
+	"bootretry=30\0"
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT 5
+
+#define CONFIG_TULIP
+#define CONFIG_TULIP_FIX_DAVICOM	1
+#define CONFIG_ETHADDR      		b6:b4:45:eb:fb:c0
+
+#define CONFIG_HW_WATCHDOG
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE	    0x00000000
+
+#define CFG_FLASH_BASE      0xFFF00000
+#define CFG_MONITOR_BASE    TEXT_BASE
+
+#define CFG_RESET_ADDRESS   0xFFF00100
+#define CFG_EUMB_ADDR	    0xFC000000
+
+#define CFG_MONITOR_LEN     0x00100000
+#define CFG_MALLOC_LEN      (512 << 10) /* Reserve some kB for malloc()  */
+
+#define CFG_MEMTEST_START   0x00100000	/* memtest works on		*/
+#define CFG_MEMTEST_END	    0x00800000	/* 1M ... 8M in DRAM		*/
+
+/* Maximum amount of RAM.  */
+#define CFG_MAX_RAM_SIZE    0x10000000	/* 0 .. 256MB of (S)DRAM */
+
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_ISA_IO      0xFE000000
+
+/*
+ * serial configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE    1
+
+#define CFG_NS16550_CLK     get_bus_freq(0)
+
+#define CFG_NS16550_COM1    (CFG_EUMB_ADDR + 0x4500)
+#define CFG_NS16550_COM2    (CFG_EUMB_ADDR + 0x4600)
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x1000
+#define CFG_GBL_DATA_SIZE     128
+#define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33000000
+#define CFG_HZ		     	 10000
+
+/* Bit-field values for MCCR1.  */
+#define CFG_ROMNAL      7
+#define CFG_ROMFAL      11
+
+/* Bit-field values for MCCR2.  */
+#define CFG_TSWAIT      0x5
+#define CFG_REFINT      430
+
+/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.  */
+#define CFG_BSTOPRE     121
+
+/* Bit-field values for MCCR3.  */
+#define CFG_REFREC      8
+
+/* Bit-field values for MCCR4.  */
+#define CFG_PRETOACT    3
+#define CFG_ACTTOPRE    5
+#define CFG_ACTORW      3
+#define CFG_SDMODE_CAS_LAT  3
+#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CFG_EXTROM      1
+#define CFG_REGDIMM     0
+#define CFG_DBUS_SIZE2  1
+#define CFG_SDMODE_WRAP 0
+
+#define CFG_PGMAX       0x32
+#define CFG_SDRAM_DSCD  0x20
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CFG_BANK0_START	    0x00000000
+#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE    1
+#define CFG_BANK1_START     0x3ff00000
+#define CFG_BANK1_END       0x3fffffff
+#define CFG_BANK1_ENABLE    0
+#define CFG_BANK2_START     0x3ff00000
+#define CFG_BANK2_END       0x3fffffff
+#define CFG_BANK2_ENABLE    0
+#define CFG_BANK3_START     0x3ff00000
+#define CFG_BANK3_END       0x3fffffff
+#define CFG_BANK3_ENABLE    0
+#define CFG_BANK4_START     0x3ff00000
+#define CFG_BANK4_END       0x3fffffff
+#define CFG_BANK4_ENABLE    0
+#define CFG_BANK5_START     0x3ff00000
+#define CFG_BANK5_END       0x3fffffff
+#define CFG_BANK5_ENABLE    0
+#define CFG_BANK6_START     0x3ff00000
+#define CFG_BANK6_END       0x3fffffff
+#define CFG_BANK6_ENABLE    0
+#define CFG_BANK7_START     0x3ff00000
+#define CFG_BANK7_END       0x3fffffff
+#define CFG_BANK7_ENABLE    0
+
+#define CFG_ODCR	    0xff
+
+#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L  CFG_IBAT0L
+#define CFG_DBAT0U  CFG_IBAT0U
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+#define CFG_DBAT2L  CFG_IBAT2L
+#define CFG_DBAT2U  CFG_IBAT2U
+#define CFG_DBAT3L  CFG_IBAT3L
+#define CFG_DBAT3U  CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#undef  CFG_FLASH_PROTECTION
+#define CFG_MAX_FLASH_BANKS		1	/* Max number of flash banks		*/
+#define CFG_MAX_FLASH_SECT		63	/* Max number of sectors per flash	*/
+
+#define CFG_FLASH_ERASE_TOUT	12000
+#define CFG_FLASH_WRITE_TOUT	1000
+
+
+#define CFG_ENV_IS_IN_FLASH
+
+#define CFG_ENV_OFFSET		0x00010000
+#define CFG_ENV_SIZE		0x00010000
+#define CFG_ENV_SECT_SIZE	0x00010000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h
new file mode 100755
index 0000000..5995918
--- /dev/null
+++ b/include/configs/MVS1.h
@@ -0,0 +1,406 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_MVS		1	/* ...on a MVsensor module	*/
+#define CONFIG_MVS_16BIT_FLASH		/* ...with 16-bit flash access	*/
+#define CONFIG_8xx_GCLK_FREQ	50000000/* ... and a 50 MHz CPU		*/
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#undef	CONFIG_8xx_CONS_SMC1		/* Console is *NOT* on SMC1	*/
+#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate 		*/
+#define CONFIG_BOOTDELAY	5	/* autoboot after this many seconds	*/
+
+#define CONFIG_PREBOOT		"echo;echo To mount root over NFS use \"run bootnet\";echo To mount root from FLASH use  \"run bootflash\";echo"
+#define	CONFIG_BOOTARGS		"root=/dev/mtdblock2 rw"
+#define CONFIG_BOOTCOMMAND						\
+    "bootp; "                               				\
+    "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+    "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
+    "bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#define	CONFIG_WATCHDOG			/* watchdog disabled/enabled	*/
+
+#undef	CONFIG_STATUS_LED		/* Status LED disabled/enabled	*/
+
+#undef  CONFIG_CAN_DRIVER       /* CAN Driver support disabled  */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_VENDOREX )
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+/* MVsensor uses a really minimal U-Boot ! */
+#define CONFIG_COMMANDS	       (CFG_CMD_LOADS	| \
+				CFG_CMD_LOADB	| \
+				CFG_CMD_IMI	| \
+				CFG_CMD_FLASH	| \
+				CFG_CMD_MEMORY	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ENV	| \
+				CFG_CMD_BOOTD	| \
+				CFG_CMD_RUN	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#undef  CFG_HUSH_PARSER			/* Hush parse for U-Boot ?? */
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2     "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+
+#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 192 kB for Monitor	*/
+
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip (for AMD320DB chip)	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+
+/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */
+#define	CFG_ENV_OFFSET		0x8000	/* Offset of Environment Sector	(bottom boot sector) */
+#define	CFG_ENV_SIZE		0x2000	/* Used Size of Environment Sector 8k	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+	     SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR  (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_PCCARD	0	/* **DON'T** Use IDE with PC Card Adapter	*/
+
+#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		0	/* max. no. of IDE buses			*/
+#define CFG_IDE_MAXDEVICE	0	/* max. no. of drives per IDE bus	*/
+
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#undef FLASH_BASE1_PRELIM
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+
+/*
+ * FLASH timing:
+ */
+/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+/*
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+				 OR_SCY_5_CLK | OR_EHTR)
+*/
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#ifdef CONFIG_MVS_16BIT_FLASH
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#else
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
+#endif
+
+#undef CFG_OR1_REMAP
+#undef CFG_OR1_PRELIM
+#undef CFG_BR1_PRELIM
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#undef SDRAM_BASE3_PRELIM
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#undef CFG_OR3_PRELIM
+#undef CFG_BR3_PRELIM
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#define CFG_MAMR_PTA		 98
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
new file mode 100755
index 0000000..371ea17
--- /dev/null
+++ b/include/configs/NC650.h
@@ -0,0 +1,424 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC852T		1
+#define CONFIG_NC650		1
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+
+/*
+ * 10 MHz - PLL input clock
+ */
+#define CONFIG_8xx_OSCLK		10000000
+
+/*
+ * 50 MHz - default CPU clock
+ */
+#define CONFIG_8xx_CPUCLK_DEFAULT	50000000
+
+/*
+ * 15 MHz - CPU minimum clock
+ */
+#define CFG_8xx_CPUCLK_MIN		15000000
+
+/*
+ * 133 MHz - CPU maximum clock
+ */
+#define CFG_8xx_CPUCLK_MAX		133000000
+
+#define CFG_MEASURE_CPUCLK
+#define CFG_8XX_XIN			CONFIG_8xx_OSCLK
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp;" 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" 	\
+	"bootm"
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
+#define FEC_ENET
+#define CONFIG_MII
+#define CFG_DISCOVER_PHY	1
+
+
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		100000	/* 100 kHz			*/
+#define CFG_I2C_SLAVE		0x7f
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define SCL		0x1000		/* PA 3 */
+#define SDA		0x2000		/* PA 2 */
+
+#define __I2C_DIR	immr->im_ioport.iop_padir
+#define __I2C_DAT	immr->im_ioport.iop_padat
+#define __I2C_PAR	immr->im_ioport.iop_papar
+#define	I2C_INIT	{ __I2C_PAR &= ~(SDA|SCL);	\
+			  __I2C_DIR |= (SDA|SCL);	}
+#define	I2C_READ	((__I2C_DAT & SDA) ? 1 : 0)
+#define	I2C_SDA(x)	{ if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
+#define	I2C_SCL(x)	{ if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
+#define	I2C_DELAY	{ udelay(5); }
+#define	I2C_ACTIVE	{ __I2C_DIR |= SDA; }
+#define	I2C_TRISTATE	{ __I2C_DIR &= ~SDA; }
+
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR		0x51
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR	 	0x00100000
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00740000
+
+#define CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Used Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * NAND flash support
+ */
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_ChipID_UNKNOWN	0x00
+#define SECTORSIZE		512
+#define NAND_MAX_FLOORS		1
+#define NAND_MAX_CHIPS		1
+#define ADDR_PAGE		2
+#define ADDR_COLUMN_PAGE	3
+#define ADDR_COLUMN		1
+#define NAND_NO_RB
+
+#define NAND_WAIT_READY(nand)		udelay(12)
+#define WRITE_NAND_COMMAND(d, adr)	WRITE_NAND(d, adr + 2)
+#define WRITE_NAND_ADDRESS(d, adr)	WRITE_NAND(d, adr + 1)
+#define WRITE_NAND(d, adr)		(*(volatile uint8_t *)(adr) = (uint8_t)(d))
+#define READ_NAND(adr)			(*(volatile uint8_t *)(adr))
+#define NAND_DISABLE_CE(nand)		/* nop */
+#define NAND_ENABLE_CE(nand)		/* nop */
+#define NAND_CTL_CLRALE(nandptr)	/* nop */
+#define NAND_CTL_SETALE(nandptr)	/* nop */
+#define NAND_CTL_CLRCLE(nandptr)	/* nop */
+#define NAND_CTL_SETCLE(nandptr)	/* nop */
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration					11-6
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00	| SCCR_DFSYNC00	| \
+			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
+			 SCCR_DFLCD000	| SCCR_DFALCD00)
+
+ /*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: Default value of OR0 after reset */
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_MSK | OR_BI | \
+				 OR_SCY_15_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
+
+/*
+ * BR2 and OR2 (NAND Flash) - now addressed through UPMB
+ */
+#define CFG_NAND_BASE		0x50000000
+#define CFG_NAND_SIZE		0x04000000
+
+#define CFG_OR_TIMING_NAND	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+				 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
+
+#define CFG_BR2_PRELIM  ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V  )
+#define CFG_OR2_PRELIM  (((-CFG_NAND_SIZE) & OR_AM_MSK) | OR_BI )
+
+/*
+ * BR3 and OR3 (SDRAM)
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank		*/
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+ /*
+  * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
+  */
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR3_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+
+/*
+ * BR5 and OR5 (SRAM)
+ */
+#define CFG_SRAM_BASE		0x60000000
+#define CFG_SRAM_SIZE		0x00080000
+
+#define CFG_OR_TIMING_SRAM	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+				 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)
+
+#define CFG_BR5_PRELIM  ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CFG_OR5_PRELIM  (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
+
+
+/*
+ * 4096 Rows from SDRAM example configuration
+ * 1000 factor s -> ms
+ * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4    Number of refresh cycles per period
+ * 64   Refresh cycle in ms per number of rows
+ */
+#define CFG_PTA_PER_CLK		((4096 * 64 * 1000) / (4 * 64))
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA		39
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
+
+/*
+ * MBMR settings for NAND flash
+ */
+
+#define CFG_MBMR_NAND ( MBMR_WLFB_5X )
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
+#define NAND_CACHE_PAGES 16			/* size of nand cache in 512 bytes pages */
+
+/*
+ * JFFS2 partitions
+ */
+
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nand0"
+#define CONFIG_JFFS2_PART_SIZE		0x00400000
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=nc650-0,nand0=nc650-nand"
+
+#define MTDPARTS_DEFAULT	"mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
+					"2560k(cramfs1),2560k(cramfs2)," \
+					"256k(u-boot),256k(env);" \
+				"nc650-nand:4m(nand1),28m(nand2)"
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
new file mode 100755
index 0000000..bf4c899
--- /dev/null
+++ b/include/configs/NETPHONE.h
@@ -0,0 +1,811 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2
+#error Unsupported CONFIG_NETPHONE version
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC870		1	/* This is a MPC885 CPU		*/
+#define CONFIG_NETPHONE		1	/* ...on a NetPhone board	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+/* #define CONFIG_XIN		 10000000 */
+#define CONFIG_XIN		 50000000
+/* #define MPC8XX_HZ		120000000 */
+#define MPC8XX_HZ		 66666666
+
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"echo;"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm"
+
+#define CONFIG_AUTOSCRIPT
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
+
+#define CONFIG_BOOTP_MASK		(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define	CONFIG_NET_MULTI	1 	/* the only way to get the FEC in */
+#define	FEC_ENET		1	/* eth.c needs it that way... */
+#undef CFG_DISCOVER_PHY
+#define CONFIG_MII		1
+#define CONFIG_RMII		1	/* use RMII interface */
+
+#define CONFIG_ETHER_ON_FEC1	1
+#define CONFIG_FEC1_PHY		8 	/* phy address of FEC */
+#define CONFIG_FEC1_PHY_NORXERR 1
+
+#define CONFIG_ETHER_ON_FEC2	1
+#define CONFIG_FEC2_PHY		4
+#define CONFIG_FEC2_PHY_NORXERR 1
+
+#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
+
+#define CONFIG_COMMANDS       ( CONFIG_CMD_DFL	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PING  	| \
+				CFG_CMD_MII 	| \
+				CFG_CMD_CDP	  \
+				)
+
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_MISC_INIT_R
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#define CFG_HUSH_PARSER	1
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#if CONFIG_NETPHONE_VERSION == 2
+#define CFG_FLASH_BASE4		0x40080000
+#endif
+
+#define CFG_RESET_ADDRESS   0x80000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#if CONFIG_NETPHONE_VERSION == 1
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#elif CONFIG_NETPHONE_VERSION == 2
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#endif
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	0x10000
+
+#define	CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
+#define CFG_ENV_OFFSET		0
+#define	CFG_ENV_SIZE		0x4000
+
+#define CFG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x70000)
+#define CFG_ENV_OFFSET_REDUND	0
+#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+#if CONFIG_XIN == 10000000
+
+#if MPC8XX_HZ == 120000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 100000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 50000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 25000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 40000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 75000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 10MHz
+#endif
+
+#elif CONFIG_XIN == 50000000
+
+#if MPC8XX_HZ == 120000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 100000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ ==  66666666
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 50MHz
+#endif
+
+#else
+
+#error unsupported XIN freq
+#endif
+
+
+/*
+ *-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ *
+ * Note: When TBS == 0 the timebase is independent of current cpu clock.
+ */
+
+#define SCCR_MASK	SCCR_EBDF11
+#if MPC8XX_HZ > 66666666
+#define CFG_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00 | SCCR_EBDF01)
+#else
+#define CFG_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+#if CONFIG_NETPHONE_VERSION == 2
+
+#define FLASH_BASE4_PRELIM	0x40080000	/* FLASH bank #1	*/
+
+#define CFG_OR4_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR4_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR4_PRELIM	((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+#endif
+
+/*
+ * BR3 and OR3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+
+#define CFG_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_MAMR_PTA		 234
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_ARTOS			/* include ARTOS support */
+
+#define CONFIG_LAST_STAGE_INIT		/* needed to reset the damn phys */
+
+/****************************************************************/
+
+#define DSP_SIZE	0x00010000	/* 64K */
+#define NAND_SIZE	0x00010000	/* 64K */
+
+#define DSP_BASE	0xF1000000
+#define NAND_BASE	0xF1010000
+
+/****************************************************************/
+
+/* NAND */
+#define CFG_NAND_BASE		NAND_BASE
+#define CONFIG_MTD_NAND_ECC_JFFS2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_MTD_NAND_UNSAFE
+
+#define CFG_MAX_NAND_DEVICE	1
+
+#define SECTORSIZE		512
+#define ADDR_COLUMN		1
+#define ADDR_PAGE		2
+#define ADDR_COLUMN_PAGE	3
+#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_MAX_FLOORS		1
+#define NAND_MAX_CHIPS		1
+
+/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
+#define NAND_DISABLE_CE(nand) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 20)); \
+	} while(0)
+
+#define NAND_ENABLE_CE(nand) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
+	} while(0)
+
+#define NAND_CTL_CLRALE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
+	} while(0)
+
+#define NAND_CTL_SETALE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 17)); \
+	} while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
+	} while(0)
+
+#define NAND_CTL_SETCLE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 18)); \
+	} while(0)
+
+#if CONFIG_NETPHONE_VERSION == 1
+#define NAND_WAIT_READY(nand) \
+	do { \
+		int _tries = 0; \
+		while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
+			if (++_tries > 100000) \
+				break; \
+	} while (0)
+#elif CONFIG_NETPHONE_VERSION == 2
+#define NAND_WAIT_READY(nand) \
+	do { \
+		int _tries = 0; \
+		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
+			if (++_tries > 100000) \
+				break; \
+	} while (0)
+#endif
+
+#define WRITE_NAND_COMMAND(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define WRITE_NAND_ADDRESS(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define WRITE_NAND(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define READ_NAND(adr) \
+	((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
+
+/*****************************************************************************/
+
+#define CFG_DIRECT_FLASH_TFTP
+#define CFG_DIRECT_NAND_TFTP
+
+/*****************************************************************************/
+
+#if CONFIG_NETPHONE_VERSION == 1
+#define STATUS_LED_BIT		0x00000008		/* bit 28 */
+#elif CONFIG_NETPHONE_VERSION == 2
+#define STATUS_LED_BIT		0x00000080		/* bit 24 */
+#endif
+
+#define STATUS_LED_PERIOD	(CFG_HZ / 2)
+#define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */
+
+#ifndef __ASSEMBLY__
+
+/* LEDs */
+
+/* led_id_t is unsigned int mask */
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+	do { \
+		((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \
+	} while(0)
+
+#define __led_set(_msk, _st) \
+	do { \
+		if ((_st)) \
+			((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \
+		else \
+			((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
+	} while(0)
+
+#define __led_init(msk, st) __led_set(msk, st)
+
+#endif
+
+/***********************************************************************************************************
+
+ ----------------------------------------------------------------------------------------------
+
+   (V1) version 1 of the board
+   (V2) version 2 of the board
+
+ ----------------------------------------------------------------------------------------------
+
+   Pin definitions:
+
+ +------+----------------+--------+------------------------------------------------------------
+ |  #   | Name           | Type   | Comment
+ +------+----------------+--------+------------------------------------------------------------
+ | PA3  | SPIEN_MAX      | Output | MAX serial to uart chip select
+ | PA7  | DSP_INT        | Output | DSP interrupt
+ | PA10 | DSP_RESET      | Output | DSP reset
+ | PA14 | USBOE          | Output | USB (1)
+ | PA15 | USBRXD         | Output | USB (1)
+ | PB19 | BT_RTS         | Output | Bluetooth (0)
+ | PB23 | BT_CTS         | Output | Bluetooth (0)
+ | PB26 | SPIEN_SEP      | Output | Serial EEPROM chip select
+ | PB27 | SPICS_DISP     | Output | Display chip select
+ | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
+ | PB29 | SPI_TXD        | Output | SPI Data Tx
+ | PB30 | SPI_CLK        | Output | SPI Clock
+ | PC10 | DISPA0         | Output | Display A0
+ | PC11 | BACKLIGHT      | Output | Display backlit
+ | PC12 | SPI2RXD        | Input  | (V1) 2nd SPI RXD
+ |      | IO_RESET       | Output | (V2) General I/O reset
+ | PC13 | SPI2TXD        | Output | (V1) 2nd SPI TXD (V1)
+ |      | HOOK           | Input  | (V2) Hook input interrupt
+ | PC15 | SPI2CLK        | Output | (V1) 2nd SPI CLK
+ |      | F_RY_BY        | Input  | (V2) NAND F_RY_BY
+ | PE17 | F_ALE          | Output | NAND F_ALE
+ | PE18 | F_CLE          | Output | NAND F_CLE
+ | PE20 | F_CE           | Output | NAND F_CE
+ | PE24 | SPICS_SCOUT    | Output | (V1) Codec chip select
+ |      | LED            | Output | (V2) LED
+ | PE27 | SPICS_ER       | Output | External serial register CS
+ | PE28 | LEDIO1         | Output | (V1) LED
+ |      | BKBR1          | Input  | (V2) Keyboard input scan
+ | PE29 | LEDIO2         | Output | (V1) LED hook for A (TA2)
+ |      | BKBR2          | Input  | (V2) Keyboard input scan
+ | PE30 | LEDIO3         | Output | (V1) LED hook for A (TA2)
+ |      | BKBR3          | Input  | (V2) Keyboard input scan
+ | PE31 | F_RY_BY        | Input  | (V1) NAND F_RY_BY
+ |      | BKBR4          | Input  | (V2) Keyboard input scan
+ +------+----------------+--------+---------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+   Serial register input:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ |    0 | BKBR1          | (V1) Keyboard input scan
+ |    1 | BKBR3          | (V1) Keyboard input scan
+ |    2 | BKBR4          | (V1) Keyboard input scan
+ |    3 | BKBR2          | (V1) Keyboard input scan
+ |    4 | HOOK           | (V1) Hook switch
+ |    5 | BT_LINK        | (V1) Bluetooth link status
+ |    6 | HOST_WAKE      | (V1) Bluetooth host wake up
+ |    7 | OK_ETH         | (V1) Cisco inline power OK status
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+   Serial register output:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ |    0 | KEY1           | Keyboard output scan
+ |    1 | KEY2           | Keyboard output scan
+ |    2 | KEY3           | Keyboard output scan
+ |    3 | KEY4           | Keyboard output scan
+ |    4 | KEY5           | Keyboard output scan
+ |    5 | KEY6           | Keyboard output scan
+ |    6 | KEY7           | Keyboard output scan
+ |    7 | BT_WAKE        | Bluetooth wake up
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+ Chip selects:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | CS0  | CS0            | Boot flash
+ | CS1  | CS_FLASH       | NAND flash
+ | CS2  | CS_DSP         | DSP
+ | CS3  | DCS_DRAM       | DRAM
+ | CS4  | CS_FLASH2      | (V2) 2nd flash
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+ Interrupts:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | IRQ1 | IRQ_DSP        | DSP interrupt
+ | IRQ3 | S_INTER        | DUSLIC ???
+ | IRQ4 | F_RY_BY        | NAND
+ | IRQ7 | IRQ_MAX        | MAX 3100 interrupt
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+ Interrupts on PCMCIA pins:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | IP_A0| PHY1_LINK      | Link status changed for #1 Ethernet interface
+ | IP_A1| PHY2_LINK      | Link status changed for #2 Ethernet interface
+ | IP_A2| RMII1_MDINT    | PHY interrupt for #1
+ | IP_A3| RMII2_MDINT    | PHY interrupt for #2
+ | IP_A5| HOST_WAKE      | (V2) Bluetooth host wake
+ | IP_A6| OK_ETH         | (V2) Cisco inline power OK
+ +------+----------------+------------------------------------------------------------
+
+*************************************************************************************************/
+
+#define CONFIG_SED156X			1	/* use SED156X */
+#define CONFIG_SED156X_PG12864Q		1	/* type of display used */
+
+/* serial interfacing macros */
+
+#define SED156X_SPI_RXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define SED156X_SPI_RXD_MASK	0x00000008
+
+#define SED156X_SPI_TXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define SED156X_SPI_TXD_MASK	0x00000004
+
+#define SED156X_SPI_CLK_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define SED156X_SPI_CLK_MASK	0x00000002
+
+#define SED156X_CS_PORT		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define SED156X_CS_MASK		0x00000010
+
+#define SED156X_A0_PORT		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
+#define SED156X_A0_MASK		0x0020
+
+/*************************************************************************************************/
+
+#define CFG_CONSOLE_IS_IN_ENV		1
+#define CFG_CONSOLE_OVERWRITE_ROUTINE	1
+#define CFG_CONSOLE_ENV_OVERWRITE	1
+
+/*************************************************************************************************/
+
+/* use board specific hardware */
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_SHOW_ACTIVITY
+
+/*************************************************************************************************/
+
+/* phone console configuration */
+
+#define PHONE_CONSOLE_POLL_HZ		(CFG_HZ/200)	/* poll every 5ms */
+
+/*************************************************************************************************/
+
+#define CONFIG_CDP_DEVICE_ID		20
+#define CONFIG_CDP_DEVICE_ID_PREFIX	"NP"	/* netphone */
+#define CONFIG_CDP_PORT_ID		"eth%d"
+#define CONFIG_CDP_CAPABILITIES		0x00000010
+#define CONFIG_CDP_VERSION		"u-boot" " " __DATE__ " " __TIME__
+#define CONFIG_CDP_PLATFORM		"Intracom NetPhone"
+#define CONFIG_CDP_TRIGGER		0x20020001
+#define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
+#define CONFIG_CDP_APPLIANCE_VLAN_TYPE	0x01	/* ipphone */
+
+/*************************************************************************************************/
+
+#define CONFIG_AUTO_COMPLETE	1
+
+/*************************************************************************************************/
+
+#define CONFIG_CRC32_VERIFY	1
+
+/*************************************************************************************************/
+
+#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1
+
+/*************************************************************************************************/
+#endif	/* __CONFIG_H */
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
new file mode 100755
index 0000000..1bcd88d
--- /dev/null
+++ b/include/configs/NETTA.h
@@ -0,0 +1,787 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC885		1	/* This is a MPC885 CPU		*/
+#define CONFIG_NETTA		1	/* ...on a NetTA board		*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+/* #define CONFIG_XIN		 10000000 */
+#define CONFIG_XIN		 50000000
+#define MPC8XX_HZ		120000000
+/* #define MPC8XX_HZ		100000000 */
+/* #define MPC8XX_HZ		 50000000 */
+/* #define MPC8XX_HZ		 80000000 */
+
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_HW_WATCHDOG
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK		(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define	CONFIG_NET_MULTI	1 	/* the only way to get the FEC in */
+#define	FEC_ENET		1	/* eth.c needs it that way... */
+#undef  CFG_DISCOVER_PHY		/* do not discover phys */
+#define CONFIG_MII		1
+#define CONFIG_RMII		1	/* use RMII interface */
+
+#if defined(CONFIG_NETTA_ISDN)
+#define CONFIG_ETHER_ON_FEC1	1
+#define CONFIG_FEC1_PHY		1   	/* phy address of FEC1 */
+#define CONFIG_FEC1_PHY_NORXERR 1
+#undef  CONFIG_ETHER_ON_FEC2
+#else
+#define CONFIG_ETHER_ON_FEC1	1
+#define CONFIG_FEC1_PHY		8  	/* phy address of FEC1 */
+#define CONFIG_FEC1_PHY_NORXERR 1
+#define CONFIG_ETHER_ON_FEC2	1
+#define CONFIG_FEC2_PHY		1   	/* phy address of FEC2 */
+#define CONFIG_FEC2_PHY_NORXERR 1
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
+
+/* POST support */
+#define CONFIG_POST		(CFG_POST_MEMORY   | \
+				 CFG_POST_CODEC	   | \
+				 CFG_POST_DSP	   )
+
+#define CONFIG_COMMANDS       ( CONFIG_CMD_DFL	| \
+				CFG_CMD_CDP	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG    | \
+				CFG_CMD_FAT	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_MII 	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCMCIA	| \
+				CFG_CMD_PING  	| \
+				0)
+
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_MISC_INIT_R
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#define CFG_HUSH_PARSER	1
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	0x10000
+
+#define	CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
+#define CFG_ENV_OFFSET		0
+#define	CFG_ENV_SIZE		0x4000
+
+#define CFG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x70000)
+#define CFG_ENV_OFFSET_REDUND	0
+#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+#if CONFIG_XIN == 10000000
+
+#if MPC8XX_HZ == 120000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 100000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 50000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 25000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 40000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 75000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 10MHz
+#endif
+
+#elif CONFIG_XIN == 50000000
+
+#if MPC8XX_HZ == 120000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 100000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ ==  80000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ ==  50000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 50MHz
+#endif
+
+#else
+
+#error unsupported XIN freq
+#endif
+
+
+/*
+ *-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ *
+ * Note: When TBS == 0 the timebase is independent of current cpu clock.
+ */
+
+#define SCCR_MASK	SCCR_EBDF11
+#if MPC8XX_HZ > 66666666
+#define CFG_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL111 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00 | SCCR_EBDF01)
+#else
+#define CFG_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL111 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR3 and OR3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+
+#define CFG_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#if   MPC8XX_HZ == 120000000
+#define CFG_MAMR_PTA		 234
+#elif MPC8XX_HZ == 100000000
+#define CFG_MAMR_PTA		 195
+#elif MPC8XX_HZ ==  80000000
+#define CFG_MAMR_PTA		 156
+#elif MPC8XX_HZ ==  50000000
+#define CFG_MAMR_PTA		  98
+#else
+#error Unknown frequency
+#endif
+
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_ARTOS			/* include ARTOS support */
+
+#define CONFIG_LAST_STAGE_INIT		/* needed to reset the damn phys */
+
+/***********************************************************************************************************
+
+   Pin definitions:
+
+ +------+----------------+--------+------------------------------------------------------------
+ |  #   | Name           | Type   | Comment
+ +------+----------------+--------+------------------------------------------------------------
+ | PA3  | OK_ETH_3V      | Input  | CISCO Ethernet power OK
+ |      |                |        | (NetRoute: FEC1, TA: FEC2) (0=power OK)
+ | PA6  | P_VCCD1        | Output | TPS2211A PCMCIA
+ | PA7  | DCL1_3V        | Periph | IDL1 PCM clock
+ | PA8  | DSP_DR1        | Periph | IDL1 PCM Data Rx
+ | PA9  | L1TXDA         | Periph | IDL1 PCM Data Tx
+ | PA10 | P_VCCD0        | Output | TPS2211A PCMCIA
+ | PA12 | P_SHDN         | Output | TPS2211A PCMCIA
+ | PA13 | ETH_LOOP       | Output | CISCO Loopback remote power
+ |      |                |        | (NetRoute: FEC1, TA: FEC2) (1=NORMAL)
+ | PA14 | P_VPPD0        | Output | TPS2211A PCMCIA
+ | PA15 | P_VPPD1        | Output | TPS2211A PCMCIA
+ | PB14 | SPIEN_FXO      | Output | SPI CS for FXO daughter-board
+ | PB15 | SPIEN_S1       | Output | SPI CS for S-interface 1 (NetRoute only)
+ | PB16 | DREQ1          | Output | D channel request for S-interface chip 1.
+ | PB17 | L1ST3          | Periph | IDL1 timeslot enable signal for PPC
+ | PB18 | L1ST2          | Periph | IDL1 timeslot enable signal for PPC
+ | PB19 | SPIEN_S2       | Output | SPI CS for S-interface 2 (NetRoute only)
+ | PB20 | SPIEN_SEEPROM  | Output | SPI CS for serial eeprom
+ | PB21 | LEDIO          | Output | Led mode indication for PHY
+ | PB22 | UART_CTS       | Input  | UART CTS
+ | PB23 | UART_RTS       | Output | UART RTS
+ | PB24 | UART_RX        | Periph | UART Data Rx
+ | PB25 | UART_TX        | Periph | UART Data Tx
+ | PB26 | RMII-MDC       | Periph | Free for future use (MII mgt clock)
+ | PB27 | RMII-MDIO      | Periph | Free for future use (MII mgt data)
+ | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
+ | PB29 | SPI_TXD        | Output | SPI Data Tx
+ | PB30 | SPI_CLK        | Output | SPI Clock
+ | PB31 | RMII1-REFCLK   | Periph | RMII reference clock for FEC1
+ | PC4  | PHY1_LINK      | Input  | PHY link state FEC1 (interrupt)
+ | PC5  | PHY2_LINK      | Input  | PHY link state FEC2 (interrupt)
+ | PC6  | RMII1-MDINT    | Input  | PHY prog interrupt FEC1 (interrupt)
+ | PC7  | RMII2-MDINT    | Input  | PHY prog interrupt FEC1 (interrupt)
+ | PC8  | P_OC           | Input  | TPS2211A PCMCIA overcurrent (interrupt) (1=OK)
+ | PC9  | COM_HOOK1      | Input  | Codec interrupt chip #1 (interrupt)
+ | PC10 | COM_HOOK2      | Input  | Codec interrupt chip #2 (interrupt)
+ | PC11 | COM_HOOK4      | Input  | Codec interrupt chip #4 (interrupt)
+ | PC12 | COM_HOOK3      | Input  | Codec interrupt chip #3 (interrupt)
+ | PC13 | F_RY_BY        | Input  | NAND ready signal (interrupt)
+ | PC14 | FAN_OK         | Input  | Fan status signal (interrupt) (1=OK)
+ | PC15 | PC15_DIRECT0   | Periph | PCMCIA DMA request.
+ | PD3  | F_ALE          | Output | NAND
+ | PD4  | F_CLE          | Output | NAND
+ | PD5  | F_CE           | Output | NAND
+ | PD6  | DSP_INT        | Output | DSP debug interrupt
+ | PD7  | DSP_RESET      | Output | DSP reset
+ | PD8  | RMII_MDC       | Periph | MII mgt clock
+ | PD9  | SPIEN_C1       | Output | SPI CS for codec #1
+ | PD10 | SPIEN_C2       | Output | SPI CS for codec #2
+ | PD11 | SPIEN_C3       | Output | SPI CS for codec #3
+ | PD12 | FSC2           | Periph | IDL2 frame sync
+ | PD13 | DGRANT2        | Input  | D channel grant from S #2
+ | PD14 | SPIEN_C4       | Output | SPI CS for codec #4
+ | PD15 | TP700          | Output | Testpoint for software debugging
+ | PE14 | RMII2-TXD0     | Periph | FEC2 transmit data
+ | PE15 | RMII2-TXD1     | Periph | FEC2 transmit data
+ | PE16 | RMII2-REFCLK   | Periph | TA: RMII ref clock for
+ |      | DCL2           | Periph | NetRoute: PCM clock #2
+ | PE17 | TP703          | Output | Testpoint for software debugging
+ | PE18 | DGRANT1        | Input  |  D channel grant from S #1
+ | PE19 | RMII2-TXEN     | Periph | TA: FEC2 tx enable
+ |      | PCM2OUT        | Periph | NetRoute: Tx data for IDL2
+ | PE20 | FSC1           | Periph | IDL1 frame sync
+ | PE21 | RMII2-RXD0     | Periph | FEC2 receive data
+ | PE22 | RMII2-RXD1     | Periph | FEC2 receive data
+ | PE23 | L1ST1          | Periph | IDL1 timeslot enable signal for PPC
+ | PE24 | U-N1           | Output | Select user/network for S #1 (0=user)
+ | PE25 | U-N2           | Output | Select user/network for S #2 (0=user)
+ | PE26 | RMII2-RXDV     | Periph | FEC2 valid
+ | PE27 | DREQ2          | Output | D channel request for S #2.
+ | PE28 | FPGA_DONE      | Input  | FPGA done signal
+ | PE29 | FPGA_INIT      | Output | FPGA init signal
+ | PE30 | UDOUT2_3V      | Input  | IDL2 PCM input
+ | PE31 |                |        | Free
+ +------+----------------+--------+---------------------------------------------------
+
+ Chip selects:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | CS0  | CS0            | Boot flash
+ | CS1  | CS_FLASH       | NAND flash
+ | CS2  | CS_DSP         | DSP
+ | CS3  | DCS_DRAM       | DRAM
+ | CS4  | CS_ER1         | External output register
+ +------+----------------+------------------------------------------------------------
+
+ Interrupts:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | IRQ1 | UINTER_3V      | S interupt chips interrupt (common)
+ | IRQ3 | IRQ_DSP        | DSP interrupt
+ | IRQ4 | IRQ_DSP1       | Extra DSP interrupt
+ +------+----------------+------------------------------------------------------------
+
+*************************************************************************************************/
+
+#define DSP_SIZE	0x00010000	/* 64K */
+#define NAND_SIZE	0x00010000	/* 64K */
+#define ER_SIZE		0x00010000	/* 64K */
+#define DUMMY_SIZE	0x00010000	/* 64K */
+
+#define DSP_BASE	0xF1000000
+#define NAND_BASE	0xF1010000
+#define ER_BASE		0xF1020000
+#define DUMMY_BASE	0xF1FF0000
+
+/****************************************************************/
+
+/* NAND */
+#define CFG_NAND_BASE			NAND_BASE
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_MTD_NAND_UNSAFE
+
+#define CFG_MAX_NAND_DEVICE		1
+/* #define NAND_NO_RB */
+
+#define SECTORSIZE		512
+#define ADDR_COLUMN		1
+#define ADDR_PAGE		2
+#define ADDR_COLUMN_PAGE	3
+#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_MAX_FLOORS		1
+#define NAND_MAX_CHIPS		1
+
+/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */
+#define NAND_DISABLE_CE(nand) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 5)); \
+	} while(0)
+
+#define NAND_ENABLE_CE(nand) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \
+	} while(0)
+
+#define NAND_CTL_CLRALE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \
+	} while(0)
+
+#define NAND_CTL_SETALE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 3)); \
+	} while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \
+	} while(0)
+
+#define NAND_CTL_SETCLE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 4)); \
+	} while(0)
+
+#ifndef NAND_NO_RB
+#define NAND_WAIT_READY(nand) \
+	do { \
+		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \
+			WATCHDOG_RESET(); \
+		} \
+	} while (0)
+#else
+#define NAND_WAIT_READY(nand) udelay(12)
+#endif
+
+#define WRITE_NAND_COMMAND(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define WRITE_NAND_ADDRESS(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define WRITE_NAND(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define READ_NAND(adr) \
+	((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
+
+#define CONFIG_JFFS2_NAND	1			/* jffs2 on nand support */
+#define NAND_CACHE_PAGES	16			/* size of nand cache in 512 bytes pages */
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nand0"
+#define CONFIG_JFFS2_PART_SIZE		0x00100000
+#define CONFIG_JFFS2_PART_OFFSET	0x00200000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=netta-nand"
+#define MTDPARTS_DEFAULT	"mtdparts=netta-nand:1m@2m(jffs2)"
+*/
+
+/*****************************************************************************/
+
+#define CFG_DIRECT_FLASH_TFTP
+#define CFG_DIRECT_NAND_TFTP
+
+/*****************************************************************************/
+
+#if 1
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*************************************************************************************************/
+
+#define CONFIG_CDP_DEVICE_ID		20
+#define CONFIG_CDP_DEVICE_ID_PREFIX	"NT"	/* netta */
+#define CONFIG_CDP_PORT_ID		"eth%d"
+#define CONFIG_CDP_CAPABILITIES		0x00000010
+#define CONFIG_CDP_VERSION		"u-boot 1.0" " " __DATE__ " " __TIME__
+#define CONFIG_CDP_PLATFORM		"Intracom NetTA"
+#define CONFIG_CDP_TRIGGER		0x20020001
+#define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
+#define CONFIG_CDP_APPLIANCE_VLAN_TYPE	0x01	/* ipphone? */
+
+/*************************************************************************************************/
+
+#define CONFIG_AUTO_COMPLETE	1
+
+/*************************************************************************************************/
+
+#define CONFIG_CRC32_VERIFY	1
+
+/*************************************************************************************************/
+
+#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1
+
+/*************************************************************************************************/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
new file mode 100755
index 0000000..529cb4c
--- /dev/null
+++ b/include/configs/NETTA2.h
@@ -0,0 +1,762 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if !defined(CONFIG_NETTA2_VERSION) || CONFIG_NETTA2_VERSION > 2
+#error Unsupported CONFIG_NETTA2 version
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC870		1	/* This is a MPC885 CPU		*/
+#define CONFIG_NETTA2		1	/* ...on a NetTA2 board		*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+/* #define CONFIG_XIN		 10000000 */
+#define CONFIG_XIN		 50000000
+/* #define MPC8XX_HZ		120000000 */
+#define MPC8XX_HZ		 66666666
+
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"echo;"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+#define CONFIG_AUTOSCRIPT
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
+
+#define CONFIG_BOOTP_MASK		(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define	CONFIG_NET_MULTI	1 	/* the only way to get the FEC in */
+#define	FEC_ENET		1	/* eth.c needs it that way... */
+#undef CFG_DISCOVER_PHY
+#define CONFIG_MII		1
+#define CONFIG_RMII		1	/* use RMII interface */
+
+#define CONFIG_ETHER_ON_FEC1	1
+#define CONFIG_FEC1_PHY		8 	/* phy address of FEC */
+#define CONFIG_FEC1_PHY_NORXERR 1
+
+#define CONFIG_ETHER_ON_FEC2	1
+#define CONFIG_FEC2_PHY		4
+#define CONFIG_FEC2_PHY_NORXERR 1
+
+#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
+
+#define CONFIG_COMMANDS       ( CONFIG_CMD_DFL	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PING  	| \
+				CFG_CMD_MII 	| \
+				CFG_CMD_CDP	  \
+				)
+
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_MISC_INIT_R
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#define CFG_HUSH_PARSER	1
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#if CONFIG_NETTA2_VERSION == 2
+#define CFG_FLASH_BASE4		0x40080000
+#endif
+
+#define CFG_RESET_ADDRESS   0x80000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#if CONFIG_NETTA2_VERSION == 1
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#elif CONFIG_NETTA2_VERSION == 2
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#endif
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	0x10000
+
+#define	CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
+#define CFG_ENV_OFFSET		0
+#define	CFG_ENV_SIZE		0x4000
+
+#define CFG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x70000)
+#define CFG_ENV_OFFSET_REDUND	0
+#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+#if CONFIG_XIN == 10000000
+
+#if MPC8XX_HZ == 120000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 100000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 50000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 25000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 40000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 75000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 10MHz
+#endif
+
+#elif CONFIG_XIN == 50000000
+
+#if MPC8XX_HZ == 120000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 100000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ ==  66666666
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 50MHz
+#endif
+
+#else
+
+#error unsupported XIN freq
+#endif
+
+
+/*
+ *-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ *
+ * Note: When TBS == 0 the timebase is independent of current cpu clock.
+ */
+
+#define SCCR_MASK	SCCR_EBDF11
+#if MPC8XX_HZ > 66666666
+#define CFG_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00 | SCCR_EBDF01)
+#else
+#define CFG_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+#if CONFIG_NETTA2_VERSION == 2
+
+#define FLASH_BASE4_PRELIM	0x40080000	/* FLASH bank #1	*/
+
+#define CFG_OR4_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR4_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR4_PRELIM	((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+#endif
+
+/*
+ * BR3 and OR3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+
+#define CFG_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_MAMR_PTA		 234
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_ARTOS			/* include ARTOS support */
+
+#define CONFIG_LAST_STAGE_INIT		/* needed to reset the damn phys */
+
+/****************************************************************/
+
+#define DSP_SIZE	0x00010000	/* 64K */
+#define NAND_SIZE	0x00010000	/* 64K */
+
+#define DSP_BASE	0xF1000000
+#define NAND_BASE	0xF1010000
+
+/****************************************************************/
+
+/* NAND */
+#define CFG_NAND_BASE		NAND_BASE
+#define CONFIG_MTD_NAND_ECC_JFFS2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_MTD_NAND_UNSAFE
+
+#define CFG_MAX_NAND_DEVICE	1
+
+#define SECTORSIZE		512
+#define ADDR_COLUMN		1
+#define ADDR_PAGE		2
+#define ADDR_COLUMN_PAGE	3
+#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_MAX_FLOORS		1
+#define NAND_MAX_CHIPS		1
+
+/* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */
+#define NAND_DISABLE_CE(nand) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 20)); \
+	} while(0)
+
+#define NAND_ENABLE_CE(nand) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
+	} while(0)
+
+#define NAND_CTL_CLRALE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
+	} while(0)
+
+#define NAND_CTL_SETALE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 17)); \
+	} while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
+	} while(0)
+
+#define NAND_CTL_SETCLE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) |=  (1 << (31 - 18)); \
+	} while(0)
+
+#if CONFIG_NETTA2_VERSION == 1
+#define NAND_WAIT_READY(nand) \
+	do { \
+		int _tries = 0; \
+		while ((((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
+			if (++_tries > 100000) \
+				break; \
+	} while (0)
+#elif CONFIG_NETTA2_VERSION == 2
+#define NAND_WAIT_READY(nand) \
+	do { \
+		int _tries = 0; \
+		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
+			if (++_tries > 100000) \
+				break; \
+	} while (0)
+#endif
+
+#define WRITE_NAND_COMMAND(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define WRITE_NAND_ADDRESS(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define WRITE_NAND(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define READ_NAND(adr) \
+	((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
+
+/*****************************************************************************/
+
+#define CFG_DIRECT_FLASH_TFTP
+#define CFG_DIRECT_NAND_TFTP
+
+/*****************************************************************************/
+
+#if CONFIG_NETTA2_VERSION == 1
+#define STATUS_LED_BIT		0x00000008		/* bit 28 */
+#elif CONFIG_NETTA2_VERSION == 2
+#define STATUS_LED_BIT		0x00000080		/* bit 24 */
+#endif
+
+#define STATUS_LED_PERIOD	(CFG_HZ / 2)
+#define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */
+
+#ifndef __ASSEMBLY__
+
+/* LEDs */
+
+/* led_id_t is unsigned int mask */
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+	do { \
+		((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat ^= (_msk); \
+	} while(0)
+
+#define __led_set(_msk, _st) \
+	do { \
+		if ((_st)) \
+			((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat |= (_msk); \
+		else \
+			((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
+	} while(0)
+
+#define __led_init(msk, st) __led_set(msk, st)
+
+#endif
+
+/***********************************************************************************************************
+
+ ----------------------------------------------------------------------------------------------
+
+   (V1) version 1 of the board
+   (V2) version 2 of the board
+
+ ----------------------------------------------------------------------------------------------
+
+   Pin definitions:
+
+ +------+----------------+--------+------------------------------------------------------------
+ |  #   | Name           | Type   | Comment
+ +------+----------------+--------+------------------------------------------------------------
+ | PA3  | SPIEN_MAX      | Output | MAX serial to uart chip select
+ | PA7  | DSP_INT        | Output | DSP interrupt
+ | PA10 | DSP_RESET      | Output | DSP reset
+ | PA14 | USBOE          | Output | USB (1)
+ | PA15 | USBRXD         | Output | USB (1)
+ | PB19 | BT_RTS         | Output | Bluetooth (0)
+ | PB23 | BT_CTS         | Output | Bluetooth (0)
+ | PB26 | SPIEN_SEP      | Output | Serial EEPROM chip select
+ | PB27 | SPICS_DISP     | Output | Display chip select
+ | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
+ | PB29 | SPI_TXD        | Output | SPI Data Tx
+ | PB30 | SPI_CLK        | Output | SPI Clock
+ | PC10 | DISPA0         | Output | Display A0
+ | PC11 | BACKLIGHT      | Output | Display backlit
+ | PC12 | SPI2RXD        | Input  | (V1) 2nd SPI RXD
+ |      | IO_RESET       | Output | (V2) General I/O reset
+ | PC13 | SPI2TXD        | Output | (V1) 2nd SPI TXD (V1)
+ |      | HOOK           | Input  | (V2) Hook input interrupt
+ | PC15 | SPI2CLK        | Output | (V1) 2nd SPI CLK
+ |      | F_RY_BY        | Input  | (V2) NAND F_RY_BY
+ | PE17 | F_ALE          | Output | NAND F_ALE
+ | PE18 | F_CLE          | Output | NAND F_CLE
+ | PE20 | F_CE           | Output | NAND F_CE
+ | PE24 | SPICS_SCOUT    | Output | (V1) Codec chip select
+ |      | LED            | Output | (V2) LED
+ | PE27 | SPICS_ER       | Output | External serial register CS
+ | PE28 | LEDIO1         | Output | (V1) LED
+ |      | BKBR1          | Input  | (V2) Keyboard input scan
+ | PE29 | LEDIO2         | Output | (V1) LED hook for A (TA2)
+ |      | BKBR2          | Input  | (V2) Keyboard input scan
+ | PE30 | LEDIO3         | Output | (V1) LED hook for A (TA2)
+ |      | BKBR3          | Input  | (V2) Keyboard input scan
+ | PE31 | F_RY_BY        | Input  | (V1) NAND F_RY_BY
+ |      | BKBR4          | Input  | (V2) Keyboard input scan
+ +------+----------------+--------+---------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+   Serial register input:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ |    4 | HOOK           | Hook switch
+ |    5 | BT_LINK        | Bluetooth link status
+ |    6 | HOST_WAKE      | Bluetooth host wake up
+ |    7 | OK_ETH         | Cisco inline power OK status
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+ Chip selects:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | CS0  | CS0            | Boot flash
+ | CS1  | CS_FLASH       | NAND flash
+ | CS2  | CS_DSP         | DSP
+ | CS3  | DCS_DRAM       | DRAM
+ | CS4  | CS_FLASH2      | (V2) 2nd flash
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+ Interrupts:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | IRQ1 | IRQ_DSP        | DSP interrupt
+ | IRQ3 | S_INTER        | DUSLIC ???
+ | IRQ4 | F_RY_BY        | NAND
+ | IRQ7 | IRQ_MAX        | MAX 3100 interrupt
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+ Interrupts on PCMCIA pins:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | IP_A0| PHY1_LINK      | Link status changed for #1 Ethernet interface
+ | IP_A1| PHY2_LINK      | Link status changed for #2 Ethernet interface
+ | IP_A2| RMII1_MDINT    | PHY interrupt for #1
+ | IP_A3| RMII2_MDINT    | PHY interrupt for #2
+ | IP_A5| HOST_WAKE      | (V2) Bluetooth host wake
+ | IP_A6| OK_ETH         | (V2) Cisco inline power OK
+ +------+----------------+------------------------------------------------------------
+
+**************************************************************************************************/
+
+#define CFG_CONSOLE_IS_IN_ENV		1
+#define CFG_CONSOLE_OVERWRITE_ROUTINE	1
+#define CFG_CONSOLE_ENV_OVERWRITE	1
+
+/*************************************************************************************************/
+
+/* use board specific hardware */
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_SHOW_ACTIVITY
+
+/*************************************************************************************************/
+
+#define CONFIG_CDP_DEVICE_ID		20
+#define CONFIG_CDP_DEVICE_ID_PREFIX	"NT"	/* netta2 */
+#define CONFIG_CDP_PORT_ID		"eth%d"
+#define CONFIG_CDP_CAPABILITIES		0x00000010
+#define CONFIG_CDP_VERSION		"u-boot" " " __DATE__ " " __TIME__
+#define CONFIG_CDP_PLATFORM		"Intracom NetTA2"
+#define CONFIG_CDP_TRIGGER		0x20020001
+#define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
+#define CONFIG_CDP_APPLIANCE_VLAN_TYPE	0x01	/* ipphone ? */
+
+/*************************************************************************************************/
+
+#define CONFIG_AUTO_COMPLETE	1
+
+/*************************************************************************************************/
+
+#define CONFIG_CRC32_VERIFY	1
+
+/*************************************************************************************************/
+
+#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1
+
+/*************************************************************************************************/
+#endif	/* __CONFIG_H */
diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h
new file mode 100755
index 0000000..dc6b15f
--- /dev/null
+++ b/include/configs/NETVIA.h
@@ -0,0 +1,530 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetVia board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_NETVIA		1	/* ...on a NetVia board		*/
+
+#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#else
+#define CONFIG_8xx_CONS_NONE
+#define CONFIG_MAX3100_SERIAL
+#endif
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define CONFIG_XIN		10000000
+#define CONFIG_8xx_GCLK_FREQ	80000000
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
+#endif
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK		(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS_BASE  ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PING )
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+#define CONFIG_COMMANDS		(CONFIG_COMMANDS_BASE | CFG_CMD_NAND)
+#else
+#define CONFIG_COMMANDS		CONFIG_COMMANDS_BASE
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_MISC_INIT_R
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	0x10000
+
+#define	CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
+#define CFG_ENV_OFFSET		0
+#define	CFG_ENV_SIZE		0x4000
+
+#define CFG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x70000)
+#define CFG_ENV_OFFSET_REDUND	0
+#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ *
+ *-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+
+#define SCCR_MASK	SCCR_EBDF11
+
+#if CONFIG_8xx_GCLK_FREQ == 50000000
+
+#define CFG_PLPRCR	( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+#elif CONFIG_8xx_GCLK_FREQ == 80000000
+
+#define CFG_PLPRCR	( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00 | SCCR_EBDF01)
+
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR3 and OR3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+
+#define CFG_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	208
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/* Ethernet at SCC2 */
+#define CONFIG_SCC2_ENET
+
+#define CONFIG_ARTOS			/* include ARTOS support */
+
+/****************************************************************/
+
+#define DSP_SIZE	0x00010000	/* 64K */
+#define FPGA_SIZE	0x00010000	/* 64K */
+
+#define DSP0_BASE	0xF1000000
+#define DSP1_BASE	(DSP0_BASE + DSP_SIZE)
+#define FPGA_BASE	(DSP1_BASE + DSP_SIZE)
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+
+#define ER_SIZE		0x00010000	/* 64K */
+#define ER_BASE		(FPGA_BASE + FPGA_SIZE)
+
+#define NAND_SIZE	0x00010000	/* 64K */
+#define NAND_BASE	(ER_BASE + ER_SIZE)
+
+#endif
+
+/****************************************************************/
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+
+#define STATUS_LED_BIT		0x00000001		/* bit 31 */
+#define STATUS_LED_PERIOD	(CFG_HZ / 2)
+#define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+#define STATUS_LED_BIT1		0x00000002		/* bit 30 */
+#define STATUS_LED_PERIOD1	(CFG_HZ / 2)
+#define STATUS_LED_STATE1	STATUS_LED_OFF
+
+#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */
+
+#endif
+
+/*****************************************************************************/
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+
+/* NAND */
+#define CFG_NAND_BASE			NAND_BASE
+#define CONFIG_MTD_NAND_ECC_JFFS2
+
+#define CFG_MAX_NAND_DEVICE		1
+
+#define SECTORSIZE		512
+#define ADDR_COLUMN		1
+#define ADDR_PAGE		2
+#define ADDR_COLUMN_PAGE	3
+#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_MAX_FLOORS		1
+#define NAND_MAX_CHIPS		1
+
+#define NAND_DISABLE_CE(nand) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  0x0040; \
+	} while(0)
+
+#define NAND_ENABLE_CE(nand) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \
+	} while(0)
+
+#define NAND_CTL_CLRALE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \
+	} while(0)
+
+#define NAND_CTL_SETALE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  0x0100; \
+	} while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \
+	} while(0)
+
+#define NAND_CTL_SETCLE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  0x0080; \
+	} while(0)
+
+#define NAND_WAIT_READY(nand) \
+	do { \
+		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \
+			; \
+	} while (0)
+
+#define WRITE_NAND_COMMAND(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define WRITE_NAND_ADDRESS(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define WRITE_NAND(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define READ_NAND(adr) \
+	((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
+
+#endif
+
+/*****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+
+/* LEDs */
+
+/* last value written to the external register; we cannot read back */
+extern unsigned int last_er_val;
+
+/* led_id_t is unsigned long mask */
+typedef unsigned int led_id_t;
+
+static inline void __led_init(led_id_t mask, int state)
+{
+	unsigned int new_er_val;
+
+	if (state)
+		new_er_val = last_er_val & ~mask;
+	else
+		new_er_val = last_er_val |  mask;
+
+	*(volatile unsigned int *)ER_BASE = new_er_val;
+	last_er_val = new_er_val;
+}
+
+static inline void __led_toggle(led_id_t mask)
+{
+	unsigned int new_er_val;
+
+	new_er_val = last_er_val ^ mask;
+	*(volatile unsigned int *)ER_BASE = new_er_val;
+	last_er_val = new_er_val;
+}
+
+static inline void __led_set(led_id_t mask, int state)
+{
+	unsigned int new_er_val;
+
+	if (state)
+		new_er_val = last_er_val & ~mask;
+	else
+		new_er_val = last_er_val |  mask;
+
+	*(volatile unsigned int *)ER_BASE = new_er_val;
+	last_er_val = new_er_val;
+}
+
+/* MAX3100 console */
+#define MAX3100_SPI_RXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define MAX3100_SPI_RXD_BIT	0x00000008
+
+#define MAX3100_SPI_TXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define MAX3100_SPI_TXD_BIT	0x00000004
+
+#define MAX3100_SPI_CLK_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define MAX3100_SPI_CLK_BIT	0x00000002
+
+#define MAX3100_CS_PORT		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
+#define MAX3100_CS_BIT		0x0010
+
+#endif
+
+#endif
+
+/*************************************************************************************************/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h
new file mode 100755
index 0000000..d994420
--- /dev/null
+++ b/include/configs/NSCU.h
@@ -0,0 +1,461 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
+#define CONFIG_TQM855M		1	/* ...on a TQM8xxM module	*/
+#define CONFIG_NSCU		1
+
+#define	CONFIG_8xx_CONS_SCC1	1	/* Console is on SMC1		*/
+
+#define	CONFIG_66MHz		1	/* running at 66 MHz, 1:1 clock	*/
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/NSCU/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_MISC_INIT_R	  1
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define	CONFIG_ISP1362_USB		/* ISP1362 USB OTG controller	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x08000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+/* NSCU use both slots, SLOT_A as "primary". */
+#define	CONFIG_PCMCIA_SLOT_A 1
+
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define PCMCIA_MEM_WIN_NO 	8 /* override default 4 in pcmcia.h */
+#define	PCMCIA_SOCKETS_NO 	2 /* we have two sockets */
+#undef	NSCU_OE_INV		/* PCMCIA_GCRX_CXOE was inverted on early boards */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		2	/* max. 2 IDE buses		*/
+#define CFG_IDE_MAXDEVICE	4	/* max. 2 drives per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_IDE1_OFFSET	(4 * CFG_PCMCIA_MEM_SIZE) /* starts @ 4th window */
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+#ifdef	CONFIG_ISP1362_USB
+#define	CFG_ISP1362_BASE	0xD0000000	/* ISP1362 mapped at 0xD0000000 */
+#define CFG_ISP1362_OR_AM	0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR5_ISP1362		(CFG_ISP1362_OR_AM | OR_CSNT_SAM | \
+				 OR_ACS_DIV2       | OR_BI       | OR_SCY_5_CLK)
+#define CFG_BR5_ISP1362		((CFG_ISP1362_BASE & BR_BA_MSK) | \
+				 BR_PS_16          | BR_MS_GPCM | BR_V )
+#endif	/* CONFIG_ISP1362_USB */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#undef CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+/* #define CONFIG_ETHPRIME		"FEC ETHERNET" */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/NX823.h b/include/configs/NX823.h
new file mode 100755
index 0000000..1cb8b8f
--- /dev/null
+++ b/include/configs/NX823.h
@@ -0,0 +1,360 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU	    */
+#define CONFIG_NX823		1	/* ...on a NEXUS 823  module	*/
+
+/*#define  CONFIG_VIDEO		1 */
+
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_SPEED
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1	    */
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE 57600	/* console baudrate = 115kbps	*/
+#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds */
+#define CONFIG_BOOTARGS		"ramdisk=8000 "\
+				"root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\
+				"nfsaddrs=10.77.77.20:10.77.77.250"
+#define CONFIG_BOOTCOMMAND	"bootm 400e0000"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled, for now	    */
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+#define CONFIG_COMMANDS	 	(CONFIG_CMD_DFL | CFG_CMD_AUTOSCRIPT)
+#define CONFIG_AUTOSCRIPT
+
+/* call various generic functions */
+#define CONFIG_MISC_INIT_R
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on */
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define CFG_MONITOR_LEN 	(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	    */
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)  */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define xEMBED
+#ifdef	EMBED
+#define CFG_ENV_SIZE		0x200	/* FIXME How big when embedded?? */
+#define CFG_ENV_ADDR		CFG_MONITOR_BASE
+#else
+#define CFG_ENV_ADDR		0x40020000	/* absolute address for now   */
+#define CFG_ENV_SIZE		0x20000 /* 8K ouch, this may later be */
+#endif
+
+#define CFG_FLASH_SN_BASE	0x4001fff0	/* programmer automagically puts    */
+#define CFG_FLASH_SN_SECTOR	0x40000000	/* a serial number here		    */
+#define CFG_FLASH_SN_BYTES	8
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs		*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value    */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				12-30
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				12-16
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		12-18
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		12-23
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		5-7
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define MPC8XX_SPEED	66666666L
+#define MPC8XX_XIN	32768	/* 32.768 kHz crystal */
+#define MPC8XX_FACT		(MPC8XX_SPEED/MPC8XX_XIN)
+#define CFG_PLPRCR_MF  ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
+#define CFG_PLPRCR		(CFG_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		5-3
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0    */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV1 | OR_BI | \
+				 OR_SCY_8_CLK )
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/*
+ * BR1/2 and OR1/2 (SDRAM)
+ */
+#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0    */
+#define SDRAM_BASE2_PRELIM	0x20000000	/* SDRAM bank #1    */
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
+#define CFG_OR_TIMING_SDRAM	(OR_G5LS | OR_CSNT_SAM)
+
+#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CFG_OR2_PRELIM	CFG_OR1_PRELIM
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/* IO and memory mapped stuff */
+#define NX823_IO_OR_AM		0xFFFF0000	/* mask for IO addresses */
+#define NX823_IO_BASE		0xFF000000	/* start of IO	*/
+#define GPOUT_OFFSET		(3<<16)
+#define QUART_OFFSET		(4<<16)
+#define VIDAC_OFFSET		(5<<16)
+#define CPLD_OFFSET		(6<<16)
+#define SED1386_OFFSET		(7<<16)
+
+/*
+ * BR3 and OR3 (general purpose output latches)
+ */
+#define GPOUT_BASE	(NX823_IO_BASE + GPOUT_OFFSET)
+#define GPOUT_TIMING	(OR_CSNT_SAM | OR_TRLX | OR_BI)
+#define CFG_OR3_PRELIM	(NX823_IO_OR_AM | GPOUT_TIMING)
+#define CFG_BR3_PRELIM	(GPOUT_BASE | BR_V)
+
+/*
+ * BR4 and OR4 (QUART)
+ */
+#define QUART_BASE	(NX823_IO_BASE + QUART_OFFSET)
+#define QUART_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)
+#define CFG_OR4_PRELIM	(NX823_IO_OR_AM | QUART_TIMING | OR_BI)
+#define CFG_BR4_PRELIM	(QUART_BASE | BR_PS_8 | BR_V)
+
+/*
+ * BR5 and OR5 (Video DAC)
+ */
+#define VIDAC_BASE	(NX823_IO_BASE + VIDAC_OFFSET)
+#define VIDAC_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
+#define CFG_OR5_PRELIM	(NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
+#define CFG_BR5_PRELIM	(VIDAC_BASE | BR_PS_8 | BR_V)
+
+/*
+ * BR6 and OR6 (CPLD)
+ * FIXME timing not verified for CPLD
+ */
+#define CPLD_BASE	(NX823_IO_BASE + CPLD_OFFSET)
+#define CPLD_TIMING	(OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
+#define CFG_OR6_PRELIM	(NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
+#define CFG_BR6_PRELIM	(CPLD_BASE | BR_PS_8 | BR_V )
+
+/*
+ * BR7 and OR7 (SED1386)
+ * FIXME timing not verified for SED controller
+ */
+#define SED1386_BASE	0xF7000000
+#define CFG_OR7_PRELIM	(0xFF000000 | OR_BI | OR_SETA)
+#define CFG_BR7_PRELIM	(SED1386_BASE | BR_PS_16 | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz   */
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16 /* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32 /* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8	/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16 /* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot	    */
+
+#define CONFIG_ENV_OVERWRITE	/* allow changes to ethaddr (for now)	*/
+#define CONFIG_ETHADDR		00:10:20:30:40:50
+#define CONFIG_IPADDR		10.77.77.20
+#define CONFIG_SERVERIP		10.77.77.250
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
new file mode 100755
index 0000000..aa9d1ba
--- /dev/null
+++ b/include/configs/OCRTC.h
@@ -0,0 +1,302 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_OCRTC		1	/* ...on a OCRTC board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND "go fff00100"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_EEPROM	)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_PCI_BOOTDELAY	1	/* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0410	/* PCI Device ID: OCRTC		*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFD0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
+#define CFG_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/
+
+#else /* Use EEPROM for environment variables */
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
+				   /* total size of a CAT24WC08 is 1024 bytes */
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (PLD - FPGA-boot) initialization				*/
+#define CFG_EBC_PB2AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (PLD - OSL) initialization					*/
+#define CFG_EBC_PB3AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 4 (Spartan2 1) initialization					*/
+#define CFG_EBC_PB4AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB4CR		0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
+
+/* Memory Bank 5 (Spartan2 2) initialization					*/
+#define CFG_EBC_PB5AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB5CR		0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
+
+/* Memory Bank 6 (Virtex 1) initialization					*/
+#define CFG_EBC_PB6AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB6CR		0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 7 (Virtex 2) initialization					*/
+#define CFG_EBC_PB7AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
+
+
+#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h
new file mode 100755
index 0000000..2e7c505
--- /dev/null
+++ b/include/configs/ORSG.h
@@ -0,0 +1,300 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_ORSG		1	/* ...on a ORSG board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND "go fff00100"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_EEPROM	)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter		*/
+#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0411	/* PCI Device ID: ORSG		*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFD0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
+#define CFG_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/
+
+#else /* Use EEPROM for environment variables */
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
+				   /* total size of a CAT24WC08 is 1024 bytes */
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (PLD - FPGA-boot) initialization				*/
+#define CFG_EBC_PB2AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (PLD - OSL) initialization					*/
+#define CFG_EBC_PB3AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 4 (Spartan2 1) initialization					*/
+#define CFG_EBC_PB4AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB4CR		0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
+
+/* Memory Bank 5 (Spartan2 2) initialization					*/
+#define CFG_EBC_PB5AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB5CR		0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
+
+/* Memory Bank 6 (Virtex 1) initialization					*/
+#define CFG_EBC_PB6AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB6CR		0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 7 (Virtex 2) initialization					*/
+#define CFG_EBC_PB7AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
+
+
+#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/OXC.h b/include/configs/OXC.h
new file mode 100755
index 0000000..787407c
--- /dev/null
+++ b/include/configs/OXC.h
@@ -0,0 +1,314 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8240		1
+#define CONFIG_OXC		1
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+#define CONFIG_IDENT_STRING     " [oxc] "
+
+#define CONFIG_WATCHDOG		1
+#define CONFIG_SHOW_ACTIVITY	1
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_ELF)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		1		/* undef to save memory		*/
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_MISC_INIT_R	1		/* call misc_init_r() on init	*/
+
+/*-----------------------------------------------------------------------
+ * Boot options
+ */
+
+#define CONFIG_SERVERIP		10.0.0.1
+#define CONFIG_GATEWAYIP	10.0.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_LOADADDR		0x10000
+#define CONFIG_BOOTFILE		"/mnt/ide0/p2/usr/tftp/oxc.elf"
+#define CONFIG_BOOTCOMMAND	"tftp 0x10000 ; bootelf 0x10000"
+#define CONFIG_BOOTDELAY	10
+
+#define CFG_OXC_GENERATE_IP	1		/* Generate IP automatically	*/
+#define CFG_OXC_IPMASK		0x0A000000	/* 10.0.0.x			*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ */
+
+#define CONFIG_PCI				/* include pci support		*/
+
+#define CONFIG_NET_MULTI			/* Multi ethernet cards support */
+
+#define CONFIG_EEPRO100				/* Ethernet Express PRO 100	*/
+#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+
+#define PCI_ENET0_IOADDR	0x80000000
+#define PCI_ENET0_MEMADDR	0x80000000
+#define	PCI_ENET1_IOADDR	0x81000000
+#define	PCI_ENET1_MEMADDR	0x81000000
+
+/*-----------------------------------------------------------------------
+ * FLASH
+ */
+
+#define CFG_FLASH_PRELIMBASE	0xFF800000
+#define CFG_FLASH_BASE		(0-flash_info[0].size)
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	32	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * RAM
+ */
+
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MAX_RAM_SIZE	0x10000000
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		0x00030000
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_PRELIMBASE)
+# define CFG_RAMBOOT		1
+#else
+# undef CFG_RAMBOOT
+#endif
+
+#define CFG_INIT_RAM_ADDR	0x40000000
+#define CFG_INIT_RAM_END	0x1000
+
+#define CFG_GBL_DATA_SIZE	128
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+
+/*-----------------------------------------------------------------------
+ * Memory mapping
+ */
+
+#define CFG_CPLD_BASE		0xff000000	/* CPLD registers */
+#define CFG_CPLD_WATCHDOG	(CFG_CPLD_BASE)			/* Watchdog */
+#define CFG_CPLD_RESET		(CFG_CPLD_BASE + 0x040000)	/* Minor resets */
+#define CFG_UART_BASE		(CFG_CPLD_BASE + 0x700000)	/* debug UART */
+
+/*-----------------------------------------------------------------------
+ * NS16550 Configuration
+ */
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	-4
+#define CFG_NS16550_CLK		1843200
+#define CFG_NS16550_COM1	CFG_UART_BASE
+
+/*-----------------------------------------------------------------------
+ * I2C Bus
+ */
+
+#define CONFIG_I2C		1		/* I2C support on ... */
+#define CONFIG_HARD_I2C		1		/* ... hardware one */
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F		/* I2C slave address */
+
+#define CFG_I2C_EXPANDER0_ADDR	0x20		/* PCF8574 expander 0 addrerr */
+#define CFG_I2C_EXPANDER1_ADDR	0x21		/* PCF8574 expander 1 addrerr */
+#define CFG_I2C_EXPANDER2_ADDR	0x26		/* PCF8574 expander 2 addrerr */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0xFFF30000	/* Offset of Environment Sector	*/
+#define CFG_ENV_SIZE		0x00010000	/* Total Size of Environment Sector */
+#define	CFG_ENV_IS_EMBEDDED	1		/* short-cut compile-time test	*/
+#define CONFIG_ENV_OVERWRITE    1		/* Allow modifying the environment */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
+#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2
+
+#define CFG_EUMB_ADDR		0xFC000000
+
+/* MCCR1 */
+#define CFG_ROMNAL		0	/* rom/flash next access time		*/
+#define CFG_ROMFAL		19	/* rom/flash access time		*/
+
+/* MCCR2 */
+#define CFG_ASRISE		15	/* ASRISE=15 clocks			*/
+#define CFG_ASFALL		3	/* ASFALL=3 clocks			*/
+#define CFG_REFINT		1000	/* REFINT=1000 clocks			*/
+
+/* MCCR3 */
+#define CFG_BSTOPRE		0x35c	/* Burst To Precharge			*/
+#define CFG_REFREC		7	/* Refresh to activate interval		*/
+#define CFG_RDLAT		4	/* data latency from read command	*/
+
+/* MCCR4 */
+#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
+#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CFG_ACTORW		2	/* Activate to R/W			*/
+#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CFG_SDMODE_BURSTLEN	3	/* SDMODE Burst length 2=4, 3=8		*/
+#define CFG_REGISTERD_TYPE_BUFFER   1
+
+/* memory bank settings*/
+/*
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CFG_BANK0_START		0x00000000
+#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE	1
+#define CFG_BANK1_START		0x00000000
+#define CFG_BANK1_END		0x00000000
+#define CFG_BANK1_ENABLE	0
+#define CFG_BANK2_START		0x00000000
+#define CFG_BANK2_END		0x00000000
+#define CFG_BANK2_ENABLE	0
+#define CFG_BANK3_START		0x00000000
+#define CFG_BANK3_END		0x00000000
+#define CFG_BANK3_ENABLE	0
+#define CFG_BANK4_START		0x00000000
+#define CFG_BANK4_END		0x00000000
+#define CFG_BANK4_ENABLE	0
+#define CFG_BANK5_START		0x00000000
+#define CFG_BANK5_END		0x00000000
+#define CFG_BANK5_ENABLE	0
+#define CFG_BANK6_START		0x00000000
+#define CFG_BANK6_END		0x00000000
+#define CFG_BANK6_ENABLE	0
+#define CFG_BANK7_START		0x00000000
+#define CFG_BANK7_END		0x00000000
+#define CFG_BANK7_ENABLE	0
+/*
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CFG_BANK_ENABLE		0x01
+
+#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+					/* see 8240 book for bit definitions	*/
+#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+/* SDRAM 0 - 256MB */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* PCI memory */
+#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h
new file mode 100755
index 0000000..a933e1b
--- /dev/null
+++ b/include/configs/P3G4.h
@@ -0,0 +1,426 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifndef __ASSEMBLY__
+#include <galileo/core.h>
+#endif
+
+#include "../board/evb64260/local.h"
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_P3G4		1	/* this is a P3G4  board	*/
+#define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
+
+#define CONFIG_BAUDRATE		115200 	/* console baudrate = 115200	*/
+
+#undef	CONFIG_ECC			/* enable ECC support */
+/* #define CONFIG_EVB64260_750CX  1 */      /* Support the EVB-64260-750CX Board */
+
+/* which initialization functions to call for this board */
+#define CONFIG_MISC_INIT_R	1
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+#define CFG_BOARD_NAME		"P3G4"
+
+#undef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
+ * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
+ */
+#define	CONFIG_MPSC
+#define CONFIG_MPSC_PORT	0
+
+#define CONFIG_NET_MULTI        /* attempt all available adapters */
+
+/* define this if you want to enable GT MAC filtering */
+#define CONFIG_GT_USE_MAC_HASH_TABLE
+
+#undef CONFIG_ETHER_PORT_MII	/* use RMII */
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=p3g4\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_74xx\0"					\
+	"bootfile=/tftpboot/p3g4/uImage\0"				\
+	"kernel_addr=ff000000\0"					\
+	"ramdisk_addr=ff010000\0"					\
+	"load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0"			\
+	"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;"	\
+		"cp.b 100000 fff00000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#define	CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_ALTIVEC                  /* undef to disable             */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE)
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_UNIVERSE| \
+				CFG_CMD_BSP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x00300000	/* default load address	*/
+
+#define	CFG_HZ			1000		/* decr freq: 1ms ticks	*/
+#define CFG_BUS_HZ		133000000	/* 133 MHz		*/
+#define CFG_BUS_CLK		CFG_BUS_HZ
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_RAM_ADDR	0x40000000
+#define	CFG_INIT_RAM_END	0x1000
+#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_RAM_LOCK
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xff000000
+#define CFG_RESET_ADDRESS	0xfff00100
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+
+/* areas to map different things with the GT in physical space */
+#define CFG_DRAM_BANKS		1
+#define CFG_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
+
+/* What to put in the bats. */
+#define CFG_MISC_REGION_BASE	0xf0000000
+
+/* Peripheral Device section */
+#define CFG_GT_REGS		0xf8000000
+#define CFG_DEV_BASE		0xff000000
+
+#define CFG_DEV0_SPACE		CFG_DEV_BASE
+#define CFG_DEV1_SPACE		(CFG_DEV0_SPACE + CFG_DEV0_SIZE)
+#define CFG_DEV2_SPACE		(CFG_DEV1_SPACE + CFG_DEV1_SIZE)
+#define CFG_DEV3_SPACE		(CFG_DEV2_SPACE + CFG_DEV2_SIZE)
+
+#define CFG_DEV0_SIZE		 _8M /* Flash bank */
+#define CFG_DEV1_SIZE		 0   /* unused */
+#define CFG_DEV2_SIZE		 0   /* unused */
+#define CFG_DEV3_SIZE		 0   /* unused */
+
+#define CFG_16BIT_BOOT_PAR	0xc01b5e7c
+#define CFG_DEV0_PAR		CFG_16BIT_BOOT_PAR
+
+#if 0 /* Wrong?? NTL */
+#define CFG_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
+						/* DMAAck[1:0] GNT0[1:0] */
+#else
+#define CFG_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
+						/* REQ0[1:0] GNT0[1:0] */
+#endif
+#define CFG_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
+						/* DMAReq[4] DMAAck[4] WDNMI WDE */
+#if 0 /* Wrong?? NTL */
+#define CFG_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
+						/* DMAAck[1:0] GNT1[1:0] */
+#else
+#define CFG_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
+						/* GPP[22] (RS232IntB or PCI1Int) */
+						/* GPP[21] (RS323IntA) */
+						/* BClkIn */
+						/* REQ1[1:0] GNT1[1:0] */
+#endif
+
+#if 0 /* Wrong?? NTL */
+# define CFG_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
+						/* GPP[27:26] Int[1:0] */
+#else
+# define CFG_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
+						/* GPP[29]    (PCI1Int) */
+						/* BClkOut0 */
+						/* GPP[27]    (PCI0Int) */
+						/* GPP[26]    (RtcInt or PCI1Int) */
+						/* CPUInt[25:24] */
+#endif
+
+#define CFG_SERIAL_PORT_MUX	0x00001102	/* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
+
+#if 0 /* Wrong?? - NTL */
+# define CFG_GPP_LEVEL_CONTROL	0x000002c6
+#else
+# define CFG_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
+						/* gpp[29] */
+						/* gpp[27:26] */
+						/* gpp[22:21] */
+
+# define CFG_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
+				/* idmas use buffer 1,1
+				   comm use buffer 0
+				   pci use buffer 1,1
+				   cpu use buffer 0
+				   normal load (see also ifdef HVL)
+				   standard SDRAM (see also ifdef REG)
+				   non staggered refresh */
+				/* 31:26  25 23  20 19 18 16 */
+				/* 110110 00 111 0  0  00 1 */
+				/* refresh_count=0x200
+				   phisical interleaving disable
+				   virtual interleaving enable */
+				/* 15 14 13:0 */
+				/* 1  0  0x200 */
+#endif
+
+#if 0
+#define CFG_DUART_IO		CFG_DEV2_SPACE
+#define CFG_DUART_CHAN		1		/* channel to use for console */
+#endif
+#undef CFG_INIT_CHAN1
+#undef CFG_INIT_CHAN2
+#if 0
+#define SRAM_BASE		CFG_DEV0_SPACE
+#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI                      /* include pci support          */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
+
+/* PCI MEMORY MAP section */
+#define CFG_PCI0_MEM_BASE	0x80000000
+#define CFG_PCI0_MEM_SIZE	_128M
+#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
+
+#define CFG_PCI1_MEM_BASE	0x88000000
+#define CFG_PCI1_MEM_SIZE	_128M
+#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+
+/* PCI I/O MAP section */
+#define CFG_PCI0_IO_BASE	0xfa000000
+#define CFG_PCI0_IO_SIZE	_16M
+#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
+#define CFG_PCI0_IO_SPACE_PCI	0x00000000
+
+#define CFG_PCI1_IO_BASE	0xfb000000
+#define CFG_PCI1_IO_SIZE	_16M
+#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
+#define CFG_PCI1_IO_SPACE_PCI	0x00000000
+
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+
+/* SDRAM */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT0U CFG_IBAT0U
+
+/* init ram */
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+
+/* PCI0, PCI1 in one BAT */
+#define CFG_IBAT2L BATL_NO_ACCESS
+#define CFG_IBAT2U CFG_DBAT2U
+#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U CFG_IBAT3U
+
+/* I2C speed and slave address (for compatability) defaults */
+#define CFG_I2C_SPEED	400000
+#define CFG_I2C_SLAVE	0x7F
+
+/* I2C addresses for the two DIMM SPD chips */
+#ifndef CONFIG_EVB64260_750CX
+#define DIMM0_I2C_ADDR	0x56
+#define DIMM1_I2C_ADDR	0x54
+#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
+#define DIMM0_I2C_ADDR  0x54
+#define DIMM1_I2C_ADDR	0x54
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+
+#define CFG_EXTRA_FLASH_DEVICE	BOOT_DEVICE
+#define CFG_EXTRA_FLASH_WIDTH	2	/* 16 bit */
+#define CFG_BOOT_FLASH_WIDTH	2	/* 16 bit */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_CFI		1
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR		0xFFFE0000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/74xx_7xx.h for the defines used here
+ */
+
+#define CFG_L2
+
+#define L2_INIT  	(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		    */
+
+#define CFG_BOARD_ASM_INIT      1
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
new file mode 100755
index 0000000..d88fff3
--- /dev/null
+++ b/include/configs/PATI.h
@@ -0,0 +1,280 @@
+/*
+ * (C) Copyright 2003
+ * Denis Peter d.peter@mpl.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation,
+ */
+
+/*
+ * File:		PATI.h
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_MPC555		1		/* This is an MPC555 CPU		*/
+#define CONFIG_PATI		1		/* ...On a PATI board 	*/
+/* Serial Console Configuration */
+#define	CONFIG_5xx_CONS_SCI1
+#undef	CONFIG_5xx_CONS_SCI2
+
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_COMMANDS		(CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | 		\
+				 CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ENV |  CFG_CMD_REGINFO	| 		\
+				 CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_RUN | CFG_CMD_BSP |	\
+				 CFG_CMD_IMI | CFG_CMD_EEPROM  | CFG_CMD_IRQ | CFG_CMD_MISC \
+)
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if 0
+#define CONFIG_BOOTDELAY	-1		/* autoboot disabled			*/
+#else
+#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds		*/
+#endif
+#define CONFIG_BOOTCOMMAND	"" 	/* autoboot command			*/
+
+#define CONFIG_BOOTARGS		""		/* */
+
+#define CONFIG_WATCHDOG				/* turn on platform specific watchdog 	*/
+
+/*#define CONFIG_STATUS_LED	1		*/ /* Enable status led */
+
+#define CONFIG_LOADS_ECHO	1		/* Echo on for serial download */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
+#define CONFIG_PREBOOT
+
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"pati=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	       /* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00010000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x00A00000	/* 10 MB in SRAM			*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address		*/
+
+#define	CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
+
+
+/***********************************************************************
+ * Last Stage Init
+ ***********************************************************************/
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * Low Level Configuration Settings
+ */
+
+/*
+ * Internal Memory Mapped (This is not the IMMR content)
+ */
+#define CFG_IMMR		0x01C00000				/* Physical start adress of internal memory map */
+
+/*
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_RAM_ADDR	(CFG_IMMR + 0x003f9800)      		/* Physical start adress of internal MPC555 writable RAM */
+#define	CFG_INIT_RAM_END	(CFG_IMMR + 0x003fffff)       		/* Physical end adress of internal MPC555 used RAM area	*/
+#define	CFG_GBL_DATA_SIZE	128					/* Size in bytes reserved for initial global data */
+#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
+#define	CFG_INIT_SP_ADDR	(CFG_IMMR + 0x03fa000)			/* Physical start adress of inital stack */
+/*
+ * Start addresses for the final memory configuration
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000	/* Monitor won't change memory map 			*/
+#define CFG_FLASH_BASE		0xffC00000	/* External flash */
+#define PCI_BASE		0x03000000	/* PCI Base (CS2) */
+#define PCI_CONFIG_BASE		0x04000000	/* PCI & PLD  (CS3) */
+#define PLD_CONFIG_BASE		0x04001000	/* PLD  (CS3) */
+
+#define	CFG_MONITOR_BASE	0xFFF00000
+/* CFG_FLASH_BASE	*/ /* TEXT_BASE is defined in the board config.mk file. 	*/
+						/* This adress is given to the linker with -Ttext to 	*/
+						/* locate the text section at this adress. 		*/
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 192 kB for Monitor				*/
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()				*/
+
+#define CFG_RESET_ADDRESS	(PLD_CONFIG_BASE + 0x10)	 /* Adress which causes reset */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/
+
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ *-----------------------------------------------------------------------
+ *
+ */
+
+#define CFG_MAX_FLASH_BANKS		1		/* Max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT		128		/* Max number of sectors on one chip 	*/
+#define CFG_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms) 	*/
+#define CFG_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms) 	*/
+
+
+#define	CFG_ENV_IS_IN_EEPROM
+#ifdef	CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_OFFSET		0
+#define CFG_ENV_SIZE		2048
+#endif
+
+#undef  CFG_ENV_IS_IN_FLASH
+#ifdef	CFG_ENV_IS_IN_FLASH
+#define	CFG_ENV_SIZE		0x00002000		/* Set whole sector as env 		*/
+#define CFG_ENV_OFFSET		((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) 		/* Environment starts at this adress 	*/
+#endif
+
+
+#define CONFIG_SPI		1
+#define CFG_SPI_CS_USED	0x09 /* CS0 and CS3 are used */
+#define CFG_SPI_CS_BASE	0x08 /* CS3 is active low */
+#define CFG_SPI_CS_ACT	0x00 /* CS3 is active low */
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * SW Watchdog freeze
+ */
+#undef CONFIG_WATCHDOG
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWP)
+#endif	/* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+#define CFG_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
+			 SCCR_COM01   | SCCR_DFNL000 | SCCR_DFNH000)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration
+ *-----------------------------------------------------------------------
+ * Data show cycle
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle 	*/
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register
+ *-----------------------------------------------------------------------
+ * Set all bits to 40 Mhz
+ *
+ */
+#define CFG_OSC_CLK   	((uint)4000000) 	/* Oscillator clock is 4MHz 	*/
+
+
+#define CFG_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
+
+/*-----------------------------------------------------------------------
+ * UMCR - UIMB Module Configuration Register
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_UMCR	(UMCR_FSPEED) 		/* IMB clock same as U-bus 	*/
+
+/*-----------------------------------------------------------------------
+ * ICTRL - I-Bus Support Control Register
+ */
+#define CFG_ICTRL	(ICTRL_ISCT_SER_7) 	/* Take out of serialized mode 	*/
+
+/*-----------------------------------------------------------------------
+ * USIU - Memory Controller Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
+#define CFG_OR0_PRELIM		(0xffc00000) /* SCY is not used if external TA is set */
+/* SDRAM */
+#define CFG_BR1_PRELIM		(CFG_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
+#define CFG_OR1_PRELIM		(OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
+/* PCI */
+#define CFG_BR2_PRELIM		(PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
+#define CFG_OR2_PRELIM		(OR_ADDR_MK_FF)
+/* config registers: */
+#define CFG_BR3_PRELIM		(PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
+#define CFG_OR3_PRELIM		(0xffff0000)
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* We don't realign the flash	*/
+
+/*-----------------------------------------------------------------------
+ * DER - Timer Decrementer
+ *-----------------------------------------------------------------------
+ * Initialise to zero
+ */
+#define CFG_DER			0x00000000
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01			/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02			/* Software reboot			*/
+
+
+#define VERSION_TAG "released"
+#define CONFIG_ISO_STRING "MEV-10084-001"
+
+#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
new file mode 100755
index 0000000..9d5c4f4
--- /dev/null
+++ b/include/configs/PCI405.h
@@ -0,0 +1,355 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_IDENT_STRING     " $Name: esd_PCI405_05_07_28 $"
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_PCI405		1	/* ...on a PCI405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r() on init	*/
+
+#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	0	/* autoboot after 0 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"mem_linux=14336k\0"					        \
+	"optargs=panic=0\0"					        \
+	"ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0"	\
+	"addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
+	""
+#define	CONFIG_BOOTCOMMAND      "run ramargs;run addcon;loadpci"
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+
+#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_EEPROM	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+#define CONFIG_PRAM		2048	/* reserve 2 MB "protected RAM" */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#define CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0407	/* PCI Device ID: PCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0280	/* PCI Class Code: Network/Other*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+
+#if 0 /* test-only */
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#else
+#define CFG_PCI_PTM2LA	0xef600000	/* point to internal regs	*/
+#define CFG_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x00000000	/* Host: use this pci address	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFD0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#define CFG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))	/* Env	*/
+
+#else /* Use EEPROM for environment variables */
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars*/
+				   /* total size of a CAT24WC08 is 1024 bytes */
+#endif
+
+#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (NVRAM/RTC) initialization					*/
+#define CFG_EBC_PB1AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
+#define CFG_EBC_PB1CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+/*#define CFG_EBC_PB2AP		  0x038056C0  / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (FPGA internal) initialization					*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF041C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
+#define CFG_FPGA_BASE_ADDR	0xF0400000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CFG_FPGA_MODE		0x00
+#define CFG_FPGA_STATUS		0x02
+#define CFG_FPGA_TS		0x04
+#define CFG_FPGA_TS_LOW		0x06
+#define CFG_FPGA_TS_CAP0	0x10
+#define CFG_FPGA_TS_CAP0_LOW	0x12
+#define CFG_FPGA_TS_CAP1	0x14
+#define CFG_FPGA_TS_CAP1_LOW	0x16
+#define CFG_FPGA_TS_CAP2	0x18
+#define CFG_FPGA_TS_CAP2_LOW	0x1a
+#define CFG_FPGA_TS_CAP3	0x1c
+#define CFG_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CFG_FPGA_MODE_CF_RESET	0x0001
+#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CFG_FPGA_MODE_TS_CLEAR	0x2000
+
+/* FPGA Status Reg */
+#define CFG_FPGA_STATUS_DIP0	0x0001
+#define CFG_FPGA_STATUS_DIP1	0x0002
+#define CFG_FPGA_STATUS_DIP2	0x0004
+#define CFG_FPGA_STATUS_FLASH	0x0008
+#define CFG_FPGA_STATUS_TS_IRQ	0x1000
+
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
+/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support)   */
+#define CFG_FPGA_INIT_V12	0x00008000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE_V12	0x00010000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#if 0 /* test-only */
+#define CFG_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#else
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h
new file mode 100755
index 0000000..3a7f7f0
--- /dev/null
+++ b/include/configs/PCI5441.h
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU
+ *----------------------------------------------------------------------*/
+#define	CONFIG_PCI5441		1		/* PCI-5441 board	*/
+#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
+
+#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CFG_NIOS_SYSID_BASE	0x00920828	/* System id address	*/
+#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
+
+/*------------------------------------------------------------------------
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ *----------------------------------------------------------------------*/
+#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+
+/*------------------------------------------------------------------------
+ * MEMORY BASE ADDRESSES
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION
+ * 	-Monitor at top.
+ * 	-The heap is placed below the monitor.
+ * 	-Global data is placed below the heap.
+ * 	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128k		*/
+#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
+ * CFG_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ *----------------------------------------------------------------------*/
+#define	CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
+#define CFG_ENV_ADDR 	(CFG_RESET_ADDR + CFG_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CONSOLE_JTAG)
+#define CFG_NIOS_CONSOLE	0x00920820	/* JTAG UART base addr	*/
+#else
+#define CFG_NIOS_CONSOLE	0x009208a0	/* UART base addr	*/
+#endif
+
+#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
+#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+
+/*------------------------------------------------------------------------
+ * DEBUG
+ *----------------------------------------------------------------------*/
+#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
+
+/*------------------------------------------------------------------------
+ * TIMEBASE --
+ *
+ * The high res timer defaults to 1 msec. Since it includes the period
+ * registers, we can slow it down to 10 msec using TMRCNT. If the default
+ * period is acceptable, TMRCNT can be left undefined.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_TMRBASE	0x00920860	/* Tick timer base addr	*/
+#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CFG_NIOS_TMRCNT	(CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define	CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS		(CFG_CMD_BDI	| \
+				 CFG_CMD_ECHO	| \
+				 CFG_CMD_ENV	| \
+				 CFG_CMD_FLASH	| \
+				 CFG_CMD_IMI	| \
+				 CFG_CMD_IRQ	| \
+				 CFG_CMD_LOADS	| \
+				 CFG_CMD_LOADB	| \
+				 CFG_CMD_MEMORY	| \
+				 CFG_CMD_MISC	| \
+				 CFG_CMD_RUN	| \
+				 CFG_CMD_SAVES	)
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define	CFG_LONGHELP				/* Provide extended help*/
+#define	CFG_PROMPT		"==> "		/* Command prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O buf size	*/
+#define	CFG_MAXARGS		16	    	/* Max command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE 	/* Boot arg buf size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size	*/
+#define	CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address	*/
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
+#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h
new file mode 100755
index 0000000..d03706e
--- /dev/null
+++ b/include/configs/PCIPPC2.h
@@ -0,0 +1,267 @@
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * Configuration settings for the PCIPPC-2 board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_PCIPPC2		1	/* this is a PCIPPC2 board	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_MISC_INIT_R	1
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_PREBOOT		""
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DOC	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_SNTP	)
+
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1	/* PCI plug-and-play */
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+/* Print Buffer Size
+ */
+#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+#define	CFG_MAXARGS	64		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE	    0x00000000
+#define CFG_FLASH_BASE	    0xFFF00000
+#define CFG_FLASH_MAX_SIZE  0x00100000
+/* Maximum amount of RAM.
+ */
+#define CFG_MAX_RAM_SIZE    0x20000000  /* 512Mb			*/
+
+#define CFG_RESET_ADDRESS   0xFFF00100
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+
+#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+
+#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
+    CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+/* Size in bytes reserved for initial data
+ */
+#define CFG_GBL_DATA_SIZE    128
+
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x8000
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET    CFG_GBL_DATA_OFFSET
+
+#define CFG_INIT_RAM_LOCK
+
+/*
+ * Temporary buffer for serial data until the real serial driver
+ * is initialised (memtest will destroy this buffer)
+ */
+#define CFG_SCONSOLE_ADDR     CFG_INIT_RAM_ADDR
+#define CFG_SCONSOLE_SIZE     0x0002000
+
+/* SDRAM 0 - 256MB
+ */
+#define CFG_DBAT0L	      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U	      (CFG_SDRAM_BASE | \
+			       BATU_BL_256M | BATU_VS | BATU_VP)
+/* SDRAM 1 - 256MB
+ */
+#define CFG_DBAT1L	      ((CFG_SDRAM_BASE + 0x10000000) | \
+			       BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_DBAT1U	      ((CFG_SDRAM_BASE + 0x10000000) | \
+			       BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Init RAM in the CPU DCache (no backing memory)
+ */
+#define CFG_DBAT2L	      (CFG_INIT_RAM_ADDR | \
+			       BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_DBAT2U	      (CFG_INIT_RAM_ADDR | \
+			       BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* I/O and PCI memory at 0xf0000000
+ */
+#define CFG_DBAT3L	      (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_DBAT3U	      (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT0L	      CFG_DBAT0L
+#define CFG_IBAT0U	      CFG_DBAT0U
+#define CFG_IBAT1L	      CFG_DBAT1L
+#define CFG_IBAT1U	      CFG_DBAT1U
+#define CFG_IBAT2L	      CFG_DBAT2L
+#define CFG_IBAT2U	      CFG_DBAT2U
+#define CFG_IBAT3L	      CFG_DBAT3L
+#define CFG_IBAT3U	      CFG_DBAT3U
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the PCIPPC2 user's manual.
+ */
+#define CFG_HZ		      1000
+#define CFG_BUS_HZ            100000000 /* bus speed - 100 mhz          */
+#define CFG_CPU_CLK	      300000000
+#define CFG_BUS_CLK	      100000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	      (8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CFG_MAX_FLASH_SECT	16	/* Max number of sectors in one bank	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+/*
+ * Note: environment is not EMBEDDED in the U-Boot code.
+ * It's stored in flash separately.
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x70000)
+#define CFG_ENV_SIZE		0x1000	/* Size of the Environment		*/
+#define CFG_ENV_SECT_SIZE	0x10000 /* Size of the Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * L2 cache
+ */
+#undef CFG_L2
+#define L2_INIT   (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+		   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#define L2_ENABLE (L2_INIT | L2CR_L2E)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+/*-----------------------------------------------------------------------
+ * Disk-On-Chip configuration
+ */
+
+#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+
+#define CFG_DOC_SUPPORT_2000
+#undef CFG_DOC_SUPPORT_MILLENNIUM
+
+/*-----------------------------------------------------------------------
+  RTC m48t59
+*/
+#define CONFIG_RTC_MK48T59
+
+#define CONFIG_WATCHDOG
+
+#define CONFIG_NET_MULTI			/* Multi ethernet cards support */
+
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_TULIP
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h
new file mode 100755
index 0000000..92b2f7c
--- /dev/null
+++ b/include/configs/PCIPPC6.h
@@ -0,0 +1,281 @@
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * Configuration settings for the PCIPPC-6 board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_PCIPPC2		1	/* this is a PCIPPC2 board	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_MISC_INIT_R	1
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_PREBOOT		""
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_COMMANDS        (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DOC	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_SCSI	| \
+				CFG_CMD_SNTP	)
+
+
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1	/* PCI plug-and-play */
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+/* Print Buffer Size
+ */
+#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+#define CFG_MAXARGS	64		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE	    0x00000000
+#define CFG_FLASH_BASE	    0xFFF00000
+#define CFG_FLASH_MAX_SIZE  0x00100000
+/* Maximum amount of RAM.
+ */
+#define CFG_MAX_RAM_SIZE    0x20000000	/* 512Mb			*/
+
+#define CFG_RESET_ADDRESS   0xFFF00100
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+
+#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+
+#if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
+    CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+/* Size in bytes reserved for initial data
+ */
+#define CFG_GBL_DATA_SIZE    128
+
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x8000
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET    CFG_GBL_DATA_OFFSET
+
+#define CFG_INIT_RAM_LOCK
+
+/*
+ * Temporary buffer for serial data until the real serial driver
+ * is initialised (memtest will destroy this buffer)
+ */
+#define CFG_SCONSOLE_ADDR     CFG_INIT_RAM_ADDR
+#define CFG_SCONSOLE_SIZE     0x0002000
+
+/* SDRAM 0 - 256MB
+ */
+#define CFG_DBAT0L	      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U	      (CFG_SDRAM_BASE | \
+			       BATU_BL_256M | BATU_VS | BATU_VP)
+/* SDRAM 1 - 256MB
+ */
+#define CFG_DBAT1L	      ((CFG_SDRAM_BASE + 0x10000000) | \
+			       BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_DBAT1U	      ((CFG_SDRAM_BASE + 0x10000000) | \
+			       BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Init RAM in the CPU DCache (no backing memory)
+ */
+#define CFG_DBAT2L	      (CFG_INIT_RAM_ADDR | \
+			       BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_DBAT2U	      (CFG_INIT_RAM_ADDR | \
+			       BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* I/O and PCI memory at 0xf0000000
+ */
+#define CFG_DBAT3L	      (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_DBAT3U	      (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT0L	      CFG_DBAT0L
+#define CFG_IBAT0U	      CFG_DBAT0U
+#define CFG_IBAT1L	      CFG_DBAT1L
+#define CFG_IBAT1U	      CFG_DBAT1U
+#define CFG_IBAT2L	      CFG_DBAT2L
+#define CFG_IBAT2U	      CFG_DBAT2U
+#define CFG_IBAT3L	      CFG_DBAT3L
+#define CFG_IBAT3U	      CFG_DBAT3U
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the PCIPPC2 user's manual.
+ */
+#define CFG_HZ		      1000
+#define CFG_BUS_HZ	      100000000 /* bus speed - 100 mhz		*/
+#define CFG_CPU_CLK	      300000000
+#define CFG_BUS_CLK	      100000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	      (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CFG_MAX_FLASH_SECT	16	/* Max number of sectors in one bank	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+/*
+ * Note: environment is not EMBEDDED in the U-Boot code.
+ * It's stored in flash separately.
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x70000)
+#define CFG_ENV_SIZE		0x1000	/* Size of the Environment		*/
+#define CFG_ENV_SECT_SIZE	0x10000 /* Size of the Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * L2 cache
+ */
+#undef CFG_L2
+#define L2_INIT	  (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+		   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#define L2_ENABLE (L2_INIT | L2CR_L2E)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+/*-----------------------------------------------------------------------
+ * Disk-On-Chip configuration
+ */
+
+#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+
+#define CFG_DOC_SUPPORT_2000
+#undef CFG_DOC_SUPPORT_MILLENNIUM
+
+/*-----------------------------------------------------------------------
+  RTC m48t59
+*/
+#define CONFIG_RTC_MK48T59
+
+#define CONFIG_WATCHDOG
+
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support */
+
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_TULIP
+
+
+#define CONFIG_SCSI_SYM53C8XX
+#define CONFIG_SCSI_DEV_ID	0x000B	/* 53c896 */
+#define CFG_SCSI_MAX_LUN	8	/* number of supported LUNs */
+#define CFG_SCSI_MAX_SCSI_ID	15	/* maximum SCSI ID (0..6) */
+#define CFG_SCSI_MAX_DEVICE	CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
+#define CFG_SCSI_SPIN_UP_TIME	2
+#define CFG_SCSI_SCAN_BUS_REVERSE 0
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
new file mode 100755
index 0000000..9668fb0
--- /dev/null
+++ b/include/configs/PIP405.h
@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/***********************************************************
+ * High Level Configuration Options
+ * (easy to change)
+ ***********************************************************/
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_PIP405		1	/* ...on a PIP405 board		*/
+/***********************************************************
+ * Clock
+ ***********************************************************/
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
+
+/***********************************************************
+ * Command definitions
+ ***********************************************************/
+#define CONFIG_COMMANDS		\
+		       (CONFIG_CMD_DFL	| \
+			CFG_CMD_IDE	| \
+			CFG_CMD_DHCP	| \
+			CFG_CMD_PCI	| \
+			CFG_CMD_CACHE	| \
+			CFG_CMD_IRQ	| \
+			CFG_CMD_ECHO	| \
+			CFG_CMD_EEPROM	| \
+			CFG_CMD_I2C	| \
+			CFG_CMD_REGINFO | \
+			CFG_CMD_FDC	| \
+			CFG_CMD_SCSI	| \
+			CFG_CMD_FAT 	| \
+			CFG_CMD_DATE	| \
+			CFG_CMD_ELF	| \
+			CFG_CMD_USB	| \
+			CFG_CMD_MII	| \
+			CFG_CMD_SDRAM	| \
+			CFG_CMD_DOC	| \
+			CFG_CMD_PING	| \
+			CFG_CMD_SAVES   | \
+			CFG_CMD_BSP	)
+/* this must be included AFTER the definition of CONFIG_COMMANDS  (if any) */
+#include <cmd_confdefs.h>
+
+#define	 CFG_HUSH_PARSER
+#define	 CFG_PROMPT_HUSH_PS2 "> "
+/**************************************************************
+ * I2C Stuff:
+ * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
+ * 0x53.
+ * Caution: on the same bus is the SPD (Serial Presens Detect
+ * EEPROM of the SDRAM
+ * The Atmel EEPROM uses 16Bit addressing.
+ ***************************************************************/
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		50000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x53
+#define CFG_I2C_EEPROM_ADDR_LEN	2
+#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE            0x800   /* 2 kBytes may be used for env vars */
+
+#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#define CFG_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
+					/* 64 byte page write mode using*/
+					/* last	6 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_ENABLE	/* enable Page write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+
+/***************************************************************
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ ***************************************************************/
+#define SPD_EEPROM_ADDRESS      0x50
+
+#define CONFIG_BOARD_EARLY_INIT_F
+/**************************************************************
+ * Environment definitions
+ **************************************************************/
+#define CONFIG_BAUDRATE		9600	/* STD Baudrate */
+
+
+#define CONFIG_BOOTDELAY	5
+/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
+/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
+#define CONFIG_ZERO_BOOTDELAY_CHECK  	/* check console even if bootdelay = 0 */
+
+
+#define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
+#define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
+
+#define CONFIG_IPADDR		10.0.0.100
+#define CONFIG_SERVERIP		10.0.0.1
+#define CONFIG_PREBOOT
+/***************************************************************
+ * defines if the console is stored in the environment
+ ***************************************************************/
+#define CFG_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
+/***************************************************************
+ * defines if an overwrite_console function exists
+ *************************************************************/
+#define CFG_CONSOLE_OVERWRITE_ROUTINE
+#define CFG_CONSOLE_INFO_QUIET
+/***************************************************************
+ * defines if the overwrite_console should be stored in the
+ * environment
+ **************************************************************/
+#undef CFG_CONSOLE_ENV_OVERWRITE
+
+/**************************************************************
+ * loads config
+ *************************************************************/
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MISC_INIT_R
+/***********************************************************
+ * Miscellaneous configurable options
+ **********************************************************/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_BASE_BAUD       691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR		0x400000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
+#define CONFIG_PCI_PNP			/* pci plug-and-play		*/
+					/* resource configuration	*/
+#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFF80000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ */
+#define FLASH_MAX_SIZE		0x00800000		/* 8MByte max */
+#define FLASH_BASE_PRELIM	0xFF800000  /* open the flash CS */
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR	0xF4000000
+#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in On Chip SRAM)
+ */
+#define CFG_TEMP_STACK_OCM	1
+#define CFG_OCM_DATA_ADDR	0xF0000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR 	/* inside of On Chip SRAM    */
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
+#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+
+/***********************************************************************
+ * External peripheral base address
+ ***********************************************************************/
+#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
+
+/***********************************************************************
+ * Last Stage Init
+ ***********************************************************************/
+#define CONFIG_LAST_STAGE_INIT
+/************************************************************
+ * Ethernet Stuff
+ ***********************************************************/
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
+#define CONFIG_CS8952_PHY	1	/* its a CS8952 PHY		*/
+/************************************************************
+ * RTC
+ ***********************************************************/
+#define CONFIG_RTC_MC146818
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/************************************************************
+ * IDE/ATA stuff
+ ************************************************************/
+#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	CFG_ISA_IO_BASE_ADDRESS /* base address */
+#define CFG_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
+#define CFG_ATA_IDE1_OFFSET	0x0170	/* ide1 offset */
+#define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
+#define CFG_ATA_REG_OFFSET	0	/* reg offset */
+#define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET		/* reset for ide supported...	*/
+#define CONFIG_IDE_RESET_ROUTINE	/* with a special reset function */
+#define CONFIG_SUPPORT_VFAT
+
+/************************************************************
+ * ATAPI support (experimental)
+ ************************************************************/
+#define CONFIG_ATAPI			/* enable ATAPI Support */
+
+/************************************************************
+ * SCSI support (experimental) only SYM53C8xx supported
+ ************************************************************/
+#define CONFIG_SCSI_SYM53C8XX
+#define CFG_SCSI_MAX_LUN	8	/* number of supported LUNs */
+#define CFG_SCSI_MAX_SCSI_ID	7	/* maximum SCSI ID (0..6) */
+#define CFG_SCSI_MAX_DEVICE	CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
+#define CFG_SCSI_SPIN_UP_TIME	2
+
+/************************************************************
+ * Disk-On-Chip configuration
+ ************************************************************/
+#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+#define CFG_DOC_SHORT_TIMEOUT
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+
+/************************************************************
+ * DISK Partition support
+ ************************************************************/
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION /* Experimental */
+
+/************************************************************
+ * Keyboard support
+ ************************************************************/
+#define CONFIG_ISA_KEYBOARD
+
+/************************************************************
+ * Video support
+ ************************************************************/
+#define CONFIG_VIDEO			/*To enable video controller support */
+#define CONFIG_VIDEO_CT69000
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VIDEO_ONBOARD		/* Video controller is on-board */
+
+/************************************************************
+ * USB support
+ ************************************************************/
+#define CONFIG_USB_UHCI
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_USB_STORAGE
+
+/* Enable needed helper functions */
+#define CFG_DEVICE_DEREGISTER		/* needs device_deregister */
+
+/************************************************************
+ * Debug support
+ ************************************************************/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/************************************************************
+ * support BZIP2 compression
+ ************************************************************/
+#define CONFIG_BZIP2		1
+
+/************************************************************
+ * Ident
+ ************************************************************/
+#define VERSION_TAG "released"
+#define CONFIG_ISO_STRING "MEV-10066-001"
+#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h
new file mode 100755
index 0000000..91e9518
--- /dev/null
+++ b/include/configs/PK1C20.h
@@ -0,0 +1,229 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU
+ *----------------------------------------------------------------------*/
+#define CONFIG_PK1C20		1		/* PK1C20 board		*/
+#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
+
+#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CFG_NIOS_SYSID_BASE	0x00920828	/* System id address	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
+
+/*------------------------------------------------------------------------
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ *----------------------------------------------------------------------*/
+#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+
+/*------------------------------------------------------------------------
+ * MEMORY BASE ADDRESSES
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CFG_SRAM_BASE		0x00800000	/* SRAM base addr	*/
+#define CFG_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION
+ *	-Monitor at top.
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128k		*/
+#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
+ * CFG_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
+#define CFG_ENV_ADDR	(CFG_RESET_ADDR + CFG_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CONSOLE_JTAG)
+#define CFG_NIOS_CONSOLE	0x00920820	/* JTAG UART base addr	*/
+#else
+#define CFG_NIOS_CONSOLE	0x009208a0	/* UART base addr	*/
+#endif
+
+#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
+#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+
+/*------------------------------------------------------------------------
+ * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
+ * epcs device access is enabled. The base address is the epcs
+ * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
+ * The register base is currently at offset 0x400 from the memory base.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_EPCSBASE	0x00900400	/* EPCS register base	*/
+
+/*------------------------------------------------------------------------
+ * DEBUG
+ *----------------------------------------------------------------------*/
+#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
+
+/*------------------------------------------------------------------------
+ * TIMEBASE --
+ *
+ * The high res timer defaults to 1 msec. Since it includes the period
+ * registers, we can slow it down to 10 msec using TMRCNT. If the default
+ * period is acceptable, TMRCNT can be left undefined.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_TMRBASE	0x00920860	/* Tick timer base addr */
+#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+
+/*------------------------------------------------------------------------
+ * STATUS LED -- Provides a simple blinking led. For Nios2 each board
+ * must implement its own led routines -- leds are, after all,
+ * board-specific, no?
+ *----------------------------------------------------------------------*/
+#define CFG_LEDPIO_ADDR		0x00920840	/* LED PIO base addr	*/
+#define CONFIG_STATUS_LED			/* Enable status driver */
+
+#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
+#define STATUS_LED_STATE	1		/* Blinking		*/
+#define STATUS_LED_PERIOD	(500/CFG_NIOS_TMRMS) /* Every 500 msec	*/
+
+/*------------------------------------------------------------------------
+ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
+ * and really doesn't need any additional clutter. So I choose the lazy
+ * way out to avoid changes there -- define the base address to ensure
+ * cache bypass so there's no need to monkey with inx/outx macros.
+ *----------------------------------------------------------------------*/
+#define CONFIG_SMC91111_BASE	0x80910300	/* Base addr (bypass)	*/
+#define CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
+#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.2.21
+#define CONFIG_SERVERIP		192.168.2.16
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS		(CFG_CMD_BDI	| \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_ECHO	| \
+				 CFG_CMD_ENV	| \
+				 CFG_CMD_FLASH	| \
+				 CFG_CMD_IMI	| \
+				 CFG_CMD_IRQ	| \
+				 CFG_CMD_LOADS	| \
+				 CFG_CMD_LOADB	| \
+				 CFG_CMD_MEMORY | \
+				 CFG_CMD_MISC	| \
+				 CFG_CMD_NET	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_RUN	| \
+				 CFG_CMD_SAVES	)
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * COMPACT FLASH
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define CONFIG_IDE_PREINIT			/* Implement id_preinit	*/
+#define CFG_IDE_MAXBUS		1		/* 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1		/* 1 drive per IDE bus	*/
+
+#define CFG_ATA_BASE_ADDR	0x00900800	/* ATA base addr	*/
+#define CFG_ATA_IDE0_OFFSET	0x0000		/* IDE0 offset		*/
+#define CFG_ATA_DATA_OFFSET	0x0040		/* Data IO offset	*/
+#define CFG_ATA_REG_OFFSET	0x0040		/* Register offset	*/
+#define CFG_ATA_ALT_OFFSET	0x0100		/* Alternate reg offset	*/
+#define CFG_ATA_STRIDE          4		/* Width betwix addrs	*/
+#define CONFIG_DOS_PARTITION
+
+/* Board-specific cf regs */
+#define CFG_CF_PRESENT		0x00900880	/* CF Present PIO base	*/
+#define CFG_CF_POWER		0x00900890	/* CF Power FET PIO base*/
+#define CFG_CF_ATASEL		0x009008a0	/* CF ATASEL PIO base	*/
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */
+
+/*------------------------------------------------------------------------
+ * JFFS2
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#define CFG_JFFS_CUSTOM_PART			/* board defined part	*/
+#endif
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP				/* Provide extended help*/
+#define CFG_PROMPT		"==> "		/* Command prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O buf size */
+#define CFG_MAXARGS		16		/* Max command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
+#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address */
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
+#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
new file mode 100755
index 0000000..54ecfa4
--- /dev/null
+++ b/include/configs/PLU405.h
@@ -0,0 +1,455 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_PLU405		1	/* ...on a PLU405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
+
+#define CONFIG_BAUDRATE		9600
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#if 0 /* test-only */
+#define CONFIG_NET_MULTI	1
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY1_ADDR	1	/* PHY address			*/
+#else
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#endif
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_EEPROM	)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
+#define CONFIG_AUTO_UPDATE_SHOW 1       /* use board show routine       */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+/* Only interrupt boot if space is pressed */
+/* If a long serial cable is connected but */
+/* other end is dead, garbage will be read */
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
+
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xf8000001      /* 128MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CFG_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CFG_RAMBOOT		1
+#else
+# undef CFG_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
+#if 1 /* test-only */
+/* CAT24WC08/16... */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#else
+/* CAT24WC32/64... */
+#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+					/* 32 byte page write mode using*/
+					/* last 5 bits of the address	*/
+#endif
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
+#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
+#define VGA_BA		0xF1000000	    /* Epson VGA Base Address		*/
+#define CFG_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address		*/
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+
+#define CFG_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address	*/
+
+/* FPGA internal regs */
+#define CFG_FPGA_CTRL		0x000
+
+/* FPGA Control Reg */
+#define CFG_FPGA_CTRL_CF_RESET	0x0001
+#define CFG_FPGA_CTRL_WDI	0x0002
+#define CFG_FPGA_CTRL_PS2_RESET 0x0020
+
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+#define CFG_GPIO0_ISR1L		0x15555445
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FE0014
+
+#define CFG_DUART_RST		(0x80000000 >> 14)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
new file mode 100755
index 0000000..9f1dec8
--- /dev/null
+++ b/include/configs/PM520.h
@@ -0,0 +1,384 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_PM520		1	/* ... on PM520 board */
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
+
+#define CONFIG_MISC_INIT_R
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_MII		1
+#define CONFIG_EEPRO100		1
+#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#undef  CONFIG_NS8382X
+
+#define ADD_PCI_CMD 		CFG_CMD_PCI
+
+#else	/* MPC5100 */
+
+#define ADD_PCI_CMD		0  /* no CFG_CMD_PCI */
+
+#endif
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 1
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD             0
+#endif
+
+#if defined(CONFIG_BOOT_ROM)
+#define ADD_DOC_CMD             0
+#else
+#define ADD_DOC_CMD             CFG_CMD_DOC
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				ADD_DOC_CMD	| \
+				ADD_PCI_CMD	| \
+				ADD_USB_CMD	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=pm520\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk30/ppc_82xx\0"					\
+	"bootfile=/tftpboot/PM520/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#endif
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x58
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR		0x51
+
+/*
+ * Disk-On-Chip configuration
+ */
+
+#define CFG_DOC_SHORT_TIMEOUT
+#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
+
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+#define CFG_DOC_BASE		0xE0000000
+#define CFG_DOC_SIZE		0x00100000
+
+#if defined(CONFIG_BOOT_ROM)
+/*
+ * Flash configuration (8,16 or 32 MB)
+ * TEXT base always at 0xFFF00000
+ * ENV_ADDR always at  0xFFF40000
+ * FLASH_BASE at 0xFC000000 for 32 MB
+ *               0xFD000000 for 16 MB
+ *               0xFD800000 for  8 MB
+ */
+#define CFG_FLASH_BASE		0xfc000000
+#define CFG_FLASH_SIZE		0x02000000
+#define CFG_BOOTROM_BASE	0xFFF00000
+#define CFG_BOOTROM_SIZE	0x00080000
+#define CFG_ENV_ADDR		(0xFDF00000 + 0x40000)
+#else
+/*
+ * Flash configuration (8,16 or 32 MB)
+ * TEXT base always at 0xFFF00000
+ * ENV_ADDR always at  0xFFF40000
+ * FLASH_BASE at 0xFE000000 for 32 MB
+ *               0xFF000000 for 16 MB
+ *               0xFF800000 for  8 MB
+ */
+#define CFG_FLASH_BASE		0xfe000000
+#define CFG_FLASH_SIZE		0x02000000
+#define CFG_ENV_ADDR		(0xFFF00000 + 0x40000)
+#endif
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+
+#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
+
+#undef CONFIG_FLASH_16BIT	/* Flash is 32-bit */
+
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x10000
+#define CFG_ENV_SECT_SIZE	0x40000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xf0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG	0x10000004
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#if defined(CONFIG_BOOT_ROM)
+#define CFG_BOOTCS_START	CFG_BOOTROM_BASE
+#define CFG_BOOTCS_SIZE		CFG_BOOTROM_SIZE
+#define CFG_BOOTCS_CFG		0x00047800
+#define CFG_CS0_START		CFG_BOOTROM_BASE
+#define CFG_CS0_SIZE		CFG_BOOTROM_SIZE
+#define CFG_CS1_START		CFG_FLASH_BASE
+#define CFG_CS1_SIZE		CFG_FLASH_SIZE
+#define CFG_CS1_CFG		0x0004fb00
+#else
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x0004fb00
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+#define CFG_CS1_START		CFG_DOC_BASE
+#define CFG_CS1_SIZE		CFG_DOC_SIZE
+#define CFG_CS1_CFG		0x00047800
+#endif
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00005000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#undef	CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	2	/* max. 2 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers                                                */
+#define CFG_ATA_STRIDE          4
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
new file mode 100755
index 0000000..6e5e3bb
--- /dev/null
+++ b/include/configs/PM826.h
@@ -0,0 +1,576 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef CFG_RAMBOOT
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU	*/
+#define CONFIG_PM826		1	/* ...on a PM8260 module	*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#undef CONFIG_DB_CR826_J30x_ON		/* J30x jumpers on D.B. carrier	*/
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+# define CFG_I2C_SPEED		50000
+# define CFG_I2C_SLAVE		0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR	0x51
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else*/
+#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if CONFIG_ETHER_ON_SCC is selected, then
+ *   - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
+ *   - CONFIG_NET_MULTI must not be defined
+ *
+ * if CONFIG_ETHER_ON_FCC is selected, then
+ *   - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
+ *   - CONFIG_NET_MULTI must be defined
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#define	CONFIG_NET_MULTI
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_INDEX    1		/* which SCC channel for ethernet */
+
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+/*
+ * - Rx-CLK is CLK11
+ * - Tx-CLK is CLK10
+ */
+#define	CONFIG_ETHER_ON_FCC1
+# define CFG_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+#ifndef CONFIG_DB_CR826_J30x_ON
+# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
+#else
+# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
+#endif
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK14
+ */
+#define	CONFIG_ETHER_ON_FCC2
+# define CFG_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+/*
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	64000000	/* in Hz */
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#ifdef CONFIG_PCI
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DOC	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_SNTP	)
+#else	/* ! PCI */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DOC	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+#endif	/* CONFIG_PCI */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Disk-On-Chip configuration
+ */
+
+#define CFG_DOC_SHORT_TIMEOUT
+#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
+
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Flash and Boot ROM mapping
+ */
+#ifdef CONFIG_FLASH_32MB
+#define	CFG_FLASH0_BASE		0x40000000
+#define	CFG_FLASH0_SIZE		0x02000000
+#else
+#define	CFG_FLASH0_BASE		0xFF000000
+#define	CFG_FLASH0_SIZE		0x00800000
+#endif
+#define	CFG_BOOTROM_BASE	0xFF800000
+#define	CFG_BOOTROM_SIZE	0x00080000
+#define CFG_DOC_BASE		0xFF800000
+#define CFG_DOC_SIZE		0x00100000
+
+/* Flash bank size (for preliminary settings)
+ */
+#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#ifdef CONFIG_FLASH_32MB
+#define CFG_MAX_FLASH_SECT	135	/* max num of sects on one chip */
+#else
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#endif
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#if 0
+/* Start port with environment in flash; switch to EEPROM later */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
+#define CFG_ENV_SIZE		0x40000
+#define CFG_ENV_SECT_SIZE	0x40000
+#else
+/* Final version: environment in EEPROM */
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_I2C_EEPROM_ADDR	0x58
+#define CFG_I2C_EEPROM_ADDR_LEN	1
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CFG_ENV_OFFSET		512
+#define CFG_ENV_SIZE		(2048 - 512)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#if defined(CONFIG_BOOT_ROM)
+#define CFG_HRCW_MASTER		(HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
+#else
+#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
+#endif
+
+/* no slaves so just fill with zeros */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
+ * is mapped at SDRAM_BASE2_PRELIM.
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		CFG_FLASH0_BASE
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT
+#endif
+
+#ifdef	CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL  (HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CFG_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR         RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+
+#define BCR_APD01       0x10000000
+#define CFG_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#if 0
+#define CFG_SIUMCR	(SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
+#else
+#define CFG_SIUMCR	(SIUMCR_DPPC10|SIUMCR_APPC10)
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SCCR        (SCCR_DFBRG00)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    64 bit  FLASH
+ *  1   60x     SDRAM   64 bit  SDRAM
+ *
+ */
+
+	/* Initialize SDRAM on local bus
+	 */
+#define CFG_INIT_LOCAL_SDRAM
+
+
+/* Minimum mask to separate preliminary
+ * address ranges for CS[0:2]
+ */
+#define CFG_MIN_AM_MASK	0xC0000000
+
+/*
+ * we use the same values for 32 MB and 128 MB SDRAM
+ * refresh rate = 7.73 uS (64 MHz Bus Clock)
+ */
+#define CFG_MPTPR       0x2000
+#define CFG_PSRT        0x0E
+
+#define CFG_MRS_OFFS	0x00000000
+
+
+#if defined(CONFIG_BOOT_ROM)
+/*
+ * Bank 0 - Boot ROM (8 bit wide)
+ */
+#define CFG_BR0_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_3_CLK			|\
+			 ORxG_EHTR			|\
+			 ORxG_TRLX)
+
+/*
+ * Bank 1 - Flash (64 bit wide)
+ */
+#define CFG_BR1_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_64			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_3_CLK			|\
+			 ORxG_EHTR			|\
+			 ORxG_TRLX)
+
+#else	/* ! CONFIG_BOOT_ROM */
+
+/*
+ * Bank 0 - Flash (64 bit wide)
+ */
+#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxG_EHTR                      |\
+			 ORxG_TRLX)
+
+/*
+ * Bank 1 - Disk-On-Chip
+ */
+#define CFG_BR1_PRELIM	((CFG_DOC_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_DOC_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_3_CLK			|\
+			 ORxG_EHTR			|\
+			 ORxG_TRLX)
+
+#endif /* CONFIG_BOOT_ROM */
+
+/* Bank 2 - SDRAM
+ */
+
+#ifndef CFG_RAMBOOT
+#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CFG_OR2_8COL    (CFG_MIN_AM_MASK	        |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A9             |\
+			 ORxS_NUMR_12)
+
+#define CFG_PSDMR_8COL  (PSDMR_SDAM_A13_IS_A5           |\
+			 PSDMR_BSMA_A14_A16             |\
+			 PSDMR_SDA10_PBI0_A10           |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_1W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_1C                   |\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CFG_OR2_9COL    (CFG_MIN_AM_MASK                |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A7             |\
+			 ORxS_NUMR_13)
+
+#define CFG_PSDMR_9COL  (PSDMR_SDAM_A14_IS_A5           |\
+			 PSDMR_BSMA_A13_A15             |\
+			 PSDMR_SDA10_PBI0_A9            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_1W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_1C                   |\
+			 PSDMR_CL_2)
+
+#define CFG_OR2_PRELIM   CFG_OR2_9COL
+#define CFG_PSDMR        CFG_PSDMR_9COL
+
+#endif /* CFG_RAMBOOT */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PM828.h b/include/configs/PM828.h
new file mode 100755
index 0000000..982a1f8
--- /dev/null
+++ b/include/configs/PM828.h
@@ -0,0 +1,570 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef CFG_RAMBOOT
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU	*/
+#define CONFIG_PM828		1	/* ...on a PM828 module */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#undef CONFIG_DB_CR826_J30x_ON		/* J30x jumpers on D.B. carrier */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp;"								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm"
+
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+# define CFG_I2C_SPEED		50000
+# define CFG_I2C_SLAVE		0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else	iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else	iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR	0x51
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else*/
+#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if CONFIG_ETHER_ON_SCC is selected, then
+ *   - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
+ *   - CONFIG_NET_MULTI must not be defined
+ *
+ * if CONFIG_ETHER_ON_FCC is selected, then
+ *   - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
+ *   - CONFIG_NET_MULTI must be defined
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#define CONFIG_NET_MULTI
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
+#define CONFIG_ETHER_INDEX    1		/* which SCC channel for ethernet */
+
+#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
+/*
+ * - Rx-CLK is CLK11
+ * - Tx-CLK is CLK10
+ */
+#define CONFIG_ETHER_ON_FCC1
+# define CFG_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+#ifndef CONFIG_DB_CR826_J30x_ON
+# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
+#else
+# define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
+#endif
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK14
+ */
+#define CONFIG_ETHER_ON_FCC2
+# define CFG_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+/*
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	100000000	/* in Hz */
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#ifdef CONFIG_PCI
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DOC	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_SNTP	)
+#else	/* ! PCI */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DOC	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+#endif	/* CONFIG_PCI */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Disk-On-Chip configuration
+ */
+
+#define CFG_DOC_SHORT_TIMEOUT
+#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
+
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END 0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	     (8 << 20)	     /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Flash and Boot ROM mapping
+ */
+
+#define CFG_BOOTROM_BASE	0xFF800000
+#define CFG_BOOTROM_SIZE	0x00080000
+#define CFG_FLASH0_BASE		0x40000000
+#define CFG_FLASH0_SIZE		0x02000000
+#define CFG_DOC_BASE		0xFF800000
+#define CFG_DOC_SIZE		0x00100000
+
+
+/* Flash bank size (for preliminary settings)
+ */
+#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CFG_MAX_FLASH_SECT	135	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+#if 0
+/* Start port with environment in flash; switch to EEPROM later */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
+#define CFG_ENV_SIZE		0x40000
+#define CFG_ENV_SECT_SIZE	0x40000
+#else
+/* Final version: environment in EEPROM */
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_I2C_EEPROM_ADDR	0x58
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CFG_ENV_OFFSET		512
+#define CFG_ENV_SIZE		(2048 - 512)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#if defined(CONFIG_BOOT_ROM)
+#define CFG_HRCW_MASTER		(HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
+#else
+#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
+#endif
+
+/* no slaves so just fill with zeros */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
+ * is mapped at SDRAM_BASE2_PRELIM.
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		CFG_FLASH0_BASE
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT
+#endif
+
+#ifdef	CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot		   */
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CFG_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register					 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR		RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+
+#define BCR_APD01	0x10000000
+#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+#if 0
+#define CFG_SIUMCR	(SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
+#else
+#define CFG_SIUMCR	(SIUMCR_DPPC10|SIUMCR_APPC10)
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				 4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SCCR	(SCCR_DFBRG00)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR	0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus	Machine PortSz	Device
+ * ---- ---	------- ------	------
+ *  0	60x	GPCM	64 bit	FLASH
+ *  1	60x	SDRAM	64 bit	SDRAM
+ *
+ */
+
+	/* Initialize SDRAM on local bus
+	 */
+#define CFG_INIT_LOCAL_SDRAM
+
+
+/* Minimum mask to separate preliminary
+ * address ranges for CS[0:2]
+ */
+#define CFG_MIN_AM_MASK 0xC0000000
+
+/*
+ * we use the same values for 32 MB and 128 MB SDRAM
+ * refresh rate = 7.68 uS (100 MHz Bus Clock)
+ */
+#define CFG_MPTPR	0x2000
+#define CFG_PSRT	0x16
+
+#define CFG_MRS_OFFS	0x00000000
+
+
+#if defined(CONFIG_BOOT_ROM)
+/*
+ * Bank 0 - Boot ROM (8 bit wide)
+ */
+#define CFG_BR0_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxG_EHTR			|\
+			 ORxG_TRLX)
+
+/*
+ * Bank 1 - Flash (64 bit wide)
+ */
+#define CFG_BR1_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_64			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxG_EHTR			|\
+			 ORxG_TRLX)
+
+#else	/* ! CONFIG_BOOT_ROM */
+
+/*
+ * Bank 0 - Flash (64 bit wide)
+ */
+#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_64			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxG_EHTR			|\
+			 ORxG_TRLX)
+
+/*
+ * Bank 1 - Disk-On-Chip
+ */
+#define CFG_BR1_PRELIM	((CFG_DOC_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_DOC_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxG_EHTR			|\
+			 ORxG_TRLX)
+
+#endif /* CONFIG_BOOT_ROM */
+
+/* Bank 2 - SDRAM
+ */
+
+#ifndef CFG_RAMBOOT
+#define CFG_BR2_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A9		|\
+			 ORxS_NUMR_12)
+
+#define CFG_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
+			 PSDMR_BSMA_A14_A16		|\
+			 PSDMR_SDA10_PBI0_A10		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A7		|\
+			 ORxS_NUMR_13)
+
+#define CFG_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
+			 PSDMR_BSMA_A13_A15		|\
+			 PSDMR_SDA10_PBI0_A9		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+#define CFG_OR2_PRELIM	 CFG_OR2_9COL
+#define CFG_PSDMR	 CFG_PSDMR_9COL
+
+#endif /* CFG_RAMBOOT */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PM854.h b/include/configs/PM854.h
new file mode 100755
index 0000000..da01186
--- /dev/null
+++ b/include/configs/PM854.h
@@ -0,0 +1,440 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * pm854 board configuration file
+ *
+ * Please refer to doc/README.mpc85xx for more info.
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
+#define CONFIG_MPC8540		1	/* MPC8540 specific */
+#define CONFIG_PM854		1	/* PM854 board specific */
+
+#define CONFIG_PCI
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#undef	CONFIG_SPD_EEPROM		/* do not use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_MEM_INIT_VALUE		0xDEADBEEF
+
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ *    33000000
+ *    66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz.  In any event, this value
+ * must match the settings of some switches.  Details can be found
+ * in the README.mpc85xxads.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	66000000
+#endif
+
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00200000	/* memtest region */
+#define CFG_MEMTEST_END		0x00400000
+
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#if defined(CONFIG_SPD_EEPROM)
+    /*
+     * Determine DDR configuration from I2C interface.
+     */
+    #define SPD_EEPROM_ADDRESS	0x58		/* DDR DIMM */
+
+#else
+    /*
+     * Manually set up DDR parameters
+     */
+    #define CFG_SDRAM_SIZE	256		/* DDR is 256 MB */
+    #define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-256MB */
+    #define CFG_DDR_CS0_CONFIG	0x80000102
+    #define CFG_DDR_TIMING_1	0x47444321
+    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+    #define CFG_DDR_CONTROL	0xc2008000	/* unbuffered,no DYN_PWR */
+    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
+    #define CFG_DDR_INTERVAL	0x045b0100	/* autocharge,no open page */
+#endif
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	0		/* LBC SDRAM is 0 MB */
+
+#define CFG_FLASH_BASE		0xfe000000	/* start of 32 MB FLASH */
+#define CFG_BR0_PRELIM		0xfe001801	/* port size 32bit */
+
+#define CFG_OR0_PRELIM		0xfe006f67	/* 32 MB Flash */
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef	CFG_RAMBOOT
+#endif
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
+#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
+
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x58
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR		0x51
+
+/* RapidIO MMU */
+#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
+#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0xe2000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_EEPRO100
+#define	CONFIG_E1000
+#undef	CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR	0xe0000000
+    #define PCI_ENET0_MEMADDR	0xe0000000
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+#define CONFIG_MPC85XX_FEC	1
+#define CONFIG_MPC85XX_FEC_NAME		"FEC"
+#define FEC_PHY_ADDR		3
+#define FEC_PHYIDX		0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#define	CONFIG_HAS_ETH1		1
+#define	CONFIG_HAS_ETH2		1
+
+#endif	/* CONFIG_TSEC_ENET */
+
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+  #define CFG_ENV_IS_IN_FLASH	1
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x80000)
+  #define CFG_ENV_SECT_SIZE	0x40000 /* 256K(one sector) for env */
+  #define CFG_ENV_SIZE		0x2000
+#else
+  #define CFG_NO_FLASH		1	/* Flash is not usable now */
+  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_PCI		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+  #else
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+  #endif
+#else
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_EEPROM	\
+				| CFG_CMD_DATE		\
+				| CFG_CMD_MII		\
+				| CFG_CMD_PCI		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+  #else
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_EEPROM	\
+				| CFG_CMD_DATE		\
+				| CFG_CMD_MII		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+  #endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory */
+#define CFG_LOAD_ADDR	0x2000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_LOOPW
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR	 00:40:42:01:00:00
+#define CONFIG_ETH1ADDR	 00:40:42:01:00:01
+#define CONFIG_ETH2ADDR	 00:40:42:01:00:02
+#endif
+
+
+#define CONFIG_ROOTPATH		/opt/eldk/ppc_85xx
+#define CONFIG_BOOTFILE		pm854/uImage
+
+#define CONFIG_HOSTNAME		pm854
+#define CONFIG_IPADDR	 192.168.0.103
+#define CONFIG_SERVERIP	 192.168.0.64
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_NETMASK	 255.255.255.0
+
+#define CONFIG_LOADADDR	 200000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 5	/* -1 disables auto-boot */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 9600
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+   "netdev=eth0\0"							\
+   "consoledev=ttyS0\0"							\
+   "ramdiskaddr=400000\0"						\
+   "ramdiskfile=pm854/uRamdisk\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+   "setenv bootargs root=/dev/nfs rw "					\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $loadaddr $bootfile;"						\
+   "bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "					\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $ramdiskaddr $ramdiskfile;"					\
+   "tftp $loadaddr $bootfile;"						\
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PM856.h b/include/configs/PM856.h
new file mode 100755
index 0000000..4d83487
--- /dev/null
+++ b/include/configs/PM856.h
@@ -0,0 +1,443 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * MicroSys PM856 board configuration file
+ *
+ * Please refer to doc/README.mpc85xx for more info.
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
+#define CONFIG_MPC8560		1	/* MPC8560 specific */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+#define CONFIG_PM856		1	/* PM856 board specific */
+
+#define CONFIG_PCI
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#undef  CONFIG_SPD_EEPROM		/* do not use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_DDR_DLL			/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+#define CONFIG_MEM_INIT_VALUE		0xDEADBEEF
+
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ *    33000000
+ *    66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz.  In any event, this value
+ * must match the settings of some switches.  Details can be found
+ * in the README.mpc85xxads.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	66000000
+#endif
+
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#define CFG_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00200000	/* memtest region */
+#define CFG_MEMTEST_END		0x00400000
+
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
+#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#if defined(CONFIG_SPD_EEPROM)
+    /*
+     * Determine DDR configuration from I2C interface.
+     */
+    #define SPD_EEPROM_ADDRESS	0x58		/* DDR DIMM */
+
+#else
+    /*
+     * Manually set up DDR parameters
+     */
+    #define CFG_SDRAM_SIZE	256		/* DDR is 256 MB */
+    #define CFG_DDR_CS0_BNDS	0x0000000f	/* 0-256MB */
+    #define CFG_DDR_CS0_CONFIG	0x80000102
+    #define CFG_DDR_TIMING_1	0x47444321
+    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+    #define CFG_DDR_CONTROL	0xc2008000	/* unbuffered,no DYN_PWR */
+    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
+    #define CFG_DDR_INTERVAL	0x045b0100	/* autocharge,no open page */
+#endif
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	0		/* LBC SDRAM is 0 MB */
+
+#define CFG_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
+#define CFG_BR0_PRELIM		0xfe001801	/* port size 32bit */
+
+#define CFG_OR0_PRELIM		0xfe006f67	/* 32MB Flash */
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
+#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Local Bus Definitions
+ */
+
+#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
+#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
+
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(512 * 1024)    /* Reserve 512 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_ON_SCC	/* define if console on SCC */
+#undef  CONFIG_CONS_NONE	/* define if console on something else */
+#define CONFIG_CONS_INDEX       1  /* which serial channel for console */
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x58
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR		0x51
+
+/* RapidIO MMU */
+#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
+#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0xe2000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR	0xe0000000
+    #define PCI_ENET0_MEMADDR	0xe0000000
+    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#undef CONFIG_MPC85XX_FEC
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+#endif  /* CONFIG_TSEC_ENET */
+
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#define CONFIG_ETHER_ON_FCC	/* define if ether on FCC   */
+#undef  CONFIG_ETHER_NONE	/* define if ether on something else */
+
+
+/*
+   * - Rx-CLK is CLK15
+   * - Tx-CLK is CLK14
+   * - Select bus for bd/buffers
+   * - Full duplex
+ */
+#define CONFIG_ETHER_ON_FCC3
+#define CFG_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE)
+
+/*
+ * Environment
+ */
+#ifndef CFG_RAMBOOT
+  #define CFG_ENV_IS_IN_FLASH	1
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x80000)
+  #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+  #define CFG_ENV_SIZE		0x2000
+#else
+  #define CFG_NO_FLASH		1	/* Flash is not usable now */
+  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#if defined(CFG_RAMBOOT)
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_PCI		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+  #else
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
+				 | CFG_CMD_PING		\
+				 | CFG_CMD_I2C)		\
+				&			\
+				 ~(CFG_CMD_ENV		\
+				  | CFG_CMD_LOADS))
+  #endif
+#else
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_EEPROM	\
+				| CFG_CMD_DATE		\
+				| CFG_CMD_PCI		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+  #else
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
+				| CFG_CMD_EEPROM	\
+				| CFG_CMD_DATE		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_I2C)
+  #endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_LOAD_ADDR	0x1000000	/* default load address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */
+#define CONFIG_LOOPW
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_ETHADDR   00:40:42:01:00:00
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:40:42:01:00:01
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:40:42:01:00:02
+#endif
+
+
+#define CONFIG_ROOTPATH		/opt/eldk/ppc_85xx
+#define CONFIG_BOOTFILE		pm856/uImage
+
+#define CONFIG_HOSTNAME		pm856
+#define CONFIG_IPADDR    192.168.0.103
+#define CONFIG_SERVERIP  192.168.0.64
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 5	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	9600
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS0\0"                                                 \
+   "ramdiskaddr=400000\0"						\
+   "ramdiskfile=pm856/uRamdisk\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
new file mode 100755
index 0000000..8bcab0b
--- /dev/null
+++ b/include/configs/PMC405.h
@@ -0,0 +1,320 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_PMC405		1	/* ...on a PMC405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_UNIVERSE | \
+				CFG_CMD_EEPROM  )
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address         */
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0408  /* PCI Device ID: PMC-405       */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MONITOR_BASE	0xFFFC0000
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_FLASH_INCREMENT	0x01000000
+
+#define CFG_FLASH_CFI         1       /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER  1       /* Use the common driver */
+#define CFG_FLASH_PROTECTION  1       /* don't use hardware protection        */
+#define CFG_FLASH_USE_BUFFER_WRITE 1  /* use buffered writes (20x faster)     */
+#define CFG_MAX_FLASH_BANKS   2       /* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + CFG_FLASH_INCREMENT }
+#define CFG_MAX_FLASH_SECT    128     /* max num of sects on one chip */
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*
+ * JFFS2 partitions - second bank contains u-boot
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0x01b00000
+#define CONFIG_JFFS2_PART_OFFSET	0x00400000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=pmc405-0"
+#define MTDPARTS_DEFAULT	"mtdparts=pmc405-0:-(jffs2)"
+*/
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+#define FLASH0_BA	0xFF000000	    /* FLASH 0 Base Address		*/
+#define FLASH1_BA	0xFE000000	    /* FLASH 1 Base Address		*/
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
+#define CF_BA		0xF0100000	    /* CompactFlash Base Address	*/
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP	0x92015480
+#define CFG_EBC_PB0CR	FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CFG_EBC_PB1AP	0x92015480
+#define CFG_EBC_PB1CR	FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 2 (CAN0, 1, RTC) initialization					*/
+#define CFG_EBC_PB2AP	0x03000440   /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
+#define CFG_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization		*/
+#define CFG_EBC_PB3AP	0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR	CF_BA | 0x1A000	    /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
+#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
+#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+
+#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PN62.h b/include/configs/PN62.h
new file mode 100755
index 0000000..a717659
--- /dev/null
+++ b/include/configs/PN62.h
@@ -0,0 +1,304 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8240		1
+#define CONFIG_PN62		1
+
+#define CONFIG_CONS_INDEX	1
+
+
+#define REMOVE_COMMANDS         ( CFG_CMD_AUTOSCRIPT	| \
+ 				  CFG_CMD_LOADS		| \
+ 				  CFG_CMD_ENV		| \
+ 				  CFG_CMD_FLASH		| \
+				  CFG_CMD_IMLS		)
+
+#define CONFIG_COMMANDS		( (CONFIG_CMD_DFL & ~REMOVE_COMMANDS) |\
+				  CFG_CMD_PCI |\
+				  CFG_CMD_BSP)
+
+#define CONFIG_BAUDRATE		19200	/* console baudrate		*/
+
+#define CONFIG_BOOTDELAY	1	/* autoboot after n seconds	*/
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_SERVERIP		10.0.0.201
+#define CONFIG_IPADDR 		10.0.0.200
+#define CONFIG_ROOTPATH		/opt/eldk/ppc_82xx
+#define CONFIG_NETMASK		255.255.255.0
+#undef CONFIG_BOOTARGS
+#if 0
+/* Boot Linux with NFS root filesystem */
+#define CONFIG_BOOTCOMMAND \
+			"setenv verify y;" \
+       			"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
+			"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+			"ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
+			"loadp 100000; bootm"
+			/* "tftpboot 100000 uImage; bootm" */
+#else
+/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
+#define CONFIG_BOOTCOMMAND \
+			"setenv verify n;" \
+       			"setenv bootargs console=ttyS0,19200 mem=31M quiet " \
+			"root=/dev/ram rw " \
+			"ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
+			"loadp 200000; bootm"
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		1		/* undef to save memory		*/
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_PRAM		1024		/* reserve 1 MB protected RAM	*/
+
+#define CONFIG_MISC_INIT_R	1		/* call misc_init_r() on init	*/
+
+#define CONFIG_HAS_ETH1		1		/* add support for eth1addr	*/
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1		/* Show boot progress on LEDs   */
+
+/*
+ * PCI stuff
+ */
+#define CONFIG_PCI				/* include pci support		*/
+#define CONFIG_PCI_PNP				/* we need Plug 'n Play		*/
+#if 0
+#define CONFIG_PCI_SCAN_SHOW			/* show PCI auto-scan at boot	*/
+#endif
+
+/*
+ * Networking stuff
+ */
+#define CONFIG_NET_MULTI       			/* Multi ethernet cards support */
+
+#define CONFIG_PCNET				/* there are 2 AMD PCnet 79C973	*/
+#define CONFIG_PCNET_79C973
+
+#define _IO_BASE		0xfe000000	/* points to PCI I/O space	*/
+
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MAX_RAM_SIZE	0x10000000
+
+#define CFG_RESET_ADDRESS	0xfff00100
+
+#undef	CFG_RAMBOOT
+#define CFG_MONITOR_LEN		0x00030000
+#define CFG_MONITOR_BASE	TEXT_BASE
+
+/*#define CFG_GBL_DATA_SIZE    256*/
+#define CFG_GBL_DATA_SIZE	128
+
+#define CFG_INIT_RAM_ADDR   	0x40000000
+#define CFG_INIT_RAM_END    	0x1000
+#define CFG_GBL_DATA_OFFSET 	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+
+#define CFG_NO_FLASH		1		/* There is no FLASH memory	*/
+
+#define CFG_ENV_IS_NOWHERE	1		/* Store ENV in memory only	*/
+#define CFG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
+#define CFG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
+
+#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+
+#define CFG_MEMTEST_START	0x00004000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x01f00000	/* 0 ... 32 MB in DRAM		*/
+
+/*
+ * Serial port configuration
+ */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	1
+
+#define CFG_NS16550_CLK		1843200
+
+#define CFG_NS16550_COM1	0xff800008
+#define CFG_NS16550_COM2	0xff800000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
+#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  3
+
+#define CFG_EUMB_ADDR		0xFCE00000
+
+/* MCCR1 */
+#define CFG_ROMNAL		3	/* rom/flash next access time		*/
+#define CFG_ROMFAL		7	/* rom/flash access time		*/
+
+/* MCCR2 */
+#define CFG_ASRISE		6	/* ASRISE in clocks			*/
+#define CFG_ASFALL		12	/* ASFALL in clocks			*/
+#define CFG_REFINT		5600	/* REFINT in clocks			*/
+
+/* MCCR3 */
+#define CFG_BSTOPRE		0x3cf	/* Burst To Precharge			*/
+#define CFG_REFREC		2	/* Refresh to activate interval		*/
+#define CFG_RDLAT		3	/* data latency from read command	*/
+
+/* MCCR4 */
+#define CFG_PRETOACT		1	/* Precharge to activate interval	*/
+#define CFG_ACTTOPRE		3	/* Activate to Precharge interval	*/
+#define CFG_ACTORW		2	/* Activate to R/W			*/
+#define CFG_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
+#define CFG_SDMODE_WRAP		0	/* SDMODE Wrap type			*/
+#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
+#define CFG_REGISTERD_TYPE_BUFFER   1
+
+/* Memory bank settings:
+ *
+ * only bits 20-29 are actually used from these vales to set the
+ * start/qend address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CFG_BANK0_START		0x00000000
+#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE	1
+#define CFG_BANK1_START		0x00000000
+#define CFG_BANK1_END		0x00000000
+#define CFG_BANK1_ENABLE	0
+#define CFG_BANK2_START		0x00000000
+#define CFG_BANK2_END		0x00000000
+#define CFG_BANK2_ENABLE	0
+#define CFG_BANK3_START		0x00000000
+#define CFG_BANK3_END		0x00000000
+#define CFG_BANK3_ENABLE	0
+#define CFG_BANK4_START		0x00000000
+#define CFG_BANK4_END		0x00000000
+#define CFG_BANK4_ENABLE	0
+#define CFG_BANK5_START		0x00000000
+#define CFG_BANK5_END		0x00000000
+#define CFG_BANK5_ENABLE	0
+#define CFG_BANK6_START		0x00000000
+#define CFG_BANK6_END		0x00000000
+#define CFG_BANK6_ENABLE	0
+#define CFG_BANK7_START		0x00000000
+#define CFG_BANK7_END		0x00000000
+#define CFG_BANK7_ENABLE	0
+
+/*
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ * are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CFG_BANK_ENABLE		0x01
+
+#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+					/* see 8240 book for bit definitions	*/
+#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+/* SDRAM 0 - 256MB */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* PCI memory space */
+#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Config addrs, etc */
+#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
new file mode 100755
index 0000000..7ca827f
--- /dev/null
+++ b/include/configs/PPChameleonEVB.h
@@ -0,0 +1,810 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * (C) Copyright 2003
+ * DAVE Srl
+ *
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * Credits: Stefan Roese, Wolfgang Denk
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PPCHAMELEON_MODULE_BA	0	/* Basic    Model */
+#define CONFIG_PPCHAMELEON_MODULE_ME	1	/* Medium   Model */
+#define CONFIG_PPCHAMELEON_MODULE_HI	2	/* High-End Model */
+#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
+#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
+#endif
+
+
+/* Only one of the following two symbols must be defined (default is 25 MHz)
+ * CONFIG_PPCHAMELEON_CLK_25
+ * CONFIG_PPCHAMELEON_CLK_33
+ */
+#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
+#define CONFIG_PPCHAMELEON_CLK_25
+#endif
+
+#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
+#error "* Two external frequencies (SysClk) are defined! *"
+#endif
+
+#undef	CONFIG_PPCHAMELEON_SMI712
+
+/*
+ * Debug stuff
+ */
+#undef	__DEBUG_START_FROM_SRAM__
+#define __DISABLE_MACHINE_EXCEPTION__
+
+#ifdef __DEBUG_START_FROM_SRAM__
+#define CFG_DUMMY_FLASH_SIZE		1024*1024*4
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_PPCHAMELEONEVB	1	/* ...on a PPChameleonEVB board */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+
+#ifdef CONFIG_PPCHAMELEON_CLK_25
+# define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
+#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
+# define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
+#else
+# error "* External frequency (SysClk) not defined! *"
+#endif
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+
+/* Ethernet stuff */
+#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
+#define CONFIG_ETHADDR	00:50:c2:1e:af:fe
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#undef CONFIG_EXT_PHY
+#define CONFIG_NET_MULTI	1
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#ifndef	 CONFIG_EXT_PHY
+#define CONFIG_PHY_ADDR		1	/* EMAC0 PHY address		*/
+#define CONFIG_PHY1_ADDR	2	/* EMAC1 PHY address		*/
+#else
+#define CONFIG_PHY_ADDR		2	/* PHY address			*/
+#endif
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_SNTP	)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_M41T11	1	/* uses a M41T00 RTC		*/
+#define CFG_I2C_RTC_ADDR	0x68
+#define CFG_M41T11_BASE_YEAR	1900
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK		/* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD		691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_NAND0_BASE 0xFF400000
+#define CFG_NAND1_BASE 0xFF000000
+
+#define CFG_MAX_NAND_DEVICE	2	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+#define NAND_NO_RB
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
+#define CFG_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
+#define CFG_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
+#define CFG_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
+
+#define CFG_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
+#define CFG_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
+#define CFG_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
+#define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
+
+#define NAND_DISABLE_CE(nand) do \
+{ \
+	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
+		break; \
+	} \
+} while(0)
+
+#define NAND_ENABLE_CE(nand) do \
+{ \
+	switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
+		break; \
+	} \
+} while(0)
+
+#define NAND_CTL_CLRALE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
+		break; \
+	} \
+} while(0)
+
+#define NAND_CTL_SETALE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
+		break; \
+	} \
+} while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
+		break; \
+	    case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
+		break; \
+	} \
+} while(0)
+
+#define NAND_CTL_SETCLE(nandptr) do { \
+	switch((unsigned long)nandptr) { \
+	case CFG_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
+		break; \
+	case CFG_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
+		break; \
+	} \
+} while(0)
+
+#ifdef NAND_NO_RB
+/* constant delay (see also tR in the datasheet) */
+#define NAND_WAIT_READY(nand) do { \
+	udelay(12); \
+} while (0)
+#else
+/* use the R/B pin */
+/* TBD */
+#endif
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	 /* select pci host function	 */
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* PCI Vendor ID: IBM	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: ---	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+
+/* Reserve 256 kB for Monitor	*/
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)
+
+/* Reserve 320 kB for Monitor	*/
+/*
+#define CFG_FLASH_BASE		0xFFFB0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(320 * 1024)
+*/
+
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#ifdef ENVIRONMENT_IN_EEPROM
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
+
+#else	/* DEFAULT: environment in flash, using redundand flash sectors */
+
+#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define CFG_ENV_ADDR		0xFFFF8000	/* environment starts at the first small sector */
+#define CFG_ENV_SECT_SIZE	0x2000	/* 8196 bytes may be used for env vars*/
+#define CFG_ENV_ADDR_REDUND	0xFFFFA000
+#define CFG_ENV_SIZE_REDUND	0x2000
+
+#endif	/* ENVIRONMENT_IN_EEPROM */
+
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (External SRAM) initialization					*/
+/* Since this must replace NOR Flash, we use the same settings for CS0		*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB2AP		0x92015480
+#define CFG_EBC_PB2CR		0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB3AP		0x92015480
+#define CFG_EBC_PB3CR		0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit	*/
+
+#ifdef CONFIG_PPCHAMELEON_SMI712
+/*
+ * Video console (graphic: SMI LynxEM)
+ */
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_VIDEO_BMP_LOGO*/
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
+#define CFG_ISA_IO 0xE8000000
+/* see also drivers/videomodes.c */
+#define CFG_DEFAULT_VIDEO_MODE 0x303
+#endif
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CFG_FPGA_MODE		0x00
+#define CFG_FPGA_STATUS		0x02
+#define CFG_FPGA_TS		0x04
+#define CFG_FPGA_TS_LOW		0x06
+#define CFG_FPGA_TS_CAP0	0x10
+#define CFG_FPGA_TS_CAP0_LOW	0x12
+#define CFG_FPGA_TS_CAP1	0x14
+#define CFG_FPGA_TS_CAP1_LOW	0x16
+#define CFG_FPGA_TS_CAP2	0x18
+#define CFG_FPGA_TS_CAP2_LOW	0x1a
+#define CFG_FPGA_TS_CAP3	0x1c
+#define CFG_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CFG_FPGA_MODE_CF_RESET	0x0001
+#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CFG_FPGA_MODE_TS_CLEAR	0x2000
+
+/* FPGA Status Reg */
+#define CFG_FPGA_STATUS_DIP0	0x0001
+#define CFG_FPGA_STATUS_DIP1	0x0002
+#define CFG_FPGA_STATUS_DIP2	0x0004
+#define CFG_FPGA_STATUS_FLASH	0x0008
+#define CFG_FPGA_STATUS_TS_IRQ	0x1000
+
+#define CFG_FPGA_SPARTAN2	1		/* using Xilinx Spartan 2 now	 */
+#define CFG_FPGA_MAX_SIZE	128*1024	/* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000	/* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000	/* FPGA clk pin (ppc output)	 */
+#define CFG_FPGA_DATA		0x01000000	/* FPGA data pin (ppc output)	 */
+#define CFG_FPGA_INIT		0x00010000	/* FPGA init pin (ppc input)	 */
+#define CFG_FPGA_DONE		0x00008000	/* FPGA done pin (ppc input)	 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30]	- EMAC0 input
+ * GPIO0[31]	- EMAC1 reject packet as output
+ */
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+/*#define CFG_GPIO0_ISR1L	0x15555445*/
+#define CFG_GPIO0_ISR1L		0x15555444
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FF8014
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+
+#define CONFIG_NO_SERIAL_EEPROM
+
+/*--------------------------------------------------------------------*/
+
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*
+!-----------------------------------------------------------------------
+! Defines for entry options.
+! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
+!	are plugged in the board will be utilized as non-ECC DIMMs.
+!-----------------------------------------------------------------------
+*/
+#undef		AUTO_MEMORY_CONFIG
+#define		DIMM_READ_ADDR 0xAB
+#define		DIMM_WRITE_ADDR 0xAA
+
+#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register		*/
+#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register	*/
+#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register		*/
+#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register	*/
+#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register		*/
+#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register		*/
+#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register		*/
+#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register			*/
+#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR				*/
+#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register		*/
+
+/* Defines for CPC0_PLLMR1 Register fields */
+#define PLL_ACTIVE		0x80000000
+#define CPC0_PLLMR1_SSCS	0x80000000
+#define PLL_RESET		0x40000000
+#define CPC0_PLLMR1_PLLR	0x40000000
+    /* Feedback multiplier */
+#define PLL_FBKDIV		0x00F00000
+#define CPC0_PLLMR1_FBDV	0x00F00000
+#define PLL_FBKDIV_16		0x00000000
+#define PLL_FBKDIV_1		0x00100000
+#define PLL_FBKDIV_2		0x00200000
+#define PLL_FBKDIV_3		0x00300000
+#define PLL_FBKDIV_4		0x00400000
+#define PLL_FBKDIV_5		0x00500000
+#define PLL_FBKDIV_6		0x00600000
+#define PLL_FBKDIV_7		0x00700000
+#define PLL_FBKDIV_8		0x00800000
+#define PLL_FBKDIV_9		0x00900000
+#define PLL_FBKDIV_10		0x00A00000
+#define PLL_FBKDIV_11		0x00B00000
+#define PLL_FBKDIV_12		0x00C00000
+#define PLL_FBKDIV_13		0x00D00000
+#define PLL_FBKDIV_14		0x00E00000
+#define PLL_FBKDIV_15		0x00F00000
+    /* Forward A divisor */
+#define PLL_FWDDIVA		0x00070000
+#define CPC0_PLLMR1_FWDVA	0x00070000
+#define PLL_FWDDIVA_8		0x00000000
+#define PLL_FWDDIVA_7		0x00010000
+#define PLL_FWDDIVA_6		0x00020000
+#define PLL_FWDDIVA_5		0x00030000
+#define PLL_FWDDIVA_4		0x00040000
+#define PLL_FWDDIVA_3		0x00050000
+#define PLL_FWDDIVA_2		0x00060000
+#define PLL_FWDDIVA_1		0x00070000
+    /* Forward B divisor */
+#define PLL_FWDDIVB		0x00007000
+#define CPC0_PLLMR1_FWDVB	0x00007000
+#define PLL_FWDDIVB_8		0x00000000
+#define PLL_FWDDIVB_7		0x00001000
+#define PLL_FWDDIVB_6		0x00002000
+#define PLL_FWDDIVB_5		0x00003000
+#define PLL_FWDDIVB_4		0x00004000
+#define PLL_FWDDIVB_3		0x00005000
+#define PLL_FWDDIVB_2		0x00006000
+#define PLL_FWDDIVB_1		0x00007000
+    /* PLL tune bits */
+#define PLL_TUNE_MASK		0x000003FF
+#define PLL_TUNE_2_M_3		0x00000133	/*  2 <= M <= 3			*/
+#define PLL_TUNE_4_M_6		0x00000134	/*  3 <	 M <= 6			*/
+#define PLL_TUNE_7_M_10		0x00000138	/*  6 <	 M <= 10		*/
+#define PLL_TUNE_11_M_14	0x0000013C	/* 10 <	 M <= 14		*/
+#define PLL_TUNE_15_M_40	0x0000023E	/* 14 <	 M <= 40		*/
+#define PLL_TUNE_VCO_LOW	0x00000000	/* 500MHz <= VCO <=  800MHz	*/
+#define PLL_TUNE_VCO_HI		0x00000080	/* 800MHz <  VCO <= 1000MHz	*/
+
+/* Defines for CPC0_PLLMR0 Register fields */
+    /* CPU divisor */
+#define PLL_CPUDIV		0x00300000
+#define CPC0_PLLMR0_CCDV	0x00300000
+#define PLL_CPUDIV_1		0x00000000
+#define PLL_CPUDIV_2		0x00100000
+#define PLL_CPUDIV_3		0x00200000
+#define PLL_CPUDIV_4		0x00300000
+    /* PLB divisor */
+#define PLL_PLBDIV		0x00030000
+#define CPC0_PLLMR0_CBDV	0x00030000
+#define PLL_PLBDIV_1		0x00000000
+#define PLL_PLBDIV_2		0x00010000
+#define PLL_PLBDIV_3		0x00020000
+#define PLL_PLBDIV_4		0x00030000
+    /* OPB divisor */
+#define PLL_OPBDIV		0x00003000
+#define CPC0_PLLMR0_OPDV	0x00003000
+#define PLL_OPBDIV_1		0x00000000
+#define PLL_OPBDIV_2		0x00001000
+#define PLL_OPBDIV_3		0x00002000
+#define PLL_OPBDIV_4		0x00003000
+    /* EBC divisor */
+#define PLL_EXTBUSDIV		0x00000300
+#define CPC0_PLLMR0_EPDV	0x00000300
+#define PLL_EXTBUSDIV_2		0x00000000
+#define PLL_EXTBUSDIV_3		0x00000100
+#define PLL_EXTBUSDIV_4		0x00000200
+#define PLL_EXTBUSDIV_5		0x00000300
+    /* MAL divisor */
+#define PLL_MALDIV		0x00000030
+#define CPC0_PLLMR0_MPDV	0x00000030
+#define PLL_MALDIV_1		0x00000000
+#define PLL_MALDIV_2		0x00000010
+#define PLL_MALDIV_3		0x00000020
+#define PLL_MALDIV_4		0x00000030
+    /* PCI divisor */
+#define PLL_PCIDIV		0x00000003
+#define CPC0_PLLMR0_PPFD	0x00000003
+#define PLL_PCIDIV_1		0x00000000
+#define PLL_PCIDIV_2		0x00000001
+#define PLL_PCIDIV_3		0x00000002
+#define PLL_PCIDIV_4		0x00000003
+
+#ifdef CONFIG_PPCHAMELEON_CLK_25
+/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
+#define PPCHAMELEON_PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_8	|  \
+			      PLL_FWDDIVA_6 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8  |  \
+			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
+			      PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
+			      PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
+
+/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
+#define PPCHAMELEON_PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_4	|  \
+				  PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
+				  PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
+				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
+				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#else
+#error "* External frequency (SysClk) not defined! *"
+#endif
+
+#if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
+/* Model HI */
+#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_333_111_37_55_55
+#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_333_111_37_55_55
+#define CFG_OPB_FREQ	55555555
+/* Model ME */
+#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
+#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_266_133_33_66_33
+#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_266_133_33_66_33
+#define CFG_OPB_FREQ	66666666
+#else
+/* Model BA (default) */
+#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_133_133_33_66_33
+#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_133_133_33_66_33
+#define CFG_OPB_FREQ	66666666
+#endif
+
+#endif /* CONFIG_NO_SERIAL_EEPROM */
+
+#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
+#define NAND_CACHE_PAGES 16			/* size of nand cache in 512 bytes pages */
+
+/*
+ * JFFS2 partitions
+ */
+
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nand0"
+#define CONFIG_JFFS2_PART_SIZE		0x00400000
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
+*/
+
+/* 256 kB U-boot image */
+/*
+#define MTDPARTS_DEFAULT	"mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
+					"1792k(user),256k(u-boot);" \
+				"ppchameleonevb-nand:-(nand)"
+*/
+
+/* 320 kB U-boot image */
+/*
+#define MTDPARTS_DEFAULT	"mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
+					"1728k(user),320k(u-boot);" \
+				"ppchameleonevb-nand:-(nand)"
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/QS823.h b/include/configs/QS823.h
new file mode 100755
index 0000000..235bc48
--- /dev/null
+++ b/include/configs/QS823.h
@@ -0,0 +1,571 @@
+/*
+ * (C) Copyright 2003
+ * MuLogic B.V.
+ *
+ * (C) Copyright 2002
+ * Simple Network Magic Corporation
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* various debug settings */
+#undef CFG_DEVICE_NULLDEV		/* null device */
+#undef CONFIG_SILENT_CONSOLE		/* silent console */
+#undef CFG_CONSOLE_INFO_QUIET		/* silent console ? */
+#undef DEBUG				/* debug output code */
+#undef DEBUG_FLASH			/* debug flash code */
+#undef FLASH_DEBUG			/* debug fash code */
+#undef DEBUG_ENV			/* debug environment code */
+
+#define CFG_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
+#define CONFIG_ENV_OVERWRITE	1	/* allow overwrite MAC address */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU */
+#define CONFIG_QS823		1	/* ...on a QS823 module */
+#define CONFIG_SCC2_ENET	1	/* SCC2 10BaseT ethernet */
+
+/* Select the target clock speed */
+#undef CONFIG_CLOCK_16MHZ		/* cpu=16,777,216 Hz, mem=16Mhz */
+#undef CONFIG_CLOCK_33MHZ		/* cpu=33,554,432 Hz, mem=33Mhz */
+#undef CONFIG_CLOCK_50MHZ		/* cpu=49,971,200 Hz, mem=33Mhz */
+#define CONFIG_CLOCK_66MHZ	1	/* cpu=67,108,864 Hz, mem=66Mhz */
+#undef CONFIG_CLOCK_80MHZ		/* cpu=79,986,688 Hz, mem=33Mhz */
+
+#ifdef CONFIG_CLOCK_16MHZ
+#define CONFIG_CLOCK_MULT	512
+#endif
+
+#ifdef CONFIG_CLOCK_33MHZ
+#define CONFIG_CLOCK_MULT	1024
+#endif
+
+#ifdef CONFIG_CLOCK_50MHZ
+#define CONFIG_CLOCK_MULT	1525
+#endif
+
+#ifdef CONFIG_CLOCK_66MHZ
+#define CONFIG_CLOCK_MULT	2048
+#endif
+
+#ifdef CONFIG_CLOCK_80MHZ
+#define CONFIG_CLOCK_MULT	2441
+#endif
+
+/* choose flash size, 4Mb or 8Mb */
+#define CONFIG_FLASH_4MB	1	/* board has 4Mb flash */
+#undef CONFIG_FLASH_8MB			/* board has 8Mb flash */
+
+#define CONFIG_CLOCK_BASE	32768	/* Base clock input freq */
+
+#undef CONFIG_8xx_CONS_SMC1
+#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2 */
+#undef CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		38400	/* console baudrate = 38.4kbps */
+
+#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */
+
+/* Define default IP addresses */
+#define CONFIG_IPADDR		192.168.1.99	/* own ip address */
+#define CONFIG_SERVERIP		192.168.1.19	/* used for tftp (not nfs?) */
+
+/* message to say directly after booting */
+#define CONFIG_PREBOOT		"echo '';" \
+	"echo 'type:';" \
+	"echo 'run boot_nfs       to boot to NFS';" \
+	"echo 'run boot_flash     to boot to flash';" \
+	"echo '';" \
+	"echo 'run flash_rootfs   to install a new rootfs';" \
+	"echo 'run flash_env      to clear the env sector';" \
+	"echo 'run flash_rw       to clear the rw fs';" \
+	"echo 'run flash_uboot    to install a new u-boot';" \
+	"echo 'run flash_kernel   to install a new kernel';"
+
+/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOTCOMMAND	"run boot_nfs"
+
+#undef CONFIG_BOOTARGS		/* made by set_nfs of set_flash */
+
+/* Our flash filesystem looks like this
+ *
+ * 4Mb board:
+ * ffc0 0000 - ffeb ffff	root filesystem (jffs2) (~3Mb)
+ * ffec 0000 - ffed ffff	read-write filesystem (ext2)
+ * ffee 0000 - ffef ffff	environment
+ * fff0 0000 - fff1 ffff	u-boot
+ * fff2 0000 - ffff ffff	linux kernel
+ *
+ * 8Mb board:
+ * ff80 0000 - ffeb ffff	root filesystem (jffs2) (~7Mb)
+ * ffec 0000 - ffed ffff	read-write filesystem (ext2)
+ * ffee 0000 - ffef ffff	environment
+ * fff0 0000 - fff1 ffff	u-boot
+ * fff2 0000 - ffff ffff	linux kernel
+ *
+ */
+
+/* environment for 4Mb board */
+#ifdef CONFIG_FLASH_4MB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"serial#=QS823\0" \
+	"hostname=qs823\0" \
+	"netdev=eth0\0" \
+	"ethaddr=00:01:02:B4:36:56\0" \
+	"rootpath=/exports/rootfs\0" \
+	"mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
+	/* fill in variables */ \
+	"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
+	"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
+	"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
+	/* commands */ \
+	"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
+	"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
+	/* reinstall flash parts */ \
+	"flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
+	"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
+	"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
+	"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
+	"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
+#endif /* CONFIG_FLASH_4MB */
+
+/* environment for 8Mb board */
+#ifdef CONFIG_FLASH_8MB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"serial#=QS823\0" \
+	"hostname=qs823\0" \
+	"netdev=eth0\0" \
+	"ethaddr=00:01:02:B4:36:56\0" \
+	"rootpath=/exports/rootfs\0" \
+	"mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
+	/* fill in variables */ \
+	"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
+	"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
+	"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
+	/* commands */ \
+	"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
+	"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
+	/* reinstall flash parts */ \
+	"flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
+	"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
+	"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
+	"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
+	"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
+#endif /* CONFIG_FLASH_8MB */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change */
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+#undef CONFIG_STATUS_LED		/* Status LED disabled */
+#undef CONFIG_CAN_DRIVER		/* CAN Driver support disabled */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_MPC8xx	/* use internal RTC of MPC8xx */
+
+#define CONFIG_COMMANDS		(CFG_CMD_BDI	| \
+	CFG_CMD_BOOTD	| \
+	CFG_CMD_CONSOLE	| \
+	CFG_CMD_DATE	| \
+	CFG_CMD_ENV	| \
+	CFG_CMD_FLASH	| \
+	CFG_CMD_IMI	| \
+	CFG_CMD_IMMAP	| \
+	CFG_CMD_MEMORY	| \
+	CFG_CMD_NET	| \
+	CFG_CMD_RUN)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*-----------------------------------------------------------------------
+ * Environment variable storage is in FLASH, one sector before U-boot
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	0x20000		/* 128Kb, one whole sector */
+#define CFG_ENV_SIZE		0x2000		/* 8kb */
+#define CFG_ENV_ADDR		0xffee0000	/* address of env sector */
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory */
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+
+#define CFG_HUSH_PARSER		1		/* use "hush" command parser */
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works */
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR		0x400000	/* default load address */
+
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFF800000	/* Allow an 8Mbyte window */
+
+#define FLASH_BASE0_4M_PRELIM	0xFFC00000	/* Base for 4M Flash */
+#define FLASH_BASE0_8M_PRELIM	0xFF800000	/* Base for 8M Flash */
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CFG_MONITOR_BASE	0xFFF00000	/* U-boot location */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * TODO flash parameters
+ * FLASH organization for Intel Strataflash
+ */
+#undef  CFG_FLASH_16BIT				/* 32-bit wide flash memory */
+#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	71		/* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4		/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+
+#ifdef CONFIG_WATCHDOG
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR	(SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ */
+
+/* MF (Multiplication Factor of SPLL) */
+/* Sets the QS823 to specified clock from 32KHz clock at EXTAL. */
+#define vPLPRCR_MF	((CONFIG_CLOCK_MULT+1) << 20)
+#define CFG_PLPRCR	(vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ */
+#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
+#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
+#define CFG_BRGCLK_PRESCALE	1
+#endif
+
+#if defined(CONFIG_CLOCK_66MHZ)
+#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
+#define CFG_BRGCLK_PRESCALE	4
+#endif
+
+#if defined(CONFIG_CLOCK_80MHZ)
+#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
+#define CFG_BRGCLK_PRESCALE	4
+#endif
+
+#define SCCR_MASK		CFG_SCCR
+
+/*-----------------------------------------------------------------------
+ * Debug Enable Register
+ * 0x73E67C0F - All interrupts handled by BDM
+ * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
+ *-----------------------------------------------------------------------
+#define CFG_DER			0x73E67C0F
+#define CFG_DER			0x0082400F
+
+ #-------------------------------------------------------------------------
+ # Program the Debug Enable Register (DER). This register provides the user
+ # with the reason for entering into the debug mode. We want all conditions
+ # to end up as an exception. We don't want to enter into debug mode for
+ # any condition. See the back of of the Development Support section of the
+ # MPC860 User Manual for a description of this register.
+ #-------------------------------------------------------------------------
+*/
+#define CFG_DER			0
+
+/*-----------------------------------------------------------------------
+ * Memory Controller Initialization Constants
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * BR0 and OR0 (AMD dual FLASH devices)
+ * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
+ */
+#define CFG_PRELIM_OR_AM
+#define CFG_OR_TIMING_FLASH
+
+/*
+ *-----------------------------------------------------------------------
+ * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
+ *                        flash that resides on the QS823.
+ *-----------------------------------------------------------------------
+ */
+
+/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
+/*                     represents a minumum 32K block size. */
+#define vBR0_BA			((0xFF80 << 16) + (0 << 15))
+#define CFG_BR0_PRELIM		(vBR0_BA | BR_V)
+
+/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits        */
+/*                                 which defines a 8 Mbyte memory block. */
+#define vOR0_AM			((0xFF80 << 16) + (0 << 15))
+
+#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
+/*  0101 = Add a 5 clock cycle wait state */
+#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
+#endif
+
+#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
+/*  0011 = Add a 3 clock cycle wait state */
+/*  29.8ns clock * (3 + 2) = 149ns cycle time */
+#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
+#endif
+
+#if defined(CONFIG_CLOCK_16MHZ)
+/*  0010 = Add a 2 clock cycle wait state */
+#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
+#endif
+
+/*
+ * BR1 and OR1 (SDRAM)
+ * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
+ * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation)
+ * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
+ * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
+ */
+
+#define SDRAM_BASE		0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+
+/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
+ *                                 represents a 128 Mbyte block the DRAM in
+ *                                 this address base.
+ */
+#define vOR1_AM			((0xF800 << 16) + (0 << 15))
+#define vBR1_BA			((0x0000 << 16) + (0 << 15))
+#define CFG_OR1			(vOR1_AM | OR_CSNT_SAM | OR_BI)
+#define CFG_BR1			(vBR1_BA | BR_MS_UPMA | BR_V)
+
+/* Machine A Mode Register */
+
+/* PTA Periodic Timer A */
+
+#if defined(CONFIG_CLOCK_80MHZ)
+#define vMAMR_PTA		(19 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_66MHZ)
+#define vMAMR_PTA		(16 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_50MHZ)
+#define vMAMR_PTA		(195 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_33MHZ)
+#define vMAMR_PTA		(131 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_16MHZ)
+#define vMAMR_PTA		(65 << 24)
+#endif
+
+/* For boards with 16M of SDRAM */
+#define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
+#define CFG_16M_MAMR 		(vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
+MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+/* For boards with 32M of SDRAM */
+#define SDRAM_32M_MAX_SIZE	0x02000000	/* max 32MB SDRAM */
+#define CFG_32M_MAMR 		(vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
+MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+
+/* Memory Periodic Timer Prescaler Register */
+
+#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
+/* Divide by 32 */
+#define CFG_MPTPR		0x02
+#endif
+
+#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
+/* Divide by 16 */
+#define CFG_MPTPR		0x04
+#endif
+
+/*
+ * BR2 and OR2 (Unused)
+ * Base address = 0xF020_0000 - 0xF020_0FFF
+ *
+ */
+#define CFG_OR2_PRELIM		0xFFF00000
+#define CFG_BR2_PRELIM		0xF0200000
+
+/*
+ * BR3 and OR3 (External Bus CS3)
+ * Base address = 0xF030_0000 - 0xF030_0FFF
+ *
+ */
+#define CFG_OR3_PRELIM		0xFFF00000
+#define CFG_BR3_PRELIM		0xF0300000
+
+/*
+ * BR4 and OR4 (External Bus CS3)
+ * Base address = 0xF040_0000 - 0xF040_0FFF
+ *
+ */
+#define CFG_OR4_PRELIM		0xFFF00000
+#define CFG_BR4_PRELIM		0xF0400000
+
+
+/*
+ * BR4 and OR4 (External Bus CS3)
+ * Base address = 0xF050_0000 - 0xF050_0FFF
+ *
+ */
+#define CFG_OR5_PRELIM		0xFFF00000
+#define CFG_BR5_PRELIM		0xF0500000
+
+/*
+ * BR6 and OR6 (Unused)
+ * Base address = 0xF060_0000 - 0xF060_0FFF
+ *
+ */
+#define CFG_OR6_PRELIM		0xFFF00000
+#define CFG_BR6_PRELIM		0xF0600000
+
+/*
+ * BR7 and OR7 (Unused)
+ * Base address = 0xF070_0000 - 0xF070_0FFF
+ *
+ */
+#define CFG_OR7_PRELIM		0xFFF00000
+#define CFG_BR7_PRELIM		0xF0700000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+/*
+ * Sanity checks
+ */
+#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
+#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/QS850.h b/include/configs/QS850.h
new file mode 100755
index 0000000..967582b
--- /dev/null
+++ b/include/configs/QS850.h
@@ -0,0 +1,571 @@
+/*
+ * (C) Copyright 2003
+ * MuLogic B.V.
+ *
+ * (C) Copyright 2002
+ * Simple Network Magic Corporation
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* various debug settings */
+#undef CFG_DEVICE_NULLDEV		/* null device */
+#undef CONFIG_SILENT_CONSOLE		/* silent console */
+#undef CFG_CONSOLE_INFO_QUIET		/* silent console ? */
+#undef DEBUG				/* debug output code */
+#undef DEBUG_FLASH			/* debug flash code */
+#undef FLASH_DEBUG			/* debug fash code */
+#undef DEBUG_ENV			/* debug environment code */
+
+#define CFG_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
+#define CONFIG_ENV_OVERWRITE	1	/* allow overwrite MAC address */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU */
+#define CONFIG_QS850		1	/* ...on a QS850 module */
+#define CONFIG_SCC2_ENET	1	/* SCC2 10BaseT ethernet */
+
+/* Select the target clock speed */
+#undef CONFIG_CLOCK_16MHZ		/* cpu=16,777,216 Hz, mem=16Mhz */
+#undef CONFIG_CLOCK_33MHZ		/* cpu=33,554,432 Hz, mem=33Mhz */
+#undef CONFIG_CLOCK_50MHZ		/* cpu=49,971,200 Hz, mem=33Mhz */
+#define CONFIG_CLOCK_66MHZ	1	/* cpu=67,108,864 Hz, mem=66Mhz */
+#undef CONFIG_CLOCK_80MHZ		/* cpu=79,986,688 Hz, mem=33Mhz */
+
+#ifdef CONFIG_CLOCK_16MHZ
+#define CONFIG_CLOCK_MULT	512
+#endif
+
+#ifdef CONFIG_CLOCK_33MHZ
+#define CONFIG_CLOCK_MULT	1024
+#endif
+
+#ifdef CONFIG_CLOCK_50MHZ
+#define CONFIG_CLOCK_MULT	1525
+#endif
+
+#ifdef CONFIG_CLOCK_66MHZ
+#define CONFIG_CLOCK_MULT	2048
+#endif
+
+#ifdef CONFIG_CLOCK_80MHZ
+#define CONFIG_CLOCK_MULT	2441
+#endif
+
+/* choose flash size, 4Mb or 8Mb */
+#define CONFIG_FLASH_4MB	1	/* board has 4Mb flash */
+#undef CONFIG_FLASH_8MB			/* board has 8Mb flash */
+
+#define CONFIG_CLOCK_BASE	32768	/* Base clock input freq */
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		38400	/* console baudrate = 38.4kbps */
+
+#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */
+
+/* Define default IP addresses */
+#define CONFIG_IPADDR		192.168.1.99	/* own ip address */
+#define CONFIG_SERVERIP		192.168.1.19	/* used for tftp (not nfs?) */
+
+/* message to say directly after booting */
+#define CONFIG_PREBOOT		"echo '';" \
+	"echo 'type:';" \
+	"echo 'run boot_nfs       to boot to NFS';" \
+	"echo 'run boot_flash     to boot to flash';" \
+	"echo '';" \
+	"echo 'run flash_rootfs   to install a new rootfs';" \
+	"echo 'run flash_env      to clear the env sector';" \
+	"echo 'run flash_rw       to clear the rw fs';" \
+	"echo 'run flash_uboot    to install a new u-boot';" \
+	"echo 'run flash_kernel   to install a new kernel';"
+
+/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOTCOMMAND	"run boot_nfs"
+
+#undef CONFIG_BOOTARGS		/* made by set_nfs of set_flash */
+
+/* Our flash filesystem looks like this
+ *
+ * 4Mb board:
+ * ffc0 0000 - ffeb ffff	root filesystem (jffs2) (~3Mb)
+ * ffec 0000 - ffed ffff	read-write filesystem (ext2)
+ * ffee 0000 - ffef ffff	environment
+ * fff0 0000 - fff1 ffff	u-boot
+ * fff2 0000 - ffff ffff	linux kernel
+ *
+ * 8Mb board:
+ * ff80 0000 - ffeb ffff	root filesystem (jffs2) (~7Mb)
+ * ffec 0000 - ffed ffff	read-write filesystem (ext2)
+ * ffee 0000 - ffef ffff	environment
+ * fff0 0000 - fff1 ffff	u-boot
+ * fff2 0000 - ffff ffff	linux kernel
+ *
+ */
+
+/* environment for 4Mb board */
+#ifdef CONFIG_FLASH_4MB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"serial#=QS850\0" \
+	"hostname=qs850\0" \
+	"netdev=eth0\0" \
+	"ethaddr=00:01:02:B4:36:56\0" \
+	"rootpath=/exports/rootfs\0" \
+	"mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
+	/* fill in variables */ \
+	"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
+	"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
+	"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
+	/* commands */ \
+	"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
+	"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
+	/* reinstall flash parts */ \
+	"flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
+	"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
+	"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
+	"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
+	"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
+#endif /* CONFIG_FLASH_4MB */
+
+/* environment for 8Mb board */
+#ifdef CONFIG_FLASH_8MB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"serial#=QS850\0" \
+	"hostname=qs850\0" \
+	"netdev=eth0\0" \
+	"ethaddr=00:01:02:B4:36:56\0" \
+	"rootpath=/exports/rootfs\0" \
+	"mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
+	/* fill in variables */ \
+	"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
+	"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
+	"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
+	/* commands */ \
+	"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
+	"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
+	/* reinstall flash parts */ \
+	"flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
+	"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
+	"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
+	"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
+	"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
+#endif /* CONFIG_FLASH_8MB */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change */
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+#undef CONFIG_STATUS_LED		/* Status LED disabled */
+#undef CONFIG_CAN_DRIVER		/* CAN Driver support disabled */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_MPC8xx	/* use internal RTC of MPC8xx */
+
+#define CONFIG_COMMANDS		(CFG_CMD_BDI	| \
+	CFG_CMD_BOOTD	| \
+	CFG_CMD_CONSOLE	| \
+	CFG_CMD_DATE	| \
+	CFG_CMD_ENV	| \
+	CFG_CMD_FLASH	| \
+	CFG_CMD_IMI	| \
+	CFG_CMD_IMMAP	| \
+	CFG_CMD_MEMORY	| \
+	CFG_CMD_NET	| \
+	CFG_CMD_RUN)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*-----------------------------------------------------------------------
+ * Environment variable storage is in FLASH, one sector before U-boot
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	0x20000		/* 128Kb, one whole sector */
+#define CFG_ENV_SIZE		0x2000		/* 8kb */
+#define CFG_ENV_ADDR		0xffee0000	/* address of env sector */
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory */
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+
+#define CFG_HUSH_PARSER		1		/* use "hush" command parser */
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works */
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR		0x400000	/* default load address */
+
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFF800000	/* Allow an 8Mbyte window */
+
+#define FLASH_BASE0_4M_PRELIM	0xFFC00000	/* Base for 4M Flash */
+#define FLASH_BASE0_8M_PRELIM	0xFF800000	/* Base for 8M Flash */
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CFG_MONITOR_BASE	0xFFF00000	/* U-boot location */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * TODO flash parameters
+ * FLASH organization for Intel Strataflash
+ */
+#undef  CFG_FLASH_16BIT				/* 32-bit wide flash memory */
+#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	71		/* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4		/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+
+#ifdef CONFIG_WATCHDOG
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR	(SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ */
+
+/* MF (Multiplication Factor of SPLL) */
+/* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */
+#define vPLPRCR_MF	((CONFIG_CLOCK_MULT+1) << 20)
+#define CFG_PLPRCR	(vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ */
+#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
+#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
+#define CFG_BRGCLK_PRESCALE	1
+#endif
+
+#if defined(CONFIG_CLOCK_66MHZ)
+#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
+#define CFG_BRGCLK_PRESCALE	4
+#endif
+
+#if defined(CONFIG_CLOCK_80MHZ)
+#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
+#define CFG_BRGCLK_PRESCALE	4
+#endif
+
+#define SCCR_MASK		CFG_SCCR
+
+/*-----------------------------------------------------------------------
+ * Debug Enable Register
+ * 0x73E67C0F - All interrupts handled by BDM
+ * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
+ *-----------------------------------------------------------------------
+#define CFG_DER			0x73E67C0F
+#define CFG_DER			0x0082400F
+
+ #-------------------------------------------------------------------------
+ # Program the Debug Enable Register (DER). This register provides the user
+ # with the reason for entering into the debug mode. We want all conditions
+ # to end up as an exception. We don't want to enter into debug mode for
+ # any condition. See the back of of the Development Support section of the
+ # MPC860 User Manual for a description of this register.
+ #-------------------------------------------------------------------------
+*/
+#define CFG_DER			0
+
+/*-----------------------------------------------------------------------
+ * Memory Controller Initialization Constants
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * BR0 and OR0 (AMD dual FLASH devices)
+ * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
+ */
+#define CFG_PRELIM_OR_AM
+#define CFG_OR_TIMING_FLASH
+
+/*
+ *-----------------------------------------------------------------------
+ * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
+ *                        flash that resides on the QS850.
+ *-----------------------------------------------------------------------
+ */
+
+/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
+/*                     represents a minumum 32K block size. */
+#define vBR0_BA			((0xFF80 << 16) + (0 << 15))
+#define CFG_BR0_PRELIM		(vBR0_BA | BR_V)
+
+/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits        */
+/*                                 which defines a 8 Mbyte memory block. */
+#define vOR0_AM			((0xFF80 << 16) + (0 << 15))
+
+#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
+/*  0101 = Add a 5 clock cycle wait state */
+#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
+#endif
+
+#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
+/*  0011 = Add a 3 clock cycle wait state */
+/*  29.8ns clock * (3 + 2) = 149ns cycle time */
+#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
+#endif
+
+#if defined(CONFIG_CLOCK_16MHZ)
+/*  0010 = Add a 2 clock cycle wait state */
+#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
+#endif
+
+/*
+ * BR1 and OR1 (SDRAM)
+ * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
+ * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation)
+ * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
+ * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
+ */
+
+#define SDRAM_BASE		0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+
+/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
+ *                                 represents a 128 Mbyte block the DRAM in
+ *                                 this address base.
+ */
+#define vOR1_AM			((0xF800 << 16) + (0 << 15))
+#define vBR1_BA			((0x0000 << 16) + (0 << 15))
+#define CFG_OR1			(vOR1_AM | OR_CSNT_SAM | OR_BI)
+#define CFG_BR1			(vBR1_BA | BR_MS_UPMA | BR_V)
+
+/* Machine A Mode Register */
+
+/* PTA Periodic Timer A */
+
+#if defined(CONFIG_CLOCK_80MHZ)
+#define vMAMR_PTA		(19 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_66MHZ)
+#define vMAMR_PTA		(16 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_50MHZ)
+#define vMAMR_PTA		(195 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_33MHZ)
+#define vMAMR_PTA		(131 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_16MHZ)
+#define vMAMR_PTA		(65 << 24)
+#endif
+
+/* For boards with 16M of SDRAM */
+#define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
+#define CFG_16M_MAMR 		(vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
+MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+/* For boards with 32M of SDRAM */
+#define SDRAM_32M_MAX_SIZE	0x02000000	/* max 32MB SDRAM */
+#define CFG_32M_MAMR 		(vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
+MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+
+/* Memory Periodic Timer Prescaler Register */
+
+#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
+/* Divide by 32 */
+#define CFG_MPTPR		0x02
+#endif
+
+#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
+/* Divide by 16 */
+#define CFG_MPTPR		0x04
+#endif
+
+/*
+ * BR2 and OR2 (Unused)
+ * Base address = 0xF020_0000 - 0xF020_0FFF
+ *
+ */
+#define CFG_OR2_PRELIM		0xFFF00000
+#define CFG_BR2_PRELIM		0xF0200000
+
+/*
+ * BR3 and OR3 (External Bus CS3)
+ * Base address = 0xF030_0000 - 0xF030_0FFF
+ *
+ */
+#define CFG_OR3_PRELIM		0xFFF00000
+#define CFG_BR3_PRELIM		0xF0300000
+
+/*
+ * BR4 and OR4 (External Bus CS3)
+ * Base address = 0xF040_0000 - 0xF040_0FFF
+ *
+ */
+#define CFG_OR4_PRELIM		0xFFF00000
+#define CFG_BR4_PRELIM		0xF0400000
+
+
+/*
+ * BR4 and OR4 (External Bus CS3)
+ * Base address = 0xF050_0000 - 0xF050_0FFF
+ *
+ */
+#define CFG_OR5_PRELIM		0xFFF00000
+#define CFG_BR5_PRELIM		0xF0500000
+
+/*
+ * BR6 and OR6 (Unused)
+ * Base address = 0xF060_0000 - 0xF060_0FFF
+ *
+ */
+#define CFG_OR6_PRELIM		0xFFF00000
+#define CFG_BR6_PRELIM		0xF0600000
+
+/*
+ * BR7 and OR7 (Unused)
+ * Base address = 0xF070_0000 - 0xF070_0FFF
+ *
+ */
+#define CFG_OR7_PRELIM		0xFFF00000
+#define CFG_BR7_PRELIM		0xF0700000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+/*
+ * Sanity checks
+ */
+#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
+#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h
new file mode 100755
index 0000000..32faa61
--- /dev/null
+++ b/include/configs/QS860T.h
@@ -0,0 +1,410 @@
+/*
+ * (C) Copyright 2003
+ * MuLogic B.V.
+ *
+ * (C) Copyright 2002
+ * Simple Network Magic Corporation
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* various debug settings */
+#undef CFG_DEVICE_NULLDEV		/* null device */
+#undef CONFIG_SILENT_CONSOLE		/* silent console */
+#undef CFG_CONSOLE_INFO_QUIET		/* silent console ? */
+#undef DEBUG				/* debug output code */
+#undef DEBUG_FLASH			/* debug flash code */
+#undef FLASH_DEBUG			/* debug fash code */
+#undef DEBUG_ENV			/* debug environment code */
+
+#define CFG_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
+#define CONFIG_ENV_OVERWRITE	1	/* allow overwrite MAC address */
+
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU */
+#define CONFIG_QS860T		1	/* ...on a QS860T module */
+
+#define CONFIG_FEC_ENET		1	/* FEC 10/100BaseT ethernet */
+#define CONFIG_MII
+#define FEC_INTERRUPT		SIU_LEVEL1
+#undef CONFIG_SCC1_ENET			/* SCC1 10BaseT ethernet */
+#define CFG_DISCOVER_PHY
+
+#undef CONFIG_8xx_CONS_SMC1
+#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC */
+#undef CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		38400	/* console baudrate = 38.4kbps */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+/* Pass clocks to Linux 2.4.18 in Hz */
+#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT		"echo;" \
+	"echo 'Type \"run flash_nfs\" to mount root filesystem over NFS';" \
+	"echo"
+
+#undef CONFIG_BOOTARGS
+/* TODO compare against CADM860 */
+#define CONFIG_BOOTCOMMAND	"bootp; " \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change */
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#undef CONFIG_STATUS_LED		/* Status LED disabled */
+
+#undef CONFIG_CAN_DRIVER		/* CAN Driver support disabled */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_MPC8xx	/* use internal RTC of MPC8xx */
+
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
+	CFG_CMD_REGINFO	| \
+	CFG_CMD_IMMAP	| \
+	CFG_CMD_ASKENV	| \
+	CFG_CMD_NET	| \
+	CFG_CMD_DHCP	| \
+	CFG_CMD_DATE	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+
+/* TODO */
+#if 0
+/* Look at these */
+CONFIG_IPADDR
+CONFIG_SERVERIP
+CONFIG_I2C
+CONFIG_SPI
+#endif
+
+/*
+ * Environment variable storage is in NVRAM
+ */
+#define CFG_ENV_IS_IN_NVRAM	1
+#define CFG_ENV_SIZE		0x00001000	/* We use only the last 4K for PPCBoot */
+#define CFG_ENV_ADDR		0xD100E000
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory */
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+
+#define CFG_HUSH_PARSER		1		/* use "hush" command parser */
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+/* TODO - size? */
+#define CFG_MEMTEST_START	0x0400000	/* memtest works */
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFF00000
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/* TODO flash parameters */
+/*-----------------------------------------------------------------------
+ * FLASH organization for Intel Strataflash
+ */
+#define CFG_FLASH_16BIT		1		/* 16-bit wide flash memory */
+#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	64		/* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */
+
+#undef	CFG_ENV_IS_IN_FLASH
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4		/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI)
+#else
+#define CFG_SYPCR	0xFFFFFF88
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR	0x00620000
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ */
+#define CFG_TBSCR	0x00C3
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_PISCR	0x0082
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ */
+#define CFG_PLPRCR	0x0090D000
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	0x02000000
+
+
+/*-----------------------------------------------------------------------
+ * Debug Enable Register
+ * 0x73E67C0F - All interrupts handled by BDM
+ * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
+ *-----------------------------------------------------------------------
+#define CFG_DER			0x73E67C0F
+*/
+#define CFG_DER			0x0082400F
+
+
+/*-----------------------------------------------------------------------
+ * Memory Controller Initialization Constants
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * BR0 and OR0 (AMD 512K Socketed FLASH)
+ * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
+ */
+#define CFG_PRELIM_OR_AM
+#define CFG_OR_TIMING_FLASH
+
+#define FLASH_BASE0_PRELIM	0xFFF00001
+#define CFG_OR0_PRELIM		0xFFF80D42
+#define CFG_BR0_PRELIM		0xFFF00401
+
+
+/*
+ * BR1 and OR1 (Intel 8M StrataFLASH)
+ * Base address = 0xD000_0000 - 0xD07F_FFFF
+ */
+
+#define FLASH_BASE1_PRELIM	0xD0000000
+#define CFG_OR1_PRELIM		0xFF800D42
+#define CFG_BR1_PRELIM		0xD0000801
+/* #define CFG_OR1		0xFF800D42 */
+/* #define CFG_BR1		0xD0000801 */
+
+
+/*
+ * BR2 and OR2 (SDRAM)
+ * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
+ * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
+ * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
+ *
+ */
+#define SDRAM_BASE		0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+
+/* SDRAM timing */
+#define SDRAM_TIMING		0x00000A00
+
+/* For boards with 16M of SDRAM */
+#define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
+#define CFG_16M_MBMR		0x18802114	/* Mem Periodic Timer Prescaler */
+
+/* For boards with 64M of SDRAM */
+#define SDRAM_64M_MAX_SIZE	0x04000000	/* max 64MB SDRAM */
+/* TODO - determine real value */
+#define CFG_64M_MBMR		0x18802114	/* Mem Period Timer Prescaler */
+
+#define CFG_OR2			(SDRAM_PRELIM_OR_AM | SDRAM_TIMING)
+#define CFG_BR2			(SDRAM_BASE | 0x000000C1)
+
+
+/*
+ * BR3 and OR3 (NVRAM, Sipex, NAND Flash)
+ * Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM)
+ * Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register)
+ * Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register)
+ * Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register)
+ *
+ */
+
+#define CFG_OR3_PRELIM		0xFFC00DF6
+#define CFG_BR3_PRELIM		0xD1000401
+/* #define CFG_OR3		0xFFC00DF6 */
+/* #define CFG_BR3		0xD1000401 */
+
+
+/*
+ * BR4 and OR4 (Unused)
+ * Base address = 0xE000_0000 - 0xE3FF_FFFF
+ *
+ */
+
+#define CFG_OR4_PRELIM		0xFF000000
+#define CFG_BR4_PRELIM		0xE0000000
+/* #define CFG_OR4		0xFF000000 */
+/* #define CFG_BR4		0xE0000000 */
+
+
+/*
+ * BR5 and OR5 (Expansion bus)
+ * Base address = 0xE400_0000 - 0xE7FF_FFFF
+ *
+ */
+
+#define CFG_OR5_PRELIM		0xFF000000
+#define CFG_BR5_PRELIM		0xE4000000
+/* #define CFG_OR5		0xFF000000 */
+/* #define CFG_BR5		0xE4000000 */
+
+
+/*
+ * BR6 and OR6 (Expansion bus)
+ * Base address = 0xE800_0000 - 0xEBFF_FFFF
+ *
+ */
+
+#define CFG_OR6_PRELIM		0xFF000000
+#define CFG_BR6_PRELIM		0xE8000000
+/* #define CFG_OR6		0xFF000000 */
+/* #define CFG_BR6		0xE8000000 */
+
+
+/*
+ * BR7 and OR7 (Expansion bus)
+ * Base address = 0xEC00_0000 - 0xEFFF_FFFF
+ *
+ */
+
+#define CFG_OR7_PRELIM		0xFF000000
+#define CFG_BR7_PRELIM		0xE8000000
+/* #define CFG_OR7		0xFF000000 */
+/* #define CFG_BR7		0xE8000000 */
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+/*
+ * Sanity checks
+ */
+#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
+#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h
new file mode 100755
index 0000000..82228c0
--- /dev/null
+++ b/include/configs/R360MPI.h
@@ -0,0 +1,476 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_R360MPI		1
+
+#define CONFIG_LCD
+#undef  CONFIG_EDT32F10
+#define CONFIG_SHARP_LQ057Q3DC02
+
+#define	CONFIG_SPLASH_SCREEN
+
+#define MPC8XX_FACT             1		/* Multiply by 1	*/
+#define MPC8XX_XIN              50000000	/* 50 MHz in		*/
+#define CONFIG_8xx_GCLK_FREQ    50000000 /* define if can't use get_gclk_freq */
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate in bps	*/
+#if 0
+#define CONFIG_BOOTDELAY	0	/* immediate boot		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+#undef	CONFIG_SCC1_ENET
+#define	CONFIG_SCC2_ENET
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#define	CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_CAN_DRIVER		/* CAN Driver support enabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_HARD_I2C		1	/* To I2C with hardware support */
+#undef CONFIG_SORT_I2C			/* To I2C with software support */
+#define CFG_I2C_SPEED		4700	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL			0x00000020	/* PB 26 */
+#define PB_SDA			0x00000010	/* PB 27 */
+
+#define I2C_INIT		(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE		(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE		(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ		((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+				else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+				else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY		udelay(50)
+
+#define CFG_I2C_LCD_ADDR	0x8	/* LCD Control */
+#define CFG_I2C_KEY_ADDR	0x9	/* Keyboard coprocessor */
+#define CFG_I2C_TEM_ADDR	0x49	/* Temperature Sensors */
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BMP	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCMCIA	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_DEVICE_NULLDEV	1	/* we need the null device	*/
+#define CFG_CONSOLE_IS_IN_ENV	1	/* must set console from env	*/
+
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition
+ * use all the space starting at offset 3MB*/
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00300000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=r360-0"
+#define MTDPARTS_DEFAULT	"mtdparts=r360-0:-@3m(user)"
+*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x40000	/* Offset of Environment		*/
+#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Used Size of Environment sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_PLPRCR							\
+		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else			/* up to 50 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif	/* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#if 1
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFF000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+
+/*
+ * BR2 and OR2 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+#define CFG_PRELIM_OR2_AM	0xF8000000	/* OR addr mask */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	(OR_ACS_DIV1  | OR_CSNT_SAM | \
+				 OR_SCY_0_CLK | OR_G5LS)
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR2_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR3 and OR3 (CAN Controller)
+ */
+#ifdef CONFIG_CAN_DRIVER
+#define CFG_CAN_BASE		0xC0000000	/* CAN base address   */
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask */
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA |OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+				 BR_PS_8 | BR_MS_UPMB | BR_V)
+#endif	/* CONFIG_CAN_DRIVER */
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#if   defined(CONFIG_80MHz)
+#define CFG_MAMR_PTA		156
+#elif defined(CONFIG_66MHz)
+#define CFG_MAMR_PTA		129
+#else		/*   50 MHz */
+#define CFG_MAMR_PTA		 98
+#endif	/*CONFIG_??MHz */
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
new file mode 100755
index 0000000..242c837
--- /dev/null
+++ b/include/configs/RBC823.h
@@ -0,0 +1,439 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Udi Finkelstein udif@udif.com
+ * For the RBC823 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_RBC823		1	/* ...on a RBC823 module	*/
+
+
+#if 0
+#define DEBUG			1
+#define CONFIG_LAST_STAGE_INIT
+#endif
+#define CONFIG_KEYBOARD		1	/* This board has a custom keybpard */
+#define CONFIG_LCD		1	/* use LCD controller ...	*/
+#define CONFIG_HITACHI_SP19X001_Z1A	/* The LCD type we use */
+
+#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#undef	CONFIG_8xx_CONS_SMC1
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+#if 1
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_8xx_GCLK_FREQ    48000000L
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#undef CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef	CONFIG_RTC_MPC8xx		/* don't use internal RTC of MPC8xx (no battery)	*/
+
+#define CONFIG_HARD_I2C
+#define CFG_I2C_SPEED 40000
+#define CFG_I2C_SLAVE 0xfe
+#define CFG_I2C_EEPROM_ADDR		0x50
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_WRITE_BITS		4
+#define CFG_EEPROM_WRITE_DELAY_MS	10
+
+#define CONFIG_COMMANDS	      ( CFG_CMD_ALL	& \
+				~CFG_CMD_BSP	& \
+				~CFG_CMD_DATE	& \
+				~CFG_CMD_DISPLAY& \
+				~CFG_CMD_DTT	& \
+				~CFG_CMD_EXT2	& \
+				~CFG_CMD_FDC	& \
+				~CFG_CMD_FDOS	& \
+				~CFG_CMD_HWFLOW	& \
+				~CFG_CMD_IDE	& \
+				~CFG_CMD_IRQ	& \
+				~CFG_CMD_JFFS2	& \
+				~CFG_CMD_MII	& \
+				~CFG_CMD_MMC	& \
+				~CFG_CMD_NAND	& \
+				~CFG_CMD_PCI	& \
+				~CFG_CMD_PCMCIA	& \
+				~CFG_CMD_REISER	& \
+				~CFG_CMD_SCSI	& \
+				~CFG_CMD_SETGETDCR & \
+				~CFG_CMD_SNTP	& \
+				~CFG_CMD_SPI	& \
+				~CFG_CMD_UNIVERSE & \
+				~CFG_CMD_USB	& \
+				~CFG_CMD_VFD	& \
+				~CFG_CMD_XIMG	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x0100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFF00000
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+/*
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+*/
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+/*
+ * for 48 MHz, we use a 4 MHz clock * 12
+ */
+#define CFG_PLPRCR							\
+		( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_RTDIV   | SCCR_RTSEL    | SCCR_CRQEN    | \
+		         SCCR_PRQEN   | SCCR_EBDF00   | \
+		         SCCR_COM01   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD001 | \
+			 SCCR_DFALCD00)
+
+#ifdef NOT_USED
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+#endif
+
+/************************************************************
+ * Disk-On-Chip configuration
+ ************************************************************/
+#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+#define CFG_DOC_SHORT_TIMEOUT
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x04000000	/* D.O.C Millenium	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+
+/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH  (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
+
+#define CFG_OR_TIMING_MSYS   (OR_ACS_DIV1 | OR_BI)
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
+
+#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_MSYS)
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
+		          BR_PS_8 | BR_V)
+
+/*
+ * BR4 and OR4 (SDRAM)
+ *
+ */
+#define SDRAM_BASE4_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/*
+ * SDRAM timing:
+ */
+#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM)
+
+#define CFG_OR4_PRELIM	(~(SDRAM_MAX_SIZE-1) | CFG_OR_TIMING_SDRAM )
+#define CFG_BR4_PRELIM	((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	187		/* start with divider for 48 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		""
+#define MTDPARTS_DEFAULT	""
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h
new file mode 100755
index 0000000..591382c
--- /dev/null
+++ b/include/configs/RPXClassic.h
@@ -0,0 +1,495 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define	RPXClassic_50MHz
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860           1
+#define CONFIG_RPXCLASSIC		1
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
+
+/* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1   */
+#define CONFIG_FEC_ENET
+#ifdef CONFIG_FEC_ENET
+#define CFG_DISCOVER_PHY        1
+#define CONFIG_MII              1
+#endif /* CONFIG_FEC_ENET */
+
+/* Video console (graphic: Epson SED13806 on ECCX board, no keyboard         */
+#if 1
+#define CONFIG_VIDEO_SED13806
+#define CONFIG_NEC_NL6448BC20
+#define CONFIG_VIDEO_SED13806_16BPP
+
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#endif
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK 1
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+
+#define CONFIG_COMMANDS	((CFG_CMD_ALL & ~CFG_CMD_NONSTD) | CFG_CMD_ELF)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_RESET_ADDRESS	0x80000000
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0040000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFA200000
+
+/*-----------------------------------------------------------------------------
+ * I2C Configuration
+ *-----------------------------------------------------------------------------
+ */
+#define CONFIG_I2C              1
+#define CFG_I2C_SPEED           50000
+#define CFG_I2C_SLAVE           0x34
+
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef  CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_PORT	1		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00000010)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00000010)
+#define I2C_READ	((iop->pdat & 0x00000010) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00000010; \
+			else    iop->pdat &= ~0x00000010
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00000020; \
+			else    iop->pdat &= ~0x00000020
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+
+# define CFG_I2C_SPEED		50000
+# define CFG_I2C_SLAVE		0x34
+# define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM X24C16		*/
+# define CFG_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE	0xFF000000
+
+#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	0xFF000000
+/*%%% #define CFG_MONITOR_BASE	CFG_FLASH_BASE */
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#if 0
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x20000	/*   Offset   of Environment Sector  */
+#define CFG_ENV_SECT_SIZE       0x8000
+#define	CFG_ENV_SIZE		0x8000	/* Total Size of Environment Sector  */
+#else
+#define CFG_ENV_IS_IN_NVRAM     1
+#define CFG_ENV_ADDR            0xfa000100
+#define CFG_ENV_SIZE            0x1000
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_MLRC10)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CFG_RTCSC	(RTCSC_SEC |  RTCSC_ALR | RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+/* up to 50 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+/* up to 50 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_COM00 | SCCR_TBS)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/* #define	CFG_DER	0x2002000F */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE_PRELIM	0xFE000000	/* FLASH base */
+#define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
+#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
+
+/*
+ * BR1 and OR1 (SDRAM)
+ *
+ */
+#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
+#define	SDRAM_MAX_SIZE		0x01000000	/* max 16 MB */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000E00
+
+#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/* RPXLITE mem setting */
+#define	CFG_BR3_PRELIM	0xFA400001		/* BCSR */
+#define CFG_OR3_PRELIM	0xff7f8970
+#define	CFG_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
+#define CFG_OR4_PRELIM	0xFFF80970
+
+/* ECCX CS settings                                                          */
+#define SED13806_OR             0xFFC00108     /* - 4 Mo
+						   - Burst inhibit
+						   - external TA             */
+#define SED13806_REG_ADDR       0xa0000000
+#define SED13806_ACCES          0x801           /* 16 bit access             */
+
+
+/* Global definitions for the ECCX board                                     */
+#define ECCX_CSR_ADDR           (0xfac00000)
+#define ECCX_CSR8_OFFSET        (0x8)
+#define ECCX_CSR11_OFFSET       (0xB)
+#define ECCX_CSR12_OFFSET       (0xC)
+
+#define ECCX_CSR8  (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET)
+#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET)
+#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET)
+
+
+#define REG_GPIO_CTRL 0x008
+
+/* Definitions for CSR8                                                      */
+#define ECCX_ENEPSON            0x80    /* Bit 0:
+					   0= disable and reset SED1386
+					   1= enable SED1386                 */
+/* Bit 1:   0= SED1386 in Big Endian mode                                    */
+/*          1= SED1386 in little endian mode                                 */
+#define ECCX_LE                 0x40
+#define ECCX_BE                 0x00
+
+/* Bit 2,3: Selection                                                        */
+/*      00 = Disabled                                                        */
+/*      01 = CS2 is used for the SED1386                                     */
+/*      10 = CS5 is used for the SED1386                                     */
+/*      11 = reserved                                                        */
+#define ECCX_CS2                0x10
+#define ECCX_CS5                0x20
+
+/* Definitions for CSR12                                                     */
+#define ECCX_ID                 0x02
+#define ECCX_860                0x01
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	58
+
+/*
+ * Refresh clock Prescalar
+ */
+#define CFG_MPTPR	MPTPR_PTP_DIV8
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 10 column SDRAM */
+#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |	\
+			 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+
+/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
+/* Configuration variable added by yooth. */
+/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
+
+/*
+ * BCSRx
+ *
+ * Board Status and Control Registers
+ *
+ */
+
+#define BCSR0 0xFA400000
+#define BCSR1 0xFA400001
+#define BCSR2 0xFA400002
+#define BCSR3 0xFA400003
+
+#define BCSR0_ENMONXCVR	0x01	/* Monitor XVCR Control */
+#define BCSR0_ENNVRAM	0x02 	/* CS4# Control */
+#define BCSR0_LED5		0x04	/* LED5 control 0='on' 1='off' */
+#define BCSR0_LED4		0x08	/* LED4 control 0='on' 1='off' */
+#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
+#define BCSR0_COLTEST	0x20
+#define BCSR0_ETHLPBK	0x40
+#define BCSR0_ETHEN	0x80
+
+#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
+#define BCSR1_PCVCTL6	0x02
+#define BCSR1_PCVCTL5	0x04
+#define BCSR1_PCVCTL4	0x08
+#define BCSR1_IPB5SEL	0x10
+
+#define BCSR2_MIIRST    0x80
+#define BCSR2_MIIPWRDWN 0x40
+#define BCSR2_MIICTL    0x08
+
+#define BCSR3_BWRTC		0x01	/* Real Time Clock Battery */
+#define BCSR3_BWNVR		0x02	/* NVRAM Battery */
+#define BCSR3_RDY_BSY	0x04	/* Flash Operation */
+#define BCSR3_RPXL		0x08	/* Reserved (reads back '1') */
+#define BCSR3_D27		0x10	/* Dip Switch settings */
+#define BCSR3_D26		0x20
+#define BCSR3_D25		0x40
+#define BCSR3_D24		0x80
+
+
+/*
+ * Environment setting
+ */
+
+/* #define CONFIG_ETHADDR	00:10:EC:00:2C:A2 */
+/* #define CONFIG_IPADDR	10.10.106.1 */
+/* #define CONFIG_SERVERIP	10.10.104.11 */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h
new file mode 100755
index 0000000..6b65031
--- /dev/null
+++ b/include/configs/RPXlite.h
@@ -0,0 +1,392 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define	RPXLite_50MHz
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#undef CONFIG_MPC860
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_RPXLITE		1
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0040000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFA200000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE	0xFFC00000
+/*%%% #define CFG_FLASH_BASE		0xFFF00000 */
+#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	0xFFF00000
+/*%%% #define CFG_MONITOR_BASE	CFG_FLASH_BASE */
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_MLRC10)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+/* up to 50 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+/* up to 50 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_COM11 | SCCR_TBS)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE_PRELIM	0xFE000000	/* FLASH base */
+#define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
+#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
+
+/*
+ * BR1 and OR1 (SDRAM)
+ *
+ */
+#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
+#define	SDRAM_MAX_SIZE		0x01000000	/* max 16 MB */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000E00
+
+#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/* RPXLITE mem setting */
+#define	CFG_BR3_PRELIM	0xFA400001		/* BCSR */
+#define CFG_OR3_PRELIM	0xFFFF8910
+#define	CFG_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
+#define CFG_OR4_PRELIM	0xFFFE0970
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	58
+
+/*
+ * Refresh clock Prescalar
+ */
+#define CFG_MPTPR	MPTPR_PTP_DIV8
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 10 column SDRAM */
+#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |	\
+			 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+
+/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
+/* Configuration variable added by yooth. */
+/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
+
+/*
+ * BCSRx
+ *
+ * Board Status and Control Registers
+ *
+ */
+
+#define BCSR0 0xFA400000
+#define BCSR1 0xFA400001
+#define BCSR2 0xFA400002
+#define BCSR3 0xFA400003
+
+#define BCSR0_ENMONXCVR	0x01	/* Monitor XVCR Control */
+#define BCSR0_ENNVRAM	0x02 	/* CS4# Control */
+#define BCSR0_LED5		0x04	/* LED5 control 0='on' 1='off' */
+#define BCSR0_LED4		0x08	/* LED4 control 0='on' 1='off' */
+#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
+#define BCSR0_COLTEST	0x20
+#define BCSR0_ETHLPBK	0x40
+#define BCSR0_ETHEN		0x80
+
+#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
+#define BCSR1_PCVCTL6	0x02
+#define BCSR1_PCVCTL5	0x04
+#define BCSR1_PCVCTL4	0x08
+#define BCSR1_IPB5SEL	0x10
+
+#define BCSR2_ENPA5HDR	0x08	/* USB Control */
+#define BCSR2_ENUSBCLK	0x10
+#define BCSR2_USBPWREN	0x20
+#define BCSR2_USBSPD	0x40
+#define BCSR2_USBSUSP	0x80
+
+#define BCSR3_BWRTC		0x01	/* Real Time Clock Battery */
+#define BCSR3_BWNVR		0x02	/* NVRAM Battery */
+#define BCSR3_RDY_BSY	0x04	/* Flash Operation */
+#define BCSR3_RPXL		0x08	/* Reserved (reads back '1') */
+#define BCSR3_D27		0x10	/* Dip Switch settings */
+#define BCSR3_D26		0x20
+#define BCSR3_D25		0x40
+#define BCSR3_D24		0x80
+
+
+/*
+ * Environment setting
+ */
+
+#define CONFIG_ETHADDR	00:10:EC:00:1D:0B
+#define CONFIG_IPADDR	192.168.1.65
+#define CONFIG_SERVERIP	192.168.1.27
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h
new file mode 100755
index 0000000..8cd7df1
--- /dev/null
+++ b/include/configs/RPXlite_DW.h
@@ -0,0 +1,450 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-BOOT port on RPXlite board
+ */
+
+/*
+ * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+ * U-BOOT port on RPXlite DW version board--RPXlite_DW
+ * June 8 ,2004
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* #define DEBUG	1 */
+/* #ifdef DEPLOYMENT	1 */
+
+#undef	CONFIG_MPC860
+#define CONFIG_MPC823		1	/* This is a MPC823e CPU. */
+#define CONFIG_RPXLITE		1	/* RPXlite DW version board */
+
+#ifdef	CONFIG_LCD			/* with LCD controller ?	*/
+#define CONFIG_SPLASH_SCREEN		/* ... with splashscreen support*/
+#endif
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600	/* console default baudrate = 9600bps	*/
+
+#ifdef DEBUG
+#define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
+#else
+#define CONFIG_BOOTDELAY        6       /* autoboot after 6 seconds     */
+
+#ifdef DEPLOYMENT
+#define CONFIG_BOOT_RETRY_TIME          -1
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT          "autoboot in %d seconds (stop with 'st')...\n"
+#define CONFIG_AUTOBOOT_STOP_STR        "st"
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_RESET_TO_RETRY           1
+#define CONFIG_BOOT_RETRY_MIN           1
+#endif	/* DEPLOYMENT */
+#endif	/* DEBUG */
+
+/* pre-boot commands */
+#define CONFIG_PREBOOT          "setenv stdout serial;setenv stdin serial"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 "	\
+		"root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
+	"ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0"	\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"gatewayip=172.16.115.254\0"					\
+	"netmask=255.255.255.0\0"					\
+	"kernel_addr=ff040000\0"					\
+	"ramdisk_addr=ff200000\0"					\
+	"ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} "	\
+		"${filesize};md ${kernel_addr};"			\
+		"echo kernel updating finished\0"			\
+	"uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 "		\
+		"${filesize};md ff000000;"				\
+		"echo u-boot updating finished\0"			\
+	"eu=protect off 1:6;era 1:6;reset\0"				\
+	"lcd=setenv stdout lcd;setenv stdin lcd\0"			\
+	"ser=setenv stdout serial;setenv stdin serial\0"		\
+	"verify=no"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_STATUS_LED		/* disturbs display. Status LED disabled. */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"u-boot>"	/* Monitor Command Prompt   */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0040000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFA200000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00		/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFF000000
+
+#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor */
+#endif
+
+#define CFG_MONITOR_BASE	0xFF000000
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#ifdef	CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_ADDR		0xFA000100
+#define CFG_ENV_SIZE		0x1000
+#else
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_OFFSET		0x30000 /* Offset of Environment Sector		*/
+#define CFG_ENV_SIZE		0x8000	/* Total Size of Environment Sector	*/
+#endif	/* CFG_ENV_IS_IN_NVRAM */
+
+#define CFG_RESET_ADDRESS	((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control	32-bit			12-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif	/* We can get SYPCR: 0xFFFF0689. */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration	32-bit			 12-30
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_MLRC10)	       /* SIUMCR:0x00000800 */
+
+/*---------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control	 16-bit			 12-16
+ *---------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+/* TBSCR: 0x00C3 [SAM] */
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 16-bit	 12-18
+ *-----------------------------------------------------------------------
+ * [RTC enabled but not stopped on FRZ]
+ */
+#define CFG_RTCSC    (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1	*/
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 16-bit		 12-23
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ * [Periodic timer enabled,Periodic timer interrupt disable. ]
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)  /* PISCR:0x0083		*/
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	32-bit	 5-7
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+/* up to 64 MHz we use a 1:2 clock */
+#if defined(RPXlite_64MHz)
+#define CFG_PLPRCR	( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )   /*PLPRCR: 0x00700000. */
+#else
+#define CFG_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
+#endif
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		5-3
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+/* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */
+#if defined(RPXlite_64MHz)
+#define CFG_SCCR	( SCCR_TBS | SCCR_EBDF01 )  /* %%%SCCR:0x02020000 */
+#else
+#define CFG_SCCR        ( SCCR_TBS | SCCR_EBDF00 )  /* %%%SCCR:0x02000000 */
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+#define		CFG_DER		0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+#define FLASH_BASE_PRELIM	0xFC000000	/* FLASH base	*/
+#define CFG_PRELIM_OR_AM	0xFC000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */
+#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
+
+/*
+ * BR1 and OR1 (SDRAM)
+ *
+ */
+#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
+#define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB in system */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000E00
+#define CFG_OR_AM_SDRAM		(-(SDRAM_MAX_SIZE & OR_AM_MSK))
+#define CFG_OR1_PRELIM	( CFG_OR_AM_SDRAM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/* RPXlite mem setting */
+#define CFG_BR3_PRELIM	0xFA400001		/* BCSR */
+#define CFG_OR3_PRELIM	0xFF7F8900
+#define CFG_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
+#define CFG_OR4_PRELIM	0xFFFE0040
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+/* periodic timer for refresh */
+#if defined(RPXlite_64MHz)
+#define CFG_MAMR_PTA	32
+#else
+#define CFG_MAMR_PTA	20
+#endif
+
+/*
+ * Refresh clock Prescalar
+ */
+#define CFG_MPTPR	MPTPR_PTP_DIV2
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL  ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
+			MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
+/* CFG_MAMR_9COL:0x20904000 @ 64MHz */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
+/* Configuration variable added by yooth. */
+/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
+/*
+ * BCSRx
+ *
+ * Board Status and Control Registers
+ *
+ */
+#define BCSR0 0xFA400000
+#define BCSR1 0xFA400001
+#define BCSR2 0xFA400002
+#define BCSR3 0xFA400003
+
+#define BCSR0_ENMONXCVR 0x01	/* Monitor XVCR Control */
+#define BCSR0_ENNVRAM	0x02	/* CS4# Control */
+#define BCSR0_LED5	0x04	/* LED5 control 0='on' 1='off' */
+#define BCSR0_LED4	0x08	/* LED4 control 0='on' 1='off' */
+#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
+#define BCSR0_COLTEST	0x20
+#define BCSR0_ETHLPBK	0x40
+#define BCSR0_ETHEN	0x80
+
+#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
+#define BCSR1_PCVCTL6	0x02
+#define BCSR1_PCVCTL5	0x04
+#define BCSR1_PCVCTL4	0x08
+#define BCSR1_IPB5SEL	0x10
+
+#define BCSR1_SMC1CTS	0x40	/* Added by SAM. */
+#define BCSR1_SMC1TRS	0x80	/* Added by SAM. */
+
+#define BCSR2_ENRTCIRQ	0x01	/* Added by SAM. */
+#define BCSR2_ENBRG1	0x04	/* Added by SAM. */
+
+#define BCSR2_ENPA5HDR	0x08	/* USB Control */
+#define BCSR2_ENUSBCLK	0x10
+#define BCSR2_USBPWREN	0x20
+#define BCSR2_USBSPD	0x40
+#define BCSR2_USBSUSP	0x80
+
+#define BCSR3_BWKAPWR	0x01   /* Changed by SAM. Backup battery situation */
+#define BCSR3_IRQRTC	0x02   /* Changed by SAM. NVRAM Battery */
+#define BCSR3_RDY_BSY	0x04   /* Changed by SAM. Flash Operation */
+#define BCSR3_MPLX_LIN	0x08   /* Changed by SAM. Linear or Multiplexed address Mode */
+
+#define BCSR3_D27	0x10	  /* Dip Switch settings */
+#define BCSR3_D26	0x20
+#define BCSR3_D25	0x40
+#define BCSR3_D24	0x80
+
+/*
+ * Environment setting
+ */
+#define CONFIG_ETHADDR	00:10:EC:00:37:5B
+#define CONFIG_IPADDR	172.16.115.7
+#define CONFIG_SERVERIP 172.16.115.6
+#define CONFIG_ROOTPATH /workspace/myfilesystem/target/
+#define CONFIG_BOOTFILE uImage.rpxusb
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h
new file mode 100755
index 0000000..6ae9403
--- /dev/null
+++ b/include/configs/RPXsuper.h
@@ -0,0 +1,504 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+/*****************************************************************************
+ *
+ * These settings must match the way _your_ board is set up
+ *
+ *****************************************************************************/
+/* for the AY-Revision which does not use the HRCW */
+#define CFG_DEFAULT_IMMR	0x00010000
+
+/* What is the oscillator's (UX2) frequency in Hz? */
+#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
+
+/* How is switch S2 set? We really only want the MODCK[1-3] bits, so
+ * only the 3 least significant bits are important.
+*/
+#define CFG_SBC_S2  0x04
+
+/* What should MODCK_H be? It is dependent on the oscillator
+ * frequency, MODCK[1-3], and desired CPM and core frequencies.
+ * Some example values (all frequencies are in MHz):
+ *
+ * MODCK_H   MODCK[1-3]  Osc    CPM    Core
+ * 0x2       0x2         33     133    133
+ * 0x2       0x4         33     133    200
+ * 0x5       0x5         66     133    133
+ * 0x5       0x7         66     133    200
+ */
+#define CFG_SBC_MODCK_H 0x06
+
+#define CFG_SBC_BOOT_LOW 1	/* only for HRCW */
+#undef CFG_SBC_BOOT_LOW
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
+ * The main FLASH is whichever is connected to *CS0. U-Boot expects
+ * this to be the SIMM.
+ */
+#define CFG_FLASH0_BASE 0x80000000
+#define CFG_FLASH0_SIZE 16
+
+/* What should the base address of the secondary FLASH be and how big
+ * is it (in Mbytes)? The secondary FLASH is whichever is connected
+ * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
+ * want it enabled, don't define these constants.
+ */
+#define CFG_FLASH1_BASE 0
+#define CFG_FLASH1_SIZE 0
+#undef CFG_FLASH1_BASE
+#undef CFG_FLASH1_SIZE
+
+/* What should be the base address of SDRAM DIMM and how big is
+ * it (in Mbytes)?
+*/
+#define CFG_SDRAM0_BASE 0x00000000
+#define CFG_SDRAM0_SIZE 64
+
+/* What should be the base address of SDRAM DIMM and how big is
+ * it (in Mbytes)?
+*/
+#define CFG_SDRAM1_BASE 0x04000000
+#define CFG_SDRAM1_SIZE 32
+
+/* What should be the base address of the LEDs and switch S0?
+ * If you don't want them enabled, don't define this.
+ */
+#define CFG_LED_BASE 0x00000000
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ */
+#define CONFIG_CONS_ON_SMC          /* define if console on SMC */
+#undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
+#undef  CONFIG_CONS_NONE            /* define if console on neither */
+#define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
+#define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
+#undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
+#define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */
+
+#if ( CONFIG_ETHER_INDEX == 3 )
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK16
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Half Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CFG_CPMFCR_RAMTYPE	0
+/*#define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB) */
+# define CFG_FCC_PSMR		0
+
+#else /* CONFIG_ETHER_INDEX */
+# error "on RPX Super ethernet must be FCC3"
+#endif /* CONFIG_ETHER_INDEX */
+
+#define CONFIG_HARD_I2C         1	/* I2C with hardware support	*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+
+/* Define this to reserve an entire FLASH sector (256 KB) for
+ * environment variables. Otherwise, the environment will be
+ * put in the same sector as U-Boot, and changing variables
+ * will erase U-Boot temporarily
+ */
+#define CFG_ENV_IN_OWN_SECT
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* What should the console's baud rate be? */
+#define CONFIG_BAUDRATE         115200
+
+/* Ethernet MAC address */
+#define CONFIG_ETHADDR          08:00:22:50:70:63
+
+#define CONFIG_IPADDR		192.168.1.99
+#define CONFIG_SERVERIP         192.168.1.3
+
+/* Set to a positive value to delay for running BOOTCOMMAND */
+#define CONFIG_BOOTDELAY        -1
+
+/* undef this to save memory */
+#define CFG_LONGHELP
+
+/* Monitor Command Prompt       */
+#define CFG_PROMPT              "=> "
+
+/* What U-Boot subsytems do you want enabled? */
+#define CONFIG_COMMANDS         ( CONFIG_CMD_DFL | \
+				  CFG_CMD_IMMAP  | \
+				  CFG_CMD_ASKENV | \
+				  CFG_CMD_ECHO   | \
+				  CFG_CMD_I2C    | \
+				  CFG_CMD_REGINFO & \
+				 ~CFG_CMD_KGDB )
+
+/* Where do the internal registers live? */
+#define CFG_IMMR               0xF0000000
+
+/* Where do the on board registers (CS4) live? */
+#define CFG_REGS_BASE          0xFA000000
+
+/*****************************************************************************
+ *
+ * You should not have to modify any of the following settings
+ *
+ *****************************************************************************/
+
+#define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
+#define CONFIG_RPXSUPER         1       /* on an Embedded Planet RPX Super Board  */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CBSIZE              1024       /* Console I/O Buffer Size      */
+#else
+#  define CFG_CBSIZE              256        /* Console I/O Buffer Size      */
+#endif
+
+/* Print Buffer Size */
+#define CFG_PBSIZE        (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+
+#define CFG_MAXARGS       8            /* max number of command args   */
+
+#define CFG_BARGSIZE      CFG_CBSIZE   /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START 0x04000000   /* memtest works on  */
+#define CFG_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CFG_LOAD_ADDR     0x100000     /* default load address */
+#define CFG_HZ            1000         /* decrementer freq: 1 ms ticks */
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_FLASH_BASE    CFG_FLASH0_BASE
+#define CFG_SDRAM_BASE    CFG_SDRAM0_BASE
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+#if defined(CFG_SBC_BOOT_LOW)
+#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#else
+#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CFG_SBC_BOOT_LOW) */
+
+/* get the HRCW ISB field from CFG_IMMR */
+#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
+			    ((CFG_IMMR & 0x01000000) >> 7)  |\
+			    ((CFG_IMMR & 0x00100000) >> 4) )
+
+#define CFG_HRCW_MASTER (HRCW_BPS11                           |\
+			 HRCW_DPPC11                          |\
+			 CFG_SBC_HRCW_IMMR                    |\
+			 HRCW_MMR00                           |\
+			 HRCW_LBPC11                          |\
+			 HRCW_APPC10                          |\
+			 HRCW_CS10PC00                        |\
+			 (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\
+			 CFG_SBC_HRCW_BOOT_FLAGS)
+
+/* no slaves */
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR       CFG_IMMR
+#define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ */
+#define CFG_MONITOR_BASE        (CFG_FLASH0_BASE + 0x00F00000)
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#  define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS   1       /* max number of memory banks         */
+#define CFG_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
+
+#define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
+#define CFG_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
+
+#ifndef CFG_RAMBOOT
+#  define CFG_ENV_IS_IN_FLASH  1
+
+#  ifdef CFG_ENV_IN_OWN_SECT
+#    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
+#    define CFG_ENV_SECT_SIZE  0x40000
+#  else
+#    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
+#    define CFG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
+#    define CFG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
+#  endif /* CFG_ENV_IN_OWN_SECT */
+#else
+#  define CFG_ENV_IS_IN_NVRAM  1
+#  define CFG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
+#  define CFG_ENV_SIZE         0x200
+#endif /* CFG_RAMBOOT */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT     5     /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT   (/*HID0_ICE  |*/\
+			 /*HID0_DCE  |*/\
+			 HID0_ICFI |\
+			 HID0_DCI  |\
+			 HID0_IFEM |\
+			 HID0_ABE)
+
+#define CFG_HID0_FINAL  (/*HID0_ICE  |*/\
+			 HID0_IFEM |\
+			 HID0_ABE  |\
+			 HID0_EMCP)
+#define CFG_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMR         0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR         (BCR_EBM   |\
+			 BCR_PLDP  |\
+			 BCR_EAV   |\
+			 BCR_NPQM0)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+
+#define CFG_SIUMCR      (SIUMCR_L2CPC01 |\
+			 SIUMCR_APPC10  |\
+			 SIUMCR_CS10PC01)
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                            11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#define CFG_SYPCR       (SYPCR_SWTC |\
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWRI |\
+			 SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC     (TMCNTSC_SEC |\
+			 TMCNTSC_ALR |\
+			 TMCNTSC_TCF |\
+			 TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR       (PISCR_PS  |\
+			 PISCR_PTF |\
+			 PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SCCR        (SCCR_DFBRG01)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90)
+ *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60)
+ *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60)
+ *  3   unused
+ *  4   60x     GPCM     8 bit  Board Regs, LEDs, switches
+ *  5   unused
+ *  6   unused
+ *  7   unused
+ *  8   PCMCIA
+ *  9   unused
+ * 10   unused
+ * 11   unused
+*/
+
+/* Bank 0 - FLASH
+ *
+ */
+#define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64                      |\
+			 BRx_DECC_NONE                  |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_6_CLK                 |\
+			 ORxG_EHTR)
+
+/* Bank 1 - SDRAM
+ *
+ */
+#define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A8             |\
+			 ORxS_NUMR_12                   |\
+			 ORxS_IBID)
+
+#define CFG_PSDMR       0x014DA412
+#define CFG_PSRT	0x79
+
+
+/* Bank 2 - SDRAM
+ *
+ */
+#define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
+			 BRx_PS_32                      |\
+			 BRx_MS_SDRAM_L                 |\
+			 BRx_V)
+
+#define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A9             |\
+			 ORxS_NUMR_12)
+
+#define CFG_LSDMR       0x0169A512
+#define CFG_LSRT	0x79
+
+#define CFG_MPTPR	(0x0800 & MPTPR_PTP_MSK)
+
+/* Bank 4 - On board registers
+ *
+ */
+#define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
+			   BRx_PS_8                     |\
+			   BRx_MS_GPCM_P                |\
+			   BRx_V)
+
+#define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\
+			   ORxG_CSNT                   |\
+			   ORxG_ACS_DIV1               |\
+			   ORxG_SCY_5_CLK              |\
+			   ORxG_TRLX)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM   0x02    /* Software reboot                   */
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
new file mode 100755
index 0000000..3885bcd
--- /dev/null
+++ b/include/configs/RRvision.h
@@ -0,0 +1,466 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_RRVISION		1	/* ...on a RRvision board	*/
+
+#define CONFIG_8xx_GCLK_FREQ 64000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"setenv stdout serial"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_ETHADDR                00:50:C2:00:E0:70
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+#define CONFIG_IPADDR                 10.0.0.5
+#define CONFIG_SERVERIP               10.0.0.2
+#define CONFIG_NETMASK                255.0.0.0
+#define CONFIG_ROOTPATH               /opt/eldk/ppc_8xx
+#define CONFIG_BOOTCOMMAND            "run flash_self"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}"	\
+		":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"load=tftp 100000 /tftpboot/u-boot.bin\0"			\
+	"update=protect off 1:0-8;era 1:0-8;"				\
+		"cp.b 100000 40000000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"kernel_addr=40040000\0"					\
+	"ramdisk_addr=40100000\0"					\
+	"kernel_img=/tftpboot/uImage\0"					\
+	"kernel_load=tftp 200000 ${kernel_img}\0"			\
+	"net_nfs=run kernel_load nfsargs addip addtty;bootm\0"		\
+	"flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0"	\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"
+
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#undef	CONFIG_STATUS_LED		/* disturbs display		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+#ifndef CONFIG_LCD
+#define CONFIG_VIDEO		1	/* To enable the video initialization */
+
+/* Video related */
+#define CONFIG_VIDEO_LOGO			1	/* Show the logo */
+#define CONFIG_VIDEO_ENCODER_AD7179		1	/* Enable this encoder */
+#define CONFIG_VIDEO_ENCODER_AD7179_ADDR	0x2A	/* ALSB to ground */
+#endif
+
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C         	/* I2C bit-banged		*/
+
+# define CFG_I2C_SPEED		50000	/* 50 kHz is supposed to work	*/
+# define CFG_I2C_SLAVE		0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(1)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SOFT_I2C */
+
+
+#define CONFIG_COMMANDS	    ( ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_DATE	) & \
+			     ~( CFG_CMD_PCMCIA  | \
+			        CFG_CMD_IDE	) )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+/* timeout values are in ticks = ms */
+#define CFG_FLASH_ERASE_TOUT	(120*CFG_HZ)	/* Timeout for Flash Erase	*/
+#define CFG_FLASH_WRITE_TOUT	(1 * CFG_HZ)	/* Timeout for Flash Write	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+
+/* for 64 MHz, we use a 16 MHz clock * 4 */
+#define CFG_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(/* SCCR_TBS  | */ SCCR_RTSEL | SCCR_RTDIV    | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#define CFG_MAMR_PTA		129
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
new file mode 100755
index 0000000..a170f29
--- /dev/null
+++ b/include/configs/Rattler.h
@@ -0,0 +1,290 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * U-Boot configuration for Analogue&Micro Rattler boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_MPC8248
+#define CPU_ID_STR		"MPC8248"
+#else
+#define CONFIG_MPC8260
+#define CPU_ID_STR		"MPC8250"
+#endif /* CONFIG_MPC8248 */
+
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define CONFIG_RATTLER			/* Analogue&Micro Rattler board */
+
+#undef DEBUG
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
+#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
+#undef	CONFIG_CONS_NONE		/* It's not on external UART */
+#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CFG_CMD_NET must
+ * be removed from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
+#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
+#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
+
+#ifdef CONFIG_ETHER_ON_FCC
+
+#define CONFIG_ETHER_INDEX	1	/* FCC1 is used for Ethernet */
+
+#if   (CONFIG_ETHER_INDEX == 1)
+
+/* - Rx clock is CLK11
+ * - Tx clock is CLK10
+ * - BDs/buffers on 60x bus
+ * - Full duplex
+ */
+#define CFG_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+#define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#elif (CONFIG_ETHER_INDEX == 2)
+
+/* - Rx clock is CLK15
+ * - Tx clock is CLK14
+ * - BDs/buffers on 60x bus
+ * - Full duplex
+ */
+#define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_INDEX */
+
+#define CONFIG_MII			/* MII PHY management        */
+#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT		2	/* Port C */
+#define MDIO_ACTIVE		(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE		(iop->pdir &= ~0x00400000)
+#define MDIO_READ		((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)		if(bit) iop->pdat |=  0x00400000; \
+				else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)		if(bit) iop->pdat |=  0x00800000; \
+				else	iop->pdat &= ~0x00800000
+
+#define MIIDELAY		udelay(1)
+
+#endif /* CONFIG_ETHER_ON_FCC */
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN	100000000	/* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL   \
+				| CFG_CMD_DHCP    \
+				| CFG_CMD_ECHO    \
+				| CFG_CMD_IMMAP   \
+				| CFG_CMD_JFFS2   \
+				| CFG_CMD_MII     \
+				| CFG_CMD_PING    \
+				)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND	"bootm FE040000"	/* autoboot command */
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+
+#define	CFG_DIRECT_FLASH_TFTP
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
+#define CFG_JFFS2_SORT_FRAGMENTS
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00100000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=rattler-0"
+#define MTDPARTS_DEFAULT	"mtdparts=rattler-0:-@1m(jffs2)"
+*/
+#endif /* CFG_CMD_JFFS2 */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+
+#define CFG_ENV_IS_IN_FLASH
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+#define CFG_DEFAULT_IMMR	0xFF010000
+
+#define CFG_IMMR		0xF0000000
+
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_SIZE		32
+#define CFG_SDRAM_BR		(CFG_SDRAM_BASE | 0x00000041)
+#define CFG_SDRAM_OR		0xFE002EC0
+
+#define CFG_BCSR		0xFC000000
+
+/* Hard reset configuration word */
+#define CFG_HRCW_MASTER		0x0A06875A /* Not used - provided by FPGA */
+/* No slaves */
+#define CFG_HRCW_SLAVE1 	0
+#define CFG_HRCW_SLAVE2 	0
+#define CFG_HRCW_SLAVE3 	0
+#define CFG_HRCW_SLAVE4 	0
+#define CFG_HRCW_SLAVE5 	0
+#define CFG_HRCW_SLAVE6 	0
+#define CFG_HRCW_SLAVE7 	0
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot                  */
+
+#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
+
+#define CFG_HID2		0
+
+#define CFG_SIUMCR		0x0E04C000
+#define CFG_SYPCR		0xFFFFFFC3
+#define CFG_BCR			0x00000000
+#define CFG_SCCR		SCCR_DFBRG01
+
+#define CFG_RMR			RMR_CSRE
+#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CFG_RCCR		0
+
+#define CFG_PSDMR		0x8249A452
+#define CFG_PSRT		0x1F
+#define CFG_MPTPR		0x2000
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00001001)
+#define CFG_OR0_PRELIM		0xFF001ED6
+#define CFG_BR7_PRELIM		(CFG_BCSR | 0x00000801)
+#define CFG_OR7_PRELIM		0xFFFF87F6
+
+#define CFG_RESET_ADDRESS	0xC0000000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
new file mode 100755
index 0000000..0451b20
--- /dev/null
+++ b/include/configs/SBC8540.h
@@ -0,0 +1,422 @@
+/*
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+ * Added support for Wind River SBC8540 board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* mpc8560ads board configuration file */
+/* please refer to doc/README.mpc85xx for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if XXX
+#define DEBUG		      /* General debug */
+#define ET_DEBUG
+#endif
+#define TSEC_DEBUG
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE			*/
+#define CONFIG_E500		1	/* BOOKE e500 family		*/
+#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560		*/
+#define CONFIG_MPC85xx_REV1	1	/* MPC85xx Rev 1.0 chip		*/
+
+
+#define CONFIG_CPM2		1	/* has CPM2 */
+
+#define CONFIG_SBC8540      	1   	/* configuration for SBC8560 board */
+
+#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific (supplement)	*/
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
+#undef	CONFIG_PCI			/* pci ethernet support		*/
+#undef  CONFIG_ETHER_ON_FCC		/* cpm FCC ethernet support	*/
+
+
+#define CONFIG_ENV_OVERWRITE
+
+/* Using Localbus SDRAM to emulate flash before we can program the flash,
+ * normally you need a flash-boot image(u-boot.bin), if so undef this.
+ */
+#undef CONFIG_RAM_AS_FLASH
+
+#if defined(CONFIG_PCI_66)			/* some PCI card is 33Mhz only	*/
+  #define CONFIG_SYS_CLK_FREQ	66000000	/* sysclk for MPC85xx		*/
+#else
+  #define CONFIG_SYS_CLK_FREQ	33000000	/* most pci cards are 33Mhz	*/
+#endif
+
+/* below can be toggled for performance analysis. otherwise use default */
+#define CONFIG_L2_CACHE			    /* toggle L2 cache		*/
+#undef	CONFIG_BTB			    /* toggle branch predition	*/
+#undef	CONFIG_ADDR_STREAMING		    /* toggle addr streaming	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
+
+#undef	CFG_DRAM_TEST			    /* memory test, takes time	*/
+#define CFG_MEMTEST_START	0x00200000  /* memtest region */
+#define CFG_MEMTEST_END		0x00400000
+
+#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
+     defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
+     defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
+#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
+#endif
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
+
+#if XXX
+  #define CFG_CCSRBAR		0xfdf00000	/* relocated CCSRBAR	*/
+#else
+  #define CFG_CCSRBAR		0xff700000	/* default CCSRBAR	*/
+#endif
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
+#define SPD_EEPROM_ADDRESS	0x55		/*  DDR DIMM */
+
+#undef  CONFIG_DDR_ECC				/* only for ECC DDR module	*/
+#undef  CONFIG_SPD_EEPROM			/* Use SPD EEPROM for DDR setup */
+
+#if defined(CONFIG_MPC85xx_REV1)
+  #define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#if defined(CONFIG_RAM_AS_FLASH)
+  #define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
+  #define CFG_FLASH_BASE	0xf8000000      /* start of FLASH 8M  */
+  #define CFG_BR0_PRELIM	0xf8000801      /* port size 8bit */
+  #define CFG_OR0_PRELIM	0xf8000ff7	/* 8MB Flash		*/
+#else /* Boot from real Flash */
+  #define CFG_LBC_SDRAM_BASE	0xf8000000	/* Localbus SDRAM */
+  #define CFG_FLASH_BASE	0xff800000      /* start of FLASH 8M    */
+  #define CFG_BR0_PRELIM	0xff800801      /* port size 8bit      */
+  #define CFG_OR0_PRELIM	0xff800ff7	/* 8MB Flash		*/
+#endif
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/
+
+/* local bus definitions */
+#define CFG_BR1_PRELIM		0xe4001801	/* 64M, 32-bit flash */
+#define CFG_OR1_PRELIM		0xfc000ff7
+
+#define CFG_BR2_PRELIM		0x00000000	/* CS2 not used */
+#define CFG_OR2_PRELIM		0x00000000
+
+#define CFG_BR3_PRELIM		0xf0001861	/* 64MB localbus SDRAM	*/
+#define CFG_OR3_PRELIM		0xfc000cc1
+
+#if defined(CONFIG_RAM_AS_FLASH)
+  #define CFG_BR4_PRELIM	0xf4001861	/* 64M localbus SDRAM */
+#else
+  #define CFG_BR4_PRELIM	0xf8001861	/* 64M localbus SDRAM */
+#endif
+#define CFG_OR4_PRELIM		0xfc000cc1
+
+#define CFG_BR5_PRELIM		0xfc000801	/* 16M CS5 misc devices */
+#if 1
+  #define CFG_OR5_PRELIM	0xff000ff7
+#else
+  #define CFG_OR5_PRELIM	0xff0000f0
+#endif
+
+#define CFG_BR6_PRELIM		0xe0001801	/* 64M, 32-bit flash */
+#define CFG_OR6_PRELIM		0xfc000ff7
+#define CFG_LBC_LCRR		0x00030002	/* local bus freq	*/
+#define CFG_LBC_LBCR		0x00000000
+#define CFG_LBC_LSRT		0x20000000
+#define CFG_LBC_MRTPR		0x20000000
+#define CFG_LBC_LSDMR_1		0x2861b723
+#define CFG_LBC_LSDMR_2		0x0861b723
+#define CFG_LBC_LSDMR_3		0x0861b723
+#define CFG_LBC_LSDMR_4		0x1861b723
+#define CFG_LBC_LSDMR_5		0x4061b723
+
+/* just hijack the MOT BCSR def for SBC8560 misc devices */
+#define CFG_BCSR		((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
+/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#undef  CONFIG_CONS_ON_SCC			/* define if console on SCC */
+#undef	CONFIG_CONS_NONE			/* define if console on something else */
+
+#define CONFIG_CONS_INDEX     1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#if 0
+#define CFG_NS16550_CLK		1843200 /* get_bus_freq(0) */
+#else
+#define CFG_NS16550_CLK		264000000 /* get_bus_freq(0) */
+#endif
+
+#define CONFIG_BAUDRATE		9600
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#if 0
+#define CFG_NS16550_COM1	((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
+#define CFG_NS16550_COM2	((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
+#else
+/* SBC8540 uses internal COMM controller */
+#define CFG_NS16550_COM1	((CFG_CCSRBAR & 0xfff00000)+0x00004500)
+#define CFG_NS16550_COM2	((CFG_CCSRBAR & 0xfff00000)+0x00004600)
+#endif
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+
+#define CFG_PCI_MEM_BASE	0xC0000000
+#define CFG_PCI_MEM_PHYS	0xC0000000
+#define CFG_PCI_MEM_SIZE	0x10000000
+
+#if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */
+
+#  define CONFIG_NET_MULTI	1
+#  define CONFIG_MPC85xx_TSEC1
+#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
+#  define CONFIG_MII		1	/* MII PHY management		*/
+#  define TSEC1_PHY_ADDR	25
+#  define TSEC1_PHYIDX		0
+/* Options are: TSEC0 */
+#  define CONFIG_ETHPRIME		"TSEC0"
+
+
+#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
+
+  #undef  CONFIG_ETHER_NONE		/* define if ether on something else */
+  #define CONFIG_ETHER_ON_FCC2		/* cpm FCC ethernet support	*/
+  #define CONFIG_ETHER_INDEX	2	/* which channel for ether  */
+
+  #if (CONFIG_ETHER_INDEX == 2)
+    /*
+     * - Rx-CLK is CLK13
+     * - Tx-CLK is CLK14
+     * - Select bus for bd/buffers
+     * - Full duplex
+     */
+    #define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+    #define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+    #define CFG_CPMFCR_RAMTYPE	0
+    #define CFG_FCC_PSMR	(FCC_PSMR_FDE)
+
+  #elif (CONFIG_ETHER_INDEX == 3)
+    /* need more definitions here for FE3 */
+  #endif				/* CONFIG_ETHER_INDEX */
+
+  #define CONFIG_MII			/* MII PHY management */
+  #define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+  /*
+   * GPIO pins used for bit-banged MII communications
+   */
+  #define MDIO_PORT	2		/* Port C */
+  #define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
+  #define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
+  #define MDIO_READ	((iop->pdat &  0x00400000) != 0)
+
+  #define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
+			else	iop->pdat &= ~0x00400000
+
+  #define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
+			else	iop->pdat &= ~0x00200000
+
+  #define MIIDELAY	udelay(1)
+
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
+#if 0
+#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
+#define CFG_FLASH_PROTECTION		/* use hardware protection		*/
+#endif
+#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	200000		/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	50000		/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
+
+#if 0
+/* XXX This doesn't work and I don't want to fix it */
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+  #define CFG_RAMBOOT
+#else
+  #undef  CFG_RAMBOOT
+#endif
+#endif
+
+/* Environment */
+#if !defined(CFG_RAMBOOT)
+  #if defined(CONFIG_RAM_AS_FLASH)
+    #define CFG_ENV_IS_NOWHERE
+    #define CFG_ENV_ADDR	(CFG_FLASH_BASE + 0x100000)
+    #define CFG_ENV_SIZE	0x2000
+  #else
+    #define CFG_ENV_IS_IN_FLASH	1
+    #define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
+    #define CFG_ENV_ADDR	(CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
+    #define CFG_ENV_SIZE	0x2000 /* CFG_ENV_SECT_SIZE */
+  #endif
+#else
+  #define CFG_NO_FLASH		1	/* Flash is not usable now	*/
+  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
+/*#define CONFIG_BOOTARGS      "root=/dev/ram rw console=ttyS0,115200"*/
+#define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xffa00000"
+#define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PCI | \
+				CFG_CMD_PING | CFG_CMD_I2C) & \
+				 ~(CFG_CMD_ENV | \
+				  CFG_CMD_LOADS ))
+  #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_MII | \
+				CFG_CMD_PING | CFG_CMD_I2C) & \
+				~(CFG_CMD_ENV))
+  #endif
+#else
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI | \
+				CFG_CMD_PING | CFG_CMD_I2C)
+  #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_MII | \
+				CFG_CMD_PING | CFG_CMD_I2C)
+  #endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"SBC8540=> " /* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+  #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+  #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x1000000	/* default load address */
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+  #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+  #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+  #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*Note: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#  define CONFIG_ETHADDR	00:vv:ww:xx:yy:8a
+#  define CONFIG_HAS_ETH1
+#  define CONFIG_ETH1ADDR	00:vv:ww:xx:yy:8b
+#  define CONFIG_HAS_ETH2
+#  define CONFIG_ETH2ADDR	00:vv:ww:xx:yy:8c
+#endif
+
+#define CONFIG_SERVERIP		YourServerIP
+#define CONFIG_IPADDR		YourTargetIP
+#define CONFIG_GATEWAYIP	YourGatewayIP
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_HOSTNAME		SBC8560
+#define CONFIG_ROOTPATH		YourRootPath
+#define CONFIG_BOOTFILE		YourImageName
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/SCM.h b/include/configs/SCM.h
new file mode 100755
index 0000000..e263db6
--- /dev/null
+++ b/include/configs/SCM.h
@@ -0,0 +1,711 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
+#define CONFIG_TQM8260		200	/* ...on a TQM8260 module Rev.200	*/
+#define CONFIG_SCM              1	/* ...on a System Controller Module	*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#if (CONFIG_TQM8260 <= 100)
+#  error "TQM8260 module revison not supported"
+#endif
+
+/* We use a TQM8260 module with a 300MHz CPU */
+#define CONFIG_300MHz
+
+/* Define 60x busmode only if your TQM8260 has L2 cache! */
+#ifdef CONFIG_L2_CACHE
+#  define CONFIG_BUSMODE_60x	1	/* bus mode: 60x			*/
+#else
+#  undef  CONFIG_BUSMODE_60x		/* bus mode: 8260			*/
+#endif
+
+/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */
+#ifdef CONFIG_300MHz
+#  define CONFIG_BUSMODE_60x
+#endif
+
+#define CONFIG_82xx_CONS_SMC1	1	/* console on SMC1			*/
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CFG_I2C_EEPROM_ADDR	0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CONFIG_I2C_X
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else*/
+#ifdef CONFIG_82xx_CONS_SMC1
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+#endif
+#ifdef CONFIG_82xx_CONS_SMC2
+#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
+#endif
+
+#undef  CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
+#define CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
+#define CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9 */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ *
+ * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
+ * X.29 connector, and FCC2 is hardwired to the X.1 connector)
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define	CONFIG_ETHER_INDEX    1		/* which SCC/FCC channel for ethernet */
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
+
+/*
+ * - Rx-CLK is CLK12
+ * - Tx-CLK is CLK11
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK16
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CFG_CMXFCR_VALUE 	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#ifndef CONFIG_300MHz
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+#else
+#define CONFIG_8260_CLKIN	83333000	/* in Hz */
+#endif
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		115200
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_EEPROM	| \
+				 CFG_CMD_BSP)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START 0x0400000	/* memtest works on		*/
+#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM		*/
+
+#define	CFG_LOAD_ADDR	0x100000	/* default load address		*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CFG_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/
+
+#define CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
+ * The main FLASH is whichever is connected to *CS0.
+ */
+#define CFG_FLASH0_BASE 0x40000000
+#define CFG_FLASH1_BASE 0x60000000
+#define CFG_FLASH0_SIZE 32
+#define CFG_FLASH1_SIZE 32
+
+/* Flash bank size (for preliminary settings)
+ */
+#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#if 0
+/* Start port with environment in flash; switch to EEPROM later */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
+#define CFG_ENV_SIZE		0x40000
+#define CFG_ENV_SECT_SIZE	0x40000
+#else
+/* Final version: environment in EEPROM */
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_ENV_OFFSET		0
+#define CFG_ENV_SIZE		2048
+#endif
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#if defined(CONFIG_266MHz)
+#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
+							      HRCW_MODCK_H0111)
+#elif defined(CONFIG_300MHz)
+#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
+							      HRCW_MODCK_H0110)
+#else
+#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
+#endif
+
+/* no slaves so just fill with zeros */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
+ * is mapped at SDRAM_BASE2_PRELIM.
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		CFG_FLASH0_BASE
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
+
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CFG_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR         RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#ifdef	CONFIG_BUSMODE_60x
+#define CFG_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
+			 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2)	/* 60x mode  */
+#else
+#define BCR_APD01	0x10000000
+#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#if 0
+#define CFG_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
+#else
+#define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR        0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    64 bit  FLASH
+ *  1   60x     SDRAM   64 bit  SDRAM
+ *  2   Local   SDRAM   32 bit  SDRAM
+ *
+ */
+
+	/* Initialize SDRAM on local bus
+	 */
+#define CFG_INIT_LOCAL_SDRAM
+
+#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+
+/* Minimum mask to separate preliminary
+ * address ranges for CS[0:2]
+ */
+#define CFG_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
+#define CFG_LOCAL_SDRAM_LIMIT	(128<<20)	/* less than 128 MB */
+
+#define CFG_MPTPR       0x4000
+
+/*-----------------------------------------------------------------------------
+ * Address for Mode Register Set (MRS) command
+ *-----------------------------------------------------------------------------
+ * In fact, the address is rather configuration data presented to the SDRAM on
+ * its address lines. Because the address lines may be mux'ed externally either
+ * for 8 column or 9 column devices, some bits appear twice in the 8260's
+ * address:
+ *
+ * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
+ * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
+ *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
+ *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
+ *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
+ *-----------------------------------------------------------------------------
+ */
+#define CFG_MRS_OFFS	0x00000110
+
+
+/* Bank 0 - FLASH
+ */
+#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxG_EHTR                      |\
+			 ORxG_TRLX)
+
+	/* SDRAM on TQM8260 can have either 8 or 9 columns.
+	 * The number affects configuration values.
+	 */
+
+/* Bank 1 - 60x bus SDRAM
+ */
+#define CFG_PSRT        0x20
+#define CFG_LSRT        0x20
+#ifndef CFG_RAMBOOT
+#define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CFG_OR1_PRELIM	CFG_OR1_8COL
+
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A7             |\
+			 ORxS_NUMR_12)
+
+#define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A15_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A8            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A5             |\
+			 ORxS_NUMR_13)
+
+#define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A16_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A7            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_CL_2)
+
+/* Bank 2 - Local bus SDRAM
+ */
+#ifdef CFG_INIT_LOCAL_SDRAM
+#define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
+			 BRx_PS_32                      |\
+			 BRx_MS_SDRAM_L                 |\
+			 BRx_V)
+
+#define CFG_OR2_PRELIM	CFG_OR2_8COL
+
+#define SDRAM_BASE2_PRELIM	0x80000000
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CFG_OR2_8COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A8             |\
+			 ORxS_NUMR_12)
+
+#define CFG_LSDMR_8COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A15_IS_A5           |\
+			 PSDMR_BSMA_A13_A15             |\
+			 PSDMR_SDA10_PBI1_A9            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CFG_OR2_9COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A6             |\
+			 ORxS_NUMR_13)
+
+#define CFG_LSDMR_9COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A16_IS_A5           |\
+			 PSDMR_BSMA_A13_A15             |\
+			 PSDMR_SDA10_PBI1_A8            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_CL_2)
+
+#endif /* CFG_INIT_LOCAL_SDRAM */
+
+#endif /* CFG_RAMBOOT */
+
+#define CFG_CAN0_BASE		0xc0000000
+#define CFG_CAN1_BASE		0xc0008000
+#define CFG_FIOX_BASE		0xc0010000
+#define CFG_FDOHM_BASE		0xc0018000
+#define CFG_EXTPROM_BASE	0xc2000000
+
+#define CFG_CAN_SIZE		0x00000100
+#define CFG_FIOX_SIZE		0x00000020
+#define CFG_FDOHM_SIZE		0x00002000
+#define CFG_EXTPROM_BANK_SIZE	0x01000000
+
+#define EXT_EEPROM_MAX_FLASH_BANKS	0x02
+
+/* CS3 - CAN 0
+ */
+#define CFG_CAN0_BR3   ((CFG_CAN0_BASE & BRx_BA_MSK)	|\
+			BRx_PS_8			|\
+			BRx_MS_UPMA			|\
+			BRx_V)
+
+#define CFG_CAN0_OR3   (P2SZ_TO_AM(CFG_CAN_SIZE)	|\
+			ORxU_BI				|\
+			ORxU_EHTR_4IDLE)
+
+/* CS4 - CAN 1
+ */
+#define CFG_CAN1_BR4   ((CFG_CAN1_BASE & BRx_BA_MSK)	|\
+			BRx_PS_8			|\
+			BRx_MS_UPMA			|\
+			BRx_V)
+
+#define CFG_CAN1_OR4   (P2SZ_TO_AM(CFG_CAN_SIZE)	|\
+			ORxU_BI				|\
+			ORxU_EHTR_4IDLE)
+
+/* CS5 - Extended PROM (16MB optional)
+ */
+#define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\
+			BRx_PS_32			|\
+			BRx_MS_GPCM_P			|\
+			BRx_V)
+
+#define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
+			ORxG_CSNT			|\
+			ORxG_ACS_DIV4			|\
+			ORxG_SCY_5_CLK			|\
+			ORxG_TRLX)
+
+/* CS6 - Extended PROM (16MB optional)
+ */
+#define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \
+			CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
+			BRx_PS_32			|\
+			BRx_MS_GPCM_P			|\
+			BRx_V)
+
+#define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
+			ORxG_CSNT			|\
+			ORxG_ACS_DIV4			|\
+			ORxG_SCY_5_CLK			|\
+			ORxG_TRLX)
+
+/* CS7 - FPGA FIOX: Glue Logic
+ */
+#define CFG_FIOX_BR7   ((CFG_FIOX_BASE & BRx_BA_MSK)	|\
+			BRx_PS_32			|\
+			BRx_MS_GPCM_P			|\
+			BRx_V)
+
+#define CFG_FIOX_OR7   (P2SZ_TO_AM(CFG_FIOX_SIZE)	|\
+			ORxG_ACS_DIV4			|\
+			ORxG_SCY_5_CLK			|\
+			ORxG_TRLX)
+
+/* CS8 - FPGA DOH Master
+ */
+#define CFG_FDOHM_BR8  ((CFG_FDOHM_BASE & BRx_BA_MSK)	|\
+			BRx_PS_16			|\
+			BRx_MS_GPCM_P			|\
+			BRx_V)
+
+#define CFG_FDOHM_OR8  (P2SZ_TO_AM(CFG_FDOHM_SIZE)	|\
+			ORxG_ACS_DIV4			|\
+			ORxG_SCY_5_CLK			|\
+			ORxG_TRLX)
+
+
+/* FPGA configuration */
+#define CFG_PD_FIOX_PROG	(1 << (31- 5))	/* PD  5 */
+#define CFG_PD_FIOX_DONE	(1 << (31-28))	/* PD 28 */
+#define CFG_PD_FIOX_INIT	(1 << (31-29))	/* PD 29 */
+
+#define CFG_PD_FDOHM_PROG	(1 << (31- 4))	/* PD  4 */
+#define CFG_PD_FDOHM_DONE	(1 << (31-26))	/* PD 26 */
+#define CFG_PD_FDOHM_INIT	(1 << (31-27))	/* PD 27 */
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/SL8245.h b/include/configs/SL8245.h
new file mode 100755
index 0000000..61896d0
--- /dev/null
+++ b/include/configs/SL8245.h
@@ -0,0 +1,283 @@
+/*
+ * (C) Copyright 2001 - 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Configuration settings for the SL8245 board.
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8245		1
+#define CONFIG_SL8245		1
+
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_BOOTDELAY	5
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_PCI)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) 	*/
+
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+/* Print Buffer Size
+ */
+#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS	32		/* Max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x00400000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE	    	0x00000000
+
+#define CFG_FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank on RCS#0 */
+#define CFG_FLASH_BASE 		CFG_FLASH_BASE0_PRELIM
+#define CFG_FLASH_BANKS		{ CFG_FLASH_BASE0_PRELIM }
+
+#define CFG_RESET_ADDRESS   0xFFF00100
+
+#define CFG_EUMB_ADDR	    0xFC000000
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+
+#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+	/* Maximum amount of RAM.
+	 */
+#define CFG_MAX_RAM_SIZE    0x10000000	/* 0 .. 256 MB of (S)DRAM */
+
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	1
+
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+#define CFG_GBL_DATA_SIZE      128
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x1000
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  66666666	/* external frequency to pll */
+#define CFG_HZ		     1000
+
+	/* Bit-field values for MCCR1.
+	 */
+#define CFG_ROMNAL	    0
+#define CFG_ROMFAL	    7
+#define CFG_BANK0_ROW       2
+
+	/* Bit-field values for MCCR2.
+	 */
+#define CFG_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
+
+	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+	 */
+#define CFG_BSTOPRE	    192
+
+	/* Bit-field values for MCCR3.
+	 */
+#define CFG_REFREC	    2	    /* Refresh to activate interval */
+
+	/* Bit-field values for MCCR4.
+	 */
+#define CFG_PRETOACT	    2	    /* Precharge to activate interval */
+#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval */
+#define CFG_ACTORW	    3       /* FIXME was 2 */
+#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
+#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
+#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CFG_EXTROM	    1
+#define CFG_REGDIMM	    0
+
+#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+					/* see 8245 book for bit definitions	*/
+#define CFG_PGMAX		0x32	/* how long the 8245 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8245 book for details		*/
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CFG_BANK0_START	    0x00000000
+#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE    1
+#define CFG_BANK1_START	    0x3ff00000
+#define CFG_BANK1_END	    0x3fffffff
+#define CFG_BANK1_ENABLE    0
+#define CFG_BANK2_START	    0x3ff00000
+#define CFG_BANK2_END	    0x3fffffff
+#define CFG_BANK2_ENABLE    0
+#define CFG_BANK3_START	    0x3ff00000
+#define CFG_BANK3_END	    0x3fffffff
+#define CFG_BANK3_ENABLE    0
+#define CFG_BANK4_START	    0x3ff00000
+#define CFG_BANK4_END	    0x3fffffff
+#define CFG_BANK4_ENABLE    0
+#define CFG_BANK5_START	    0x3ff00000
+#define CFG_BANK5_END	    0x3fffffff
+#define CFG_BANK5_ENABLE    0
+#define CFG_BANK6_START	    0x3ff00000
+#define CFG_BANK6_END	    0x3fffffff
+#define CFG_BANK6_ENABLE    0
+#define CFG_BANK7_START	    0x3ff00000
+#define CFG_BANK7_END	    0x3fffffff
+#define CFG_BANK7_ENABLE    0
+
+#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L  CFG_IBAT0L
+#define CFG_DBAT0U  CFG_IBAT0U
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+#define CFG_DBAT2L  CFG_IBAT2L
+#define CFG_DBAT2U  CFG_IBAT2U
+#define CFG_DBAT3L  CFG_IBAT3L
+#define CFG_DBAT3U  CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CFG_MAX_FLASH_SECT	35	/* Max number of sectors per flash	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+
+	/* Warining: environment is not EMBEDDED in the U-Boot code.
+	 * It's stored in flash separately.
+	 */
+#define CFG_ENV_IS_IN_FLASH	    1
+#define CFG_ENV_ADDR		0xFFFF0000
+#define CFG_ENV_SIZE		0x00010000 /* Size of the Environment		*/
+#define CFG_ENV_SECT_SIZE	0x00010000 /* Size of the Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#undef  CONFIG_PCI_SCAN_SHOW
+
+
+#define CONFIG_SK98
+#define CONFIG_NET_MULTI
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/SM850.h b/include/configs/SM850.h
new file mode 100755
index 0000000..4977629
--- /dev/null
+++ b/include/configs/SM850.h
@@ -0,0 +1,363 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef TQM8xxL_80MHz	/*	1	/ * define for 80 MHz CPU only	*/
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_SM850		1	/*...on a MPC850 Service Module	*/
+
+#undef	CONFIG_8xx_CONS_SMC1	/* SMC1 not usable because Ethernet on SCC3 */
+#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#undef	CONFIG_STATUS_LED		/* Status LED not enabled	*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL	| \
+				  CFG_CMD_DHCP		| \
+				  CFG_CMD_DATE		)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && defined(KGDB_DEBUG)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#ifdef TQM8xxL_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_PLPRCR							\
+		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif	/* TQM8xxL_80MHz */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#ifdef TQM8xxL_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_SCCR	(/* SCCR_TBS  | */ \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#else			/* up to 50 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif	/* TQM8xxL_80MHz */
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+				 OR_SCY_5_CLK | OR_EHTR)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h
new file mode 100755
index 0000000..ae4dcc2
--- /dev/null
+++ b/include/configs/SPD823TS.h
@@ -0,0 +1,411 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_SPD823TS		1	/* ...on a SPD823TS board	*/
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
+
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
+				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
+				"nfsaddrs=10.0.0.99:10.0.0.2"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_COMMANDS \
+((CONFIG_CMD_DFL & ~(CFG_CMD_FLASH)) | CFG_CMD_IDE) /* no Flash, but IDE */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*----------------------------------------------------------------------*/
+#define CONFIG_ETHADDR		00:D0:93:00:01:CB
+#define CONFIG_IPADDR		10.0.0.98
+#define CONFIG_SERVERIP		10.0.0.1
+#undef	CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND	"tftp 200000 uImage;bootm 200000"
+/*----------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x00100000	/* default load address */
+
+#define CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+#define CFG_PC_IDE_RESET	((ushort)0x0008)	/* PC 12	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000 /* was: 0xFF000000 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFF000000
+#ifdef	DEBUG
+#define CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#else
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	0	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	0	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	0	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	0	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define CFG_ENV_SIZE		0x0800	/* Total Size of Environment Sector	*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+/* 0x00000040 */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* 0x00b0c0c0 */
+#define CFG_PLPRCR							\
+		(	(11 << PLPRCR_MF_SHIFT) |			\
+			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
+			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
+			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
+		)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* 0x01800014 */
+#define CFG_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
+			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
+			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
+			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
+			 SCCR_DFNH000	|   SCCR_DFLCD101 |	\
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register
+ *-----------------------------------------------------------------------
+ */
+/* 0x00C3 */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register
+ *-----------------------------------------------------------------------
+ */
+/* TIMEP=2 */
+#define CFG_RCCR 0x0200
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMDS 0
+
+/*-----------------------------------------------------------------------
+ * SDSR - SDMA Status Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SDSR ((u_char)0x83)
+
+/*-----------------------------------------------------------------------
+ * SDMR - SDMA Mask Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SDMR ((u_char)0x00)
+
+/*-----------------------------------------------------------------------
+ *
+ * Interrupt Levels
+ *-----------------------------------------------------------------------
+ */
+#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/
+#define CONFIG_IDE_LED		1	/* LED   for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CFG_IDE_MAXBUS		2	/* max. 2 IDE busses		*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR	0xFE100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_IDE1_OFFSET	0x0C00
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CFG_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFF080000	/* FLASH bank #1	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+/* EPROMs are 512kb */
+#define CFG_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	(/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
+				 OR_SCY_5_CLK | OR_EHTR)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+/* 16 bit, bank valid */
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+/* 16 bit, bank valid */
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/*
+ * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC)
+ *
+ */
+#define SRAM_BASE	0xFE200000	/* SRAM bank */
+#define SRAM_OR_AM	0xFFE00000	/* SRAM is 2 MB */
+
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
+
+#define PER8_BASE	0xFE000000	/* PER8 bank */
+#define PER8_OR_AM	0xFFF00000	/* PER8 is 1 MB */
+
+#define SHARC_BASE	0xFE400000	/* SHARC bank */
+#define SHARC_OR_AM	0xFFC00000	/* SHARC is 4 MB */
+
+/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+
+#define CFG_OR_TIMING_SRAM	0x00000D42	/* SRAM-Timing */
+#define CFG_OR2 (SRAM_OR_AM | CFG_OR_TIMING_SRAM )
+#define CFG_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+
+#define CFG_OR_TIMING_SDRAM	0x00000A00	/* SDRAM-Timing */
+#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
+
+#define CFG_OR_TIMING_PER8	0x00000F32	/* PER8-Timing */
+#define CFG_OR4 (PER8_OR_AM | CFG_OR_TIMING_PER8 )
+#define CFG_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+#define CFG_OR_TIMING_SHARC	0x00000700	/* SHARC-Timing */
+#define CFG_OR5 (SHARC_OR_AM | CFG_OR_TIMING_SHARC )
+#define CFG_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MBMR_PTB	204
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MBMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MBMR_8COL	((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/SX1.h b/include/configs/SX1.h
new file mode 100755
index 0000000..6ed98b8
--- /dev/null
+++ b/include/configs/SX1.h
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM925T	1		/* This is an arm925t CPU	*/
+#define CONFIG_OMAP	1		/* in a TI OMAP core	*/
+#define CONFIG_OMAP1510 1		/* which is in a 1510 (helen) */
+#define CONFIG_OMAP_SX1 1		/*	a SX1 Board  */
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ	12000000	/* the SX1 has 12MHz input clock */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	(-4)
+#define CFG_NS16550_CLK		(CONFIG_SYS_CLK_FREQ)	/* can be 12M/32Khz or 48Mhz  */
+#define CFG_NS16550_COM1	0xfffb0000		/* uart1, bluetooth uart on helen */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		1	/* we use SERIAL 1 on SX1 */
+
+/*
+ * USB device configuration
+ */
+#define CONFIG_USB_DEVICE	1
+#define CONFIG_USB_TTY		1
+
+#define CONFIG_USBD_VENDORID		0x1234
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Siemens"
+#define CONFIG_USBD_PRODUCT_NAME	"SX1"
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C
+#define CFG_I2C_SPEED		100000
+#define CFG_I2C_SLAVE		1
+#define CONFIG_DRIVER_OMAP1510_I2C
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_COMMANDS		(( CONFIG_CMD_DFL | \
+				   CFG_CMD_I2C ) & \
+				  ~CFG_CMD_NET)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#include <configs/omap1510.h>
+
+#define CONFIG_BOOTARGS		"mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw"
+#define CONFIG_PREBOOT		"setenv stdout usbtty;setenv stdin usbtty"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT		"SX1# " /* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x10000000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x12000000	/* 32 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0x10000000	/* default load address */
+
+/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
+ * This time is further subdivided by a local divisor.
+ */
+#define CFG_TIMERBASE	0xFFFEC500	    /* use timer 1 */
+#define CFG_PVT		7		    /* 2^(pvt+1), divide by 256 */
+#define CFG_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x10000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define PHYS_FLASH_SIZE		(16 << 10) /* 16 MB */
+#define PHYS_FLASH_SECT_SIZE	(128*1024) /* Size of a sector (128kB) */
+#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + PHYS_FLASH_SECT_SIZE) /* addr of environment */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE	/* Monitor at beginning of flash */
+#define CFG_MONITOR_LEN		PHYS_FLASH_SECT_SIZE	/* Reserve 1 sector */
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE }
+
+/*-----------------------------------------------------------------------
+ * FLASH driver setup
+ */
+#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION	1	/* Use hardware sector protection */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_SIZE		CFG_ENV_SECT_SIZE /* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET	( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_SIZE_REDUND	0x20000
+#define CFG_ENV_OFFSET_REDUND	0x40000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h
new file mode 100755
index 0000000..c1c765f
--- /dev/null
+++ b/include/configs/SXNI855T.h
@@ -0,0 +1,460 @@
+/*
+ * U-Boot configuration for SIXNET SXNI855T CPU board.
+ * This board is based (loosely) on the Motorola FADS board, so this
+ * file is based (loosely) on config_FADS860T.h, see it for additional
+ * credits.
+ *
+ * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * Memory map:
+ *
+ *   ff100000 -> ff13ffff : FPGA        CS1
+ *   ff030000 -> ff03ffff : EXPANSION   CS7
+ *   ff020000 -> ff02ffff : DATA FLASH  CS4
+ *   ff018000 -> ff01ffff : UART B      CS6/UPMB
+ *   ff010000 -> ff017fff : UART A      CS5/UPMB
+ *   ff000000 -> ff00ffff : IMAP                   internal to the MPC855T
+ *   f8000000 -> fbffffff : FLASH       CS0        up to 64MB
+ *   f4000000 -> f7ffffff : NVSRAM      CS2        up to 64MB
+ *   00000000 -> 0fffffff : SDRAM       CS3/UPMA   up to 256MB
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#include <mpc8xx_irq.h>
+
+#define CONFIG_SXNI855T		1	/* SIXNET IPm 855T CPU module */
+
+/* The 855T is just a stripped 860T and needs code for 860, so for now
+ * at least define 860, 860T and 855T
+ */
+#define CONFIG_MPC860		1
+#define CONFIG_MPC860T		1
+#define CONFIG_MPC855T		1
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_SCC1
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+
+#define MPC8XX_FACT		10	/* 50 MHz is 5 MHz in times 10	*/
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_HAS_ETH1
+
+/*-----------------------------------------------------------------------
+ * Definitions for status LED
+ */
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+# define STATUS_LED_PAR		im_ioport.iop_papar
+# define STATUS_LED_DIR		im_ioport.iop_padir
+# define STATUS_LED_ODR		im_ioport.iop_paodr
+# define STATUS_LED_DAT		im_ioport.iop_padat
+
+# define STATUS_LED_BIT		0x8000		/* LED 0 is on PA.0 */
+# define STATUS_LED_PERIOD	((CFG_HZ / 2) / 5)	/* blink at 5 Hz */
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+#ifdef DEV	/* development (debug) settings */
+#define CONFIG_BOOT_LED_STATE	STATUS_LED_OFF
+#else		/* production settings */
+#define CONFIG_BOOT_LED_STATE	STATUS_LED_ON
+#endif
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define CONFIG_BOOTCOMMAND	"bootm f8040000 f8100000" /* autoboot command */
+#define CONFIG_BOOTARGS		"root=/dev/ram ip=off"
+
+#define CONFIG_MISC_INIT_R		/* have misc_init_r() function */
+#define CONFIG_BOARD_POSTCLK_INIT	/* have board_postclk_init() function */
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_RTC_DS1306		/* Dallas 1306 real time clock	*/
+
+#define	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+# define CFG_I2C_SPEED		50000
+# define CFG_I2C_SLAVE		0xFE
+# define CFG_I2C_EEPROM_ADDR	0x50	/* Atmel 24C64			*/
+# define CFG_I2C_EEPROM_ADDR_LEN 2	/* two byte address		*/
+
+#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
+#define	CONFIG_MII		1
+
+#define CFG_DISCOVER_PHY
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL		| \
+				 CFG_CMD_EEPROM		| \
+				 CFG_CMD_JFFS2		| \
+				 CFG_CMD_NAND		| \
+				 CFG_CMD_DATE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_JFFS2_SORT_FRAGMENTS
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+
+/*
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0x00780000
+#define CONFIG_JFFS2_PART_OFFSET	0x00080000
+*/
+
+#define CONFIG_JFFS2_DEV		"nand0"
+#define CONFIG_JFFS2_PART_SIZE		0x00200000
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=sixnet-0,nand0=sixnet-nand"
+#define MTDPARTS_DEFAULT	"mtdparts=sixnet-0:7680k@512k();sixnet-nand:2m(jffs2-nand)"
+*/
+
+/* NAND flash support */
+#define CONFIG_MTD_NAND_ECC_JFFS2
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices	*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+/* DFBUSY is available on Port C, bit 12; 0 if busy */
+#define NAND_WAIT_READY(nand)	\
+	while (!(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x0008));
+#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr))
+#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr))
+#define WRITE_NAND(d, adr)	\
+	 do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0)
+#define READ_NAND(adr) (*(volatile uint8_t *)(adr))
+#define	CLE_LO	0x01	/* 0 selects CLE mode (CLE high) */
+#define	ALE_LO	0x02	/* 0 selects ALE mode (ALE high) */
+#define	CE_LO	0x04	/* 1 selects chip (CE low) */
+#define	nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0)
+#define NAND_DISABLE_CE(nand) \
+	nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO)
+#define NAND_ENABLE_CE(nand) \
+	nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO)
+#define NAND_CTL_CLRALE(nandptr) \
+	nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
+#define NAND_CTL_SETALE(nandptr) \
+	nand_setcr((nandptr) + 1, CE_LO | CLE_LO)
+#define NAND_CTL_CLRCLE(nandptr) \
+	nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
+#define NAND_CTL_SETCLE(nandptr) \
+	nand_setcr((nandptr) + 1, CE_LO | ALE_LO)
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save a little memory */
+#define	CFG_PROMPT		"=>"	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR	 	0x00100000
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+#define CFG_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define	CFG_SRAM_BASE		0xF4000000
+#define	CFG_SRAM_SIZE		0x04000000	/* autosize up to 64Mbyte */
+
+#define CFG_FLASH_BASE		0xF8000000
+#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+
+#define CFG_DFLASH_BASE		0xff020000 /* DiskOnChip or NAND FLASH */
+#define CFG_DFLASH_SIZE		0x00010000
+
+#define CFG_FPGA_BASE		0xFF100000	/* Xilinx FPGA */
+#define CFG_FPGA_PROG		0xFF130000	/* Programming address */
+#define CFG_FPGA_SIZE		0x00040000	/* 256KiB usable */
+
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
+ * AMD 29LV641 has 128 64K sectors in 8MB
+ */
+#define CFG_MAX_FLASH_SECT	135	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration					11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control (15-29)
+ */
+#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+
+ /*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER		0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+ * entire address space, we have to set the memory controller
+ * differently.  Normally, you write the option register
+ * first, and then enable the chip select by writing the
+ * base register.  For CS0, you must write the base register
+ * first, followed by the option register.
+ */
+
+/*
+ * Init Memory Controller:
+ *
+ **********************************************************
+ * BR0 and OR0 (FLASH)
+ */
+
+#define CFG_PRELIM_OR0_AM	0xFC000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR0_AM | CFG_OR_TIMING_FLASH)
+
+#define CONFIG_FLASH_16BIT
+#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CFG_FLASH_PROTECTION	/* need to lock/unlock sectors in hardware */
+
+/**********************************************************
+ * BR1 and OR1 (FPGA)
+ * These preliminary values are also the final values.
+ */
+#define CFG_OR_TIMING_FPGA \
+	(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX)
+#define CFG_BR1_PRELIM	((CFG_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CFG_OR1_PRELIM	(((-CFG_FPGA_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_FPGA)
+
+/**********************************************************
+ * BR4 and OR4 (data flash)
+ * These preliminary values are also the final values.
+ */
+#define CFG_OR_TIMING_DFLASH \
+	(OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX)
+#define CFG_BR4_PRELIM	((CFG_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CFG_OR4_PRELIM	(((-CFG_DFLASH_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_DFLASH)
+
+/**********************************************************
+ * BR5/6 and OR5/6 (Dual UART)
+ */
+#define CFG_DUART_SIZE	0x8000	/* 32K window, only uses 8 bytes */
+#define CFG_DUARTA_BASE	0xff010000
+#define CFG_DUARTB_BASE	0xff018000
+
+#define DUART_MBMR	0
+#define DUART_OR_VALUE (ORMASK(CFG_DUART_SIZE) | OR_G5LS| OR_BI)
+#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)
+#define DUART_BR5_VALUE ((CFG_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
+#define DUART_BR6_VALUE ((CFG_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
+
+/**********************************************************
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_RESET_ON_PANIC		/* reset if system panic() */
+
+#define CFG_ENV_IS_IN_FLASH
+#ifdef CFG_ENV_IS_IN_FLASH
+  /* environment is in FLASH */
+  #define CFG_ENV_ADDR		0xF8040000	/* AM29LV641 or AM29LV800BT */
+  #define CFG_ENV_ADDR_REDUND	0xF8050000	/* AM29LV641 or AM29LV800BT */
+  #define CFG_ENV_SECT_SIZE	0x00010000
+  #define CFG_ENV_SIZE		0x00002000
+#else
+  /* environment is in EEPROM */
+  #define CFG_ENV_IS_IN_EEPROM		1
+  #define CFG_ENV_OFFSET		0	/* at beginning of EEPROM */
+  #define CFG_ENV_SIZE		     1024	/* Use only a part of it*/
+#endif
+
+#if 1
+#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR	"delayabit"
+#define CONFIG_AUTOBOOT_STOP_STR	" " /* easy to stop for now */
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h
new file mode 100755
index 0000000..f4339ec
--- /dev/null
+++ b/include/configs/Sandpoint8240.h
@@ -0,0 +1,413 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8240		1
+#define CONFIG_SANDPOINT	1
+
+#if 0
+#define USE_DINK32		1
+#else
+#undef USE_DINK32
+#endif
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"net_self=tftp ${kernel_addr} ${bootfile};"			\
+		"tftp ${ramdisk_addr} ${ramdisk};"			\
+		"run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp ${kernel_addr} ${bootfile};"			\
+		"run nfsargs addip;bootm\0"				\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/SP8240/uImage\0"				\
+	"ramdisk=/tftpboot/SP8240/uRamdisk\0"				\
+	"kernel_addr=200000\0"						\
+	"ramdisk_addr=400000\0"						\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
+#include <cmd_confdefs.h>
+
+#define CONFIG_DRAM_SPEED	100		/* MHz				*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		1		/* undef to save memory		*/
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI				/* include pci support		*/
+#undef CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI			/* Multi ethernet cards support */
+
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+
+#define PCI_ENET0_IOADDR	0x80000000
+#define PCI_ENET0_MEMADDR	0x80000000
+#define	PCI_ENET1_IOADDR	0x81000000
+#define	PCI_ENET1_MEMADDR	0x81000000
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MAX_RAM_SIZE	0x10000000
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#if defined (USE_DINK32)
+#define CFG_MONITOR_LEN		0x00030000
+#define CFG_MONITOR_BASE	0x00090000
+#define CFG_RAMBOOT		1
+#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_INIT_RAM_END	0x10000
+#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#else
+#undef	CFG_RAMBOOT
+#define CFG_MONITOR_LEN		0x00030000
+#define CFG_MONITOR_BASE	TEXT_BASE
+
+/*#define CFG_GBL_DATA_SIZE    256*/
+#define CFG_GBL_DATA_SIZE	128
+
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x1000
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#endif
+
+#define CFG_FLASH_BASE		0xFFF00000
+#if 0
+#define CFG_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom	*/
+#else
+#define CFG_FLASH_SIZE		(1024 * 1024)	/* Unity has onboard 1MByte flash */
+#endif
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
+#define CFG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
+
+#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+
+#define CFG_EUMB_ADDR		0xFC000000
+
+#define CFG_ISA_MEM		0xFD000000
+#define CFG_ISA_IO		0xFE000000
+
+#define CFG_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
+#define CFG_FLASH_RANGE_SIZE	0x01000000
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
+#define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/
+
+/*
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
+#undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#ifdef CONFIG_SOFT_I2C
+#error "Soft I2C is not configured properly.  Please review!"
+#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
+#define I2C_READ		((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
+				else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
+				else    iop->pdat &= ~0x00020000
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+
+#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CFG_EEPROM_PAGE_WRITE_BITS	3	/* write page size		*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec		*/
+
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+
+#define CFG_WINBOND_83C553	1	/*has a winbond bridge			*/
+#define CFG_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
+#define CFG_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
+#define CFG_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
+
+#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+/*
+ * NS87308 Configuration
+ */
+#define CFG_NS87308			/* Nat Semi super-io controller on ISA bus */
+
+#define CFG_NS87308_BADDR_10	1
+
+#define CFG_NS87308_DEVS	( CFG_NS87308_UART1   | \
+				  CFG_NS87308_UART2   | \
+				  CFG_NS87308_POWRMAN | \
+				  CFG_NS87308_RTC_APC )
+
+#undef  CFG_NS87308_PS2MOD
+
+#define CFG_NS87308_CS0_BASE	0x0076
+#define CFG_NS87308_CS0_CONF	0x30
+#define CFG_NS87308_CS1_BASE	0x0075
+#define CFG_NS87308_CS1_CONF	0x30
+#define CFG_NS87308_CS2_BASE	0x0074
+#define CFG_NS87308_CS2_CONF	0x30
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	1
+
+#define CFG_NS16550_CLK		1843200
+
+#define CFG_NS16550_COM1	(CFG_ISA_IO + CFG_NS87308_UART1_BASE)
+#define CFG_NS16550_COM2	(CFG_ISA_IO + CFG_NS87308_UART2_BASE)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
+#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  1
+
+#define CFG_ROMNAL		7	/*rom/flash next access time		*/
+#define CFG_ROMFAL		11	/*rom/flash access time			*/
+
+#define CFG_REFINT	430	/* no of clock cycles between CBR refresh cycles */
+
+/* the following are for SDRAM only*/
+#define CFG_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
+#define CFG_REFREC		8	/* Refresh to activate interval		*/
+#define CFG_RDLAT		4	/* data latency from read command	*/
+#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
+#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CFG_ACTORW		3	/* Activate to R/W			*/
+#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
+
+#define CFG_REGISTERD_TYPE_BUFFER   1
+
+/* memory bank settings*/
+/*
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CFG_BANK0_START		0x00000000
+#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE	1
+#define CFG_BANK1_START		0x3ff00000
+#define CFG_BANK1_END		0x3fffffff
+#define CFG_BANK1_ENABLE	0
+#define CFG_BANK2_START		0x3ff00000
+#define CFG_BANK2_END		0x3fffffff
+#define CFG_BANK2_ENABLE	0
+#define CFG_BANK3_START		0x3ff00000
+#define CFG_BANK3_END		0x3fffffff
+#define CFG_BANK3_ENABLE	0
+#define CFG_BANK4_START		0x00000000
+#define CFG_BANK4_END		0x00000000
+#define CFG_BANK4_ENABLE	0
+#define CFG_BANK5_START		0x00000000
+#define CFG_BANK5_END		0x00000000
+#define CFG_BANK5_ENABLE	0
+#define CFG_BANK6_START		0x00000000
+#define CFG_BANK6_END		0x00000000
+#define CFG_BANK6_ENABLE	0
+#define CFG_BANK7_START		0x00000000
+#define CFG_BANK7_END		0x00000000
+#define CFG_BANK7_ENABLE	0
+/*
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CFG_BANK_ENABLE		0x01
+
+#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+					/* see 8240 book for bit definitions	*/
+#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+/* SDRAM 0 - 256MB */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#if defined(USE_DINK32)
+#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
+#else
+#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#endif
+
+/* PCI memory */
+#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+
+/* values according to the manual */
+
+#define CONFIG_DRAM_50MHZ	1
+#define CONFIG_SDRAM_50MHZ
+
+#undef	NR_8259_INTS
+#define NR_8259_INTS		1
+
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h
new file mode 100755
index 0000000..d42bd69
--- /dev/null
+++ b/include/configs/Sandpoint8245.h
@@ -0,0 +1,392 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8245		1
+#define CONFIG_SANDPOINT	1
+
+#if 0
+#define USE_DINK32		1
+#else
+#undef USE_DINK32
+#endif
+
+#define CONFIG_CONS_INDEX     3               /* set to '3' for on-chip DUART */
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_DRAM_SPEED	100		/* MHz				*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		1		/* undef to save memory		*/
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI				/* include pci support		*/
+#undef CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI			/* Multi ethernet cards support */
+
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_NATSEMI
+#define CONFIG_NS8382X
+
+#define PCI_ENET0_IOADDR	0x80000000
+#define PCI_ENET0_MEMADDR	0x80000000
+#define	PCI_ENET1_IOADDR	0x81000000
+#define	PCI_ENET1_MEMADDR	0x81000000
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MAX_RAM_SIZE	0x10000000
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#if defined (USE_DINK32)
+#define CFG_MONITOR_LEN		0x00030000
+#define CFG_MONITOR_BASE	0x00090000
+#define CFG_RAMBOOT		1
+#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_INIT_RAM_END	0x10000
+#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#else
+#undef	CFG_RAMBOOT
+#define CFG_MONITOR_LEN		0x00030000
+#define CFG_MONITOR_BASE	TEXT_BASE
+
+/*#define CFG_GBL_DATA_SIZE    256*/
+#define CFG_GBL_DATA_SIZE	128
+
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x1000
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#endif
+
+#define CFG_FLASH_BASE		0xFFF00000
+#if 0
+#define CFG_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom	*/
+#else
+#define CFG_FLASH_SIZE		(1024 * 1024)	/* Unity has onboard 1MByte flash */
+#endif
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
+#define CFG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
+
+#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+
+#define CFG_EUMB_ADDR		0xFC000000
+
+#define CFG_ISA_MEM		0xFD000000
+#define CFG_ISA_IO		0xFE000000
+
+#define CFG_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
+#define CFG_FLASH_RANGE_SIZE	0x01000000
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
+#define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/
+
+/*
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
+#undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#ifdef CONFIG_SOFT_I2C
+#error "Soft I2C is not configured properly.  Please review!"
+#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
+#define I2C_READ		((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
+				else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
+				else    iop->pdat &= ~0x00020000
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+
+#define CFG_WINBOND_83C553	1	/*has a winbond bridge			*/
+#define CFG_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
+#define CFG_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
+#define CFG_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
+
+#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+/*
+ * NS87308 Configuration
+ */
+#define CFG_NS87308			/* Nat Semi super-io controller on ISA bus */
+
+#define CFG_NS87308_BADDR_10	1
+
+#define CFG_NS87308_DEVS	( CFG_NS87308_UART1   | \
+				  CFG_NS87308_UART2   | \
+				  CFG_NS87308_POWRMAN | \
+				  CFG_NS87308_RTC_APC )
+
+#undef  CFG_NS87308_PS2MOD
+
+#define CFG_NS87308_CS0_BASE	0x0076
+#define CFG_NS87308_CS0_CONF	0x30
+#define CFG_NS87308_CS1_BASE	0x0075
+#define CFG_NS87308_CS1_CONF	0x30
+#define CFG_NS87308_CS2_BASE	0x0074
+#define CFG_NS87308_CS2_CONF	0x30
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	1
+
+#if (CONFIG_CONS_INDEX > 2)
+#define CFG_NS16550_CLK         CONFIG_DRAM_SPEED*1000000
+#else
+#define CFG_NS16550_CLK         1843200
+#endif
+
+#define CFG_NS16550_COM1	(CFG_ISA_IO + CFG_NS87308_UART1_BASE)
+#define CFG_NS16550_COM2	(CFG_ISA_IO + CFG_NS87308_UART2_BASE)
+#define CFG_NS16550_COM3	(CFG_EUMB_ADDR + 0x4500)
+#define CFG_NS16550_COM4	(CFG_EUMB_ADDR + 0x4600)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
+
+#define CFG_ROMNAL		7	/*rom/flash next access time		*/
+#define CFG_ROMFAL		11	/*rom/flash access time			*/
+
+#define CFG_REFINT	430	/* no of clock cycles between CBR refresh cycles */
+
+/* the following are for SDRAM only*/
+#define CFG_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
+#define CFG_REFREC		8	/* Refresh to activate interval		*/
+#define CFG_RDLAT		4	/* data latency from read command	*/
+#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
+#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CFG_ACTORW		3	/* Activate to R/W			*/
+#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#if 0
+#define CFG_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
+#endif
+
+#define CFG_REGISTERD_TYPE_BUFFER   1
+#define CFG_EXTROM 1
+#define CFG_REGDIMM 0
+
+
+/* memory bank settings*/
+/*
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CFG_BANK0_START		0x00000000
+#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE	1
+#define CFG_BANK1_START		0x3ff00000
+#define CFG_BANK1_END		0x3fffffff
+#define CFG_BANK1_ENABLE	0
+#define CFG_BANK2_START		0x3ff00000
+#define CFG_BANK2_END		0x3fffffff
+#define CFG_BANK2_ENABLE	0
+#define CFG_BANK3_START		0x3ff00000
+#define CFG_BANK3_END		0x3fffffff
+#define CFG_BANK3_ENABLE	0
+#define CFG_BANK4_START		0x00000000
+#define CFG_BANK4_END		0x00000000
+#define CFG_BANK4_ENABLE	0
+#define CFG_BANK5_START		0x00000000
+#define CFG_BANK5_END		0x00000000
+#define CFG_BANK5_ENABLE	0
+#define CFG_BANK6_START		0x00000000
+#define CFG_BANK6_END		0x00000000
+#define CFG_BANK6_ENABLE	0
+#define CFG_BANK7_START		0x00000000
+#define CFG_BANK7_END		0x00000000
+#define CFG_BANK7_ENABLE	0
+/*
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CFG_BANK_ENABLE		0x01
+
+#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+					/* see 8240 book for bit definitions	*/
+#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+/* SDRAM 0 - 256MB */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#if defined(USE_DINK32)
+#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
+#else
+#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#endif
+
+/* PCI memory */
+#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+
+/* values according to the manual */
+
+#define CONFIG_DRAM_50MHZ	1
+#define CONFIG_SDRAM_50MHZ
+
+#undef	NR_8259_INTS
+#define NR_8259_INTS		1
+
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
new file mode 100755
index 0000000..119bc24
--- /dev/null
+++ b/include/configs/TASREG.h
@@ -0,0 +1,278 @@
+/*
+ * Configuation settings for the esd TASREG board.
+ *
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _TASREG_H
+#define _TASREG_H
+
+#ifndef __ASSEMBLY__
+#include <asm/m5249.h>
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF52x2			/* define processor family */
+#define CONFIG_M5249			/* define processor type */
+
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+
+#define CONFIG_BAUDRATE		19200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef  CONFIG_WATCHDOG
+
+#undef CONFIG_MONITOR_IS_IN_RAM	              /* no pre-loader required!!! ;-) */
+
+#define CONFIG_COMMANDS	      ((CONFIG_CMD_DFL        |    \
+				CFG_CMD_BSP           |    \
+				CFG_CMD_EEPROM        |    \
+				CFG_CMD_I2C            ) & \
+			       ~(CFG_CMD_NET))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#define CONFIG_BOOTDELAY	3
+
+#define CFG_PROMPT		"=> "
+#define CFG_LONGHELP				/* undef to save memory		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+
+#define CFG_LOAD_ADDR	        0x200000	/* default load address */
+
+#define CFG_MEMTEST_START	0x400
+#define CFG_MEMTEST_END		0x380000
+
+#define CFG_HZ			1000
+
+/*
+ * Clock configuration: enable only one of the following options
+ */
+
+#if 0 /* this setting will run the cpu at 11MHz */
+#define CFG_PLL_BYPASS          1                /* bypass PLL for test purpose */
+#undef  CFG_FAST_CLK                             /* MCF5249 can run at 140MHz   */
+#define CFG_CLK		        11289600         /* PLL bypass                  */
+#endif
+
+#if 0 /* this setting will run the cpu at 70MHz */
+#undef  CFG_PLL_BYPASS                           /* bypass PLL for test purpose */
+#undef  CFG_FAST_CLK                             /* MCF5249 can run at 140MHz   */
+#define CFG_CLK		        72185018         /* The next lower speed        */
+#endif
+
+#if 1 /* this setting will run the cpu at 140MHz */
+#undef  CFG_PLL_BYPASS                           /* bypass PLL for test purpose */
+#define CFG_FAST_CLK            1                /* MCF5249 can run at 140MHz   */
+#define	CFG_CLK		        132025600        /* MCF5249 can run at 140MHz   */
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_MBAR		0x10000000	/* Register Base Addrs */
+#define	CFG_MBAR2	        0x80000000
+
+/*-----------------------------------------------------------------------
+ * I2C
+ */
+#define	CONFIG_SOFT_I2C
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+					/* 32 byte page write mode using*/
+					/* last 5 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+#if defined (CONFIG_SOFT_I2C)
+#if 0 /* push-pull */
+#define	SDA	        0x00800000
+#define	SCL	        0x00000008
+#define DIR0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
+#define DIR1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
+#define OUT0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
+#define OUT1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
+#define IN0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
+#define IN1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
+#define	I2C_INIT	{OUT1|=SDA;OUT0|=SCL;}
+#define	I2C_READ	((IN1&SDA)?1:0)
+#define	I2C_SDA(x)	{if(x)OUT1|=SDA;else OUT1&=~SDA;}
+#define	I2C_SCL(x)	{if(x)OUT0|=SCL;else OUT0&=~SCL;}
+#define	I2C_DELAY	{udelay(5);}
+#define	I2C_ACTIVE	{DIR1|=SDA;}
+#define	I2C_TRISTATE    {DIR1&=~SDA;}
+#else /* open-collector */
+#define	SDA	        0x00800000
+#define	SCL	        0x00000008
+#define DIR0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
+#define DIR1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
+#define OUT0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
+#define OUT1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
+#define IN0	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
+#define IN1	        *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
+#define	I2C_INIT	{DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
+#define	I2C_READ	((IN1&SDA)?1:0)
+#define	I2C_SDA(x)	{if(x)DIR1&=~SDA;else DIR1|=SDA;}
+#define	I2C_SCL(x)	{if(x)DIR0&=~SCL;else DIR0|=SCL;}
+#define	I2C_DELAY	{udelay(5);}
+#define	I2C_ACTIVE	{DIR1|=SDA;}
+#define	I2C_TRISTATE    {DIR1&=~SDA;}
+#endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x20000000
+#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
+#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0xFFC40000	/* Address of Environment Sector*/
+#define CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_SIZE		16		/* SDRAM size in MB */
+#define CFG_FLASH_BASE		0xffc00000
+
+#if 0 /* test-only */
+#define CONFIG_PRAM             512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
+#endif
+
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+
+#define CFG_MONITOR_LEN		0x20000
+#define CFG_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
+#define CFG_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define	CFG_CSAR0               0xffc0
+#define	CFG_CSCR0               0x1980          /* WS=0110, AA=1, PS=10         */
+/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
+#define	CFG_CSMR0               0x003f0021      /* 4MB, AA=0, WP=0, C/I=1, V=1  */
+
+/* CS1 - FPGA, address 0xe0000000 */
+#define	CFG_CSAR1               0xe000
+#define	CFG_CSCR1               0x0d80          /* WS=0011, AA=1, PS=10         */
+#define	CFG_CSMR1               0x00010001      /* 128kB, AA=0, WP=0, C/I=0, V=1*/
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define	CFG_GPIO_FUNC           0x00000008      /* Set gpio pins: none          */
+#define	CFG_GPIO1_FUNC          0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54*/
+#define	CFG_GPIO_EN             0x00000008      /* Set gpio output enable       */
+#define	CFG_GPIO1_EN            0x00c70000      /* Set gpio output enable       */
+#define	CFG_GPIO_OUT            0x00000008      /* Set outputs to default state */
+#define	CFG_GPIO1_OUT           0x00c70000      /* Set outputs to default state */
+
+#define CFG_GPIO1_LED           0x00400000      /* user led                     */
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	512*1024    /* 512kByte is enough for XC2S200*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x00010000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x00040000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x00020000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00080000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00100000  /* FPGA done pin (ppc input)     */
+
+#endif	/* _TASREG_H */
diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
new file mode 100755
index 0000000..f41dbd0
--- /dev/null
+++ b/include/configs/TOP5200.h
@@ -0,0 +1,418 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
+ *
+ * TOP5200 differences from IceCube:
+ * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
+ *   bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
+ * 1 SDRAM/DDRAM Bank up to 256 MB
+ * local VPD I2C Bus is software driven and uses
+ *   GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
+ * FLASH is re-located at 0xff000000
+ * Internal regs are at 0xf0000000
+ * Reset jumps to 0x00000100
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
+#define CONFIG_TOP5200		1	/* ... on TOP5200 board - we need this for FEC.C */
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#  define CONFIG_PCI		1
+#  define CONFIG_PCI_PNP		1
+#  define CONFIG_PCI_SCAN_SHOW	1
+
+#  define CONFIG_PCI_MEM_BUS	0x40000000
+#  define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#  define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#  define CONFIG_PCI_IO_BUS	0x50000000
+#  define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#  define CONFIG_PCI_IO_SIZE	0x01000000
+
+#  define ADD_PCI_CMD 		CFG_CMD_PCI
+
+#else	/* no Evaluation board */
+
+#  define ADD_PCI_CMD		0  /* no CFG_CMD_PCI */
+
+#endif
+
+/* USB */
+#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
+
+#  define CONFIG_USB_OHCI
+#  define CONFIG_USB_CLOCK	0x0001bbbb
+#  if defined (CONFIG_EVAL5200)
+#    define CONFIG_USB_CONFIG	0x00005100
+#  else
+#    define CONFIG_USB_CONFIG	0x00001000
+#  endif
+#  define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
+#  define CONFIG_DOS_PARTITION
+#  define CONFIG_USB_STORAGE
+
+#else
+
+#  define ADD_USB_CMD		0
+
+#endif
+
+/* IDE */
+#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
+
+#  define ADD_IDE_CMD             CFG_CMD_IDE | CFG_CMD_FAT
+#  define CONFIG_DOS_PARTITION
+
+#else
+
+#  define ADD_IDE_CMD		0
+
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				ADD_PCI_CMD	| \
+				ADD_USB_CMD	| \
+				ADD_IDE_CMD	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_IMMAP	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_MII 	| \
+				CFG_CMD_BEDBUG	\
+			      )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * MUST be low boot - HIGHBOOT is not supported anymore
+ */
+#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT16	1
+#else
+#   error "TEXT_BASE must be 0xff000000"
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/MPC5200/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+/*
+ * EEPROM configuration
+ */
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_SIZE 0x2000
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_MISC_INIT_R
+
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support */
+#define	CONFIG_SOFT_I2C		1	/* I2C with softwate support */
+
+#if defined (CONFIG_SOFT_I2C)
+#  define SDA0			0x40
+#  define SCL0			0x80
+#  define GPIOE0		*((volatile uchar*)(CFG_MBAR+0x0c00))
+#  define DDR0			*((volatile uchar*)(CFG_MBAR+0x0c08))
+#  define DVO0			*((volatile uchar*)(CFG_MBAR+0x0c0c))
+#  define DVI0			*((volatile uchar*)(CFG_MBAR+0x0c20))
+#  define ODE0			*((volatile uchar*)(CFG_MBAR+0x0c04))
+#  define I2C_INIT		{GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
+#  define I2C_READ		((DVI0&SDA0)?1:0)
+#  define I2C_SDA(x)	{if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
+#  define I2C_SCL(x)	{if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
+#  define I2C_DELAY		{udelay(5);}
+#  define I2C_ACTIVE	{DDR0|=SDA0;}
+#  define I2C_TRISTATE	{DDR0&=~SDA0;}
+#  define CFG_I2C_SPEED		100000
+#  define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_FACT_ADDR	0x57
+#endif
+
+#if defined (CONFIG_HARD_I2C)
+#  define CFG_I2C_MODULE	2		/* Select I2C module #1 or #2 */
+#  define CFG_I2C_SPEED		100000	/* 100 kHz */
+#  define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_EEPROM_ADDR 0x54
+#define CFG_I2C_FACT_ADDR	0x54
+#endif
+
+/*
+ * Flash configuration, expect one 16 Megabyte Bank at most
+ */
+#define CFG_FLASH_BASE		0xff000000
+#define CFG_FLASH_SIZE		0x01000000
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0)
+
+#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */
+
+/*
+ * DRAM configuration - will be read from VPD later... TODO!
+ */
+#if 0
+/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
+#define	CFG_DRAM_DDR		0
+#define CFG_DRAM_EMODE		0
+#define CFG_DRAM_MODE		0x008D
+#define CFG_DRAM_CONTROL	0x514F0000
+#define CFG_DRAM_CONFIG1	0xC2233A00
+#define CFG_DRAM_CONFIG2	0x88B70004
+#define	CFG_DRAM_TAP_DEL	0x08
+#define CFG_DRAM_RAM_SIZE	0x19
+#endif
+#if 1
+/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
+#define	CFG_DRAM_DDR		0
+#define CFG_DRAM_EMODE		0
+#define CFG_DRAM_MODE		0x00CD
+#define CFG_DRAM_CONTROL	0x514F0000
+#define CFG_DRAM_CONFIG1	0xD2333A00
+#define CFG_DRAM_CONFIG2	0x8AD70004
+#define	CFG_DRAM_TAP_DEL	0x08
+#define CFG_DRAM_RAM_SIZE	0x19
+#endif
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
+#define CFG_ENV_OFFSET		0x1000
+#define CFG_ENV_SIZE		0x0700
+
+/*
+ * VPD settings
+ */
+#define CFG_FACT_OFFSET		0x1800
+#define CFG_FACT_SIZE		0x0800
+
+/*
+ * Memory map
+ *
+ * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
+ */
+#define CFG_MBAR			0xf0000000	/* DO NOT CHANGE this */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_FEC_10MBIT	1		/* Workaround for FEC 100Mbit problem */
+#define	CONFIG_PHY_ADDR		0x1f
+#define	CONFIG_PHY_TYPE		0x79c874
+/*
+ * GPIO configuration:
+ * PSC1,2,3 predefined as UART
+ * PCI disabled
+ * Ethernet 100 with MD
+ */
+#define CFG_GPS_PORT_CONFIG	0x00058044
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#  define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x200000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#ifdef CONFIG_EVAL5200		/* M48T08 is available with the Evaluation board only */
+  #define CONFIG_RTC_MK48T59	1	/* use M48T08 on EVAL5200 */
+  #define RTC(reg)		(0xf0010000+reg)
+  /* setup CS2 for M48T08. Must MAP 64kB */
+  #define CFG_CS2_START	RTC(0)
+  #define CFG_CS2_SIZE	0x10000
+  /* setup CS2 configuration register: */
+  /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
+  /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
+  #define CFG_CS2_CFG	0x00047800
+#else
+  #define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
+#endif
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x00047801
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0x7f000000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define CONFIG_IDE_RESET	1
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005c)
+
+/* Interval between registers                                                */
+#define CFG_ATA_STRIDE          4
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h
new file mode 100755
index 0000000..2344b96
--- /dev/null
+++ b/include/configs/TOP860.h
@@ -0,0 +1,442 @@
+/*
+ * (C) Copyright 2003
+ * EMK Elektronik GmbH <www.emk-elektronik.de>
+ * Reinhard Meyer <r.meyer@emk-elektronik.de>
+ *
+ * Configuation settings for the TOP860 board.
+ *
+ * -----------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * TOP860 is a simple module:
+ * 16-bit wide FLASH on CS0	(2MB or more)
+ * 32-bit wide DRAM on CS2 (either 4MB or 16MB)
+ * FEC with Am79C874 100-Base-T and Fiber Optic
+ * Ports available, but we choose SMC1 for Console
+ * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
+ * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
+ *
+ * This config has been copied from MBX.h / MBX860T.h
+ */
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/*-----------------------------------------------------------------------
+ * CPU and BOARD type
+ */
+#define CONFIG_MPC860	1	/* This is a MPC860 CPU		*/
+#define CONFIG_MPC860T	1	/* even better... an FEC!	*/
+#define CONFIG_TOP860	1	/* ...on a TOP860 module	*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define	CONFIG_IDENT_STRING " EMK TOP860"
+
+/*-----------------------------------------------------------------------
+ * CLOCK settings
+ */
+#define	CONFIG_SYSCLK	49152000
+#define	CFG_XTAL		32768
+#define	CONFIG_EBDF		1
+#define	CONFIG_COM		3
+#define	CONFIG_RTC_MPC8xx
+
+/*-----------------------------------------------------------------------
+ * Physical memory map as defined by EMK
+ */
+#define CFG_IMMR		0xFFF00000	/* Internal Memory Mapped Register */
+#define	CFG_FLASH_BASE	0x80000000	/* FLASH in final mapping */
+#define	CFG_DRAM_BASE	0x00000000	/* DRAM in final mapping */
+#define	CFG_FLASH_MAX	0x00400000	/* max FLASH to expect */
+#define	CFG_DRAM_MAX	0x01000000	/* max DRAM to expect */
+
+/*-----------------------------------------------------------------------
+ * derived values
+ */
+#define	CFG_MF			(CONFIG_SYSCLK/CFG_XTAL)
+#define	CFG_CPUCLOCK	CONFIG_SYSCLK
+#define	CFG_BRGCLOCK	CONFIG_SYSCLK
+#define	CFG_BUSCLOCK	(CONFIG_SYSCLK >> CONFIG_EBDF)
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+#define	CONFIG_8xx_GCLK_FREQ	CONFIG_SYSCLK
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_FLASH_CFI
+
+/*-----------------------------------------------------------------------
+ * Command interpreter
+ */
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#define CONFIG_BAUDRATE		9600
+
+/*
+ * Allow partial commands to be matched to uniqueness.
+ */
+#define CFG_MATCH_PARTIAL_CMD
+
+/*
+ * List of available monitor commands.  Use the system default list
+ * plus add some of the "non-standard" commands back in.
+ * See ./cmd_confdefs.h
+ */
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+								CFG_CMD_ASKENV	| \
+								CFG_CMD_DHCP	| \
+								CFG_CMD_I2C		| \
+								CFG_CMD_EEPROM	| \
+								CFG_CMD_REGINFO	| \
+								CFG_CMD_IMMAP	| \
+								CFG_CMD_ELF		| \
+								CFG_CMD_DATE	| \
+								CFG_CMD_MII 	| \
+								CFG_CMD_BEDBUG	\
+						      )
+
+#define	CONFIG_AUTOSCRIPT		1
+#define	CFG_LOADS_BAUD_CHANGE	1
+#undef	CONFIG_LOADS_ECHO			/* NO echo on for serial download	*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* Hush parse for U-Boot	*/
+
+#ifdef	CFG_HUSH_PARSER
+ #define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+ #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/*-----------------------------------------------------------------------
+ * Memory Test Command
+ */
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+/*-----------------------------------------------------------------------
+ * Environment handler
+ * only the first 6k in EEPROM are available for user. Of that we use 256b
+ */
+#define	CONFIG_SOFT_I2C
+#define CFG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
+#define CFG_ENV_OFFSET		0x1000
+#define CFG_ENV_SIZE		0x0700
+#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_FACT_OFFSET		0x1800
+#define CFG_FACT_SIZE		0x0800
+#define CFG_I2C_FACT_ADDR	0x57
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_SIZE 0x2000
+#define	CFG_I2C_SPEED	100000
+#define	CFG_I2C_SLAVE	0xFE
+#define	CFG_EEPROM_PAGE_WRITE_DELAY_MS 12
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_MISC_INIT_R
+
+#if defined (CONFIG_SOFT_I2C)
+#define	SDA	0x00010
+#define	SCL	0x00020
+#define __I2C_DIR	immr->im_cpm.cp_pbdir
+#define __I2C_DAT	immr->im_cpm.cp_pbdat
+#define __I2C_PAR	immr->im_cpm.cp_pbpar
+#define	__I2C_ODR	immr->im_cpm.cp_pbodr
+#define	I2C_INIT	{ __I2C_PAR &= ~(SDA|SCL);	\
+			  __I2C_ODR &= ~(SDA|SCL);	\
+			  __I2C_DAT |= (SDA|SCL);	\
+			  __I2C_DIR|=(SDA|SCL);	}
+#define	I2C_READ	((__I2C_DAT & SDA) ? 1 : 0)
+#define	I2C_SDA(x)	{ if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
+#define	I2C_SCL(x)	{ if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
+#define	I2C_DELAY	{ udelay(5); }
+#define	I2C_ACTIVE	{ __I2C_DIR |= SDA; }
+#define	I2C_TRISTATE	{ __I2C_DIR &= ~SDA; }
+#endif
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*-----------------------------------------------------------------------
+ * defines we need to get FEC running
+ */
+#define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
+#define CONFIG_FEC_ENET 	1	/* Ethernet only via FEC	*/
+#define	FEC_ENET			1	/* eth.c needs it that way... */
+#define CFG_DISCOVER_PHY	1
+#define CONFIG_MII			1
+#define CONFIG_PHY_ADDR		31
+
+/*-----------------------------------------------------------------------
+ * adresses
+ */
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x80000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2f00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
+#define CFG_INIT_VPD_OFFSET	(CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
+#define CFG_INIT_SP_OFFSET	(CFG_INIT_VPD_OFFSET-8)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*-----------------------------------------------------------------------
+ * Debug Enable Register
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0					/* used in start.S */
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * set up PLPRCR (PLL, Low-Power, and Reset Control Register)
+ *	12	MF		calculated	Multiplication factor
+ *	4	0		0000
+ *	1	SPLSS	0			System PLL lock status sticky
+ *	1	TEXPS	1			Timer expired status
+ *	1	0		0
+ *	1	TMIST	0			Timers interrupt status
+ *	1	0		0
+ *	1	CSRC	0			Clock source (0=DFNH, 1=DFNL)
+ *	2	LPM		00			Low-power modes
+ *	1	CSR		0			Checkstop reset enable
+ *	1	LOLRE	0			Loss-of-lock reset enable
+ *	1	FIOPD	0			Force I/O pull down
+ *	5	0		00000
+ */
+#define CFG_PLPRCR	(PLPRCR_TEXPS | ((CFG_MF-1)<<20))
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * set up SYPCR:
+ *	16	SWTC	0xffff		Software watchdog timer count
+ *	8	BMT		0xff 		Bus monitor timing
+ *	1	BME		1			Bus monitor enable
+ *	3	0		000
+ *	1	SWF		1			Software watchdog freeze
+ *	1	SWE		0/1			Software watchdog enable
+ *	1	SWRI	0/1			Software watchdog reset/interrupt select (1=HRESET)
+ *	1	SWP		0/1			Software watchdog prescale (1=/2048)
+ */
+#if defined (CONFIG_WATCHDOG)
+ #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 		 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+ #define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * set up SIUMCR
+ *	1	EARB	0			External arbitration
+ *	3	EARP	000			External arbitration request priority
+ *	4	0		0000
+ *	1	DSHW	0			Data show cycles
+ *	2	DBGC	00			Debug pin configuration
+ *	2	DBPC	00			Debug port pins configuration
+ *	1	0		0
+ *	1	FRC		0			FRZ pin configuration
+ *	1	DLK		0			Debug register lock
+ *	1	OPAR	0			Odd parity
+ *	1	PNCS	0			Parity enable for non memory controller regions
+ *	1	DPC		0			Data parity pins configuration
+ *	1	MPRE	0			Multiprocessor reservation enable
+ *	2	MLRC	11			Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
+ *	1	AEME	0			Async external master enable
+ *	1	SEME	0			Sync external master enable
+ *	1	BSC		0			Byte strobe configuration
+ *	1	GB5E	0			GPL_B5 enable
+ *	1	B2DD	0			Bank 2 double drive
+ *	1	B3DD	0			Bank 3 double drive
+ *	4	0		0000
+ */
+#define CFG_SIUMCR	(SIUMCR_MLRC11)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * set up SCCR (System Clock and Reset Control Register)
+ *	1	0		0
+ *	2	COM		11			Clock output module (00=full, 01=half, 11=off)
+ *	3	0		000
+ *	1	TBS		1			Timebase source (0=OSCCLK, 1=GCLK2)
+ *	1	RTDIV	0			Real-time clock divide (0=/4, 1=/512)
+ *	1	RTSEL	0			Real-time clock select (0=OSCM, 1=EXTCLK)
+ *	1	CRQEN	0			CPM request enable
+ *	1	PRQEN	0			Power management request enable
+ *	2	0		00
+ *	2	EBDF	xx			External bus division factor
+ *	2	0		00
+ *	2	DFSYNC	00			Division factor for SYNCLK
+ *	2	DFBRG	00			Division factor for BRGCLK
+ *	3	DFNL	000			Division factor low frequency
+ *	3	DFNH	000			Division factor high frequency
+ *	5	0		00000
+ */
+#define SCCR_MASK	0
+#ifdef CONFIG_EBDF
+ #define CFG_SCCR	(SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
+#else
+ #define CFG_SCCR	(SCCR_COM11 | SCCR_TBS)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Chip Select 0 - FLASH
+ *-----------------------------------------------------------------------
+ * Preliminary Values
+ */
+/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
+#define CFG_OR0_PRELIM	(-CFG_FLASH_MAX | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	(CFG_FLASH_BASE | BR_PS_16 | BR_V )
+
+/*-----------------------------------------------------------------------
+ * misc
+ *-----------------------------------------------------------------------
+ *
+ */
+/*
+ * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
+ */
+#define CONFIG_BOOTDELAY				5
+
+/*
+ * Pass the clock frequency to the Linux kernel in units of MHz
+ */
+#define	CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_PREBOOT		\
+	"echo;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND	\
+	"bootp;" \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+	"bootm"
+
+/*
+ * BOOTP options
+ */
+#undef	CONFIG_BOOTP_MASK
+#define CONFIG_BOOTP_MASK				( CONFIG_BOOTP_DEFAULT		| \
+									  	  CONFIG_BOOTP_BOOTFILESIZE   \
+										)
+
+
+/*
+ * Set default IP stuff just to get bootstrap entries into the
+ * environment so that we can autoscript the full default environment.
+ */
+#define CONFIG_ETHADDR					9a:52:63:15:85:25
+#define CONFIG_SERVERIP					10.0.4.200
+#define CONFIG_IPADDR					10.0.4.111
+
+/*-----------------------------------------------------------------------
+ * Defaults for Autoscript
+ */
+#define CFG_LOAD_ADDR		0x00100000	/* default load address */
+#define	CFG_TFTP_LOADADDR	0x00100000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
new file mode 100755
index 0000000..5ad1939
--- /dev/null
+++ b/include/configs/TQM5200.h
@@ -0,0 +1,564 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
+#define CONFIG_TQM5200		1	/* ... on TQM5200 module */
+#undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules */
+#define CONFIG_STK52XX		1	/* ... on a STK52XX base board */
+#define CONFIG_STK52XX_REV100	1	/*  define for revision 100 baseboards */
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#ifdef CONFIG_STK52XX
+#define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
+#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
+#define CONFIG_PS2SERIAL	6	/* .. on PSC6			*/
+#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
+#define CONFIG_BOARD_EARLY_INIT_R
+#endif /* CONFIG_STK52XX */
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#ifdef CONFIG_STK52XX
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+/* #define CONFIG_PCI_SCAN_SHOW	1 */
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X		1
+#endif	/* CONFIG_STK52XX */
+
+#ifdef CONFIG_PCI
+#define ADD_PCI_CMD		CFG_CMD_PCI
+#else
+#define ADD_PCI_CMD		0
+#endif
+
+/*
+ * Video console
+ */
+#if 1
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501
+#define CONFIG_VIDEO_SM501_32BPP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CFG_CONSOLE_IS_IN_ENV
+#endif
+
+#ifdef CONFIG_VIDEO
+#define ADD_BMP_CMD		CFG_CMD_BMP
+#else
+#define ADD_BMP_CMD		0
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* USB */
+#ifdef CONFIG_STK52XX
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD		0
+#endif
+
+/* POST support */
+#define CONFIG_POST		(CFG_POST_MEMORY   | \
+				 CFG_POST_CPU	   | \
+				 CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+
+/* IDE */
+#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
+#define ADD_IDE_CMD		(CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
+#else
+#define ADD_IDE_CMD		0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				ADD_BMP_CMD	| \
+				ADD_IDE_CMD	| \
+				ADD_PCI_CMD	| \
+				ADD_USB_CMD	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ECHO	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_POST_DIAG | \
+				CFG_CMD_REGINFO | \
+				CFG_CMD_SNTP	| \
+				CFG_CMD_BSP)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define	CONFIG_TIMESTAMP		/* display image timestamps */
+
+#if (TEXT_BASE == 0xFC000000)		/* Boot low */
+#   define CFG_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#if defined (CONFIG_TQM5200_AA)
+# define CONFIG_U_BOOT_SUFFIX	"-AA\0"
+#elif defined (CONFIG_TQM5200_AB)
+# define CONFIG_U_BOOT_SUFFIX	"-AB\0"
+#elif defined (CONFIG_TQM5200_AC)
+# define CONFIG_U_BOOT_SUFFIX	"-AC\0"
+#else
+# define CONFIG_U_BOOT_SUFFIX	"\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"bootfile=/tftpboot/tqm5200/uImage\0"				\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"u-boot=/tftpboot/tqm5200/u-boot.bin"	CONFIG_U_BOOT_SUFFIX	\
+	"update=protect off FC000000 FC05FFFF;"				\
+		"erase FC000000 FC05FFFF;"				\
+		"cp.b 200000 FC000000 ${filesize};"			\
+		"protect on FC000000 FC05FFFF\0"			\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#ifdef CONFIG_TQM5200_REV100
+#define CFG_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
+#else
+#define CFG_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
+#endif
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
+ * also). For other EEPROMs configuration should be verified. On Mini-FAP the
+ * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
+ * same configuration could be used.
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/*
+ * HW-Monitor configuration on Mini-FAP
+ */
+#if defined (CONFIG_MINIFAP)
+#define CFG_I2C_HWMON_ADDR		0x2C
+#endif
+
+/* List of I2C addresses to be verified by POST */
+#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB)
+#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
+				CFG_I2C_SLAVE }
+#elif defined (CONFIG_TQM5200_AC)
+#define I2C_ADDR_LIST	{	CFG_I2C_SLAVE }
+#endif
+
+#if defined (CONFIG_MINIFAP)
+#undef I2C_ADDR_LIST
+#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
+				CFG_I2C_HWMON_ADDR,	\
+				CFG_I2C_SLAVE }
+#endif
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver if no module variant is spezified */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#undef CFG_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
+
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00760000 + 0x00800000)
+#else	/* CFG_LOWBOOT */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
+#endif	/* CFG_LOWBOOT */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+/* Dynamic MTD partition support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=TQM5200-0"
+#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
+						"1408k(kernel),"	\
+						"2m(initrd),"		\
+						"4m(small-fs),"		\
+						"16m(big-fs),"		\
+						"8m(misc)"
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x10000
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ *
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
+ *	Bit 0 (mask: 0x80000000): 1
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ *	00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ *	      Use for REV200 STK52XX boards. Do not use with REV100 modules
+ *	      (because, there I2C1 is used as I2C bus)
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
+ *	000 -> All PSC2 pins are GIOPs
+ *	001 -> CAN1/2 on PSC2 pins
+ *	       Use for REV100 STK52xx boards
+ * use PSC6:
+ *   on STK52xx:
+ *	use as UART. Pins PSC6_0 to PSC6_3 are used.
+ *	Bits 9:11 (mask: 0x00700000):
+ *	   101 -> PSC6 : Extended POST test is not available
+ *   on MINI-FAP and TQM5200_IB:
+ *	use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
+ *	   000 -> PSC6 could not be used as UART, CODEC or IrDA
+ *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
+ *   tests.
+ */
+#if defined (CONFIG_MINIFAP)
+# define CFG_GPS_PORT_CONFIG	0x91000004
+#elif defined (CONFIG_STK52XX)
+# if defined (CONFIG_STK52XX_REV100)
+#  define CFG_GPS_PORT_CONFIG	0x81500014
+# else /* STK52xx REV200 and above */
+#  if defined (CONFIG_TQM5200_REV100)
+#   error TQM5200 REV100 not supported on STK52XX REV200 or above
+#  else/* TQM5200 REV200 and above */
+#   define CFG_GPS_PORT_CONFIG	0x91500004
+#  endif
+# endif
+#else  /* TMQ5200 Inbetriebnahme-Board */
+# define CFG_GPS_PORT_CONFIG	0x81000004
+#endif
+
+/*
+ * RTC configuration
+ */
+#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
+# define CONFIG_RTC_M41T11 1
+# define CFG_I2C_RTC_ADDR 0x68
+#else
+# define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#ifdef CFG_PCISPEED_66
+#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
+#endif
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+/* automatic configuration of chip selects */
+#ifdef CONFIG_CS_AUTOCONF
+#define CONFIG_LAST_STAGE_INIT
+#endif
+
+/*
+ * SRAM - Do not map below 2 GB in address space, because this area is used
+ * for SDRAM autosizing.
+ */
+#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF)
+#define CFG_CS2_START		0xE5000000
+#ifdef CONFIG_TQM5200_AB
+#define CFG_CS2_SIZE		0x80000		/* 512 kByte */
+#else  /* CONFIG_CS_AUTOCONF */
+#define CFG_CS2_SIZE		0x100000	/* 1 MByte */
+#endif
+#define CFG_CS2_CFG		0x0004D930
+#endif
+
+/*
+ * Grafic controller - Do not map below 2 GB in address space, because this
+ * area is used for SDRAM autosizing.
+ */
+#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \
+    defined (CONFIG_CS_AUTOCONF)
+#define SM501_FB_BASE		0xE0000000
+#define CFG_CS1_START		(SM501_FB_BASE)
+#define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
+#define CFG_CS1_CFG		0x8F48FF70
+#define SM501_MMIO_BASE		CFG_CS1_START + 0x03E00000
+#endif
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers						     */
+#define CFG_ATA_STRIDE		4
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
new file mode 100755
index 0000000..b1c70f8
--- /dev/null
+++ b/include/configs/TQM823L.h
@@ -0,0 +1,453 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_TQM823L		1	/* ...on a TQM8xxL module	*/
+
+#ifdef	CONFIG_LCD			/* with LCD controller ?	*/
+#define	CONFIG_SPLASH_SCREEN		/* ... with splashscreen support*/
+#endif
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM823L/uImage\0"				\
+	"kernel_addr=40040000\0"					\
+	"ramdisk_addr=40100000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#if defined(CONFIG_LCD)
+# undef	 CONFIG_STATUS_LED		/* disturbs display		*/
+#else
+# define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#endif	/* CONFIG_LCD */
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#ifdef	CONFIG_SPLASH_SCREEN
+# define CONFIG_COMMANDS      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_BMP	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+#else
+# define CONFIG_COMMANDS      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
new file mode 100755
index 0000000..9f958f5
--- /dev/null
+++ b/include/configs/TQM823M.h
@@ -0,0 +1,443 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_TQM823M		1	/* ...on a TQM8xxM module	*/
+
+#ifdef	CONFIG_LCD			/* with LCD controller ?	*/
+/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display	*/
+#endif
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM823M/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#ifdef CONFIG_LCD
+# undef	 CONFIG_STATUS_LED		/* disturbs display		*/
+#else
+# define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#endif	/* CONFIG_LCD */
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x08000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
new file mode 100755
index 0000000..49c3872
--- /dev/null
+++ b/include/configs/TQM8260.h
@@ -0,0 +1,639 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Imported from global configuration:
+ *	CONFIG_MPC8255
+ *	CONFIG_MPC8265
+ *	CONFIG_200MHz
+ *	CONFIG_266MHz
+ *	CONFIG_300MHz
+ *	CONFIG_L2_CACHE
+ *	CONFIG_BUSMODE_60x
+ */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is a MPC8260 CPU		*/
+
+#if 0
+#define CONFIG_TQM8260		100	/* ...on a TQM8260 module Rev.100	*/
+#else
+#define CONFIG_TQM8260		200	/* ...on a TQM8260 module Rev.200	*/
+#endif
+
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define CONFIG_82xx_CONS_SMC1	1	/* console on SMC1			*/
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/TQM8260/uImage\0"				\
+	"kernel_addr=40040000\0"					\
+	"ramdisk_addr=40100000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/* enable I2C and select the hardware/software driver */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+
+/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
+#if (CONFIG_TQM8260 <= 100)
+
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00020000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00020000)
+#define I2C_READ	((iop->pdat & 0x00020000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#else
+
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+#endif
+
+#define CFG_I2C_EEPROM_ADDR	0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CONFIG_I2C_X
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else*/
+#ifdef CONFIG_82xx_CONS_SMC1
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+#endif
+#ifdef CONFIG_82xx_CONS_SMC2
+#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
+#endif
+
+#undef  CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
+#define CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
+#define CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9 */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ *
+ * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
+ * X.29 connector, and FCC2 is hardwired to the X.1 connector)
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define	CONFIG_ETHER_INDEX    2		/* which SCC/FCC channel for ethernet */
+
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+
+/*
+ *  - RX clk is CLK11
+ *  - TX clk is CLK12
+ */
+# define CFG_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
+#  define CONFIG_8260_CLKIN	66666666	/* in Hz */
+#else	/* !CONFIG_MPC8255 && !CONFIG_MPC8265 */
+# ifndef CONFIG_300MHz
+#  define CONFIG_8260_CLKIN	66666666	/* in Hz */
+# else
+#  define CONFIG_8260_CLKIN	83333000	/* in Hz */
+# endif
+#endif	/* CONFIG_MPC8255 */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CFG_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
+ * The main FLASH is whichever is connected to *CS0.
+ */
+#define CFG_FLASH0_BASE 0x40000000
+#define CFG_FLASH1_BASE 0x60000000
+#define CFG_FLASH0_SIZE 32
+#define CFG_FLASH1_SIZE 32
+
+/* Flash bank size (for preliminary settings)
+ */
+#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#if 0
+/* Start port with environment in flash; switch to EEPROM later */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x40000)
+#define CFG_ENV_SIZE		0x40000
+#define CFG_ENV_SECT_SIZE	0x40000
+#else
+/* Final version: environment in EEPROM */
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_ENV_OFFSET		0
+#define CFG_ENV_SIZE		2048
+#endif
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#define	__HRCW__ALL__		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
+
+#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
+#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
+#else	/* ! MPC8255 && !MPC8265 */
+# if defined(CONFIG_266MHz)
+#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
+# elif defined(CONFIG_300MHz)
+#  define CFG_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0110)
+# else
+#  define CFG_HRCW_MASTER	(__HRCW__ALL__)
+# endif
+#endif	/* CONFIG_MPC8255 */
+
+/* no slaves so just fill with zeros */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x4000  /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
+ * is mapped at SDRAM_BASE2_PRELIM.
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		CFG_FLASH0_BASE
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CFG_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR         RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#ifdef	CONFIG_BUSMODE_60x
+#define CFG_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
+			 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2)	/* 60x mode  */
+#else
+#define BCR_APD01	0x10000000
+#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#if 0
+#define CFG_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
+#else
+#define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR        0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    64 bit  FLASH
+ *  1   60x     SDRAM   64 bit  SDRAM
+ *  2   Local   SDRAM   32 bit  SDRAM
+ *
+ */
+
+	/* Initialize SDRAM on local bus
+	 */
+#define CFG_INIT_LOCAL_SDRAM
+
+#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+
+/* Minimum mask to separate preliminary
+ * address ranges for CS[0:2]
+ */
+#define CFG_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
+#define CFG_LOCAL_SDRAM_LIMIT	(128<<20)	/* less than 128 MB */
+
+#define CFG_MPTPR       0x4000
+
+/*-----------------------------------------------------------------------------
+ * Address for Mode Register Set (MRS) command
+ *-----------------------------------------------------------------------------
+ * In fact, the address is rather configuration data presented to the SDRAM on
+ * its address lines. Because the address lines may be mux'ed externally either
+ * for 8 column or 9 column devices, some bits appear twice in the 8260's
+ * address:
+ *
+ * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
+ * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
+ *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
+ *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
+ *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
+ *-----------------------------------------------------------------------------
+ */
+#define CFG_MRS_OFFS	0x00000110
+
+
+/* Bank 0 - FLASH
+ */
+#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxG_EHTR                      |\
+			 ORxG_TRLX)
+
+	/* SDRAM on TQM8260 can have either 8 or 9 columns.
+	 * The number affects configuration values.
+	 */
+
+/* Bank 1 - 60x bus SDRAM
+ */
+#define CFG_PSRT        0x20
+#define CFG_LSRT        0x20
+#ifndef CFG_RAMBOOT
+#define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CFG_OR1_PRELIM	CFG_OR1_8COL
+
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A7             |\
+			 ORxS_NUMR_12)
+
+#define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A15_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A8            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A5             |\
+			 ORxS_NUMR_13)
+
+#define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A16_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A7            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_CL_2)
+
+/* Bank 2 - Local bus SDRAM
+ */
+#ifdef CFG_INIT_LOCAL_SDRAM
+#define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
+			 BRx_PS_32                      |\
+			 BRx_MS_SDRAM_L                 |\
+			 BRx_V)
+
+#define CFG_OR2_PRELIM	CFG_OR2_8COL
+
+#define SDRAM_BASE2_PRELIM	0x80000000
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CFG_OR2_8COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A8             |\
+			 ORxS_NUMR_12)
+
+#define CFG_LSDMR_8COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A15_IS_A5           |\
+			 PSDMR_BSMA_A13_A15             |\
+			 PSDMR_SDA10_PBI1_A9            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CFG_OR2_9COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A6             |\
+			 ORxS_NUMR_13)
+
+#define CFG_LSDMR_9COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A16_IS_A5           |\
+			 PSDMR_BSMA_A13_A15             |\
+			 PSDMR_SDA10_PBI1_A8            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_CL_2)
+
+#endif /* CFG_INIT_LOCAL_SDRAM */
+
+#endif /* CFG_RAMBOOT */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
new file mode 100755
index 0000000..41f44c5
--- /dev/null
+++ b/include/configs/TQM834x.h
@@ -0,0 +1,511 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * TQM8349 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DEBUG
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC83XX		1	/* MPC83XX family */
+#define CONFIG_MPC834X		1	/* MPC834X specific */
+#define CONFIG_TQM834X		1	/* TQM834X board specific */
+
+/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
+#define CFG_IMMRBAR		0xff400000
+
+/* System clock. Primary input clock when in PCI host mode */
+#define CONFIG_83XX_CLKIN	66666000	/* 66,666 MHz */
+
+/*
+ * Local Bus LCRR
+ *    LCRR:  DLL bypass, Clock divider is 8
+ *
+ *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
+ *
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
+
+/* board pre init: do not call, nothing to do */
+#undef CONFIG_BOARD_EARLY_INIT_F
+
+/* detect the number of flash banks */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define DDR_CASLAT_25				/* CASLAT set to 2.5 */
+#undef CONFIG_DDR_ECC				/* only for ECC DDR module */
+#undef CONFIG_SPD_EEPROM			/* do not use SPD EEPROM for DDR setup */
+
+#undef CFG_DRAM_TEST				/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00000000	/* memtest region */
+#define CFG_MEMTEST_END		0x00100000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI				/* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_BASE		0x80000000	/* start of FLASH   */
+
+/* buffered writes in the AMD chip set is not supported yet */
+#undef CFG_FLASH_USE_BUFFER_WRITE
+
+/*
+ * FLASH bank number detection
+ */
+
+/*
+ * When CFG_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
+ * banks has to be determined at runtime and stored in a gloabl variable
+ * tqm834x_num_flash_banks. The value of CFG_MAX_FLASH_BANKS_DETECT is only
+ * used instead of CFG_MAX_FLASH_BANKS to allocate the array flash_info, and
+ * should be made sufficiently large to accomodate the number of banks that
+ * might actually be detected.  Since most (all?) Flash related functions use
+ * CFG_MAX_FLASH_BANKS as the number of actual banks on the board, it is
+ * defined as tqm834x_num_flash_banks.
+ */
+#define CFG_MAX_FLASH_BANKS_DETECT	2
+#ifndef __ASSEMBLY__
+extern int tqm834x_num_flash_banks;
+#endif
+#define CFG_MAX_FLASH_BANKS (tqm834x_num_flash_banks)
+
+#define CFG_MAX_FLASH_SECT		512	/* max sectors per device */
+
+/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
+#define CFG_BR0_PRELIM		((CFG_FLASH_BASE & BR_BA) | \
+					BR_MS_GPCM | BR_PS_32 | BR_V)
+
+/* FLASH timing (0x0000_0c54) */
+#define CFG_OR_TIMING_FLASH	(OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \
+					OR_GPCM_SCY_5 | OR_GPCM_TRLX)
+
+#define CFG_PRELIM_OR_AM	0xc0000000	/* OR addr mask: 1 GiB */
+
+#define CFG_OR0_PRELIM		(CFG_PRELIM_OR_AM  | CFG_OR_TIMING_FLASH)
+
+#define CFG_LBLAWAR0_PRELIM	0x8000001D	/* 1 GiB window size (2^(size + 1)) */
+
+#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* Window base at flash base */
+
+/* disable remaining mappings */
+#define CFG_BR1_PRELIM		0x00000000
+#define CFG_OR1_PRELIM		0x00000000
+#define CFG_LBLAWBAR1_PRELIM	0x00000000
+#define CFG_LBLAWAR1_PRELIM	0x00000000
+
+#define CFG_BR2_PRELIM		0x00000000
+#define CFG_OR2_PRELIM		0x00000000
+#define CFG_LBLAWBAR2_PRELIM	0x00000000
+#define CFG_LBLAWAR2_PRELIM	0x00000000
+
+#define CFG_BR3_PRELIM		0x00000000
+#define CFG_OR3_PRELIM		0x00000000
+#define CFG_LBLAWBAR3_PRELIM	0x00000000
+#define CFG_LBLAWAR3_PRELIM	0x00000000
+
+#define CFG_BR4_PRELIM		0x00000000
+#define CFG_OR4_PRELIM		0x00000000
+#define CFG_LBLAWBAR4_PRELIM	0x00000000
+#define CFG_LBLAWAR4_PRELIM	0x00000000
+
+#define CFG_BR5_PRELIM		0x00000000
+#define CFG_OR5_PRELIM		0x00000000
+#define CFG_LBLAWBAR5_PRELIM	0x00000000
+#define CFG_LBLAWAR5_PRELIM	0x00000000
+
+#define CFG_BR6_PRELIM		0x00000000
+#define CFG_OR6_PRELIM		0x00000000
+#define CFG_LBLAWBAR6_PRELIM	0x00000000
+#define CFG_LBLAWAR6_PRELIM	0x00000000
+
+#define CFG_BR7_PRELIM		0x00000000
+#define CFG_OR7_PRELIM		0x00000000
+#define CFG_LBLAWBAR7_PRELIM	0x00000000
+#define CFG_LBLAWAR7_PRELIM	0x00000000
+
+/*
+ * Monitor config
+ */
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0x20000000	/* Initial RAM address */
+#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/
+
+#define CFG_GBL_DATA_SIZE  	0x100		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1	(CFG_IMMRBAR + 0x4500)
+#define CFG_NS16550_COM2	(CFG_IMMRBAR + 0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C				/* I2C with hardware support	*/
+#undef CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED			400000	/* I2C speed: 400KHz		*/
+#define CFG_I2C_SLAVE			0x7F	/* slave address		*/
+#define CFG_I2C_OFFSET			0x3000
+
+/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x			*/
+#define CFG_I2C_EEPROM_ADDR_LEN		2	/* 16 bit			*/
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 32 bytes per write		*/
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	12	/* 10ms +/- 20%			*/
+#define CFG_I2C_MULTI_EEPROMS		1       /* more than one eeprom		*/
+
+/* I2C RTC */
+#define CONFIG_RTC_DS1337			/* use ds1337 rtc via i2c	*/
+#define CFG_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75			1	/* ON Semi's LM75		*/
+#define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses		*/
+#define CFG_DTT_MAX_TEMP		70
+#define CFG_DTT_LOW_TEMP		-30
+#define CFG_DTT_HYSTERESIS		3
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
+#define CONFIG_MII
+
+#define CFG_TSEC1_OFFSET	0x24000
+#define CFG_TSEC1		(CFG_IMMRBAR + CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET	0x25000
+#define CFG_TSEC2		(CFG_IMMRBAR + CFG_TSEC2_OFFSET)
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+
+#define CONFIG_MPC83XX_TSEC1		1
+#define CONFIG_MPC83XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC83XX_TSEC2		1
+#define CONFIG_MPC83XX_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR			2
+#define TSEC2_PHY_ADDR			1
+#define TSEC1_PHYIDX			0
+#define TSEC2_PHYIDX			0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_PCI
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_PNP                  /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
+
+/* PCI1 host bridge */
+#define CFG_PCI1_MEM_BASE       0xc0000000
+#define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
+#define CFG_PCI1_IO_BASE        0xe2000000
+#define CFG_PCI1_IO_PHYS        CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE        0x1000000       /* 16M */
+
+
+#undef CONFIG_EEPRO100
+#define CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	CFG_PCI1_IO_BASE
+	#define PCI_ENET0_MEMADDR	CFG_PCI1_MEM_BASE
+	#define PCI_IDSEL_NUMBER	0x1c    /* slot0 (IDSEL) = 28 */
+#endif
+
+#define CFG_PCI_SUBSYS_VENDORID		0x1957  /* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#ifndef CFG_RAMBOOT
+	#define CFG_ENV_IS_IN_FLASH	1
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
+	#define CFG_ENV_SECT_SIZE	0x20000	/* 256K(one sector) for env */
+	#define CFG_ENV_SIZE		0x2000
+#else
+	#define CFG_NO_FLASH		1	/* Flash is not usable now */
+	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+	#define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE		1	/* allow baudrate change */
+
+/* Common commands */
+#define CFG_CMD_TQM8349_COMMON	CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\
+				| CFG_CMD_PING | CFG_CMD_EEPROM		\
+				| CFG_CMD_MII | CFG_CMD_JFFS2
+
+#if defined(CFG_RAMBOOT)
+
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PCI	\
+				| CFG_CMD_TQM8349_COMMON)	\
+				&				\
+				~(CFG_CMD_ENV | CFG_CMD_LOADS))
+#else
+#define  CONFIG_COMMANDS	((CONFIG_CMD_DFL		\
+				| CFG_CMD_TQM8349_COMMON)	\
+				&				\
+				~(CFG_CMD_ENV | CFG_CMD_LOADS))
+#endif
+
+#else /* CFG_RAMBOOT */
+
+#if defined(CONFIG_PCI)
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI	\
+				| CFG_CMD_TQM8349_COMMON)
+#else
+#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL			\
+				| CFG_CMD_TQM8349_COMMON)
+#endif
+
+#endif /* CFG_RAMBOOT */
+
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory	*/
+#define CFG_LOAD_ADDR		0x2000000	/* default load address */
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+#define CFG_HZ			1000		/* decrementer freq: 1ms ticks */
+
+#undef CONFIG_WATCHDOG				/* watchdog disabled */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/*
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#if defined(PCI_64BIT)
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_64_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#else
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII )
+#endif
+
+/* i-cache and d-cache disabled */
+#define CFG_HID0_INIT		0x000000000
+#define CFG_HID0_FINAL		CFG_HID0_INIT
+#define CFG_HID2		0x000000000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR		D2:DA:5E:44:BC:29
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		1E:F3:40:21:92:53
+#endif
+
+#define CONFIG_IPADDR		192.168.205.1
+
+#define CONFIG_HOSTNAME		tqm8349
+#define CONFIG_ROOTPATH		/opt/eldk/ppc_6xx
+#define CONFIG_BOOTFILE		/tftpboot/tqm83xx/uImage
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+#define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=tqm83xx\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=/tftpboot/tqm83xx/uImage\0"				\
+	"kernel_addr=80060000\0"					\
+	"ramdisk_addr=80160000\0"					\
+	"load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0"		\
+	"update=protect off 80000000 8003ffff; "			\
+		"era 80000000 8003ffff; cp.b 100000 80000000 40000\0"	\
+	"upd=run load;run update\0"					\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * JFFS2 partitions
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=TQM834x-0"
+
+/* default mtd partition table */
+#define MTDPARTS_DEFAULT	"mtdparts=TQM834x-0:256k(u-boot),128k(env),"\
+						"1m(kernel),2m(initrd),"\
+						"-(user);"\
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
new file mode 100755
index 0000000..16b2ce3
--- /dev/null
+++ b/include/configs/TQM850L.h
@@ -0,0 +1,434 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_TQM850L		1	/* ...on a TQM8xxL module	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM850L/uImage\0"				\
+	"kernel_addr=40040000\0"					\
+	"ramdisk_addr=40100000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
new file mode 100755
index 0000000..bbc6960
--- /dev/null
+++ b/include/configs/TQM850M.h
@@ -0,0 +1,433 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_TQM850M		1	/* ...on a TQM8xxM module	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM850M/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x08000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
new file mode 100755
index 0000000..198db19
--- /dev/null
+++ b/include/configs/TQM855L.h
@@ -0,0 +1,441 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
+#define CONFIG_TQM855L		1	/* ...on a TQM8xxL module	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM855L/uImage\0"				\
+	"kernel_addr=40040000\0"					\
+	"ramdisk_addr=40100000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC ETHERNET"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
new file mode 100755
index 0000000..e25a7a2
--- /dev/null
+++ b/include/configs/TQM855M.h
@@ -0,0 +1,476 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
+#define CONFIG_TQM855M		1	/* ...on a TQM8xxM module	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM855M/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
+
+#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SOFT_I2C */
+
+#define CFG_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C64	*/
+#define CFG_I2C_EEPROM_ADDR_LEN	2		/* two byte address	*/
+#if 0
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
+#define CFG_EEPROM_PAGE_WRITE_BITS	5
+#endif
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x08000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC ETHERNET"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
new file mode 100755
index 0000000..18197f2
--- /dev/null
+++ b/include/configs/TQM85xx.h
@@ -0,0 +1,452 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Wolfgang Denk <wd@denx.de>
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * TQM85xx (8560/40/55/41) board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE			*/
+#define CONFIG_E500		1	/* BOOKE e500 family		*/
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41		*/
+
+#define CONFIG_PCI
+#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
+
+#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
+
+/*
+ * Only MPC8540 doesn't have CPM module
+ */
+#ifndef CONFIG_MPC8540
+#define CONFIG_CPM2		1	/* has CPM2			*/
+#endif
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ *    33000000
+ *    66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz.  In any event, this value
+ * must match the settings of some switches.  Details can be found
+ * in the README.mpc85xxads.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	33333333
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache		*/
+#define CONFIG_BTB			/* toggle branch predition	*/
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming	*/
+
+#define CFG_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
+
+#undef	CFG_DRAM_TEST			/* memory test, takes time	*/
+#define CFG_MEMTEST_START	0x00000000
+#define CFG_MEMTEST_END		0x10000000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT	0xFF700000	/* CCSRBAR Default	*/
+#define CFG_CCSRBAR		0xE0000000	/* relocated CCSRBAR	*/
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	*/
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CONFIG_ADD_RAM_INFO	1		/* print additional info*/
+
+#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
+/* TQM8540 & 8560 need DLL-override */
+#define CONFIG_DDR_DLL				/* DLL fix needed	*/
+#define CONFIG_DDR_DEFAULT_CL	25		/* CAS latency 2,5	*/
+#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */
+
+#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
+#define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/
+#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */
+
+/*
+ * Flash on the Local Bus
+ */
+#define CFG_FLASH0		0xFC000000
+#define CFG_FLASH1		0xF8000000
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH1, CFG_FLASH0 }
+
+#define CFG_LBC_FLASH_BASE	CFG_FLASH1	/* Localbus flash start	*/
+#define CFG_FLASH_BASE		CFG_LBC_FLASH_BASE /* start of FLASH	*/
+
+#define CFG_BR0_PRELIM		0xfc001801	/* port size 32bit	*/
+#define CFG_OR0_PRELIM		0xfc000040	/* 64MB Flash		*/
+#define CFG_BR1_PRELIM		0xf8001801	/* port size 32bit	*/
+#define CFG_OR1_PRELIM		0xfc000040	/* 64MB Flash		*/
+
+#define CFG_FLASH_CFI				/* flash is CFI compat.	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
+
+#define CFG_MAX_FLASH_BANKS	2		/* number of banks	*/
+#define CFG_MAX_FLASH_SECT	512		/* sectors per device	*/
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/
+
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
+
+#define CFG_LBC_LCRR		0x00030008    /* LB clock ratio reg	*/
+#define CFG_LBC_LBCR		0x00000000    /* LB config reg		*/
+#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
+#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x4000		/* End used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256kB for Mon*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc	*/
+
+/* Serial Port */
+#if defined(CONFIG_TQM8560)
+
+#define CONFIG_CONS_ON_SCC      /* define if console on SCC */
+#undef  CONFIG_CONS_NONE        /* define if console on something else */
+#define CONFIG_CONS_INDEX       1  /* which serial channel for console */
+
+#else
+
+#define CONFIG_CONS_INDEX     1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
+
+#endif /* CONFIG_TQM8560 */
+
+#define CONFIG_BAUDRATE         115200
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x48}	/* Don't probe these addrs	*/
+
+/* I2C RTC */
+#define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
+#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
+
+/* I2C EEPROM */
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x		*/
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write	*/
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CFG_I2C_MULTI_EEPROMS		1       /* more than one eeprom */
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define CFG_DTT_HYSTERESIS	3
+
+/* RapidIO MMU */
+#define CFG_RIO_MEM_BASE	0xc0000000	/* base address		*/
+#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M			*/
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
+#define CFG_PCI1_IO_BASE	0xe2000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M			*/
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+
+#define CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola			*/
+
+#endif	/* CONFIG_PCI */
+
+
+#define CONFIG_NET_MULTI	1
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define FEC_PHY_ADDR		3
+#define FEC_PHYIDX		0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+
+/* Options are TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#if defined(CONFIG_TQM8540)
+/*
+ * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
+ * The FEC port is connected on the same signals as the FCC3 port
+ * of the TQM8560 to the baseboard (STK85xx Starterkit).
+ *
+ * On the STK85xx Starterkit the X47/X50 jumper has to be set to
+ * a - d (X50.2 - 3) to enable the FEC port.
+ */
+#define CONFIG_MPC85XX_FEC	1
+#define CONFIG_MPC85XX_FEC_NAME	"FEC"
+#endif
+
+#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
+/*
+ * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
+ * can be used at once, since only one FCC port is available on the STK85xx
+ * Starterkit.
+ *
+ * To use this port you have to configure U-Boot to use the FCC port 1...2
+ * and set the X47/X50 jumper to:
+ * FCC1: a - b (X47.2 - X50.2)
+ * FCC2: a - c (X50.2 - 1)
+ */
+#define CONFIG_ETHER_ON_FCC
+#define	CONFIG_ETHER_INDEX    1		/* FCC channel for ethernet	*/
+#endif
+
+#if defined(CONFIG_TQM8560)
+/*
+ * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
+ * can be used at once, since only one FCC port is available on the STK85xx
+ * Starterkit.
+ *
+ * To use this port you have to configure U-Boot to use the FCC port 1...3
+ * and set the X47/X50 jumper to:
+ * FCC1: a - b (X47.2 - X50.2)
+ * FCC2: a - c (X50.2 - 1)
+ * FCC3: a - d (X50.2 - 3)
+ */
+#define CONFIG_ETHER_ON_FCC
+#define	CONFIG_ETHER_INDEX    3		/* FCC channel for ethernet	*/
+#endif
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
+#define CONFIG_ETHER_ON_FCC1
+#define CFG_CMXFCR_MASK1	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+#define CFG_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#endif
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+#define CONFIG_ETHER_ON_FCC2
+#define CFG_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#endif
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
+#define CONFIG_ETHER_ON_FCC3
+#define CFG_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#endif
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x20000)
+#define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env	*/
+#define CFG_ENV_SIZE		0x2000
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with ts	*/
+
+#if defined(CONFIG_PCI)
+# define ADD_PCI_CMD		(CFG_CMD_PCI)
+#else
+# define ADD_PCI_CMD		0
+#endif
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_NFS	| \
+				 CFG_CMD_SNTP	| \
+				 ADD_PCI_CMD	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_DATE	| \
+				 CFG_CMD_EEPROM	| \
+				 CFG_CMD_DTT	| \
+				 CFG_CMD_MII	| \
+				 CFG_CMD_PING	)
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_LOAD_ADDR	0x2000000	/* default load address		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+    #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size	*/
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use	*/
+#endif
+
+
+#define CONFIG_LOADADDR	 200000		/* default addr for tftp & bootm*/
+
+#define CONFIG_BOOTDELAY 5		/* -1 disables auto-boot	*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs	*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CFG_BOOTFILE							\
+	"netdev=eth0\0"							\
+	"consdev=ttyS0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$serverip:$rootpath\0"				\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $bootargs "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
+		":$hostname:$netdev:off panic=1\0"			\
+	"addcons=setenv bootargs $bootargs "				\
+		"console=$consdev,$baudrate\0"				\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm $kernel_addr\0"					\
+	"flash_self=run ramargs addip addcons;"				\
+		"bootm $kernel_addr $ramdisk_addr\0"			\
+	"net_nfs=tftp $loadaddr $bootfile;"				\
+		"run nfsargs addip addcons;bootm\0"			\
+	"rootpath=/opt/eldk/ppc_85xx\0"					\
+	"kernel_addr=FE000000\0"					\
+	"ramdisk_addr=FE100000\0"					\
+	"load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0"		\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
new file mode 100755
index 0000000..4a1a432
--- /dev/null
+++ b/include/configs/TQM860L.h
@@ -0,0 +1,444 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
+#define CONFIG_TQM860L		1	/* ...on a TQM8xxL module	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM860L/uImage\0"				\
+	"kernel_addr=40040000\0"					\
+	"ramdisk_addr=40100000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+#define CONFIG_NETCONSOLE
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC ETHERNET"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
new file mode 100755
index 0000000..4b754ba
--- /dev/null
+++ b/include/configs/TQM860M.h
@@ -0,0 +1,443 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
+#define CONFIG_TQM860M		1	/* ...on a TQM8xxM module	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM860M/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x08000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC ETHERNET"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
new file mode 100755
index 0000000..1dc9f74
--- /dev/null
+++ b/include/configs/TQM862L.h
@@ -0,0 +1,447 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1
+#define CONFIG_MPC860T		1
+#define CONFIG_MPC862		1
+
+#define CONFIG_TQM862L		1	/* ...on a TQM8xxL module	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM862L/uImage\0"				\
+	"kernel_addr=40040000\0"					\
+	"ramdisk_addr=40100000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ *  50 MHz =>  50.000.000 / Divider =  98
+ *  66 Mhz =>  66.000.000 / Divider = 129
+ *  80 Mhz =>  80.000.000 / Divider = 156
+ * 100 Mhz => 100.000.000 / Divider = 195
+ */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_NET_MULTI
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC ETHERNET"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
new file mode 100755
index 0000000..3df060c
--- /dev/null
+++ b/include/configs/TQM862M.h
@@ -0,0 +1,448 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1
+#define CONFIG_MPC860T		1
+#define CONFIG_MPC862		1
+
+#define CONFIG_TQM862M		1	/* ...on a TQM8xxM module	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM862M/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+
+#define	CFG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x08000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ *  50 MHz =>  50.000.000 / Divider =  98
+ *  66 Mhz =>  66.000.000 / Divider = 129
+ *  80 Mhz =>  80.000.000 / Divider = 156
+ * 100 Mhz => 100.000.000 / Divider = 195
+ */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_NET_MULTI
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC ETHERNET"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
new file mode 100755
index 0000000..8f9c2c9
--- /dev/null
+++ b/include/configs/TQM866M.h
@@ -0,0 +1,461 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC866		1	/* This is a MPC866 CPU		*/
+#define CONFIG_TQM866M		1	/* ...on a TQM8xxM module	*/
+
+#define CONFIG_8xx_OSCLK		10000000	/*  10 MHz - PLL input clock	*/
+#define CFG_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
+#define CFG_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
+#define CONFIG_8xx_CPUCLK_DEFAULT	50000000	/*  50 MHz - CPU default clock	*/
+						/* (it will be used if there is no	*/
+						/* 'cpuclk' variable with valid value)	*/
+
+#undef CFG_MEASURE_CPUCLK			/* Measure real cpu clock	*/
+						/* (function measure_gclk()	*/
+						/* will be called)		*/
+#ifdef CFG_MEASURE_CPUCLK
+#define CFG_8XX_XIN		10000000	/* measure_gclk() needs this	*/
+#endif
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM866M/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+
+#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SOFT_I2C */
+
+#define CFG_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C256	*/
+#define CFG_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef CONFIG_RTC_MPC8xx		/* MPC866 does not support RTC	*/
+
+#define	CONFIG_TIMESTAMP		/* but print image timestmps	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
+#define CFG_ENV_SIZE		0x08000 /* Total Size of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	0x20000 /* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing: Default value of OR0 after reset
+ */
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
+				 OR_SCY_15_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define SDRAM_MAX_SIZE		(256 << 20)	/* max 256 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef CONFIG_CAN_DRIVER
+#define CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * 4096	Rows from SDRAM example configuration
+ * 1000	factor s -> ms
+ * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4	Number of refresh cycles per period
+ * 64	Refresh cycle in ms per number of rows
+ */
+#define CFG_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
+
+/*
+ * Memory Periodic Timer Prescaler
+ * Periodic timer for refresh, start with refresh rate for 40 MHz clock
+ * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
+ */
+#define CFG_MAMR_PTA		39
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 10 column SDRAM */
+#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC ETHERNET"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h
new file mode 100755
index 0000000..8175703
--- /dev/null
+++ b/include/configs/Total5200.h
@@ -0,0 +1,415 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Check valid setting of revision define.
+ * Total5100 and Total5200 Rev.1 are identical except for the processor.
+ */
+#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
+#error CONFIG_TOTAL5200_REV must be 1 or 2
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_TOTAL5200	1	/* ... on Total5200 board */
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Video console
+ */
+#if 1
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SED13806
+#define CONFIG_VIDEO_SED13806_16BPP
+
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+/* #define CONFIG_VIDEO_BMP_LOGO */
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+
+#define ADD_VIDEO_CMD	CFG_CMD_BMP
+#else
+#define ADD_VIDEO_CMD	0
+#endif
+
+#ifdef CONFIG_MPC5200	/* MGT5100 PCI is not supported yet. */
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_MII		1
+#define CONFIG_EEPRO100		1
+#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X		1
+
+#define ADD_PCI_CMD 		CFG_CMD_PCI
+
+#else	/* MGT5100 */
+
+#define CONFIG_MII		1
+#define ADD_PCI_CMD		0  /* no CFG_CMD_PCI */
+
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 1
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD             0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_EEPROM	| \
+				 CFG_CMD_FAT	| \
+				 CFG_CMD_IDE	| \
+				 ADD_VIDEO_CMD  | \
+				 ADD_PCI_CMD	| \
+				 ADD_USB_CMD)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if (TEXT_BASE == 0xFE000000)		/* Boot low */
+#   define CFG_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	\
+	"setenv stdout serial;setenv stderr serial;" \
+	"echo;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/MPC5200/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#if CONFIG_TOTAL5200_REV==2
+#   define CFG_MAX_FLASH_BANKS	3	/* max num of flash banks */
+#   define CFG_FLASH_BANKS_LIST { CFG_CS5_START, CFG_CS4_START, CFG_BOOTCS_START }
+#else
+#   define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks  */
+#   define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
+#endif
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#if CONFIG_TOTAL5200_REV==1
+#   define CFG_FLASH_BASE	0xFE000000
+#   define CFG_FLASH_SIZE	0x02000000
+#elif CONFIG_TOTAL5200_REV==2
+#   define CFG_FLASH_BASE	0xFA000000
+#   define CFG_FLASH_SIZE	0x06000000
+#endif /* CONFIG_TOTAL5200_REV */
+
+#if defined(CFG_LOWBOOT)
+#   define CFG_ENV_ADDR		0xFE040000
+#else	/* CFG_LOWBOOT */
+#   define CFG_ENV_ADDR		0xFFF40000
+#endif	/* CFG_LOWBOOT */
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x40000
+#define CFG_ENV_SECT_SIZE	0x40000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+#define CFG_MBAR		0xF0000000	/*   64 kB */
+#define CFG_FPGA_BASE		0xF0010000	/*   64 kB */
+#define CFG_CPLD_BASE		0xF0020000	/*   64 kB */
+#define CFG_LCD_BASE		0xF1000000	/* 4096 kB */
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/* dummy, 7-wire FEC does not have phy address */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ *
+ * CS1:   SDRAM CS1 disabled, gpio_wkup_6 enabled                0
+ * Reserved                                                      0
+ * ALTs:  CAN1/2 on PSC2, SPI on PSC3                            00
+ * CS7:   Interrupt GPIO on PSC3_5                               0
+ * CS8:   Interrupt GPIO on PSC3_4                               0
+ * ATA:   reset default, changed in ATA driver                   00
+ * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO       0
+ * IRDA:  reset default, changed in IrDA driver                  000
+ * ETHER: reset default, changed in Ethernet driver              0000
+ * PCI_DIS: reset default, changed in PCI driver                 0
+ * USB_SE: reset default, changed in USB driver                  0
+ * USB:   reset default, changed in USB driver                   00
+ * PSC3:  SPI and UART functionality without CD                  1100
+ * Reserved                                                      0
+ * PSC2:  CAN1/2                                                 001
+ * Reserved                                                      0
+ * PSC1:  reset default, changed in AC'97 driver                 000
+ *
+ */
+#define CFG_GPS_PORT_CONFIG	0x00000C10
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#if defined (CONFIG_MGT5100)
+#   define CONFIG_BOARD_EARLY_INIT_R	/* switch from CS_BOOT to CS0 */
+#endif
+
+#if CONFIG_TOTAL5200_REV==1
+#   define CFG_BOOTCS_START	CFG_FLASH_BASE
+#   define CFG_BOOTCS_SIZE	0x02000000	/* 32 MB */
+#   define CFG_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#   define CFG_CS0_START	CFG_FLASH_BASE
+#   define CFG_CS0_SIZE		0x02000000	/* 32 MB */
+#else
+#   define CFG_BOOTCS_START	(CFG_CS4_START + CFG_CS4_SIZE)
+#   define CFG_BOOTCS_SIZE	0x02000000	/* 32 MB */
+#   define CFG_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#   define CFG_CS4_START	(CFG_CS5_START + CFG_CS5_SIZE)
+#   define CFG_CS4_SIZE		0x02000000	/* 32 MB */
+#   define CFG_CS4_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#   define CFG_CS5_START	CFG_FLASH_BASE
+#   define CFG_CS5_SIZE		0x02000000	/* 32 MB */
+#   define CFG_CS5_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#endif
+
+#define CFG_CS1_START		CFG_FPGA_BASE
+#define CFG_CS1_SIZE		0x00010000	/* 64 kB */
+#define CFG_CS1_CFG		0x0019FF00	/* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
+
+#define CFG_CS2_START		CFG_LCD_BASE
+#define CFG_CS2_SIZE		0x00400000	/* 4096 kB */
+#define CFG_CS2_CFG		0x0032FD0C	/* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
+
+#if CONFIG_TOTAL5200_REV==1
+#   define CFG_CS3_START	CFG_CPLD_BASE
+#   define CFG_CS3_SIZE		0x00010000	/* 64 kB */
+#   define CFG_CS3_CFG		0x000ADF00	/* 10WS, MX, AL, CE, AS_25, DS_32 */
+#else
+#   define CFG_CS3_START	CFG_CPLD_BASE
+#   define CFG_CS3_SIZE		0x00010000	/* 64 kB */
+#   define CFG_CS3_CFG		0x000AD800	/* 10WS, MX, AL, CE, AS_24, DS_8 */
+#endif
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers                                                */
+#define CFG_ATA_STRIDE          4
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
new file mode 100755
index 0000000..3f29190
--- /dev/null
+++ b/include/configs/VCMA9.h
@@ -0,0 +1,284 @@
+/*
+ * (C) Copyright 2002, 2003
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * Configuation settings for the MPL VCMA9 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
+#define	CONFIG_S3C2410		1	/* in a SAMSUNG S3C2410 SoC     */
+#define CONFIG_VCMA9		1	/* on a MPL VCMA9 Board  */
+#define LITTLEENDIAN		1	/* used by usb_ohci.c		*/
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ	12000000/* VCMA9 has 12MHz input clock	*/
+
+#define USE_920T_MMU		1
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs    	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#define CONFIG_COMMANDS \
+			(CONFIG_CMD_DFL	 | \
+			CFG_CMD_CACHE	 | \
+			/*CFG_CMD_JFFS2	 |*/ \
+			/*CFG_CMD_NAND	 |*/ \
+			CFG_CMD_EEPROM	 | \
+			CFG_CMD_I2C	 | \
+			CFG_CMD_USB	 | \
+			CFG_CMD_REGINFO  | \
+			CFG_CMD_FAT	 | \
+			CFG_CMD_DATE	 | \
+			CFG_CMD_ELF	 | \
+			CFG_CMD_DHCP	 | \
+			CFG_CMD_PING	 | \
+			CFG_CMD_BSP)
+
+/* this must be included after the definiton of CONFIG_COMMANDS */
+#include <cmd_confdefs.h>
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+/***********************************************************
+ * I2C stuff:
+ * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
+ * address 0x50 with 16bit addressing
+ ***********************************************************/
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#define CFG_I2C_SPEED 		100000	/* I2C speed */
+#define CFG_I2C_SLAVE 		0x7F	/* I2C slave addr */
+
+#define CFG_I2C_EEPROM_ADDR	0x50
+#define CFG_I2C_EEPROM_ADDR_LEN	2
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at offset 0 */
+#define CFG_ENV_SIZE		0x800	/* 2KB should be more than enough */
+
+#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#define CFG_EEPROM_PAGE_WRITE_BITS 6	/* 64 bytes page write mode on 24C256 */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/*
+ * Size of malloc() pool
+ */
+/*#define CONFIG_MALLOC_SIZE	(CFG_ENV_SIZE + 128*1024)*/
+#define CFG_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
+
+#define CFG_MONITOR_LEN		(256 * 1024)
+#define CFG_MALLOC_LEN		(1024 * 1024)	/* BUNZIP2 needs a lot of RAM */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900	1		/* we have a CS8900 on-board */
+#define CS8900_BASE		0x20000300
+#define CS8900_BUS16		1 		/* the Linux driver does accesses as shorts */
+
+#define CONFIG_DRIVER_S3C24X0_I2C	1	/* we use the buildin I2C controller */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on VCMA9 */
+
+/************************************************************
+ * USB support
+ ************************************************************/
+#define CONFIG_USB_OHCI		1
+#define CONFIG_USB_KEYBOARD	1
+#define CONFIG_USB_STORAGE	1
+#define CONFIG_DOS_PARTITION	1
+
+/* Enable needed helper functions */
+#define CFG_DEVICE_DEREGISTER		/* needs device_deregister */
+
+/************************************************************
+ * RTC
+ ************************************************************/
+#define	CONFIG_RTC_S3C24X0	1
+
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_BOOTDELAY	5
+/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
+/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
+#define CONFIG_ZERO_BOOTDELAY_CHECK  	/* check console even if bootdelay = 0 */
+
+#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_IPADDR		10.0.0.110
+#define CONFIG_SERVERIP		10.0.0.1
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"VCMA9 # "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x30F80000	/* 15.5 MB in DRAM	*/
+
+#define CFG_ALT_MEMTEST
+#define	CFG_LOAD_ADDR		0x30800000	/* default load address	*/
+
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+/* we configure PWM Timer 4 to 1us ~ 1MHz */
+/*#define	CFG_HZ			1000000 */
+#define	CFG_HZ			1562500
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* support BZIP2 compression */
+#define CONFIG_BZIP2		1
+
+/************************************************************
+ * Ident
+ ************************************************************/
+/*#define VERSION_TAG "released"*/
+#define VERSION_TAG "unstable"
+#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CONFIG_AMD_LV400	1	/* uncomment this if you have a LV400 flash */
+#if 0
+#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
+#endif
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#ifdef CONFIG_AMD_LV800
+#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
+#define CFG_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
+#endif
+#ifdef CONFIG_AMD_LV400
+#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
+#define CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x070000) /* addr of environment */
+#endif
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+
+#if 0
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
+#endif
+
+
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	1
+
+#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
+
+/*-----------------------------------------------------------------------
+ * NAND flash settings
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define NAND_WAIT_READY(nand)	NF_WaitRB()
+
+#define NAND_DISABLE_CE(nand)	NF_SetCE(NFCE_HIGH)
+#define NAND_ENABLE_CE(nand)	NF_SetCE(NFCE_LOW)
+
+
+#define WRITE_NAND_COMMAND(d, adr)	NF_Cmd(d)
+#define WRITE_NAND_COMMANDW(d, adr)	NF_CmdW(d)
+#define WRITE_NAND_ADDRESS(d, adr)	NF_Addr(d)
+#define WRITE_NAND(d, adr)		NF_Write(d)
+#define READ_NAND(adr)			NF_Read()
+/* the following functions are NOP's because S3C24X0 handles this in hardware */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+
+#define CONFIG_MTD_NAND_VERIFY_WRITE	1
+#define CONFIG_MTD_NAND_ECC_JFFS2	1
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_NAND */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h
new file mode 100755
index 0000000..3ca137e
--- /dev/null
+++ b/include/configs/VOH405.h
@@ -0,0 +1,457 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_VOH405		1	/* ...on a VOH405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_EEPROM	)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
+#define CFG_BASE_BAUD       691200
+#define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
+
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CFG_IDE_MAXBUS		2		/* max. 2 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+#define CONFIG_ATAPI		1	/* ATAPI for Travelstar		*/
+
+#define CFG_ATA_BASE_ADDR	0xF0100000
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_IDE1_OFFSET	0x0010
+
+#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CFG_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CFG_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFF80000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(2 * 1024*1024)	/* Reserve 2 MB for malloc()	*/
+
+#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CFG_RAMBOOT		1
+#else
+# undef CFG_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
+#if 0 /* test-only */
+/* CAT24WC08/16... */
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#else
+/* CAT24WC32/64... */
+#define CFG_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CFG_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+					/* 32 byte page write mode using*/
+					/* last 5 bits of the address	*/
+#endif
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
+#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
+#define VGA_BA		0xF1000000	    /* Epson VGA Base Address		*/
+#define CFG_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address		*/
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (Epson VGA) initialization					*/
+#define CFG_EBC_PB4AP	0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
+#define CFG_EBC_PB4CR	VGA_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * LCD Setup
+ */
+
+#define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
+#define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
+#define CFG_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
+#define CFG_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
+
+#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+
+#define CFG_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address	*/
+
+/* FPGA internal regs */
+#define CFG_FPGA_CTRL		0x000
+
+/* FPGA Control Reg */
+#define CFG_FPGA_CTRL_CF_RESET	0x0001
+#define CFG_FPGA_CTRL_WDI	0x0002
+#define CFG_FPGA_CTRL_PS2_RESET 0x0020
+
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
+ */
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+#define CFG_GPIO0_ISR1L		0x15555440
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FE0017
+
+#define CFG_DUART_RST		(0x80000000 >> 14)
+#define CFG_LCD_ENDIAN		(0x80000000 >> 7)
+#define CFG_LCD0_RST		(0x80000000 >> 30)
+#define CFG_LCD1_RST		(0x80000000 >> 31)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
new file mode 100755
index 0000000..f2f3ea7
--- /dev/null
+++ b/include/configs/VOM405.h
@@ -0,0 +1,343 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_VOM405		1	/* ...on a VOM405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_NET_MULTI	1
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_DNS | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME )
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_EEPROM	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+#undef  CONFIG_PRAM			/* no "protected RAM"           */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#undef	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CFG_RAMBOOT		1
+#else
+# undef CFG_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
+#define CFG_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CFG_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
+#define CFG_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+/* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
+/* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
+/* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
+/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
+#define CFG_GPIO0_OSRH		0x40000500  /*	0 ... 15 */
+#define CFG_GPIO0_OSRL		0x00000110  /* 16 ... 31 */
+#define CFG_GPIO0_ISR1H		0x00000000  /*	0 ... 15 */
+#define CFG_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
+#define CFG_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
+#define CFG_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
+#define CFG_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h
new file mode 100755
index 0000000..92bade5
--- /dev/null
+++ b/include/configs/VoVPN-GW.h
@@ -0,0 +1,406 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* define cpu used */
+#define	CONFIG_MPC8272			1
+
+/* define busmode: 8260 */
+#undef	CONFIG_BUSMODE_60x
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#ifdef	CONFIG_CLKIN_66MHz
+#define	CONFIG_8260_CLKIN		66666666	/* in Hz */
+#else
+#define	CONFIG_8260_CLKIN		100000000	/* in Hz */
+#endif
+
+/* call board_early_init_f */
+#define	CONFIG_BOARD_EARLY_INIT_F	1
+
+/* have misc_init_r() function */
+#define CONFIG_MISC_INIT_R		1
+
+/* have reset_phy_r() function */
+#define CONFIG_RESET_PHY_R		1
+
+/* have special reset function */
+#define	CONFIG_HAVE_OWN_RESET		1
+
+/* allow serial and ethaddr to be overwritten */
+#define	CONFIG_ENV_OVERWRITE
+
+/* watchdog disabled */
+#undef	CONFIG_WATCHDOG
+
+/* include support for bzip2 compressed images */
+#undef	CONFIG_BZIP2
+
+/* status led */
+#undef	CONFIG_STATUS_LED		/* XXX jse */
+
+/* vendor parameter protection */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC
+#undef	CONFIG_CONS_ON_SCC
+#undef	CONFIG_CONS_NONE
+#define	CONFIG_CONS_INDEX		1
+
+/* serial port default baudrate */
+#define CONFIG_BAUDRATE			115200
+
+/* echo on for serial download	*/
+#define CONFIG_LOADS_ECHO		1
+
+/* don't allow baudrate change	*/
+#undef	CFG_LOADS_BAUD_CHANGE
+
+/* supported baudrates */
+#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC
+#define	CONFIG_ETHER_ON_FCC
+#undef	CONFIG_ETHER_NONE
+
+#ifdef	CONFIG_ETHER_ON_FCC
+
+/* which SCC/FCC channel for ethernet */
+#define	CONFIG_ETHER_INDEX		1
+
+/* Marvell Switch SMI base addr */
+#define CFG_PHY_ADDR			0x10
+
+/* FCC1 RMII REFCLK is CLK10 */
+#define CFG_CMXFCR_VALUE		CMXFCR_TF1CS_CLK10
+#define CFG_CMXFCR_MASK			(CMXFCR_FC1|CMXFCR_TF1CS_MSK)
+
+/* BDs and buffers on 60x bus */
+#define CFG_CPMFCR_RAMTYPE		0
+
+/* Local Protect, Full duplex, Flowcontrol, RMII */
+#define CFG_FCC_PSMR			(FCC_PSMR_LPB|FCC_PSMR_FDE|\
+					 FCC_PSMR_FCE|FCC_PSMR_RMII)
+
+/* bit-bang MII PHY management	*/
+#define CONFIG_BITBANGMII
+
+#define MDIO_PORT			1		/* Port B */
+#define CFG_MDIO_PIN			0x00002000	/* PB18 */
+#define CFG_MDC_PIN			0x00001000	/* PB19 */
+#define MDIO_ACTIVE			(iop->pdir |=  CFG_MDIO_PIN)
+#define MDIO_TRISTATE			(iop->pdir &= ~CFG_MDIO_PIN)
+#define MDIO_READ			((iop->pdat &  CFG_MDIO_PIN) != 0)
+#define MDIO(bit)			if(bit) iop->pdat |=  CFG_MDIO_PIN; \
+					else	iop->pdat &= ~CFG_MDIO_PIN
+#define MDC(bit)			if(bit) iop->pdat |=  CFG_MDC_PIN; \
+					else	iop->pdat &= ~CFG_MDC_PIN
+#define MIIDELAY			udelay(1)
+
+#endif
+
+/* configure commands */
+#define CONFIG_COMMANDS		(	CFG_CMD_AUTOSCRIPT	| \
+					CFG_CMD_BDI		| \
+					CFG_CMD_CONSOLE		| \
+					CFG_CMD_ECHO		| \
+					CFG_CMD_ENV		| \
+					CFG_CMD_FLASH		| \
+					CFG_CMD_IMI		| \
+					CFG_CMD_IMLS		| \
+					CFG_CMD_LOADB		| \
+					CFG_CMD_MEMORY		| \
+					CFG_CMD_MISC		| \
+					CFG_CMD_NET		| \
+					CFG_CMD_PING		| \
+					CFG_CMD_RUN	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * boot options & environment
+ */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTCOMMAND		"run flash_self"
+#undef  CONFIG_BOOTARGS
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+"clean_nv=erase fff20000 ffffffff\0" \
+"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
+"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
+"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
+"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
+"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
+"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
+"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
+"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
+"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
+"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
+"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
+"fstype=cramfs\0" \
+"rootpath=/root_fs\0" \
+"uboot=PPC/u-boot.bin\0" \
+"kernel=PPC/uImage\0" \
+"kernel_addr=ffe00000\0" \
+"fs=PPC/root_fs\0" \
+"console=ttyS0\0" \
+"netdev=eth0\0" \
+"rootdev=31:3\0" \
+"ethaddr=00:09:4f:01:02:03\0" \
+"ipaddr=10.0.0.201\0" \
+"netmask=255.255.255.0\0" \
+"serverip=10.0.0.136\0" \
+"gatewayip=10.0.0.10\0" \
+"hostname=bastard\0" \
+""
+
+
+/*
+ * miscellaneous configurable options
+ */
+
+/* undef to save memory */
+#define	CFG_LONGHELP
+
+/* monitor command prompt */
+#define	CFG_PROMPT			"=> "
+
+/* console i/o buffer size */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE			1024
+#else
+#define	CFG_CBSIZE			256
+#endif
+
+/* print buffer size */
+#define	CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+/* max number of command args */
+#define	CFG_MAXARGS			16
+
+/* boot argument buffer size */
+#define CFG_BARGSIZE			CFG_CBSIZE
+
+/* memtest works on */
+#define CFG_MEMTEST_START		0x00100000
+/* 1 ... 15 MB in DRAM */
+#define CFG_MEMTEST_END			0x00f00000
+/* full featured memtest */
+#define CFG_ALT_MEMTEST
+
+/* default load address */
+#define	CFG_LOAD_ADDR			0x00100000
+
+/* decrementer freq: 1 ms ticks	*/
+#define	CFG_HZ				1000
+
+/* configure flash */
+#define CFG_FLASH_BASE			0xff800000
+#define CFG_MAX_FLASH_BANKS		1
+#define CFG_MAX_FLASH_SECT		64
+#define CFG_FLASH_SIZE			8
+#undef	CFG_FLASH_16BIT
+#define CFG_FLASH_ERASE_TOUT		240000
+#define CFG_FLASH_WRITE_TOUT		500
+#define CFG_FLASH_LOCK_TOUT		500
+#define CFG_FLASH_UNLOCK_TOUT		10000
+#define CFG_FLASH_PROTECTION
+
+/* monitor in flash */
+#define CFG_MONITOR_OFFSET		0x00700000
+
+/* environment in flash */
+#define CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_ADDR			(CFG_FLASH_BASE + 0x00020000)
+#define CFG_ENV_SIZE			0x00020000
+#define CFG_ENV_SECT_SIZE		0x00020000
+
+/*
+ * Initial memory map for linux
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ			(8 << 20)
+
+/* hard reset configuration words */
+#ifdef	CONFIG_CLKIN_66MHz
+#define CFG_HRCW_MASTER			0x04643050
+#else
+#error NO HRCW FOR 100MHZ SPECIFIED !!!
+#endif
+#define CFG_HRCW_SLAVE1			0x00000000
+#define CFG_HRCW_SLAVE2			0x00000000
+#define CFG_HRCW_SLAVE3			0x00000000
+#define CFG_HRCW_SLAVE4			0x00000000
+#define CFG_HRCW_SLAVE5			0x00000000
+#define CFG_HRCW_SLAVE6			0x00000000
+#define CFG_HRCW_SLAVE7			0x00000000
+
+/* internal memory mapped register */
+#define CFG_IMMR			0xF0000000
+
+/* definitions for initial stack pointer and data area (in DPRAM) */
+#define CFG_INIT_RAM_ADDR		CFG_IMMR
+#define CFG_INIT_RAM_END		0x2000
+#define CFG_GBL_DATA_SIZE		128
+#define CFG_GBL_DATA_OFFSET		(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET		CFG_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE			0x00000000
+#define CFG_SDRAM_SIZE			(32*1024*1024)
+#define CFG_MONITOR_BASE		TEXT_BASE
+#define CFG_MONITOR_FLASH		(CFG_FLASH_BASE + CFG_MONITOR_OFFSET)
+#define CFG_MONITOR_LEN			0x00020000
+#define CFG_MALLOC_LEN			0x00020000
+
+/* boot flags */
+#define BOOTFLAG_COLD			0x01	/* normal power-on */
+#define BOOTFLAG_WARM			0x02	/* software reboot */
+
+/* cache configuration */
+#define CFG_CACHELINE_SIZE		32      /* for MPC8260 */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT		5	/* log base 2 of above */
+#endif
+
+/*
+ * HIDx - Hardware Implementation-dependent Registers
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT			(HID0_ICE|HID0_DCE|\
+					 HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL			(HID0_IFEM|HID0_ABE)
+#define CFG_HID2			0
+
+/* RMR - reset mode register - turn on checkstop reset enable */
+#define CFG_RMR				RMR_CSRE
+
+/* BCR - bus configuration */
+#define CFG_BCR				0x00000000
+
+/* SIUMCR - siu module configuration */
+#define CFG_SIUMCR			0x4905c000
+
+/* SYPCR - system protection control */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR			0xffffff87
+#else
+#define CFG_SYPCR			0xffffff83
+#endif
+
+/* TMCNTSC - time counter status and control */
+/* clear interrupts XXX jse */
+/*#define CFG_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR) */
+#define CFG_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR|\
+					 TMCNTSC_TCF|TMCNTSC_TCE)
+
+/* PISCR - periodic interrupt status and control */
+/* clear interrupts XXX jse */
+/*#define CFG_PISCR			(PISCR_PS) */
+#define CFG_PISCR			(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/* SCCR - system clock control */
+#define CFG_SCCR			0x000001a9
+
+/* RCCR - risc controller configuration */
+#define CFG_RCCR			0
+
+/*
+ * MEMORY MAP
+ * ----------
+ * CS0 - FLASH    8MB/8Bit 	base=0xff800000 (boot: 0xfe000000, 8x mirrored)
+ * CS1 - SDRAM   32MB/64Bit	base=0x00000000
+ * CS2 - DSP/SL1  1MB/16Bit	base=0xf0100000
+ * CS3 - DSP/SL2  1MB/16Bit	base=0xf0200000
+ * CS4 - DSP/SL3  1MB/16Bit	base=0xf0300000
+ * CS5 - DSP/SL4  1MB/16Bit	base=0xf0400000
+ * CS7 - DPRAM    1KB/8Bit	base=0xf0500000, size=32KB (32x mirrored)
+ *  x  - IMMR     384KB		base=0xf0000000
+ */
+/* XXX jse 100MHz TODO */
+#define CFG_BR0_PRELIM			0xff800801
+#define CFG_OR0_PRELIM			0xff801e44
+#define CFG_BR1_PRELIM			0x00000041
+#define CFG_OR1_PRELIM			0xfe002ec0
+#if 1
+#define CFG_BR2_PRELIM			0xf0101001
+#define CFG_OR2_PRELIM			0xfff00ef4
+#define CFG_BR3_PRELIM			0xf0201001
+#define CFG_OR3_PRELIM			0xfff00ef4
+#define CFG_BR4_PRELIM			0xf0301001
+#define CFG_OR4_PRELIM			0xfff00ef4
+#define CFG_BR5_PRELIM			0xf0401001
+#define CFG_OR5_PRELIM			0xfff00ef4
+#else
+#define CFG_BR2_PRELIM			0xf0101081
+#define CFG_OR2_PRELIM			0xfff00104
+#define CFG_BR3_PRELIM			0xf0201081
+#define CFG_OR3_PRELIM			0xfff00104
+#define CFG_BR4_PRELIM			0xf0301081
+#define CFG_OR4_PRELIM			0xfff00104
+#define CFG_BR5_PRELIM			0xf0401081
+#define CFG_OR5_PRELIM			0xfff00104
+#endif
+#define CFG_BR7_PRELIM			0xf0500881
+#define CFG_OR7_PRELIM			0xffff8104
+#define CFG_MPTPR			0x2700
+#define CFG_PSDMR			0x822a2452	/* optimal */
+/*#define CFG_PSDMR			0x822a48a3 */	/* relaxed */
+#define CFG_PSRT			0x1a
+
+/* "bad" address */
+#define	CFG_RESET_ADDRESS		0x40000000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
new file mode 100755
index 0000000..8dc623e
--- /dev/null
+++ b/include/configs/W7OLMC.h
@@ -0,0 +1,326 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1		/* This is a PPC405GP CPU	*/
+#define CONFIG_4xx		1		/* ...member of PPC405 family	*/
+#define CONFIG_W7O		1		/* ...on a Wave 7 Optics board	*/
+#define CONFIG_W7OLMC		1		/* ...specifically an LMC	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f	*/
+#define	CONFIG_MISC_INIT_F	1		/* and misc_init_f()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3		/* autoboot after 3 seconds	*/
+
+#if 1
+#define CONFIG_BOOTCOMMAND	"bootvx"	/* VxWorks boot command		*/
+#else
+#define CONFIG_BOOTCOMMAND	"bootp"		/* autoboot command		*/
+#endif
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_LOADADDR		F0080000
+
+#define CONFIG_ETHADDR		00:06:0D:00:00:00 /* Default, overridden at boot	*/
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_IPADDR		192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP		192.168.1.2
+
+#define CONFIG_LOADS_ECHO	1		/* echo on for serial download	*/
+#undef CFG_LOADS_BAUD_CHANGE			/* disallow baudrate change	*/
+
+#define CONFIG_MII		1		/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0		/* PHY address			*/
+
+#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
+
+#define CONFIG_COMMANDS		\
+	(CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
+	 CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
+	 CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG				/* watchdog disabled		*/
+#define CONFIG_HW_WATCHDOG			/* HW Watchdog, board specific	*/
+
+#define	CONFIG_SPD_EEPROM			/* SPD EEPROM for SDRAM param.	*/
+#define CONFIG_SPDDRAM_SILENT			/* No output if spd fails	*/
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT		"Wave7Optics> " /* Monitor Command Prompt	*/
+#undef  CFG_HUSH_PARSER				/* No hush parse for U-Boot       */
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2     "> "
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size	*/
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
+
+#undef  CFG_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CFG_405_UART_ERRATA_59			/* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD		384000
+
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	{9600}
+
+#define CFG_CLKS_IN_HZ		1		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address		*/
+#define CFG_EXTBDINFO		1		/* use extended board_info (bd_t) */
+
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER	0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE		1		/* configure as pci host	*/
+#define PCI_HOST_AUTO		2		/* detected via arbiter enable	*/
+
+
+#define CONFIG_PCI				/* include pci support		*/
+#define CONFIG_PCI_HOST		PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP				/* pci plug-and-play		*/
+/* resource configuration	*/
+#define CFG_PCI_SUBSYS_VENDORID 0x1014		/* PCI Vendor ID: IBM		*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0156		/* PCI Device ID: 405GP		*/
+#define CFG_PCI_PTM1LA		0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS		0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CFG_PCI_PTM1PCI 	0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA		0x00000000	/* disabled		*/
+#define CFG_PCI_PTM2MS		0x00000000	/* disabled		*/
+#define CFG_PCI_PTM2PCI 	0x00000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Set up values for external bus controller
+ * used by cpu_init.c
+ *-----------------------------------------------------------------------
+ */
+ /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
+#undef CONFIG_USE_PERWE
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM        1
+
+/* bank 0 is boot flash */
+/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_W7O_EBC_PB0AP   0x03050440
+/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
+#define CFG_W7O_EBC_PB0CR   0xFFE38000
+
+/* bank 1 is main flash */
+/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_EBC_PB1AP   0x05850240
+/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
+#define CFG_EBC_PB1CR   0xF00FC000
+
+/* bank 2 is RTC/NVRAM */
+/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_EBC_PB2AP   0x03000440
+/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
+#define CFG_EBC_PB2CR   0xFC018000
+
+/* bank 3 is FPGA 0 */
+/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
+#define CFG_EBC_PB3AP   0x02000400
+/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
+#define CFG_EBC_PB3CR   0xFD01A000
+
+/* bank 4 is FPGA 1 */
+/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
+#define CFG_EBC_PB4AP   0x02000400
+/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
+#define CFG_EBC_PB4CR   0xFD11A000
+
+/* bank 5 is FPGA 2 */
+/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
+#define CFG_EBC_PB5AP   0x02000400
+/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
+#define CFG_EBC_PB5CR   0xFD21A000
+
+/* bank 6 is unused */
+/* pb6ap = 0 */
+#define CFG_EBC_PB6AP   0x00000000
+/* pb6cr = 0 */
+#define CFG_EBC_PB6CR   0x00000000
+
+/* bank 7 is LED register */
+/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_W7O_EBC_PB7AP   0x03050440
+/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
+#define CFG_W7O_EBC_PB7CR   0xFE01C000
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2		/* max number of memory banks	*/
+#define CFG_MAX_FLASH_SECT	256		/* max number of sec on 1 chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout, Flash Erase, in ms	*/
+#define CFG_FLASH_WRITE_TOUT	500		/* Timeout, Flash Write, in ms	*/
+#define CFG_FLASH_PROTECTION	1		/* Use real Flash protection	*/
+
+#if 1 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_IN_NVRAM	1		/* use NVRAM for env vars	*/
+#define CFG_NVRAM_BASE_ADDR	0xfc000000	/* NVRAM base address		*/
+#define CFG_NVRAM_SIZE		(32*1024)	/* NVRAM size			*/
+#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
+/*define CFG_ENV_ADDR		 \
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env  */
+#define CFG_ENV_ADDR		CFG_NVRAM_BASE_ADDR
+
+#else /* Use Boot Flash for environment variables */
+/*-----------------------------------------------------------------------
+ * Flash EEPROM for environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define CFG_ENV_SIZE		0x10000		/* Total Size of env. sector	*/
+
+#define CFG_ENV_SECT_SIZE	0x10000		/* see README - env sec tot sze */
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last	4 bits of the address	*/
+#define CFG_I2C_MULTI_EEPROMS
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS      0x50	/* XXX conflicting address!!! XXX */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192		/* For AMCC 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32		/* ...		*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5		/* log base 2 of the above val. */
+#endif
+
+/*
+ * Init Memory Controller:
+ */
+#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0		*/
+#define FLASH_BASE1_PRELIM	0xF0000000	/* FLASH bank #1		*/
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in RAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02		/* Software reboot		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use	*/
+#endif
+
+/*
+ * FPGA(s) configuration
+ */
+#define CFG_FPGA_IMAGE_LEN	0x80000		/* 512KB FPGA image		*/
+#define CONFIG_NUM_FPGAS	3		/* Number of FPGAs on board	*/
+#define CONFIG_MAX_FPGAS	6		/* Maximum number of FPGAs	*/
+#define CONFIG_FPGAS_BASE	0xFD000000L	/* Base address of FPGAs	*/
+#define CONFIG_FPGAS_BANK_SIZE	0x00100000L	/* FPGAs' mmap bank size	*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
new file mode 100755
index 0000000..2bd98b3
--- /dev/null
+++ b/include/configs/W7OLMG.h
@@ -0,0 +1,327 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1		/* This is a PPC405GP CPU	*/
+#define CONFIG_4xx		1		/* ...member of PPC405 family	*/
+#define CONFIG_W7O		1		/* ...on a Wave 7 Optics board	*/
+#define CONFIG_W7OLMG		1		/* ...specifically an LMG	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f	*/
+#define	CONFIG_MISC_INIT_F	1		/* and misc_init_f()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3		/* autoboot after 3 seconds	*/
+
+#if 1
+#define CONFIG_BOOTCOMMAND	"bootvx"	/* VxWorks boot command		*/
+#else
+#define CONFIG_BOOTCOMMAND	"bootp"		/* autoboot command		*/
+#endif
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_LOADADDR		F0080000
+
+#define CONFIG_ETHADDR		00:06:0D:00:00:00 /* Default, overridden at boot	*/
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_IPADDR		192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP		192.168.1.2
+
+#define CONFIG_LOADS_ECHO	1		/* echo on for serial download	*/
+#undef CFG_LOADS_BAUD_CHANGE			/* disallow baudrate change	*/
+
+#define CONFIG_MII		1		/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0		/* PHY address			*/
+
+#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
+#define CONFIG_DTT_LM75     1                /* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS  {2, 4}           /* Sensor addresses */
+#define CFG_DTT_MAX_TEMP	70
+#define CFG_DTT_LOW_TEMP	-30
+#define CFG_DTT_HYSTERESIS	3
+
+#define CONFIG_COMMANDS		\
+	(CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
+	 CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
+	 CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO | \
+	 CFG_CMD_DTT)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG				/* watchdog disabled		*/
+#define CONFIG_HW_WATCHDOG			/* HW Watchdog, board specific	*/
+
+#define	CONFIG_SPD_EEPROM			/* SPD EEPROM for SDRAM param.	*/
+#define CONFIG_SPDDRAM_SILENT			/* No output if spd fails	*/
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT		"Wave7Optics> " /* Monitor Command Prompt	*/
+#undef  CFG_HUSH_PARSER				/* No hush parse for U-Boot       */
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2     "> "
+#endif
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size	*/
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
+
+#undef  CFG_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CFG_405_UART_ERRATA_59			/* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD		384000
+
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	{9600}
+
+#define CFG_CLKS_IN_HZ		1		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address		*/
+#define CFG_EXTBDINFO		1		/* use extended board_info (bd_t) */
+
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER	0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE		1		/* configure as pci host	*/
+#define PCI_HOST_AUTO		2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI				/* include pci support		*/
+#define CONFIG_PCI_HOST		PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP				/* pci plug-and-play		*/
+/* resource configuration	*/
+#define CFG_PCI_SUBSYS_VENDORID 0x1014		/* PCI Vendor ID: IBM		*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0156		/* PCI Device ID: 405GP		*/
+#define CFG_PCI_PTM1LA		0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS		0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CFG_PCI_PTM1PCI 	0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA		0x00000000	/* disabled		*/
+#define CFG_PCI_PTM2MS		0x00000000	/* disabled		*/
+#define CFG_PCI_PTM2PCI 	0x00000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Set up values for external bus controller
+ * used by cpu_init.c
+ *-----------------------------------------------------------------------
+ */
+ /* use PerWE instead of PCI_INT ( these functions share a pin ) */
+#define CONFIG_USE_PERWE 1
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM        1
+
+/* bank 0 is boot flash */
+/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_W7O_EBC_PB0AP   0x03050440
+/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
+#define CFG_W7O_EBC_PB0CR   0xFFE38000
+
+/* bank 1 is main flash */
+/* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_EBC_PB1AP   0x04850240
+/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
+#define CFG_EBC_PB1CR   0xF00FC000
+
+/* bank 2 is RTC/NVRAM */
+/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_EBC_PB2AP   0x03000440
+/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
+#define CFG_EBC_PB2CR   0xFC018000
+
+/* bank 3 is FPGA 0 */
+/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
+#define CFG_EBC_PB3AP   0x02000400
+/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
+#define CFG_EBC_PB3CR   0xFD01A000
+
+/* bank 4 is SAM 8 bit range */
+/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
+#define CFG_EBC_PB4AP   0x02840380
+/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
+#define CFG_EBC_PB4CR   0xFE878000
+
+/* bank 5 is SAM 16 bit range */
+/* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */
+#define CFG_EBC_PB5AP   0x05040d80
+/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
+#define CFG_EBC_PB5CR   0xFD87A000
+
+/* bank 6 is unused */
+/* pb6ap = 0 */
+#define CFG_EBC_PB6AP   0x00000000
+/* pb6cr = 0 */
+#define CFG_EBC_PB6CR   0x00000000
+
+/* bank 7 is LED register */
+/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_W7O_EBC_PB7AP   0x03050440
+/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
+#define CFG_W7O_EBC_PB7CR   0xFE01C000
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2		/* max number of memory banks	*/
+#define CFG_MAX_FLASH_SECT	256		/* max number of sec on 1 chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout, Flash Erase, in ms	*/
+#define CFG_FLASH_WRITE_TOUT	500		/* Timeout, Flash Write, in ms	*/
+#define CFG_FLASH_PROTECTION	1		/* Use real Flash protection	*/
+
+#if 1 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_IN_NVRAM	1		/* use NVRAM for env vars	*/
+#define CFG_NVRAM_BASE_ADDR	0xfc000000	/* NVRAM base address		*/
+#define CFG_NVRAM_SIZE		(32*1024)	/* NVRAM size			*/
+#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
+/*define CFG_ENV_ADDR		 \
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env  */
+#define CFG_ENV_ADDR		CFG_NVRAM_BASE_ADDR
+
+#else /* Use Boot Flash for environment variables */
+/*-----------------------------------------------------------------------
+ * Flash EEPROM for environment
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define CFG_ENV_SIZE		0x10000		/* Total Size of env. sector	*/
+
+#define CFG_ENV_SECT_SIZE	0x10000		/* see README - env sec tot sze */
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (ATMEL 24C04N)
+ */
+#define CONFIG_HARD_I2C		1		/* Hardware assisted I2C	*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50		/* EEPROM ATMEL 24C04N		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_I2C_MULTI_EEPROMS
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS      0x50	/* XXX conflicting address!!! XXX */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192		/* For AMCC 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32		/* ...		*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5		/* log base 2 of the above val. */
+#endif
+
+/*
+ * Init Memory Controller:
+ */
+#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0		*/
+#define FLASH_BASE1_PRELIM	0xF0000000	/* FLASH bank #1		*/
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in RAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02		/* Software reboot		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use	*/
+#endif
+
+/*
+ * FPGA(s) configuration
+ */
+#define CFG_FPGA_IMAGE_LEN	0x80000		/* 512KB FPGA image		*/
+#define CONFIG_NUM_FPGAS	1		/* Number of FPGAs on board	*/
+#define CONFIG_MAX_FPGAS	6		/* Maximum number of FPGAs	*/
+#define CONFIG_FPGAS_BASE	0xFD000000L	/* Base address of FPGAs	*/
+#define CONFIG_FPGAS_BANK_SIZE	0x00100000L	/* FPGAs' mmap bank size	*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
new file mode 100755
index 0000000..d92f81f
--- /dev/null
+++ b/include/configs/WUH405.h
@@ -0,0 +1,388 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_IDENT_STRING     " $Name:  $"
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_WUH405		1	/* ...on a WUH405 board		*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33333300 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_EEPROM	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD	    691200
+#define	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define CFG_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CFG_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CFG_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CFG_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
+
+#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
+#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
+#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
+#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
+#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
+#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
+#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+#define CONFIG_MTD_NAND_VERIFY_WRITE 1  /* verify all writes!!!         */
+#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFFC0000
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CFG_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x92015480
+/*#define CFG_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x92015480
+#define CFG_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CFG_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
+#define CFG_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
+#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
+#define DUART2_BA	0xF0000410	    /* DUART Base Address		*/
+#define DUART3_BA	0xF0000418	    /* DUART Base Address		*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
+#define CFG_NAND_BASE	0xF4000000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH		0x40000550
+#define CFG_GPIO0_OSRL		0x00000110
+#define CFG_GPIO0_ISR1H		0x00000000
+#define CFG_GPIO0_ISR1L		0x15555445
+#define CFG_GPIO0_TSRH		0x00000000
+#define CFG_GPIO0_TSRL		0x00000000
+#define CFG_GPIO0_TCR		0xF7FE0014
+
+#define CFG_DUART_RST		(0x80000000 >> 14)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h
new file mode 100755
index 0000000..9b32514
--- /dev/null
+++ b/include/configs/XPEDITE1K.h
@@ -0,0 +1,274 @@
+/*
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * config for XPedite1000 from XES Inc.
+ * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
+ * (C) Copyright 2003 Sandburst Corporation
+ * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_XPEDITE1K	1		/* Board is XPedite 1000 */
+#define CONFIG_4xx		1		/* ... PPC4xx family	*/
+#define CONFIG_440		1
+#define CONFIG_440GX		1		/* 440 GX */
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_pre_init	*/
+#undef	CFG_DRAM_TEST				/* Disable-takes long time! */
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll */
+
+
+/* POST support */
+#define CONFIG_POST		(CFG_POST_RTC	   | \
+				 CFG_POST_I2C)
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE	    0x00000000		/* _must_ be 0		*/
+#define CFG_FLASH_BASE	    0xfff80000		/* start of FLASH	*/
+
+#define CFG_MONITOR_BASE    CFG_FLASH_BASE	/* start of monitor	*/
+#define CFG_PCI_MEMBASE	    0x80000000		/* mapped pci memory	*/
+#define CFG_PERIPHERAL_BASE 0xe0000000		/* internal peripherals */
+#define CFG_ISRAM_BASE	    0xc0000000		/* internal SRAM	*/
+#define CFG_PCI_BASE	    0xd0000000		/* internal PCI regs	*/
+
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+#define CFG_GPIO_BASE	    (CFG_PERIPHERAL_BASE + 0x00000700)
+
+#define USR_LED0	    0x00000080
+#define USR_LED1	    0x00000100
+#define USR_LED2	    0x00000200
+#define USR_LED3	    0x00000400
+
+#ifndef __ASSEMBLY__
+extern unsigned long in32(unsigned int);
+extern void out32(unsigned int, unsigned long);
+
+#define LED0_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED0))
+#define LED1_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED1))
+#define LED2_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED2))
+#define LED3_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED3))
+
+#define LED0_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED0))
+#define LED1_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED1))
+#define LED2_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED2))
+#define LED3_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED3))
+#endif
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM  1
+#define CFG_OCM_DATA_ADDR   CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
+#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
+
+
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR  (CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET  CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
+#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_BAUDRATE		9600
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+/* TBS:	 Xpedite 1000 has STMicro M41T00 via IIC */
+#define CONFIG_RTC_M41T11 1
+#define CFG_I2C_RTC_ADDR 0x68
+#define CFG_M41T11_BASE_YEAR 2000
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS	1		    /* number of banks	    */
+#define CFG_MAX_FLASH_SECT	8		    /* sectors per device   */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	    /* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS {0x54}	/* SPD i2c spd addresses	*/
+#define CONFIG_VERY_BIG_RAM 1
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7f
+#define CFG_I2C_NOPROBES	{0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69}	/* Don't probe these addrs */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_SIZE		0x100	    /* Size of Environment vars */
+#define CFG_ENV_OFFSET		0x100
+#define CFG_I2C_EEPROM_ADDR	0x50		/* this is actually the second page of the eeprom */
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#define CONFIG_BOOTARGS		"root=/dev/hda1 "
+#define CONFIG_BOOTCOMMAND	"bootm ffc00000"    /* autoboot command */
+#define CONFIG_BOOTDELAY	5		    /* disable autoboot */
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII			1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address phy0 not populated */
+#define CONFIG_PHY1_ADDR	1	/* PHY address phy1 not populated */
+#define CONFIG_PHY2_ADDR	4	/* PHY address phy2 */
+#define CONFIG_PHY3_ADDR	8	/* PHY address phy3 */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
+#define CFG_RX_ETH_BUFFER   32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_HAS_ETH2		1	/* add support for "eth2addr"	*/
+#define CONFIG_HAS_ETH3		1	/* add support for "eth3addr"	*/
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_PING | \
+				CFG_CMD_ELF | \
+				CFG_CMD_MII | \
+				CFG_CMD_DIAG | \
+				CFG_CMD_FAT )
+
+/*				CFG_CMD_DHCP	| \ */
+/*				CFG_CMD_KGDB	| \ */
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI				    /* include pci support		*/
+#define CONFIG_PCI_PNP				/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
+#define CFG_PCI_TARGET_INIT		    /* let board init pci target    */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CFG_PCI_FORCE_PCI_CONV          /* Force PCI Conventional Mode */
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192 /* For AMCC 440GX CPUs */
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h
new file mode 100755
index 0000000..37ef105
--- /dev/null
+++ b/include/configs/Yukon8220.h
@@ -0,0 +1,318 @@
+/*
+ * (C) Copyright 2004
+ * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC8220		1
+#define CONFIG_YUKON8220	1	/* ... on Yukon board	*/
+
+/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
+   determine the CPU speed. */
+#define CFG_MPC8220_CLKIN	30000000/* ... running at 30MHz */
+#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	*/
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5   /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+
+/* Define this for PSC console
+#define CONFIG_PSC_CONSOLE	1
+*/
+
+#define CONFIG_EXTUART_CONSOLE	1
+
+#ifdef CONFIG_EXTUART_CONSOLE
+#   define CONFIG_CONS_INDEX	1
+#   define CFG_NS16550_SERIAL
+#   define CFG_NS16550
+#   define CFG_NS16550_REG_SIZE 1
+#   define CFG_NS16550_COM1	(CFG_CPLD_BASE + 0x1008)
+#   define CFG_NS16550_CLK	18432000
+#endif
+
+#define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_TIMESTAMP			/* Print image info with timestamp */
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BOOTD	| \
+				CFG_CMD_CACHE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO | \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_SNTP	)
+
+#define CONFIG_NET_MULTI
+#define CONFIG_MII
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5    /* autoboot after 5 seconds */
+#define CONFIG_BOOTARGS		"root=/dev/ram rw"
+#define CONFIG_ETHADDR		00:e0:0c:bc:e0:60
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:e0:0c:bc:e0:61
+#define CONFIG_IPADDR		192.162.1.2
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP		192.162.1.1
+#define CONFIG_GATEWAYIP	192.162.1.1
+#define CONFIG_HOSTNAME		yukon
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1
+#define CFG_I2C_MODULE		1
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x52	/* 1011000xb */
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+/*
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_ENV_OFFSET		0
+#define CFG_ENV_SIZE		256
+*/
+
+/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
+   else undefined it will boot from Intel Strata flash */
+#define CFG_AMD_BOOT		1
+
+/*
+ * Flexbus Chipselect configuration
+ */
+#if defined (CFG_AMD_BOOT)
+#define CFG_CS0_BASE		0xfff0
+#define CFG_CS0_MASK		0x00080000  /* 512 KB */
+#define CFG_CS0_CTRL		0x003f0d40
+
+#define CFG_CS1_BASE		0xfe00
+#define CFG_CS1_MASK		0x01000000  /* 16 MB */
+#define CFG_CS1_CTRL		0x003f1540
+#else
+#define CFG_CS0_BASE		0xff00
+#define CFG_CS0_MASK		0x01000000  /* 16 MB */
+#define CFG_CS0_CTRL		0x003f1540
+
+#define CFG_CS1_BASE		0xfe08
+#define CFG_CS1_MASK		0x00080000  /* 512 KB */
+#define CFG_CS1_CTRL		0x003f0d40
+#endif
+
+#define CFG_CS2_BASE		0xf100
+#define CFG_CS2_MASK		0x00040000
+#define CFG_CS2_CTRL		0x003f1140
+
+#define CFG_CS3_BASE		0xf200
+#define CFG_CS3_MASK		0x00040000
+#define CFG_CS3_CTRL		0x003f1100
+
+
+#define CFG_FLASH0_BASE		(CFG_CS0_BASE << 16)
+#define CFG_FLASH1_BASE		(CFG_CS1_BASE << 16)
+
+#if defined (CFG_AMD_BOOT)
+#define CFG_AMD_BASE		CFG_FLASH0_BASE
+#define CFG_INTEL_BASE		CFG_FLASH1_BASE + 0xf00000
+#define CFG_FLASH_BASE		CFG_AMD_BASE
+#else
+#define CFG_INTEL_BASE		CFG_FLASH0_BASE + 0xf00000
+#define CFG_AMD_BASE		CFG_FLASH1_BASE
+#define CFG_FLASH_BASE		CFG_INTEL_BASE
+#endif
+
+#define CFG_CPLD_BASE		(CFG_CS2_BASE << 16)
+#define CFG_FPGA_BASE		(CFG_CS3_BASE << 16)
+
+
+#define CFG_MAX_FLASH_BANKS	4	/* max num of memory banks	*/
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+
+#define PHYS_AMD_SECT_SIZE	0x00010000 /*  64 KB sectors (x2) */
+#define PHYS_INTEL_SECT_SIZE	0x00020000 /* 128 KB sectors (x2) */
+
+#define CFG_FLASH_CHECKSUM
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#if defined (CFG_AMD_BOOT)
+#define CFG_ENV_ADDR		(CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
+#define CFG_ENV_SIZE		PHYS_AMD_SECT_SIZE
+#define CFG_ENV_SECT_SIZE	PHYS_AMD_SECT_SIZE
+#define CFG_ENV1_ADDR		(CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
+#define CFG_ENV1_SIZE		PHYS_INTEL_SECT_SIZE
+#define CFG_ENV1_SECT_SIZE	PHYS_INTEL_SECT_SIZE
+#else
+#define CFG_ENV_ADDR		(CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
+#define CFG_ENV_SIZE		PHYS_INTEL_SECT_SIZE
+#define CFG_ENV_SECT_SIZE	PHYS_INTEL_SECT_SIZE
+#define CFG_ENV1_ADDR		(CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
+#define CFG_ENV1_SIZE		PHYS_AMD_SECT_SIZE
+#define CFG_ENV1_SECT_SIZE	PHYS_AMD_SECT_SIZE
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1
+
+#if defined CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_EEPROM
+#elif defined CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_EEPROM
+#elif defined CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#endif
+
+#ifndef CFG_JFFS2_FIRST_SECTOR
+#define CFG_JFFS2_FIRST_SECTOR	0
+#endif
+#ifndef CFG_JFFS2_FIRST_BANK
+#define CFG_JFFS2_FIRST_BANK	0
+#endif
+#ifndef CFG_JFFS2_NUM_BANKS
+#define CFG_JFFS2_NUM_BANKS	1
+#endif
+#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+#define CFG_SRAM_BASE		(CFG_MBAR + 0x20000)
+#define CFG_SRAM_SIZE		0x8000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	(CFG_MBAR + 0x20000)
+#define CFG_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
+#define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
+
+/* SDRAM configuration */
+#define CFG_SDRAM_TOTAL_BANKS		2
+#define CFG_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
+#define CFG_SDRAM_SPD_SIZE		0x40
+#define CFG_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */
+
+/* SDRAM drive strength register */
+#define CFG_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
+					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
+					 (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
+					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBD_SHIFT))
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC8220_FEC	1
+#define CONFIG_FEC_10MBIT	1 /* Workaround for FEC 100Mbit problem */
+#define CONFIG_PHY_ADDR		0x18
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			    /* undef to save memory	*/
+#define CFG_PROMPT		"=> "	    /* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	    /* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	    /* max number of command args   */
+#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START	0x00100000  /* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
+
+#define CFG_LOAD_ADDR		0x100000    /* default load address */
+
+#define CFG_HZ			1000	    /* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
new file mode 100755
index 0000000..f71e691
--- /dev/null
+++ b/include/configs/ZPC1900.h
@@ -0,0 +1,268 @@
+/*
+ * Copyright (C) 2003-2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
+ * This port was developed and tested on Revision C board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU      */
+#define CONFIG_ZPC1900		1	/* ...on Zephyr ZPC.1900 board */
+#define CPU_ID_STR		"MPC8265"
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#undef DEBUG
+
+#undef CONFIG_BOARD_EARLY_INIT_F	/* Don't call board_early_init_f */
+
+/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
+#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
+#undef	CONFIG_CONS_NONE		/* It's not on external UART */
+#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CFG_CMD_NET must
+ * be removed from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
+#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
+#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
+
+#ifdef CONFIG_ETHER_ON_FCC
+
+#define CONFIG_ETHER_INDEX	2	/* FCC2 is used for Ethernet */
+
+#if (CONFIG_ETHER_INDEX == 2)
+/*
+ * - Rx clock is CLK13
+ * - Tx clock is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Full duplex
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_INDEX */
+
+#define CONFIG_MII			/* MII PHY management        */
+#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT		2	/* Port C */
+#define MDIO_ACTIVE		(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE		(iop->pdir &= ~0x00400000)
+#define MDIO_READ		((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)		if(bit) iop->pdat |=  0x00400000; \
+				else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)		if(bit) iop->pdat |=  0x00200000; \
+				else	iop->pdat &= ~0x00200000
+
+#define MIIDELAY		udelay(1)
+
+#endif /* CONFIG_ETHER_ON_FCC */
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL   \
+				| CFG_CMD_ASKENV  \
+				| CFG_CMD_DHCP    \
+				| CFG_CMD_ECHO    \
+				| CFG_CMD_IMMAP   \
+				| CFG_CMD_MII     \
+				| CFG_CMD_PING    \
+				)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND	"dhcp;bootm"	/* autoboot command */
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=:::::eth0:dhcp"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_FLASH_BASE		0xFFE00000
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
+
+#define CFG_DEFAULT_IMMR	0x0F010000
+
+#define CFG_IMMR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_SIZE		64
+#define CFG_FLSIMM_BASE		0xFC000000
+#define CFG_LSDRAM_BASE		0xFE000000
+#define CFG_BCSR		0xFEA00000
+#define CFG_EEPROM		0xFEB00000
+
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+
+#define BCSR_PCI_MODE		0x01
+
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/* Hard reset configuration word */
+#define CFG_HRCW_MASTER		(HRCW_EBM | HRCW_BPS01| HRCW_CIP          |\
+				 HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\
+				 HRCW_BMS | HRCW_LBPC01 | HRCW_APPC10     |\
+				 HRCW_MODCK_H0101                          \
+				) /* 0x16828605 */
+/* No slaves */
+#define CFG_HRCW_SLAVE1 	0
+#define CFG_HRCW_SLAVE2 	0
+#define CFG_HRCW_SLAVE3 	0
+#define CFG_HRCW_SLAVE4 	0
+#define CFG_HRCW_SLAVE5 	0
+#define CFG_HRCW_SLAVE6 	0
+#define CFG_HRCW_SLAVE7 	0
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot                  */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#if !defined(CFG_ENV_IS_IN_FLASH) && !defined(CFG_ENV_IS_IN_NVRAM)
+#define CFG_ENV_IS_IN_NVRAM	1
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#  define CFG_ENV_SECT_SIZE	0x10000
+#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#else
+#  define CFG_ENV_ADDR		(CFG_EEPROM + 0x400)
+#  define CFG_ENV_SIZE		0x1000
+#  define CFG_NVRAM_ACCESS_ROUTINE
+#endif
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )
+
+#define CFG_HID2		0
+
+#define CFG_SIUMCR		0x42200000
+#define CFG_SYPCR		0xFFFFFFC3
+#define CFG_BCR			0x90400000
+#define CFG_SCCR		SCCR_DFBRG01
+
+#define CFG_RMR			RMR_CSRE
+#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CFG_RCCR		0
+
+#define CFG_PSDMR		0x014EB45A
+#define CFG_PSRT		0x0C
+#define CFG_LSDMR		0x008AB552
+#define CFG_LSRT		0x0E
+#define CFG_MPTPR		0x4000
+
+#define CFG_BR0_PRELIM		CFG_FLASH_BASE | 0x00000801
+#define CFG_OR0_PRELIM		0xFFE00856
+#define CFG_BR5_PRELIM		CFG_EEPROM | 0x00000801
+#define CFG_OR5_PRELIM		0xFFFF03F6
+#define CFG_BR6_PRELIM		CFG_FLSIMM_BASE | 0x00000801
+#define CFG_OR6_PRELIM		0xFE000856
+#define CFG_BR7_PRELIM		CFG_BCSR | 0x00000801
+#define CFG_OR7_PRELIM		0xFFFF83F6
+
+#define CFG_RESET_ADDRESS	0xC0000000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h
new file mode 100755
index 0000000..f163d00
--- /dev/null
+++ b/include/configs/ZUMA.h
@@ -0,0 +1,391 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
+#define CONFIG_ETHER_PORT_MII	/* use two MII ports */
+#define CONFIG_INTEL_LXT97X	/* Intel LXT97X phy */
+
+#ifndef __ASSEMBLY__
+#include <galileo/core.h>
+#endif
+
+#include "../board/evb64260/local.h"
+
+#define CONFIG_EVB64260		1	/* this is an EVB64260 board	*/
+#define CONFIG_ZUMA_V2		1	/* always define this for ZUMA v2 */
+
+/* #define CONFIG_ZUMA_V2_OLD	1 */	/* backwards compat for old V2 board */
+
+#define CONFIG_BAUDRATE		38400	/* console baudrate = 38400	*/
+
+#define CONFIG_ECC			/* enable ECC support */
+
+#define CONFIG_750CX			/* we have a 750CX/CXe (override local.h) */
+
+/* which initialization functions to call for this board */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CFG_BOARD_ASM_INIT
+
+#define CFG_BOARD_NAME		"Zuma APv2"
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * what to do:
+ * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
+ * cable onto the second DUART channel, change the CFG_DUART port from 1
+ * to 0 below.
+ *
+ * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
+ * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
+ */
+#define CONFIG_MPSC
+
+#define CONFIG_MPSC_PORT	0
+
+#define CONFIG_NET_MULTI        /* attempt all available adapters */
+
+/* define this if you want to enable GT MAC filtering */
+#define CONFIG_GT_USE_MAC_HASH_TABLE
+
+#if 1
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot && "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
+	"ip=$ipaddr:$serverip:$gatewayip:"				\
+	"$netmask:$hostname:eth0:none panic=5 && bootm"
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
+#define CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_ALTIVEC			/* undef to disable		*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MII		/* enable MII commands */
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
+				 CFG_CMD_ASKENV | \
+				 CFG_CMD_BSP	| \
+				 CFG_CMD_JFFS2	| \
+				 CFG_CMD_MII	| \
+				 CFG_CMD_DATE)
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor1=zuma-1,nor2=zuma-2"
+#define MTDPARTS_DEFAULT	"mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
+*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x00300000	/* default load address */
+
+#define CFG_HZ			1000		/* decr freq: 1ms ticks */
+
+#define CFG_BUS_HZ		133000000	/* 133 MHz		*/
+
+#define CFG_BUS_CLK		CFG_BUS_HZ
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_RAM_ADDR	0x40000000
+#define CFG_INIT_RAM_END	0x1000
+#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_RAM_LOCK
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xfff00000
+#define CFG_RESET_ADDRESS	0xfff00100
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+
+/* areas to map different things with the GT in physical space */
+#define CFG_DRAM_BANKS		4
+#define CFG_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
+
+/* What to put in the bats. */
+#define CFG_MISC_REGION_BASE	0xf0000000
+
+/* Peripheral Device section */
+#define CFG_GT_REGS		0xf8000000	/* later mapped GT_REGS */
+#define CFG_DEV_BASE		0xf0000000
+#define CFG_DEV0_SIZE		_64M /* zuma flash @ 0xf000.0000*/
+#define CFG_DEV1_SIZE		 _8M /* zuma IDE   @ 0xf400.0000 */
+#define CFG_DEV2_SIZE		 _8M /* unused */
+#define CFG_DEV3_SIZE		 _8M /* unused */
+
+#define CFG_DEV0_PAR		0xc498243c
+	/*     c    4     9     8     2	    4     3     c */
+	/* 33 22|2222|22 22|111 1|11 11|1 1  |	   |      */
+	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
+	/* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */
+	/*  3| 0|.... ..| 1| 4 |  0 |  4 |   8 |   7 | 4  */
+
+#define CFG_DEV1_PAR		0xc01b6ac5
+	/*     c    0     1     b     6	    a     c     5 */
+	/* 33 22|2222|22 22|111 1|11 11|1 1  |	   |      */
+	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
+	/* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */
+	/*  3| 0|.... ..| 1| 5 |  5 |  5 |   5 |   8 | 5  */
+
+
+#define CFG_8BIT_BOOT_PAR	0xc00b5e7c
+
+#define CFG_MPP_CONTROL_0	0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */
+#define CFG_MPP_CONTROL_1	0x00000000 /* GPP[15:12] : GPP[11:8] */
+#define CFG_MPP_CONTROL_2	0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */
+#define CFG_MPP_CONTROL_3	0x00000000 /* GPP[31:28] (int[3:0]) */
+					   /* GPP[27:24] (27 is int4, rest are GPP) */
+
+#define CFG_SERIAL_PORT_MUX	0x00001101 /* 11=MPSC1/MPSC0 01=ETH,  0=only MII */
+#define CFG_GPP_LEVEL_CONTROL	0xf8000000 /* interrupt inputs: GPP[31:27] */
+
+#define CFG_SDRAM_CONFIG	0xe4e18200	/* 0x448 */
+				/* idmas use buffer 1,1
+				   comm use buffer 1
+				   pci use buffer 0,0 (pci1->0 pci0->0)
+				   cpu use buffer 1 (R*18)
+				   normal load (see also ifdef HVL)
+				   standard SDRAM (see also ifdef REG)
+				   non staggered refresh */
+				/* 31:26  25 23	 20 19 18 16 */
+				/* 111001 00 111 0  0  00 1 */
+
+				/* refresh count=0x200
+				   phy interleave disable (by default,
+				   set later by dram config..)
+				   virt interleave enable */
+				/* 15 14 13:0 */
+				/* 1  0	 0x200 */
+
+#define CFG_DEV0_SPACE		CFG_DEV_BASE
+#define CFG_DEV1_SPACE		(CFG_DEV0_SPACE + CFG_DEV0_SIZE)
+#define CFG_DEV2_SPACE		(CFG_DEV1_SPACE + CFG_DEV1_SIZE)
+#define CFG_DEV3_SPACE		(CFG_DEV2_SPACE + CFG_DEV2_SIZE)
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ */
+
+#define PCI_HOST_ADAPTER	0	/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE		1	/* configure as pci host	*/
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+
+/* PCI MEMORY MAP section */
+#define CFG_PCI0_MEM_BASE	0x80000000
+#define CFG_PCI0_MEM_SIZE	_128M
+#define CFG_PCI1_MEM_BASE	0x88000000
+#define CFG_PCI1_MEM_SIZE	_128M
+
+#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
+#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+
+/* PCI I/O MAP section */
+#define CFG_PCI0_IO_BASE	0xfa000000
+#define CFG_PCI0_IO_SIZE	_16M
+#define CFG_PCI1_IO_BASE	0xfb000000
+#define CFG_PCI1_IO_SIZE	_16M
+
+#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
+#define CFG_PCI0_IO_SPACE_PCI	0x00000000
+#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
+#define CFG_PCI1_IO_SPACE_PCI	0x00000000
+
+
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+
+/* SDRAM */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT0U CFG_IBAT0U
+
+/* init ram */
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+
+/* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */
+#define CFG_IBAT2L BATL_NO_ACCESS
+#define CFG_IBAT2U CFG_DBAT2U
+#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT3U CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks	*/
+#define CFG_MAX_FLASH_SECT	130	/* max number of sectors on one chip */
+
+#define CFG_EXTRA_FLASH_DEVICE	DEVICE0 /* extra flash at device 0 */
+#define CFG_EXTRA_FLASH_WIDTH	2	/* 16 bit */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_CFI		1
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sect real size */
+#define CFG_ENV_ADDR		(0xfff80000 - CFG_ENV_SECT_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/74xx_7xx.h for the defines used here
+ */
+
+#define CFG_L2
+
+#ifdef CONFIG_750CX
+#define L2_INIT		0
+#else
+#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#endif
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+/*------------------------------------------------------------------------
+ * Real time clock
+ */
+#define CONFIG_RTC_DS1302
+
+
+/*------------------------------------------------------------------------
+ * Galileo I2C driver
+ */
+#define CONFIG_GT_I2C
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		    */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h
new file mode 100755
index 0000000..c410891
--- /dev/null
+++ b/include/configs/adsvix.h
@@ -0,0 +1,347 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the LUBBOCK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA27X		1	/* This is an PXA27x CPU    */
+#define CONFIG_ADSVIX		1	/* on a Adsvix Board     */
+#define CONFIG_MMC		1
+#define BOARD_LATE_INIT		1
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+#define RTC
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART	       1       /* we use FFUART on ADSVIX */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE	       38400
+
+#define CONFIG_DOS_PARTITION   1
+
+#define CONFIG_COMMANDS		((CONFIG_CMD_DFL & ~CFG_CMD_NET) | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_IDE | CFG_CMD_PCMCIA)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_SERVERIP		192.168.1.99
+#define CONFIG_BOOTCOMMAND	"run boot_flash"
+#define CONFIG_BOOTARGS		"console=ttyS0,38400 ramdisk_size=12288"\
+				" rw root=/dev/ram initrd=0xa0800000,5m"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"program_boot_cf="						\
+			"mw.b 0xa0010000 0xff 0x20000; "		\
+			"if	 pinit on && "				\
+				"ide reset && "				\
+				"fatload ide 0 0xa0010000 u-boot.bin; "	\
+			"then "						\
+				"protect off 0x0 0x1ffff; "		\
+				"erase 0x0 0x1ffff; "			\
+				"cp.b 0xa0010000 0x0 0x20000; "		\
+			"fi\0"						\
+	"program_uzImage_cf="						\
+			"mw.b 0xa0010000 0xff 0x180000; "		\
+			"if	 pinit on && "				\
+				"ide reset && "				\
+				"fatload ide 0 0xa0010000 uzImage; "	\
+			"then "						\
+				"protect off 0x40000 0x1bffff; "	\
+				"erase 0x40000 0x1bffff; "		\
+				"cp.b 0xa0010000 0x40000 0x180000; "	\
+			"fi\0"						\
+	"program_ramdisk_cf="						\
+			"mw.b 0xa0010000 0xff 0x500000; "		\
+			"if	 pinit on && "				\
+				"ide reset && "				\
+				"fatload ide 0 0xa0010000 ramdisk.gz; "	\
+			"then "						\
+				"protect off 0x1c0000 0x6bffff; "	\
+				"erase 0x1c0000 0x6bffff; "		\
+				"cp.b 0xa0010000 0x1c0000 0x500000; "	\
+			"fi\0"						\
+	"boot_cf="							\
+			"if	 pinit on && "				\
+				"ide reset && "				\
+				"fatload ide 0 0xa0030000 uzImage && "	\
+				"fatload ide 0 0xa0800000 ramdisk.gz; "	\
+			"then "						\
+				"bootm 0xa0030000; "			\
+			"fi\0"						\
+	"program_boot_mmc="						\
+			"mw.b 0xa0010000 0xff 0x20000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0010000 u-boot.bin; "	\
+			"then "						\
+				"protect off 0x0 0x1ffff; "		\
+				"erase 0x0 0x1ffff; "			\
+				"cp.b 0xa0010000 0x0 0x20000; "		\
+			"fi\0"						\
+	"program_uzImage_mmc="						\
+			"mw.b 0xa0010000 0xff 0x180000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0010000 uzImage; "	\
+			"then "						\
+				"protect off 0x40000 0x1bffff; "	\
+				"erase 0x40000 0x1bffff; "		\
+				"cp.b 0xa0010000 0x40000 0x180000; "	\
+			"fi\0"						\
+	"program_ramdisk_mmc="						\
+			"mw.b 0xa0010000 0xff 0x500000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0010000 ramdisk.gz; "	\
+			"then "						\
+				"protect off 0x1c0000 0x6bffff; "	\
+				"erase 0x1c0000 0x6bffff; "		\
+				"cp.b 0xa0010000 0x1c0000 0x500000; "	\
+			"fi\0"						\
+	"boot_mmc="							\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0030000 uzImage && "	\
+				"fatload mmc 0 0xa0800000 ramdisk.gz; "	\
+			"then "						\
+				"bootm 0xa0030000; "			\
+			"fi\0"						\
+	"boot_flash="							\
+			"cp.b 0x1c0000 0xa0800000 0x500000; "		\
+			"bootm 0x40000\0"				\
+
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+/* #define CONFIG_INITRD_TAG	 1 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER		1
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#define CFG_LONGHELP				/* undef to save memory		*/
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
+#else
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_DEVICE_NULLDEV	1
+
+#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0xa1000000	/* default load address */
+
+#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x207		/* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_MMC_BASE		0xF0000000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+
+#define CFG_DRAM_BASE		0xa0000000
+#define CFG_DRAM_SIZE		0x04000000
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*
+ * GPIO settings
+ */
+
+#define CFG_GPSR0_VAL		0x00018004
+#define CFG_GPSR1_VAL		0x004F0080
+#define CFG_GPSR2_VAL		0x13EFC000
+#define CFG_GPSR3_VAL		0x0006E032
+#define CFG_GPCR0_VAL		0x084AFE1A
+#define CFG_GPCR1_VAL		0x003003F2
+#define CFG_GPCR2_VAL		0x0C014000
+#define CFG_GPCR3_VAL		0x00000C00
+#define CFG_GPDR0_VAL		0xCBC3BFFC
+#define CFG_GPDR1_VAL		0x00FFABF3
+#define CFG_GPDR2_VAL		0x1EEFFC00
+#define CFG_GPDR3_VAL		0x0187EC32
+#define CFG_GAFR0_L_VAL		0x84400000
+#define CFG_GAFR0_U_VAL		0xA51A8010
+#define CFG_GAFR1_L_VAL		0x699A955A
+#define CFG_GAFR1_U_VAL		0x0005A0AA
+#define CFG_GAFR2_L_VAL		0x40000000
+#define CFG_GAFR2_U_VAL		0x0109A400
+#define CFG_GAFR3_L_VAL		0x54000000
+#define CFG_GAFR3_U_VAL		0x00001409
+
+#define CFG_PSSR_VAL		0x20
+
+/*
+ * Clock settings
+ */
+#define CFG_CKEN		0x00400200
+#define CFG_CCCR		0x02000290 /*   520Mhz */
+/* #define CFG_CCCR		0x02000210  416 Mhz */
+
+/*
+ * Memory settings
+ */
+
+#define CFG_MSC0_VAL		0x23F2B3DB
+#define CFG_MSC1_VAL		0x0000CCD1
+#define CFG_MSC2_VAL		0x0000B884
+#define CFG_MDCNFG_VAL		0x08000AC8
+#define CFG_MDREFR_VAL		0x0000001E
+#define CFG_MDMRS_VAL		0x00000000
+
+#define CFG_FLYCNFG_VAL		0x00010001
+#define CFG_SXCNFG_VAL		0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL		0x00000002
+#define CFG_MCMEM0_VAL		0x00004204
+#define CFG_MCMEM1_VAL		0x00000000
+#define CFG_MCATT0_VAL		0x00010504
+#define CFG_MCATT1_VAL		0x00000000
+#define CFG_MCIO0_VAL		0x00008407
+#define CFG_MCIO1_VAL		0x00000000
+
+#define CONFIG_PXA_PCMCIA 1
+#define CONFIG_PXA_IDE 1
+
+#define CONFIG_PCMCIA_SLOT_A 1
+/* just to keep build system happy  */
+
+#define CFG_PCMCIA_MEM_ADDR     0x28000000
+#define CFG_PCMCIA_MEM_SIZE     0x04000000
+
+
+#define CFG_IDE_MAXBUS		1
+/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1
+/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	0x20000000
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	0x1f0
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0x1f0
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x3f0
+
+/*
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER	1
+
+#define CFG_MONITOR_BASE	0
+#define CFG_MONITOR_LEN		0x20000
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	4 + 255  /* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+
+/* write flash less slowly */
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+
+/* Flash environment locations */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + CFG_MONITOR_LEN)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment     	*/
+#define CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/aev.h b/include/configs/aev.h
new file mode 100755
index 0000000..aa6bc91
--- /dev/null
+++ b/include/configs/aev.h
@@ -0,0 +1,401 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
+#define CONFIG_TQM5200		1	/* ... on TQM5200 module */
+#undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules */
+#define CONFIG_STK52XX		1	/* ... on a STK52XX base board */
+#define CONFIG_STK52XX_REV100	1	/*  define for revision 100 baseboards */
+#define CONFIG_AEVFIFO		1
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#ifdef CONFIG_AEVFIFO
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+/* #define CONFIG_PCI_SCAN_SHOW	1 */
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_EEPRO100		1
+#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X		1
+#endif	/* CONFIG_AEVFIFO */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* POST support */
+#define CONFIG_POST		(CFG_POST_MEMORY   | \
+				 CFG_POST_CPU	   | \
+				 CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				ADD_BMP_CMD	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ECHO	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_POST_DIAG | \
+				CFG_CMD_REGINFO | \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define	CONFIG_TIMESTAMP		/* display image timestamps */
+
+#if (TEXT_BASE == 0xFC000000)		/* Boot low */
+#   define CFG_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath} "			\
+		"console=ttyS0,${baudrate}\0"				\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"bootfile=/tftpboot/tqm5200/uImage\0"				\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"				\
+	"update=protect off FC000000 FC05FFFF;"				\
+		"erase FC000000 FC05FFFF;"				\
+		"cp.b 200000 FC000000 ${filesize};"			\
+		"protect on FC000000 FC05FFFF\0"			\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#ifdef CONFIG_TQM5200_REV100
+#define CFG_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
+#else
+#define CFG_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
+#endif
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
+ * also). For other EEPROMs configuration should be verified. On Mini-FAP the
+ * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
+ * same configuration could be used.
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver if no module variant is spezified */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#undef CFG_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
+
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00760000 + 0x00800000)
+#else	/* CFG_LOWBOOT */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
+#endif	/* CFG_LOWBOOT */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x10000
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ *
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
+ *	Bit 0 (mask: 0x80000000): 1
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ *	00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ *	      Use for REV200 STK52XX boards. Do not use with REV100 modules
+ *	      (because, there I2C1 is used as I2C bus)
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
+ *	000 -> All PSC2 pins are GIOPs
+ *	001 -> CAN1/2 on PSC2 pins
+ *	       Use for REV100 STK52xx boards
+ * use PSC6:
+ *   on STK52xx:
+ *	use as UART. Pins PSC6_0 to PSC6_3 are used.
+ *	Bits 9:11 (mask: 0x00700000):
+ *	   101 -> PSC6 : Extended POST test is not available
+ *   on MINI-FAP and TQM5200_IB:
+ *	use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
+ *	   000 -> PSC6 could not be used as UART, CODEC or IrDA
+ *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
+ *   tests.
+ */
+#define CFG_GPS_PORT_CONFIG	0x81500014
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#ifdef CFG_PCISPEED_66
+#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
+#endif
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+/* automatic configuration of chip selects */
+#ifdef CONFIG_CS_AUTOCONF
+#define CONFIG_LAST_STAGE_INIT
+#endif
+
+/*
+ * SRAM - Do not map below 2 GB in address space, because this area is used
+ * for SDRAM autosizing.
+ */
+#define CFG_CS2_START		0xE5000000
+#define CFG_CS2_SIZE		0x80000		/* 512 kByte */
+#define CFG_CS2_CFG		0x0004D930
+
+/*
+ * Grafic controller - Do not map below 2 GB in address space, because this
+ * area is used for SDRAM autosizing.
+ */
+#define SM501_FB_BASE           0xE0000000
+#define CFG_CS1_START           (SM501_FB_BASE)
+#define CFG_CS1_SIZE            0x4000000       /* 64 MByte */
+#define CFG_CS1_CFG             0x8F48FF70
+#define SM501_MMIO_BASE         CFG_CS1_START + 0x03E00000
+
+#define CFG_CS_BURST            0x00000000
+#define CFG_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for flash and SM501 */
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h
new file mode 100755
index 0000000..9a1c559
--- /dev/null
+++ b/include/configs/armadillo.h
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the EP7312 board.
+ *
+ * Modified to work on Armadillo HT1070 ARM720T board
+ * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+/*#define	CONFIG_INIT_CRITICAL*/		/* undef for developing */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
+#define CONFIG_ARMADILLO 	1	/* on an Armadillo Board      */
+#define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
+#undef  CONFIG_ARM7_REVD	 	/* disable ARM720 REV.D Workarounds */
+
+#undef CONFIG_USE_IRQ			/* don't need them anymore */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
+#define CS8900_BASE		0x20000300 /* armadillo board */
+#define CS8900_BUS16		1
+#undef  CS8900_BUS32
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		1	/* we use Serial line 1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL) /* | CFG_CMD_JFFS2)*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS    	"root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200"
+
+#define CONFIG_BOOTCOMMAND	"bootm 40000 180000"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"ARMADILLO # "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x00040000	/* default load address	for armadillo: kernel img is here*/
+
+#define	CFG_HZ			2000		/* decrementer freq: 2 kHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB armadillo SDRAM */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE		0x00400000 /* 4 MB */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x20000)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment Sector	*/
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/assabet.h b/include/configs/assabet.h
new file mode 100755
index 0000000..1a69ebe
--- /dev/null
+++ b/include/configs/assabet.h
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * Configuation settings for the Intel Assabet board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SA1110		1	/* This is an SA1100 CPU        */
+#define CONFIG_ASSABET		1	/* on an Intel Assabet Board    */
+
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE       128	/* size rsrvd for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_LAN91C96	/* we have an SMC9194 on-board */
+#define CONFIG_LAN91C96_BASE	0x18000000
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on Intel Assabet */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_DHCP)
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySA0,115200n8 root=/dev/nfs ip=bootp"
+#define CONFIG_BOOTCOMMAND	"bootp;tftp;bootm"
+#define CFG_AUTOLOAD            "n"	/* No autoload */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory         */
+#define CFG_PROMPT		"Intel Assabet # "	/* Monitor Command Prompt       */
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size      */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args   */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START	0xc0400000	/* memtest works on     */
+#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM   */
+
+#undef  CFG_CLKS_IN_HZ
+
+#define CFG_LOAD_ADDR		0xc0000000	/* default load address */
+
+#define CFG_HZ			3686400	/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x0a	/* set core clock to 206MHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	/* we have 1 bank of SDRAM */
+#define PHYS_SDRAM_1		0xc0000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
+
+#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1 */
+#define PHYS_FLASH_SIZE		0x02000000	/* 32 MB */
+#define PHYS_FLASH_BANK_SIZE    0x01000000	/* 16 MB Banks */
+#define PHYS_FLASH_SECT_SIZE    0x00040000	/* 256 KB sectors (x2) */
+
+#define CFG_MONITOR_BASE        TEXT_BASE
+#define CFG_MONITOR_LEN         (256 * 1024)	/* Reserve 256 KB for Monitor */
+
+#if CFG_MONITOR_BASE < CFG_FLASH_BASE
+#define CFG_RAMSTART
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CFG_FLASH_SIZE          PHYS_FLASH_SIZE
+#define CFG_FLASH_CFI           1	/* flash is CFI conformant      */
+#define CFG_FLASH_CFI_DRIVER    1	/* use common cfi driver        */
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_BANKS     1	/* max # of memory banks        */
+#define CFG_FLASH_INCREMENT     0	/* there is only one bank       */
+#define CFG_MAX_FLASH_SECT      128	/* max # of sectors on one chip */
+#undef CFG_FLASH_PROTECTION
+#define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
+
+#define CFG_ENV_IS_IN_FLASH	1
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_IN_OWN_SECTOR	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
+#define CFG_ENV_SIZE		PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
new file mode 100755
index 0000000..8fad55d
--- /dev/null
+++ b/include/configs/at91rm9200dk.h
@@ -0,0 +1,234 @@
+/*
+ * Rick Bronson <rick@efn.org>
+ *
+ * Configuation settings for the AT91RM9200DK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
+#define AT91C_MASTER_CLOCK	59904000	/* peripheral clock (AT91C_MASTER_CLOCK / 3) */
+/* #define AT91C_MASTER_CLOCK	44928000 */	/* peripheral clock (AT91C_MASTER_CLOCK / 4) */
+
+#define AT91_SLOW_CLOCK		32768	/* slow clock */
+
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
+#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
+#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	*/
+#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+#define USE_920T_MMU		1
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CFG_USE_MAIN_OSCILLATOR		1
+/* flash */
+#define MC_PUIA_VAL	0x00000000
+#define MC_PUP_VAL	0x00000000
+#define MC_PUER_VAL	0x00000000
+#define MC_ASR_VAL	0x00000000
+#define MC_AASR_VAL	0x00000000
+#define EBI_CFGR_VAL	0x00000000
+#define SMC2_CSR_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
+#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+
+/* sdram */
+#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define PIOC_BSR_VAL	0x00000000
+#define PIOC_PDR_VAL	0xFFFF0000
+#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
+#define SDRC_CR_VAL	0x2188c155 /* set up the SDRAM */
+#define SDRAM		0x20000000 /* address of the SDRAM */
+#define SDRAM1		0x20000080 /* address of the SDRAM */
+#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
+#define SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1	0x00000004 /* refresh */
+#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Hardware drivers
+ */
+
+/* define one of these to choose the DBGU, USART0  or USART1 as console */
+#define CONFIG_DBGU
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+
+#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/
+
+#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */
+
+#define CONFIG_BOOTDELAY      3
+/* #define CONFIG_ENV_OVERWRITE	1 */
+
+#define CONFIG_COMMANDS		\
+		       ((CONFIG_CMD_DFL | CFG_CMD_MII |\
+			CFG_CMD_DHCP ) & \
+		      ~(CFG_CMD_BDI | \
+			CFG_CMD_IMI | \
+			CFG_CMD_AUTOSCRIPT | \
+			CFG_CMD_FPGA | \
+			CFG_CMD_MISC | \
+			CFG_CMD_LOADS ))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define AT91_SMART_MEDIA_ALE (1 << 22)	/* our ALE is AD22 */
+#define AT91_SMART_MEDIA_CLE (1 << 21)	/* our CLE is AD21 */
+
+#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
+#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
+
+#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+/* the following are NOP's in our implementation */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x2000000  /* 32 megs */
+
+#define CFG_MEMTEST_START		PHYS_SDRAM
+#define CFG_MEMTEST_END			CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
+
+#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_AT91C_USE_RMII
+
+#define CONFIG_HAS_DATAFLASH		1
+#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS 	2
+#define CFG_MAX_DATAFLASH_PAGES 	16384
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
+#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
+
+#define PHYS_FLASH_1			0x10000000
+#define PHYS_FLASH_SIZE			0x200000  /* 2 megs main flash */
+#define CFG_FLASH_BASE			PHYS_FLASH_1
+#define CFG_MAX_FLASH_BANKS		1
+#define CFG_MAX_FLASH_SECT		256
+#define CFG_FLASH_ERASE_TOUT		(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2*CFG_HZ) /* Timeout for Flash Write */
+
+#undef	CFG_ENV_IS_IN_DATAFLASH
+
+#ifdef CFG_ENV_IS_IN_DATAFLASH
+#define CFG_ENV_OFFSET			0x20000
+#define CFG_ENV_ADDR			(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE			0x2000  /* 0x8000 */
+#else
+#define CFG_ENV_IS_IN_FLASH		1
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CFG_ENV_ADDR			(PHYS_FLASH_1 + 0x60000)  /* after u-boot.bin */
+#define CFG_ENV_SIZE			0x10000 /* sectors are 64K here */
+#else
+#define CFG_ENV_ADDR			(PHYS_FLASH_1 + 0xe000)  /* between boot.bin and u-boot.bin.gz */
+#define CFG_ENV_SIZE			0x2000  /* 0x8000 */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+#endif	/* CFG_ENV_IS_IN_DATAFLASH */
+
+
+#define CFG_LOAD_ADDR		0x21000000  /* default load address */
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CFG_BOOT_SIZE		0x00 /* 0 KBytes */
+#define CFG_U_BOOT_BASE		PHYS_FLASH_1
+#define CFG_U_BOOT_SIZE		0x60000 /* 384 KBytes */
+#else
+#define CFG_BOOT_SIZE		0x6000 /* 24 KBytes */
+#define CFG_U_BOOT_BASE		(PHYS_FLASH_1 + 0x10000)
+#define CFG_U_BOOT_SIZE		0x10000 /* 64 KBytes */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+
+#ifndef __ASSEMBLY__
+/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext {
+	/* helper variable for board environment handling
+	 *
+	 * env_crc_valid == 0    =>   uninitialised
+	 * env_crc_valid  > 0    =>   environment crc in flash is valid
+	 * env_crc_valid  < 0    =>   environment crc in flash is invalid
+	 */
+	int env_crc_valid;
+};
+#endif
+
+#define CFG_HZ 1000
+#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
+					/* AT91C_TC_TIMER_DIV1_CLOCK */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/atc.h b/include/configs/atc.h
new file mode 100755
index 0000000..bf6c170
--- /dev/null
+++ b/include/configs/atc.h
@@ -0,0 +1,509 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
+#define CONFIG_ATC		1	/* ...on a ATC board	*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define  CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else*/
+#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
+
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ *
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_ON_FCC
+
+#define	CONFIG_NET_MULTI
+#define CONFIG_ETHER_ON_FCC2
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#define CONFIG_ETHER_ON_FCC3
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK16
+ * - RAM for BD/Buffers is on the local Bus (see 28-13)
+ * - Enable Half Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	64000000	/* in Hz */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#undef	CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in Hz */
+
+#define CONFIG_PREBOOT							\
+	"echo;"								\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND						\
+	"bootp;"							\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=${serverip}:${rootpath} " 				\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
+	"bootm"
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configuration options
+ */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
+				 CFG_CMD_EEPROM | \
+				 CFG_CMD_PCI | \
+				 CFG_CMD_PCMCIA | \
+				 CFG_CMD_DATE | \
+				 CFG_CMD_IDE)
+
+
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/
+
+#define CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CFG_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
+
+#define CFG_ALLOC_DPRAM
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SPI
+
+#define CONFIG_RTC_DS12887
+
+#define RTC_BASE_ADDR 		0xF5000000
+#define RTC_PORT_ADDR 		RTC_BASE_ADDR + 0x800
+#define RTC_PORT_DATA 		RTC_BASE_ADDR + 0x808
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Flash configuration
+ */
+
+#define CFG_FLASH_BASE		0xFF000000
+#define CFG_FLASH_SIZE		0x00800000
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#define CONFIG_FLASH_16BIT
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
+				 HRCW_BPS10 |\
+				 HRCW_APPC10)
+
+/* no slaves so just fill with zeros */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00  /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CFG_SDRAM_BASE.
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT
+#endif
+
+#define	CONFIG_PCI
+#define	CONFIG_PCI_PNP
+#define	CFG_PCI_MSTR_IO_BUS	0x00000000	/* PCI base   */
+
+#if 1
+/* environment is in Flash */
+#define CFG_ENV_IS_IN_FLASH	1
+# define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x30000)
+# define CFG_ENV_SIZE		0x10000
+# define CFG_ENV_SECT_SIZE	0x10000
+#else
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_ENV_OFFSET		0
+#define CFG_ENV_SIZE		2048
+#define CFG_EEPROM_PAGE_WRITE_BITS	4	/* 16-byte page size	*/
+#endif
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot                 */
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
+			 HID0_DCI|HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CFG_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR         RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#define BCR_APD01	0x10000000
+#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR      (SIUMCR_BBD|SIUMCR_APPC10|\
+			 SIUMCR_CS10PC00|SIUMCR_BCTLC10)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR        SCCR_DFBRG01
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR        0
+
+#define CFG_MIN_AM_MASK	0xC0000000
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Refresh Timer Prescaler Register              10-18
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MPTPR       0x1F00
+
+/*-----------------------------------------------------------------------
+ * PSRT - Refresh Timer Register                                10-16
+ *-----------------------------------------------------------------------
+ */
+#define CFG_PSRT        0x0f
+
+/*-----------------------------------------------------------------------
+ * PSRT - SDRAM Mode Register                                   10-10
+ *-----------------------------------------------------------------------
+ */
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI1_A7		|\
+			 ORxS_NUMR_12)
+
+#define CFG_PSDMR_8COL	(PSDMR_PBI			|\
+			 PSDMR_SDAM_A15_IS_A5		|\
+			 PSDMR_BSMA_A15_A17		|\
+			 PSDMR_SDA10_PBI1_A7		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_3W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI1_A6		|\
+			 ORxS_NUMR_12)
+
+#define CFG_PSDMR_9COL	(PSDMR_PBI			|\
+			 PSDMR_SDAM_A16_IS_A5		|\
+			 PSDMR_BSMA_A15_A17		|\
+			 PSDMR_SDA10_PBI1_A6		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_3W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    8  bit  Boot ROM
+ *  1   60x     GPCM    64 bit  FLASH
+ *  2   60x     SDRAM   64 bit  SDRAM
+ *
+ */
+
+#define CFG_MRS_OFFS	0x00000000
+
+/* Bank 0 - FLASH
+ */
+#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_16                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
+
+
+/* Bank 2 - 60x bus SDRAM
+ */
+#ifndef CFG_RAMBOOT
+#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CFG_OR2_PRELIM	 CFG_OR2_8COL
+
+#define CFG_PSDMR	 CFG_PSDMR_8COL
+#endif /* CFG_RAMBOOT */
+
+#define CFG_BR4_PRELIM  ((RTC_BASE_ADDR & BRx_BA_MSK)   |\
+			 BRx_PS_8                       |\
+			 BRx_MS_UPMA                    |\
+			 BRx_V)
+
+#define CFG_OR4_PRELIM  (ORxU_AM_MSK | ORxU_BI)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_I82365
+
+#define CFG_PCMCIA_MEM_ADDR	0x81000000
+#define CFG_PCMCIA_MEM_SIZE	0x1000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	0xa0000000
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	0x100
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0x100
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x108
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h
new file mode 100755
index 0000000..eacc744
--- /dev/null
+++ b/include/configs/bamboo.h
@@ -0,0 +1,406 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * bamboo.h - configuration for BAMBOO board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_BAMBOO		1	/* Board is BAMBOO              */
+#define CONFIG_440EP		1	/* Specific PPC440EP support    */
+#define CONFIG_4xx		1	/* ... PPC4xx family	        */
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
+
+/*
+ * Please note that, if NAND support is enabled, the 2nd ethernet port
+ * can't be used because of pin multiplexing. So, if you want to use the
+ * 2nd ethernet port you have to "undef" the following define.
+ */
+#define CONFIG_BAMBOO_NAND      1       /* enable nand flash support    */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
+#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
+#define CFG_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
+#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
+#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
+#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
+
+/*Don't change either of these*/
+#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
+#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
+/*Don't change either of these*/
+
+#define CFG_USB_DEVICE          0x50000000
+#define CFG_NVRAM_BASE_ADDR     0x80000000
+#define CFG_BOOT_BASE_ADDR      0xf0000000
+#define CFG_NAND_ADDR           0x90000000
+#define CFG_NAND2_ADDR          0x94000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CFG_INIT_RAM_END	(4 << 10)
+#define CFG_GBL_DATA_SIZE	256		    	/* num bytes initial data	*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI     1
+/* define this if you want console on UART1 */
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
+ * The DS1558 code assumes this condition
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE	        (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs     */
+#define CONFIG_RTC_DS1556	1		         /* DS1556 RTC		*/
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
+#define CFG_MAX_FLASH_SECT	256		    /* sectors per device   */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_ADDR0         0x555
+#define CFG_FLASH_ADDR1         0x2aa
+#define CFG_FLASH_WORD_SIZE     unsigned char
+
+#define CFG_FLASH_2ND_16BIT_DEV 1         /* bamboo has 8 and 16bit device      */
+#define CFG_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device    */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH related
+ *----------------------------------------------------------------------*/
+#define NAND_CMD_REG   (0x00) /* NandFlash Command Register */
+#define NAND_ADDR_REG  (0x04) /* NandFlash Address Register */
+#define NAND_DATA_REG  (0x08) /* NandFlash Data Register */
+#define NAND_ECC0_REG  (0x10) /* NandFlash ECC Register0 */
+#define NAND_ECC1_REG  (0x14) /* NandFlash ECC Register1 */
+#define NAND_ECC2_REG  (0x18) /* NandFlash ECC Register2 */
+#define NAND_ECC3_REG  (0x1C) /* NandFlash ECC Register3 */
+#define NAND_ECC4_REG  (0x20) /* NandFlash ECC Register4 */
+#define NAND_ECC5_REG  (0x24) /* NandFlash ECC Register5 */
+#define NAND_ECC6_REG  (0x28) /* NandFlash ECC Register6 */
+#define NAND_ECC7_REG  (0x2C) /* NandFlash ECC Register7 */
+#define NAND_CR0_REG   (0x30) /* NandFlash Device Bank0 Config Register */
+#define NAND_CR1_REG   (0x34) /* NandFlash Device Bank1 Config Register */
+#define NAND_CR2_REG   (0x38) /* NandFlash Device Bank2 Config Register */
+#define NAND_CR3_REG   (0x3C) /* NandFlash Device Bank3 Config Register */
+#define NAND_CCR_REG   (0x40) /* NandFlash Core Configuration Register */
+#define NAND_STAT_REG  (0x44) /* NandFlash Device Status Register */
+#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */
+#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */
+
+/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */
+#define NAND0_CMD_READ1_HALF1     0x00     /* Starting addr for 1rst half of registers */
+#define NAND0_CMD_READ1_HALF2     0x01     /* Starting addr for 2nd half of registers */
+#define NAND0_CMD_READ2           0x50
+#define NAND0_CMD_READ_ID         0x90
+#define NAND0_CMD_READ_STATUS     0x70
+#define NAND0_CMD_RESET           0xFF
+#define NAND0_CMD_PAGE_PROG       0x80
+#define NAND0_CMD_PAGE_PROG_TRUE  0x10
+#define NAND0_CMD_PAGE_PROG_DUMMY 0x11
+#define NAND0_CMD_BLOCK_ERASE     0x60
+#define NAND0_CMD_BLOCK_ERASE_END 0xD0
+
+#define CFG_MAX_NAND_DEVICE     1	/* Max number of NAND devices */
+#define SECTORSIZE              512
+
+#define ADDR_COLUMN             1
+#define ADDR_PAGE               2
+#define ADDR_COLUMN_PAGE        3
+
+#define NAND_ChipID_UNKNOWN     0x00
+#define NAND_MAX_FLOORS         1
+#define NAND_MAX_CHIPS          1
+
+#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0)
+#define WRITE_NAND(d, adr)      do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0)
+#define READ_NAND(adr)          (*(volatile u8 *)((ulong)adr+NAND_DATA_REG))
+#define NAND_WAIT_READY(nand)   while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01))
+
+/* not needed with 440EP NAND controller */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------------- */
+#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
+#undef CONFIG_DDR_ECC			/* don't use ECC			*/
+#define CFG_SIMULATE_SPD_EEPROM	0xff	/* simulate spd eeprom on this address	*/
+#define SPD_EEPROM_ADDRESS      {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE		0x200	    /* Size of Environment vars */
+#define CFG_ENV_OFFSET		0x0
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=bamboo\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/bamboo/uImage\0"				\
+	"kernel_addr=fff00000\0"					\
+	"ramdisk_addr=fff10000\0"					\
+	"load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0"		\
+	"update=protect off fff80000 ffffffff;era fff80000 ffffffff;"	\
+		"cp.b 100000 fff80000 80000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR        1
+
+#ifndef CONFIG_BAMBOO_NAND
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#endif /* CONFIG_BAMBOO_NAND */
+
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+#define CONFIG_NET_MULTI        1       /* required for netconsole      */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef CONFIG_440EP
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/*Comment this out to enable USB 1.1 device*/
+#define USB_2_0_DEVICE
+#endif /*CONFIG_440EP*/
+
+#ifdef CONFIG_BAMBOO_NAND
+#define _CFG_CMD_NAND CFG_CMD_NAND
+#else
+#define _CFG_CMD_NAND 0
+#endif /* CONFIG_BAMBOO_NAND */
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_USB	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_EXT2	| \
+				_CFG_CMD_NAND	| \
+				CFG_CMD_SNTP	)
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI          1       /* support kdi files            */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/barco.h b/include/configs/barco.h
new file mode 100755
index 0000000..624fa1d
--- /dev/null
+++ b/include/configs/barco.h
@@ -0,0 +1,364 @@
+/********************************************************************
+ *
+ * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
+ *
+ * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/include/configs/barco.h,v $
+ * $Revision: 1.2 $
+ * $Author: mleeman $
+ * $Date: 2005/02/21 12:48:58 $
+ *
+ * Last ChangeLog Entry
+ * $Log: barco.h,v $
+ * Revision 1.2  2005/02/21 12:48:58  mleeman
+ * update of copyright years (feedback wd)
+ *
+ * Revision 1.1  2005/02/14 09:29:25  mleeman
+ * moved barcohydra.h to barco.h
+ *
+ * Revision 1.4  2005/02/09 12:56:23  mleeman
+ * add generic header to track changes in sources
+ *
+ *
+ *******************************************************************/
+
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8245		1
+#define CONFIG_BARCOBCD_STREAMING	1
+
+#undef USE_DINK32
+
+#define CONFIG_CONS_INDEX     3               /* set to '3' for on-chip DUART */
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_DRAM_SPEED	100		/* MHz				*/
+
+#define CONFIG_BOOTARGS "mem=32M"
+
+/* Add support for a few extra bootp options like:
+ *	- File size
+ *	- DNS
+ */
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE | \
+				 CONFIG_BOOTP_DNS)
+
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL | \
+				  CFG_CMD_ELF    | \
+				  CFG_CMD_I2C 	 | \
+				  CFG_CMD_EEPROM | \
+				  CFG_CMD_PCI    )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
+#include <cmd_confdefs.h>
+
+#define CONFIG_HUSH_PARSER	1 /* use "hush" command parser */
+#define CONFIG_BOOTDELAY 	1
+#define CONFIG_BOOTCOMMAND 	"boot_default"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		1		/* undef to save memory		*/
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI				/* include pci support		*/
+#undef CONFIG_PCI_PNP
+#undef CFG_CMD_NET
+
+#define PCI_ENET0_IOADDR	0x80000000
+#define PCI_ENET0_MEMADDR	0x80000000
+#define	PCI_ENET1_IOADDR	0x81000000
+#define	PCI_ENET1_MEMADDR	0x81000000
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MAX_RAM_SIZE	0x02000000
+
+#define CONFIG_LOGBUFFER
+#ifdef	CONFIG_LOGBUFFER
+#define CFG_STDOUT_ADDR 	0x1FFC000
+#else
+#define CFG_STDOUT_ADDR 	0x2B9000
+#endif
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#if defined (USE_DINK32)
+#define CFG_MONITOR_LEN		0x00030000
+#define CFG_MONITOR_BASE	0x00090000
+#define CFG_RAMBOOT		1
+#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_INIT_RAM_END	0x10000
+#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#else
+#undef	CFG_RAMBOOT
+#define CFG_MONITOR_LEN		0x00030000
+#define CFG_MONITOR_BASE	TEXT_BASE
+
+#define CFG_GBL_DATA_SIZE	128
+
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x1000
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#endif
+
+#define CFG_FLASH_BASE		0xFFF00000
+#define CFG_FLASH_SIZE		(8 * 1024 * 1024)	/* Unity has onboard 1MByte flash */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x000047A4	/* Offset of Environment Sector */
+#define CFG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
+/* #define ENV_CRC		0x8BF6F24B	XXX - FIXME: gets defined automatically */
+
+#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+
+#define CFG_EUMB_ADDR		0xFDF00000
+
+#define CFG_FLASH_RANGE_BASE	0xFFC00000	/* flash memory address range	*/
+#define CFG_FLASH_RANGE_SIZE	0x00400000
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
+#define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/
+
+/*
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
+#undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#ifdef CONFIG_SOFT_I2C
+#error "Soft I2C is not configured properly.  Please review!"
+#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
+#define I2C_READ		((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
+				else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
+				else    iop->pdat &= ~0x00020000
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
+#define CFG_DBUS_SIZE2		1
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+
+ /*
+ * NS16550 Configuration (internal DUART)
+ */
+ /*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
+
+#define CFG_ROMNAL		0x0F	/*rom/flash next access time		*/
+#define CFG_ROMFAL		0x1E	/*rom/flash access time			*/
+
+#define CFG_REFINT	0x8F	/* no of clock cycles between CBR refresh cycles */
+
+/* the following are for SDRAM only*/
+#define CFG_BSTOPRE	0x25C	/* Burst To Precharge, sets open page interval */
+#define CFG_REFREC		8	/* Refresh to activate interval		*/
+#define CFG_RDLAT		4	/* data latency from read command	*/
+#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
+#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CFG_ACTORW		2	/* Activate to R/W			*/
+#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+
+#define CFG_REGISTERD_TYPE_BUFFER   1
+#define CFG_EXTROM 0
+#define CFG_REGDIMM 0
+
+
+/* memory bank settings*/
+/*
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CFG_BANK0_START		0x00000000
+#define CFG_BANK0_END		0x01FFFFFF
+#define CFG_BANK0_ENABLE	1
+#define CFG_BANK1_START		0x02000000
+#define CFG_BANK1_END		0x02ffffff
+#define CFG_BANK1_ENABLE	0
+#define CFG_BANK2_START		0x03f00000
+#define CFG_BANK2_END		0x03ffffff
+#define CFG_BANK2_ENABLE	0
+#define CFG_BANK3_START		0x04000000
+#define CFG_BANK3_END		0x04ffffff
+#define CFG_BANK3_ENABLE	0
+#define CFG_BANK4_START		0x05000000
+#define CFG_BANK4_END		0x05FFFFFF
+#define CFG_BANK4_ENABLE	0
+#define CFG_BANK5_START		0x06000000
+#define CFG_BANK5_END		0x06FFFFFF
+#define CFG_BANK5_ENABLE	0
+#define CFG_BANK6_START		0x07000000
+#define CFG_BANK6_END		0x07FFFFFF
+#define CFG_BANK6_ENABLE	0
+#define CFG_BANK7_START		0x08000000
+#define CFG_BANK7_END		0x08FFFFFF
+#define CFG_BANK7_ENABLE	0
+/*
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CFG_BANK_ENABLE		0x01
+
+#define CFG_ODCR		0xff	/* configures line driver impedances,	*/
+					/* see 8240 book for bit definitions	*/
+#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+/* SDRAM 0 - 256MB */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#if defined(USE_DINK32)
+#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
+#else
+#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#endif
+
+/* PCI memory */
+#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_CHECKSUM
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+/* values according to the manual */
+
+#define CONFIG_DRAM_50MHZ	1
+#define CONFIG_SDRAM_50MHZ
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
new file mode 100755
index 0000000..4a79835
--- /dev/null
+++ b/include/configs/bubinga.h
@@ -0,0 +1,432 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_BUBINGA	        1	/* ...on a BUBINGA board	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+
+#define CONFIG_NO_SERIAL_EEPROM
+/*#undef CONFIG_NO_SERIAL_EEPROM*/
+/*----------------------------------------------------------------------------*/
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*
+!-------------------------------------------------------------------------------
+! Defines for entry options.
+! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
+!       are plugged in the board will be utilized as non-ECC DIMMs.
+!-------------------------------------------------------------------------------
+*/
+#define        AUTO_MEMORY_CONFIG
+#define        DIMM_READ_ADDR 0xAB
+#define        DIMM_WRITE_ADDR 0xAA
+
+/*
+!-------------------------------------------------------------------------------
+! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
+! assuming a 33MHz input clock to the 405EP from the C9531.
+!-------------------------------------------------------------------------------
+*/
+#define PLLMR0_DEFAULT   PLLMR0_266_133_66
+#define PLLMR1_DEFAULT   PLLMR1_266_133_66
+
+#endif
+/*----------------------------------------------------------------------------*/
+
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ *       supported for backward compatibility.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#endif
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=bubinga\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/bubinga/uImage\0"				\
+	"kernel_addr=fff80000\0"					\
+	"ramdisk_addr=fff90000\0"					\
+	"load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0"		\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define	CONFIG_PHY_ADDR		1	/* PHY address			*/
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	2	/* EMAC1 PHY address		*/
+#define CONFIG_NET_MULTI	1
+#define CFG_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+#define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Bubinga	*/
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_CACHE	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#undef  CFG_EXT_SERIAL_CLOCK           /* external serial clock */
+#undef  CFG_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD       691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * I2C stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef  CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_NOPROBES	{ 0x69 }	/* avoid iprobe hangup (why?) */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
+
+#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
+#define CFG_I2C_EEPROM_ADDR	0x50	/* I2C boot EEPROM (24C02W)	*/
+#define CFG_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CFG_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host  */
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
+#define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * External peripheral base address
+ *-----------------------------------------------------------------------
+ */
+#define	CFG_KEY_REG_BASE_ADDR	0xF0100000
+#define	CFG_IR_REG_BASE_ADDR	0xF0200000
+#define	CFG_FPGA_REG_BASE_ADDR	0xF0300000
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SRAM_BASE		0xFFF00000
+#define CFG_FLASH_BASE		0xFFF80000
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_ADDR0         0x5555
+#define CFG_FLASH_ADDR1         0x2aaa
+#define CFG_FLASH_WORD_SIZE     unsigned char
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405EP CPU			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash/SRAM) initialization                                    */
+#define CFG_EBC_PB0AP           0x04006000
+#define CFG_EBC_PB0CR           0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 1 (NVRAM/RTC) initialization                                     */
+#define CFG_EBC_PB1AP           0x04041000
+#define CFG_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 2 (not used) initialization                                      */
+#define CFG_EBC_PB2AP           0x00000000
+#define CFG_EBC_PB2CR           0x00000000
+
+/* Memory Bank 2 (not used) initialization                                      */
+#define CFG_EBC_PB3AP           0x00000000
+#define CFG_EBC_PB3CR           0x00000000
+
+/* Memory Bank 4 (FPGA regs) initialization                                     */
+#define CFG_EBC_PB4AP           0x01815000
+#define CFG_EBC_PB4CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS      0x55
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]     - External Bus Controller BLAST output
+ * GPIO0[1-9]   - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CFG_GPIO0_OSRH          0x55555555
+#define CFG_GPIO0_OSRL          0x40000110
+#define CFG_GPIO0_ISR1H         0x00000000
+#define CFG_GPIO0_ISR1L         0x15555445
+#define CFG_GPIO0_TSRH          0x00000000
+#define CFG_GPIO0_TSRL          0x00000000
+#define CFG_GPIO0_TCR           0xFFFF8014
+
+/*-----------------------------------------------------------------------
+ * Some BUBINGA stuff...
+ */
+#define NVRAM_BASE      0xF0000000
+#define FPGA_REG0       0xF0300000    /* FPGA Reg 0              */
+#define FPGA_REG1       0xF0300001    /* FPGA Reg 1              */
+#define NVRVFY1     0x4f532d4f    /* used to determine if state data in */
+#define NVRVFY2     0x50454e00    /* NVRAM initialized (ascii for OS-OPEN)*/
+
+#define FPGA_REG0_F_RANGE     0x80       /* SDRAM PLL freq range              */
+#define FPGA_REG0_EXT_INT_DIS 0x20       /* External interface disable        */
+#define FPGA_REG0_LED_MASK    0x07       /* Board LEDs DS9, DS10, and DS11    */
+#define FPGA_REG0_LED0        0x04       /* Turn on LED0                      */
+#define FPGA_REG0_LED1        0x02       /* Turn on LED1                      */
+#define FPGA_REG0_LED2        0x01       /* Turn on LED2                      */
+
+#define FPGA_REG1_SSPEC_DIS   0x80       /* C9531 Spread Spectrum disabled    */
+#define FPGA_REG1_OFFBD_PCICLK 0x40      /* Onboard PCI clock selected       */
+#define FPGA_REG1_CLOCK_MASK  0x30       /* Mask for C9531 output freq select */
+#define FPGA_REG1_CLOCK_BIT_SHIFT  4
+#define FPGA_REG1_PCI_INT_ARB 0x08       /* PCI Internal arbiter selected     */
+#define FPGA_REG1_PCI_FREQ    0x04       /* PCI Frequency select              */
+#define FPGA_REG1_OFFB_FLASH  0x02       /* Off board flash                   */
+#define FPGA_REG1_SRAM_BOOT   0x01       /* SRAM at 0xFFF80000 not Flash      */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h
new file mode 100755
index 0000000..ae75539
--- /dev/null
+++ b/include/configs/c2mon.h
@@ -0,0 +1,418 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
+#define CONFIG_C2MON		1	/* ...on a C2MON module		*/
+
+#define CONFIG_80MHz		1	/* Running at 5 * 16 = 80 MHz	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_FEC_ENET		1	/* Use Fast Ethernet Controller	*/
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_PLPRCR							\
+		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else			/* up to 50 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif	/* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CFG_SCCR	(/* SCCR_TBS  | */ \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#else			/* up to 50 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif	/* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * PCMCIA Power Switch
+ *
+ * The C2MON uses a TPS2211A PC-Card Power-Interface Switch to
+ * control the voltages on the PCMCIA slot which is connected
+ * to Port C (all outputs) and Port B (Over-Current Input)
+ *-----------------------------------------------------------------------
+ */
+			/* Output pins */
+#define TPS2211_VCCD0	0x0002		/* PC.14 */
+#define TPS2211_VCCD1	0x0004		/* PC.13 */
+#define TPS2211_VPPD0	0x0008		/* PC.12 */
+#define TPS2211_VPPD1	0x0010		/* PC.11 */
+#define TPS2211_OUTPUTS ( TPS2211_VCCD0 | TPS2211_VCCD1 | \
+			  TPS2211_VPPD0 | TPS2211_VPPD1 )
+
+			/* Input pins */
+#define TPS2211_OC	0x00000200	/* PB.22: Over-Current		*/
+#define TPS2211_INPUTS	( TPS2211_OC )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+				 OR_SCY_5_CLK | OR_EHTR)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
new file mode 100755
index 0000000..2c160a4
--- /dev/null
+++ b/include/configs/canmb.h
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
+#define CONFIG_CANMB  		1	/* ... on canmb board - we need this for FEC.C */
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_IMMAP	| \
+				CFG_CMD_MII 	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * MUST be low boot - HIGHBOOT is not supported anymore
+ */
+#if (TEXT_BASE == 0xFE000000)		/* Boot low with 32 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT16	1
+#else
+#   error "TEXT_BASE must be 0xFE000000"
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=/tftpboot/canmb/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
+
+/*
+ * Flash configuration, expect one 16 Megabyte Bank at most
+ */
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_FLASH_SIZE		0x02000000
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		(2*128*1024)
+#define CFG_ENV_SIZE		0x2000
+#define CFG_ENV_SECT_SIZE       (128*1024)
+
+/*
+ * Memory map
+ *
+ * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
+ */
+#define CFG_MBAR			0xf0000000	/* DO NOT CHANGE this */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define	CONFIG_PHY_ADDR		0x0
+/*
+ * GPIO configuration:
+ * PSC1,2,3 predefined as UART
+ * PCI disabled
+ * Ethernet 100 with MD
+ */
+#define CFG_GPS_PORT_CONFIG	0x00058444
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#  define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x200000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x00047D01
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0x7f000000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
new file mode 100755
index 0000000..6997c7a
--- /dev/null
+++ b/include/configs/cerf250.h
@@ -0,0 +1,214 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the CERF250 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA250		1	/* This is an PXA250 CPU    */
+#define CONFIG_CERF250		1	/* on Cerf PXA Board	    */
+#define BOARD_LATE_INIT		1
+#define CONFIG_BAUDRATE		38400
+
+#undef 	CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE 0x04000300
+#define CONFIG_SMC_USE_32_BIT
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART	     1	/* we use FFUART on CERF PXA */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_ETHADDR		00:D0:CA:F1:3C:D2
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.0.5
+#define CONFIG_SERVERIP		192.168.0.2
+#define CONFIG_BOOTCOMMAND	"bootm 0xC0000"
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400"
+#define CONFIG_CMDLINE_TAG
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER		1
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#define CFG_LONGHELP					/* undef to save memory		*/
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT			"uboot$ "	/* Monitor Command Prompt */
+#else
+#define CFG_PROMPT			"=> "		/* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE			256			/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE 			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+										/* Print Buffer Size */
+#define CFG_MAXARGS			16			/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_DEVICE_NULLDEV	1
+
+#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ
+
+#define CFG_LOAD_ADDR		0xa2000000	/* default load address */
+
+#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	4	   		/* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1			0xa0000000 	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE		0x04000000 	/* 64 MB */
+#define PHYS_SDRAM_2			0xa4000000 	/* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE		0x00000000 	/* 0 MB */
+#define PHYS_SDRAM_3			0xa8000000 	/* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE		0x00000000 	/* 0 MB */
+#define PHYS_SDRAM_4			0xac000000 	/* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE		0x00000000 	/* 0 MB */
+
+#define PHYS_FLASH_1			0x00000000 	/* Flash Bank #1 */
+#define PHYS_FLASH_2			0x04000000 	/* Flash Bank #2 */
+#define PHYS_FLASH_SIZE			0x02000000 	/* 32 MB */
+#define PHYS_FLASH_BANK_SIZE		0x02000000 	/* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE		0x00040000 	/* 256 KB sectors (x2) */
+
+#define CFG_DRAM_BASE			0xa0000000
+#define CFG_DRAM_SIZE			0x04000000
+
+#define CFG_FLASH_BASE			PHYS_FLASH_1
+
+/*
+ * GPIO settings
+ */
+
+
+#define CFG_GPSR0_VAL		0x00408030
+#define CFG_GPSR1_VAL		0x00BFA882
+#define CFG_GPSR2_VAL		0x0001C000
+#define CFG_GPCR0_VAL		0xC0031100
+#define CFG_GPCR1_VAL		0xFC400300
+#define CFG_GPCR2_VAL		0x00003FFF
+#define CFG_GPDR0_VAL		0xC0439330
+#define CFG_GPDR1_VAL		0xFCFFAB82
+#define CFG_GPDR2_VAL		0x0001FFFF
+#define CFG_GAFR0_L_VAL		0x80000000
+#define CFG_GAFR0_U_VAL		0xA5000010
+#define CFG_GAFR1_L_VAL		0x60008018
+#define CFG_GAFR1_U_VAL		0xAAA5AAAA
+#define CFG_GAFR2_L_VAL		0xAAA0000A
+#define CFG_GAFR2_U_VAL		0x00000002
+
+#define CFG_PSSR_VAL		0x20
+
+/*
+ * Memory settings
+ */
+#define CFG_MSC0_VAL		0x12447FF0
+#define CFG_MSC1_VAL		0x12BC5554
+#define CFG_MSC2_VAL		0x7FF97FF1
+#define CFG_MDCNFG_VAL		0x00001AC9
+#define CFG_MDREFR_VAL		0x03CDC017
+#define CFG_MDMRS_VAL		0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL		0x00000000
+#define CFG_MCMEM0_VAL		0x00010504
+#define CFG_MCMEM1_VAL		0x00010504
+#define CFG_MCATT0_VAL		0x00010504
+#define CFG_MCATT1_VAL		0x00010504
+#define CFG_MCIO0_VAL		0x00004715
+#define CFG_MCIO1_VAL		0x00004715
+
+#define _LED			0x08000010	/*check this */
+#define LED_BLANK		0x08000040
+#define LED_GPIO		0x10
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	128  	/* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_MONITOR_LEN		0x40000		/* 256 KiB */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + CFG_MONITOR_LEN)
+#define CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h
new file mode 100755
index 0000000..5947c2a
--- /dev/null
+++ b/include/configs/cm4008.h
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2004
+ * Greg Ungerer <greg.ungerer@opengear.com>.
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_KS8695	1		/* it is a KS8695 CPU */
+#define CONFIG_CM4008	1		/* it is an OpenGear CM4008 boad */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+
+#define CONFIG_DRIVER_KS8695ETH		/* use KS8695 ethernet driver	*/
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CFG_ENV_IS_NOWHERE
+#define	CONFIG_SERIAL1
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#undef CONFIG_COMMANDS
+#define	CONFIG_COMMANDS		(CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV))
+
+#define CONFIG_BOOTDELAY	0
+#define CONFIG_BOOTARGS		"mem=16M console=ttyAM0,115200"
+#define CONFIG_BOOTCOMMAND	"gofsk 0x02200000"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00800000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x01000000	/* 16 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0x00008000	/* default load address */
+
+#define CFG_HZ			(1000)		/* 1ms resolution ticks */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
+
+#define PHYS_FLASH_1		0x02000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_SIZE		0x20000     /* Total Size of Environment */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h
new file mode 100755
index 0000000..e62fc06
--- /dev/null
+++ b/include/configs/cm41xx.h
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer <greg.ungerer@opengear.com>.
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_KS8695	1		/* it is a KS8695 CPU */
+#define CONFIG_CM41xx	1		/* it is an OpenGear CM41xx boad */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+
+#define CONFIG_DRIVER_KS8695ETH		/* use KS8695 ethernet driver	*/
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CFG_ENV_IS_NOWHERE
+#define	CONFIG_SERIAL1
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#undef CONFIG_COMMANDS
+#define	CONFIG_COMMANDS		(CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV))
+
+#define CONFIG_BOOTDELAY	0
+#define CONFIG_BOOTARGS		"mem=32M console=ttyAM0,115200"
+#define CONFIG_BOOTCOMMAND	"gofsk 0x02200000"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00800000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x01000000	/* 16 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0x00008000	/* default load address */
+
+#define CFG_HZ			(1000)		/* 1ms resolution ticks */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
+
+#define PHYS_FLASH_1		0x02000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_SIZE		0x20000     /* Total Size of Environment */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
new file mode 100755
index 0000000..46280f7
--- /dev/null
+++ b/include/configs/cmc_pu2.h
@@ -0,0 +1,253 @@
+/*
+ * 2004-2005 Gary Jennejohn <garyj@denx.de>
+ *
+ * Configuration settings for the CMC PU2 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
+#define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK/3)	/* peripheral clock */
+
+#define AT91_SLOW_CLOCK		32768	/* slow clock */
+
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
+#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
+#define CONFIG_CMC_PU2		1	/* on an CMC_PU2 Board		*/
+#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+#define USE_920T_MMU		1
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CFG_USE_MAIN_OSCILLATOR		1
+/* flash */
+#define MC_PUIA_VAL	0x00000000
+#define MC_PUP_VAL	0x00000000
+#define MC_PUER_VAL	0x00000000
+#define MC_ASR_VAL	0x00000000
+#define MC_AASR_VAL	0x00000000
+#define EBI_CFGR_VAL	0x00000000
+#define SMC2_CSR_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR_VAL	0x2026BE04 /* 179,712 MHz for PCK */
+#define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
+
+/* sdram */
+#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define PIOC_BSR_VAL	0x00000000
+#define PIOC_PDR_VAL	0xFFFF0000
+#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
+#define SDRC_CR_VAL	0x3399c1d4 /* set up the SDRAM */
+#define SDRAM		0x20000000 /* address of the SDRAM */
+#define SDRAM1		0x20000080 /* address of the SDRAM */
+#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
+#define SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1	0x00000004 /* refresh */
+#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+#define CONFIG_BAUDRATE		9600
+
+/*
+ * Hardware drivers
+ */
+
+/* define one of these to choose the DBGU, USART0  or USART1 as console */
+#undef CONFIG_DBGU
+#define CONFIG_USART0
+#undef CONFIG_USART1
+
+#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/
+
+#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */
+
+#define CONFIG_HARD_I2C
+
+#ifdef CONFIG_HARD_I2C
+#define CFG_I2C_SPEED		0	/* not used */
+#define CFG_I2C_SLAVE		0	/* not used */
+#define CONFIG_RTC_RS5C372A		/* RICOH I2C RTC */
+#define CFG_I2C_RTC_ADDR	0x32
+#define CFG_I2C_EEPROM_ADDR	0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW
+#endif
+/* still about 20 kB free with this defined */
+#define CFG_LONGHELP
+
+#define CONFIG_BOOTDELAY      3
+
+#ifdef CONFIG_HARD_I2C
+#define CONFIG_COMMANDS		\
+		       ((CONFIG_CMD_DFL	| \
+			CFG_CMD_DATE	| \
+			CFG_CMD_DHCP 	| \
+			CFG_CMD_EEPROM	| \
+			CFG_CMD_I2C	| \
+			CFG_CMD_NFS	| \
+			CFG_CMD_SNTP  ) & \
+		      ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
+#else
+#define CONFIG_COMMANDS		\
+		       ((CONFIG_CMD_DFL	| \
+			CFG_CMD_DHCP 	| \
+			CFG_CMD_NFS	| \
+			CFG_CMD_SNTP  ) & \
+		      ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
+#define CONFIG_TIMESTAMP
+#endif
+#define CFG_LONGHELP
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define AT91_SMART_MEDIA_ALE	(1 << 22)	/* our ALE is AD22 */
+#define AT91_SMART_MEDIA_CLE	(1 << 21)	/* our CLE is AD21 */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x20000000
+#define PHYS_SDRAM_SIZE		0x1000000 	/* 16 megs */
+
+#define CFG_MEMTEST_START	PHYS_SDRAM
+#define CFG_MEMTEST_END		CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
+
+#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_AT91C_USE_RMII
+
+#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS		2
+#define CFG_MAX_DATAFLASH_PAGES		16384
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
+#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
+
+#define PHYS_FLASH_1			0x10000000
+#define PHYS_FLASH_SIZE			0x800000  /* 8 megs main flash */
+#define CFG_FLASH_BASE			PHYS_FLASH_1
+#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+#define CFG_MAX_FLASH_BANKS		1
+#define CFG_MAX_FLASH_SECT		256
+#define CFG_FLASH_ERASE_TOUT		(11 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		( 2 * CFG_HZ)	/* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_OFFSET			0x20000		/* after u-boot.bin */
+#define CFG_ENV_SECT_SIZE		(64 << 10)	/* sectors are 64 kB */
+#define CFG_ENV_SIZE			(16 << 10)	/* Use only 16 kB */
+
+#define CFG_LOAD_ADDR		0x21000000  /* default load address */
+
+#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define CFG_MAXARGS		32		/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+
+#ifndef __ASSEMBLY__
+/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext {
+	/* helper variable for board environment handling
+	 *
+	 * env_crc_valid == 0	 =>   uninitialised
+	 * env_crc_valid  > 0	 =>   environment crc in flash is valid
+	 * env_crc_valid  < 0	 =>   environment crc in flash is invalid
+	 */
+	int env_crc_valid;
+};
+#endif	/* __ASSEMBLY__ */
+
+#define CFG_HZ 1000
+#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2)	/* AT91C_TC0_CMR is implicitly set to */
+						/* AT91C_TC_TIMER_DIV1_CLOCK */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#define CFG_DEVICE_NULLDEV	 1	/* enble null device		*/
+#define CONFIG_SILENT_CONSOLE	 1	/* enable silent startup	*/
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_STOP_STR "R"	/* default password */
+
+#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \
+		"addmtd;bootm\0" \
+	"nfsargs=setenv bootargs root=/dev/nfs rw " \
+		"nfsroot=${serverip}:${rootpath}\0" \
+	"net_cramfs=tftp ${loadaddr} ${bootfile}; run flashargs addip " \
+		"addcons addmtd; bootm\0" \
+	"flash_cramfs=run flashargs addip addcons addmtd; bootm 10030000\0" \
+	"flashargs=setenv bootargs root=/dev/mtdblock3 ro\0" \
+	"addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
+		"${hostname}::off\0" \
+	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmtd=setenv bootargs ${bootargs} mtdparts=cmc_pu2:128k(uboot)ro," \
+		"64k(environment),768k(linux),4096k(root),-\0" \
+	"load=tftp ${loadaddr} ${loadfile}\0" \
+	"update=protect off 10000000 1001ffff;erase 10000000 1001ffff; " \
+		"cp.b ${loadaddr} 10000000 ${filesize};" \
+		"protect on 10000000 1001ffff\0" \
+	"updatel=era 10030000 100effff;tftp ${loadaddr} ${bootfile}; " \
+		"cp.b ${loadaddr} 10030000 ${filesize}\0" \
+	"updatec=era 100f0000 104effff;tftp ${loadaddr} ${cramfsimage}; " \
+		"cp.b ${loadaddr} 100f0000 ${filesize}\0" \
+	"updatej=era 104f0000 107fffff;tftp ${loadaddr} ${jffsimage}; " \
+		"cp.b ${loadaddr} 104f0000 ${filesize}\0" \
+	"cramfsimage=cramfs_cmc-pu2.img\0" \
+	"jffsimage=jffs2_cmc-pu2.img\0" \
+	"loadfile=u-boot_cmc-pu2.bin\0" \
+	"bootfile=uImage_cmc-pu2\0" \
+	"loadaddr=0x20800000\0" \
+	"hostname=CMC-TC-PU2\0" \
+	"bootcmd=run dhcp_start;run flash_cramfs\0" \
+	"autoload=n\0" \
+	"dhcp_start=echo no DHCP\0" \
+	"ipaddr=192.168.0.190\0"
+#endif	/* __CONFIG_H */
diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h
new file mode 100755
index 0000000..e459919
--- /dev/null
+++ b/include/configs/cmi_mpc5xx.h
@@ -0,0 +1,256 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation,
+ */
+
+/*
+ * File:		cmi_mpc5xx.h
+ *
+ * Discription:		Config header file for cmi
+ * 			board  using an MPC5xx CPU
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_MPC555		1		/* This is an MPC555 CPU		*/
+#define CONFIG_CMI		1		/* Using the customized cmi board 	*/
+
+/* Serial Console Configuration */
+#define	CONFIG_5xx_CONS_SCI1
+#undef	CONFIG_5xx_CONS_SCI2
+
+#define CONFIG_BAUDRATE		57600
+
+#define CONFIG_COMMANDS		(CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | 		\
+				 CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ASKENV |   		\
+				 CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_ENV | CFG_CMD_RUN |	\
+				 CFG_CMD_IMI)
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if 0
+#define CONFIG_BOOTDELAY	-1		/* autoboot disabled			*/
+#else
+#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds		*/
+#endif
+#define CONFIG_BOOTCOMMAND	"go 02034004" 	/* autoboot command			*/
+
+#define CONFIG_BOOTARGS		""		/* Assuming OS Image in 4 flash sector at offset 4004 */
+
+#define CONFIG_WATCHDOG				/* turn on platform specific watchdog 	*/
+
+#define CONFIG_STATUS_LED	1		/* Enable status led */
+
+#define CONFIG_LOADS_ECHO	1		/* Echo on for serial download */
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	       /* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x000fa000	/* 1 MB in SRAM			*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address		*/
+
+#define	CFG_HZ			1000		/* Decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
+
+
+/*
+ * Low Level Configuration Settings
+ */
+
+/*
+ * Internal Memory Mapped (This is not the IMMR content)
+ */
+#define CFG_IMMR		0x01000000				/* Physical start adress of internal memory map */
+
+/*
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_RAM_ADDR	(CFG_IMMR + 0x003f9800)      		/* Physical start adress of internal MPC555 writable RAM */
+#define	CFG_INIT_RAM_END	(CFG_IMMR + 0x003fffff)       		/* Physical end adress of internal MPC555 used RAM area	*/
+#define	CFG_GBL_DATA_SIZE	64					/* Size in bytes reserved for initial global data */
+#define CFG_GBL_DATA_OFFSET	((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
+#define	CFG_INIT_SP_ADDR	0x013fa000				/* Physical start adress of inital stack */
+
+/*
+ * Start addresses for the final memory configuration
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000	/* Monitor won't change memory map 			*/
+#define CFG_FLASH_BASE		0x02000000	/* External flash */
+#define PLD_BASE		0x03000000	/* PLD  */
+#define ANYBUS_BASE		0x03010000	/* Anybus Module */
+
+#define CFG_RESET_ADRESS	0x01000000	/* Adress which causes reset */
+#define	CFG_MONITOR_BASE	CFG_FLASH_BASE	/* TEXT_BASE is defined in the board config.mk file. 	*/
+						/* This adress is given to the linker with -Ttext to 	*/
+						/* locate the text section at this adress. 		*/
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor				*/
+#define	CFG_MALLOC_LEN		(64 << 10)	/* Reserve 128 kB for malloc()				*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/
+
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ *-----------------------------------------------------------------------
+ *
+ */
+
+#define CFG_MAX_FLASH_BANKS	1		/* Max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	64		/* Max number of sectors on one chip 	*/
+#define CFG_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms) 	*/
+#define CFG_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms) 	*/
+#define CFG_FLASH_PROTECTION    1		/* Physically section protection on	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_OFFSET		0x00020000		/* Environment starts at this adress 	*/
+#define	CFG_ENV_SIZE		0x00010000		/* Set whole sector as env 		*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWP)
+#endif	/* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+#define CFG_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
+			 SCCR_COM00   | SCCR_DFNL000 | SCCR_DFNH000)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration
+ *-----------------------------------------------------------------------
+ * Data show cycle
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00)		/* Disable data show cycle 	*/
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register
+ *-----------------------------------------------------------------------
+ * Set all bits to 40 Mhz
+ *
+ */
+#define CFG_OSC_CLK   	((uint)4000000) 	/* Oscillator clock is 4MHz 	*/
+#define CFG_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
+
+
+/*-----------------------------------------------------------------------
+ * UMCR - UIMB Module Configuration Register
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_UMCR	(UMCR_FSPEED) 		/* IMB clock same as U-bus 	*/
+
+/*-----------------------------------------------------------------------
+ * ICTRL - I-Bus Support Control Register
+ */
+#define CFG_ICTRL	(ICTRL_ISCT_SER_7) 	/* Take out of serialized mode 	*/
+
+/*-----------------------------------------------------------------------
+ * USIU - Memory Controller Register
+ *-----------------------------------------------------------------------
+ */
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
+#define CFG_OR0_PRELIM		(OR_ADDR_MK_FF | OR_SCY_3)
+#define CFG_BR1_PRELIM		(ANYBUS_BASE)
+#define CFG_OR1_PRELIM		(OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
+#define CFG_BR2_PRELIM		(CFG_SDRAM_BASE | BR_V | BR_PS_32)
+#define CFG_OR2_PRELIM		(OR_ADDR_MK_FF)
+#define CFG_BR3_PRELIM		(PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
+#define CFG_OR3_PRELIM		(OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
+			 	 OR_ACS_10 | OR_ETHR | OR_CSNT)
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* We don't realign the flash	*/
+
+/*-----------------------------------------------------------------------
+ * DER - Timer Decrementer
+ *-----------------------------------------------------------------------
+ * Initialise to zero
+ */
+#define CFG_DER			0x00000000
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01			/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02			/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
new file mode 100755
index 0000000..9033fa8
--- /dev/null
+++ b/include/configs/cobra5272.h
@@ -0,0 +1,355 @@
+/*
+ * Configuation settings for the Sentec Cobra Board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ---
+ * Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board
+ * Date: 2004-03-29
+ * Author: Florian Schlote
+ *
+ * For a description of configuration options please refer also to the
+ * general u-boot-1.x.x/README file
+ * ---
+ */
+
+/* ---
+ * board/config.h - configuration options, board specific
+ * ---
+ */
+
+#ifndef _CONFIG_COBRA5272_H
+#define _CONFIG_COBRA5272_H
+
+/* ---
+ * Define processor
+ * possible values for Sentec board: only Coldfire M5272 processor supported
+ * (please do not change)
+ * ---
+ */
+
+#define CONFIG_MCF52x2			/* define processor family */
+#define CONFIG_M5272			/* define processor type */
+
+/* ---
+ * Defines processor clock - important for correct timings concerning serial
+ * interface etc.
+ * CFG_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
+ * ---
+ */
+
+#define CFG_HZ			1000
+#define CFG_CLK			66000000
+#define CFG_SDRAM_SIZE		16		/* SDRAM size in MB */
+
+/* ---
+ * Enable use of Ethernet
+ * ---
+ */
+
+#define FEC_ENET
+
+/* ---
+ * Define baudrate for UART1 (console output, tftp, ...)
+ * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
+ * CFG_BAUDRATE_TABLE defines values that can be selected in u-boot command
+ * interface
+ * ---
+ */
+
+#define CONFIG_BAUDRATE		19200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+/* ---
+ * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
+ * timeout acc. to your needs
+ * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
+ * for 10 sec
+ * ---
+ */
+
+#if 0
+#define CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
+#endif
+
+/* ---
+ * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
+ * bootloader residing in flash ('chainloading'); if you want to use
+ * chainloading or want to compile a u-boot binary that can be loaded into
+ * RAM via BDM set
+ * 	"#if 0" to "#if 1"
+ * You will need a first stage bootloader then, e. g. colilo or a working BDM
+ * cable (Background Debug Mode)
+ *
+ * Setting #if 0: u-boot will start from flash and relocate itself to RAM
+ *
+ * Please do not forget to modify the setting of TEXT_BASE
+ * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
+ *
+ * ---
+ */
+
+#if 0
+#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
+#endif
+
+/* ---
+ * Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ * ---
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_ENV_OFFSET		0x4000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_IS_EMBEDDED	1
+#else
+#define CFG_ENV_ADDR		0xffe04000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#endif
+
+/* ---
+ * Define which commmands should be available at u-boot command prompt
+ * ---
+ */
+
+#define CONFIG_COMMANDS	 ( CONFIG_CMD_DFL | CFG_CMD_PING & ~(CFG_CMD_LOADS | \
+CFG_CMD_LOADB) | CFG_CMD_MII)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ *-----------------------------------------------------------------------------
+ * Define user parameters that have to be customized most likely
+ *-----------------------------------------------------------------------------
+ */
+
+/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
+
+#define CONFIG_BOOTDELAY	5		/* used for autoboot, delay in
+seconds u-boot will wait before starting defined (auto-)boot command, setting
+to -1 disables delay, setting to 0 will too prevent access to u-boot command
+interface: u-boot then has to reflashed */
+
+
+/* The following settings will be contained in the environment block ; if you
+want to use a neutral environment all those settings can be manually set in
+u-boot: 'set' command */
+
+#if 0
+
+#define CONFIG_BOOTCOMMAND	"bootm 0xffe80000"	/*Autoboto command, please
+enter a valid image address in flash */
+
+#define CONFIG_BOOTARGS		" "			/* default bootargs that are
+considered during boot */
+
+/* User network settings */
+
+#define CONFIG_ETHADDR 00:00:00:00:00:09	/* default ethernet MAC addr. */
+#define CONFIG_IPADDR 192.168.100.2		/* default board IP address */
+#define CONFIG_SERVERIP 192.168.100.1	/* default tftp server IP address */
+
+#endif
+
+#define CFG_PROMPT		"COBRA > "	/* Layout of u-boot prompt*/
+
+#define CFG_LOAD_ADDR		0x20000		/*Defines default RAM address
+from which user programs will be started */
+
+/*---*/
+
+#define CFG_LONGHELP				/* undef to save memory		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/*
+ *-----------------------------------------------------------------------------
+ * End of user parameters to be customized
+ *-----------------------------------------------------------------------------
+ */
+
+/* ---
+ * Defines memory range for test
+ * ---
+ */
+
+#define CFG_MEMTEST_START	0x400
+#define CFG_MEMTEST_END		0x380000
+
+/* ---
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * ---
+ */
+
+/* ---
+ * Base register address
+ * ---
+ */
+
+#define CFG_MBAR		0x10000000	/* Register Base Addrs */
+
+/* ---
+ * System Conf. Reg. & System Protection Reg.
+ * ---
+ */
+
+#define CFG_SCR			0x0003;
+#define CFG_SPR			0xffff;
+
+/* ---
+ * Ethernet settings
+ * ---
+ */
+
+#define CFG_DISCOVER_PHY
+#define CFG_ENET_BD_BASE	0x780000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in internal SRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x20000000
+#define CFG_INIT_RAM_END	0x1000	/* End of used area in internal SRAM	*/
+#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+
+/*
+ *-------------------------------------------------------------------------
+ * RAM SIZE (is defined above)
+ *-----------------------------------------------------------------------
+ */
+
+/* #define CFG_SDRAM_SIZE		16 */
+
+/*
+ *-----------------------------------------------------------------------
+ */
+
+#define CFG_FLASH_BASE		0xffe00000
+
+#ifdef	CONFIG_MONITOR_IS_IN_RAM
+#define CFG_MONITOR_BASE	0x20000
+#else
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#endif
+
+#define CFG_MONITOR_LEN		0x20000
+#define CFG_MALLOC_LEN		(256 << 10)
+#define CFG_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	11	/* max number of sectors on one chip	*/
+#define CFG_FLASH_ERASE_TOUT	1000	/* flash timeout */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ *
+ * Please refer also to Motorola Coldfire user manual - Chapter XXX
+ * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
+ */
+#define CFG_BR0_PRELIM		0xFFE00201
+#define CFG_OR0_PRELIM		0xFFE00014
+
+#define CFG_BR1_PRELIM		0
+#define CFG_OR1_PRELIM		0
+
+#define CFG_BR2_PRELIM		0
+#define CFG_OR2_PRELIM		0
+
+#define CFG_BR3_PRELIM		0
+#define CFG_OR3_PRELIM		0
+
+#define CFG_BR4_PRELIM		0
+#define CFG_OR4_PRELIM		0
+
+#define CFG_BR5_PRELIM		0
+#define CFG_OR5_PRELIM		0
+
+#define CFG_BR6_PRELIM		0
+#define CFG_OR6_PRELIM		0
+
+#define CFG_BR7_PRELIM		0x00000701
+#define CFG_OR7_PRELIM		0xFF00007C
+
+/*-----------------------------------------------------------------------
+ * LED config
+ */
+#define	LED_STAT_0	0xffff /*all LEDs off*/
+#define	LED_STAT_1	0xfffe
+#define	LED_STAT_2	0xfffd
+#define	LED_STAT_3	0xfffb
+#define	LED_STAT_4	0xfff7
+#define	LED_STAT_5	0xffef
+#define	LED_STAT_6	0xffdf
+#define	LED_STAT_7	0xff00 /*all LEDs on*/
+
+/*-----------------------------------------------------------------------
+ * Port configuration (GPIO)
+ */
+#define CFG_PACNT		0x00000000		/* PortA control reg.: All pins are external
+GPIO*/
+#define CFG_PADDR		0x00FF			/* PortA direction reg.: PA7 to PA0 are outputs
+(1^=output, 0^=input) */
+#define CFG_PADAT		LED_STAT_0		/* PortA value reg.: Turn all LED off */
+#define CFG_PBCNT		0x55554155		/* PortB control reg.: Ethernet/UART
+configuration */
+#define CFG_PBDDR		0x0000			/* PortB direction: All pins configured as inputs */
+#define CFG_PBDAT		0x0000			/* PortB value reg. */
+#define CFG_PDCNT		0x00000000		/* PortD control reg. */
+
+#endif	/* _CONFIG_COBRA5272_H */
diff --git a/include/configs/cogent_common.h b/include/configs/cogent_common.h
new file mode 100755
index 0000000..cdf5802
--- /dev/null
+++ b/include/configs/cogent_common.h
@@ -0,0 +1,208 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen, CSIRO-MST
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CONFIG_COGENT_COMMON_H
+#define _CONFIG_COGENT_COMMON_H
+
+/*
+ * Cogent Motherboard Capabilities
+ */
+#define CMA_MB_CAP_SERPAR	0x0001	/* has dual serial+parallel (16C552) */
+#define CMA_MB_CAP_LCD		0x0002	/* has LCD display (HD44780) */
+#define CMA_MB_CAP_FLASH	0x0004	/* has flash (E28F800B or AM29F800BB) */
+#define CMA_MB_CAP_RTC		0x0008	/* has RTC+NVRAM (MK48T02) */
+#define CMA_MB_CAP_ETHER	0x0010	/* has Ethernet (MB86964) */
+#define CMA_MB_CAP_SLOT1	0x0020	/* has CMABus slot 1 */
+#define CMA_MB_CAP_SLOT2	0x0040	/* has CMABus slot 2 */
+#define CMA_MB_CAP_SLOT3	0x0080	/* has CMABus slot 3 */
+#define CMA_MB_CAP_KBM		0x0100	/* has PS/2 keyboard+mouse (HT6542B) */
+#define CMA_MB_CAP_SER2		0x0200	/* has 2nd dual serial (16C2552) */
+#define CMA_MB_CAP_PCI		0x0400	/* has pci bridge (V360EPC) */
+#define CMA_MB_CAP_PCI_EXT	0x0800	/* can access extended pci space  */
+#define CMA_MB_CAP_PCI_ETHER	0x1000	/* has 10/100 ether on PCI (GD82559) */
+#define CMA_MB_CAP_PCI_VIDEO	0x2000	/* has video int'face on PCI (B69000) */
+#define CMA_MB_CAP_PCI_CARDBUS	0x4000	/* has Cardbus Ctlr on PCI (PD6832) */
+
+/*
+ * Cogent option sanity checking
+ */
+
+#if defined(CONFIG_MPC821) || defined(CONFIG_MPC823) || \
+      defined(CONFIG_MPC850) || defined(CONFIG_MPC860)
+
+/*
+ * check a PowerPC 8xx cpu module has been selected
+ */
+
+# if defined(CONFIG_CMA286_21)
+
+#  define COGENT_CPU_MODULE	"CMA286-21"
+
+# elif defined(CONFIG_CMA286_60_OLD)
+
+#  define COGENT_CPU_MODULE	"CMA286-60 (old)"
+
+# elif defined(CONFIG_CMA286_60)
+
+#  define COGENT_CPU_MODULE	"CMA286-60"
+
+# elif defined(CONFIG_CMA286_60P)
+
+#  define COGENT_CPU_MODULE	"CMA286-60P"
+
+# elif defined(CONFIG_CMA287_21)
+
+#  define COGENT_CPU_MODULE	"CMA287-21"
+
+# elif defined(CONFIG_CMA287_50)
+
+#  define COGENT_CPU_MODULE	"CMA287-50"
+
+# else
+
+#  error Cogent CPU Module must be a PowerPC MPC8xx module
+
+# endif
+
+#elif defined(CONFIG_MPC8260)
+
+/*
+ * check a PowerPC 8260 cpu module has been selected
+ */
+
+# if defined(CONFIG_CMA282)
+
+#  define COGENT_CPU_MODULE	"CMA282"
+
+# else
+
+#  error Cogent CPU Module must be a PowerPC MPC8260 module
+
+# endif
+
+#else
+
+# error CPU type must be PowerPC 8xx or 8260
+
+#endif
+
+/*
+ * check a motherboard has been selected
+ * define the motherboard capabilities while we're at it
+ */
+
+#if defined(CONFIG_CMA101)
+
+# define COGENT_MOTHERBOARD	"CMA101"
+# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
+				 CMA_MB_CAP_RTC | CMA_MB_CAP_ETHER | \
+				 CMA_MB_CAP_SLOT1 | CMA_MB_CAP_SLOT2 | \
+				 CMA_MB_CAP_SLOT3)
+# define CMA_MB_NSLOTS		3
+
+#elif defined(CONFIG_CMA102)
+
+# define COGENT_MOTHERBOARD	"CMA102"
+# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
+				 CMA_MB_CAP_RTC | CMA_MB_CAP_SLOT1 | \
+				 CMA_MB_CAP_SLOT2 | CMA_MB_CAP_SLOT3)
+# define CMA_MB_NSLOTS		3
+
+#elif defined(CONFIG_CMA110)
+
+# define COGENT_MOTHERBOARD	"CMA110"
+# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
+				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
+				 CMA_MB_CAP_KBM | CMA_MB_CAP_PCI)
+# define CMA_MB_NSLOTS		0
+
+#elif defined(CONFIG_CMA111)
+
+# define COGENT_MOTHERBOARD	"CMA111"
+# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
+				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
+				 CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \
+				 CMA_MB_CAP_PCI | CMA_MB_CAP_PCI_EXT | \
+				 CMA_MB_CAP_PCI_ETHER)
+# define CMA_MB_NSLOTS		1
+
+#elif defined(CONFIG_CMA120)
+
+# define COGENT_MOTHERBOARD	"CMA120"
+# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
+				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
+				 CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \
+				 CMA_MB_CAP_SER2 | CMA_MB_CAP_PCI | \
+				 CMA_MB_CAP_PCI_EXT | CMA_MB_CAP_PCI_ETHER | \
+				 CMA_MB_CAP_PCI_VIDEO | CMA_MB_CAP_PCI_CARDBUS)
+# define CMA_MB_NSLOTS		1
+
+#elif defined(CONFIG_CMA150)
+
+# define COGENT_MOTHERBOARD	"CMA150"
+# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
+				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
+				 CMA_MB_CAP_KBM)
+# define CMA_MB_NSLOTS		0
+
+#else
+
+# error Cogent Motherboard either unsupported or undefined
+
+#endif
+
+/*
+ * check a flash i/o module has been selected if no flash on m/b
+ */
+
+#if defined(CONFIG_CMA302)
+
+# define COGENT_FLASH_MODULE	"CMA302"
+
+#elif (CMA_MB_CAPS & CMA_MB_CAP_FLASH) == 0
+
+# error Cogent Flash I/O module (e.g. CMA302) is required with this Motherboard
+
+#endif
+
+/*
+ * some further sanity checks
+ */
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) && (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
+#error Cogent Sanity Check: Both Slot2 and PCI are defined
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI)
+#error Extended PCI capability defined without PCI capability
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_ETHER) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI)
+#error Motherboard ethernet capability defined without PCI capability
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) && !(CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
+#error 2nd dual serial capability defined without serial/parallel capability
+#endif
+#include "../board/cogent/mb.h"
+#endif	/* _CONFIG_COGENT_COMMON_H */
diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h
new file mode 100755
index 0000000..aea2e64
--- /dev/null
+++ b/include/configs/cogent_mpc8260.h
@@ -0,0 +1,404 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Config header file for Cogent platform using an MPC8xx CPU module
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
+#define CONFIG_COGENT		1	/* using Cogent Modular Architecture */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+
+/* Cogent Modular Architecture options */
+#define CONFIG_CMA282		1	/* ...on a CMA282 CPU module	*/
+#define CONFIG_CMA111		1	/* ...on a CMA111 motherboard	*/
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define	CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else*/
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+#undef	CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
+#define	CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
+#define	CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
+#undef	CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
+#define	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX	1	/* which channel for ether	*/
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+#define CONFIG_COMMANDS		((CONFIG_CMD_DFL|CFG_CMD_KGDB)&~CFG_CMD_NET)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#ifdef DEBUG
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_BOOTCOMMAND	"bootm 04080000 04200000" /* autoboot command*/
+
+#define CONFIG_BOOTARGS		"root=/dev/ram rw"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define	CONFIG_KGDB_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
+#define	CONFIG_KGDB_EXTC_RATE	3686400	/* serial ext clk rate in Hz */
+#define	CONFIG_KGDB_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
+# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port at */
+# else
+#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
+# endif
+#endif
+
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Low Level Cogent settings
+ * if CFG_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
+ * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
+ * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
+ * (second 2 for CMA120 only)
+ */
+#define CFG_CMA_MB_BASE		0x00000000	/* base of m/b address space */
+
+#include <configs/cogent_common.h>
+
+#ifdef CONFIG_CONS_NONE
+#define CFG_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
+#endif
+#define CFG_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
+#define CONFIG_SHOW_ACTIVITY
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
+/*
+ * flash exists on the motherboard
+ * set these four according to TOP dipsw:
+ * TOP on  => ..._FLLOW_...	(boot EPROM space is high so FLASH is low )
+ * TOP off => ..._FLHIGH_...	(boot EPROM space is low  so FLASH is high)
+ */
+#define CMA_MB_FLASH_EXEC_BASE	CMA_MB_FLLOW_EXEC_BASE
+#define CMA_MB_FLASH_EXEC_SIZE	CMA_MB_FLLOW_EXEC_SIZE
+#define CMA_MB_FLASH_RDWR_BASE	CMA_MB_FLLOW_RDWR_BASE
+#define CMA_MB_FLASH_RDWR_SIZE	CMA_MB_FLLOW_RDWR_SIZE
+#endif
+#define CMA_MB_FLASH_BASE	CMA_MB_FLASH_EXEC_BASE
+#define CMA_MB_FLASH_SIZE	CMA_MB_FLASH_EXEC_SIZE
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#define CFG_HRCW_MASTER	(HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
+			 HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
+/* no slaves so just duplicate the master hrcw */
+#define CFG_HRCW_SLAVE1	CFG_HRCW_MASTER
+#define CFG_HRCW_SLAVE2	CFG_HRCW_MASTER
+#define CFG_HRCW_SLAVE3	CFG_HRCW_MASTER
+#define CFG_HRCW_SLAVE4	CFG_HRCW_MASTER
+#define CFG_HRCW_SLAVE5	CFG_HRCW_MASTER
+#define CFG_HRCW_SLAVE6	CFG_HRCW_MASTER
+#define CFG_HRCW_SLAVE7	CFG_HRCW_MASTER
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		CMA_MB_RAM_BASE
+#ifdef CONFIG_CMA302
+#define CFG_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
+#else
+#define CFG_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
+#endif
+#define	CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
+#define CFG_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		CFG_FLASH_BASE /* Addr of Environment Sector */
+#ifdef CONFIG_CMA302
+#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
+#else
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CFG_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register					 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CFG_RMR		RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR		BCR_EBM
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR	(SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				 4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR	(SCCR_DFBRG01)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR	0
+
+#if defined(CONFIG_CMA282)
+
+/*
+ * Init Memory Controller:
+ *
+ * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
+ * and CS2 for (optional) local bus RAM on the CPU module.
+ *
+ * Note the motherboard address space (256 Mbyte in size) is connected
+ * to the 60x Bus and is located starting at address 0. The Hard Reset
+ * Configuration Word should put the 60x Bus into External Bus Mode, since
+ * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
+ *
+ * (the *_SIZE vars must be a power of 2)
+ */
+
+#define CFG_CMA_CS0_BASE	TEXT_BASE	/* EPROM */
+#define CFG_CMA_CS0_SIZE	(1 << 20)
+#if 0
+#define CFG_CMA_CS2_BASE	0x10000000	/* Local Bus SDRAM */
+#define CFG_CMA_CS2_SIZE	(16 << 20)
+#endif
+
+/*
+ * CS0 maps the EPROM on the cpu module
+ * Set it for 10 wait states, address CFG_MONITOR_BASE and size 1M
+ *
+ * Note: We must have already transferred control to the final location
+ * of the EPROM before these are used, because when BR0/OR0 are set, the
+ * mirror of the eprom at any other addresses will disappear.
+ */
+
+/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
+#define CFG_BR0_PRELIM	((CFG_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
+/* mask size CFG_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
+#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_CMA_CS0_SIZE)|\
+				ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
+
+/*
+ * CS2 enables the Local Bus SDRAM on the CPU Module
+ *
+ * Will leave this unset for the moment, because a) my CPU module has no
+ * SDRAM installed (it is optional); and b) it will require programming
+ * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
+ * if you can't test it.
+ */
+
+#if 0
+/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, ??? */
+#define CFG_BR0_PRELIM	((CFG_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
+/* mask size CFG_CMA_CS2_SIZE, CS time normal, ??? */
+#define CFG_OR2_PRELIM	((~(CFG_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
+#endif
+
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h
new file mode 100755
index 0000000..80962d3
--- /dev/null
+++ b/include/configs/cogent_mpc8xx.h
@@ -0,0 +1,360 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Config header file for Cogent platform using an MPC8xx CPU module
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is an MPC860 CPU	*/
+#define CONFIG_COGENT		1	/* using Cogent Modular Architecture */
+
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+
+/* Cogent Modular Architecture options */
+#define CONFIG_CMA286_60_OLD	1	/* ...on an old CMA286-60 CPU module */
+#define CONFIG_CMA102		1	/* ...on a CMA102 motherboard	*/
+#define CONFIG_CMA302		1	/* ...with a CMA302 flash I/O module */
+
+/* serial console configuration */
+#undef	CONFIG_8xx_CONS_SMC1
+#undef	CONFIG_8xx_CONS_SMC2
+#define CONFIG_8xx_CONS_NONE	/* not on 8xx serial ports (eg on cogent m/b) */
+
+#if defined(CONFIG_CMA286_60_OLD)
+#define CONFIG_8xx_GCLK_FREQ	33333000 /* define if cant use get_gclk_freq */
+#endif
+
+#define CONFIG_BAUDRATE		230400
+
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#define CFG_I2C_SPEED		400000  /* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+
+#define CONFIG_COMMANDS		((CONFIG_CMD_DFL | CFG_CMD_KGDB | CFG_CMD_I2C) & ~CFG_CMD_NET)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_BOOTCOMMAND	"bootm 04080000 04200000" /* autoboot command*/
+
+#define CONFIG_BOOTARGS		"root=/dev/ram rw"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#define	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which SMC/SCC channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+#define CONFIG_WATCHDOG			/* turn on platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_ALLOC_DPRAM
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Low Level Cogent settings
+ * if CFG_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
+ * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
+ * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
+ * (second 2 for CMA120 only)
+ */
+#define CFG_CMA_MB_BASE		0x00000000	/* base of m/b address space */
+
+#include <configs/cogent_common.h>
+
+#define CFG_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
+#define CONFIG_CONS_INDEX	1
+#define CFG_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
+#define CONFIG_SHOW_ACTIVITY
+#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
+/*
+ * flash exists on the motherboard
+ * set these four according to TOP dipsw:
+ * TOP on  => ..._FLLOW_...	(boot EPROM space is high so FLASH is low )
+ * TOP off => ..._FLHIGH_...	(boot EPROM space is low  so FLASH is high)
+ */
+#define CMA_MB_FLASH_EXEC_BASE	CMA_MB_FLLOW_EXEC_BASE
+#define CMA_MB_FLASH_EXEC_SIZE	CMA_MB_FLLOW_EXEC_SIZE
+#define CMA_MB_FLASH_RDWR_BASE	CMA_MB_FLLOW_RDWR_BASE
+#define CMA_MB_FLASH_RDWR_SIZE	CMA_MB_FLLOW_RDWR_SIZE
+#endif
+#define CMA_MB_FLASH_BASE	CMA_MB_FLASH_EXEC_BASE
+#define CMA_MB_FLASH_SIZE	CMA_MB_FLASH_EXEC_SIZE
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		CMA_MB_RAM_BASE
+#ifdef CONFIG_CMA302
+#define CFG_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
+#else
+#define CFG_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
+#endif
+#define	CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		CFG_FLASH_BASE /* Addr of Environment Sector */
+#ifdef CONFIG_CMA302
+#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
+#else
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif	/* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CFG_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0
+
+#if defined(CONFIG_CMA286_60_OLD)
+
+/*
+ * Init Memory Controller:
+ *
+ * NOTE: although the names (CFG_xRn_PRELIM) suggest preliminary settings,
+ * they are actually the final settings for this cpu/board, because the
+ * flash and RAM are on the motherboard, accessed via the CMAbus, and the
+ * mappings are pretty much fixed.
+ *
+ * (the *_SIZE vars must be a power of 2)
+ */
+
+#define CFG_CMA_CS0_BASE	TEXT_BASE		/* EPROM */
+#define CFG_CMA_CS0_SIZE	(1 << 20)
+#define CFG_CMA_CS1_BASE	CMA_MB_RAM_BASE		/* RAM + I/O SLOT 1 */
+#define CFG_CMA_CS1_SIZE	(64 << 20)
+#define CFG_CMA_CS2_BASE	CMA_MB_SLOT2_BASE	/* I/O SLOTS 2 + 3 */
+#define CFG_CMA_CS2_SIZE	(64 << 20)
+#define CFG_CMA_CS3_BASE	CMA_MB_ROMLOW_BASE	/* M/B I/O */
+#define CFG_CMA_CS3_SIZE	(32 << 20)
+
+/*
+ * CS0 maps the EPROM on the cpu module
+ * Set it for 4 wait states, address CFG_MONITOR_BASE and size 1M
+ *
+ * Note: We must have already transferred control to the final location
+ * of the EPROM before these are used, because when BR0/OR0 are set, the
+ * mirror of the eprom at any other addresses will disappear.
+ */
+
+/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
+#define CFG_BR0_PRELIM	((CFG_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
+/* mask size CFG_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
+#define CFG_OR0_PRELIM	((~(CFG_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
+
+/*
+ * CS1 maps motherboard DRAM and motherboard I/O slot 1
+ * (each 32Mbyte in size)
+ */
+
+/* base address = CFG_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
+#define CFG_BR1_PRELIM	((CFG_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
+/* mask size CFG_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
+#define CFG_OR1_PRELIM	((~(CFG_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
+
+/*
+ * CS2 maps motherboard I/O slots 2 and 3
+ * (each 32Mbyte in size)
+ */
+
+/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
+#define CFG_BR2_PRELIM	((CFG_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
+/* mask size CFG_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
+#define CFG_OR2_PRELIM	((~(CFG_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
+
+/*
+ * CS3 maps motherboard I/O
+ * (32Mbyte in size)
+ */
+
+/* base address = CFG_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
+#define CFG_BR3_PRELIM	((CFG_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
+/* mask size CFG_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
+#define CFG_OR3_PRELIM	((~(CFG_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
+
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h
new file mode 100755
index 0000000..f9586fb
--- /dev/null
+++ b/include/configs/cpci5200.h
@@ -0,0 +1,417 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+
+ */
+
+/*************************************************************************
+ * (c) 2005 esd gmbh Hannover
+ *
+ *
+ * from IceCube.h file
+ * by Reinhard Arlt reinhard.arlt@esd-electronics.com
+ *
+ *************************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_ICECUBE		1	/* ... on IceCube board	  */
+#define CONFIG_CPCI5200		1	/* ... on CPCI5200  board */
+#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	  */
+
+#define CFG_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#ifdef CONFIG_MPC5200		/* MPC5100 PCI is not supported yet. */
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#if 1
+#define CONFIG_PCI		1
+#if 1
+#define CONFIG_PCI_PNP		1
+#endif
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+#endif
+
+#define CONFIG_MII
+#if 0				/* test-only !!! */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_EEPRO100		1
+#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+#define CONFIG_NS8382X		1
+#endif
+
+#define ADD_PCI_CMD		CFG_CMD_PCI
+
+#else				/* MPC5100 */
+
+#define ADD_PCI_CMD		0	/* no CFG_CMD_PCI */
+
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 0
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD		0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				 CFG_CMD_EEPROM	| \
+				 CFG_CMD_FAT	| \
+				 CFG_CMD_IDE	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_BSP	| \
+				 CFG_CMD_ELF	| \
+				 CFG_CMD_EXT2	| \
+				 CFG_CMD_DATE	| \
+				 ADD_PCI_CMD	  )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if (TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT16	1
+#endif
+#if (TEXT_BASE == 0xFF800000)	/* Boot low with  8 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT08	1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Welcome to esd CPU CPCI/5200;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=eth0\0" \
+	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
+	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
+	"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
+	"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
+	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
+	"loadaddr=01000000\0" \
+	"serverip=192.168.2.99\0" \
+	"gatewayip=10.0.0.79\0" \
+	"user=mu\0" \
+	"target=cpci5200.esd\0" \
+	"script=cpci5200.bat\0" \
+	"image=/tftpboot/vxWorks_cpci5200\0" \
+	"ipaddr=10.0.13.196\0" \
+	"netmask=255.255.0.0\0" \
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
+
+#if defined(CONFIG_MPC5200)
+
+#define CONFIG_RTC_M48T35A	1	/* ST Electronics M48 timekeeper */
+#define CFG_NVRAM_BASE_ADDR	0xfd010000
+#define CFG_NVRAM_SIZE		32*1024
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133		/* define for 133MHz speed */
+#endif
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		86000	/* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CFG_I2C_MULTI_EEPROMS		1
+/*
+ * Flash configuration
+ */
+
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant	     */
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_FLASH_SIZE		0x02000000
+#define CFG_FLASH_INCREMENT	0x01000000
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00000000)
+#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
+#define CFG_MAX_FLASH_SECT	128
+
+#define CFG_FLASH_PROTECTION	1	/* use hardware protection	     */
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)  */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+/*
+ * Environment settings
+ */
+#if 1				/* test-only */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x20000
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OVERWRITE	1
+#else
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x0000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x0400	/* 8192 bytes may be used for env vars */
+				   /* total size of a CAT24WC32 is 8192 bytes */
+#define CONFIG_ENV_OVERWRITE	1
+#endif
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_UDP_CHECKSUM	1
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG	0x01052444
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x0004DD00
+
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CFG_CS1_START		0xfd000000
+#define CFG_CS1_SIZE		0x00010000
+#define CFG_CS1_CFG		0x10101410
+
+#define CFG_CS3_START		0xfd010000
+#define CFG_CS3_SIZE		0x00010000
+#define CFG_CS3_CFG		0x10109410
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED		/* LED	 for ide not supported	*/
+
+#define	CONFIG_IDE_RESET	/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers						     */
+#define CFG_ATA_STRIDE		4
+
+/*-----------------------------------------------------------------------
+ * CPLD stuff
+ */
+#define CFG_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
+#define CFG_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */
+
+/* CPLD program pin configuration */
+#define CFG_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
+#define CFG_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
+#define CFG_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */
+
+#define JTAG_GPIO_ADDR_TMS	(CFG_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
+#define JTAG_GPIO_ADDR_TCK	(CFG_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
+#define JTAG_GPIO_ADDR_TDI	(CFG_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
+#define JTAG_GPIO_ADDR_TDO	(CFG_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */
+
+#define JTAG_GPIO_ADDR_CFG	(CFG_MBAR + 0xB00)
+#define JTAG_GPIO_CFG_SET	0x00000000
+#define JTAG_GPIO_CFG_RESET	0x00F00000
+
+#define JTAG_GPIO_ADDR_EN_TMS	(CFG_MBAR + 0xB04)
+#define JTAG_GPIO_TMS_EN_SET	0x20000000	/* Enable for GPIO */
+#define JTAG_GPIO_TMS_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TMS	(CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_TMS_DDR_SET	0x20000000	/* Set as output   */
+#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TCK	(CFG_MBAR + 0xC00)
+#define JTAG_GPIO_TCK_EN_SET	0x20000000	/* Enable for GPIO */
+#define JTAG_GPIO_TCK_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TCK	(CFG_MBAR + 0xC08)
+#define JTAG_GPIO_TCK_DDR_SET	0x20000000	/* Set as output   */
+#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDI	(CFG_MBAR + 0xC00)
+#define JTAG_GPIO_TDI_EN_SET	0x10000000	/* Enable as GPIO  */
+#define JTAG_GPIO_TDI_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDI	(CFG_MBAR + 0xC08)
+#define JTAG_GPIO_TDI_DDR_SET	0x10000000	/* Set as output   */
+#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDO	(CFG_MBAR + 0xB04)
+#define JTAG_GPIO_TDO_EN_SET	0x10000000	/* Enable as GPIO  */
+#define JTAG_GPIO_TDO_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDO	(CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_TDO_DDR_SET	0x00000000
+#define JTAG_GPIO_TDO_DDR_RESET 0x10000000	/* Set as input	   */
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/cradle.h b/include/configs/cradle.h
new file mode 100755
index 0000000..776e1d2
--- /dev/null
+++ b/include/configs/cradle.h
@@ -0,0 +1,349 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA250           1       /* This is an PXA250 CPU    */
+#define CONFIG_HHP_CRADLE       1       /* on an Cradle Board       */
+
+#undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE 0x10000300
+#define CONFIG_SMC91111_EXT_PHY
+#define CONFIG_SMC_USE_32_BIT
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART          1       /* we use FFUART on LUBBOCK */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE         115200
+
+#define CONFIG_COMMANDS         (CONFIG_CMD_DFL)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY        3
+#define CONFIG_BOOTARGS         "root=/dev/mtdblock2 console=ttyS0,115200"
+#define CONFIG_ETHADDR          08:00:3e:26:0a:5b
+#define CONFIG_NETMASK          255.255.0.0
+#define CONFIG_IPADDR           192.168.0.21
+#define CONFIG_SERVERIP         192.168.0.250
+#define CONFIG_BOOTCOMMAND      "bootm 40000"
+#define CONFIG_CMDLINE_TAG
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                            /* undef to save memory         */
+#define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
+#define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS             16              /* max number of command args   */
+#define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START       0xa0400000      /* memtest works on     */
+#define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
+
+#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR           0xa2000000      /* default load address */
+
+#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS    4          /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE       0x01000000 /* 64 MB */
+#define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2            0x04000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
+
+#define CFG_DRAM_BASE           0xa0000000
+#define CFG_DRAM_SIZE           0x04000000
+
+#define CFG_FLASH_BASE          PHYS_FLASH_1
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS     1     /* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT      32    /* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR				0x00020000	/* absolute address for now   */
+#define CFG_ENV_SIZE				0x20000	   /* 8K ouch, this may later be */
+
+/******************************************************************************
+ *
+ * CPU specific defines
+ *
+ ******************************************************************************/
+
+/*
+ * GPIO settings
+ *
+ * GPIO pin assignments
+ * GPIO     Name        Dir Out AF
+ * 0        NC
+ * 1        NC
+ * 2        SIRQ1       I
+ * 3        SIRQ2       I
+ * 4        SIRQ3       I
+ * 5        DMAACK1     O   0
+ * 6        DMAACK2     O   0
+ * 7        DMAACK3     O   0
+ * 8        TC1         O   0
+ * 9        TC2         O   0
+ * 10       TC3         O   0
+ * 11       nDMAEN      O   1
+ * 12       AENCTRL     O   0
+ * 13       PLDTC       O   0
+ * 14       ETHIRQ      I
+ * 15       NC
+ * 16       NC
+ * 17       NC
+ * 18       RDY         I
+ * 19       DMASIO      I
+ * 20       ETHIRQ      NC
+ * 21       NC
+ * 22       PGMEN       O   1    FIXME for debug only enable flash
+ * 23       NC
+ * 24       NC
+ * 25       NC
+ * 26       NC
+ * 27       NC
+ * 28       NC
+ * 29       NC
+ * 30       NC
+ * 31       NC
+ * 32       NC
+ * 33       NC
+ * 34       FFRXD       I       01
+ * 35       FFCTS       I       01
+ * 36       FFDCD       I       01
+ * 37       FFDSR       I       01
+ * 38       FFRI        I       01
+ * 39       FFTXD       O   1   10
+ * 40       FFDTR       O   0   10
+ * 41       FFRTS       O   0   10
+ * 42       RS232FOFF   O   0   00
+ * 43       NC
+ * 44       NC
+ * 45       IRSL0       O   0
+ * 46       IRRX0       I       01
+ * 47       IRTX0       O   0   10
+ * 48       NC
+ * 49       nIOWE       O   0
+ * 50       NC
+ * 51       NC
+ * 52       NC
+ * 53       NC
+ * 54       NC
+ * 55       NC
+ * 56       NC
+ * 57       NC
+ * 58       DKDIRQ      I
+ * 59       NC
+ * 60       NC
+ * 61       NC
+ * 62       NC
+ * 63       NC
+ * 64       COMLED      O   0
+ * 65       COMLED      O   0
+ * 66       COMLED      O   0
+ * 67       COMLED      O   0
+ * 68       COMLED      O   0
+ * 69       COMLED      O   0
+ * 70       COMLED      O   0
+ * 71       COMLED      O   0
+ * 72       NC
+ * 73       NC
+ * 74       NC
+ * 75       NC
+ * 76       NC
+ * 77       NC
+ * 78       CSIO        O   1
+ * 79       NC
+ * 80       CSETH       O   1
+ *
+ * NOTE: All NC's are defined to be outputs
+ *
+ */
+/* Pin direction control */
+/* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */
+#define CFG_GPDR0_VAL       0xfff3bf02
+#define CFG_GPDR1_VAL       0xfbffbf83
+#define CFG_GPDR2_VAL       0x0001ffff
+/* Set and Clear registers */
+#define CFG_GPSR0_VAL       0x00400800
+#define CFG_GPSR1_VAL       0x00000480
+#define CFG_GPSR2_VAL       0x00014000
+#define CFG_GPCR0_VAL       0x00000000
+#define CFG_GPCR1_VAL       0x00000000
+#define CFG_GPCR2_VAL       0x00000000
+/* Edge detect registers (these are set by the kernel) */
+#define CFG_GRER0_VAL       0x00000000
+#define CFG_GRER1_VAL       0x00000000
+#define CFG_GRER2_VAL       0x00000000
+#define CFG_GFER0_VAL       0x00000000
+#define CFG_GFER1_VAL       0x00000000
+#define CFG_GFER2_VAL       0x00000000
+/* Alternate function registers */
+#define CFG_GAFR0_L_VAL     0x00000000
+#define CFG_GAFR0_U_VAL     0x00000010
+#define CFG_GAFR1_L_VAL     0x900a9550
+#define CFG_GAFR1_U_VAL     0x00000008
+#define CFG_GAFR2_L_VAL     0x20000000
+#define CFG_GAFR2_U_VAL     0x00000002
+
+/*
+ * Clocks, power control and interrupts
+ */
+#define CFG_PSSR_VAL        0x00000020
+#define CFG_CCCR_VAL        0x00000141  /* 100 MHz memory, 200 MHz CPU  */
+#define CFG_CKEN_VAL        0x00000060  /* FFUART and STUART enabled    */
+#define CFG_ICMR_VAL        0x00000000  /* No interrupts enabled        */
+
+/* FIXME
+ *
+ * RTC settings
+ * Watchdog
+ *
+ */
+
+/*
+ * Memory settings
+ *
+ * FIXME Can ethernet be burst read and/or write?? This is set for lubbock
+ *       Verify timings on all
+ */
+#define CFG_MSC0_VAL        0x000023FA  /* flash bank    (cs0)   */
+/*#define CFG_MSC1_VAL        0x00003549  / * SuperIO bank  (cs2)   */
+#define CFG_MSC1_VAL        0x0000354c  /* SuperIO bank  (cs2)   */
+#define CFG_MSC2_VAL        0x00001224  /* Ethernet bank (cs4)   */
+#ifdef REDBOOT_WAY
+#define CFG_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
+#define CFG_MDMRS_VAL       0x00000000
+#define CFG_MDREFR_VAL      0x00018018
+#else
+#define CFG_MDCNFG_VAL      0x00001aa1  /* FIXME can DTC be 01?     */
+#define CFG_MDMRS_VAL       0x00000000
+#define CFG_MDREFR_VAL      0x00403018  /* Initial setting, individual bits set in lowlevel_init.S */
+#endif
+
+/*
+ * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
+ */
+#define CFG_MECR_VAL          0x00000000
+#define CFG_MCMEM0_VAL        0x00010504
+#define CFG_MCMEM1_VAL        0x00010504
+#define CFG_MCATT0_VAL        0x00010504
+#define CFG_MCATT1_VAL        0x00010504
+#define CFG_MCIO0_VAL         0x00004715
+#define CFG_MCIO1_VAL         0x00004715
+
+/* Board specific defines */
+
+/* LED defines */
+#define YELLOW    0x03
+#define RED       0x02
+#define GREEN     0x01
+#define OFF       0x00
+#define LED_IRDA0 0
+#define LED_IRDA1 2
+#define LED_IRDA2 4
+#define LED_IRDA3 6
+#define CRADLE_LED_SET_REG GPSR2
+#define CRADLE_LED_CLR_REG GPCR2
+
+/* SuperIO defines */
+#define CRADLE_SIO_INDEX      0x2e
+#define CRADLE_SIO_DATA       0x2f
+
+/* IO defines */
+#define CRADLE_CPLD_PHYS      0x08000000
+#define CRADLE_SIO1_PHYS      0x08100000
+#define CRADLE_SIO2_PHYS      0x08200000
+#define CRADLE_SIO3_PHYS      0x08300000
+#define CRADLE_ETH_PHYS       0x10000000
+
+#ifndef __ASSEMBLY__
+
+/* global prototypes */
+void led_code(int code, int color);
+
+#endif
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
new file mode 100755
index 0000000..f04102e
--- /dev/null
+++ b/include/configs/csb226.h
@@ -0,0 +1,472 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
+ *
+ * Configuration for the Cogent CSB226 board. For details see
+ * http://www.cogcomp.com/csb_csb226.htm
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * include/configs/csb226.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DEBUG 1
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA250 		1	/* This is an PXA250 CPU            */
+#define CONFIG_CSB226		1	/* on a CSB226 board                */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
+					/* for timer/console/ethernet       */
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART		1	/* we use FFUART on CSB226          */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		19200
+#undef  CONFIG_MISC_INIT_R		/* not used yet                     */
+
+#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_DHCP|CFG_CMD_CACHE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0"
+#define CONFIG_ETHADDR		FF:FF:FF:FF:FF:FF
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.1.56
+#define CONFIG_SERVERIP		192.168.1.5
+#define CONFIG_BOOTCOMMAND	"bootm 0x40000"
+#define CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_CMDLINE_TAG	1
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	19200		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+
+/*
+ * Size of malloc() pool; this lives below the uppermost 128 KiB which are
+ * used for the RAM copy of the uboot code
+ *
+ */
+#define CFG_MALLOC_LEN		(128*1024)
+#define CFG_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
+
+#define CFG_LONGHELP				/* undef to save memory         */
+#define CFG_PROMPT		"uboot> "	/* Monitor Command Prompt       */
+#define CFG_CBSIZE		128		/* Console I/O Buffer Size      */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args   */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START	0xa0400000      /* memtest works on     */
+#define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
+
+#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR           0xa3000000	/* default load address */
+						/* RS: where is this documented? */
+						/* RS: is this where U-Boot is  */
+						/* RS: relocated to in RAM?      */
+
+#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
+						/* RS: the oscillator is actually 3680130?? */
+#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
+						/* 0101000001 */
+						/*      ^^^^^ Memory Speed 99.53 MHz         */
+						/*    ^^      Run Mode Speed = 2x Mem Speed  */
+						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
+
+#define CFG_MONITOR_LEN		0x20000		/* 128 KiB */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Network chip
+ */
+#define CONFIG_DRIVER_CS8900	1
+#define CS8900_BUS32		1
+#define CS8900_BASE		0x08000000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
+#ifdef  CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM   */
+#define PHYS_SDRAM_1		0xa0000000	/* SDRAM Bank #1            */
+#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB                    */
+
+#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1            */
+#define PHYS_FLASH_SIZE		0x02000000	/* 32 MB                    */
+
+#define CFG_DRAM_BASE		0xa0000000	/* RAM starts here          */
+#define CFG_DRAM_SIZE		0x02000000
+
+#define CFG_FLASH_BASE          PHYS_FLASH_1
+
+# if 0
+/* FIXME: switch to _documented_ registers */
+/*
+ * GPIO settings
+ *
+ * GP15 == nCS1      is 1
+ * GP24 == SFRM      is 1
+ * GP25 == TXD       is 1
+ * GP33 == nCS5      is 1
+ * GP39 == FFTXD     is 1
+ * GP41 == RTS       is 1
+ * GP47 == TXD       is 1
+ * GP49 == nPWE      is 1
+ * GP62 == LED_B     is 1
+ * GP63 == TDM_OE    is 1
+ * GP78 == nCS2      is 1
+ * GP79 == nCS3      is 1
+ * GP80 == nCS4      is 1
+ */
+#define CFG_GPSR0_VAL       0x03008000
+#define CFG_GPSR1_VAL       0xC0028282
+#define CFG_GPSR2_VAL       0x0001C000
+
+/* GP02 == DON_RST   is 0
+ * GP23 == SCLK      is 0
+ * GP45 == USB_ACT   is 0
+ * GP60 == PLLEN     is 0
+ * GP61 == LED_A     is 0
+ * GP73 == SWUPD_LED is 0
+ */
+#define CFG_GPCR0_VAL       0x00800004
+#define CFG_GPCR1_VAL       0x30002000
+#define CFG_GPCR2_VAL       0x00000100
+
+/* GP00 == DON_READY is input
+ * GP01 == DON_OK    is input
+ * GP02 == DON_RST   is output
+ * GP03 == RESET_IND is input
+ * GP07 == RES11     is input
+ * GP09 == RES12     is input
+ * GP11 == SWUPDATE  is input
+ * GP14 == nPOWEROK  is input
+ * GP15 == nCS1      is output
+ * GP17 == RES22     is input
+ * GP18 == RDY       is input
+ * GP23 == SCLK      is output
+ * GP24 == SFRM      is output
+ * GP25 == TXD       is output
+ * GP26 == RXD       is input
+ * GP32 == RES21     is input
+ * GP33 == nCS5      is output
+ * GP34 == FFRXD     is input
+ * GP35 == CTS       is input
+ * GP39 == FFTXD     is output
+ * GP41 == RTS       is output
+ * GP42 == USB_OK    is input
+ * GP45 == USB_ACT   is output
+ * GP46 == RXD       is input
+ * GP47 == TXD       is output
+ * GP49 == nPWE      is output
+ * GP58 == nCPUBUSINT is input
+ * GP59 == LANINT    is input
+ * GP60 == PLLEN     is output
+ * GP61 == LED_A     is output
+ * GP62 == LED_B     is output
+ * GP63 == TDM_OE    is output
+ * GP64 == nDSPINT   is input
+ * GP65 == STRAP0    is input
+ * GP67 == STRAP1    is input
+ * GP69 == STRAP2    is input
+ * GP70 == STRAP3    is input
+ * GP71 == STRAP4    is input
+ * GP73 == SWUPD_LED is output
+ * GP78 == nCS2      is output
+ * GP79 == nCS3      is output
+ * GP80 == nCS4      is output
+ */
+#define CFG_GPDR0_VAL       0x03808004
+#define CFG_GPDR1_VAL       0xF002A282
+#define CFG_GPDR2_VAL       0x0001C200
+
+/* GP15 == nCS1  is AF10
+ * GP18 == RDY   is AF01
+ * GP23 == SCLK  is AF10
+ * GP24 == SFRM  is AF10
+ * GP25 == TXD   is AF10
+ * GP26 == RXD   is AF01
+ * GP33 == nCS5  is AF10
+ * GP34 == FFRXD is AF01
+ * GP35 == CTS   is AF01
+ * GP39 == FFTXD is AF10
+ * GP41 == RTS   is AF10
+ * GP46 == RXD   is AF10
+ * GP47 == TXD   is AF01
+ * GP49 == nPWE  is AF10
+ * GP78 == nCS2  is AF10
+ * GP79 == nCS3  is AF10
+ * GP80 == nCS4  is AF10
+ */
+#define CFG_GAFR0_L_VAL     0x80000000
+#define CFG_GAFR0_U_VAL     0x001A8010
+#define CFG_GAFR1_L_VAL     0x60088058
+#define CFG_GAFR1_U_VAL     0x00000008
+#define CFG_GAFR2_L_VAL     0xA0000000
+#define CFG_GAFR2_U_VAL     0x00000002
+
+
+/* FIXME: set GPIO_RER/FER */
+
+/* RDH = 1
+ * PH  = 1
+ * VFS = 1
+ * BFS = 1
+ * SSS = 1
+ */
+#define CFG_PSSR_VAL		0x37
+
+/*
+ * Memory settings
+ *
+ * This is the configuration for nCS0/1 -> flash banks
+ * configuration for nCS1:
+ * [31]    0    - Slower Device
+ * [30:28] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
+ * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
+ * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
+ * [19]    1    - 16 Bit bus width
+ * [18:16] 000  - nonburst RAM or FLASH
+ * configuration for nCS0:
+ * [15]    0    - Slower Device
+ * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
+ * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
+ * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
+ * [03]    1    - 16 Bit bus width
+ * [02:00] 000  - nonburst RAM or FLASH
+ */
+#define CFG_MSC0_VAL		0x25b825b8 /* flash banks                   */
+
+/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
+ * configuration for nCS3: DSP
+ * [31]    0    - Slower Device
+ * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
+ * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
+ * [19]    1    - 16 Bit bus width
+ * [18:16] 100  - variable latency I/O
+ * configuration for nCS2: TDM-Switch
+ * [15]    0    - Slower Device
+ * [14:12] 101  - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
+ * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
+ * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
+ * [03]    1    - 16 Bit bus width
+ * [02:00] 100  - variable latency I/O
+ */
+#define CFG_MSC1_VAL		0x123C593C /* TDM switch, DSP               */
+
+/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
+ *
+ * configuration for nCS5: LAN Controller
+ * [31]    0    - Slower Device
+ * [30:28] 001  - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
+ * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
+ * [19]    1    - 16 Bit bus width
+ * [18:16] 100  - variable latency I/O
+ * configuration for nCS4: ExtBus
+ * [15]    0    - Slower Device
+ * [14:12] 110  - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
+ * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
+ * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
+ * [03]    1    - 16 Bit bus width
+ * [02:00] 100  - variable latency I/O
+ */
+#define CFG_MSC2_VAL		0x123C6CDC /* extra bus, LAN controller     */
+
+/* MDCNFG: SDRAM Configuration Register
+ *
+ * [31:29]   000 - reserved
+ * [28]      0	 - no SA1111 compatiblity mode
+ * [27]      0   - latch return data with return clock
+ * [26]      0   - alternate addressing for pair 2/3
+ * [25:24]   00  - timings
+ * [23]      0   - internal banks in lower partition 2/3 (not used)
+ * [22:21]   00  - row address bits for partition 2/3 (not used)
+ * [20:19]   00  - column address bits for partition 2/3 (not used)
+ * [18]      0   - SDRAM partition 2/3 width is 32 bit
+ * [17]      0   - SDRAM partition 3 disabled
+ * [16]      0   - SDRAM partition 2 disabled
+ * [15:13]   000 - reserved
+ * [12]      1	 - SA1111 compatiblity mode
+ * [11]      1   - latch return data with return clock
+ * [10]      0   - no alternate addressing for pair 0/1
+ * [09:08]   01  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
+ * [7]       1   - 4 internal banks in lower partition pair
+ * [06:05]   10  - 13 row address bits for partition 0/1
+ * [04:03]   01  - 9 column address bits for partition 0/1
+ * [02]      0   - SDRAM partition 0/1 width is 32 bit
+ * [01]      0   - disable SDRAM partition 1
+ * [00]      1   - enable  SDRAM partition 0
+ */
+/* use the configuration above but disable partition 0 */
+#define CFG_MDCNFG_VAL		0x000019c8
+
+/* MDREFR: SDRAM Refresh Control Register
+ *
+ * [32:26] 0     - reserved
+ * [25]    0     - K2FREE: not free running
+ * [24]    0     - K1FREE: not free running
+ * [23]    1     - K0FREE: not free running
+ * [22]    0     - SLFRSH: self refresh disabled
+ * [21]    0     - reserved
+ * [20]    0     - APD: no auto power down
+ * [19]    0     - K2DB2: SDCLK2 is MemClk
+ * [18]    0     - K2RUN: disable SDCLK2
+ * [17]    0     - K1DB2: SDCLK1 is MemClk
+ * [16]    1     - K1RUN: enable SDCLK1
+ * [15]    1     - E1PIN: SDRAM clock enable
+ * [14]    1     - K0DB2: SDCLK0 is MemClk
+ * [13]    0     - K0RUN: disable SDCLK0
+ * [12]    1     - E0PIN: disable SDCKE0
+ * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
+ */
+#define CFG_MDREFR_VAL		0x0081D018
+
+/* MDMRS: Mode Register Set Configuration Register
+ *
+ * [31]      0       - reserved
+ * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
+ * [22:20]   000     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
+ * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
+ * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
+ * [15]      0       - reserved
+ * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
+ * [06:04]   010     - MDCL0:  SDRAM0/1 Cas Latency.
+ * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
+ * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
+ */
+#define CFG_MDMRS_VAL		0x00020022
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL		0x00000000
+#define CFG_MCMEM0_VAL		0x00000000
+#define CFG_MCMEM1_VAL		0x00000000
+#define CFG_MCATT0_VAL		0x00000000
+#define CFG_MCATT1_VAL		0x00000000
+#define CFG_MCIO0_VAL		0x00000000
+#define CFG_MCIO1_VAL		0x00000000
+#endif
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPSR0_VAL		0xFFFFFFFF
+#define CFG_GPSR1_VAL		0xFFFFFFFF
+#define CFG_GPSR2_VAL		0xFFFFFFFF
+#define CFG_GPCR0_VAL		0x08022080
+#define CFG_GPCR1_VAL		0x00000000
+#define CFG_GPCR2_VAL		0x00000000
+#define CFG_GPDR0_VAL		0xCD82A878
+#define CFG_GPDR1_VAL		0xFCFFAB80
+#define CFG_GPDR2_VAL		0x0001FFFF
+#define CFG_GAFR0_L_VAL		0x80000000
+#define CFG_GAFR0_U_VAL		0xA5254010
+#define CFG_GAFR1_L_VAL		0x599A9550
+#define CFG_GAFR1_U_VAL		0xAAA5AAAA
+#define CFG_GAFR2_L_VAL		0xAAAAAAAA
+#define CFG_GAFR2_U_VAL		0x00000002
+
+/* FIXME: set GPIO_RER/FER */
+
+#define CFG_PSSR_VAL        0x20
+
+/*
+ * Memory settings
+ */
+
+#define CFG_MSC0_VAL            0x2ef15af0
+#define CFG_MSC1_VAL            0x00003ff4
+#define CFG_MSC2_VAL            0x7ff07ff0
+#define CFG_MDCNFG_VAL          0x09a909a9
+#define CFG_MDREFR_VAL          0x038ff030
+#define CFG_MDMRS_VAL           0x00220022
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL        0x00000000
+#define CFG_MCMEM0_VAL      0x00000000
+#define CFG_MCMEM1_VAL      0x00000000
+#define CFG_MCATT0_VAL      0x00000000
+#define CFG_MCATT1_VAL      0x00000000
+#define CFG_MCIO0_VAL       0x00000000
+#define CFG_MCIO1_VAL       0x00000000
+
+#define CSB226_USER_LED0	0x00000008
+#define CSB226_USER_LED1	0x00000010
+#define CSB226_USER_LED2	0x00000020
+
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS     1	/* max number of memory banks       */
+#define CFG_MAX_FLASH_SECT	128	/* max number of sect. on one chip  */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase       */
+#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write       */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x1C000)
+					/* Addr of Environment Sector       */
+#define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector */
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/csb272.h b/include/configs/csb272.h
new file mode 100755
index 0000000..27d64c1
--- /dev/null
+++ b/include/configs/csb272.h
@@ -0,0 +1,314 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405GP CPU     	*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_CSB272		1	/* on a Cogent CSB272 board     */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f()    */
+#define CONFIG_LAST_STAGE_INIT	1	/* Call last_stage_init()	*/
+#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
+
+/*
+ * OS Bootstrap configuration
+ *
+ */
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY	3	/* autoboot after X seconds	*/
+#endif
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check keypress when bootdelay = 0 */
+
+#if 1
+#undef  CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs console=ttyS0,38400 debug " \
+	"root=/dev/ram rw ramdisk_size=4096 " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+	"bootm fe000000 fe100000"
+#endif
+
+#if 0
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+	"bootp; " \
+	"setenv bootargs console=ttyS0,38400 debug " \
+	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+	"bootm"
+#endif
+
+/*
+ * BOOTP/DHCP protocol configuration
+ *
+ */
+#define CONFIG_BOOTP_MASK	( CONFIG_BOOTP_DEFAULT		| \
+				  CONFIG_BOOTP_DNS2		| \
+				  CONFIG_BOOTP_BOOTFILESIZE	)
+/*
+ * U-Boot Monitor Command Line Functions Configuration
+ *
+ */
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL	| \
+				  CFG_CMD_ASKENV	| \
+				  CFG_CMD_BEDBUG	| \
+				  CFG_CMD_ELF		| \
+				  CFG_CMD_IRQ		| \
+				  CFG_CMD_I2C		| \
+				  CFG_CMD_PCI		| \
+				  CFG_CMD_DATE		| \
+				  CFG_CMD_MII		| \
+				  CFG_CMD_PING		| \
+				  CFG_CMD_DHCP		 )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Serial download configuration
+ *
+ */
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+/*
+ * KGDB Configuration
+ *
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ *
+ */
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser */
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "	/* hush shell secondary prompt */
+#endif
+
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define CFG_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
+#define CFG_EXTBDINFO		1	/* To use extended board_info (bd_t) */
+#define CFG_LOAD_ADDR		0x100000 /* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * watchdog configuration
+ *
+ */
+#undef  CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * UART configuration
+ *
+ */
+#define CFG_EXT_SERIAL_CLOCK	3868400	/* use external serial clock */
+#undef  CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59 */
+#undef  CFG_BASE_BAUD
+#define CONFIG_BAUDRATE		38400	/* Default baud rate */
+#define CFG_BAUDRATE_TABLE      \
+    { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * I2C configuration
+ *
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#define CFG_I2C_SPEED		100000	/* I2C speed			*/
+#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+
+/*
+ * MII PHY configuration
+ *
+ */
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay 		*/
+					/* 32usec min. for LXT971A	*/
+#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
+
+/*
+ * RTC configuration
+ *
+ * Note that DS1307 RTC is limited to 100Khz I2C bus.
+ *
+ */
+#define CONFIG_RTC_DS1307		/* Use Dallas 1307 RTC		*/
+
+/*
+ * PCI stuff
+ *
+ */
+#define CONFIG_PCI			/* include pci support	        */
+#define PCI_HOST_ADAPTER	0	/* configure ar pci adapter     */
+#define PCI_HOST_FORCE		1	/* configure as pci host        */
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable  */
+
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
+#define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*
+ * IDE stuff
+ *
+ */
+#undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
+
+/*
+ * Environment configuration
+ *
+ */
+#define CFG_ENV_IS_IN_FLASH	1	/* environment is in FLASH	*/
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_EEPROM
+
+/*
+ * General Memory organization
+ *
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_FLASH_SIZE		0x02000000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 KB for Monitor */
+#define CFG_MALLOC_LEN		(128 * 1024) /* Reserve 128 KB for malloc() */
+
+#if CFG_MONITOR_BASE < CFG_FLASH_BASE
+#define CFG_RAMSTART
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_IN_OWN_SECTOR	1	   /* Give Environment own sector */
+#define CFG_ENV_ADDR		0xFFF00000 /* Address of Environment Sector */
+#define	CFG_ENV_SIZE		0x00001000 /* Size of Environment */
+#define CFG_ENV_SECT_SIZE	0x00040000 /* Size of Environment Sector */
+#endif
+
+/*
+ * FLASH Device configuration
+ *
+ */
+#define CFG_FLASH_CFI		1	/* flash is CFI conformant	*/
+#define CFG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
+#define CFG_FLASH_INCREMENT	0	/* there is only one bank	*/
+#define CFG_MAX_FLASH_SECT	128	/* max # of sectors on one chip	*/
+#define CFG_FLASH_PROTECTION	1	/* hardware flash protection	*/
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+
+/*
+ * On Chip Memory location/size
+ *
+ */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+/*
+ * Global info and initial stack
+ *
+ */
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	128 /* byte size reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*
+ * Cache configuration
+ *
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's */
+					/* have only 8kB, 16kB is save here  */
+#define CFG_CACHELINE_SIZE	32
+
+/*
+ * Miscellaneous board specific definitions
+ *
+ */
+#define CFG_I2C_PLL_ADDR	0x58	/* I2C address of AMIS FS6377-01 PLL */
+#define CONFIG_I2CFAST		1	/* enable "i2cfast" env. setting     */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ *
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/csb472.h b/include/configs/csb472.h
new file mode 100755
index 0000000..09d52de
--- /dev/null
+++ b/include/configs/csb472.h
@@ -0,0 +1,313 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405GP CPU     	*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
+#define CONFIG_CSB472		1	/* on a Cogent CSB472 board     */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f()    */
+#define CONFIG_LAST_STAGE_INIT	1	/* Call last_stage_init()	*/
+#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
+
+/*
+ * OS Bootstrap configuration
+ *
+ */
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY	3	/* autoboot after X seconds	*/
+#endif
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check keypress when bootdelay = 0 */
+
+#if 1
+#undef  CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs console=ttyS0,38400 debug " \
+	"root=/dev/ram rw ramdisk_size=4096 " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+	"bootm ff800000 ff900000"
+#endif
+
+#if 0
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+	"bootp; " \
+	"setenv bootargs console=ttyS0,38400 debug " \
+	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+	"bootm"
+#endif
+
+/*
+ * BOOTP/DHCP protocol configuration
+ *
+ */
+#define CONFIG_BOOTP_MASK	( CONFIG_BOOTP_DEFAULT		| \
+				  CONFIG_BOOTP_DNS2		| \
+				  CONFIG_BOOTP_BOOTFILESIZE	)
+/*
+ * U-Boot Monitor Command Line Functions Configuration
+ *
+ */
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL	| \
+				  CFG_CMD_ASKENV	| \
+				  CFG_CMD_BEDBUG	| \
+				  CFG_CMD_ELF		| \
+				  CFG_CMD_IRQ		| \
+				  CFG_CMD_I2C		| \
+				  CFG_CMD_PCI		| \
+				  CFG_CMD_DATE		| \
+				  CFG_CMD_MII		| \
+				  CFG_CMD_PING		| \
+				  CFG_CMD_DHCP		 )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Serial download configuration
+ *
+ */
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+/*
+ * KGDB Configuration
+ *
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ *
+ */
+#undef	CFG_HUSH_PARSER			/* use "hush" command parser */
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "	/* hush shell secondary prompt */
+#endif
+
+#define CFG_LONGHELP			/* undef to save memory	*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on */
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+#define CFG_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
+#define CFG_EXTBDINFO		1	/* To use extended board_info (bd_t) */
+#define CFG_LOAD_ADDR		0x100000 /* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * watchdog configuration
+ *
+ */
+#undef  CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * UART configuration
+ *
+ */
+#undef CFG_EXT_SERIAL_CLOCK		/* use internal serial clock */
+#undef  CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59 */
+#define CFG_BASE_BAUD		691200
+#define CONFIG_BAUDRATE		38400	/* Default baud rate */
+#define CFG_BAUDRATE_TABLE      \
+    { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * I2C configuration
+ *
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#define CFG_I2C_SPEED		100000	/* I2C speed			*/
+#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+
+/*
+ * MII PHY configuration
+ *
+ */
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay 		*/
+					/* 32usec min. for LXT971A	*/
+#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
+
+/*
+ * RTC configuration
+ *
+ * Note that DS1307 RTC is limited to 100Khz I2C bus.
+ *
+ */
+#define CONFIG_RTC_DS1307		/* Use Dallas 1307 RTC		*/
+
+/*
+ * PCI stuff
+ *
+ */
+#define CONFIG_PCI			/* include pci support	        */
+#define PCI_HOST_ADAPTER	0	/* configure ar pci adapter     */
+#define PCI_HOST_FORCE		1	/* configure as pci host        */
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable  */
+
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
+#define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*
+ * IDE stuff
+ *
+ */
+#undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
+
+/*
+ * Environment configuration
+ *
+ */
+#define CFG_ENV_IS_IN_FLASH	1	/* environment is in FLASH	*/
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_EEPROM
+
+/*
+ * General Memory organization
+ *
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFF800000
+#define CFG_FLASH_SIZE		0x00800000
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 KB for Monitor */
+#define CFG_MALLOC_LEN		(128 * 1024) /* Reserve 128 KB for malloc() */
+
+#if CFG_MONITOR_BASE < CFG_FLASH_BASE
+#define CFG_RAMSTART
+#endif
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+#define CFG_ENV_IN_OWN_SECTOR	1	   /* Give Environment own sector */
+#define CFG_ENV_ADDR		0xFFF00000 /* Address of Environment Sector */
+#define	CFG_ENV_SIZE		0x00001000 /* Size of Environment */
+#define CFG_ENV_SECT_SIZE	0x00040000 /* Size of Environment Sector */
+#endif
+
+/*
+ * FLASH Device configuration
+ *
+ */
+#define CFG_FLASH_CFI		1	/* flash is CFI conformant	*/
+#define CFG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
+#define CFG_FLASH_INCREMENT	0	/* there is only one bank	*/
+#define CFG_MAX_FLASH_SECT	64	/* max # of sectors on one chip	*/
+#define CFG_FLASH_PROTECTION	1	/* hardware flash protection	*/
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+
+/*
+ * On Chip Memory location/size
+ *
+ */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+/*
+ * Global info and initial stack
+ *
+ */
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	128 /* byte size reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*
+ * Cache configuration
+ *
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's */
+					/* have only 8kB, 16kB is save here  */
+#define CFG_CACHELINE_SIZE	32
+
+/*
+ * Miscellaneous board specific definitions
+ *
+ */
+#define CONFIG_I2CFAST		1	/* enable "i2cfast" env. setting     */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ *
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/csb637.h b/include/configs/csb637.h
new file mode 100755
index 0000000..071d5b7
--- /dev/null
+++ b/include/configs/csb637.h
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
+ * Anders Larsen <alarsen@rea.de>
+ *
+ * Configuation settings for the Cogent CSB637 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91C_MAIN_CLOCK	184320000	/* from 3.6864 MHz crystal (3686400 * 50) */
+#define AT91C_MASTER_CLOCK	46080000	/* (AT91C_MAIN_CLOCK/4)	peripheral clock */
+
+#define AT91_SLOW_CLOCK		32768	/* slow clock */
+
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
+#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
+#define CONFIG_CSB637		1	/* on a CSB637 board		*/
+#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+#define USE_920T_MMU		1
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CFG_USE_MAIN_OSCILLATOR		1
+/* flash */
+#define MC_PUIA_VAL	0x00000000
+#define MC_PUP_VAL	0x00000000
+#define MC_PUER_VAL	0x00000000
+#define MC_ASR_VAL	0x00000000
+#define MC_AASR_VAL	0x00000000
+#define EBI_CFGR_VAL	0x00000000
+#define SMC2_CSR_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR_VAL	0x2031BE01 /* 184.320000 MHz for PCK */
+#define PLLBR_VAL	0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
+#define MCKR_VAL	0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
+
+/* sdram */
+#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define PIOC_BSR_VAL	0x00000000
+#define PIOC_PDR_VAL	0xFFFF0000
+#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
+#define SDRC_CR_VAL	0x21914159 /* set up the SDRAM */
+#define SDRAM		0x20000000 /* address of the SDRAM */
+#define SDRAM1		0x20000080 /* address of the SDRAM */
+#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
+#define SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1	0x00000004 /* refresh */
+#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_AT91C_BRGR_DIVISOR	75	/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
+
+/*
+ * Hardware drivers
+ */
+
+/* define one of these to choose the DBGU, USART0  or USART1 as console */
+#define CONFIG_DBGU
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+
+#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/
+
+#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */
+
+#define CONFIG_BOOTDELAY      3
+/* #define CONFIG_ENV_OVERWRITE	1 */
+
+#define CONFIG_COMMANDS		\
+		       ((CONFIG_CMD_DFL | \
+			CFG_CMD_JFFS2 | \
+			CFG_CMD_DHCP | \
+			CFG_CMD_PING ) & \
+		      ~(CFG_CMD_BDI | \
+			CFG_CMD_IMI | \
+			CFG_CMD_AUTOSCRIPT | \
+			CFG_CMD_FPGA | \
+			CFG_CMD_MISC | \
+			CFG_CMD_LOADS ))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define SECTORSIZE 512
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 1
+
+#define AT91_SMART_MEDIA_ALE (1 << 22)	/* our ALE is AD22 */
+#define AT91_SMART_MEDIA_CLE (1 << 21)	/* our CLE is AD21 */
+
+#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
+#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
+
+#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+/* the following are NOP's in our implementation */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM			0x20000000
+#define PHYS_SDRAM_SIZE			0x4000000  /* 64 megs */
+
+#define CFG_MEMTEST_START		PHYS_SDRAM
+#define CFG_MEMTEST_END			CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4
+#define CFG_ALT_MEMTEST			1
+#define CFG_MEMTEST_SCRATCH		CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 4
+
+#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_RETRY_COUNT		20
+#undef CONFIG_AT91C_USE_RMII
+
+#undef CONFIG_HAS_DATAFLASH
+#define CFG_SPI_WRITE_TOUT		(5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS 	0
+#define CFG_MAX_DATAFLASH_PAGES 	16384
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* Logical adress for CS0 */
+#define CFG_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* Logical adress for CS3 */
+
+/*
+ * FLASH Device configuration
+ */
+#define PHYS_FLASH_1			0x10000000
+#define PHYS_FLASH_SIZE			0x800000  /* 8 megs main flash */
+#define CFG_FLASH_BASE			PHYS_FLASH_1
+#define CFG_FLASH_CFI		1	/* flash is CFI conformant	*/
+#define CFG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
+#define CFG_FLASH_INCREMENT	0	/* there is only one bank	*/
+#define CFG_FLASH_PROTECTION	1	/* hardware flash protection	*/
+#define CFG_MAX_FLASH_SECT		64
+
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_FIRST_SECTOR	3
+#define CFG_JFFS2_NUM_BANKS	1
+
+#undef	CFG_ENV_IS_IN_DATAFLASH
+
+#ifdef CFG_ENV_IS_IN_DATAFLASH
+#define CFG_ENV_OFFSET			0x20000
+#define CFG_ENV_ADDR			(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE			0x2000  /* 0x8000 */
+#else
+#define CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_ADDR			(PHYS_FLASH_1 + 0x20000)  /* after u-boot.bin */
+#define CFG_ENV_SIZE			0x20000 /* sectors are 128K here */
+#endif	/* CFG_ENV_IS_IN_DATAFLASH */
+
+
+#define CFG_LOAD_ADDR		0x21000000  /* default load address */
+
+#define CFG_BAUDRATE_TABLE	{115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+
+#ifndef __ASSEMBLY__
+/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext {
+	/* helper variable for board environment handling
+	 *
+	 * env_crc_valid == 0    =>   uninitialised
+	 * env_crc_valid  > 0    =>   environment crc in flash is valid
+	 * env_crc_valid  < 0    =>   environment crc in flash is invalid
+	 */
+	int env_crc_valid;
+};
+#endif
+
+#define CFG_HZ 1000
+#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
+					/* AT91C_TC_TIMER_DIV1_CLOCK */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
new file mode 100755
index 0000000..0a10e3c
--- /dev/null
+++ b/include/configs/dbau1x00.h
@@ -0,0 +1,224 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the dbau1x00 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
+#define CONFIG_DBAU1X00		1
+#define CONFIG_AU1X00		1  /* alchemy series cpu */
+
+#ifdef CONFIG_DBAU1000
+/* Also known as Merlot */
+#define CONFIG_AU1000		1
+#else
+#ifdef CONFIG_DBAU1100
+#define CONFIG_AU1100		1
+#else
+#ifdef CONFIG_DBAU1500
+#define CONFIG_AU1500		1
+#else
+#ifdef CONFIG_DBAU1550
+/* Cabernet */
+#define CONFIG_AU1550           1
+#else
+#error "No valid board set"
+#endif
+#endif
+#endif
+#endif
+
+#define CONFIG_ETHADDR		DE:AD:BE:EF:01:01    /* Ethernet address */
+
+#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
+
+#define CONFIG_BAUDRATE		115200
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"addmisc=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate} "				\
+		"panic=1\0"						\
+	"bootfile=/tftpboot/vmlinux.srec\0"				\
+	"load=tftp 80500000 ${u-boot}\0"				\
+	""
+
+#ifdef CONFIG_DBAU1550
+/* Boot from flash by default, revert to bootp */
+#define CONFIG_BOOTCOMMAND	"bootm 0xbfc20000; bootp; bootm"
+
+#define CONFIG_COMMANDS		((CONFIG_CMD_DFL | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_NET) & \
+				 ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FPGA | CFG_CMD_IDE | \
+				   CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \
+				   CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C))
+#else /* CONFIG_DBAU1550 */
+/* Boot from Compact flash partition 2 as default */
+#define CONFIG_BOOTCOMMAND	"ide reset;disk 0x81000000 0:2;bootm"
+
+#define CONFIG_COMMANDS		((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \
+				 ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
+				   CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | \
+				   CFG_CMD_ELF | CFG_CMD_BDI | CFG_CMD_BEDBUG))
+#endif /* CONFIG_DBAU1550 */
+
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory      */
+
+#define	CFG_PROMPT		"DbAu1xx0 # "	/* Monitor Command Prompt    */
+
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args*/
+
+#define CFG_MALLOC_LEN		128*1024
+
+#define CFG_BOOTPARAMS_LEN	128*1024
+
+#define CFG_MHZ			396
+
+#if (CFG_MHZ % 12) != 0
+#error "Invalid CPU frequency - must be multiple of 12!"
+#endif
+
+#define CFG_HZ                  (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
+
+#define CFG_SDRAM_BASE		0x80000000     /* Cached addr */
+
+#define	CFG_LOAD_ADDR		0x81000000     /* default load address	*/
+
+#define CFG_MEMTEST_START	0x80100000
+#define CFG_MEMTEST_END		0x80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#ifdef CONFIG_DBAU1550
+
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	(512)	/* max number of sectors on one chip */
+
+#define PHYS_FLASH_1		0xb8000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0xbc000000 /* Flash Bank #2 */
+
+#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
+
+#else /* CONFIG_DBAU1550 */
+
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+
+#define PHYS_FLASH_1		0xbec00000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0xbfc00000 /* Flash Bank #2 */
+
+#endif /* CONFIG_DBAU1550 */
+
+#define CFG_FLASH_CFI           1
+#define CFG_FLASH_CFI_DRIVER    1
+
+/* The following #defines are needed to get flash environment right */
+#define	CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MONITOR_LEN		(192 << 10)
+
+#define CFG_INIT_SP_OFFSET	0x400000
+
+/* We boot from this flash, selected with dip switch */
+#define CFG_FLASH_BASE		PHYS_FLASH_2
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_NOWHERE	1
+
+/* Address and size of Primary Environment Sector	*/
+#define CFG_ENV_ADDR		0xB0030000
+#define CFG_ENV_SIZE		0x10000
+
+#define CONFIG_FLASH_16BIT
+
+#define CONFIG_NR_DRAM_BANKS	2
+
+#define CONFIG_NET_MULTI
+
+#ifdef CONFIG_DBAU1550
+#define MEM_SIZE 192
+#else
+#define MEM_SIZE 64
+#endif
+
+#define CONFIG_MEMSIZE_IN_BYTES
+
+#ifndef CONFIG_DBAU1550
+/*---ATA PCMCIA ------------------------------------*/
+#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
+#define CFG_PCMCIA_MEM_ADDR 0x20000000
+#define CONFIG_PCMCIA_SLOT_A
+
+#define CONFIG_ATAPI 1
+#define CONFIG_MAC_PARTITION 1
+
+/* We run CF in "true ide" mode or a harddrive via pcmcia */
+#define CONFIG_IDE_PCMCIA 1
+
+/* We only support one slot for now */
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET     8
+
+/* Offset for normal register accesses  */
+#define CFG_ATA_REG_OFFSET      0
+
+/* Offset for alternate registers       */
+#define CFG_ATA_ALT_OFFSET      0x0100
+#endif /* CONFIG_DBAU1550 */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384
+#define CFG_ICACHE_SIZE		16384
+#define CFG_CACHELINE_SIZE	32
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/debris.h b/include/configs/debris.h
new file mode 100755
index 0000000..8ff963f
--- /dev/null
+++ b/include/configs/debris.h
@@ -0,0 +1,459 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Environments */
+
+/* bootargs */
+#define CONFIG_BOOTARGS \
+	"console=ttyS0,9600 init=/linuxrc " \
+	"root=/dev/nfs rw nfsroot=192.168.0.1:" \
+	"/tftpboot/target " \
+	"ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
+	"255.255.255.0:debris:eth0:none " \
+	"mtdparts=phys:12m(root),-(kernel)"
+
+/* bootcmd */
+#define CONFIG_BOOTCOMMAND \
+	"tftp 800000 pImage; " \
+	"setenv bootargs console=ttyS0,9600 init=/linuxrc " \
+	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
+	"${netmask}:${hostname}:eth0:none " \
+	"mtdparts=phys:12m(root),-(kernel); " \
+	"bootm 800000"
+
+/* bootdelay */
+#define CONFIG_BOOTDELAY	5	/* autoboot 5s */
+
+/* baudrate */
+#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
+
+/* loads_echo */
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
+
+/* ethaddr */
+#undef CONFIG_ETHADDR
+
+/* eth2addr */
+#undef CONFIG_ETH2ADDR
+
+/* eth3addr */
+#undef CONFIG_ETH3ADDR
+
+/* ipaddr */
+#define CONFIG_IPADDR	192.168.0.2
+
+/* serverip */
+#define CONFIG_SERVERIP	192.168.0.1
+
+/* autoload */
+#undef CFG_AUTOLOAD
+
+/* rootpath */
+#define CONFIG_ROOTPATH /tftpboot/target
+
+/* gatewayip */
+#define CONFIG_GATEWAYIP 192.168.0.1
+
+/* netmask */
+#define CONFIG_NETMASK 255.255.255.0
+
+/* hostname */
+#define CONFIG_HOSTNAME debris
+
+/* bootfile */
+#define CONFIG_BOOTFILE pImage
+
+/* loadaddr */
+#define CONFIG_LOADADDR 800000
+
+/* preboot */
+#undef CONFIG_PREBOOT
+
+/* clocks_in_mhz */
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8245		1
+#define CONFIG_DEBRIS		1
+
+#if 0
+#define USE_DINK32		1
+#else
+#undef USE_DINK32
+#endif
+
+#define CONFIG_CONS_INDEX       1
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_DRAM_SPEED	100		/* MHz */
+
+#define CONFIG_COMMANDS		( CONFIG_CMD_DFL	| \
+				  CFG_CMD_ASKENV	| \
+				  CFG_CMD_CACHE		| \
+				  CFG_CMD_DATE		| \
+				  CFG_CMD_DHCP		| \
+				  CFG_CMD_DIAG		| \
+				  CFG_CMD_EEPROM	| \
+				  CFG_CMD_ELF		| \
+				  CFG_CMD_I2C		| \
+				  CFG_CMD_JFFS2		| \
+				  CFG_CMD_KGBD		| \
+				  CFG_CMD_PCI		| \
+				  CFG_CMD_PING		| \
+				  CFG_CMD_SAVES		| \
+				  CFG_CMD_SDRAM)
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		1		/* undef to save memory		*/
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI				/* include pci support		*/
+#define CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support */
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100  */
+#define CONFIG_EEPRO100_SROM_WRITE
+
+#define PCI_ENET0_IOADDR	0x80000000
+#define PCI_ENET0_MEMADDR	0x80000000
+#define	PCI_ENET1_IOADDR	0x81000000
+#define	PCI_ENET1_MEMADDR	0x81000000
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MAX_RAM_SIZE	0x20000000
+#define CONFIG_VERY_BIG_RAM
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#if defined (USE_DINK32)
+#define CFG_MONITOR_LEN		0x00040000
+#define CFG_MONITOR_BASE	0x00090000
+#define CFG_RAMBOOT		1
+#define CFG_INIT_RAM_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_INIT_RAM_END	0x10000
+#define CFG_GBL_DATA_SIZE	256  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#else
+#undef	CFG_RAMBOOT
+#define CFG_MONITOR_LEN		0x00040000
+#define CFG_MONITOR_BASE	TEXT_BASE
+
+/*#define CFG_GBL_DATA_SIZE    256*/
+#define CFG_GBL_DATA_SIZE	128
+
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x1000
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+#endif
+
+#define CFG_FLASH_BASE		0x7C000000
+#define CFG_FLASH_SIZE		(16*1024*1024)	/* debris has tiny eeprom	*/
+
+#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+
+#define CFG_EUMB_ADDR		0xFC000000
+
+#define CFG_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
+#define CFG_FLASH_RANGE_SIZE	0x01000000
+#define FLASH_BASE0_PRELIM	0x7C000000	/* debris flash		*/
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=debris-0"
+#define MTDPARTS_DEFAULT	"mtdparts=debris-0:-(jffs2)"
+*/
+
+#define CFG_ENV_IS_IN_NVRAM      1
+#define CONFIG_ENV_OVERWRITE     1
+#define CFG_NVRAM_ACCESS_ROUTINE 1
+#define CFG_ENV_ADDR		0xFF000000 /* right at the start of NVRAM  */
+#define CFG_ENV_SIZE		0x400	/* Size of the Environment - 8K	   */
+#define CFG_ENV_OFFSET		0	/* starting right at the beginning */
+
+#define CFG_NVRAM_BASE_ADDR	0xff000000
+
+/*
+ * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS =
+ * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
+ */
+#define CFG_NVRAM_VXWORKS_OFFS	0x6900
+
+/*
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
+#undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#ifdef CONFIG_SOFT_I2C
+#error "Soft I2C is not configured properly.  Please review!"
+#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
+#define I2C_READ		((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
+				else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
+				else    iop->pdat &= ~0x00020000
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+#define CFG_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CFG_FLASH_BANKS		{ FLASH_BASE0_PRELIM }
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	1
+
+#define CFG_NS16550_CLK		7372800
+
+#define CFG_NS16550_COM1	0xFF080000
+#define CFG_NS16550_COM2	(CFG_NS16550_COM1 + 8)
+#define CFG_NS16550_COM3	(CFG_NS16550_COM1 + 16)
+#define CFG_NS16550_COM4	(CFG_NS16550_COM1 + 24)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
+#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
+
+#define CFG_DLL_EXTEND		0x00
+#define CFG_PCI_HOLD_DEL	0x20
+
+#define CFG_ROMNAL	15	/* rom/flash next access time */
+#define CFG_ROMFAL	31	/* rom/flash access time */
+
+#define CFG_REFINT	430	/* # of clocks between CBR refresh cycles */
+
+#define CFG_DBUS_SIZE2	1	/* set for 8-bit RCS1, clear for 32,64 */
+
+/* the following are for SDRAM only*/
+#define CFG_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
+#define CFG_REFREC	8	/* Refresh to activate interval		*/
+#define CFG_RDLAT	4	/* data latency from read command	*/
+#define CFG_PRETOACT	3	/* Precharge to activate interval	*/
+#define CFG_ACTTOPRE	5	/* Activate to Precharge interval	*/
+#define CFG_ACTORW		3	/* Activate to R/W			*/
+#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#if 0
+#define CFG_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
+#endif
+
+#define CFG_REGISTERD_TYPE_BUFFER   1
+#define CFG_EXTROM 1
+#define CFG_REGDIMM 0
+
+
+/* memory bank settings*/
+/*
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CFG_BANK0_START		0x00000000
+#define CFG_BANK0_END		(0x4000000 - 1)
+#define CFG_BANK0_ENABLE	1
+#define CFG_BANK1_START		0x04000000
+#define CFG_BANK1_END		(0x8000000 - 1)
+#define CFG_BANK1_ENABLE	1
+#define CFG_BANK2_START		0x3ff00000
+#define CFG_BANK2_END		0x3fffffff
+#define CFG_BANK2_ENABLE	0
+#define CFG_BANK3_START		0x3ff00000
+#define CFG_BANK3_END		0x3fffffff
+#define CFG_BANK3_ENABLE	0
+#define CFG_BANK4_START		0x00000000
+#define CFG_BANK4_END		0x00000000
+#define CFG_BANK4_ENABLE	0
+#define CFG_BANK5_START		0x00000000
+#define CFG_BANK5_END		0x00000000
+#define CFG_BANK5_ENABLE	0
+#define CFG_BANK6_START		0x00000000
+#define CFG_BANK6_END		0x00000000
+#define CFG_BANK6_ENABLE	0
+#define CFG_BANK7_START		0x00000000
+#define CFG_BANK7_END		0x00000000
+#define CFG_BANK7_ENABLE	0
+/*
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CFG_BANK_ENABLE		0x01
+
+#define CFG_ODCR		0x75	/* configures line driver impedances,	*/
+					/* see 8240 book for bit definitions	*/
+#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+/* SDRAM 0 - 256MB */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#if defined(USE_DINK32)
+#define CFG_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CFG_IBAT1U	(0x40000000 | BATU_BL_128K )
+#else
+#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#endif
+
+/* PCI memory */
+#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+
+/* values according to the manual */
+
+#define CONFIG_DRAM_50MHZ	1
+#define CONFIG_SDRAM_50MHZ
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h
new file mode 100755
index 0000000..9ac2856
--- /dev/null
+++ b/include/configs/dnp1110.h
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Rolf Offermanns <rof@sysgo.de>
+ *
+ * Configuation settings for the SSV DNP1110 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT	1
+#undef  CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SA1110		1	/* This is an SA1110 CPU	*/
+#define CONFIG_DNP1110		1	/* on an DNP/1110 Board      */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE 0x20000300
+
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1          1	/* we use SERIAL 1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,115200"
+#define CONFIG_ETHADDR		02:80:ad:20:31:b8
+#define CONFIG_NETMASK          255.255.0.0
+#define CONFIG_IPADDR		172.22.2.23
+#define CONFIG_SERVERIP		172.22.2.22
+#define CONFIG_BOOTFILE		"dnp1110"
+#define CONFIG_BOOTCOMMAND	"tftp; bootm"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"DNP1110 # "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0xc0200000	/* default load address	*/
+
+#define	CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x0b		/* set core clock to 220 MHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks of DRAM */
+#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
+
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE		0x01000000 /* 16 MB */
+#define PHYS_FLASH_BANK_SIZE    0x01000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 256 KB sectors (x2) */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	128		/* max number of sectors on one chip	*/
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR			(PHYS_FLASH_1 + 0xF80000)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE			0x20000						/* Total Size of Environment Sector	*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h
new file mode 100755
index 0000000..a014c7c
--- /dev/null
+++ b/include/configs/eXalion.h
@@ -0,0 +1,454 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+/* #define CONFIG_MPC8240	   1 */
+#define CONFIG_MPC8245		1
+#define CONFIG_EXALION		1
+
+#if defined (CONFIG_MPC8240)
+    /* #warning	 ---------- eXalion with MPC8240 --------------- */
+#elif defined (CONFIG_MPC8245)
+    /* #warning	 ++++++++++ eXalion with MPC8245 +++++++++++++++ */
+#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245)
+#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245)
+#else
+#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+/* older kernels need clock in MHz newer in Hz */
+					/* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz	    */
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_BOOTDELAY	10
+
+
+						    /*#define CONFIG_DRAM_SPEED	      66   */ /* MHz			     */
+
+#define CONFIG_COMMANDS		(   CONFIG_CMD_DFL  | \
+				    CFG_CMD_FLASH   | \
+				    CFG_CMD_SDRAM   | \
+				    CFG_CMD_I2C	    | \
+				    CFG_CMD_IDE	    | \
+				    CFG_CMD_FAT	    | \
+				    CFG_CMD_ENV	    | \
+				    CFG_CMD_PCI )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)	*/
+#include <cmd_confdefs.h>
+
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		1	/* undef to save memory		*/
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
+#define CFG_MAXARGS		8	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR		0x00100000	/* default load address		*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_MISC_INIT_R	1
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MAX_RAM_SIZE	0x10000000	/* 1 GBytes - initdram() will	   */
+					     /* return real value.		*/
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+#undef	CFG_RAMBOOT
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	    */
+#define CFG_MONITOR_BASE	TEXT_BASE
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_DATA_SIZE	128
+
+#define CFG_INIT_RAM_ADDR	0x40000000
+#define CFG_INIT_RAM_END	0x1000
+#define CFG_INIT_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+
+#define CFG_GBL_DATA_SIZE	 256	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+
+#if defined (CONFIG_MPC8240)
+#define CFG_FLASH_BASE	    0xFFE00000
+#define CFG_FLASH_SIZE	    (2 * 1024 * 1024)	/* onboard 2MByte flash	    */
+#elif defined (CONFIG_MPC8245)
+#define CFG_FLASH_BASE	    0xFFC00000
+#define CFG_FLASH_SIZE	    (4 * 1024 * 1024)	/* onboard 4MByte flash	    */
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	0x20000 /* Size of one Flash sector */
+#define CFG_ENV_SIZE		CFG_ENV_SECT_SIZE	/* Use one Flash sector for enviroment	*/
+#define CFG_ENV_ADDR		0xFFFC0000
+#define CFG_ENV_OFFSET		0	/* starting right at the beginning  */
+
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+#define CFG_ALT_MEMTEST		1	/* use real memory test	    */
+#define CFG_MEMTEST_START	0x00004000	/* memtest works on	    */
+#define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM	    */
+
+#define CFG_EUMB_ADDR		0xFC000000
+
+/* #define CFG_ISA_MEM		   0xFD000000 */
+#define CFG_ISA_IO		0xFE000000
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks	    */
+#define CFG_MAX_FLASH_SECT	64	/* Max number of sectors per flash  */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE
+#define FLASH_BASE1_PRELIM	0
+
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
+#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_FLASH_INCREMENT	0	/* there is only one bank		*/
+#define CFG_FLASH_PROTECTION	1	/* use hardware protection		*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ */
+#define CONFIG_PCI		1	/* include pci support		*/
+#undef	CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI	1	/* Multi ethernet cards support */
+
+#define CONFIG_EEPRO100		1
+
+#define PCI_ENET0_MEMADDR	0x80000000	/* Intel 82559ER */
+#define PCI_ENET0_IOADDR	0x80000000
+#define PCI_ENET1_MEMADDR	0x81000000	/* Intel 82559ER */
+#define PCI_ENET1_IOADDR	0x81000000
+#define PCI_ENET2_MEMADDR	0x82000000	/* Broadcom BCM569xx */
+#define PCI_ENET2_IOADDR	0x82000000
+#define PCI_ENET3_MEMADDR	0x83000000	/* Broadcom BCM56xx */
+#define PCI_ENET3_IOADDR	0x83000000
+
+/*-----------------------------------------------------------------------
+ * NS16550 Configuration
+ */
+#define CFG_NS16550		1
+#define CFG_NS16550_SERIAL	1
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		38400
+
+#define CFG_NS16550_REG_SIZE	1
+
+#if (CONFIG_CONS_INDEX == 1)
+#define CFG_NS16550_CLK		1843200 /* COM1 only !	*/
+#else
+#define CFG_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
+#endif
+
+#define CFG_NS16550_COM1	(CFG_ISA_IO + 0x3F8)
+#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4500)
+#define CFG_NS16550_COM3	(CFG_EUMB_ADDR + 0x4600)
+
+/*-----------------------------------------------------------------------
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*-----------------------------------------------------------------------
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define CFG_HZ			1000
+
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
+#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2	/* for MPC8240 only		*/
+
+				       /*#define CONFIG_133MHZ_DRAM	 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!!    */
+
+#if defined (CONFIG_MPC8245)
+/* Bit-field values for PMCR2.							*/
+#if defined (CONFIG_133MHZ_DRAM)
+#define CFG_DLL_EXTEND		0x80	/* use DLL extended range - 133MHz only */
+#define CFG_PCI_HOLD_DEL	0x20	/* delay and hold timing - 133MHz only	*/
+#endif
+
+/* Bit-field values for MIOCR1.							*/
+#if !defined (CONFIG_133MHZ_DRAM)
+#define CFG_DLL_MAX_DELAY	0x04	/*  longer DLL delay line - 66MHz only	*/
+#endif
+/* Bit-field values for MIOCR2.							*/
+#define CFG_SDRAM_DSCD		0x20	/* SDRAM data in sample clock delay	*/
+					/*	- note bottom 3 bits MUST be 0	*/
+#endif
+
+/* Bit-field values for MCCR1.							*/
+#define CFG_ROMNAL		7	/*rom/flash next access time		*/
+#define CFG_ROMFAL	       11	/*rom/flash access time			*/
+
+/* Bit-field values for MCCR2.							*/
+#define CFG_TSWAIT		0x5	/* Transaction Start Wait States timer	*/
+#if defined (CONFIG_133MHZ_DRAM)
+#define CFG_REFINT		1300	/* no of clock cycles between CBR	*/
+#else  /* refresh cycles */
+#define CFG_REFINT		750
+#endif
+
+/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.		*/
+#if defined (CONFIG_133MHZ_DRAM)
+#define CFG_BSTOPRE		1023
+#else
+#define CFG_BSTOPRE		250
+#endif
+
+/* Bit-field values for MCCR3.							*/
+/* the following are for SDRAM only						*/
+
+#if defined (CONFIG_133MHZ_DRAM)
+#define CFG_REFREC		9	/* Refresh to activate interval		*/
+#else
+#define CFG_REFREC		5	/* Refresh to activate interval		*/
+#endif
+#if defined (CONFIG_MPC8240)
+#define CFG_RDLAT		2	/* data latency from read command	*/
+#endif
+
+/* Bit-field values for MCCR4.	*/
+#if defined (CONFIG_133MHZ_DRAM)
+#define CFG_PRETOACT		3	/* Precharge to activate interval	*/
+#define CFG_ACTTOPRE		7	/* Activate to Precharge interval	*/
+#define CFG_ACTORW		5	/* Activate to R/W			*/
+#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#else
+#if 0
+#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
+#define CFG_ACTTOPRE		3	/* Activate to Precharge interval	*/
+#define CFG_ACTORW		3	/* Activate to R/W			*/
+#define CFG_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
+#endif
+#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
+#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CFG_ACTORW		3	/* Activate to R/W			*/
+#define CFG_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#endif
+#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
+#define CFG_REGDIMM		0
+#if defined (CONFIG_MPC8240)
+#define CFG_REGISTERD_TYPE_BUFFER   0
+#elif defined (CONFIG_MPC8245)
+#define CFG_REGISTERD_TYPE_BUFFER   1
+#define CFG_EXTROM		    0
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+
+
+/*-----------------------------------------------------------------------
+ memory bank settings
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CFG_BANK0_START		0x00000000
+#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE	1
+#define CFG_BANK1_START		0x3ff00000
+#define CFG_BANK1_END		0x3fffffff
+#define CFG_BANK1_ENABLE	0
+#define CFG_BANK2_START		0x3ff00000
+#define CFG_BANK2_END		0x3fffffff
+#define CFG_BANK2_ENABLE	0
+#define CFG_BANK3_START		0x3ff00000
+#define CFG_BANK3_END		0x3fffffff
+#define CFG_BANK3_ENABLE	0
+#define CFG_BANK4_START		0x00000000
+#define CFG_BANK4_END		0x00000000
+#define CFG_BANK4_ENABLE	0
+#define CFG_BANK5_START		0x00000000
+#define CFG_BANK5_END		0x00000000
+#define CFG_BANK5_ENABLE	0
+#define CFG_BANK6_START		0x00000000
+#define CFG_BANK6_END		0x00000000
+#define CFG_BANK6_ENABLE	0
+#define CFG_BANK7_START		0x00000000
+#define CFG_BANK7_END		0x00000000
+#define CFG_BANK7_ENABLE	0
+
+/*-----------------------------------------------------------------------
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CFG_BANK_ENABLE		0x01
+
+#if defined (CONFIG_MPC8240)
+#define CFG_ODCR		0xDF	/* configures line driver impedances,	*/
+					/* see 8240 book for bit definitions	*/
+#elif defined (CONFIG_MPC8245)
+#if defined (CONFIG_133MHZ_DRAM)
+#define CFG_ODCR		0xFE	/* configures line driver impedances - 133MHz	*/
+#else
+#define CFG_ODCR		0xDE	/* configures line driver impedances - 66MHz	*/
+#endif
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+
+#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+/*-----------------------------------------------------------------------
+ * Block Address Translation (BAT) register settings.
+ */
+/* SDRAM 0 - 256MB */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#define CFG_IBAT1L	(CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* PCI memory */
+#define CFG_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CFG_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+
+/* values according to the manual */
+#define CONFIG_DRAM_50MHZ	1
+#define CONFIG_SDRAM_50MHZ
+
+#undef	NR_8259_INTS
+#define NR_8259_INTS		1
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ */
+#define CFG_IDE_MAXBUS	    1	/* max. 2 IDE busses	*/
+#define CFG_IDE_MAXDEVICE   (CFG_IDE_MAXBUS*1)	/* max. 2 drives per IDE bus */
+
+#define CFG_ATA_BASE_ADDR   CFG_ISA_IO	/* base address */
+#define CFG_ATA_IDE0_OFFSET 0x01F0	/* ide0 offste */
+#define CFG_ATA_IDE1_OFFSET 0x0170	/* ide1 offset */
+#define CFG_ATA_DATA_OFFSET 0	/* data reg offset  */
+#define CFG_ATA_REG_OFFSET  0	/* reg offset */
+#define CFG_ATA_ALT_OFFSET  0x200	/* alternate register offset */
+
+#define CONFIG_ATAPI
+
+#undef	CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED		/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET	/* reset for ide supported...	 */
+#undef	CONFIG_IDE_RESET_ROUTINE	/* with a special reset function */
+
+/*-----------------------------------------------------------------------
+ * DISK Partition support
+ */
+#define CONFIG_DOS_PARTITION
+
+/*-----------------------------------------------------------------------
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
new file mode 100755
index 0000000..a26af69
--- /dev/null
+++ b/include/configs/ebony.h
@@ -0,0 +1,295 @@
+/*
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_EBONY		1	    /* Board is ebony		*/
+#define CONFIG_440GP		1	    /* Specifc GP support	*/
+#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
+#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ *       supported for backward compatibility.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
+#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
+#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
+#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
+#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
+#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
+#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
+
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
+#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE  128		    /* num bytes initial data	*/
+
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
+#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE		0x1000	    /* Size of Environment vars */
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_NVRAM */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
+#define CFG_MAX_FLASH_SECT	32		    /* sectors per device   */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CFG_FLASH_ADDR0         0x5555
+#define CFG_FLASH_ADDR1         0x2aaa
+#define CFG_FLASH_WORD_SIZE     unsigned char
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup     */
+#define SPD_EEPROM_ADDRESS {0x53,0x52}  /* SPD i2c spd addresses        */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES    {0x69}  /* Don't probe these addrs */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=ebony\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/ebony/uImage\0"				\
+	"kernel_addr=ff800000\0"					\
+	"ramdisk_addr=ff810000\0"					\
+	"load=tftp 100000 /tftpboot/ebony/u-boot.bin\0"		        \
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		8	/* PHY address			*/
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	9	/* EMAC1 PHY address		*/
+#define CONFIG_NET_MULTI	1
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			            /* include pci support	        */
+#define CONFIG_PCI_PNP			        /* do pci plug-and-play         */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
+#define CFG_PCI_TARGET_INIT	            /* let board init pci target    */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h
new file mode 100755
index 0000000..bdda629
--- /dev/null
+++ b/include/configs/ep7312.h
@@ -0,0 +1,163 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the EP7312 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
+#define CONFIG_EP7312		1	/* on an EP7312 Board      */
+#define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
+#undef  CONFIG_ARM7_REVD	 	/* disable ARM720 REV.D Workarounds */
+
+#undef CONFIG_USE_IRQ			/* don't need them anymore */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
+#define CS8900_BASE		0x20000000
+#define CS8900_BUS16		1
+#undef  CS8900_BUS32
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		1	/* we use Serial line 1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_JFFS2)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS    	"devfs=mount root=ramfs console=ttyS0,9600"
+#define CONFIG_ETHADDR	08:00:3e:21:c7:f7
+/*#define CONFIG_NETMASK        255.255.0.0	*/
+/*#define CONFIG_IPADDR		172.22.2.128	*/
+/*#define CONFIG_SERVERIP	172.22.2.126	*/
+/*#define CONFIG_BOOTFILE	"impa7"	*/
+#define CONFIG_BOOTCOMMAND	"bootp;bootm"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"EP7312 # "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0xc0500000	/* default load address	*/
+
+#define	CFG_HZ			2000		/* decrementer freq: 2 kHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE		0x01000000 /* 16 MB */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x20000)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment Sector	*/
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=ep7312-0"
+#define MTDPARTS_DEFAULT	"mtdparts=ep7312-0:-(jffs2)"
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h
new file mode 100755
index 0000000..04147a5
--- /dev/null
+++ b/include/configs/ep8248.h
@@ -0,0 +1,277 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * U-Boot configuration for Embedded Planet EP8248 boards.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC8248
+#define CPU_ID_STR		"MPC8248"
+
+#define CONFIG_EP8248			/* Embedded Planet EP8248 board */
+
+#undef DEBUG
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
+#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
+#undef	CONFIG_CONS_NONE		/* It's not on external UART */
+#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
+
+#define CFG_BCSR		0xFA000000
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CFG_CMD_NET must
+ * be removed from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
+#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
+#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
+
+#ifdef CONFIG_ETHER_ON_FCC
+
+#define CONFIG_ETHER_INDEX	1	/* FCC1 is used for Ethernet */
+
+#if   (CONFIG_ETHER_INDEX == 1)
+
+/* - Rx clock is CLK10
+ * - Tx clock is CLK11
+ * - BDs/buffers on 60x bus
+ * - Full duplex
+ */
+#define CFG_CMXFCR_MASK	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+#define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#elif (CONFIG_ETHER_INDEX == 2)
+
+/* - Rx clock is CLK13
+ * - Tx clock is CLK14
+ * - BDs/buffers on 60x bus
+ * - Full duplex
+ */
+#define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_INDEX */
+
+#define CONFIG_MII			/* MII PHY management        */
+#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT		0	/* Not used - implemented in BCSR */
+#define MDIO_ACTIVE		(*(vu_char *)(CFG_BCSR + 8) &= 0xFB)
+#define MDIO_TRISTATE		(*(vu_char *)(CFG_BCSR + 8) |= 0x04)
+#define MDIO_READ		(*(vu_char *)(CFG_BCSR + 8) & 1)
+
+#define MDIO(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x01; \
+				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFE
+
+#define MDC(bit)		if(bit) *(vu_char *)(CFG_BCSR + 8) |= 0x02; \
+				else	*(vu_char *)(CFG_BCSR + 8) &= 0xFD
+
+#define MIIDELAY		udelay(1)
+
+#endif /* CONFIG_ETHER_ON_FCC */
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN	66000000	/* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL   \
+				| CFG_CMD_DHCP    \
+				| CFG_CMD_ECHO    \
+				| CFG_CMD_I2C     \
+				| CFG_CMD_IMMAP   \
+				| CFG_CMD_MII     \
+				| CFG_CMD_PING    \
+				)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND	"bootm FF860000"	/* autoboot command */
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	1	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size  */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CFG_FLASH_BASE		0xFF800000
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+
+#define	CFG_DIRECT_FLASH_TFTP
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
+#define CFG_JFFS2_FIRST_SECTOR  0
+#define CFG_JFFS2_LAST_SECTOR   62
+#define CFG_JFFS2_SORT_FRAGMENTS
+#define CFG_JFFS_CUSTOM_PART
+#endif /* CFG_CMD_JFFS2 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
+#define CFG_I2C_SPEED		100000	/* I2C speed			*/
+#define CFG_I2C_SLAVE		0x7F	/* I2C slave address		*/
+#endif /* CFG_CMD_I2C */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256KB for Monitor */
+
+#define CFG_ENV_IS_IN_FLASH
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+#define CFG_DEFAULT_IMMR	0x00010000
+
+#define CFG_IMMR		0xF0000000
+
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/* Hard reset configuration word */
+#define CFG_HRCW_MASTER		0x0C40025A /* Not used - provided by FPGA */
+/* No slaves */
+#define CFG_HRCW_SLAVE1 	0
+#define CFG_HRCW_SLAVE2 	0
+#define CFG_HRCW_SLAVE3 	0
+#define CFG_HRCW_SLAVE4 	0
+#define CFG_HRCW_SLAVE5 	0
+#define CFG_HRCW_SLAVE6 	0
+#define CFG_HRCW_SLAVE7 	0
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot                  */
+
+#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
+
+#define CFG_HID2		0
+
+#define CFG_SIUMCR		0x01240200
+#define CFG_SYPCR		0xFFFF0683
+#define CFG_BCR			0x00000000
+#define CFG_SCCR		SCCR_DFBRG01
+
+#define CFG_RMR			RMR_CSRE
+#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CFG_RCCR		0
+
+#define CFG_MPTPR		0x1300
+#define CFG_PSDMR		0x82672522
+#define CFG_PSRT		0x4B
+
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_BR		(CFG_SDRAM_BASE | 0x00001841)
+#define CFG_SDRAM_OR		0xFF0030C0
+
+#define CFG_BR0_PRELIM		(CFG_FLASH_BASE | 0x00001801)
+#define CFG_OR0_PRELIM		0xFF8008C2
+#define CFG_BR2_PRELIM		(CFG_BCSR | 0x00000801)
+#define CFG_OR2_PRELIM		0xFFF00864
+
+#define CFG_RESET_ADDRESS	0xC0000000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
new file mode 100755
index 0000000..6862519
--- /dev/null
+++ b/include/configs/ep8260.h
@@ -0,0 +1,775 @@
+/*
+ * (C) Copyright 2002
+ * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
+ *
+ * This file is based on similar values for other boards found in other
+ * U-Boot config files, and some that I found in the EP8260 manual.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ *
+ * "EP8260 H, V.1.1"
+ * 	- 64M 60x Bus SDRAM
+ * 	- 32M Local Bus SDRAM
+ * 	- 16M Flash (4 x AM29DL323DB90WDI)
+ * 	- 128k NVRAM with RTC
+ *
+ * "EP8260 H2, V.1.3" (CFG_EP8260_H2)
+ * 	- 300MHz/133MHz/66MHz
+ * 	- 64M 60x Bus SDRAM
+ * 	- 32M Local Bus SDRAM
+ * 	- 32M Flash
+ * 	- 128k NVRAM with RTC
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Define this to enable support the EP8260 H2 version */
+#define CFG_EP8260_H2	1
+/* #undef CFG_EP8260_H2  */
+
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/* What is the oscillator's (UX2) frequency in Hz? */
+#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
+
+/*-----------------------------------------------------------------------
+ * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
+ *-----------------------------------------------------------------------
+ * What should MODCK_H be? It is dependent on the oscillator
+ * frequency, MODCK[1-3], and desired CPM and core frequencies.
+ * Here are some example values (all frequencies are in MHz):
+ *
+ * MODCK_H   MODCK[1-3]	 Osc	CPM    Core
+ * -------   ----------	 ---	---    ----
+ * 0x2	     0x2	 33	133    133
+ * 0x2	     0x3	 33	133    166
+ * 0x2	     0x4	 33	133    200
+ * 0x2	     0x5	 33	133    233
+ * 0x2	     0x6	 33	133    266
+ *
+ * 0x5	     0x5	 66	133    133
+ * 0x5	     0x6	 66	133    166
+ * 0x5	     0x7	 66	133    200 *
+ * 0x6	     0x0	 66	133    233
+ * 0x6	     0x1	 66	133    266
+ * 0x6	     0x2	 66	133    300
+ */
+#ifdef CFG_EP8260_H2
+#define CFG_SBC_MODCK_H  (HRCW_MODCK_H0110)
+#else
+#define CFG_SBC_MODCK_H  (HRCW_MODCK_H0110)
+#endif
+
+/* Define this if you want to boot from 0x00000100. If you don't define
+ * this, you will need to program the bootloader to 0xfff00000, and
+ * get the hardware reset config words at 0xfe000000. The simplest
+ * way to do that is to program the bootloader at both addresses.
+ * It is suggested that you just let U-Boot live at 0x00000000.
+ */
+/* #define CFG_SBC_BOOT_LOW 1 */	/* only for HRCW */
+/* #undef CFG_SBC_BOOT_LOW */
+
+/* The reset command will not work as expected if the reset address does
+ * not point to the correct address.
+ */
+
+#define CFG_RESET_ADDRESS	0xFFF00100
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk
+ * The main FLASH is whichever is connected to *CS0. U-Boot expects
+ * this to be the SIMM.
+ */
+#ifdef CFG_EP8260_H2
+#define CFG_FLASH0_BASE 0xFE000000
+#define CFG_FLASH0_SIZE 32
+#else
+#define CFG_FLASH0_BASE 0xFF000000
+#define CFG_FLASH0_SIZE 16
+#endif
+
+/* What should the base address of the secondary FLASH be and how big
+ * is it (in Mbytes)? The secondary FLASH is whichever is connected
+ * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
+ * want it enabled, don't define these constants.
+ */
+#define CFG_FLASH1_BASE 0
+#define CFG_FLASH1_SIZE 0
+#undef CFG_FLASH1_BASE
+#undef CFG_FLASH1_SIZE
+
+/* What should be the base address of SDRAM DIMM (60x bus) and how big is
+ * it (in Mbytes)?
+*/
+#define CFG_SDRAM0_BASE 0x00000000
+#define CFG_SDRAM0_SIZE 64
+
+/* define CFG_LSDRAM if you want to enable the 32M SDRAM on the
+ * local bus (8260 local bus is NOT cacheable!)
+*/
+/* #define CFG_LSDRAM */
+#undef CFG_LSDRAM
+
+#ifdef CFG_LSDRAM
+/* What should be the base address of SDRAM DIMM (local bus) and how big is
+ * it (in Mbytes)?
+*/
+  #define CFG_SDRAM1_BASE 0x04000000
+  #define CFG_SDRAM1_SIZE 32
+#else
+  #define CFG_SDRAM1_BASE 0
+  #define CFG_SDRAM1_SIZE 0
+  #undef CFG_SDRAM1_BASE
+  #undef CFG_SDRAM1_SIZE
+#endif /* CFG_LSDRAM */
+
+/* What should be the base address of NVRAM and how big is
+ * it (in Bytes)
+ */
+#define CFG_NVRAM_BASE_ADDR  0xFA080000
+#define CFG_NVRAM_SIZE       (128*1024)-16
+
+/* The RTC is a Dallas DS1556
+ */
+#define CONFIG_RTC_DS1556
+
+/* What should be the base address of the LEDs and switch S0?
+ * If you don't want them enabled, don't define this.
+ */
+#define CFG_LED_BASE 0x00000000
+#undef CFG_LED_BASE
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ */
+#define CONFIG_CONS_ON_SMC          /* define if console on SMC */
+#undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
+#undef  CONFIG_CONS_NONE            /* define if console on neither */
+#define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
+#define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
+#undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
+#define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */
+
+#if ( CONFIG_ETHER_INDEX == 3 )
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK16
+ * - RAM for BD/Buffers is on the local Bus (see 28-13)
+ * - Enable Half Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+
+/*
+ * - RAM for BD/Buffers is on the local Bus (see 28-13)
+ */
+#ifdef CFG_LSDRAM
+  #define CFG_CPMFCR_RAMTYPE	3
+#else /* CFG_LSDRAM */
+  #define CFG_CPMFCR_RAMTYPE	0
+#endif /* CFG_LSDRAM */
+
+/* - Enable Half Duplex in FSMR */
+/* # define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB) */
+# define CFG_FCC_PSMR		0
+
+#else /* CONFIG_ETHER_INDEX */
+# error "on EP8260 ethernet must be FCC3"
+#endif /* CONFIG_ETHER_INDEX */
+
+/*
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#ifdef CONFIG_SOFT_I2C
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+/* #define CONFIG_RTC_DS174x */
+
+/* Define this to reserve an entire FLASH sector (256 KB) for
+ * environment variables. Otherwise, the environment will be
+ * put in the same sector as U-Boot, and changing variables
+ * will erase U-Boot temporarily
+ */
+#define CFG_ENV_IN_OWN_SECT
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* What should the console's baud rate be? */
+#ifdef CFG_EP8260_H2
+#define CONFIG_BAUDRATE         9600
+#else
+#define CONFIG_BAUDRATE         115200
+#endif
+
+/* Ethernet MAC address */
+#define CONFIG_ETHADDR          00:10:EC:00:30:8C
+
+#define CONFIG_IPADDR		192.168.254.130
+#define CONFIG_SERVERIP         192.168.254.49
+
+/* Set to a positive value to delay for running BOOTCOMMAND */
+#define CONFIG_BOOTDELAY        -1
+
+/* undef this to save memory */
+#define CFG_LONGHELP
+
+/* Monitor Command Prompt       */
+#define CFG_PROMPT              "=> "
+
+/* Define this variable to enable the "hush" shell (from
+   Busybox) as command line interpreter, thus enabling
+   powerful command line syntax like
+   if...then...else...fi conditionals or `&&' and '||'
+   constructs ("shell scripts").
+   If undefined, you get the old, much simpler behaviour
+   with a somewhat smapper memory footprint.
+*/
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+/* What U-Boot subsytems do you want enabled? */
+/*
+*/
+#define CONFIG_COMMANDS		( CFG_CMD_ALL     & \
+				  ~(	CFG_CMD_BMP	| \
+					CFG_CMD_BSP	| \
+					CFG_CMD_DCR	| \
+					CFG_CMD_DHCP	| \
+					CFG_CMD_DISPLAY	| \
+					CFG_CMD_DOC	| \
+					CFG_CMD_DTT	| \
+					CFG_CMD_EEPROM	| \
+					CFG_CMD_EXT2	| \
+					CFG_CMD_FDC	| \
+					CFG_CMD_FDOS	| \
+					CFG_CMD_HWFLOW	| \
+					CFG_CMD_IDE	| \
+					CFG_CMD_JFFS2	| \
+					CFG_CMD_KGDB	| \
+					CFG_CMD_MII	| \
+					CFG_CMD_MMC	| \
+					CFG_CMD_NAND	| \
+					CFG_CMD_PCI	| \
+					CFG_CMD_PCMCIA	| \
+					CFG_CMD_REISER	| \
+					CFG_CMD_SCSI	| \
+					CFG_CMD_SPI	| \
+					CFG_CMD_UNIVERSE| \
+					CFG_CMD_USB	| \
+					CFG_CMD_VFD	| \
+					CFG_CMD_XIMG	) )
+
+
+/* Where do the internal registers live? */
+#define CFG_IMMR               0xF0000000
+#define CFG_DEFAULT_IMMR       0x00010000
+
+/* Where do the on board registers (CS4) live? */
+#define CFG_REGS_BASE          0xFA000000
+
+/*****************************************************************************
+ *
+ * You should not have to modify any of the following settings
+ *
+ *****************************************************************************/
+
+#define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
+#define CONFIG_EP8260           11      /* on an Embedded Planet EP8260 Board, Rev. 11 */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CBSIZE              1024       /* Console I/O Buffer Size      */
+#else
+#  define CFG_CBSIZE              256        /* Console I/O Buffer Size      */
+#endif
+
+/* Print Buffer Size */
+#define CFG_PBSIZE        (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+
+#define CFG_MAXARGS       8            /* max number of command args   */
+
+#define CFG_BARGSIZE      CFG_CBSIZE   /* Boot Argument Buffer Size    */
+
+#ifdef CFG_LSDRAM
+  #define CFG_MEMTEST_START 0x04000000   /* memtest works on  */
+  #define CFG_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
+#else
+  #define CFG_MEMTEST_START 0x00000000   /* memtest works on  */
+  #define CFG_MEMTEST_END   0x02000000   /* 0-32 MB in SDRAM */
+#endif /* CFG_LSDRAM */
+
+#define	CONFIG_CLOCKS_IN_MHZ	1      /* clocks passsed to Linux in MHz */
+
+#define CFG_LOAD_ADDR     0x00100000   /* default load address */
+#define CFG_TFTP_LOADADDR 0x00100000   /* default load address for network file downloads */
+
+#define CFG_HZ            1000         /* decrementer freq: 1 ms ticks */
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_FLASH_BASE    CFG_FLASH0_BASE
+#define CFG_SDRAM_BASE    CFG_SDRAM0_BASE
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+
+#if defined(CFG_SBC_BOOT_LOW)
+#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#else
+#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0x00000000)
+#endif /* defined(CFG_SBC_BOOT_LOW) */
+
+#ifdef CFG_EP8260_H2
+/* get the HRCW ISB field from CFG_DEFAULT_IMMR */
+#define CFG_SBC_HRCW_IMMR ( ((CFG_DEFAULT_IMMR & 0x10000000) >> 10) |\
+			    ((CFG_DEFAULT_IMMR & 0x01000000) >> 7)  |\
+			    ((CFG_DEFAULT_IMMR & 0x00100000) >> 4) )
+
+#define CFG_HRCW_MASTER (HRCW_EBM                |\
+			 HRCW_L2CPC01            |\
+			 CFG_SBC_HRCW_IMMR       |\
+			 HRCW_APPC10             |\
+			 HRCW_CS10PC01           |\
+			 CFG_SBC_MODCK_H 	 |\
+			 CFG_SBC_HRCW_BOOT_FLAGS)
+#else
+#define CFG_HRCW_MASTER 0x10400245
+#endif
+
+/* no slaves */
+#define CFG_HRCW_SLAVE1 0
+#define CFG_HRCW_SLAVE2 0
+#define CFG_HRCW_SLAVE3 0
+#define CFG_HRCW_SLAVE4 0
+#define CFG_HRCW_SLAVE5 0
+#define CFG_HRCW_SLAVE6 0
+#define CFG_HRCW_SLAVE7 0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR       CFG_IMMR
+#define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ */
+#define CFG_MONITOR_BASE          TEXT_BASE
+
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#  define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS   1       /* max number of memory banks         */
+#ifdef CFG_EP8260_H2
+#define CFG_MAX_FLASH_SECT    128      /* max number of sectors on one chip  */
+#else
+#define CFG_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
+#endif
+
+#ifdef CFG_EP8260_H2
+#define CFG_FLASH_ERASE_TOUT  240000  /* Timeout for Flash Erase (in ms)    */
+#define CFG_FLASH_WRITE_TOUT  500     /* Timeout for Flash Write (in ms)    */
+#else
+#define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
+#define CFG_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
+#endif
+
+#ifndef CFG_RAMBOOT
+#  define CFG_ENV_IS_IN_FLASH  1
+
+#  ifdef CFG_ENV_IN_OWN_SECT
+#    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
+#    define CFG_ENV_SECT_SIZE  0x40000
+#  else
+#    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
+#    define CFG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
+#    define CFG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
+#  endif /* CFG_ENV_IN_OWN_SECT */
+#else
+#  define CFG_ENV_IS_IN_NVRAM  1
+#  define CFG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
+#  define CFG_ENV_SIZE         0x200
+#endif /* CFG_RAMBOOT */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT     5     /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT   (HID0_ICE  |\
+			 HID0_DCE  |\
+			 HID0_ICFI |\
+			 HID0_DCI  |\
+			 HID0_IFEM |\
+			 HID0_ABE)
+#ifdef CFG_LSDRAM
+/* 8260 local bus is NOT cacheable */
+#define CFG_HID0_FINAL  (/*HID0_ICE  |*/\
+			 HID0_IFEM |\
+			 HID0_ABE  |\
+			 HID0_EMCP)
+#else /* !CFG_LSDRAM */
+#define CFG_HID0_FINAL  (HID0_ICE  |\
+			 HID0_IFEM |\
+			 HID0_ABE  |\
+			 HID0_EMCP)
+#endif /* CFG_LSDRAM */
+
+#define CFG_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMR         0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR         (BCR_EBM   |\
+			 BCR_PLDP  |\
+			 BCR_EAV   |\
+			 BCR_NPQM0)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR      (SIUMCR_L2CPC01 |\
+			 SIUMCR_APPC10  |\
+			 SIUMCR_CS10PC01)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                            11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#ifdef CFG_EP8260_H2
+/* TBD: Find out why setting the BMT to 0xff causes the FCC to
+ * generate TX buffer underrun errors for large packets under
+ * Linux
+ */
+#define CFG_SYPCR_BMT	0x00000600
+#else
+#define CFG_SYPCR_BMT	SYPCR_BMT
+#endif
+
+#ifdef CFG_LSDRAM
+#define CFG_SYPCR       (SYPCR_SWTC |\
+			 CFG_SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWP)
+#else
+#define CFG_SYPCR       (SYPCR_SWTC |\
+			 CFG_SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC     (TMCNTSC_SEC |\
+			 TMCNTSC_ALR |\
+			 TMCNTSC_TCF |\
+			 TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#ifdef CFG_EP8260_H2
+#define CFG_PISCR       (PISCR_PS  |\
+			 PISCR_PTF |\
+			 PISCR_PTE)
+#else
+#define CFG_PISCR	0
+#endif
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ */
+#ifdef CFG_EP8260_H2
+#define CFG_SCCR        (SCCR_DFBRG00)
+#else
+#define CFG_SCCR        (SCCR_DFBRG01)
+#endif
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR        0
+
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Refresh Timer Prescale Register               10-32
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MPTPR	(0x0A00 & MPTPR_PTP_MSK)
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
+ *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
+ *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
+ *  3   unused
+ *  4   60x     GPCM     8 bit  Board Regs, NVRTC
+ *  5   unused
+ *  6   unused
+ *  7   unused
+ *  8   PCMCIA
+ *  9   unused
+ * 10   unused
+ * 11   unused
+*/
+
+/*-----------------------------------------------------------------------
+ * BRx - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * ORx - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 0 - FLASH
+ *
+ */
+#define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64                      |\
+			 BRx_DECC_NONE                  |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_8_CLK                 |\
+			 ORxG_EHTR)
+
+/* Bank 1 - SDRAM
+ * PSDRAM
+ */
+#define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A6             |\
+			 ORxS_NUMR_12)
+
+#ifdef CFG_EP8260_H2
+#define CFG_PSDMR       0xC34E246E
+#else
+#define CFG_PSDMR       0xC34E2462
+#endif
+
+#define CFG_PSRT	0x64
+
+#ifdef CFG_LSDRAM
+/* Bank 2 - SDRAM
+ * LSDRAM
+ */
+
+  #define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
+			   BRx_PS_32                      |\
+			   BRx_MS_SDRAM_L                 |\
+			   BRx_V)
+
+  #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
+			   ORxS_BPD_4                     |\
+			   ORxS_ROWST_PBI0_A9             |\
+			   ORxS_NUMR_12)
+
+  #define CFG_LSDMR      0x416A2562
+  #define CFG_LSRT	0x64
+#else
+  #define CFG_LSRT	0x0
+#endif /* CFG_LSDRAM */
+
+/* Bank 4 - On board registers
+ * NVRTC and BCSR
+ */
+#define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
+			   BRx_PS_8                     |\
+			   BRx_MS_GPCM_P                |\
+			   BRx_V)
+/*
+#define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\
+			   ORxG_CSNT                   |\
+			   ORxG_ACS_DIV1               |\
+			   ORxG_SCY_10_CLK              |\
+			   ORxG_TRLX)
+*/
+#define CFG_OR4_PRELIM 0xfff00854
+
+#ifdef _NOT_USED_SINCE_NOT_WORKING_
+/* Bank 8 - On board registers
+ * PCMCIA (currently not working!)
+ */
+#define CFG_BR8_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
+			   BRx_PS_16                     |\
+			   BRx_MS_GPCM_P                |\
+			   BRx_V)
+
+#define CFG_OR8_PRELIM    (ORxG_AM_MSK                 |\
+			   ORxG_CSNT                   |\
+			   ORxG_ACS_DIV1               |\
+			   ORxG_SETA                   |\
+			   ORxG_SCY_10_CLK)
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM   0x02    /* Software reboot                   */
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		""
+#define MTDPARTS_DEFAULT	""
+*/
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h
new file mode 100755
index 0000000..88c2c74
--- /dev/null
+++ b/include/configs/evb4510.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * Configuation settings for evb4510 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start u-boot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ *
+ * Also swap the flash1 and flash2 addresses during debug.
+ *
+ * #define CONFIG_SKIP_LOWLEVEL_INIT
+ */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7		1	/* This is a ARM7 CPU	 */
+#define CONFIG_ARM_THUMB	1	/* this is an ARM7TDMI	 */
+#define CONFIG_S3C4510B		1	/* it's a S3C4510B chip	 */
+#define CONFIG_EVB4510		1	/* on an EVB4510 Board	 */
+
+#define CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ    (4*1024)
+#define CONFIG_STACKSIZE_FIQ    (4*1024)
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_S3C4510_ETH   1
+#define CONFIG_DRIVER_S3C4510_I2C   1
+#define CONFIG_DRIVER_S3C4510_UART  1
+#define CONFIG_DRIVER_S3C4510_FLASH 1
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		1	/* we use Serial line 1, could also use 2 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		19200
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_PING)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_ETHADDR		00:40:95:36:35:33
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		10.0.0.11
+#define CONFIG_SERVERIP		10.0.0.1
+#define CONFIG_CMDLINE_TAG	/* submit bootargs to kernel */
+
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_BOOTCOMMAND	"tftp 100000 uImage"
+/* #define CONFIG_BOOTARGS    	"console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	19200		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory */
+#define CFG_PROMPT		"evb4510 # "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_CMDLINE_TAG                      /* allow passing of command line args to linux */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00780000	/* 4 ... 8 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0x00000000	/* default load address */
+
+#define CFG_SYS_CLK_FREQ	50000000	/* CPU freq: 50 MHz */
+#define CFG_HZ			1000		/* decrementer freq: 1 KHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+*/
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map after relocation
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks of DRAM */
+#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB */
+
+#define PHYS_FLASH_1		0x01000000 /* Flash Bank #1 */
+#define PHYS_FLASH_1_SIZE	0x00200000 /* 2 MB (one chip, 8bit access) */
+
+#define PHYS_FLASH_2		0x02000000 /* Flash Bank #2 */
+#define PHYS_FLASH_2_SIZE	0x00080000 /* 512KB (one chip, 8bit access) */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CFG_FLASH_SIZE		PHYS_FLASH_1_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
+#define CFG_MAIN_SECT_SIZE	0x00010000  /* main size of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(4*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+
+/* environment settings */
+#define CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_NOWHERE
+
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x20000) /* environment start address */
+#define CFG_ENV_SECT_SIZE	0x10000	   /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE		0x1000	   /* max size for environment */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h
new file mode 100755
index 0000000..b68a2dc
--- /dev/null
+++ b/include/configs/gcplus.h
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * 2003-2004 (c) MontaVista Software, Inc.
+ *
+ * Configuation settings for the ADS GraphicsClient+ board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef	 DEBUG
+
+/*
+ * The ADS GCPlus Linux boot ROM loads U-Boot into RAM at 0xc0200000.
+ * We don't actually init RAM in this case since we're using U-Boot as
+ * an secondary boot loader during Linux kernel development and testing,
+ * e.g. bootp/tftp download of the kernel is a far more convenient
+ * when testing new kernels on this target. However the ADS GCPlus Linux
+ * boot ROM leaves the MMU enabled when it passes control to U-Boot. So
+ * we use lowlevel_init (CONFIG_INIT_CRITICAL) to remedy that problem.
+ */
+#undef  CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT	1
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SA1110		1	/* This is an SA1100 CPU	*/
+#define CONFIG_GCPLUS		1	/* on an ADS GCPlus Board      */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE       128     /* size rsrvd for initial data */
+
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_LAN91C96	/* we have an SMC9194 on-board */
+#define CONFIG_LAN91C96_BASE	0x100e0000
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL3          1	/* we use SERIAL 3 on ADS GCPlus */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_DHCP)
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySA0,38400n8 mtdparts=sa1100-flash:1m@0(zImage),3m@1m(ramdisk.gz),12m@4m(userfs) root=/dev/nfs ip=bootp"
+#define CONFIG_BOOTCOMMAND	"bootp;tftp;bootm"
+#define CFG_AUTOLOAD            "n"             /* No autoload */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	38400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"ADS GCPlus # "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0xc0000000	/* default load address	*/
+
+#define	CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x0a		/* set core clock to 206MHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	   /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
+#define PHYS_SDRAM_2		0xc8000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x01000000 /* 16 MB */
+
+
+#define PHYS_FLASH_1		0x08000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE		0x00800000 /* 8 MB */
+#define PHYS_FLASH_BANK_SIZE    0x01000000 /* 16 MB Banks */
+#define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#if	1
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+#else
+/* REVISIT: This doesn't work on ADS GCPlus just yet: */
+#define CFG_FLASH_CFI           1       /* flash is CFI conformant      */
+#define CFG_FLASH_CFI_DRIVER    1       /* use common cfi driver        */
+#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_BANKS     1       /* max # of memory banks        */
+#define CFG_FLASH_INCREMENT     0       /* there is only one bank       */
+#define CFG_MAX_FLASH_SECT      128     /* max # of sectors on one chip */
+/*#define CFG_FLASH_PROTECTION    1       /--* hardware flash protection    */
+#define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
+#endif
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		PHYS_FLASH_SECT_SIZE
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
new file mode 100755
index 0000000..6c08043
--- /dev/null
+++ b/include/configs/gw8260.h
@@ -0,0 +1,821 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jmonkman@adventnetworks.com>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Oliver Brown <obrown@adventnetworks.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*********************************************************************/
+/* DESCRIPTION:
+ *   This file contains the board configuartion for the GW8260 board.
+ *
+ * MODULE DEPENDENCY:
+ *   None
+ *
+ * RESTRICTIONS/LIMITATIONS:
+ *   None
+ *
+ * Copyright (c) 2001, Advent Networks, Inc.
+ */
+/*********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Enable debug prints */
+#undef DEBUG                  /* General debug */
+#undef DEBUG_BOOTP_EXT        /* Debug received vendor fields */
+
+/* What is the oscillator's (UX2) frequency in Hz? */
+#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
+
+/*-----------------------------------------------------------------------
+ * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
+ *-----------------------------------------------------------------------
+ * What should MODCK_H be? It is dependent on the oscillator
+ * frequency, MODCK[1-3], and desired CPM and core frequencies.
+ * Here are some example values (all frequencies are in MHz):
+ *
+ * MODCK_H   MODCK[1-3]  Osc    CPM    Core  S2-6   S2-7   S2-8
+ * -------   ----------  ---    ---    ----  -----  -----  -----
+ * 0x5       0x5     66 133     133    Open  Close  Open
+ * 0x5       0x6     66 133     166    Open  Open   Close
+ * 0x5       0x7     66 133     200    Open  Open   Open
+ * 0x6       0x0     66 133     233    Close Close  Close
+ * 0x6       0x1     66 133     266    Close Close  Open
+ * 0x6       0x2     66 133     300    Close Open   Close
+ */
+#define CFG_SBC_MODCK_H 0x05
+
+/* Define this if you want to boot from 0x00000100. If you don't define
+ * this, you will need to program the bootloader to 0xfff00000, and
+ * get the hardware reset config words at 0xfe000000. The simplest
+ * way to do that is to program the bootloader at both addresses.
+ * It is suggested that you just let U-Boot live at 0x00000000.
+ */
+#define CFG_SBC_BOOT_LOW 1
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
+ * The main FLASH is whichever is connected to *CS0. U-Boot expects
+ * this to be the SIMM.
+ */
+#define CFG_FLASH0_BASE 0x40000000
+#define CFG_FLASH0_SIZE 8
+
+/* Define CFG_FLASH_CHECKSUM to enable flash checksum during boot.
+ * Note: the 'flashchecksum' environment variable must also be set to 'y'.
+ */
+#define CFG_FLASH_CHECKSUM
+
+/* What should be the base address of SDRAM DIMM and how big is
+ * it (in Mbytes)?
+ */
+#define CFG_SDRAM0_BASE 0x00000000
+#define CFG_SDRAM0_SIZE 64
+
+/*
+ * DRAM tests
+ *   CFG_DRAM_TEST - enables the following tests.
+ *
+ *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
+ *                        Environment variable 'test_dram_data' must be
+ *                        set to 'y'.
+ *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
+ *                        addressable. Environment variable
+ *                        'test_dram_address' must be set to 'y'.
+ *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
+ *                        This test takes about 6 minutes to test 64 MB.
+ *                        Environment variable 'test_dram_walk' must be
+ *                        set to 'y'.
+ */
+#define CFG_DRAM_TEST
+#if defined(CFG_DRAM_TEST)
+#define CFG_DRAM_TEST_DATA
+#define CFG_DRAM_TEST_ADDRESS
+#define CFG_DRAM_TEST_WALK
+#endif /* CFG_DRAM_TEST */
+
+/*
+ * GW8260 with 16 MB DIMM:
+ *
+ *     0x0000 0000     Exception Vector code, 8k
+ *           :
+ *     0x0000 1FFF
+ *     0x0000 2000     Free for Application Use
+ *           :
+ *           :
+ *
+ *           :
+ *           :
+ *     0x00F5 FF30     Monitor Stack (Growing downward)
+ *                     Monitor Stack Buffer (0x80)
+ *     0x00F5 FFB0     Board Info Data
+ *     0x00F6 0000     Malloc Arena
+ *           :          CFG_ENV_SECT_SIZE, 256k
+ *           :          CFG_MALLOC_LEN,    128k
+ *     0x00FC 0000     RAM Copy of Monitor Code
+ *           :              CFG_MONITOR_LEN,   256k
+ *     0x00FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
+ */
+
+/*
+ * GW8260 with 64 MB DIMM:
+ *
+ *     0x0000 0000     Exception Vector code, 8k
+ *           :
+ *     0x0000 1FFF
+ *     0x0000 2000     Free for Application Use
+ *           :
+ *           :
+ *
+ *           :
+ *           :
+ *     0x03F5 FF30     Monitor Stack (Growing downward)
+ *                     Monitor Stack Buffer (0x80)
+ *     0x03F5 FFB0     Board Info Data
+ *     0x03F6 0000     Malloc Arena
+ *           :          CFG_ENV_SECT_SIZE, 256k
+ *           :          CFG_MALLOC_LEN,    128k
+ *     0x03FC 0000     RAM Copy of Monitor Code
+ *           :              CFG_MONITOR_LEN,   256k
+ *     0x03FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
+ */
+
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ */
+#define CONFIG_CONS_ON_SMC  1   /* define if console on SMC */
+#undef  CONFIG_CONS_ON_SCC      /* define if console on SCC */
+#undef  CONFIG_CONS_NONE        /* define if console on neither */
+#define CONFIG_CONS_INDEX   1   /* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+
+#undef  CONFIG_ETHER_ON_SCC
+#define CONFIG_ETHER_ON_FCC
+#undef  CONFIG_ETHER_NONE       /* define if ethernet on neither */
+
+#ifdef  CONFIG_ETHER_ON_SCC
+#define CONFIG_ETHER_INDEX  1   /* which SCC/FCC channel for ethernet */
+#endif  /* CONFIG_ETHER_ON_SCC */
+
+#ifdef  CONFIG_ETHER_ON_FCC
+#define CONFIG_ETHER_INDEX  2   /* which SCC/FCC channel for ethernet */
+#define CONFIG_MII              /* MII PHY management           */
+#define CONFIG_BITBANGMII       /* bit-bang MII PHY management  */
+/*
+ * Port pins used for bit-banged MII communictions (if applicable).
+ */
+#define MDIO_PORT   2       /* Port C */
+#define MDIO_ACTIVE    (iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE  (iop->pdir &= ~0x00400000)
+#define MDIO_READ     ((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)   if(bit) iop->pdat |=  0x00400000; \
+	    else            iop->pdat &= ~0x00400000
+
+#define MDC(bit)    if(bit) iop->pdat |=  0x00200000; \
+	    else    iop->pdat &= ~0x00200000
+
+#define MIIDELAY    udelay(1)
+#endif  /* CONFIG_ETHER_ON_FCC */
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK16
+ * - Select bus for bd/buffers (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+/* Define this to reserve an entire FLASH sector (256 KB) for
+ * environment variables. Otherwise, the environment will be
+ * put in the same sector as U-Boot, and changing variables
+ * will erase U-Boot temporarily
+ */
+#define CFG_ENV_IN_OWN_SECT
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* What should the console's baud rate be? */
+#define CONFIG_BAUDRATE     115200
+
+/* Ethernet MAC address - This is set to all zeros to force an
+ *                        an error if we use BOOTP without setting
+ *                        the MAC address
+ */
+#define CONFIG_ETHADDR      00:00:00:00:00:00
+
+/* Set to a positive value to delay for running BOOTCOMMAND */
+#define CONFIG_BOOTDELAY    5   /* autoboot after 5 seconds */
+
+/* Be selective on what keys can delay or stop the autoboot process
+ *     To stop  use: " "
+ */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT  "Autobooting in %d seconds, press \" \" to stop\n"
+#define CONFIG_AUTOBOOT_STOP_STR    " "
+#undef  CONFIG_AUTOBOOT_DELAY_STR
+#define DEBUG_BOOTKEYS      0
+
+/* Add support for a few extra bootp options like:
+ *  - File size
+ *  - DNS
+ */
+#define CONFIG_BOOTP_MASK   (CONFIG_BOOTP_DEFAULT | \
+			     CONFIG_BOOTP_BOOTFILESIZE | \
+			     CONFIG_BOOTP_DNS)
+
+/* undef this to save memory */
+#define CFG_LONGHELP
+
+/* Monitor Command Prompt */
+#define CFG_PROMPT      "=> "
+
+/* What U-Boot subsytems do you want enabled? */
+#define CONFIG_COMMANDS     (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
+			       CFG_CMD_BEDBUG  | \
+			       CFG_CMD_ELF | \
+			       CFG_CMD_ASKENV  | \
+			       CFG_CMD_ECHO    | \
+			       CFG_CMD_REGINFO | \
+			       CFG_CMD_IMMAP   | \
+			       CFG_CMD_MII)
+
+/* Where do the internal registers live? */
+#define CFG_IMMR        0xf0000000
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* What is the address of IO controller */
+#define CFG_IO_BASE 0xe0000000
+
+/*****************************************************************************
+ *
+ * You should not have to modify any of the following settings
+ *
+ *****************************************************************************/
+
+#define CONFIG_MPC8260      1   /* This is an MPC8260 CPU   */
+#define CONFIG_GW8260       1   /* on an GW8260 Board  */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CBSIZE        1024    /* Console I/O Buffer Size       */
+#else
+#  define CFG_CBSIZE        256     /* Console I/O Buffer Size       */
+#endif
+
+/* Print Buffer Size */
+#define CFG_PBSIZE    (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+
+#define CFG_MAXARGS     8          /* max number of command args   */
+
+#define CFG_BARGSIZE    CFG_CBSIZE /* Boot Argument Buffer Size    */
+
+/* Convert clocks to MHZ when passing board info to kernel.
+ * This must be defined for eariler 2.4 kernels (~2.4.4).
+ */
+#define CONFIG_CLOCKS_IN_MHZ
+
+#define CFG_LOAD_ADDR   0x100000 /* default load address */
+#define CFG_HZ          1000     /* decrementer freq: 1 ms ticks */
+
+
+/* memtest works from the end of the exception vector table
+ * to the end of the DRAM less monitor and malloc area
+ */
+#define CFG_MEMTEST_START   0x2000
+
+#define CFG_STACK_USAGE     0x10000 /* Reserve 64k for the stack usage */
+
+#define CFG_MEM_END_USAGE   ( CFG_MONITOR_LEN \
+			    + CFG_MALLOC_LEN \
+			    + CFG_ENV_SECT_SIZE \
+			    + CFG_STACK_USAGE )
+
+#define CFG_MEMTEST_END     ( CFG_SDRAM_SIZE * 1024 * 1024 \
+			    - CFG_MEM_END_USAGE )
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_FLASH_BASE  CFG_FLASH0_BASE
+#define CFG_FLASH_SIZE  CFG_FLASH0_SIZE
+#define CFG_SDRAM_BASE  CFG_SDRAM0_BASE
+#define CFG_SDRAM_SIZE  CFG_SDRAM0_SIZE
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+#if defined(CFG_SBC_BOOT_LOW)
+#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#else
+#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CFG_SBC_BOOT_LOW) */
+
+/* get the HRCW ISB field from CFG_IMMR */
+#define CFG_SBC_HRCW_IMMR   ( ((CFG_IMMR & 0x10000000) >> 10) | \
+		  ((CFG_IMMR & 0x01000000) >>  7) | \
+		  ((CFG_IMMR & 0x00100000) >>  4) )
+
+#define CFG_HRCW_MASTER     ( HRCW_BPS11                | \
+		  HRCW_DPPC11               | \
+		  CFG_SBC_HRCW_IMMR         | \
+		  HRCW_MMR00                | \
+		  HRCW_LBPC11               | \
+		  HRCW_APPC10               | \
+		  HRCW_CS10PC00             | \
+		  (CFG_SBC_MODCK_H & HRCW_MODCK_H1111)  | \
+		  CFG_SBC_HRCW_BOOT_FLAGS )
+
+/* no slaves */
+#define CFG_HRCW_SLAVE1     0
+#define CFG_HRCW_SLAVE2     0
+#define CFG_HRCW_SLAVE3     0
+#define CFG_HRCW_SLAVE4     0
+#define CFG_HRCW_SLAVE5     0
+#define CFG_HRCW_SLAVE6     0
+#define CFG_HRCW_SLAVE7     0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR    CFG_IMMR
+#define CFG_INIT_RAM_END     0x4000  /* End of used area in DPRAM    */
+#define CFG_GBL_DATA_SIZE   128 /* bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET   CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ */
+#define CFG_MONITOR_BASE    CFG_FLASH0_BASE
+
+#define CFG_MONITOR_LEN     (256 * 1024) /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN      (128 * 1024) /* Reserve 128 kB for malloc()  */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ       (8 * 1024 * 1024) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS   1    /* max number of memory banks        */
+#define CFG_MAX_FLASH_SECT    32   /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT  8000 /* Timeout for Flash Erase (in ms)   */
+#define CFG_FLASH_WRITE_TOUT  1    /* Timeout for Flash Write (in ms)   */
+
+#define CFG_ENV_IS_IN_FLASH   1
+
+#ifdef CFG_ENV_IN_OWN_SECT
+#  define CFG_ENV_ADDR        (CFG_MONITOR_BASE +  (256 * 1024))
+#  define CFG_ENV_SECT_SIZE   (256 * 1024)
+#else
+#  define CFG_ENV_SIZE        (16 * 1024)/* Size of Environment Sector  */
+#  define CFG_ENV_ADD  ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) - CFG_ENV_SIZE)
+#  define CFG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size  */
+#endif /* CFG_ENV_IN_OWN_SECT */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE  32      /* For MPC8260 CPU */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT    5   /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers            2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT   (HID0_ICE  |\
+			 HID0_DCE  |\
+			 HID0_ICFI |\
+			 HID0_DCI  |\
+			 HID0_IFEM |\
+			 HID0_ABE)
+
+#define CFG_HID0_FINAL  (HID0_ICE  |\
+			 HID0_IFEM |\
+			 HID0_ABE  |\
+			 HID0_EMCP)
+#define CFG_HID2    0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMR     0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                           4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR     (BCR_ETM)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                 4-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR  (SIUMCR_DPPC11  |\
+		     SIUMCR_L2CPC00 |\
+		     SIUMCR_APPC10  |\
+		     SIUMCR_MMR00)
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#define CFG_SYPCR   (SYPCR_SWTC |\
+		     SYPCR_BMT  |\
+		     SYPCR_PBME |\
+		     SYPCR_LBME |\
+		     SYPCR_SWRI |\
+		     SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control             4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC (TMCNTSC_SEC |\
+		     TMCNTSC_ALR |\
+		     TMCNTSC_TCF |\
+		     TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control         4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR   (PISCR_PS  |\
+		     PISCR_PTF |\
+		     PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                           9-8
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SCCR    0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                 13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR    0
+
+/*
+ * Initialize Memory Controller:
+ *
+ * Bank Bus   Machine PortSz  Device
+ * ---- ---   ------- ------  ------
+ *  0   60x   GPCM    32 bit  FLASH (SIMM - 4MB)
+ *  1   60x   GPCM    32 bit  unused
+ *  2   60x   SDRAM   64 bit  SDRAM (DIMM - 16MB or 64MB)
+ *  3   60x   SDRAM   64 bit  unused
+ *  4   Local GPCM     8 bit  IO    (on board - 64k)
+ *  5   60x   GPCM     8 bit  unused
+ *  6   60x   GPCM     8 bit  unused
+ *  7   60x   GPCM     8 bit  unused
+ *
+ */
+
+/*-----------------------------------------------------------------------
+ * BR0 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR0 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 0,1 - FLASH SIMM
+ *
+ * This expects the FLASH SIMM to be connected to *CS0
+ * It consists of 4 AM29F016D parts.
+ *
+ * Note: For the 8 MB SIMM, *CS1 is unused.
+ */
+
+/* BR0 is configured as follows:
+ *
+ *     - Base address of 0x40000000
+ *     - 32 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+			  BRx_PS_32                     |\
+			  BRx_MS_GPCM_P                 |\
+			  BRx_V)
+
+/* OR0 is configured as follows:
+ *
+ *     - 8 MB
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 5
+ *     - *PSDVAL is generated internally by the memory controller
+ *       unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *       initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *       current bank and the next access.
+ */
+#define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE) |\
+			 ORxG_CSNT          |\
+			 ORxG_ACS_DIV1      |\
+			 ORxG_SCY_5_CLK     |\
+			 ORxG_TRLX          |\
+			 ORxG_EHTR)
+
+/*-----------------------------------------------------------------------
+ * BR2 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR2 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 2 - SDRAM DIMM
+ *
+ *     16MB DIMM: P/N
+ *     64MB DIMM: P/N  1W-8864X8-4-P1-EST or
+ *                     MT4LSDT864AG-10EB1 (Micron)
+ *
+ * Note: *CS3 is unused for this DIMM
+ */
+
+/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
+ *
+ *     - Base address of 0x00000000
+ *     - 64 bit port size (60x bus only)
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - SDRAM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR2_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+			  BRx_PS_64          |\
+			  BRx_MS_SDRAM_P     |\
+			  BRx_V)
+
+/* With a 16 MB DIMM, the OR2 is configured as follows:
+ *
+ *     - 16 MB
+ *     - 2 internal banks per device
+ *     - Row start address bit is A9 with PSDMR[PBI] = 0
+ *     - 11 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+#if (CFG_SDRAM0_SIZE == 16)
+#define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
+			 ORxS_BPD_2         |\
+			 ORxS_ROWST_PBI0_A9 |\
+			 ORxS_NUMR_11)
+
+/* With a 16 MB DIMM, the PSDMR is configured as follows:
+ *
+ *     - Page Based Interleaving,
+ *     - Refresh Enable,
+ *     - Address Multiplexing where A5 is output on A14 pin
+ *       (A6 on A15, and so on),
+ *     - use address pins A16-A18 as bank select,
+ *     - A9 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *       is 3 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *       2 clocks,
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - CAS Latency is 2.
+ */
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x Bus SDRAM Mode Register
+ *     Ref: Section 10.3.3 on page 10-21
+ *-----------------------------------------------------------------------
+ */
+#define CFG_PSDMR   (PSDMR_RFEN       |\
+		     PSDMR_SDAM_A14_IS_A5 |\
+		     PSDMR_BSMA_A16_A18   |\
+		     PSDMR_SDA10_PBI0_A9  |\
+		     PSDMR_RFRC_7_CLK     |\
+		     PSDMR_PRETOACT_3W    |\
+		     PSDMR_ACTTORW_2W     |\
+		     PSDMR_LDOTOPRE_1C    |\
+		     PSDMR_WRC_1C         |\
+		     PSDMR_CL_2)
+#endif /* (CFG_SDRAM0_SIZE == 16) */
+
+/* With a 64 MB DIMM, the OR2 is configured as follows:
+ *
+ *     - 64 MB
+ *     - 4 internal banks per device
+ *     - Row start address bit is A8 with PSDMR[PBI] = 0
+ *     - 12 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+#if (CFG_SDRAM0_SIZE == 64)
+#define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
+	     ORxS_BPD_4         |\
+	     ORxS_ROWST_PBI0_A8     |\
+	     ORxS_NUMR_12)
+
+/* With a 64 MB DIMM, the PSDMR is configured as follows:
+ *
+ *     - Page Based Interleaving,
+ *     - Refresh Enable,
+ *     - Address Multiplexing where A5 is output on A14 pin
+ *       (A6 on A15, and so on),
+ *     - use address pins A14-A16 as bank select,
+ *     - A9 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *       is 3 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *       2 clocks,
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - CAS Latency is 2.
+ */
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x Bus SDRAM Mode Register
+ *     Ref: Section 10.3.3 on page 10-21
+ *-----------------------------------------------------------------------
+ */
+#define CFG_PSDMR   (PSDMR_RFEN       |\
+		     PSDMR_SDAM_A14_IS_A5 |\
+		     PSDMR_BSMA_A14_A16   |\
+		     PSDMR_SDA10_PBI0_A9  |\
+		     PSDMR_RFRC_7_CLK     |\
+		     PSDMR_PRETOACT_3W    |\
+		     PSDMR_ACTTORW_2W     |\
+		     PSDMR_LDOTOPRE_1C    |\
+		     PSDMR_WRC_1C         |\
+		     PSDMR_CL_2)
+#endif  /* (CFG_SDRAM0_SIZE == 64) */
+
+#define CFG_PSRT    0x0e
+#define CFG_MPTPR   MPTPR_PTP_DIV32
+
+
+/*-----------------------------------------------------------------------
+ * BR4 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR4 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+/* Bank 4 - Onboard Memory Mapped IO controller
+ *
+ * This expects the onboard IO controller to connected to *CS4 and
+ * the local bus.
+ *     - Base address of 0xe0000000
+ *     - 8 bit port size (local bus only)
+ *     - Read and write access
+ *     - GPCM local bus
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ *     - extended hold time
+ *     - 11 wait states
+ */
+
+#ifdef CFG_IO_BASE
+#  define CFG_BR4_PRELIM  ((CFG_IO_BASE & BRx_BA_MSK)  |\
+			    BRx_PS_8                   |\
+			    BRx_MS_GPCM_L              |\
+			    BRx_V)
+
+#  define CFG_OR4_PRELIM   (ORxG_AM_MSK                |\
+			    ORxG_SCY_11_CLK            |\
+			    ORxG_EHTR)
+#endif /* CFG_IO_BASE */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM   0x02    /* Software reboot           */
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/h2_p2_dbg_board.h b/include/configs/h2_p2_dbg_board.h
new file mode 100755
index 0000000..e0d823f
--- /dev/null
+++ b/include/configs/h2_p2_dbg_board.h
@@ -0,0 +1,138 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   TI H2 and P2 Debug Board hardware map
+ *
+ * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
+ * Author: MPC-Data Limited
+ *	   Dave Peverley
+ *
+ *  This program is free software; you can redistribute	 it and/or modify it
+ *  under  the terms of	 the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the	License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
+ *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
+ *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __INCLUDED_H2_P2_DBH_BOARD_H
+#define __INCLUDED_H2_P2_DBH_BOARD_H
+
+#include <asm/arch/sizes.h>
+
+/*
+ * The Debug board is designed to function with the P2 Sample, H2
+ * Sample and 1610 Innovator boards. The main difference AFAICT is
+ * the chip selects used with each system ;
+ *
+ *   P2 Sample : CS1 of OMAP730 is used to select the CPLD & LAN regs
+ *   H2 Sample : CS1a is used to select the CPLD registers.
+ *
+ */
+
+/***************************************************************************
+ * CPLD Registers
+ **************************************************************************/
+
+#define H2DBG_CPLD_REVISION        0x04000010
+#define H2DBG_BOARD_REVISION       0x04000012
+#define H2DBG_GPIO_REGISTER        0x04000014
+#define H2DBG_LED_CONTROL          0x04000016
+#define H2DBG_MISC_INPUT           0x04000018
+#define H2DBG_LAN_STATUS           0x0400001A
+#define H2DBG_LAN_RESET            0x0400001C
+#define H2DBG_ETH_REG_BASE         0x04000300
+
+/***************************************************************************
+ * Ethernet Control Registers
+ * These are for the LAN91C96 on the debug board
+ **************************************************************************/
+
+/* Bank 0 in IO space */
+
+#define ETH_TCR            (H2DBG_ETH_REG_BASE + 0x00)   /* Transmit Control Register */
+#define ETH_EPH_STATUS     (H2DBG_ETH_REG_BASE + 0x02)   /* EPH Status Register */
+#define ETH_RCR            (H2DBG_ETH_REG_BASE + 0x04)   /* Receive Control Register */
+#define ETH_COUNTER        (H2DBG_ETH_REG_BASE + 0x06)   /* Counter Register */
+#define ETH_MIR            (H2DBG_ETH_REG_BASE + 0x08)   /* Memory Information Register */
+#define ETH_MCR            (H2DBG_ETH_REG_BASE + 0x0A)   /* Memory Configuration Register */
+
+/* Bank 1 in IO space */
+
+#define ETH_CONFIG         (H2DBG_ETH_REG_BASE + 0x00)   /* Configuration Register */
+#define ETH_BASE           (H2DBG_ETH_REG_BASE + 0x02)   /* Base Address Register */
+#define ETH_IA0            (H2DBG_ETH_REG_BASE + 0x04)   /* Individual Address Register - 0 */
+#define ETH_IA1            (H2DBG_ETH_REG_BASE + 0x05)   /* Individual Address Register - 1 */
+#define ETH_IA2            (H2DBG_ETH_REG_BASE + 0x06)   /* Individual Address Register - 2 */
+#define ETH_IA3            (H2DBG_ETH_REG_BASE + 0x07)   /* Individual Address Register - 3 */
+#define ETH_IA4            (H2DBG_ETH_REG_BASE + 0x08)   /* Individual Address Register - 4 */
+#define ETH_IA5            (H2DBG_ETH_REG_BASE + 0x09)   /* Individual Address Register - 5 */
+#define ETH_GEN_PURPOSE    (H2DBG_ETH_REG_BASE + 0x0A)   /* General Address Registers */
+#define ETH_CONTROL        (H2DBG_ETH_REG_BASE + 0x0B)   /* Control Register */
+
+/* Bank 2 in IO space */
+
+#define ETH_MMU            (H2DBG_ETH_REG_BASE + 0x00)   /* MMU Command Register */
+#define ETH_AUTO_TX_START  (H2DBG_ETH_REG_BASE + 0x01)   /* Auto Tx Start Register */
+#define ETH_PNR            (H2DBG_ETH_REG_BASE + 0x02)   /* Packet Number Register */
+#define ETH_ARR            (H2DBG_ETH_REG_BASE + 0x03)   /* Allocation Result Register */
+#define ETH_FIFO           (H2DBG_ETH_REG_BASE + 0x04)   /* FIFO Ports Register */
+#define ETH_POINTER        (H2DBG_ETH_REG_BASE + 0x06)   /* Pointer Register */
+#define ETH_DATA_HIGH      (H2DBG_ETH_REG_BASE + 0x08)   /* Data High Register */
+#define ETH_DATA_LOW       (H2DBG_ETH_REG_BASE + 0x0A)   /* Data Low Register */
+#define ETH_INT_STATS      (H2DBG_ETH_REG_BASE + 0x0C)   /* Interrupt Status Register - RO */
+#define ETH_INT_ACK        (H2DBG_ETH_REG_BASE + 0x0C)   /* Interrupt Acknowledge Register -WO */
+#define ETH_INT_MASK       (H2DBG_ETH_REG_BASE + 0x0D)   /* Interrupt Mask Register */
+
+
+#ifndef __ASSEMBLY__
+
+/*
+ * A couple of utility inlines to aid debugging using the LED's on the
+ * debug board.
+ */
+
+static inline void set_led_state(int state)
+{
+	static unsigned long hw_led_state = 0;
+	volatile unsigned short *led_address = (volatile unsigned short *)0x04000016;
+
+	hw_led_state = ((unsigned long)state);
+	*((unsigned short *) (led_address)) = (unsigned short) (~hw_led_state & 0xFFFF);
+}
+
+
+static inline void spin_up_leds(void)
+{
+	volatile int i, j, k;
+
+	for (k = 0; k < 2; k++) {
+		for (i = 0; i < 16; i++) {
+			for (j = 0; j < 5000; j++) {
+				set_led_state(1 << i);
+			}
+		}
+		for (i = 15; i >= 0; i--) {
+			for (j = 0; j < 5000; j++) {
+				set_led_state(1 << i);
+			}
+		}
+	}
+}
+
+#endif    /* !  __ASSEMBLY__ */
+
+#endif    /* !  __INCLUDED_H2_P2_DBH_BOARD_H */
diff --git a/include/configs/hermes.h b/include/configs/hermes.h
new file mode 100755
index 0000000..91117ba
--- /dev/null
+++ b/include/configs/hermes.h
@@ -0,0 +1,339 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860T CPU	*/
+#define CONFIG_HERMES		1	/* ...on a HERMES-PRO board	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define	CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs	*/
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_COMMANDS		CONFIG_CMD_DFL
+
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+/*----------------------------------------------------------------------*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+
+#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CFG_ALLOC_DPRAM		1	/* use allocation routines 	*/
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000	/* Non-Standard value!	*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFE000000
+#ifdef	DEBUG
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	124	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x4000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ * +0x0004
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * +0x0000 => 0x000000C0
+ */
+#define CFG_SIUMCR	0
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ * +0x0200 => 0x00C2
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ * +0x0240 => 0x0082
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* +0x0286 => 0x00B0D0C0 */
+#define CFG_PLPRCR							\
+		(	(11 << PLPRCR_MF_SHIFT) |			\
+			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
+			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
+			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
+		)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* +0x0282 => 0x03800000 */
+#define CFG_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
+			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\
+			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
+			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
+			 SCCR_DFNH000)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/* +0x0220 => 0x00C3 */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register		19-4
+ *-----------------------------------------------------------------------
+ */
+/* +0x09C4 => TIMEP=1 */
+#define CFG_RCCR 0x0100
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMDS 0
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+/* allow for max 4 MB of Flash */
+#define CFG_REMAP_OR_AM		0xFFC00000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFFC00000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0	*/
+#define CFG_OR_TIMING_FLASH	( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
+				 OR_SCY_5_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+/* 8 bit, bank valid */
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR1/OR1 - SDRAM
+ *
+ * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
+ */
+#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+#define SDRAM_TIMING		0x00000A00	/* SDRAM-Timing */
+
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
+
+#define CFG_OR1_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR2/OR2 - HPRO2: PEB2256   @ 0xE0000000, 8 Bit wide
+ */
+#define HPRO2_BASE		0xE0000000
+#define HPRO2_OR_AM		0xFFFF8000
+#define HPRO2_TIMING		0x00000934
+
+#define CFG_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
+#define CFG_BR2	((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR3/OR3: not used
+ * BR4/OR4: not used
+ * BR5/OR5: not used
+ * BR6/OR6: not used
+ * BR7/OR7: not used
+ */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h
new file mode 100755
index 0000000..cfaf153
--- /dev/null
+++ b/include/configs/hmi1001.h
@@ -0,0 +1,348 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
+#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
+#define CONFIG_HMI1001		1	/* HMI1001 board			*/
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DISPLAY	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
+
+#if (TEXT_BASE == 0xFFF00000) /* Boot low */
+#   define CFG_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+#define CONFIG_MISC_INIT_R	1
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133		/* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x58
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR		0x51
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		0xFF800000
+
+#define CFG_FLASH_SIZE		0x00800000 /* 8 MByte */
+#define CFG_MAX_FLASH_SECT	67	/* max num of sects on one chip */
+
+#define CFG_ENV_ADDR		(TEXT_BASE+0x40000) /* second sector */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_CFI_AMD_RESET
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x4000
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+#define CFG_DISPLAY_BASE	0x80600000
+#define CFG_STATUS1_BASE	0x80600200
+#define CFG_STATUS2_BASE	0x80600300
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_DDR	 1
+#define SDRAM_MODE      0x018D0000
+#define SDRAM_EMODE     0x40090000
+#define SDRAM_CONTROL   0x714f0f00
+#define SDRAM_CONFIG1   0x73722930
+#define SDRAM_CONFIG2   0x47770000
+#define SDRAM_TAPDELAY  0x10000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG	0x01051004
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x0004FB00
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+/* 8Mbit SRAM @0x80100000 */
+#define CFG_CS1_START		0x80100000
+#define CFG_CS1_SIZE		0x00100000
+#define CFG_CS1_CFG		0x19B00
+
+/* FRAM 32Kbyte @0x80700000 */
+#define CFG_CS2_START		0x80700000
+#define CFG_CS2_SIZE		0x00008000
+#define CFG_CS2_CFG		0x19800
+
+/* Display H1, Status Inputs, EPLD @0x80600000 */
+#define CFG_CS3_START		0x80600000
+#define CFG_CS3_SIZE		0x00100000
+#define CFG_CS3_CFG		0x00019800
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+
+#define CONFIG_IDE_PREINIT	1
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers                                                */
+#define CFG_ATA_STRIDE          4
+
+#define CONFIG_ATAPI            1
+
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CFG_ISA_IO		CONFIG_PCI_IO_BUS
+
+/*---------------------------------------------------------------------*/
+/* Display addresses						       */
+/*---------------------------------------------------------------------*/
+
+#define CFG_DISP_CHR_RAM	(CFG_DISPLAY_BASE + 0x38)
+#define CFG_DISP_CWORD		(CFG_DISPLAY_BASE + 0x30)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
new file mode 100755
index 0000000..8cad98d
--- /dev/null
+++ b/include/configs/hymod.h
@@ -0,0 +1,733 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Config header file for Hymod board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
+#define CONFIG_HYMOD		1	/* ...on a Hymod board		*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+
+#define CONFIG_BOARD_POSTCLK_INIT	/* have board_postclk_init() function */
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#define	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else*/
+#define	CONFIG_CONS_INDEX	1	/* which serial channel for console */
+#define	CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
+#define	CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
+#define	CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX	1	/* which channel for ether	*/
+#define CONFIG_ETHER_LOOPBACK_TEST	/* add ether external loopback test */
+
+#ifdef CONFIG_ETHER_ON_FCC
+
+#if (CONFIG_ETHER_INDEX == 1)
+
+/*
+ * - Rx-CLK is CLK10
+ * - Tx-CLK is CLK11
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+# define MDIO_PORT		0		/* Port A */
+# define MDIO_DATA_PINMASK	0x00040000	/* Pin 13 */
+# define MDIO_CLCK_PINMASK	0x00080000	/* Pin 12 */
+
+#elif (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+# define MDIO_PORT		0		/* Port A */
+# define MDIO_DATA_PINMASK	0x00000040	/* Pin 25 */
+# define MDIO_CLCK_PINMASK	0x00000080	/* Pin 24 */
+
+#elif (CONFIG_ETHER_INDEX == 3)
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK16
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+# define MDIO_PORT		0		/* Port A */
+# define MDIO_DATA_PINMASK	0x00000100	/* Pin 23 */
+# define MDIO_CLCK_PINMASK	0x00000200	/* Pin 22 */
+
+#endif	/* CONFIG_ETHER_INDEX */
+
+#define CONFIG_MII			/* MII PHY management	*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+
+#define MDIO_ACTIVE	(iop->pdir |=  MDIO_DATA_PINMASK)
+#define MDIO_TRISTATE	(iop->pdir &= ~MDIO_DATA_PINMASK)
+#define MDIO_READ	((iop->pdat &  MDIO_DATA_PINMASK) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  MDIO_DATA_PINMASK; \
+			else	iop->pdat &= ~MDIO_DATA_PINMASK
+
+#define MDC(bit)	if(bit) iop->pdat |=  MDIO_CLCK_PINMASK; \
+			else	iop->pdat &= ~MDIO_CLCK_PINMASK
+
+#define MIIDELAY	udelay(1)
+
+#endif	/* CONFIG_ETHER_ON_FCC */
+
+
+/* other options */
+#define CONFIG_HARD_I2C		1	/* To enable I2C hardware support	*/
+#define CONFIG_DTT_ADM1021	1	/* ADM1021 temp sensor support */
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#ifdef DEBUG
+#define CONFIG_8260_CLKIN	33333333	/* in Hz */
+#else
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+#endif
+
+#if defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		115200
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+/* default ip addresses - these will be overridden */
+#define CONFIG_IPADDR		192.168.1.1	/* hymod "boot" address */
+#define CONFIG_SERVERIP		192.168.1.254	/* hymod "server" address */
+
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
+					CFG_CMD_BEDBUG	| \
+					CFG_CMD_BMP	| \
+					CFG_CMD_DISPLAY	| \
+					CFG_CMD_DOC	| \
+					CFG_CMD_EXT2	| \
+					CFG_CMD_FDC	| \
+					CFG_CMD_FDOS	| \
+					CFG_CMD_FPGA    | \
+					CFG_CMD_HWFLOW	| \
+					CFG_CMD_IDE	| \
+					CFG_CMD_JFFS2	| \
+					CFG_CMD_NAND	| \
+					CFG_CMD_MMC	| \
+					CFG_CMD_PCMCIA	| \
+					CFG_CMD_PCI	| \
+					CFG_CMD_USB	| \
+					CFG_CMD_REISER	| \
+					CFG_CMD_SCSI	| \
+					CFG_CMD_SPI	| \
+					CFG_CMD_UNIVERSE| \
+					CFG_CMD_VFD	| \
+					CFG_CMD_XIMG	) )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#ifdef DEBUG
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#define CONFIG_BOOT_RETRY_TIME 30	/* retry autoboot after 30 secs	*/
+#define CONFIG_BOOT_RETRY_MIN	1	/* can go down to 1 second timeout */
+/* Be selective on what keys can delay or stop the autoboot process
+ *	To stop use: " "
+ */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		"Autobooting in %d seconds, " \
+					"press <SPACE> to stop\n"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define DEBUG_BOOTKEYS		0
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define	CONFIG_KGDB_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
+#define	CONFIG_KGDB_EXTC_RATE	3686400	/* serial ext clk rate in Hz */
+#define	CONFIG_KGDB_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
+# if defined(CONFIG_KGDB_USE_EXTC)
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+# else
+#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
+# endif
+#endif
+
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
+
+/*
+ * Hymod specific configurable options
+ */
+#undef	CFG_HYMOD_DBLEDS			/* walk mezz board LEDs */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x03c00000	/* 4 ... 60 MB in DRAM	*/
+
+#define CFG_CLKS_IN_HZ		1	/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define	CFG_I2C_SPEED		50000
+#define	CFG_I2C_SLAVE		0x7e
+
+/* these are for the ST M24C02 2kbit serial i2c eeprom */
+#define CFG_I2C_EEPROM_ADDR	0x50		/* base address */
+#define CFG_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+
+#define CFG_EEPROM_PAGE_WRITE_ENABLE	1	/* write eeprom in pages */
+#define CFG_EEPROM_PAGE_WRITE_BITS	4	/* 16 byte write page size */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CFG_I2C_MULTI_EEPROMS	1		/* hymod has two eeproms */
+
+#define CFG_I2C_RTC_ADDR	0x51	/* philips PCF8563 RTC address */
+
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the ADM1021, the rest determines index into
+ * CFG_DTT_ADM1021 array below.
+ *
+ * On HYMOD board, the remote sensor should be connected to the MPC8260
+ * temperature diode thingy, but an errata said this didn't work and
+ * should be disabled - so it isn't connected.
+ */
+#if 0
+#define CONFIG_DTT_SENSORS		{ 0, 1 }
+#else
+#define CONFIG_DTT_SENSORS		{ 0 }
+#endif
+
+/*
+ * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
+ * there will be one entry in this array for each two (dummy) sensors in
+ * CONFIG_DTT_SENSORS.
+ *
+ * For HYMOD board:
+ * - only one ADM1021
+ * - i2c addr 0x2a (both ADD0 and ADD1 are N/C)
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
+ * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above)
+ */
+#define CFG_DTT_ADM1021		{ { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CFG_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
+ */
+#ifdef DEBUG
+#define CFG_HRCW_MASTER	(HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
+			 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
+			 HRCW_MODCK_H0010)
+#else
+#define CFG_HRCW_MASTER	(HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
+			 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
+			 HRCW_MODCK_H0101)
+#endif
+/* no slaves so just duplicate the master hrcw */
+#define CFG_HRCW_SLAVE1	CFG_HRCW_MASTER
+#define CFG_HRCW_SLAVE2	CFG_HRCW_MASTER
+#define CFG_HRCW_SLAVE3	CFG_HRCW_MASTER
+#define CFG_HRCW_SLAVE4	CFG_HRCW_MASTER
+#define CFG_HRCW_SLAVE5	CFG_HRCW_MASTER
+#define CFG_HRCW_SLAVE6	CFG_HRCW_MASTER
+#define CFG_HRCW_SLAVE7	CFG_HRCW_MASTER
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		TEXT_BASE
+#define	CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_FPGA_BASE		0x80000000
+/*
+ * unfortunately, CFG_MONITOR_LEN must include the
+ * (very large i.e. 256kB) environment flash sector
+ */
+#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor*/
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
+#define CFG_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE	0x40000	/* see README - env sect real size */
+#define	CFG_ENV_ADDR	(CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#ifdef DEBUG
+#define CFG_HID0_FINAL	0
+#else
+#define CFG_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
+#endif
+#define CFG_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register					 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#ifdef DEBUG
+#define CFG_RMR		0
+#else
+#define CFG_RMR		RMR_CSRE
+#endif
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR		(BCR_ETM)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SIUMCR	(SIUMCR_DPPC10|SIUMCR_L2CPC01|\
+			 SIUMCR_APPC10|SIUMCR_MMR11)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				 4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CFG_SCCR	(SCCR_DFBRG01)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR	0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank	Bus	Machine	PortSz	Device
+ * ----	---	-------	------	------
+ *  0	60x	GPCM	32 bit	FLASH
+ *  1	60x	GPCM	32 bit	FLASH (same as 0 - unused for now)
+ *  2	60x	SDRAM	64 bit	SDRAM
+ *  3	Local	UPMC	 8 bit	Main Xilinx configuration
+ *  4	Local	GPCM	32 bit	Main Xilinx register mode
+ *  5	Local	UPMB	32 bit	Main Xilinx port mode
+ *  6	Local	UPMC	 8 bit	Mezz Xilinx configuration
+ */
+
+/*
+ * Bank 0 - FLASH
+ *
+ * Quotes from the HYMOD IO Board Reference manual:
+ *
+ * "The flash memory is two Intel StrataFlash chips, each configured for
+ *  16 bit operation and connected to give a 32 bit wide port."
+ *
+ * "The chip select logic is configured to respond to both *CS0 and *CS1.
+ *  Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
+ *  It is suggested that bank 0 be read-only and bank 1 be read/write. The
+ *  FLASH will then appear as ROM during boot."
+ *
+ * Initially, we are only going to use bank 0 in read/write mode.
+ */
+
+/* 32 bit, read-write, GPCM on 60x bus */
+#define	CFG_BR0_PRELIM	((CFG_FLASH_BASE&BRx_BA_MSK)|\
+				BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
+/* up to 32 Mb */
+#define	CFG_OR0_PRELIM	(MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
+
+/*
+ * Bank 2 - SDRAM
+ *
+ * Quotes from the HYMOD IO Board Reference manual:
+ *
+ * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
+ *  fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
+ *  dynamic random access memory organised as 4 banks by 4096 rows by 512
+ *  columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
+ *
+ * "The locations in SDRAM are accessed using multiplexed address pins to
+ *  specify row and column. The pins also act to specify commands. The state
+ *  of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
+ *  pin may function as a row address or as the AUTO PRECHARGE control line,
+ *  depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
+ *  address lines to be configured to the required multiplexing scheme."
+ */
+
+#define CFG_SDRAM_SIZE	64
+
+/* 64 bit, read-write, SDRAM on 60x bus */
+#define	CFG_BR2_PRELIM	((CFG_SDRAM_BASE&BRx_BA_MSK)|\
+				BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
+/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
+#define	CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM_SIZE)|\
+				ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
+
+/*
+ * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
+ *
+ * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
+ * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
+ * as bank select, A7 is output on SDA10 during an ACTIVATE command,
+ * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
+ * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
+ * command is 2 clocks, earliest timing for PRECHARGE after last data
+ * was read is 1 clock, earliest timing for PRECHARGE after last data
+ * was written is 1 clock, CAS Latency is 2.
+ */
+
+#define CFG_PSDMR	(PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
+				PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
+				PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
+				PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
+				PSDMR_WRC_1C|PSDMR_CL_2)
+
+/*
+ * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
+ * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
+ * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
+ * Prescaler, hence the P instead of the R). The refresh timer period is given
+ * by (note that there was a change in the 8260 UM Errata):
+ *
+ *	TimerPeriod = (PSRT + 1) / Fmptc
+ *
+ * where Fmptc is the BusClock divided by PTP. i.e.
+ *
+ *	TimerPeriod = (PSRT + 1) / (BusClock / PTP)
+ *
+ * or
+ *
+ *	TImerPeriod = (PTP * (PSRT + 1)) / BusClock
+ *
+ * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
+ * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
+ * = 15.625 usecs.
+ *
+ * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
+ * appear to be reasonable.
+ */
+
+#ifdef DEBUG
+#define CFG_PSRT	39
+#define CFG_MPTPR	MPTPR_PTP_DIV8
+#else
+#define CFG_PSRT	31
+#define CFG_MPTPR	MPTPR_PTP_DIV32
+#endif
+
+/*
+ * Banks 3,4,5 and 6 - FPGA access
+ *
+ * Quotes from the HYMOD IO Board Reference manual:
+ *
+ * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
+ *  for configuring an optional FPGA on the mezzanine interface.
+ *
+ *  Access to the FPGAs may be divided into several catagories:
+ *
+ *  1. Configuration
+ *  2. Register mode access
+ *  3. Port mode access
+ *
+ *  The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
+ *  configured only (mode 1). Consequently there are four access types.
+ *
+ *  To improve interface performance and simplify software design, the four
+ *  possible access types are separately mapped to different memory banks.
+ *
+ *  All are accessed using the local bus."
+ *
+ *	 Device		    Mode      Memory Bank Machine Port Size    Access
+ *
+ *	  Main		Configuration	   3	   UPMC	     8bit	R/W
+ *	  Main		  Register	   4	   GPCM	    32bit	R/W
+ *	  Main		    Port	   5	   UPMB	    32bit	R/W
+ *	Mezzanine	Configuration	   6	   UPMC	     8bit	W/O
+ *
+ * "Note that mezzanine mode 1 access is write-only."
+ */
+
+/* all the bank sizes must be a power of two, greater or equal to 32768 */
+#define FPGA_MAIN_CFG_BASE	(CFG_FPGA_BASE)
+#define FPGA_MAIN_CFG_SIZE	32768
+#define FPGA_MAIN_REG_BASE	(FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
+#define FPGA_MAIN_REG_SIZE	32768
+#define FPGA_MAIN_PORT_BASE	(FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
+#define FPGA_MAIN_PORT_SIZE	32768
+#define FPGA_MEZZ_CFG_BASE	(FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
+#define FPGA_MEZZ_CFG_SIZE	32768
+
+/* 8 bit, read-write, UPMC */
+#define	CFG_BR3_PRELIM	(FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
+/* up to 32Kbyte, burst inhibit */
+#define	CFG_OR3_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
+
+/* 32 bit, read-write, GPCM */
+#define	CFG_BR4_PRELIM	(FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
+/* up to 32Kbyte */
+#define	CFG_OR4_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
+
+/* 32 bit, read-write, UPMB */
+#define	CFG_BR5_PRELIM	(FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
+/* up to 32Kbyte */
+#define	CFG_OR5_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
+
+/* 8 bit, write-only, UPMC */
+#define	CFG_BR6_PRELIM	(FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
+/* up to 32Kbyte, burst inhibit */
+#define	CFG_OR6_PRELIM	(P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
+
+/*-----------------------------------------------------------------------
+ * MBMR - Machine B Mode					10-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MBMR	(MxMR_BSEL|MxMR_OP_NORM)	/* XXX - needs more */
+
+/*-----------------------------------------------------------------------
+ * MCMR - Machine C Mode					10-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_MCMR	(MxMR_BSEL|MxMR_DSx_2_CYCL)	/* XXX - needs more */
+
+/*
+ * FPGA I/O Port/Bit information
+ */
+
+#define FPGA_MAIN_PROG_PORT	IOPIN_PORTA
+#define FPGA_MAIN_PROG_PIN	4	/* PA4 */
+#define FPGA_MAIN_INIT_PORT	IOPIN_PORTA
+#define FPGA_MAIN_INIT_PIN	5	/* PA5 */
+#define FPGA_MAIN_DONE_PORT	IOPIN_PORTA
+#define FPGA_MAIN_DONE_PIN	6	/* PA6 */
+
+#define FPGA_MEZZ_PROG_PORT	IOPIN_PORTA
+#define FPGA_MEZZ_PROG_PIN	0	/* PA0 */
+#define FPGA_MEZZ_INIT_PORT	IOPIN_PORTA
+#define FPGA_MEZZ_INIT_PIN	1	/* PA1 */
+#define FPGA_MEZZ_DONE_PORT	IOPIN_PORTA
+#define FPGA_MEZZ_DONE_PIN	2	/* PA2 */
+#define FPGA_MEZZ_ENABLE_PORT	IOPIN_PORTA
+#define FPGA_MEZZ_ENABLE_PIN	3	/* PA3 */
+
+/*
+ * FPGA Interrupt configuration
+ */
+#define FPGA_MAIN_IRQ		SIU_INT_IRQ2
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		""
+#define MTDPARTS_DEFAULT	""
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/impa7.h b/include/configs/impa7.h
new file mode 100755
index 0000000..8b841ff
--- /dev/null
+++ b/include/configs/impa7.h
@@ -0,0 +1,164 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the implementa impA7 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
+#define CONFIG_IMPA7		1	/* on an impA7 Board      */
+#define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
+#define CONFIG_ARM7_REVD	1 	/* enable ARM720 REV.D Workarounds */
+
+#undef CONFIG_USE_IRQ			/* don't need them anymore */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
+#define CS8900_BASE		0x20000000
+#define CS8900_BUS32		1
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		1	/* we use Serial line 1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_JFFS2)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS    	"devfs=mount root=ramfs console=ttyS0,9600"
+/*#define CONFIG_ETHADDR	08:00:3e:26:0a:5a	*/
+/*#define CONFIG_NETMASK        255.255.0.0	*/
+/*#define CONFIG_IPADDR		172.22.2.128	*/
+/*#define CONFIG_SERVERIP	172.22.2.126	*/
+/*#define CONFIG_BOOTFILE	"impa7"	*/
+#define CONFIG_BOOTCOMMAND	"bootp;bootm"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"impA7 # "		/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0xc1000000	/* default load address	*/
+
+#define	CFG_HZ			2000		/* decrementer freq: 2 kHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	   /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB */
+#define PHYS_SDRAM_2		0xc1000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x00800000 /* 8 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0x10000000 /* Flash Bank #2 */
+#define PHYS_FLASH_SIZE		0x00800000 /* 16 MB */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x1C000)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00020000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=impA7 NOR Flash Bank #0,nor1=impA7 NOR Flash Bank #1"
+#define MTDPARTS_DEFAULT	"mtdparts=impA7 NOR Flash Bank #0:-(FileSystem1);impA7 NOR Flash Bank #1:-(FileSystem2)"
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/incaip.h b/include/configs/incaip.h
new file mode 100755
index 0000000..1c6216b
--- /dev/null
+++ b/include/configs/incaip.h
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the INCA-IP board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS32		1	/* MIPS 4Kc CPU core	*/
+#define CONFIG_INCA_IP		1	/* on a INCA-IP Board	*/
+
+#ifndef	CPU_CLOCK_RATE
+/* allowed values: 100000000, 133000000, and 150000000 */
+#define CPU_CLOCK_RATE	150000000	/* default: 150 MHz clock for the MIPS core */
+#endif
+
+#define INFINEON_EBU_BOOTCFG	0x40C4	/* CMULT = 8 */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BAUDRATE		115200
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0"				\
+	"addmisc=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate} "				\
+		"ethaddr=${ethaddr} "					\
+		"panic=1\0"						\
+	"flash_nfs=run nfsargs addip addmisc;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addmisc;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 80500000 ${bootfile};"				\
+		"run nfsargs addip addmisc;bootm\0"			\
+	"rootpath=/opt/eldk/mips_4KC\0"					\
+	"bootfile=/tftpboot/INCA/uImage\0"				\
+	"kernel_addr=B0040000\0"					\
+	"ramdisk_addr=B0100000\0"					\
+	"u-boot=/tftpboot/INCA/u-boot.bin\0"				\
+	"load=tftp 80500000 ${u-boot}\0"				\
+	"update=protect off 1:0-2;era 1:0-2;"				\
+		"cp.b 80500000 B0000000 ${filesize}\0"			\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_SNTP	)
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory      */
+#define	CFG_PROMPT		"INCA-IP # "	/* Monitor Command Prompt    */
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args*/
+
+#define CFG_MALLOC_LEN		128*1024
+
+#define CFG_BOOTPARAMS_LEN	128*1024
+
+#define CFG_HZ			(incaip_get_cpuclk() / 2)
+
+#define CFG_SDRAM_BASE		0x80000000
+
+#define	CFG_LOAD_ADDR		0x80100000	/* default load address	*/
+
+#define CFG_MEMTEST_START	0x80100000
+#define CFG_MEMTEST_END		0x80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+
+#define PHYS_FLASH_1		0xb0000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0xb0800000 /* Flash Bank #2 */
+
+/* The following #defines are needed to get flash environment right */
+#define	CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MONITOR_LEN		(192 << 10)
+
+#define CFG_INIT_SP_OFFSET	0x400000
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+
+/* Address and size of Primary Environment Sector	*/
+#define CFG_ENV_ADDR		0xB0030000
+#define CFG_ENV_SIZE		0x10000
+
+#define CONFIG_FLASH_16BIT
+
+#define CONFIG_NR_DRAM_BANKS	1
+
+#define CONFIG_INCA_IP_SWITCH
+#define CONFIG_NET_MULTI
+#define CONFIG_INCA_IP_SWITCH_AMDIX
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition, use all space on the device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor1"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=INCA-IP Bank 0"
+#define MTDPARTS_DEFAULT	"mtdparts=INCA-IP Bank 0:192k(uboot)," \
+							"64k(env)," \
+							"768k(linux)," \
+							"1m@3m(rootfs)," \
+							"768k(linux2)," \
+							"3m@5m(rootfs2)"
+*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		4096
+#define CFG_ICACHE_SIZE		4096
+#define CFG_CACHELINE_SIZE	16
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
new file mode 100755
index 0000000..c0cc4f1
--- /dev/null
+++ b/include/configs/inka4x0.h
@@ -0,0 +1,318 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
+#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
+#define CONFIG_INKA4X0		1	/* INKA4x0 board			*/
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+#define CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CFG_XLB_PIPELINING	1
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EXT2	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_SNTP	| \
+				CFG_CMD_USB	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
+
+#if (TEXT_BASE == 0xFFE00000)		/* Boot low */
+#   define CFG_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		0xFFE00000
+
+#define CFG_FLASH_SIZE		0x00200000 /* 2 MByte */
+#define CFG_MAX_FLASH_SECT	35	/* max num of sects on one chip */
+
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000) /* second sector */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x2000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+#define CONFIG_MPC5200_DDR
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ *
+ * use CS1 as gpio_wkup_6 output
+ *	Bit 0 (mask: 0x80000000): 0
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ *	00 -> No Alternatives, I2C1 is used for onboard EEPROM
+ *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
+ *	      EEPROM
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
+ *	011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
+ */
+#define CFG_GPS_PORT_CONFIG	0x01001004
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x00087800 /* for pci_clk  = 66 MHz */
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+/* 32Mbit SRAM @0x30000000 */
+#define CFG_CS1_START		0x30000000
+#define CFG_CS1_SIZE		0x00400000
+#define CFG_CS1_CFG		0x31800 /* for pci_clk = 33 MHz */
+
+/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
+#define CFG_CS2_START		0x80000000
+#define CFG_CS2_SIZE		0x0001000
+#define CFG_CS2_CFG		0x21800  /* for pci_clk = 33 MHz */
+
+/* GPIO in @0x30400000 */
+#define CFG_CS3_START		0x30400000
+#define CFG_CS3_SIZE		0x00100000
+#define CFG_CS3_CFG		0x31800 /* for pci_clk = 33 MHz */
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_CLOCK	0x00015555
+#define CONFIG_USB_CONFIG	0x00001000
+#define CONFIG_USB_STORAGE
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CFG_ATA_DATA_OFFSET	0x0060	/* Offset for data I/O		*/
+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET	0x005C	/* Offset for alternate registers */
+#define CFG_ATA_STRIDE          4	/* Interval between registers	*/
+
+#define CONFIG_ATAPI            1
+
+#define CFG_BRIGHTNESS          0xFF	/* LCD Default Brightness (255 = off) */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
new file mode 100755
index 0000000..3cb9ebc
--- /dev/null
+++ b/include/configs/innokom.h
@@ -0,0 +1,468 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
+ *
+ * Configuration for the Auerswald Innokom CPU board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * include/configs/innokom.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA250 		1	/* This is an PXA250 CPU            */
+#define CONFIG_INNOKOM		1	/* on an Auerswald Innokom board    */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
+					/* for timer/console/ethernet       */
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART		1	/* we use FFUART on CSB226 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		19200
+#define CONFIG_MISC_INIT_R	1	/* we have a misc_init_r() function */
+
+#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP|CFG_CMD_CACHE)
+/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)   */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+/* #define CONFIG_BOOTARGS	"root=/dev/nfs ip=bootp console=ttyS0,19200" */
+#define CONFIG_BOOTARGS		"console=ttyS0,19200"
+#define CONFIG_ETHADDR		FF:FF:FF:FF:FF:FF
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.1.56
+#define CONFIG_SERVERIP		192.168.1.2
+#define CONFIG_BOOTCOMMAND	"bootm 0x40000"
+#define CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_CMDLINE_TAG	1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(256*1024)
+#define CFG_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
+
+#define CFG_LONGHELP				/* undef to save memory         */
+#define CFG_PROMPT		"uboot> "	/* Monitor Command Prompt       */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size      */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args   */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START	0xa0400000      /* memtest works on     */
+#define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
+
+#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR           0xa3000000      /* load kernel to this address   */
+
+#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
+						/* RS: the oscillator is actually 3680130?? */
+
+#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
+						/* 0101000001 */
+						/*      ^^^^^ Memory Speed 99.53 MHz         */
+						/*    ^^      Run Mode Speed = 2x Mem Speed  */
+						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
+
+#define CFG_MONITOR_LEN		0x20000		/* 128 KiB */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * I2C bus
+ */
+#define CONFIG_HARD_I2C 		1
+#define CFG_I2C_SPEED 			50000
+#define CFG_I2C_SLAVE 			0xfe
+
+#define CFG_ENV_IS_IN_EEPROM 		1
+
+#define CFG_ENV_OFFSET			0x00	/* environment starts here  */
+#define CFG_ENV_SIZE			1024	/* 1 KiB                    */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* A0 = 0 (hardwired)       */
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets       */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	15	/* between stop and start   */
+#define CFG_I2C_EEPROM_ADDR_LEN		2	/* length of address        */
+#define CFG_EEPROM_SIZE			4096	/* size in bytes            */
+#define CFG_I2C_INIT_BOARD		1	/* board has it's own init  */
+
+/*
+ * SMSC91C111 Network Card
+ */
+#define CONFIG_DRIVER_SMC91111		1
+#define CONFIG_SMC91111_BASE		0x14000000 /* chip select 5         */
+#undef  CONFIG_SMC_USE_32_BIT		           /* 16 bit bus access     */
+#undef  CONFIG_SMC_91111_EXT_PHY		   /* we use internal phy   */
+#define CONFIG_SMC_AUTONEG_TIMEOUT	10	   /* timeout 10 seconds    */
+#undef  CONFIG_SHOW_ACTIVITY
+#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
+#ifdef  CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM   */
+#define PHYS_SDRAM_1		0xa0000000	/* SDRAM Bank #1            */
+#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB                    */
+
+#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1            */
+#define PHYS_FLASH_SIZE		0x01000000	/* 16 MB                    */
+
+#define CFG_DRAM_BASE		0xa0000000	/* RAM starts here          */
+#define CFG_DRAM_SIZE		0x04000000
+
+#define CFG_FLASH_BASE          PHYS_FLASH_1
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* development flash */
+#define CONFIG_MTD_INNOKOM_16MB	1
+#undef CONFIG_MTD_INNOKOM_64MB
+
+/* production flash */
+/*
+#define CONFIG_MTD_INNOKOM_64MB	1
+#undef CONFIG_MTD_INNOKOM_16MB
+*/
+
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=innokom-0"
+*/
+
+/* development flash */
+/*
+#define MTDPARTS_DEFAULT	"mtdparts=innokom-0:256k(uboot),768k(kernel),8m(user),7m(data)"
+*/
+
+/* production flash */
+/*
+#define MTDPARTS_DEFAULT	"mtdparts=innokom-0:256k(uboot),768k(kernel),16256k(user1),16256k(user2),32m(data)"
+*/
+
+/*
+ * GPIO settings
+ *
+ * GP15 == nCS1      is 1
+ * GP24 == SFRM      is 1
+ * GP25 == TXD       is 1
+ * GP33 == nCS5      is 1
+ * GP39 == FFTXD     is 1
+ * GP41 == RTS       is 1
+ * GP47 == TXD       is 1
+ * GP49 == nPWE      is 1
+ * GP62 == LED_B     is 1
+ * GP63 == TDM_OE    is 1
+ * GP78 == nCS2      is 1
+ * GP79 == nCS3      is 1
+ * GP80 == nCS4      is 1
+ */
+#define CFG_GPSR0_VAL       0x03008000
+#define CFG_GPSR1_VAL       0xC0028282
+#define CFG_GPSR2_VAL       0x0001C000
+
+/* GP02 == DON_RST   is 0
+ * GP23 == SCLK      is 0
+ * GP45 == USB_ACT   is 0
+ * GP60 == PLLEN     is 0
+ * GP61 == LED_A     is 0
+ * GP73 == SWUPD_LED is 0
+ */
+#define CFG_GPCR0_VAL       0x00800004
+#define CFG_GPCR1_VAL       0x30002000
+#define CFG_GPCR2_VAL       0x00000100
+
+/* GP00 == DON_READY is input
+ * GP01 == DON_OK    is input
+ * GP02 == DON_RST   is output
+ * GP03 == RESET_IND is input
+ * GP07 == RES11     is input
+ * GP09 == RES12     is input
+ * GP11 == SWUPDATE  is input
+ * GP14 == nPOWEROK  is input
+ * GP15 == nCS1      is output
+ * GP17 == RES22     is input
+ * GP18 == RDY       is input
+ * GP23 == SCLK      is output
+ * GP24 == SFRM      is output
+ * GP25 == TXD       is output
+ * GP26 == RXD       is input
+ * GP32 == RES21     is input
+ * GP33 == nCS5      is output
+ * GP34 == FFRXD     is input
+ * GP35 == CTS       is input
+ * GP39 == FFTXD     is output
+ * GP41 == RTS       is output
+ * GP42 == USB_OK    is input
+ * GP45 == USB_ACT   is output
+ * GP46 == RXD       is input
+ * GP47 == TXD       is output
+ * GP49 == nPWE      is output
+ * GP58 == nCPUBUSINT is input
+ * GP59 == LANINT    is input
+ * GP60 == PLLEN     is output
+ * GP61 == LED_A     is output
+ * GP62 == LED_B     is output
+ * GP63 == TDM_OE    is output
+ * GP64 == nDSPINT   is input
+ * GP65 == STRAP0    is input
+ * GP67 == STRAP1    is input
+ * GP69 == STRAP2    is input
+ * GP70 == STRAP3    is input
+ * GP71 == STRAP4    is input
+ * GP73 == SWUPD_LED is output
+ * GP78 == nCS2      is output
+ * GP79 == nCS3      is output
+ * GP80 == nCS4      is output
+ */
+#define CFG_GPDR0_VAL       0x03808004
+#define CFG_GPDR1_VAL       0xF002A282
+#define CFG_GPDR2_VAL       0x0001C200
+
+/* GP15 == nCS1  is AF10
+ * GP18 == RDY   is AF01
+ * GP23 == SCLK  is AF10
+ * GP24 == SFRM  is AF10
+ * GP25 == TXD   is AF10
+ * GP26 == RXD   is AF01
+ * GP33 == nCS5  is AF10
+ * GP34 == FFRXD is AF01
+ * GP35 == CTS   is AF01
+ * GP39 == FFTXD is AF10
+ * GP41 == RTS   is AF10
+ * GP46 == RXD   is AF10
+ * GP47 == TXD   is AF01
+ * GP49 == nPWE  is AF10
+ * GP78 == nCS2  is AF10
+ * GP79 == nCS3  is AF10
+ * GP80 == nCS4  is AF10
+ */
+#define CFG_GAFR0_L_VAL     0x80000000
+#define CFG_GAFR0_U_VAL     0x001A8010
+#define CFG_GAFR1_L_VAL     0x60088058
+#define CFG_GAFR1_U_VAL     0x00000008
+#define CFG_GAFR2_L_VAL     0xA0000000
+#define CFG_GAFR2_U_VAL     0x00000002
+
+
+/* FIXME: set GPIO_RER/FER */
+
+/* RDH = 1
+ * PH  = 1
+ * VFS = 1
+ * BFS = 1
+ * SSS = 1
+ */
+#define CFG_PSSR_VAL		0x37
+
+/*
+ * Memory settings
+ *
+ * This is the configuration for nCS0/1 -> flash banks
+ * configuration for nCS1:
+ * [31]    0    - Slower Device
+ * [30:28] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
+ * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
+ * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
+ * [19]    1    - 16 Bit bus width
+ * [18:16] 000  - nonburst RAM or FLASH
+ * configuration for nCS0:
+ * [15]    0    - Slower Device
+ * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
+ * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
+ * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
+ * [03]    1    - 16 Bit bus width
+ * [02:00] 000  - nonburst RAM or FLASH
+ */
+#define CFG_MSC0_VAL		0x25b825b8 /* flash banks                   */
+
+/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
+ * configuration for nCS3: DSP
+ * [31]    0    - Slower Device
+ * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
+ * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
+ * [19]    1    - 16 Bit bus width
+ * [18:16] 100  - variable latency I/O
+ * configuration for nCS2: TDM-Switch
+ * [15]    0    - Slower Device
+ * [14:12] 101  - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
+ * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
+ * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
+ * [03]    1    - 16 Bit bus width
+ * [02:00] 100  - variable latency I/O
+ */
+#define CFG_MSC1_VAL		0x123C593C /* TDM switch, DSP               */
+
+/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
+ *
+ * configuration for nCS5: LAN Controller
+ * [31]    0    - Slower Device
+ * [30:28] 001  - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
+ * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
+ * [19]    1    - 16 Bit bus width
+ * [18:16] 100  - variable latency I/O
+ * configuration for nCS4: ExtBus
+ * [15]    0    - Slower Device
+ * [14:12] 110  - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
+ * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
+ * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
+ * [03]    1    - 16 Bit bus width
+ * [02:00] 100  - variable latency I/O
+ */
+#define CFG_MSC2_VAL		0x123C6CDC /* extra bus, LAN controller     */
+
+/* MDCNFG: SDRAM Configuration Register
+ *
+ * [31:29]   000 - reserved
+ * [28]      0	 - no SA1111 compatiblity mode
+ * [27]      0   - latch return data with return clock
+ * [26]      0   - alternate addressing for pair 2/3
+ * [25:24]   00  - timings
+ * [23]      0   - internal banks in lower partition 2/3 (not used)
+ * [22:21]   00  - row address bits for partition 2/3 (not used)
+ * [20:19]   00  - column address bits for partition 2/3 (not used)
+ * [18]      0   - SDRAM partition 2/3 width is 32 bit
+ * [17]      0   - SDRAM partition 3 disabled
+ * [16]      0   - SDRAM partition 2 disabled
+ * [15:13]   000 - reserved
+ * [12]      1	 - SA1111 compatiblity mode
+ * [11]      1   - latch return data with return clock
+ * [10]      0   - no alternate addressing for pair 0/1
+ * [09:08]   01  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
+ * [7]       1   - 4 internal banks in lower partition pair
+ * [06:05]   10  - 13 row address bits for partition 0/1
+ * [04:03]   01  - 9 column address bits for partition 0/1
+ * [02]      0   - SDRAM partition 0/1 width is 32 bit
+ * [01]      0   - disable SDRAM partition 1
+ * [00]      1   - enable  SDRAM partition 0
+ */
+/* use the configuration above but disable partition 0 */
+#define CFG_MDCNFG_VAL		0x000019c8
+
+/* MDREFR: SDRAM Refresh Control Register
+ *
+ * [32:26] 0     - reserved
+ * [25]    0     - K2FREE: not free running
+ * [24]    0     - K1FREE: not free running
+ * [23]    1     - K0FREE: not free running
+ * [22]    0     - SLFRSH: self refresh disabled
+ * [21]    0     - reserved
+ * [20]    0     - APD: no auto power down
+ * [19]    0     - K2DB2: SDCLK2 is MemClk
+ * [18]    0     - K2RUN: disable SDCLK2
+ * [17]    0     - K1DB2: SDCLK1 is MemClk
+ * [16]    1     - K1RUN: enable SDCLK1
+ * [15]    1     - E1PIN: SDRAM clock enable
+ * [14]    1     - K0DB2: SDCLK0 is MemClk
+ * [13]    0     - K0RUN: disable SDCLK0
+ * [12]    1     - E0PIN: disable SDCKE0
+ * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
+ */
+#define CFG_MDREFR_VAL		0x0081D018
+
+/* MDMRS: Mode Register Set Configuration Register
+ *
+ * [31]      0       - reserved
+ * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
+ * [22:20]   000     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
+ * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
+ * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
+ * [15]      0       - reserved
+ * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
+ * [06:04]   010     - MDCL0:  SDRAM0/1 Cas Latency.
+ * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
+ * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
+ */
+#define CFG_MDMRS_VAL		0x00020022
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL		0x00000000
+#define CFG_MCMEM0_VAL		0x00000000
+#define CFG_MCMEM1_VAL		0x00000000
+#define CFG_MCATT0_VAL		0x00000000
+#define CFG_MCATT1_VAL		0x00000000
+#define CFG_MCIO0_VAL		0x00000000
+#define CFG_MCIO1_VAL		0x00000000
+
+/*
+#define CSB226_USER_LED0	0x00000008
+#define CSB226_USER_LED1	0x00000010
+#define CSB226_USER_LED2	0x00000020
+*/
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS     1	/* max number of memory banks       */
+#define CFG_MAX_FLASH_SECT	128	/* max number of sect. on one chip  */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase       */
+#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write       */
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
new file mode 100755
index 0000000..2f6e399
--- /dev/null
+++ b/include/configs/integratorap.h
@@ -0,0 +1,280 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ * Configuration for Integrator AP board.
+ *.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CFG_MEMTEST_START	0x100000
+#define CFG_MEMTEST_END		0x10000000
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		24000000	/* Timer 1 is clocked at 24Mhz */
+#define CFG_TIMERBASE		0x13000100	/* Timer1		       */
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r during start up */
+
+#undef CONFIG_INIT_CRITICAL
+#define CONFIG_CM_INIT		1
+#define CONFIG_CM_REMAP		1
+#undef CONFIG_CM_SPD_DETECT
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * PL010 Configuration
+ */
+#define CFG_PL010_SERIAL
+#define CONFIG_CONS_INDEX	0
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_PL01x_PORTS	{ (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) }
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CFG_SERIAL0		0x16000000
+#define CFG_SERIAL1		0x17000000
+
+/*#define CONFIG_COMMANDS	(CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */
+/*#define CONFIG_NET_MULTI */
+/*#define CONFIG_BOOTP_MASK	  CONFIG_BOOTP_DEFAULT */
+
+#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty"
+#define CONFIG_BOOTCOMMAND	""
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP	/* undef to save memory	    */
+#define CFG_PROMPT	"Integrator-AP # "	/* Monitor Command Prompt   */
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
+/* Print Buffer Size */
+#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#define CFG_LOAD_ADDR	0x7fc0	/* default load address */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
+
+#define CFG_FLASH_BASE		0x24000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_ENV_IS_NOWHERE
+#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define PHYS_FLASH_SIZE		0x01000000	/* 16MB */
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Write */
+#define CFG_MAX_FLASH_SECT	128
+#define CFG_ENV_SIZE		32768
+
+#define PHYS_FLASH_1		(CFG_FLASH_BASE)
+
+/*-----------------------------------------------------------------------
+ * PCI definitions
+ */
+
+/*#define CONFIG_PCI			/--* include pci support	*/
+#undef CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
+#define DEBUG
+
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+
+
+#define INTEGRATOR_BOOT_ROM_BASE	0x20000000
+#define INTEGRATOR_HDR0_SDRAM_BASE	0x80000000
+
+/* PCI Base area */
+#define INTEGRATOR_PCI_BASE		0x40000000
+#define INTEGRATOR_PCI_SIZE		0x3FFFFFFF
+
+/* memory map as seen by the CPU on the local bus */
+#define CPU_PCI_IO_ADRS		0x60000000	/* PCI I/O space base */
+#define CPU_PCI_IO_SIZE		0x10000
+
+#define CPU_PCI_CNFG_ADRS	0x61000000	/* PCI config space */
+#define CPU_PCI_CNFG_SIZE	0x1000000
+
+#define PCI_MEM_BASE		0x40000000   /* 512M to xxx */
+/*  unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */
+#define INTEGRATOR_PCI_IO_BASE	0x60000000   /* 16M to xxx */
+/*  unused (128-16)M from B1000000-B7FFFFFF */
+#define PCI_CONFIG_BASE		0x61000000   /* 16M to xxx */
+/*  unused ((128-16)M - 64K) from XXX */
+
+#define PCI_V3_BASE		0x62000000
+
+/* V3 PCI bridge controller */
+#define V3_BASE			0x62000000    /* V360EPC registers */
+
+#define PCI_ENET0_IOADDR	(CPU_PCI_IO_ADRS)
+#define PCI_ENET0_MEMADDR	(PCI_MEM_BASE)
+
+
+#define V3_PCI_VENDOR		0x00000000
+#define V3_PCI_DEVICE		0x00000002
+#define V3_PCI_CMD		0x00000004
+#define V3_PCI_STAT		0x00000006
+#define V3_PCI_CC_REV		0x00000008
+#define V3_PCI_HDR_CF		0x0000000C
+#define V3_PCI_IO_BASE		0x00000010
+#define V3_PCI_BASE0		0x00000014
+#define V3_PCI_BASE1		0x00000018
+#define V3_PCI_SUB_VENDOR	0x0000002C
+#define V3_PCI_SUB_ID		0x0000002E
+#define V3_PCI_ROM		0x00000030
+#define V3_PCI_BPARAM		0x0000003C
+#define V3_PCI_MAP0		0x00000040
+#define V3_PCI_MAP1		0x00000044
+#define V3_PCI_INT_STAT		0x00000048
+#define V3_PCI_INT_CFG		0x0000004C
+#define V3_LB_BASE0		0x00000054
+#define V3_LB_BASE1		0x00000058
+#define V3_LB_MAP0		0x0000005E
+#define V3_LB_MAP1		0x00000062
+#define V3_LB_BASE2		0x00000064
+#define V3_LB_MAP2		0x00000066
+#define V3_LB_SIZE		0x00000068
+#define V3_LB_IO_BASE		0x0000006E
+#define V3_FIFO_CFG		0x00000070
+#define V3_FIFO_PRIORITY	0x00000072
+#define V3_FIFO_STAT		0x00000074
+#define V3_LB_ISTAT		0x00000076
+#define V3_LB_IMASK		0x00000077
+#define V3_SYSTEM		0x00000078
+#define V3_LB_CFG		0x0000007A
+#define V3_PCI_CFG		0x0000007C
+#define V3_DMA_PCI_ADR0		0x00000080
+#define V3_DMA_PCI_ADR1		0x00000090
+#define V3_DMA_LOCAL_ADR0	0x00000084
+#define V3_DMA_LOCAL_ADR1	0x00000094
+#define V3_DMA_LENGTH0		0x00000088
+#define V3_DMA_LENGTH1		0x00000098
+#define V3_DMA_CSR0		0x0000008B
+#define V3_DMA_CSR1		0x0000009B
+#define V3_DMA_CTLB_ADR0	0x0000008C
+#define V3_DMA_CTLB_ADR1	0x0000009C
+#define V3_DMA_DELAY		0x000000E0
+#define V3_MAIL_DATA		0x000000C0
+#define V3_PCI_MAIL_IEWR	0x000000D0
+#define V3_PCI_MAIL_IERD	0x000000D2
+#define V3_LB_MAIL_IEWR		0x000000D4
+#define V3_LB_MAIL_IERD		0x000000D6
+#define V3_MAIL_WR_STAT		0x000000D8
+#define V3_MAIL_RD_STAT		0x000000DA
+#define V3_QBA_MAP		0x000000DC
+
+/* SYSTEM register bits */
+#define V3_SYSTEM_M_RST_OUT		(1 << 15)
+#define V3_SYSTEM_M_LOCK		(1 << 14)
+
+/*  PCI_CFG bits */
+#define V3_PCI_CFG_M_RETRY_EN		(1 << 10)
+#define V3_PCI_CFG_M_AD_LOW1		(1 << 9)
+#define V3_PCI_CFG_M_AD_LOW0		(1 << 8)
+
+/* PCI MAP register bits (PCI -> Local bus) */
+#define V3_PCI_MAP_M_MAP_ADR		0xFFF00000
+#define V3_PCI_MAP_M_RD_POST_INH	(1 << 15)
+#define V3_PCI_MAP_M_ROM_SIZE		(1 << 11 | 1 << 10)
+#define V3_PCI_MAP_M_SWAP		(1 << 9 | 1 << 8)
+#define V3_PCI_MAP_M_ADR_SIZE		0x000000F0
+#define V3_PCI_MAP_M_REG_EN		(1 << 1)
+#define V3_PCI_MAP_M_ENABLE		(1 << 0)
+
+/* 9 => 512M window size */
+#define V3_PCI_MAP_M_ADR_SIZE_512M	0x00000090
+
+/* A => 1024M window size */
+#define V3_PCI_MAP_M_ADR_SIZE_1024M	0x000000A0
+
+/* LB_BASE register bits (Local bus -> PCI) */
+#define V3_LB_BASE_M_MAP_ADR		0xFFF00000
+#define V3_LB_BASE_M_SWAP		(1 << 8 | 1 << 9)
+#define V3_LB_BASE_M_ADR_SIZE		0x000000F0
+#define V3_LB_BASE_M_PREFETCH		(1 << 3)
+#define V3_LB_BASE_M_ENABLE		(1 << 0)
+
+/* PCI COMMAND REGISTER bits */
+#define V3_COMMAND_M_FBB_EN		(1 << 9)
+#define V3_COMMAND_M_SERR_EN		(1 << 8)
+#define V3_COMMAND_M_PAR_EN		(1 << 6)
+#define V3_COMMAND_M_MASTER_EN		(1 << 2)
+#define V3_COMMAND_M_MEM_EN		(1 << 1)
+#define V3_COMMAND_M_IO_EN		(1 << 0)
+
+#define INTEGRATOR_SC_BASE		0x11000000
+#define INTEGRATOR_SC_PCIENABLE_OFFSET	0x18
+#define INTEGRATOR_SC_PCIENABLE \
+			(INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
+
+/*-----------------------------------------------------------------------
+ * There are various dependencies on the core module (CM) fitted
+ * Users should refer to their CM user guide
+ * - when porting adjust u-boot/Makefile accordingly
+ *   to define the necessary CONFIG_ s for the CM involved
+ * see e.g. integratorcp_CM926EJ-S_config
+ */
+#include "armcoremodule.h"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
new file mode 100755
index 0000000..4189f9c
--- /dev/null
+++ b/include/configs/integratorcp.h
@@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ * Configuration for Compact Integrator board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CFG_MEMTEST_START	0x100000
+#define CFG_MEMTEST_END		0x10000000
+#define CFG_HZ			1000
+#define CFG_HZ_CLOCK		1000000	/* Timer 1 is clocked at 1Mhz */
+#define CFG_TIMERBASE		0x13000100
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_MISC_INIT_R		1	/* call misc_init_r during start up */
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC_USE_32_BIT
+#define CONFIG_SMC91111_BASE    0xC8000000
+#undef CONFIG_SMC91111_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK	14745600
+#define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
+#define CONFIG_CONS_INDEX	0
+#define CONFIG_BAUDRATE		38400
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CFG_SERIAL0		0x16000000
+#define CFG_SERIAL1		0x17000000
+
+/*
+#define CONFIG_COMMANDS		(CFG_CMD_DFL | CFG_CMD_PCI)
+*/
+#define CONFIG_COMMANDS		(CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | \
+				 CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV \
+				)
+
+/* #define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if 0
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_BOOTARGS	"root=/dev/nfs nfsroot=<IP address>:/<exported rootfs>  mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
+#define CONFIG_BOOTCOMMAND "bootp ; bootm"
+#endif
+/* The kernel command line & boot command below are for a platform flashed with afu.axf
+
+Image 666 Block  0 End Block  0 address 0x24000000 exec 0x24000000- name u-boot
+Image 667 Block  1 End Block 13 address 0x24040000 exec 0x24040000- name u-linux
+Image 668 Block 14 End Block 33 address 0x24380000 exec 0x24380000- name rootfs
+SIB at Block62 End Block62 address 0x24f80000
+
+*/
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_BOOTARGS	"root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0 console=ttyAMA0"
+#define CONFIG_BOOTCOMMAND "cp 0x24080000 0x7fc0 0x100000; bootm"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory */
+#define CFG_PROMPT	"Integrator-CP # "	/* Monitor Command Prompt */
+#define CFG_CBSIZE	256			/* Console I/O Buffer Size*/
+/* Print Buffer Size */
+#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS	16			/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE		/* Boot Argument Buffer Size*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#define CFG_LOAD_ADDR	0x7fc0	/* default load address */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 	0x08000000	/* 128 MB */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+
+ * Top varies according to amount fitted
+ * Reserve top 4 blocks of flash
+ * - ARM Boot Monitor
+ * - Unused
+ * - SIB block
+ * - U-Boot environment
+ *
+ * Base is always 0x24000000
+
+ */
+#define CFG_FLASH_BASE		0x24000000
+#define CFG_MAX_FLASH_SECT 	64
+#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define PHYS_FLASH_SIZE 	0x01000000	/* 16MB */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Write */
+
+#define CFG_MONITOR_LEN		0x00100000
+#define CFG_ENV_IS_IN_FLASH	(1)
+
+/*
+ * Move up the U-Boot & monitor area if more flash is fitted.
+ * If this U-Boot is to be run on Integrators with varying flash sizes,
+ * drivers/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG
+ * register and dynamically assign CFG_ENV_ADDR & CFG_MONITOR_BASE
+ * - CFG_MONITOR_BASE is set to indicate that the environment is not
+ * embedded in the boot monitor(s) area
+ */
+#if ( PHYS_FLASH_SIZE == 0x04000000 )
+
+#define CFG_ENV_ADDR		0x27F00000
+#define CFG_MONITOR_BASE	0x27F40000
+
+#elif (PHYS_FLASH_SIZE == 0x02000000 )
+
+#define CFG_ENV_ADDR		0x25F00000
+#define CFG_MONITOR_BASE	0x25F40000
+
+#else
+
+#define CFG_ENV_ADDR		0x24F00000
+#define CFG_MONITOR_BASE	0x27F40000
+
+#endif
+
+#define CFG_ENV_SECT_SIZE	0x40000		/* 256KB */
+#define CFG_ENV_SIZE		8192		/* 8KB */
+/*-----------------------------------------------------------------------
+ * CP control registers
+ */
+#define CPCR_BASE		0xCB000000	/* CP Registers*/
+#define OS_FLASHPROG		0x00000004	/* Flash register*/
+#define CPMASK_EXTRABANK	0x8
+#define CPMASK_FLASHSIZE	0x4
+#define CPMASK_FLWREN		0x2
+#define CPMASK_FLVPPEN		0x1
+
+/*
+ * The ARM boot monitor initializes the board.
+ * However, the default U-Boot code also performs the initialization.
+ * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
+ * - see documentation supplied with board for details of how to choose the
+ * image to run at reset/power up
+ * e.g. whether the ARM Boot Monitor runs before U-Boot
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+ */
+
+/*
+ * The ARM boot monitor does not relocate U-Boot.
+ * However, the default U-Boot code performs the relocation check,
+ * and may relocate the code if the memory map is changed.
+ * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
+
+#define SKIP_CONFIG_RELOCATE_UBOOT
+
+ */
+/*-----------------------------------------------------------------------
+ * There are various dependencies on the core module (CM) fitted
+ * Users should refer to their CM user guide
+ * - when porting adjust u-boot/Makefile accordingly
+ * to define the necessary CONFIG_ s for the CM involved
+ * see e.g. cp_926ejs_config
+ */
+
+#include "armcoremodule.h"
+
+/*
+ * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
+ * the core module has a CM_INIT register
+ * then the U-Boot initialisation code will
+ * e.g. ARM Boot Monitor or pre-loader is repeated once
+ * (to re-initialise any existing CM_INIT settings to safe values).
+ *
+ * This is usually not the desired behaviour since the platform
+ * will either reboot into the ARM monitor (or pre-loader)
+ * or continuously cycle thru it without U-Boot running,
+ * depending upon the setting of Integrator/CP switch S2-4.
+ *
+ * However it may be needed if Integrator/CP switch S2-1
+ * is set OFF to boot direct into U-Boot.
+ * In that case comment out the line below.
+#undef	CONFIG_CM_INIT
+ */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h
new file mode 100755
index 0000000..b0a80a3
--- /dev/null
+++ b/include/configs/ixdp425.h
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2003
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * Configuation settings for the IXDP425 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_IXP425           1       /* This is an IXP425 CPU    */
+#define CONFIG_IXDP425          1       /* on an IXDP425 Board      */
+
+/***************************************************************
+ * U-boot generic defines start here.
+ ***************************************************************/
+
+#undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN      (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE         115200
+
+#define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_ELF | CFG_CMD_PCI)
+
+#define CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+/* These are u-boot generic parameters */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY        3
+/*#define CONFIG_ETHADDR          08:00:3e:26:0a:5b*/
+#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_IPADDR           192.168.0.21
+#define CONFIG_SERVERIP         192.168.0.148
+#define CONFIG_BOOTCOMMAND      "bootm 50040000"
+#define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
+#define CONFIG_CMDLINE_TAG
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                            /* undef to save memory         */
+#define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
+#define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS             16              /* max number of command args   */
+#define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START       0x00400000      /* memtest works on     */
+#define CFG_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
+
+#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR           0x00010000      /* default load address */
+
+#define CFG_HZ                  3333333         /* spec says 66.666 MHz, but it appears to be 33 */
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
+#endif
+
+/***************************************************************
+ * Platform/Board specific defines start here.
+ ***************************************************************/
+
+/*
+ * Hardware drivers
+ */
+
+
+/*
+ * select serial console configuration
+ */
+#define CFG_IXP425_CONSOLE	IXP425_UART1   /* we use UART1 for console */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS    1          /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE       0x01000000 /* 16 MB */
+
+#define PHYS_FLASH_1            0x50000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE         0x00800000 /* 8 MB */
+#define PHYS_FLASH_BANK_SIZE    0x00800000 /* 8 MB Banks */
+#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
+
+#define CFG_DRAM_BASE           0x00000000
+#define CFG_DRAM_SIZE           0x01000000
+
+#define CFG_FLASH_BASE          PHYS_FLASH_1
+
+/*
+ * Expansion bus settings
+ */
+#define CFG_EXP_CS0				0xbcd23c42
+
+/*
+ * SDRAM settings
+ */
+#define CFG_SDR_CONFIG		0xd
+#define CFG_SDR_MODE_CONFIG	0x1
+#define CFG_SDRAM_REFRESH_CNT 	0x81a
+
+/*
+ * GPIO settings
+ */
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT      128  	/* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT    (25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT    (25*CFG_HZ) /* Timeout for Flash Write */
+
+/* FIXME */
+#define	CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x20000)        /* Addr of Environment Sector   */
+#define CFG_ENV_SIZE            0x20000  /* Total Size of Environment Sector     */
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h
new file mode 100755
index 0000000..6590f6f
--- /dev/null
+++ b/include/configs/kb9202.h
@@ -0,0 +1,173 @@
+/*
+ * Rick Bronson <rick@efn.org>
+ *
+ * Configuation settings for the AT91RM9200DK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Adatped for KwikByte KB920x board from at91rm9200dk.h: 22APR2005
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91C_MAIN_CLOCK	180000000	/* from 10 MHz crystal */
+#define AT91C_MASTER_CLOCK	60000000	/* peripheral clock (AT91C_MASTER_CLOCK / 3) */
+
+#define AT91_SLOW_CLOCK		32768	/* slow clock */
+
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
+#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
+/* Only define one of the following, based on board type		*/
+/* #define	CONFIG_KB9200		1	 KwikByte KB9202 board	*/
+/* #define	CONFIG_KB9201		1	 KwikByte KB9202 board	*/
+#define	CONFIG_KB9202		1	/* KwikByte KB9202 board	*/
+
+#define	CONFIG_KB920x		1	/* Any KB920x board		*/
+#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+#define USE_920T_MMU		1
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#define	CONFIG_SKIP_LOWLEVEL_INIT
+
+#define	CFG_LONGHELP
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Hardware drivers
+ */
+
+/* define one of these to choose the DBGU, USART0  or USART1 as console */
+#define CONFIG_DBGU
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+
+#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/
+
+#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_ENV_OVERWRITE	1
+
+#define CONFIG_COMMANDS		\
+		       ((CONFIG_CMD_DFL | \
+		        CFG_CMD_I2C | \
+			CFG_CMD_PING | \
+			CFG_CMD_DHCP ) & \
+		      ~(CFG_CMD_BDI | \
+			CFG_CMD_FPGA | \
+			CFG_CMD_MISC))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x2000000  /* 32 megs */
+
+#define CFG_MEMTEST_START		PHYS_SDRAM
+#define CFG_MEMTEST_END			CFG_MEMTEST_START + PHYS_SDRAM_SIZE - (512*1024)
+
+#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_RETRY_COUNT		20
+
+#define CFG_FLASH_BASE			0x10000000
+
+#ifdef CONFIG_KB9202
+#define PHYS_FLASH_SIZE			0x1000000
+#else
+#define PHYS_FLASH_SIZE			0x200000
+#endif
+
+#define CFG_MAX_FLASH_BANKS		1
+#define CFG_MAX_FLASH_SECT		256
+
+#define	CONFIG_HARD_I2C
+
+#define	CFG_ENV_IS_IN_EEPROM
+
+#ifdef CONFIG_KB9202
+#define CFG_ENV_OFFSET			0x3E00
+#define CFG_ENV_SIZE			0x0200
+#else
+#define CFG_ENV_OFFSET			0x1000
+#define CFG_ENV_SIZE			0x1000
+#endif
+#define	CFG_I2C_EEPROM_ADDR		0x50
+#define	CFG_EEPROM_PAGE_WRITE_BITS	6
+#define	CFG_I2C_EEPROM_ADDR_LEN		2
+#define	CFG_I2C_SPEED			50000
+#define	CFG_I2C_SLAVE			0 /* not used */
+#define	CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#define CFG_LOAD_ADDR		0x21000000  /* default load address */
+
+#define CFG_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT		"U-Boot> "	/* Monitor Command Prompt */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+
+#define	CFG_FLASH_CFI_DRIVER
+#define	CFG_FLASH_CFI
+
+#ifndef __ASSEMBLY__
+/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext {
+	/* helper variable for board environment handling
+	 *
+	 * env_crc_valid == 0    =>   uninitialised
+	 * env_crc_valid  > 0    =>   environment crc in flash is valid
+	 * env_crc_valid  < 0    =>   environment crc in flash is invalid
+	 */
+	int env_crc_valid;
+};
+#endif
+
+#define CFG_HZ 1000
+#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2	/* AT91C_TC0_CMR is implicitly set to */
+					/* AT91C_TC_TIMER_DIV1_CLOCK */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff --git a/include/configs/lart.h b/include/configs/lart.h
new file mode 100755
index 0000000..a00640b
--- /dev/null
+++ b/include/configs/lart.h
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the LART board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SA1100		1	/* This is an SA1100 CPU	*/
+#define CONFIG_LART		1	/* on an LART Board      */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
+#define CS8900_BASE		0x20008300
+#define CS8900_BUS16		1
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL3          1	/* we use SERIAL 3 on LART */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600"
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK          255.255.0.0
+#define CONFIG_IPADDR		172.22.2.131
+#define CONFIG_SERVERIP		172.22.2.126
+#define CONFIG_BOOTFILE		"elinos-lart"
+#define CONFIG_BOOTCOMMAND	"tftp; bootm"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"LART # "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0xc8000000	/* default load address	*/
+
+#define	CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x0b		/* set core clock to 220 MHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB */
+#define PHYS_SDRAM_2		0xc1000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x00800000 /* 8 MB */
+#define PHYS_SDRAM_3            0xc8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE       0x00800000 /* 8 MB */
+#define PHYS_SDRAM_4            0xc9000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE       0x00800000 /* 8 MB */
+
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE		0x00400000 /* 4 MB */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	(31+8)	/* max number of sectors on one chip	*/
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x1C000)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/logodl.h b/include/configs/logodl.h
new file mode 100755
index 0000000..715ed74
--- /dev/null
+++ b/include/configs/logodl.h
@@ -0,0 +1,279 @@
+/*
+ * (C) Copyright 2003
+ * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
+ *
+ * Configuration for the Logotronic DL board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * include/configs/logodl.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA250 		1	/* This is an PXA250 CPU            */
+#define CONFIG_GEALOG		1	/* on a Logotronic GEALOG SG board  */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff      */
+					/* for timer/console/ethernet       */
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART		1	/* we use FFUART                    */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		19200
+#undef CONFIG_MISC_INIT_R		/* FIXME: misc_init_r() missing     */
+
+#define CONFIG_COMMANDS (CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO)
+/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)   */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+/* #define CONFIG_BOOTARGS	"root=/dev/nfs ip=bootp console=ttyS0,19200" */
+#define CONFIG_BOOTARGS		"console=ttyS0,19200"
+#define CONFIG_ETHADDR		FF:FF:FF:FF:FF:FF
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.1.56
+#define CONFIG_SERVERIP		192.168.1.2
+#define CONFIG_BOOTCOMMAND	"bootm 0x40000"
+#define CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_CMDLINE_TAG	1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+/*
+ * Size of malloc() pool; this lives below the uppermost 128 KiB which are
+ * used for the RAM copy of the uboot code
+ *
+ */
+#define CFG_MALLOC_LEN		(256*1024)
+
+#define CFG_LONGHELP				/* undef to save memory         */
+#define CFG_PROMPT		"uboot> "	/* Monitor Command Prompt       */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size      */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args   */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START	0x08000000      /* memtest works on             */
+#define CFG_MEMTEST_END         0x0800ffff	/* 64 KiB                       */
+
+#undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR           0x08000000      /* load kernel to this address   */
+
+#define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
+						/* RS: the oscillator is actually 3680130?? */
+
+#define CFG_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
+						/* 0101000001 */
+						/*      ^^^^^ Memory Speed 99.53 MHz         */
+						/*    ^^      Run Mode Speed = 2x Mem Speed  */
+						/* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
+
+#define CFG_MONITOR_LEN		0x20000		/* 128 KiB */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * SMSC91C111 Network Card
+ */
+#if 0
+#define CONFIG_DRIVER_SMC91111		1
+#define CONFIG_SMC91111_BASE		0x10000000 /* chip select 4         */
+#undef  CONFIG_SMC_USE_32_BIT		           /* 16 bit bus access     */
+#undef  CONFIG_SMC_91111_EXT_PHY		   /* we use internal phy   */
+#undef  CONFIG_SHOW_ACTIVITY
+#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */
+#endif
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
+#ifdef  CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of RAM    */
+#define PHYS_SDRAM_1		0x08000000	/* SRAM Bank #1             */
+#define PHYS_SDRAM_1_SIZE	(4*1024*1024)	/* 4 MB                     */
+
+#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1            */
+#define PHYS_FLASH_2		0x01000000	/* Flash Bank #2            */
+#define PHYS_FLASH_SIZE		(32*1024*1024)	/* 32 MB                    */
+
+#define CFG_DRAM_BASE		PHYS_SDRAM_1	/* RAM starts here          */
+#define CFG_DRAM_SIZE		PHYS_SDRAM_1_SIZE
+
+#define CFG_FLASH_BASE          PHYS_FLASH_1
+
+
+/*
+ * GPIO settings
+ *
+ * GP?? == FOOBAR    is 0/1
+ */
+
+#define _BIT0       0x00000001
+#define _BIT1       0x00000002
+#define _BIT2       0x00000004
+#define _BIT3       0x00000008
+
+#define _BIT4       0x00000010
+#define _BIT5       0x00000020
+#define _BIT6       0x00000040
+#define _BIT7       0x00000080
+
+#define _BIT8       0x00000100
+#define _BIT9       0x00000200
+#define _BIT10      0x00000400
+#define _BIT11      0x00000800
+
+#define _BIT12      0x00001000
+#define _BIT13      0x00002000
+#define _BIT14      0x00004000
+#define _BIT15      0x00008000
+
+#define _BIT16      0x00010000
+#define _BIT17      0x00020000
+#define _BIT18      0x00040000
+#define _BIT19      0x00080000
+
+#define _BIT20      0x00100000
+#define _BIT21      0x00200000
+#define _BIT22      0x00400000
+#define _BIT23      0x00800000
+
+#define _BIT24      0x01000000
+#define _BIT25      0x02000000
+#define _BIT26      0x04000000
+#define _BIT27      0x08000000
+
+#define _BIT28      0x10000000
+#define _BIT29      0x20000000
+#define _BIT30      0x40000000
+#define _BIT31      0x80000000
+
+
+#define CFG_LED_A_BIT           (_BIT18)
+#define CFG_LED_A_SR            GPSR0
+#define CFG_LED_A_CR            GPCR0
+
+#define CFG_LED_B_BIT           (_BIT16)
+#define CFG_LED_B_SR            GPSR1
+#define CFG_LED_B_CR            GPCR1
+
+
+/* LED A: off, LED B: off */
+#define CFG_GPSR0_VAL       (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18)
+#define CFG_GPSR1_VAL       (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25  +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
+#define CFG_GPSR2_VAL       (_BIT14+_BIT15+_BIT16)
+
+#define CFG_GPCR0_VAL       0x00000000
+#define CFG_GPCR1_VAL       0x00000000
+#define CFG_GPCR2_VAL       0x00000000
+
+#define CFG_GPDR0_VAL       (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18)
+#define CFG_GPDR1_VAL       (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25  +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
+#define CFG_GPDR2_VAL       (_BIT14+_BIT15+_BIT16)
+
+#define CFG_GAFR0_L_VAL     (_BIT22+_BIT24+_BIT31)
+#define CFG_GAFR0_U_VAL     (_BIT15+_BIT17+_BIT19+\
+			     _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31)
+#define CFG_GAFR1_L_VAL     (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\
+			     _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31)
+#define CFG_GAFR1_U_VAL     (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
+#define CFG_GAFR2_L_VAL     (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\
+			     _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
+#define CFG_GAFR2_U_VAL     (_BIT1)
+
+#define CFG_PSSR_VAL        (0x20)
+
+/*
+ * Memory settings
+ */
+#define CFG_MSC0_VAL	0x123c2980
+#define CFG_MSC1_VAL	0x123c2661
+#define CFG_MSC2_VAL	0x7ff87ff8
+
+
+/* no sdram/pcmcia here */
+#define CFG_MDCNFG_VAL		0x00000000
+#define CFG_MDREFR_VAL		0x00000000
+#define CFG_MDREFR_VAL_100	0x00000000
+#define CFG_MDMRS_VAL		0x00000000
+
+/* only SRAM */
+#define SXCNFG_SETTINGS	0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+
+#define CFG_MECR_VAL        0x00000000
+#define CFG_MCMEM0_VAL      0x00010504
+#define CFG_MCMEM1_VAL      0x00010504
+#define CFG_MCATT0_VAL      0x00010504
+#define CFG_MCATT1_VAL      0x00010504
+#define CFG_MCIO0_VAL       0x00004715
+#define CFG_MCIO1_VAL       0x00004715
+
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT      128  /* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ) /* Timeout for Flash Write */
+
+/* FIXME */
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR            (PHYS_FLASH_1 + 0x1C000)        /* Addr of Environment Sector   */
+#define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/lpd7a400-10.h b/include/configs/lpd7a400-10.h
new file mode 100755
index 0000000..3722fd2
--- /dev/null
+++ b/include/configs/lpd7a400-10.h
@@ -0,0 +1,80 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Logic LH7A400-10 card engine
+ */
+
+#ifndef __LPD7A400_10_H
+#define __LPD7A400_10_H
+
+
+#define CONFIG_ARM920T		1	/* arm920t core */
+#define CONFIG_LH7A40X		1	/* Sharp LH7A40x SoC family */
+#define CONFIG_LH7A400		1   /* Sharp LH7A400 S0C */
+
+/* The system clock PLL input frequency */
+#define CONFIG_SYS_CLK_FREQ		14745600   /* System Clock PLL Input (Hz) */
+
+/* ticks per second */
+#define CFG_HZ	(508469)
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
+
+#define CFG_FLASH_BASE		0x00000000 /* Flash Bank #1 */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	(64)	/* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+
+/*----------------------------------------------------------------------
+ * Using SMC91C111 LAN chip
+ *
+ * Default IO base of chip is 0x300, Card Engine has this address lines
+ * (LAN chip) tied to Vcc, so we just care about the chip select
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE	(0x70000000)
+#undef CONFIG_SMC_USE_32_BIT
+#define CONFIG_SMC_USE_IOFUNCS
+
+#endif  /* __LPD7A400_10_H */
diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h
new file mode 100755
index 0000000..d7d0460
--- /dev/null
+++ b/include/configs/lpd7a400.h
@@ -0,0 +1,106 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __LPD7A400_H_
+#define __LPD7A400_H_
+
+#define CONFIG_LPD7A400		/* Logic LH7A400 SDK */
+
+#undef CONFIG_USE_IRQ
+
+/*
+ * This board uses the logic LH7A400-10 card engine
+ */
+#include <configs/lpd7a400-10.h>
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONSOLE_UART2	/* UART2 LH7A40x for console */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_IPADDR		192.168.1.100
+#define CONFIG_NETMASK		255.255.1.0
+#define CONFIG_SERVERIP		192.168.1.1
+
+#define	CONFIG_TIMESTAMP	1	/* Print timestamp info for images */
+
+#ifndef USE_920T_MMU
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE))
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE)
+#endif
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"LPD7A400> "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0xc0300000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xc0500000	/* 2 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0xc0f00000	/* default load address	*/
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* size and location of u-boot in flash */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256<<10)
+
+#define	CFG_ENV_IS_IN_FLASH	1
+
+/* Address and size of Primary Environment Sector	*/
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0xFC0000)
+#define CFG_ENV_SIZE		0x40000
+
+#endif  /* __LPD7A400_H_ */
diff --git a/include/configs/lpd7a404-10.h b/include/configs/lpd7a404-10.h
new file mode 100755
index 0000000..a8af950
--- /dev/null
+++ b/include/configs/lpd7a404-10.h
@@ -0,0 +1,80 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Logic LH7A400-10 card engine
+ */
+
+#ifndef __LPD7A404_10_H
+#define __LPD7A404_10_H
+
+
+#define CONFIG_ARM920T		1	/* arm920t core */
+#define CONFIG_LH7A40X		1	/* Sharp LH7A40x SoC family */
+#define CONFIG_LH7A404		1   /* Sharp LH7A404 SoC */
+
+/* The system clock PLL input frequency */
+#define CONFIG_SYS_CLK_FREQ		14745600   /* System Clock PLL Input (Hz) */
+
+/* ticks per second */
+#define CFG_HZ	(508469)
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
+
+#define CFG_FLASH_BASE		0x00000000 /* Flash Bank #1 */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	(64)	/* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+
+/*----------------------------------------------------------------------
+ * Using SMC91C111 LAN chip
+ *
+ * Default IO base of chip is 0x300, Card Engine has this address lines
+ * (LAN chip) tied to Vcc, so we just care about the chip select
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE	(0x70000000)
+#undef CONFIG_SMC_USE_32_BIT
+#define CONFIG_SMC_USE_IOFUNCS
+
+#endif  /* __LPD7A404_10_H */
diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h
new file mode 100755
index 0000000..4002e68
--- /dev/null
+++ b/include/configs/lpd7a404.h
@@ -0,0 +1,106 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __LPD7A404_H_
+#define __LPD7A404_H_
+
+#define CONFIG_LPD7A404		/* Logic LH7A400 SDK */
+
+#undef CONFIG_USE_IRQ
+
+/*
+ * This board uses the logic LH7A404-10 card engine
+ */
+#include <configs/lpd7a404-10.h>
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONSOLE_UART2	/* UART2 LH7A40x for console */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_IPADDR		192.168.1.100
+#define CONFIG_NETMASK		255.255.1.0
+#define CONFIG_SERVERIP		192.168.1.1
+
+#define	CONFIG_TIMESTAMP	1	/* Print timestamp info for images */
+
+#ifndef USE_920T_MMU
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE))
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE)
+#endif
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"LPD7A404> "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0xc0300000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xc0500000	/* 2 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0xc0f00000	/* default load address	*/
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* size and location of u-boot in flash */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256<<10)
+
+#define	CFG_ENV_IS_IN_FLASH	1
+
+/* Address and size of Primary Environment Sector	*/
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0xFC0000)
+#define CFG_ENV_SIZE		0x40000
+
+#endif  /* __LPD7A404_H_ */
diff --git a/include/configs/luan.h b/include/configs/luan.h
new file mode 100755
index 0000000..0335a00
--- /dev/null
+++ b/include/configs/luan.h
@@ -0,0 +1,306 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ * John Otken, jotken@softadvances.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * luan.h - configuration for LUAN board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_LUAN		1	/* Board is Luan		*/
+#define CONFIG_440SP		1	/* Specific PPC440SP support    */
+#define CONFIG_4xx		1	/* PPC4xx family	        */
+#define CONFIG_440		1
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc  */
+#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
+#define CFG_SDRAM_BASE	        0x00000000	/* MUST be zero */
+
+#define CFG_LARGE_FLASH		0xffc00000	/* 4MB flash address CS0 */
+#define CFG_SMALL_FLASH		0xff900000	/* 1MB flash address CS2 */
+#define CFG_SRAM_BASE		0xff800000	/* 1MB SRAM  address CS2 */
+#define CFG_EPLD_BASE		0xff000000	/* EPLD and FRAM     CS1 */
+
+#define CFG_ISRAM_BASE	        0xf8000000	/* internal 8k SRAM (L2 cache) */
+
+#define CFG_PERIPHERAL_BASE     0xf0000000	/* internal peripherals */
+
+#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory */
+#define CFG_PCI_BASE		0xd0000000	/* internal PCI regs */
+#define CFG_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+#if CFG_LARGE_FLASH == 0xffc00000
+#define CFG_FLASH_BASE		CFG_LARGE_FLASH
+#else
+#define CFG_FLASH_BASE		CFG_SMALL_FLASH
+#endif
+
+#undef CFG_DRAM_TEST
+#if CFG_SRAM_BASE
+#define CFG_KBYTES_SDRAM	1024*2
+#else
+#define CFG_KBYTES_SDRAM	1024
+#endif
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE
+#define CFG_INIT_RAM_END	(8 << 10)
+#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK	11059200 /* external 11.059MHz clk */
+#define CONFIG_BAUDRATE		115200
+#undef  CONFIG_SERIAL_MULTI
+#undef  CONFIG_UART1_CONSOLE		/* define if you want console on UART1 */
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CFG_FLASH_ADDR0         0x555
+#define CFG_FLASH_ADDR1         0x2aa
+#define CFG_FLASH_WORD_SIZE     unsigned char
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000 /* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef  CONFIG_SPD_EEPROM		/* SPD EEPROM init doesn't support DDR2 */
+#define SPD_EEPROM_ADDRESS {0x52,0x53}	/* I2C SPD addresses */
+#define IIC0_DIMM0_ADDR         0x52
+#define IIC0_DIMM1_ADDR         0x53
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=luan\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/luan/uImage\0"				\
+	"kernel_addr=fc000000\0"					\
+	"ramdisk_addr=fc100000\0"					\
+	"load=tftp 100000 /tftpboot/luan/u-boot.bin\0"			\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		1
+#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+#define CONFIG_NET_MULTI		/* needed for NetConsole	*/
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#else
+#define CONFIG_HW_WATCHDOG			/* watchdog */
+#endif
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL		|	\
+				CFG_CMD_ASKENV		|	\
+			        CFG_CMD_CACHE		|	\
+				CFG_CMD_DHCP		|	\
+				CFG_CMD_DIAG		|	\
+				CFG_CMD_ELF		|	\
+				CFG_CMD_I2C		|	\
+				CFG_CMD_IRQ		|	\
+				CFG_CMD_MII		|	\
+				CFG_CMD_NET		|	\
+				CFG_CMD_NFS		|	\
+				CFG_CMD_PCI		|	\
+				CFG_CMD_PING		|	\
+				CFG_CMD_REGINFO		|	\
+				CFG_CMD_SETGETDCR	|	\
+				CFG_CMD_SDRAM		|	\
+				0)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000 /* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#undef  CONFIG_LYNXKDI			/* support kdi files            */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_PCI)
+
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
+#define CFG_PCI_TARGET_INIT
+#undef  CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0x4403	/* whatever */
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
new file mode 100755
index 0000000..ad1035b
--- /dev/null
+++ b/include/configs/lubbock.h
@@ -0,0 +1,240 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the LUBBOCK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA250		1	/* This is an PXA250 CPU    */
+#define CONFIG_LUBBOCK		1	/* on an LUBBOCK Board	    */
+#define CONFIG_LCD		1
+#ifdef CONFIG_LCD
+#define CONFIG_SHARP_LM8V31
+#endif
+#define CONFIG_MMC		1
+#define BOARD_LATE_INIT		1
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE 0x0C000000
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART	       1       /* we use FFUART on LUBBOCK */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.0.0
+#define CONFIG_IPADDR		192.168.0.21
+#define CONFIG_SERVERIP		192.168.0.250
+#define CONFIG_BOOTCOMMAND	"bootm 80000"
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_TIMESTAMP
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER		1
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#define CFG_LONGHELP				/* undef to save memory		*/
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
+#else
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_DEVICE_NULLDEV	1
+
+#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR	(CFG_DRAM_BASE + 0x8000) /* default load address */
+
+#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_MMC_BASE		0xF0000000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
+#define PHYS_FLASH_SIZE		0x02000000 /* 32 MB */
+#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
+
+#define CFG_DRAM_BASE		0xa0000000
+#define CFG_DRAM_SIZE		0x04000000
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+#define FPGA_REGS_BASE_PHYSICAL 0x08000000
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPSR0_VAL		0x00008000
+#define CFG_GPSR1_VAL		0x00FC0382
+#define CFG_GPSR2_VAL		0x0001FFFF
+#define CFG_GPCR0_VAL		0x00000000
+#define CFG_GPCR1_VAL		0x00000000
+#define CFG_GPCR2_VAL		0x00000000
+#define CFG_GPDR0_VAL		0x0060A800
+#define CFG_GPDR1_VAL		0x00FF0382
+#define CFG_GPDR2_VAL		0x0001C000
+#define CFG_GAFR0_L_VAL		0x98400000
+#define CFG_GAFR0_U_VAL		0x00002950
+#define CFG_GAFR1_L_VAL		0x000A9558
+#define CFG_GAFR1_U_VAL		0x0005AAAA
+#define CFG_GAFR2_L_VAL		0xA0000000
+#define CFG_GAFR2_U_VAL		0x00000002
+
+#define CFG_PSSR_VAL		0x20
+
+/*
+ * Memory settings
+ */
+#define CFG_MSC0_VAL		0x23F223F2
+#define CFG_MSC1_VAL		0x3FF1A441
+#define CFG_MSC2_VAL		0x7FF97FF1
+#define CFG_MDCNFG_VAL		0x00001AC9
+#define CFG_MDREFR_VAL		0x00018018
+#define CFG_MDMRS_VAL		0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL		0x00000000
+#define CFG_MCMEM0_VAL		0x00010504
+#define CFG_MCMEM1_VAL		0x00010504
+#define CFG_MCATT0_VAL		0x00010504
+#define CFG_MCATT1_VAL		0x00010504
+#define CFG_MCIO0_VAL		0x00004715
+#define CFG_MCIO1_VAL		0x00004715
+
+#define _LED			0x08000010
+#define LED_BLANK		0x08000040
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+
+/* NOTE: many default partitioning schemes assume the kernel starts at the
+ * second sector, not an environment.  You have been warned!
+ */
+#define	CFG_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_SIZE		(PHYS_FLASH_SECT_SIZE / 16)
+
+
+/*
+ * FPGA Offsets
+ */
+#define WHOAMI_OFFSET		0x00
+#define HEXLED_OFFSET		0x10
+#define BLANKLED_OFFSET		0x40
+#define DISCRETELED_OFFSET	0x40
+#define CNFG_SWITCHES_OFFSET	0x50
+#define USER_SWITCHES_OFFSET	0x60
+#define MISC_WR_OFFSET		0x80
+#define MISC_RD_OFFSET		0x90
+#define INT_MASK_OFFSET		0xC0
+#define INT_CLEAR_OFFSET	0xD0
+#define GP_OFFSET		0x100
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h
new file mode 100755
index 0000000..9b4c004
--- /dev/null
+++ b/include/configs/lwmon.h
@@ -0,0 +1,612 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* External logbuffer support */
+#define CONFIG_LOGBUFFER
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823E CPU	*/
+#define CONFIG_LWMON		1	/* ...on a LWMON board		*/
+
+/* Default Ethernet MAC address */
+#define CONFIG_ETHADDR          00:11:B0:00:00:00
+
+/* The default Ethernet MAC address can be overwritten just once */
+#ifdef CONFIG_ETHADDR
+#define CONFIG_OVERWRITE_ETHADDR_ONCE   1
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+#define CONFIG_BOARD_POSTCLK_INIT 1	/* Call board_postclk_init	*/
+
+#define CONFIG_LCD		1	/* use LCD controller ...	*/
+#define CONFIG_HLD1045		1	/* ... with a HLD1045 display	*/
+
+#define CONFIG_LCD_LOGO		1	/* print our logo on the LCD	*/
+#define CONFIG_LCD_INFO		1	/* ... and some board info	*/
+#define	CONFIG_SPLASH_SCREEN		/* ... with splashscreen support*/
+
+#define CONFIG_SERIAL_MULTI	1
+#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#define CONFIG_8xx_CONS_SCC2	1	/* Console is on SCC2		*/
+
+#define CONFIG_BAUDRATE		115200	/* with watchdog >= 38400 needed */
+
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+/* pre-boot commands */
+#define	CONFIG_PREBOOT		"setenv bootdelay 15"
+
+#undef	CONFIG_BOOTARGS
+
+/* POST support */
+#define CONFIG_POST		(CFG_POST_CACHE	   | \
+				 CFG_POST_WATCHDOG | \
+				 CFG_POST_RTC	   | \
+				 CFG_POST_MEMORY   | \
+				 CFG_POST_CPU	   | \
+				 CFG_POST_UART	   | \
+				 CFG_POST_ETHER    | \
+				 CFG_POST_I2C	   | \
+				 CFG_POST_SPI	   | \
+				 CFG_POST_USB	   | \
+				 CFG_POST_SPR	   | \
+				 CFG_POST_SYSMON)
+
+/*
+ * Keyboard commands:
+ * # = 0x28 = ENTER :		enable bootmessages on LCD
+ * 2 = 0x3A+0x3C = F1 + F3 :	enable update mode
+ * 3 = 0x3C+0x3F = F3 + F6 :	enable test mode
+ */
+
+#define CONFIG_BOOTCOMMAND "autoscr 40040000;saveenv"
+
+/*	"gatewayip=10.8.211.250\0"			                \ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40280000\0"					\
+	"netmask=255.255.192.0\0"				        \
+	"serverip=10.8.2.101\0"				                \
+	"ipaddr=10.8.57.0\0"				                \
+	"magic_keys=#23\0"						\
+	"key_magic#=28\0"						\
+	"key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
+	"key_magic2=3A+3C\0"						\
+	"key_cmd2=echo *** Entering Update Mode ***;"			\
+		"if fatload ide 0:3 10000 update.scr;"			\
+			"then autoscr 10000;"				\
+			"else echo *** UPDATE FAILED ***;"		\
+		"fi\0"							\
+	"key_magic3=3C+3F\0"						\
+	"key_cmd3=echo *** Entering Test Mode ***;"			\
+		"setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
+	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0"	\
+	"addip=setenv bootargs $bootargs "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
+		"panic=1\0"						\
+	"add_wdt=setenv bootargs $bootargs $wdt_args\0"			\
+	"add_misc=setenv bootargs $bootargs runmode\0"			\
+	"flash_nfs=run nfsargs addip add_wdt addfb add_misc;"		\
+		"bootm $kernel_addr\0"					\
+	"flash_self=run ramargs addip add_wdt addfb add_misc;"		\
+		"bootm $kernel_addr $ramdisk_addr\0"			\
+	"net_nfs=tftp 100000 /tftpboot/uImage.lwmon;"			\
+		"run nfsargs addip add_wdt addfb;bootm\0"		\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"load=tftp 100000 /tftpboot/u-boot.bin\0"			\
+	"update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
+	"wdt_args=wdt_8xx=off\0"					\
+	"verify=no"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
+#define	CFG_WATCHDOG_FREQ       (CFG_HZ / 20)
+
+#undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
+
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
+
+#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SOFT_I2C */
+
+
+#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_BMP	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_POST_DIAG | \
+				CFG_CMD_SNTP	)
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x00100000	/* default load address */
+
+#define CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * When the watchdog is enabled, output must be fast enough in Linux.
+ */
+#ifdef CONFIG_WATCHDOG
+#define CFG_BAUDRATE_TABLE	{		38400, 57600, 115200 }
+#else
+#define CFG_BAUDRATE_TABLE	{  9600, 19200, 38400, 57600, 115200 }
+#endif
+
+/*----------------------------------------------------------------------*/
+#define CONFIG_MODEM_SUPPORT	1	/* enable modem initialization stuff */
+#undef CONFIG_MODEM_SUPPORT_DEBUG
+
+#define	CONFIG_MODEM_KEY_MAGIC	"3C+3D"	/* press F3 + F4 keys to enable modem */
+#define	CONFIG_POST_KEY_MAGIC	"3C+3E"	/* press F3 + F5 keys to force POST */
+#if 0
+#define	CONFIG_AUTOBOOT_KEYED		/* Enable "password" protection	*/
+#define CONFIG_AUTOBOOT_PROMPT	"\nEnter password - autoboot in %d sec...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR	"  "	/* "password"	*/
+#endif
+/*----------------------------------------------------------------------*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	68  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	180000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	600	/* Timeout for Flash Write (in ms)	*/
+#define CFG_FLASH_USE_BUFFER_WRITE
+#define CFG_FLASH_BUFFER_WRITE_TOUT	2048	/* Timeout for Flash Buffer Write (in ms)	*/
+/* Buffer size.
+   We have two flash devices connected in parallel.
+   Each device incorporates a Write Buffer of 32 bytes.
+ */
+#define CFG_FLASH_BUFFER_SIZE	(2*32)
+
+/* Put environment in flash which is much faster to boot than using the EEPROM	*/
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR	    0x40040000	/* Address    of Environment Sector	*/
+#define CFG_ENV_SIZE		0x2000	/* Total Size of Environment		*/
+#define CFG_ENV_SECT_SIZE	0x40000 /* we have BIG sectors only :-(		*/
+
+/*-----------------------------------------------------------------------
+ * I2C/EEPROM Configuration
+ */
+
+#define CFG_I2C_AUDIO_ADDR	0x28	/* Audio volume control			*/
+#define CFG_I2C_SYSMON_ADDR	0x2E	/* LM87 System Monitor			*/
+#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
+#define CFG_I2C_POWER_A_ADDR	0x52	/* PCMCIA/USB power switch, channel A	*/
+#define CFG_I2C_POWER_B_ADDR	0x53	/* PCMCIA/USB power switch, channel B	*/
+#define CFG_I2C_KEYBD_ADDR	0x56	/* PIC LWE keyboard			*/
+#define CFG_I2C_PICIO_ADDR	0x57	/* PIC IO Expander			*/
+
+#undef	CONFIG_USE_FRAM			/* Use FRAM instead of EEPROM	*/
+
+#ifdef CONFIG_USE_FRAM	/* use FRAM */
+#define CFG_I2C_EEPROM_ADDR	0x55	/* FRAM FM24CL64		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	2
+#else			/* use EEPROM */
+#define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM AT24C164		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	1
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
+#endif	/* CONFIG_USE_FRAM */
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+
+/* List of I2C addresses to be verified by POST */
+#ifdef CONFIG_USE_FRAM
+#define I2C_ADDR_LIST	{  /*	CFG_I2C_AUDIO_ADDR, */	\
+				CFG_I2C_SYSMON_ADDR,	\
+				CFG_I2C_RTC_ADDR,	\
+				CFG_I2C_POWER_A_ADDR,	\
+				CFG_I2C_POWER_B_ADDR,	\
+				CFG_I2C_KEYBD_ADDR,	\
+				CFG_I2C_PICIO_ADDR,	\
+				CFG_I2C_EEPROM_ADDR,	\
+			}
+#else	/* Use EEPROM - which show up on 8 consequtive addresses */
+#define I2C_ADDR_LIST	{  /*	CFG_I2C_AUDIO_ADDR, */	\
+				CFG_I2C_SYSMON_ADDR,	\
+				CFG_I2C_RTC_ADDR,	\
+				CFG_I2C_POWER_A_ADDR,	\
+				CFG_I2C_POWER_B_ADDR,	\
+				CFG_I2C_KEYBD_ADDR,	\
+				CFG_I2C_PICIO_ADDR,	\
+				CFG_I2C_EEPROM_ADDR+0,	\
+				CFG_I2C_EEPROM_ADDR+1,	\
+				CFG_I2C_EEPROM_ADDR+2,	\
+				CFG_I2C_EEPROM_ADDR+3,	\
+				CFG_I2C_EEPROM_ADDR+4,	\
+				CFG_I2C_EEPROM_ADDR+5,	\
+				CFG_I2C_EEPROM_ADDR+6,	\
+				CFG_I2C_EEPROM_ADDR+7,	\
+			}
+#endif	/* CONFIG_USE_FRAM */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if 0 && defined(CONFIG_WATCHDOG)	/* LWMON uses external MAX706TESA WD */
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+/* EARB, DBGC and DBPC are initialised by the HCW */
+/* => 0x000000C0 */
+#define CFG_SIUMCR	(SIUMCR_GB5E)
+/*#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* 0x00405000 */
+#define CFG_PLPRCR_MF	4	/* (4+1) * 13.2 = 66 MHz Clock */
+#define CFG_PLPRCR							\
+		(	(CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) |		\
+			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
+			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
+			PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/	\
+		)
+
+#define CONFIG_8xx_GCLK_FREQ	((CFG_PLPRCR_MF+1)*13200000)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* 0x01800000 */
+#define CFG_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
+			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
+			 SCCR_EBDF00 |	 SCCR_DFSYNC00 |	\
+			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
+			 SCCR_DFNH000	|   SCCR_DFLCD100 |	\
+			 SCCR_DFALCD01)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/* 0x00C3 => 0x0003 */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register		19-4
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR 0x0000
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMDS 0
+
+/*-----------------------------------------------------------------------
+ *
+ * Interrupt Levels
+ *-----------------------------------------------------------------------
+ */
+#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0x50000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0x54000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0x58000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0x5C000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+#define CONFIG_SUPPORT_VFAT		/* enable VFAT support */
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x41000000	/* FLASH bank #1	*/
+
+/* used to re-map FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0xFF000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFF000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0	*/
+#define CFG_OR_TIMING_FLASH	(OR_SCY_8_CLK)
+
+#define CFG_OR0_REMAP	( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+				CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
+				CFG_OR_TIMING_FLASH)
+/* 16 bit, bank valid */
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
+
+/*
+ * BR3/OR3: SDRAM
+ *
+ * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF0000000	/* map 256 MB (>SDRAM_MAX_SIZE!) */
+#define SDRAM_TIMING		OR_SCY_0_CLK	/* SDRAM-Timing */
+
+#define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB SDRAM */
+
+#define CFG_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR5/OR5: Touch Panel
+ *
+ * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
+ */
+#define TOUCHPNL_BASE		0x20000000
+#define TOUCHPNL_OR_AM		0xFFFF8000
+#define TOUCHPNL_TIMING		OR_SCY_0_CLK
+
+#define CFG_OR5_PRELIM	(TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+			 TOUCHPNL_TIMING )
+#define CFG_BR5_PRELIM	((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
+
+#define	CFG_MEMORY_75
+#undef	CFG_MEMORY_7E
+#undef	CFG_MEMORY_8E
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MPTPR	0x200
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+#define CFG_MAMR_8COL	0x80802114
+#define CFG_MAMR_9COL	0x80904114
+
+/*
+ * MAR setting for SDRAM
+ */
+#define CFG_MAR		0x00000088
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ml300.h b/include/configs/ml300.h
new file mode 100755
index 0000000..6762cd6
--- /dev/null
+++ b/include/configs/ml300.h
@@ -0,0 +1,171 @@
+/*
+ * ML300.h: ML300 specific config options
+ *
+ * http://www.xilinx.com/ml300
+ *
+ * Derived from : ML2.h
+ *
+ *     Author: Xilinx, Inc.
+ *
+ *
+ *     This program is free software; you can redistribute it and/or modify it
+ *     under the terms of the GNU General Public License as published by the
+ *     Free Software Foundation; either version 2 of the License, or (at your
+ *     option) any later version.
+ *
+ *
+ *     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+ *     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+ *     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
+ *     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+ *     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR
+ *     OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+ *     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+ *     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
+ *     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
+ *     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ *     FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *     Xilinx products are not intended for use in life support appliances,
+ *     devices, or systems. Use in such applications is expressly prohibited.
+ *
+ *
+ *     (c) Copyright 2002 Xilinx Inc.
+ *     All rights reserved.
+ *
+ *
+ *     You should have received a copy of the GNU General Public License along
+ *     with this program; if not, write to the Free Software Foundation, Inc.,
+ *     675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* #define DEBUG */
+/* #define ET_DEBUG 1 */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_XILINX_ML300	1	/* ...on a Xilinx ML300 board	*/
+
+#define CONFIG_SYSTEMACE	1
+#define CONFIG_DOS_PARTITION	1
+#define CFG_SYSTEMACE_BASE	XPAR_OPB_SYSACE_0_BASEADDR
+#define CFG_SYSTEMACE_WIDTH	XPAR_XSYSACE_MEM_WIDTH
+
+#define CFG_ENV_IS_IN_EEPROM	1	/* environment is in EEPROM */
+
+/* following are used only if env is in EEPROM */
+#ifdef	CFG_ENV_IS_IN_EEPROM
+#define CFG_I2C_EEPROM_ADDR	XPAR_PERSISTENT_0_IIC_0_EEPROMADDR
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_ENV_OFFSET		XPAR_PERSISTENT_0_IIC_0_BASEADDR
+#define CONFIG_MISC_INIT_R	1	/* used to call out convert_env() */
+#define CONFIG_ENV_OVERWRITE	1	/* allow users to update ethaddr and serial# */
+#endif
+
+#include "../board/xilinx/ml300/xparameters.h"
+
+#define CFG_NO_FLASH		1	/* no flash */
+#define CFG_ENV_SIZE		XPAR_PERSISTENT_0_IIC_0_HIGHADDR - XPAR_PERSISTENT_0_IIC_0_BASEADDR + 1
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command	*/
+
+#define CONFIG_BOOTARGS		"console=ttyS0,9600 ip=off " \
+				"root=/dev/xsysace/disc0/part3 rw"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define REMOVE_COMMANDS	       (CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_FAT | \
+				CFG_CMD_IMLS )
+#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL | CFG_CMD_NET) \
+				& ~REMOVE_COMMANDS)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/* #define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ */
+/* 300000000 */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory		*/
+#define CFG_PROMPT	"=> "	/* Monitor Command Prompt	*/
+
+#define CFG_CBSIZE	256	/* Console I/O Buffer Size	*/
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS	16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_DUART_CHAN		0
+#define CFG_NS16550_REG_SIZE -4
+#define CFG_NS16550 1
+#define CFG_INIT_CHAN1	 1
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CFG_LOAD_ADDR		0x400000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000	/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MONITOR_BASE	0x04000000
+#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+#define CFG_INIT_RAM_ADDR	0x800000  /* inside of SDRAM */
+#define CFG_INIT_RAM_END	0x2000	  /* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	128	  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02	/* Software reboot			*/
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h
new file mode 100755
index 0000000..2028767
--- /dev/null
+++ b/include/configs/modnet50.h
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2004
+ * IMMS, gGmbH <www.imms.de>
+ * Thomas Elste <info@elste.org>
+ *
+ * Configuation settings for ModNET50 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7		1	/* This is a ARM7 CPU	*/
+#define CONFIG_ARM_THUMB	1	/* this is an ARM720TDMI */
+#define CONFIG_NETARM                   /* it's a Netsiclicon NET+ARM */
+#undef  CONFIG_NETARM_NET40_REV2        /* it's a Net+40 Rev. 2 */
+#undef  CONFIG_NETARM_NET40_REV4	/* it's a Net+40 Rev. 4 */
+#define CONFIG_NETARM_NET50             /* it's a Net+50 */
+
+#define CONFIG_MODNET50		1	/* on an ModNET50 Board      */
+
+#undef CONFIG_USE_IRQ			/* don't need them anymore */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_NETARMETH 1
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		1	/* we use Serial line 1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS		((CONFIG_CMD_DFL | CFG_CMD_JFFS2))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_IPADDR		192.168.30.2
+#define CONFIG_SERVERIP         192.168.30.122
+#define CFG_ETH_PHY_ADDR        0x100
+#define CONFIG_CMDLINE_TAG      /* submit bootargs to kernel */
+
+/*#define CONFIG_BOOTDELAY	10*/
+/* args and cmd for uClinux-image @ 0x10020000, ramdisk-image @ 0x100a0000 */
+#define CONFIG_BOOTCOMMAND	"bootm 0x10020000 0x100a0000"
+#define CONFIG_BOOTARGS    	"console=ttyS0,38400 initrd=0x100a0040,530K root=/dev/ram keepinitrd"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory	*/
+#define	CFG_PROMPT		"modnet50 # "	/* Monitor Command Prompt */
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define	CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x00500000	/* default load address	*/
+
+#define	CFG_HZ			900		/* decrementer freq: 2 kHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+*/
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks of DRAM */
+#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
+#define PHYS_SDRAM_2		0x01000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_2_SIZE	0x01000000 /* 16 MB */
+
+#define PHYS_FLASH_1		0x10000000 /* Flash Bank #1 */
+#define PHYS_FLASH_1_SIZE	0x00200000 /* 2 MB (one chip only, 16bit access) */
+
+#define PHYS_FLASH_2            0x10200001
+#define PHYS_FLASH_2_SIZE       0x00200000
+
+#define CONFIG_NETARM_EEPROM
+/* #ifdef CONFIG_NETARM_EEPROM */
+#define PHYS_NVRAM_1		0x20000000 /* EEPROM Bank #1 */
+#define PHYS_NVRAM_SIZE		0x00002000 /* 8 KB */
+/* #endif */
+
+#define PHYS_EXT_1		0x30000000 /* Extensions Bank #1 */
+#define PHYS_EXT_SIZE		0x01000000 /* 32 MB memory mapped I/O */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CFG_FLASH_SIZE		PHYS_FLASH_1_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
+#define CFG_MAIN_SECT_SIZE      0x00010000  /* main size of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+
+/* environment settings */
+#define	CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_NOWHERE
+
+#define CFG_ENV_ADDR		0x1001C000 /* environment start address */
+#define CFG_ENV_SECT_SIZE       0x10000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE		0x4000	/* max size for environment */
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00080000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=modnet50-0"
+#define MTDPARTS_DEFAULT	"mtdparts=modnet50-0:-@512k(jffs2)"
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
new file mode 100755
index 0000000..04f1f24
--- /dev/null
+++ b/include/configs/mp2usb.h
@@ -0,0 +1,236 @@
+/*
+ * 2004-2005 Gary Jennejohn <garyj@denx.de>
+ *
+ * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
+ * ebenard@eukrea.com
+ *
+ * Configuration settings for the MP2USB board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 45) */
+#define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK/3)	/* peripheral clock */
+
+#define AT91_SLOW_CLOCK		32768	/* slow clock */
+
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
+#define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
+#define CONFIG_AT91RM9200DK	1	/* on an AT91RM9200DK Board	*/
+#define CONFIG_MP2USB		1	/* on an MP2USB Board		*/
+#undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+#define USE_920T_MMU		1
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#define CFG_ATMEL_PLL_INIT_BUG	1
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CFG_USE_MAIN_OSCILLATOR		1
+/* flash */
+#define MC_PUIA_VAL	0x00000000
+#define MC_PUP_VAL	0x00000000
+#define MC_PUER_VAL	0x00000000
+#define MC_ASR_VAL	0x00000000
+#define MC_AASR_VAL	0x00000000
+#define EBI_CFGR_VAL	0x00000000
+#define SMC2_CSR_VAL	0x00003084 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR_VAL	0x20263E04 /* 180 MHz for PCK */
+#define PLLBR_VAL	0x1048bE0E /* 48 MHz (divider by 2 for USB) */
+#define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
+
+/* sdram */
+#define PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define PIOC_BSR_VAL	0x00000000
+#define PIOC_PDR_VAL	0xFFFF0000
+#define EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
+#define SDRC_CR_VAL	0x3211295A /* set up the SDRAM */
+#define SDRAM		0x20000000 /* address of the SDRAM */
+#define SDRAM1		0x20000020 /* address of the SDRAM */
+#define SDRAM_VAL	0x00000000 /* value written to SDRAM */
+#define SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1	0x00000004 /* refresh */
+#define SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_AT91C_BRGR_DIVISOR	33	/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */
+
+/*
+ * Hardware drivers
+ */
+
+/* define one of these to choose the DBGU, USART0  or USART1 as console */
+#define CONFIG_DBGU
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+
+#undef	CONFIG_HWFLOW			/* don't include RTS/CTS flow control support	*/
+
+#undef	CONFIG_MODEM_SUPPORT		/* disable modem initialization stuff */
+
+#define CONFIG_USB_OHCI		1
+#define CONFIG_USB_KEYBOARD	1
+#define CONFIG_USB_STORAGE	1
+#define CONFIG_DOS_PARTITION	1
+#define CONFIG_AT91C_PQFP_UHPBUG 1
+
+#undef CONFIG_HARD_I2C
+
+#ifdef CONFIG_HARD_I2C
+#define CFG_I2C_SPEED		0	/* not used */
+#define CFG_I2C_SLAVE		0	/* not used */
+#define CONFIG_RTC_RS5C372A		/* RICOH I2C RTC */
+#define CFG_I2C_RTC_ADDR	0x32
+#define CFG_I2C_EEPROM_ADDR	0x50
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW
+#endif
+/* still about 20 kB free with this defined */
+#define CFG_LONGHELP
+
+#define CONFIG_BOOTDELAY      3
+
+#ifdef CONFIG_HARD_I2C
+#define CONFIG_COMMANDS		\
+		       ((CONFIG_CMD_DFL	| \
+			CFG_CMD_DATE	| \
+			CFG_CMD_DHCP 	| \
+			CFG_CMD_EEPROM	| \
+			CFG_CMD_I2C	| \
+			CFG_CMD_NFS	| \
+			CFG_CMD_SNTP	| \
+			CFG_CMD_MISC))
+#else
+#define CONFIG_COMMANDS		\
+		       ((CONFIG_CMD_DFL	| \
+			CFG_CMD_DHCP 	| \
+			CFG_CMD_NFS	| \
+			CFG_CMD_SNTP	| \
+			CFG_CMD_USB      | \
+			CFG_CMD_CACHE)	& \
+		      ~(CFG_CMD_BDI | \
+			CFG_CMD_IMI | \
+			CFG_CMD_AUTOSCRIPT | \
+			CFG_CMD_FPGA | \
+			CFG_CMD_MISC | \
+			CFG_CMD_LOADS ))
+#define CONFIG_TIMESTAMP
+#endif
+#define CFG_LONGHELP
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x20000000
+#define PHYS_SDRAM_SIZE		0x08000000 	/* 128 megs */
+
+#define CFG_MEMTEST_START	PHYS_SDRAM
+#define CFG_MEMTEST_END		CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
+
+#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_RETRY_COUNT		20
+#undef CONFIG_AT91C_USE_RMII
+
+#define PHYS_FLASH_1			0x10000000
+#define PHYS_FLASH_SIZE			0x1000000  /* 16 megs main flash */
+#define CFG_FLASH_BASE			PHYS_FLASH_1
+#define CFG_MONITOR_BASE		CFG_FLASH_BASE
+#define CFG_MAX_FLASH_BANKS		1
+#define CFG_MAX_FLASH_SECT		256
+#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Write */
+#define CFG_FLASH_LOCK_TOUT		(10*CFG_HZ)	/* Timeout for Flash Set Lock Bit */
+#define CFG_FLASH_UNLOCK_TOUT		(10*CFG_HZ)	/* Timeout for Flash Clear Lock Bits */
+#define CFG_FLASH_PROTECTION				/* "Real" (hardware) sectors protection */
+
+#define CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_OFFSET			0x20000		/* after u-boot.bin */
+#define CFG_ENV_ADDR			(CFG_FLASH_BASE+CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE			0x20000
+
+#define CFG_LOAD_ADDR		0x21000000  /* default load address */
+
+#define CFG_BAUDRATE_TABLE	{ 115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size */
+#define CFG_MAXARGS		32		/* max number of command args */
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+
+#define CFG_DEVICE_DEREGISTER           /* needs device_deregister */
+#define LITTLEENDIAN            1       /* used by usb_ohci.c  */
+
+#ifndef __ASSEMBLY__
+/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext {
+	/* helper variable for board environment handling
+	 *
+	 * env_crc_valid == 0	 =>   uninitialised
+	 * env_crc_valid  > 0	 =>   environment crc in flash is valid
+	 * env_crc_valid  < 0	 =>   environment crc in flash is invalid
+	 */
+	int env_crc_valid;
+};
+#endif	/* __ASSEMBLY__ */
+
+#define CFG_HZ 1000
+#define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2)	/* AT91C_TC0_CMR is implicitly set to */
+						/* AT91C_TC_TIMER_DIV1_CLOCK */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#define CFG_DEVICE_NULLDEV	 1	/* enble null device		*/
+#undef CONFIG_SILENT_CONSOLE		/* enable silent startup	*/
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+
+#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h
new file mode 100755
index 0000000..7f3dfd5
--- /dev/null
+++ b/include/configs/mx1ads.h
@@ -0,0 +1,184 @@
+/*
+ * include/configs/mx1ads.h
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This is the Configuration setting for Motorola MX1ADS board
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core		*/
+#define CONFIG_IMX		1	/* It's a Motorola MC9328 SoC		*/
+#define CONFIG_MX1ADS		1	/* on a Motorola MX1ADS Board		*/
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff		*/
+
+/*
+ * Select serial console configuration
+  */
+#define CONFIG_IMX_SERIAL1		/* internal uart 1 */
+/* #define _CONFIG_UART2 */		/* internal uart 2 */
+/* #define CONFIG_SILENT_CONSOLE */	/* use this to disable output */
+
+#define BOARD_LATE_INIT		1
+#define USE_920T_MMU		1
+
+#if 0
+#define CFG_MX1_GPCR		0x000003AB	/* for MX1ADS 0L44N		*/
+#define CFG_MX1_GPCR		0x000003AB	/* for MX1ADS 0L44N		*/
+#define CFG_MX1_GPCR		0x000003AB	/* for MX1ADS 0L44N		*/
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ *  CS8900 Ethernet drivers
+ */
+#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
+#define CS8900_BASE		0x15000300
+#define CS8900_BUS16		1	/* the Linux driver does accesses as shorts */
+
+/*
+ * select serial console configuration
+ */
+
+/* #define CONFIG_UART1			*/
+/* #define CONFIG_UART2		1	*/
+
+#define CONFIG_BAUDRATE		115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#define CONFIG_COMMANDS \
+			(CONFIG_CMD_DFL	 | \
+			CFG_CMD_CACHE	 | \
+			CFG_CMD_REGINFO	 | \
+			CFG_CMD_ELF)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"root=/dev/msdk mem=48M"
+#define CONFIG_BOOTFILE		"mx1ads"
+#define CONFIG_BOOTCOMMAND	"tftp; bootm"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+						/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CFG_HUSH_PARSER		1
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#define CFG_LONGHELP				/* undef to save memory		*/
+
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT		"MX1ADS$ "	/* Monitor Command Prompt */
+#else
+#define CFG_PROMPT		"MX1ADS=> "	/* Monitor Command Prompt */
+#endif
+
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+						/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x09000000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0AF00000	/* 63 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ				/* everything, incl board info, in Hz */
+#define CFG_LOAD_ADDR		0x08800000	/* default load address */
+/*#define	CFG_HZ			1000 */
+#define CFG_HZ			3686400
+#define CFG_CPUSPEED		0x141
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of SDRAM	*/
+#define PHYS_SDRAM_1		0x08000000	/* SDRAM  on CSD0		*/
+#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB			*/
+
+#define CFG_MAX_FLASH_BANKS	1		/* 1 bank of SyncFlash		*/
+#define CFG_FLASH_BASE		0x0C000000	/* SyncFlash on CSD1		*/
+#define FLASH_BANK_SIZE		0x01000000	/* 16 MB Total			*/
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CONFIG_SYNCFLASH	1
+#define PHYS_FLASH_SIZE		0x01000000
+#define CFG_MAX_FLASH_SECT	(16)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x00ff8000)
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x04000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE	0x100000
+
+/*-----------------------------------------------------------------------
+ * Enable passing ATAGS
+ */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+
+#define CONFIG_SYS_CLK_FREQ 16780000
+#define CONFIG_SYSPLL_CLK_FREQ 16000000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h
new file mode 100755
index 0000000..9816be8
--- /dev/null
+++ b/include/configs/mx1fs2.h
@@ -0,0 +1,303 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARM920T	   1	 /* this is an ARM920T CPU     */
+#define CONFIG_IMX	   1	 /* in a Motorola MC9328MXL Chip */
+#define CONFIG_MX1FS2	   1	 /* on a mx1fs2 board */
+#undef	CONFIG_USE_IRQ		 /* don't need use IRQ/FIQ    */
+
+/*
+ * Select serial console configuration
+ */
+#undef	_CONFIG_UART1 /* internal uart 1 */
+#define _CONFIG_UART2 /* internal uart 2 */
+#undef	_CONFIG_UART3 /* internal uart 3 */
+#undef	_CONFIG_UART4 /* internal uart 4 */
+#undef	CONFIG_SILENT_CONSOLE  /* use this to disable output */
+
+/*
+ * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
+ * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
+ * functionality or size of u-boot code.
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL		 \
+				& ~CFG_CMD_LOADS	 \
+				& ~CFG_CMD_CONSOLE	 \
+				& ~CFG_CMD_AUTOSCRIPT	 \
+				& ~CFG_CMD_NET		 \
+				& ~CFG_CMD_PING		 \
+				& ~CFG_CMD_DHCP		 \
+				| CFG_CMD_JFFS2		 \
+				)
+
+#include <cmd_confdefs.h>
+
+/*
+ * Boot options. Setting delay to -1 stops autostart count down.
+ */
+#define CONFIG_BOOTDELAY   10
+#define CONFIG_BOOTARGS	   "root=/dev/mtdblock4 console=ttySMX0,115200n8 rootfstype=jffs2"
+#define CONFIG_BOOTCOMMAND "bootm 10080000"
+#define CONFIG_SHOW_BOOT_PROGRESS
+
+/*
+ * General options for u-boot. Modify to save memory foot print
+ */
+#define CFG_LONGHELP				      /* undef saves memory  */
+#define CFG_PROMPT		"mx1fs2> "	      /* prompt string	     */
+#define CFG_CBSIZE		256		      /* console I/O buffer  */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size   */
+#define CFG_MAXARGS		16		      /* max command args    */
+#define CFG_BARGSIZE		CFG_CBSIZE	      /* boot args buf size  */
+
+#define CFG_MEMTEST_START	0x08100000	      /* memtest test area   */
+#define CFG_MEMTEST_END		0x08F00000
+
+#undef	CFG_CLKS_IN_HZ			     /* use HZ for freq. display     */
+
+#define CFG_HZ			3686400	     /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x141	     /* core clock - register value  */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+/*
+ * Definitions related to passing arguments to kernel.
+ */
+#define CONFIG_CMDLINE_TAG	     1	 /* send commandline to Kernel	     */
+#define CONFIG_SETUP_MEMORY_TAGS     1	 /* send memory definition to kernel */
+#define	 CONFIG_INITRD_TAG	     1	   /* send initrd params	*/
+#undef	CONFIG_VFD			 /* do not send framebuffer setup    */
+
+/*
+ * Malloc pool need to host env + 128 Kb reserve for other allocations.
+ */
+#define CFG_MALLOC_LEN	  (CFG_ENV_SIZE + (128<<10) )
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE	(120<<10)      /* stack size */
+
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4<<10)	       /* IRQ stack  */
+#define CONFIG_STACKSIZE_FIQ	(4<<10)	       /* FIQ stack  */
+#endif
+
+/* SDRAM Setup Values
+ * 0x910a8300 Precharge Command CAS 3
+ * 0x910a8200 Precharge Command CAS 2
+ *
+ * 0xa10a8300 AutoRefresh Command CAS 3
+ * 0xa10a8200 Set AutoRefresh Command CAS 2
+ */
+#define PRECHARGE_CMD 0x910a8300
+#define AUTOREFRESH_CMD 0xa10a8300
+
+#define BUS32BIT_VERSION
+/*
+ * SDRAM Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS  1			     /* we have 1 bank of SDRAM */
+#define MX1FS2_SDRAM_1	      0x08000000	     /* SDRAM bank #1		*/
+#ifdef BUS32BIT_VERSION
+#define MX1FS2_SDRAM_1_SIZE  (0x04000000 - 0x100000) /* 64 MB - 1M Framebuffer */
+#else
+#define MX1FS2_SDRAM_1_SIZE  (0x01FC0000 - 0x100000) /* 32 MB - 1M Framebuffer */
+#endif
+/*
+ * Flash Controller settings
+ */
+
+#define CFG_MAX_FLASH_BANKS	1	/* FLASH banks count (not chip count)*/
+#define CFG_MAX_FLASH_SECT	256	/* number of sector in FLASH bank    */
+
+#ifdef BUS32BIT_VERSION
+#define MX1FS2_FLASH_BUS_WIDTH	4	/* we use 32 bit FLASH memory...     */
+#define MX1FS2_FLASH_INTERLEAVE 2	/* ... made of 2 chips */
+#define MX1FS2_FLASH_BANK_SIZE	0x02000000  /* size of one flash bank*/
+#define MX1FS2_FLASH_SECT_SIZE	0x00020000  /* size of erase sector */
+#else
+#define MX1FS2_FLASH_BUS_WIDTH	2	/* we use 16 bit FLASH memory...     */
+#define MX1FS2_FLASH_INTERLEAVE 1	/* ... made of 1 chip */
+#define MX1FS2_FLASH_BANK_SIZE	0x01000000  /* size of one flash bank*/
+#define MX1FS2_FLASH_SECT_SIZE	0x00010000  /* size of erase sector */
+#endif
+#define MX1FS2_FLASH_BASE	0x10000000  /* location of flash memory */
+#define MX1FS2_FLASH_UNLOCK	   1	   /* perform hw unlock first */
+
+/* This should be defined if CFI FLASH device is present. Actually benefit
+   is not so clear to me. In other words we can provide more informations
+   to user, but this expects more complex flash handling we do not provide
+   now.*/
+#undef	CFG_FLASH_CFI
+
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)    /* timeout for Erase operation */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)    /* timeout for Write operation */
+
+#define CFG_FLASH_BASE		MX1FS2_FLASH_BASE
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * Right now there is no gain for user, but later on booting kernel might be
+ * possible. Consider using XIP kernel running from flash to save RAM
+ * footprint.
+ * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
+ */
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition, whole device */
+/*
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00050000
+*/
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=mx1fs2-0"
+
+#ifdef BUS32BIT_VERSION
+#define MTDPARTS_DEFAULT	"mtdparts=mx1fs2-0:2m@5m(part0),5m@9m(part1)"
+#else
+#define MTDPARTS_DEFAULT	"mtdparts=mx1fs2-0:-@320k(jffs2)"
+#endif
+
+/*
+ * Environment setup. Definitions of monitor location and size with
+ * definition of environment setup ends up in 2 possibilities.
+ * 1. Embeded environment - in u-boot code is space for environment
+ * 2. Environment is read from predefined sector of flash
+ * Right now we support 2. possiblity, but expecting no env placed
+ * on mentioned address right now. This also needs to provide whole
+ * sector for it - for us 256Kb is really waste of memory. U-boot uses
+ * default env. and until kernel parameters could be sent to kernel
+ * env. has no sense to us.
+ */
+
+#define CFG_MONITOR_BASE	0x10000000
+#define CFG_MONITOR_LEN		0x20000		/* 128b ( 1 flash sector )   */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0x10020000	/* absolute address for now  */
+#define CFG_ENV_SIZE		0x20000
+
+#define	 CONFIG_ENV_OVERWRITE	1		/* env is not writable now   */
+
+/* Setup CS4 and CS5 */
+#define CFG_GIUS_A_VAL		0x0003fffe
+
+/*
+ * CSxU_VAL:
+ * 63| x	x x x | x x x x | x x  x    x | x x x x | x x x x | x x x x | x x x x | x x x x|32
+ *   |DTACK_SEL|0|BCD |	  BCS	| PSZ|PME|SYNC|	 DOL	| CNC|	  WSC	    | 0| WWS  |	  EDC  |
+ *
+ * CSxL_VAL:
+ * 31| x x x x | x x x x | x x x x | x x x x | x x x x |  x x x x | x x	 x x | x x  x	 x| 0
+ *   |	 OEA   |   OEN	 |   WEA   |   WEN   |	 CSA   |EBC| DSZ  | 0|SP|0|WP| 0 0|PA|CSEN|
+ */
+
+#define CFG_CS0U_VAL 0x00008C00
+#define CFG_CS0L_VAL 0x22222601
+#define CFG_CS1U_VAL 0x00008C00
+#define CFG_CS1L_VAL 0x22222301
+#define CFG_CS4U_VAL 0x00008C00
+#define CFG_CS4L_VAL 0x22222301
+#define CFG_CS5U_VAL 0x00008C00
+#define CFG_CS5L_VAL 0x22222301
+
+/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
+   f_ref=16,777MHz
+
+   0x002a141f: 191,9944MHz
+   0x040b2007: 144MHz
+   0x042a141f: 96MHz
+   0x0811140d: 64MHz
+   0x040e200e: 150MHz
+   0x00321431: 200MHz
+
+   0x08001800: 64MHz mit 16er Quarz
+   0x04001800: 96MHz mit 16er Quarz
+   0x04002400: 144MHz mit 16er Quarz
+
+   31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
+      |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|	    */
+
+#define CFG_MPCTL0_VAL		0x07E723AD
+#define CFG_MPCTL1_VAL		0x00000040
+#define CFG_PCDR_VAL		0x00010005
+#define CFG_GPCR_VAL		0x00000FFB
+
+#define USE_16M_OSZI /* If you have one, you want to use it
+			The internal 32kHz oszillator jitters */
+#ifdef USE_16M_OSZI
+
+#define CFG_SPCTL0_VAL		0x04001401
+#define CFG_SPCTL1_VAL		0x0C000040
+#define CFG_CSCR_VAL		0x07030003
+#define CONFIG_SYS_CLK_FREQ	16780000
+#define CONFIG_SYSPLL_CLK_FREQ	16000000
+
+#else
+
+#define CFG_SPCTL0_VAL		0x07E716D1
+#define CFG_CSCR_VAL		0x06000003
+#define CONFIG_SYS_CLK_FREQ	16780000
+#define CONFIG_SYSPLL_CLK_FREQ	16780000
+
+#endif
+
+/*
+ * Well this has to be defined, but on the other hand it is used differently
+ * one may expect. For instance loadb command do not cares :-)
+ * So advice is - do not relay on this...
+ */
+#define CFG_LOAD_ADDR		0x08400000
+
+#define CFG_FMCR_VAL		0x00000003 /* Reset Default */
+
+/* Bit[0:3] contain PERCLK1DIV for UART 1
+   0x000b00b ->b<- -> 192MHz/12=16MHz
+   0x000b00b ->8<- -> 144MHz/09=16MHz
+   0x000b00b ->3<- -> 64MHz/4=16MHz */
+
+#ifdef _CONFIG_UART1
+#define CONFIG_IMX_SERIAL1
+#elif defined _CONFIG_UART2
+#define CONFIG_IMX_SERIAL2
+#elif defined _CONFIG_UART3 | defined _CONFIG_UART4
+#define CONFIG_IMX_SERIAL_NONE
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_CLK		3686400
+#define CFG_NS16550_REG_SIZE	1
+#define CONFIG_CONS_INDEX	1
+#ifdef _CONFIG_UART3
+#define CFG_NS16550_COM1	0x15000000
+#elif defined _CONFIG_UART4
+#define CFG_NS16550_COM1	0x16000000
+#endif
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h
new file mode 100755
index 0000000..0b1541d
--- /dev/null
+++ b/include/configs/ns9750dev.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ * Markus Pietrek <mpietrek@fsforth.de>
+ *
+ * Configuation settings for the NetSilicon NS9750 DevBoard
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
+#define	CONFIG_NS9750		1	/* in an NetSilicon NS9750 SoC     */
+#define CONFIG_NS9750DEV	1	/* on an NetSilicon NS9750 DevBoard  */
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ	324403200 /* Don't use PLL. SW11-4 off */
+
+#define CPU_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/2)
+#define AHB_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/4)
+#define BBUS_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/8)
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+/*@TODO #define CONFIG_STATUS_LED*/
+#define CONFIG_USE_IRQ
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial
+					 * data */
+
+/*
+ * Hardware drivers
+ */
+#define CFG_NS9750_UART			1	/* use on-chip UART */
+#define CONFIG_DRIVER_NS9750_ETHERNET	1	/* use on-chip ethernet */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX          1 		/* Port B */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		38400
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#if 0 /* @TODO */
+#define CONFIG_COMMANDS \
+			(CONFIG_CMD_DFL	 | \
+			CFG_CMD_CACHE	 | \
+			/*CFG_CMD_NAND	 |*/ \
+			/*CFG_CMD_EEPROM |*/ \
+			/*CFG_CMD_I2C	 |*/ \
+			/*CFG_CMD_USB	 |*/ \
+			CFG_CMD_REGINFO  | \
+			CFG_CMD_DATE	 | \
+			CFG_CMD_ELF)
+#else
+#define CONFIG_COMMANDS \
+			(CONFIG_CMD_BDI | \
+			CFG_CMD_NET | \
+			CFG_CMD_PING	 | \
+			CFG_CMD_CONSOLE	 | \
+			CFG_CMD_LOADB	 | \
+			CFG_CMD_LOADS	 | \
+			CFG_CMD_MEMORY)
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+/*#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600" */
+
+#define CONFIG_ETHADDR		00:04:f3:ff:ff:fb /*@TODO unset */
+#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_IPADDR		192.168.42.30
+#define CONFIG_SERVERIP		192.168.42.1
+
+/*#define CONFIG_BOOTFILE	"elinos-lart" */
+/*#define CONFIG_BOOTCOMMAND	"tftp; bootm" */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"NS9750DEV # "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00000000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00780000	/* 7,5 MB in DRAM	*/ /* @TODO */
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x00600000	/* default load address	*/ /* @TODO */
+
+#define	CFG_HZ			(CPU_CLK_FREQ/64)
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define NS9750_ETH_PHY_ADDRESS	(0x0000)
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+/* TODO */
+#define CONFIG_NR_DRAM_BANKS	2	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB */
+#define PHYS_SDRAM_2		0x10000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_2_SIZE	0x00800000 /* 8 MB */
+
+#define PHYS_FLASH_1		0x50000000 /* Flash Bank #1 */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* @TODO*/
+#define CONFIG_AMD_LV400	1	/* uncomment this if you have a LV400 flash */
+#if 0
+#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
+#endif
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#ifdef CONFIG_AMD_LV800
+#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
+#define CFG_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
+#endif
+#ifdef CONFIG_AMD_LV400
+#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
+#define CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x070000) /* addr of environment */
+#endif
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+
+/* @TODO */
+/*#define	CFG_ENV_IS_IN_FLASH	1*/
+#define CFG_ENV_IS_NOWHERE
+#define CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
+
+#ifdef CONFIG_STATUS_LED
+
+extern void __led_init(led_id_t mask, int state);
+extern void __led_toggle(led_id_t mask);
+extern void __led_set(led_id_t mask, int state);
+
+#endif /* CONFIG_STATUS_LED */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h
new file mode 100755
index 0000000..5c05a74
--- /dev/null
+++ b/include/configs/o2dnt.h
@@ -0,0 +1,296 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200
+#define CONFIG_O2DNT		1	/* ... on O2DNT board */
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	5	/* console is on PSC5 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+/* #define CONFIG_PCI_SCAN_SHOW	1 */
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CFG_XLB_PIPELINING	1
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X		1
+
+#define ADD_PCI_CMD 		CFG_CMD_PCI
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				ADD_PCI_CMD	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
+#   define CFG_LOWBOOT		1
+#else
+#   error "TEXT_BASE must be 0xFF000000"
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/MPC5200/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#endif
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		1	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration:
+ *
+ * O2DNT board is equiped with Ramtron FRAM device FM24CL16
+ * 16 Kib Ferroelectric Nonvolatile serial RAM memory
+ * organized as 2048 x 8 bits and addressable as eight I2C devices
+ * 0x50 ... 0x57 each 256 bytes in size
+ *
+ */
+#define CFG_I2C_FRAM
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+/*
+ * There is no write delay with FRAM, write operations are performed at bus
+ * speed. Thus, no status polling or write delay is needed.
+ */
+/*#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70*/
+
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		0xFF000000
+#define CFG_FLASH_SIZE		0x01000000
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
+
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x20000
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ */
+/*#define CFG_GPS_PORT_CONFIG	0x10002004 */
+#define CFG_GPS_PORT_CONFIG	0x00002006	/* no CAN */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+
+#ifdef CFG_PCISPEED_66
+/*
+ * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
+ */
+#define CFG_BOOTCS_CFG		0x00057801 /* for pci_clk = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG		0x00047801 /* for pci_clk = 33 MHz */
+#endif
+
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h
new file mode 100755
index 0000000..a13d6a8
--- /dev/null
+++ b/include/configs/ocotea.h
@@ -0,0 +1,320 @@
+/*
+ * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * 1 March 2004	 Travis B. Sawyer <tsawyer@sandburst.com>
+ * Adapted to current Das U-Boot source
+ ***********************************************************************/
+
+
+/************************************************************************
+ * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_OCOTEA		1	    /* Board is ebony		*/
+#define CONFIG_440GX		1	    /* Specifc GX support	*/
+#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
+#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
+#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
+#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
+#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
+#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
+#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
+#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
+
+#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
+#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_TEMP_STACK_OCM  1
+#define CFG_OCM_DATA_ADDR   CFG_ISRAM_BASE
+#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
+#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE   128		    /* num bytes initial data	*/
+
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
+#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR
+
+#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
+#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ *       supported for backward compatibility.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE		0x1000	    /* Size of Environment vars */
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_NVRAM */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS	3		    /* number of banks	    */
+#define CFG_MAX_FLASH_SECT	64		    /* sectors per device   */
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_ADDR0         0x5555
+#define CFG_FLASH_ADDR1         0x2aaa
+#define CFG_FLASH_WORD_SIZE     unsigned char
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM	1	 /* Use SPD EEPROM for setup	 */
+#define SPD_EEPROM_ADDRESS {0x53,0x52}	/* SPD i2c spd addresses	*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES    {0x69}  /* Don't probe these addrs */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=ocotea\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/ocotea/uImage\0"				\
+	"kernel_addr=fff00000\0"					\
+	"ramdisk_addr=fff10000\0"					\
+	"load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0"		\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_NET_MULTI	1
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR	2
+#define CONFIG_PHY2_ADDR	0x10
+#define CONFIG_PHY3_ADDR	0x18
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
+#define CONFIG_PHY_RESET_DELAY	1000
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
+#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		32768	/* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/omap1510.h b/include/configs/omap1510.h
new file mode 100755
index 0000000..6787b19
--- /dev/null
+++ b/include/configs/omap1510.h
@@ -0,0 +1,790 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   OMAP hardware map
+ *
+ * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
+ * Author: RidgeRun, Inc.
+ *	   Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ *  This program is free software; you can redistribute	 it and/or modify it
+ *  under  the terms of	 the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the	License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
+ *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
+ *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/arch/sizes.h>
+
+/*
+  There are 2 sets of general I/O -->
+  1. GPIO (shared between ARM & DSP, configured by ARM)
+  2. MPUIO which can be used only by the ARM.
+
+  Base address FFFB:5000 is where the ARM accesses the MPUIO control registers
+  (see 7.2.2 of the TRM for MPUIO reg definitions).
+
+  Base address E101:5000 is reserved for ARM access of the same MPUIO control
+  regs, but via the DSP I/O map.  This address is unavailable on 1510.
+
+  Base address FFFC:E000 is where the ARM accesses the GPIO config registers
+  directly via its own peripheral bus.
+
+  Base address E101:E000 is where the ARM can access the same GPIO config
+  registers, but the access takes place through the ARM port interface (called
+  API or MPUI) via the DSP's peripheral bus (DSP I/O space).
+
+  Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses
+  instead of the E101:E000 addresses.  The DSP has only read access of the pin
+  control register, so this may explain the inability to write to E101:E018.
+  Try accessing pin control reg at FFFC:E018.
+ */
+#define OMAP1510_GPIO_BASE	 0xfffce000
+#define OMAP1510_GPIO_START	 OMAP1510_GPIO_BASE
+#define OMAP1510_GPIO_SIZE	 SZ_4K
+
+#define OMAP1510_MCBSP1_BASE	 0xE1011000
+#define OMAP1510_MCBSP1_SIZE	 SZ_4K
+#define OMAP1510_MCBSP1_START	 0xE1011000
+
+#define OMAP1510_MCBSP2_BASE	 0xFFFB1000
+
+#define OMAP1510_MCBSP3_BASE	 0xE1017000
+#define OMAP1510_MCBSP3_SIZE	 SZ_4K
+#define OMAP1510_MCBSP3_START	 0xE1017000
+
+/*
+ * Where's the flush address (for flushing D and I cache?)
+ */
+#define FLUSH_BASE		0xdf000000
+#define FLUSH_BASE_PHYS 0x00000000
+
+#ifndef __ASSEMBLER__
+
+#define PCIO_BASE		0
+
+/*
+ * RAM definitions
+ */
+#define MAPTOPHYS(a)		((unsigned long)(a) - PAGE_OFFSET)
+#define KERNTOPHYS(a)		((unsigned long)(&a))
+#define KERNEL_BASE		(0x10008000)
+#endif
+
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x) ((x))
+
+/* ----------------------------------------------------------------------------
+ *  OMAP1510 system registers
+ * ----------------------------------------------------------------------------
+ */
+
+#define OMAP1510_UART1_BASE	    0xfffb0000	 /* "BLUETOOTH-UART" */
+#define OMAP1510_UART2_BASE	    0xfffb0800	 /* "MODEM-UART" */
+#define OMAP1510_RTC_BASE	    0xfffb4800	 /* RTC */
+#define OMAP1510_UART3_BASE	    0xfffb9800	 /* Shared MPU/DSP UART */
+#define OMAP1510_COM_MCBSP2_BASE    0xffff1000	 /* Com McBSP2 */
+#define OMAP1510_AUDIO_MCBSP_BASE   0xffff1800	 /* Audio McBSP2 */
+#define OMAP1510_ARMIO_BASE	    0xfffb5000	 /* keyboard/gpio */
+
+/*
+ * OMAP1510 UART3 Registers
+ */
+
+#define OMAP_MPU_UART3_BASE  0xFFFB9800 /* UART3 through MPU bus */
+
+/* UART3 Registers Maping through MPU bus */
+
+#define UART3_RHR	 (OMAP_MPU_UART3_BASE + 0)
+#define UART3_THR	 (OMAP_MPU_UART3_BASE + 0)
+#define UART3_DLL	 (OMAP_MPU_UART3_BASE + 0)
+#define UART3_IER	 (OMAP_MPU_UART3_BASE + 4)
+#define UART3_DLH	 (OMAP_MPU_UART3_BASE + 4)
+#define UART3_IIR	 (OMAP_MPU_UART3_BASE + 8)
+#define UART3_FCR	 (OMAP_MPU_UART3_BASE + 8)
+#define UART3_EFR	 (OMAP_MPU_UART3_BASE + 8)
+#define UART3_LCR	 (OMAP_MPU_UART3_BASE + 0x0C)
+#define UART3_MCR	 (OMAP_MPU_UART3_BASE + 0x10)
+#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10)
+#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14)
+#define UART3_LSR	 (OMAP_MPU_UART3_BASE + 0x14)
+#define UART3_TCR	 (OMAP_MPU_UART3_BASE + 0x18)
+#define UART3_MSR	 (OMAP_MPU_UART3_BASE + 0x18)
+#define UART3_XOFF1	 (OMAP_MPU_UART3_BASE + 0x18)
+#define UART3_XOFF2	 (OMAP_MPU_UART3_BASE + 0x1C)
+#define UART3_SPR	 (OMAP_MPU_UART3_BASE + 0x1C)
+#define UART3_TLR	 (OMAP_MPU_UART3_BASE + 0x1C)
+#define UART3_MDR1	 (OMAP_MPU_UART3_BASE + 0x20)
+#define UART3_MDR2	 (OMAP_MPU_UART3_BASE + 0x24)
+#define UART3_SFLSR	 (OMAP_MPU_UART3_BASE + 0x28)
+#define UART3_TXFLL	 (OMAP_MPU_UART3_BASE + 0x28)
+#define UART3_RESUME	 (OMAP_MPU_UART3_BASE + 0x2C)
+#define UART3_TXFLH	 (OMAP_MPU_UART3_BASE + 0x2C)
+#define UART3_SFREGL	 (OMAP_MPU_UART3_BASE + 0x30)
+#define UART3_RXFLL	 (OMAP_MPU_UART3_BASE + 0x30)
+#define UART3_SFREGH	 (OMAP_MPU_UART3_BASE + 0x34)
+#define UART3_RXFLH	 (OMAP_MPU_UART3_BASE + 0x34)
+#define UART3_BLR	 (OMAP_MPU_UART3_BASE + 0x38)
+#define UART3_ACREG	 (OMAP_MPU_UART3_BASE + 0x3C)
+#define UART3_DIV16	 (OMAP_MPU_UART3_BASE + 0x3C)
+#define UART3_SCR	 (OMAP_MPU_UART3_BASE + 0x40)
+#define UART3_SSR	 (OMAP_MPU_UART3_BASE + 0x44)
+#define UART3_EBLR	 (OMAP_MPU_UART3_BASE + 0x48)
+#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C)
+#define UART3_MVR	 (OMAP_MPU_UART3_BASE + 0x50)
+
+/*
+ * Configuration Registers
+ */
+#define FUNC_MUX_CTRL_0		0xfffe1000
+#define FUNC_MUX_CTRL_1		0xfffe1004
+#define FUNC_MUX_CTRL_2		0xfffe1008
+#define COMP_MODE_CTRL_0	0xfffe100c
+#define FUNC_MUX_CTRL_3		0xfffe1010
+#define FUNC_MUX_CTRL_4		0xfffe1014
+#define FUNC_MUX_CTRL_5		0xfffe1018
+#define FUNC_MUX_CTRL_6		0xfffe101C
+#define FUNC_MUX_CTRL_7		0xfffe1020
+#define FUNC_MUX_CTRL_8		0xfffe1024
+#define FUNC_MUX_CTRL_9		0xfffe1028
+#define FUNC_MUX_CTRL_A		0xfffe102C
+#define FUNC_MUX_CTRL_B		0xfffe1030
+#define FUNC_MUX_CTRL_C		0xfffe1034
+#define FUNC_MUX_CTRL_D		0xfffe1038
+#define PULL_DWN_CTRL_0		0xfffe1040
+#define PULL_DWN_CTRL_1		0xfffe1044
+#define PULL_DWN_CTRL_2		0xfffe1048
+#define PULL_DWN_CTRL_3		0xfffe104c
+#define GATE_INH_CTRL_0		0xfffe1050
+#define VOLTAGE_CTRL_0		0xfffe1060
+#define TEST_DBG_CTRL_0		0xfffe1070
+
+#define MOD_CONF_CTRL_0		0xfffe1080
+
+#ifdef CONFIG_OMAP1610 /* 1610 Configuration Register */
+
+#define USB_OTG_CTRL			0xFFFB040C
+#define USB_TRANSCEIVER_CTRL	0xFFFE1064
+#define PULL_DWN_CTRL_4 0xFFFE10AC
+#define PU_PD_SEL_0		0xFFFE10B4
+#define PU_PD_SEL_1		0xFFFE10B8
+#define PU_PD_SEL_2		0xFFFE10BC
+#define PU_PD_SEL_3		0xFFFE10C0
+#define PU_PD_SEL_4		0xFFFE10C4
+
+#endif
+/*
+ * Traffic Controller Memory Interface Registers
+ */
+#define TCMIF_BASE		0xfffecc00
+#define IMIF_PRIO		(TCMIF_BASE + 0x00)
+#define EMIFS_PRIO_REG		(TCMIF_BASE + 0x04)
+#define EMIFF_PRIO_REG		(TCMIF_BASE + 0x08)
+#define EMIFS_CONFIG_REG	(TCMIF_BASE + 0x0c)
+#define EMIFS_CS0_CONFIG	(TCMIF_BASE + 0x10)
+#define EMIFS_CS1_CONFIG	(TCMIF_BASE + 0x14)
+#define EMIFS_CS2_CONFIG	(TCMIF_BASE + 0x18)
+#define EMIFS_CS3_CONFIG	(TCMIF_BASE + 0x1c)
+#define EMIFF_SDRAM_CONFIG	(TCMIF_BASE + 0x20)
+#define EMIFF_MRS		(TCMIF_BASE + 0x24)
+#define TC_TIMEOUT1		(TCMIF_BASE + 0x28)
+#define TC_TIMEOUT2		(TCMIF_BASE + 0x2c)
+#define TC_TIMEOUT3		(TCMIF_BASE + 0x30)
+#define TC_ENDIANISM		(TCMIF_BASE + 0x34)
+#define EMIFF_SDRAM_CONFIG_2	(TCMIF_BASE + 0x3c)
+#define EMIF_CFG_DYNAMIC_WS	(TCMIF_BASE + 0x40)
+
+/*
+ * LCD Panel
+ */
+#define TI925_LCD_BASE		0xFFFEC000
+#define TI925_LCD_CONTROL	(TI925_LCD_BASE)
+#define TI925_LCD_TIMING0	(TI925_LCD_BASE+0x4)
+#define TI925_LCD_TIMING1	(TI925_LCD_BASE+0x8)
+#define TI925_LCD_TIMING2	(TI925_LCD_BASE+0xc)
+#define TI925_LCD_STATUS	(TI925_LCD_BASE+0x10)
+#define TI925_LCD_SUBPANEL	(TI925_LCD_BASE+0x14)
+
+#define OMAP_LCD_CONTROL	TI925_LCD_CONTROL
+
+/* I2C Registers */
+
+#define I2C_BASE		0xfffb3800
+
+#define I2C_REV			(I2C_BASE + 0x00)
+#define I2C_IE			(I2C_BASE + 0x04)
+#define I2C_STAT		(I2C_BASE + 0x08)
+#define I2C_IV			(I2C_BASE + 0x0c)
+#define I2C_BUF			(I2C_BASE + 0x14)
+#define I2C_CNT			(I2C_BASE + 0x18)
+#define I2C_DATA		(I2C_BASE + 0x1c)
+#define I2C_CON			(I2C_BASE + 0x24)
+#define I2C_OA			(I2C_BASE + 0x28)
+#define I2C_SA			(I2C_BASE + 0x2c)
+#define I2C_PSC			(I2C_BASE + 0x30)
+#define I2C_SCLL		(I2C_BASE + 0x34)
+#define I2C_SCLH		(I2C_BASE + 0x38)
+#define I2C_SYSTEST		(I2C_BASE + 0x3c)
+
+/* I2C masks */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+
+#define I2C_IE_XRDY_IE	(1 << 4)	/* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE	(1 << 3)	/* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE	(1 << 2)	/* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE	(1 << 1)	/* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE	(1 << 0)	/* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_SBD	(1 << 15)	/* Single byte data */
+#define I2C_STAT_BB	(1 << 12)	/* Bus busy */
+#define I2C_STAT_ROVR	(1 << 11)	/* Receive overrun */
+#define I2C_STAT_XUDF	(1 << 10)	/* Transmit underflow */
+#define I2C_STAT_AAS	(1 << 9)	/* Address as slave */
+#define I2C_STAT_AD0	(1 << 8)	/* Address zero */
+#define I2C_STAT_XRDY	(1 << 4)	/* Transmit data ready */
+#define I2C_STAT_RRDY	(1 << 3)	/* Receive data ready */
+#define I2C_STAT_ARDY	(1 << 2)	/* Register access ready */
+#define I2C_STAT_NACK	(1 << 1)	/* No acknowledgment interrupt enable */
+#define I2C_STAT_AL	(1 << 0)	/* Arbitration lost interrupt enable */
+
+/* I2C Interrupt Vector Register (I2C_IV): */
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+#define I2C_INTCODE_MASK	7
+#define I2C_INTCODE_NONE	0
+#define I2C_INTCODE_AL		1	/* Arbitration lost */
+#define I2C_INTCODE_NAK		2	/* No acknowledgement/general call */
+#define I2C_INTCODE_ARDY	3	/* Register access ready */
+#define I2C_INTCODE_RRDY	4	/* Rcv data ready */
+#define I2C_INTCODE_XRDY	5	/* Xmit data ready */
+
+/* I2C Buffer Configuration Register (I2C_BUF): */
+
+#define I2C_BUF_RDMA_EN		(1 << 15)	/* Receive DMA channel enable */
+#define I2C_BUF_XDMA_EN		(1 << 7)	/* Transmit DMA channel enable */
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN	(1 << 15)	/* I2C module enable */
+#define I2C_CON_BE	(1 << 14)	/* Big endian mode */
+#define I2C_CON_STB	(1 << 11)	/* Start byte mode (master mode only) */
+#define I2C_CON_MST	(1 << 10)	/* Master/slave mode */
+#define I2C_CON_TRX	(1 << 9)	/* Transmitter/receiver mode (master mode only) */
+#define I2C_CON_XA	(1 << 8)	/* Expand address */
+#define I2C_CON_RM	(1 << 2)	/* Repeat mode (master mode only) */
+#define I2C_CON_STP	(1 << 1)	/* Stop condition (master mode only) */
+#define I2C_CON_STT	(1 << 0)	/* Start condition (master mode only) */
+
+/* I2C System Test Register (I2C_SYSTEST): */
+
+#define I2C_SYSTEST_ST_EN	(1 << 15)	/* System test enable */
+#define I2C_SYSTEST_FREE	(1 << 14)	/* Free running mode (on breakpoint) */
+#define I2C_SYSTEST_TMODE_MASK	(3 << 12)	/* Test mode select */
+#define I2C_SYSTEST_TMODE_SHIFT (12)		/* Test mode select */
+#define I2C_SYSTEST_SCL_I	(1 << 3)	/* SCL line sense input value */
+#define I2C_SYSTEST_SCL_O	(1 << 2)	/* SCL line drive output value */
+#define I2C_SYSTEST_SDA_I	(1 << 1)	/* SDA line sense input value */
+#define I2C_SYSTEST_SDA_O	(1 << 0)	/* SDA line drive output value */
+
+/*
+ * MMC/SD Host Controller Registers
+ */
+
+#define OMAP_MMC_CMD	 0xFFFB7800 /* MMC Command */
+#define OMAP_MMC_ARGL	 0xFFFB7804 /* MMC argument low */
+#define OMAP_MMC_ARGH	 0xFFFB7808 /* MMC argument high */
+#define OMAP_MMC_CON	 0xFFFB780C /* MMC system configuration */
+#define OMAP_MMC_STAT	 0xFFFB7810 /* MMC status */
+#define OMAP_MMC_IE	 0xFFFB7814 /* MMC system interrupt enable */
+#define OMAP_MMC_CTO	 0xFFFB7818 /* MMC command time-out */
+#define OMAP_MMC_DTO	 0xFFFB781C /* MMC data time-out */
+#define OMAP_MMC_DATA	 0xFFFB7820 /* MMC TX/RX FIFO data */
+#define OMAP_MMC_BLEN	 0xFFFB7824 /* MMC block length */
+#define OMAP_MMC_NBLK	 0xFFFB7828 /* MMC number of blocks */
+#define OMAP_MMC_BUF	 0xFFFB782C /* MMC buffer configuration */
+#define OMAP_MMC_SPI	 0xFFFB7830 /* MMC serial port interface */
+#define OMAP_MMC_SDIO	 0xFFFB7834 /* MMC SDIO mode configuration */
+#define OMAP_MMC_SYST	 0xFFFB7838 /* MMC system test */
+#define OMAP_MMC_REV	 0xFFFB783C /* MMC module version */
+#define OMAP_MMC_RSP0	 0xFFFB7840 /* MMC command response 0 */
+#define OMAP_MMC_RSP1	 0xFFFB7844 /* MMC command response 1 */
+#define OMAP_MMC_RSP2	 0xFFFB7848 /* MMC command response 2 */
+#define OMAP_MMC_RSP3	 0xFFFB784C /* MMC command response 3 */
+#define OMAP_MMC_RSP4	 0xFFFB7850 /* MMC command response 4 */
+#define OMAP_MMC_RSP5	 0xFFFB7854 /* MMC command response 5 */
+#define OMAP_MMC_RSP6	 0xFFFB7858 /* MMC command response 6 */
+#define OMAP_MMC_RSP7	 0xFFFB785C /* MMC command response 4 */
+
+/* MMC masks */
+
+#define OMAP_MMC_END_OF_CMD	(1 << 0)	/* End of command phase */
+#define OMAP_MMC_CARD_BUSY	(1 << 2)	/* Card enter busy state */
+#define OMAP_MMC_BLOCK_RS	(1 << 3)	/* Block received/sent */
+#define OMAP_MMC_EOF_BUSY	(1 << 4)	/* Card exit busy state */
+#define OMAP_MMC_DATA_TIMEOUT	(1 << 5)	/* Data response time-out */
+#define OMAP_MMC_DATA_CRC	(1 << 6)	/* Date CRC error */
+#define OMAP_MMC_CMD_TIMEOUT	(1 << 7)	/* Command response time-out */
+#define OMAP_MMC_CMD_CRC	(1 << 8)	/* Command CRC error */
+#define OMAP_MMC_A_FULL		(1 << 10)	/* Buffer almost full */
+#define OMAP_MMC_A_EMPTY	(1 << 11)	/* Buffer almost empty */
+#define OMAP_MMC_OCR_BUSY	(1 << 12)	/* OCR busy */
+#define OMAP_MMC_CARD_IRQ	(1 << 13)	/* Card IRQ received */
+#define OMAP_MMC_CARD_ERR	(1 << 14)	/* Card status error in response */
+
+/* 2.9.2 MPUI Interface Registers FFFE:C900 */
+
+#define MPUI_CTRL_REG		(volatile __u32 *)(0xfffec900)
+#define MPUI_DEBUG_ADDR		(volatile __u32 *)(0xfffec904)
+#define MPUI_DEBUG_DATA		(volatile __u32 *)(0xfffec908)
+#define MPUI_DEBUG_FLAG		(volatile __u16 *)(0xfffec90c)
+#define MPUI_STATUS_REG		(volatile __u16 *)(0xfffec910)
+#define MPUI_DSP_STATUS_REG	(volatile __u16 *)(0xfffec914)
+#define MPUI_DSP_BOOT_CONFIG	(volatile __u16 *)(0xfffec918)
+#define MPUI_DSP_API_CONFIG	(volatile __u16 *)(0xfffec91c)
+
+/* 2.9.6 Traffic Controller Memory Interface Registers: */
+#define OMAP_IMIF_PRIO_REG		0xfffecc00
+#define OMAP_EMIFS_PRIO_REG		0xfffecc04
+#define OMAP_EMIFF_PRIO_REG		0xfffecc08
+#define OMAP_EMIFS_CONFIG_REG		0xfffecc0c
+#define OMAP_EMIFS_CS0_CONFIG		0xfffecc10
+#define OMAP_EMIFS_CS1_CONFIG		0xfffecc14
+#define OMAP_EMIFS_CS2_CONFIG		0xfffecc18
+#define OMAP_EMIFS_CS3_CONFIG		0xfffecc1c
+#define OMAP_EMIFF_SDRAM_CONFIG		0xfffecc20
+#define OMAP_EMIFF_MRS			0xfffecc24
+#define OMAP_TIMEOUT1			0xfffecc28
+#define OMAP_TIMEOUT2			0xfffecc2c
+#define OMAP_TIMEOUT3			0xfffecc30
+#define OMAP_ENDIANISM			0xfffecc34
+
+/* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */
+#define OMAP_EMIFS_CONFIG_FR		(1 << 4)
+#define OMAP_EMIFS_CONFIG_PDE		(1 << 3)
+#define OMAP_EMIFS_CONFIG_PWD_EN	(1 << 2)
+#define OMAP_EMIFS_CONFIG_BM		(1 << 1)
+#define OMAP_EMIFS_CONFIG_WP		(1 << 0)
+
+/*
+ * Memory chunk set aside for the Framebuffer in SRAM
+ */
+#define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE
+
+
+/*
+ * DMA
+ */
+
+#define OMAP1510_DMA_BASE 0xFFFED800
+#define OMAP_DMA_BASE	  OMAP1510_DMA_BASE
+
+/* Global Register selection */
+#define NO_GLOBAL_DMA_ACCESS 0
+
+/* Channel select field
+ * NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc...
+ */
+#define LCD_CHANNEL 0xc
+
+/* Register Select Field (LCD) */
+#define DMA_LCD_CTRL		0
+#define DMA_LCD_TOP_F1_L	1
+#define DMA_LCD_TOP_F1_U	2
+#define DMA_LCD_BOT_F1_L	3
+#define DMA_LCD_BOT_F1_U	4
+
+#define LCD_FRAME_MODE		(1<<0)
+#define LCD_FRAME_IT_IE		(1<<1)
+#define LCD_BUS_ERROR_IT_IE	(1<<2)
+#define LCD_FRAME_1_IT_COND	(1<<3)
+#define LCD_FRAME_2_IT_COND	(1<<4)
+#define LCD_BUS_ERROR_IT_COND	(1<<5)
+#define LCD_SOURCE_IMIF		(1<<6)
+
+/*
+ * Real-Time Clock
+ */
+
+#define RTC_SECONDS		(volatile __u8 *)(OMAP1510_RTC_BASE + 0x00)
+#define RTC_MINUTES		(volatile __u8 *)(OMAP1510_RTC_BASE + 0x04)
+#define RTC_HOURS		(volatile __u8 *)(OMAP1510_RTC_BASE + 0x08)
+#define RTC_DAYS		(volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C)
+#define RTC_MONTHS		(volatile __u8 *)(OMAP1510_RTC_BASE + 0x10)
+#define RTC_YEARS		(volatile __u8 *)(OMAP1510_RTC_BASE + 0x14)
+#define RTC_CTRL		(volatile __u8 *)(OMAP1510_RTC_BASE + 0x40)
+
+
+/* ---------------------------------------------------------------------------
+ *  OMAP1510 Interrupt Handlers
+ * ---------------------------------------------------------------------------
+ *
+ */
+#define OMAP_IH1_BASE		0xfffecb00
+#define OMAP_IH2_BASE		0xfffe0000
+#define OMAP1510_ITR		0x0
+#define OMAP1510_MASK		0x4
+
+#define INTERRUPT_HANDLER_BASE	 OMAP_IH1_BASE
+#define INTERRUPT_INPUT_REGISTER OMAP1510_ITR
+#define INTERRUPT_MASK_REGISTER	 OMAP1510_MASK
+
+
+/* ---------------------------------------------------------------------------
+ *  OMAP1510 TIMERS
+ * ---------------------------------------------------------------------------
+ *
+ */
+
+#define OMAP1510_32kHz_TIMER_BASE 0xfffb9000
+
+/* 32k Timer Registers */
+#define TIMER32k_CR	0x08
+#define TIMER32k_TVR	0x00
+#define TIMER32k_TCR	0x04
+
+/* 32k Timer Control Register definition */
+#define TIMER32k_TSS	(1<<0)
+#define TIMER32k_TRB	(1<<1)
+#define TIMER32k_INT	(1<<2)
+#define TIMER32k_ARL	(1<<3)
+
+/* MPU Timer base addresses  */
+#define OMAP1510_MPUTIMER_BASE	0xfffec500
+#define OMAP1510_MPUTIMER_OFF	0x00000100
+
+#define OMAP1510_TIMER1_BASE	0xfffec500
+#define OMAP1510_TIMER2_BASE	0xfffec600
+#define OMAP1510_TIMER3_BASE	0xfffec700
+
+/* MPU Timer Registers */
+#define CNTL_TIMER	0
+#define LOAD_TIM	4
+#define READ_TIM	8
+
+/*  CNTL_TIMER register bits */
+#define MPUTIM_FREE		(1<<6)
+#define MPUTIM_CLOCK_ENABLE	(1<<5)
+#define MPUTIM_PTV_MASK		(0x7<<PTV_BIT)
+#define MPUTIM_PTV_BIT		2
+#define MPUTIM_AR		(1<<1)
+#define MPUTIM_ST		(1<<0)
+
+/* ---------------------------------------------------------------------------
+ *  OMAP1510 GPIO (SHARED)
+ * ---------------------------------------------------------------------------
+ *
+ */
+#define GPIO_DATA_INPUT_REG	(OMAP1510_GPIO_BASE + 0x0)
+#define GPIO_DATA_OUTPUT_REG	(OMAP1510_GPIO_BASE + 0x4)
+#define GPIO_DIR_CONTROL_REG	(OMAP1510_GPIO_BASE + 0x8)
+#define GPIO_INT_CONTROL_REG	(OMAP1510_GPIO_BASE + 0xc)
+#define GPIO_INT_MASK_REG	(OMAP1510_GPIO_BASE + 0x10)
+#define GPIO_INT_STATUS_REG	(OMAP1510_GPIO_BASE + 0x14)
+#define GPIO_PIN_CONTROL_REG	(OMAP1510_GPIO_BASE + 0x18)
+
+
+/* ---------------------------
+ * OMAP1510 MPUIO (ARM only)
+ *----------------------------
+ */
+#define OMAP1510_MPUIO_BASE	0xFFFB5000
+#define MPUIO_DATA_INPUT_REG	(OMAP1510_MPUIO_BASE + 0x0)
+#define MPUIO_DATA_OUTPUT_REG	(OMAP1510_MPUIO_BASE + 0x4)
+#define MPUIO_DIR_CONTROL_REG	(OMAP1510_MPUIO_BASE + 0x8)
+
+/* ---------------------------------------------------------------------------
+ *  OMAP1510 TIPB (only)
+ * ---------------------------------------------------------------------------
+ *
+ */
+#define TIPB_PUBLIC_CNTL_BASE		0xfffed300
+#define MPU_PUBLIC_TIPB_CNTL_REG	(TIPB_PUBLIC_CNTL_BASE + 0x8)
+#define TIPB_PRIVATE_CNTL_BASE		0xfffeca00
+#define MPU_PRIVATE_TIPB_CNTL_REG	(TIPB_PRIVATE_CNTL_BASE + 0x8)
+
+/*
+ * ---------------------------------------------------------------------------
+ *  OMAP1510 Camera Interface
+ * ---------------------------------------------------------------------------
+ */
+#define CAMERA_BASE		(IO_BASE + 0x6800)
+#define CAM_CTRLCLOCK_REG	(CAMERA_BASE + 0x00)
+#define CAM_IT_STATUS_REG	(CAMERA_BASE + 0x04)
+#define CAM_MODE_REG		(CAMERA_BASE + 0x08)
+#define CAM_STATUS_REG		(CAMERA_BASE + 0x0C)
+#define CAM_CAMDATA_REG		(CAMERA_BASE + 0x10)
+#define CAM_GPIO_REG		(CAMERA_BASE + 0x14)
+#define CAM_PEAK_CTR_REG	(CAMERA_BASE + 0x18)
+
+#if 0
+#ifndef __ASSEMBLY__
+typedef struct {
+	__u32 ctrlclock;
+	__u32 it_status;
+	__u32 mode;
+	__u32 status;
+	__u32 camdata;
+	__u32 gpio;
+	__u32 peak_counter;
+} camera_regs_t;
+#endif
+#endif
+
+/* CTRLCLOCK bit shifts */
+#define FOSCMOD_BIT	0
+#define FOSCMOD_MASK	(0x7 << FOSCMOD_BIT)
+#define	 FOSCMOD_12MHz	0x0
+#define	 FOSCMOD_6MHz	0x2
+#define	 FOSCMOD_9_6MHz 0x4
+#define	 FOSCMOD_24MHz	0x5
+#define	 FOSCMOD_8MHz	0x6
+#define POLCLK		(1<<3)
+#define CAMEXCLK_EN	(1<<4)
+#define MCLK_EN		(1<<5)
+#define DPLL_EN		(1<<6)
+#define LCLK_EN		(1<<7)
+
+/* IT_STATUS bit shifts */
+#define V_UP		(1<<0)
+#define V_DOWN		(1<<1)
+#define H_UP		(1<<2)
+#define H_DOWN		(1<<3)
+#define FIFO_FULL	(1<<4)
+#define DATA_XFER	(1<<5)
+
+/* MODE bit shifts */
+#define CAMOSC		(1<<0)
+#define IMGSIZE_BIT	1
+#define IMGSIZE_MASK	(0x3 << IMGSIZE_BIT)
+#define	 IMGSIZE_CIF	(0x0 << IMGSIZE_BIT)	/* 352x288 */
+#define	 IMGSIZE_QCIF	(0x1 << IMGSIZE_BIT)	/* 176x144 */
+#define	 IMGSIZE_VGA	(0x2 << IMGSIZE_BIT)	/* 640x480 */
+#define	 IMGSIZE_QVGA	(0x3 << IMGSIZE_BIT)	/* 320x240 */
+#define ORDERCAMD	(1<<3)
+#define EN_V_UP		(1<<4)
+#define EN_V_DOWN	(1<<5)
+#define EN_H_UP		(1<<6)
+#define EN_H_DOWN	(1<<7)
+#define EN_DMA		(1<<8)
+#define THRESHOLD	(1<<9)
+#define THRESHOLD_BIT	9
+#define THRESHOLD_MASK	(0x7f<<9)
+#define EN_NIRQ		(1<<16)
+#define EN_FIFO_FULL	(1<<17)
+#define RAZ_FIFO	(1<<18)
+
+/* STATUS bit shifts */
+#define VSTATUS		(1<<0)
+#define HSTATUS		(1<<1)
+
+/* GPIO bit shifts */
+#define CAM_RST		(1<<0)
+
+
+/*********************
+ * Watchdog timer.
+ *********************/
+#define WDTIM_BASE	0xfffec800
+#define WDTIM_CONTROL	(WDTIM_BASE+0x00)
+#define WDTIM_LOAD	(WDTIM_BASE+0x04)
+#define WDTIM_READ	(WDTIM_BASE+0x04)
+#define WDTIM_MODE	(WDTIM_BASE+0x08)
+
+/* Values to write to mode register to disable the watchdog function. */
+#define DISABLE_SEQ1	0xF5
+#define DISABLE_SEQ2	0xA0
+
+/* WDTIM_CONTROL bit definitions. */
+#define WDTIM_CONTROL_ST	BIT7
+
+
+/* ---------------------------------------------------------------------------
+ *  Differentiating processor versions for those who care.
+ * ---------------------------------------------------------------------------
+ *
+ */
+#define OMAP1509 0
+#define OMAP1510 1
+
+#define OMAP1510_ID_CODE_REG 0xfffed404
+
+#ifndef __ASSEMBLY__
+int cpu_type(void);
+#endif
+
+/*
+ * EVM Implementation Specifics.
+ *
+ * *** NOTE ***
+ * Any definitions in these files should be prefixed by an identifier -
+ * eg. OMAP1510P1_FLASH0_BASE .
+ *
+ */
+#ifdef CONFIG_OMAP_INNOVATOR
+#include "innovator.h"
+#endif
+
+#ifdef CONFIG_OMAP_1510P1
+#include "omap1510p1.h"
+#endif
+
+/*****************************************************************************/
+
+#define CLKGEN_RESET_BASE (0xfffece00)
+#define ARM_CKCTL	(volatile __u16 *)(CLKGEN_RESET_BASE + 0x0)
+#define ARM_IDLECT1	(volatile __u16 *)(CLKGEN_RESET_BASE + 0x4)
+#define ARM_IDLECT2	(volatile __u16 *)(CLKGEN_RESET_BASE + 0x8)
+#define ARM_EWUPCT	(volatile __u16 *)(CLKGEN_RESET_BASE + 0xC)
+#define ARM_RSTCT1	(volatile __u16 *)(CLKGEN_RESET_BASE + 0x10)
+#define ARM_RSTCT2	(volatile __u16 *)(CLKGEN_RESET_BASE + 0x14)
+#define ARM_SYSST	(volatile __u16 *)(CLKGEN_RESET_BASE + 0x18)
+
+
+#define CK_CLKIN	12 /* MHz */
+#define CK_RATEF	1
+#define CK_IDLEF	2
+#define CK_ENABLEF	4
+#define CK_SELECTF	8
+#ifndef __ASSEMBLER__
+#define CK_DPLL1	((volatile __u16 *)0xfffecf00)
+#else
+#define CK_DPLL1 (0xfffecf00)
+#endif
+#define SETARM_IDLE_SHIFT
+
+/* ARM_CKCTL bit shifts */
+#define PERDIV		0
+#define LCDDIV		2
+#define ARMDIV		4
+#define DSPDIV		6
+#define TCDIV		8
+#define DSPMMUDIV	10
+#define ARM_TIMXO	12
+#define EN_DSPCK	13
+#define ARM_INTHCK_SEL	14 /* REVISIT -- where is this used? */
+
+#define ARM_CKCTL_RSRVD_BIT15		(1 << 15)
+#define ARM_CKCTL_ARM_INTHCK_SEL	(1 << 14)
+#define ARM_CKCTL_EN_DSPCK		(1 << 13)
+#define ARM_CKCTL_ARM_TIMXO		(1 << 12)
+#define ARM_CKCTL_DSPMMU_DIV1		(1 << 11)
+#define ARM_CKCTL_DSPMMU_DIV2		(1 << 10)
+#define ARM_CKCTL_TCDIV1		(1 << 9)
+#define ARM_CKCTL_TCDIV2		(1 << 8)
+#define ARM_CKCTL_DSPDIV1		(1 << 7)
+#define ARM_CKCTL_DSPDIV0		(1 << 6)
+#define ARM_CKCTL_ARMDIV1		(1 << 5)
+#define ARM_CKCTL_ARMDIV0		(1 << 4)
+#define ARM_CKCTL_LCDDIV1		(1 << 3)
+#define ARM_CKCTL_LCDDIV0		(1 << 2)
+#define ARM_CKCTL_PERDIV1		(1 << 1)
+#define ARM_CKCTL_PERDIV0		(1 << 0)
+
+/* ARM_IDLECT1 bit shifts */
+#define IDLWDT_ARM	0
+#define IDLXORP_ARM	1
+#define IDLPER_ARM	2
+#define IDLLCD_ARM	3
+#define IDLLB_ARM	4
+#define IDLHSAB_ARM	5
+#define IDLIF_ARM	6
+#define IDLDPLL_ARM	7
+#define IDLAPI_ARM	8
+#define IDLTIM_ARM	9
+#define SETARM_IDLE	11
+
+/* ARM_IDLECT2 bit shifts */
+#define EN_WDTCK	0
+#define EN_XORPCK	1
+#define EN_PERCK	2
+#define EN_LCDCK	3
+#define EN_LBCK		4
+#define EN_HSABCK	5
+#define EN_APICK	6
+#define EN_TIMCK	7
+#define DMACK_REQ	8
+#define EN_GPIOCK	9
+#define EN_LBFREECK	10
+
+#define ARM_RSTCT1_SW_RST	(1 << 3)
+#define ARM_RSTCT1_DSP_RST	(1 << 2)
+#define ARM_RSTCT1_DSP_EN	(1 << 1)
+#define ARM_RSTCT1_ARM_RST	(1 << 0)
+
+/* ARM_RSTCT2 bit shifts */
+#define EN_PER		0
+
+#define ARM_SYSST_RSRVD_BIT15	(1 << 15)
+#define ARM_SYSST_RSRVD_BIT14	(1 << 14)
+#define ARM_SYSST_CLOCK_SELECT2 (1 << 13)
+#define ARM_SYSST_CLOCK_SELECT1 (1 << 12)
+#define ARM_SYSST_CLOCK_SELECT0 (1 << 11)
+#define ARM_SYSST_RSRVD_BIT10	(1 << 10)
+#define ARM_SYSST_RSRVD_BIT9	(1 << 9)
+#define ARM_SYSST_RSRVD_BIT8	(1 << 8)
+#define ARM_SYSST_RSRVD_BIT7	(1 << 7)
+#define ARM_SYSST_IDLE_DSP	(1 << 6)
+#define ARM_SYSST_POR		(1 << 5)
+#define ARM_SYSST_EXT_RST	(1 << 4)
+#define ARM_SYSST_ARM_MCRST	(1 << 3)
+#define ARM_SYSST_ARM_WDRST	(1 << 2)
+#define ARM_SYSST_GLOB_SWRST	(1 << 1)
+#define ARM_SYSST_DSP_WDRST	(1 << 0)
+
+/* Table 15-23. DPLL Control Registers: */
+#define DPLL_CTL_REG		(volatile __u16 *)(0xfffecf00)
+
+/* Table 15-24. Control Register (CTL_REG): */
+
+#define DPLL_CTL_REG_IOB		(1 << 13)
+#define DPLL_CTL_REG_PLL_MULT		Fld(5,0)
+
+/*****************************************************************************/
+
+/* OMAP INTERRUPT REGISTERS */
+#define IRQ_ITR			0x00
+#define IRQ_MIR			0x04
+#define IRQ_SIR_IRQ		0x10
+#define IRQ_SIR_FIQ		0x14
+#define IRQ_CONTROL_REG		0x18
+#define IRQ_ISR			0x9c
+#define IRQ_ILR0		0x1c
+
+#define REG_IHL1_MIR  (OMAP_IH1_BASE+IRQ_MIR)
+#define REG_IHL2_MIR  (OMAP_IH2_BASE+IRQ_MIR)
+
+/* INTERRUPT LEVEL REGISTER BITS */
+#define ILR_PRIORITY_MASK	(0x3c)
+#define ILR_PRIORITY_SHIFT	(2)
+#define ILR_LEVEL_TRIGGER	(1<<1)
+#define ILR_FIQ			(1<<0)
+
+#define IRQ_LEVEL_INT		1
+#define IRQ_EDGE_INT		0
+
+/* Macros to access registers */
+#define outb(v,p) *(volatile u8 *) (p) = v
+#define outw(v,p) *(volatile u16 *) (p) = v
+#define outl(v,p) *(volatile u32 *) (p) = v
+
+#define inb(p)	*(volatile u8 *) (p)
+#define inw(p)	*(volatile u16 *) (p)
+#define inl(p)	*(volatile u32 *) (p)
diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h
new file mode 100755
index 0000000..016d3d8
--- /dev/null
+++ b/include/configs/omap1510inn.h
@@ -0,0 +1,182 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM925T	1		/* This is an arm925t CPU	*/
+#define CONFIG_OMAP	1		/* in a TI OMAP core	*/
+#define CONFIG_OMAP1510 1		/* which is in a 1510 (helen) */
+#define CONFIG_INNOVATOROMAP1510 1	/*	a Innovator Board  */
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ	12000000	/* the OMAP1510 Innovator has 12MHz input clock */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+/*
+#define CONFIG_DRIVER_SMC9196
+#define CONFIG_SMC9196_BASE 0x08000300
+#define CONFIG_SMC9196_EXT_PHY
+*/
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE 0x08000300
+#define CONFIG_LAN91C96_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	(-4)
+#define CFG_NS16550_CLK		(CONFIG_SYS_CLK_FREQ)	/* can be 12M/32Khz or 48Mhz  */
+#define CFG_NS16550_COM1	0xfffb0000		/* uart1, bluetooth uart on helen */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		1	/* we use SERIAL 1 on OMAP1510 Innovator */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_DHCP)
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#include <configs/omap1510.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=bootp"
+#define CONFIG_BOOTCOMMAND	"bootp;tftp;bootm"
+#define CFG_AUTOLOAD		"n"		/* No autoload */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT		"OMAP1510 Innovator # " /* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x10000000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x12000000	/* 32 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0x10000000	/* default load address */
+
+/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
+ * This time is further subdivided by a local divisor.
+ */
+#define CFG_TIMERBASE	0xFFFEC500	    /* use timer 1 */
+#define CFG_PVT		7		    /* 2^(pvt+1), divide by 256 */
+#define CFG_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x10000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define PHYS_FLASH_SIZE		0x01000000 /* 16MB */
+#define PHYS_FLASH_SECT_SIZE	(128*1024)	/* Size of a sector (128kB) */
+#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + PHYS_FLASH_SECT_SIZE)
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE	/* Monitor at beginning of flash */
+#define CFG_MONITOR_LEN		PHYS_FLASH_SECT_SIZE	/* Reserve 1 sector */
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE }
+
+/*-----------------------------------------------------------------------
+ * FLASH driver setup
+ */
+#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION	1	/* Use hardware sector protection */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE	/* Total Size of Environment Sector */
+#define CFG_ENV_SIZE		CFG_ENV_SECT_SIZE
+#define CFG_ENV_OFFSET		( CFG_MONITOR_BASE + CFG_MONITOR_LEN )	/* Environment after Monitor */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h
new file mode 100755
index 0000000..c6ca689
--- /dev/null
+++ b/include/configs/omap1610h2.h
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuration settings for the TI OMAP 1610 H2 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP1610		1	/* which is in a 1610 */
+#define CONFIG_H2_OMAP1610	1	/* on an H2 Board */
+#define CONFIG_MACH_OMAP_H2		/* Select board mach-type */
+
+/* input clock of PLL */
+/* the OMAP1610 H2 has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ	12000000
+
+#undef CONFIG_USE_IRQ	/* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE 0x04000300
+#define CONFIG_LAN91C96_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	(-4)
+#define CFG_NS16550_CLK	(48000000)		/* can be 12M/32Khz or 48Mhz */
+#define CFG_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1	1	/* we use SERIAL 1 on OMAP1610 H2 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE	115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_DHCP)
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#include <configs/omap1510.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS	"console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=dhcp"
+#define CONFIG_BOOTCOMMAND      "bootp;tftp;bootm"
+#define CFG_AUTOLOAD            "n"             /* No autoload */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	1	/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP	/* undef to save memory */
+#define CFG_PROMPT	"OMAP1610 H2 # "	/* Monitor Command Prompt */
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS	16		/* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	0x10000000	/* memtest works on */
+#define CFG_MEMTEST_END	0x12000000	/* 32 MB in DRAM */
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR	0x10000000	/* default load address */
+
+/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
+ * DPLL1. This time is further subdivided by a local divisor.
+ */
+#define CFG_TIMERBASE	0xFFFEC500	/* use timer 1 */
+#define CFG_PVT	7	/* 2^(pvt+1), divide by 256 */
+#define CFG_HZ	((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
+
+#define PHYS_FLASH_1_BM1	0x00000000	/* Flash Bank #1 if booting from flash */
+#define PHYS_FLASH_1_BM0	0x0C000000	/* Flash Bank #1 if booting from RAM */
+
+#ifdef CONFIG_CS_AUTOBOOT			/* Determine CS assignment in runtime */
+
+#ifndef __ASSEMBLY__
+extern unsigned long omap_flash_base;		/* set in flash__init */
+#endif
+#define CFG_FLASH_BASE		omap_flash_base
+
+#elif defined(CONFIG_CS0_BOOT)
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1_BM0
+
+#else
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1_BM1
+
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define PHYS_FLASH_SIZE	0x02000000	/* 32MB */
+#define CFG_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */
+/* addr of environment */
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + 0x020000)
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE	0x20000	/* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET	0x20000	/* environment starts here */
+
+#endif							/* __CONFIG_H */
diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h
new file mode 100755
index 0000000..f28ede0
--- /dev/null
+++ b/include/configs/omap1610inn.h
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core  */
+#define CONFIG_OMAP	1			/* in a TI OMAP core    */
+#define CONFIG_OMAP1610	1		/* which is in a 1610  */
+#define CONFIG_INNOVATOROMAP1610	1	/*  a Innovator Board  */
+#define CONFIG_MACH_OMAP_INNOVATOR	/* Select board mach-type */
+
+/* input clock of PLL */
+/* the OMAP1610 Innovator has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ	12000000
+
+#undef CONFIG_USE_IRQ	/* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+/*
+*/
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE 0x04000300
+#define CONFIG_LAN91C96_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	(-4)
+#define CFG_NS16550_CLK		(48000000)	/* can be 12M/32Khz or 48Mhz */
+#define CFG_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart on helen */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		1		/* we use SERIAL 1 on OMAP1610 Innovator */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE	115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_DHCP)
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#include <configs/omap1510.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS	"mem=32M console=ttyS0,115200n8 noinitrd \
+				root=/dev/nfs rw nfsroot=157.87.82.48:\
+				/home/a0875451/mwd/myfs/target ip=dhcp"
+#define CONFIG_NETMASK	255.255.254.0	/* talk on MY local net */
+#define CONFIG_IPADDR	156.117.97.156	/* static IP I currently own */
+#define CONFIG_SERVERIP	156.117.97.139	/* current IP of my dev pc */
+#define CONFIG_BOOTFILE	"uImage"	/* file to load */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	1	/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP	/* undef to save memory     */
+#define CFG_PROMPT	"OMAP1610 Innovator # "	/* Monitor Command Prompt   */
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
+/* Print Buffer Size */
+#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS	16		/* max number of command args   */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START	0x10000000	/* memtest works on */
+#define CFG_MEMTEST_END	0x12000000	/* 32 MB in DRAM    */
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR	0x10000000	/* default load address */
+
+/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
+ * DPLL1. This time is further subdivided by a local divisor.
+ */
+#define CFG_TIMERBASE	0xFFFEC500	/* use timer 1 */
+#define CFG_PVT	7	/* 2^(pvt+1), divide by 256 */
+#define CFG_HZ	((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
+
+#define PHYS_FLASH_1_BM1	0x00000000	/* Flash Bank #1 if booting from flash */
+#define PHYS_FLASH_1_BM0	0x0C000000	/* Flash Bank #1 if booting from RAM */
+
+#ifdef CONFIG_CS_AUTOBOOT			/* Determine CS assignment in runtime */
+
+#ifndef __ASSEMBLY__
+extern unsigned long omap_flash_base;		/* set in flash__init */
+#endif
+#define CFG_FLASH_BASE		omap_flash_base
+
+#elif defined(CONFIG_CS0_BOOT)
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1_BM0
+
+#else
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1_BM1
+
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define PHYS_FLASH_SIZE	0x02000000	/* 32MB */
+#define CFG_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */
+/* addr of environment */
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + 0x020000)
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE	0x20000	/* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET	0x20000	/* environment starts here  */
+
+#endif							/* __CONFIG_H */
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
new file mode 100755
index 0000000..12252ac
--- /dev/null
+++ b/include/configs/omap2420h4.h
@@ -0,0 +1,293 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the 242x TI H4 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARM1136           1    /* This is an arm1136 CPU core */
+#define CONFIG_OMAP              1    /* in a TI OMAP core */
+#define CONFIG_OMAP2420	         1    /* which is in a 2420 */
+#define CONFIG_OMAP2420H4        1    /* and on a H4 board */
+/*#define CONFIG_APTIX           1    #* define if on APTIX test chip */
+/*#define CONFIG_VIRTIO          1    #* Using Virtio simulator */
+
+/* Clock config to target*/
+#define PRCM_CONFIG_II	1
+/* #define PRCM_CONFIG_III		1 */
+
+#include <asm/arch/omap2420.h>        /* get chip and board defs */
+
+/* On H4, NOR and NAND flash are mutual exclusive.
+   Define this if you want to use NAND
+ */
+/*#define CFG_NAND_BOOT */
+
+#ifdef CONFIG_APTIX
+#define V_SCLK                   1500000
+#else
+#define V_SCLK                   12000000
+#endif
+
+/* input clock of PLL */
+/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
+#define CONFIG_SYS_CLK_FREQ      V_SCLK
+
+#undef CONFIG_USE_IRQ                 /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG       1    /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG        1
+#define CONFIG_REVISION_TAG      1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_ENV_SIZE             SZ_128K     /* Total Size of Environment Sector */
+#define CFG_MALLOC_LEN           (CFG_ENV_SIZE + SZ_128K)
+#define CFG_GBL_DATA_SIZE        128  /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * SMC91c96 Etherent
+ */
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE     (H4_CS1_BASE+0x300)
+#define CONFIG_LAN91C96_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#ifdef CONFIG_APTIX
+#define V_NS16550_CLK            (6000000)   /* 6MHz in current MaxSet */
+#else
+#define V_NS16550_CLK            (48000000)  /* 48MHz (APLL96/2) */
+#endif
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE     (-4)
+#define CFG_NS16550_CLK          V_NS16550_CLK   /* 3MHz (1.5MHz*2) */
+#define CFG_NS16550_COM1         OMAP2420_UART1
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1           1    /* UART1 on H4 */
+
+  /*
+   * I2C configuration
+   */
+#define CONFIG_HARD_I2C
+#define CFG_I2C_SPEED          100000
+#define CFG_I2C_SLAVE          1
+#define CONFIG_DRIVER_OMAP24XX_I2C
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX        1
+#define CONFIG_BAUDRATE          115200
+#define CFG_BAUDRATE_TABLE       {9600, 19200, 38400, 57600, 115200}
+
+#ifdef CFG_NAND_BOOT
+#define CONFIG_COMMANDS          (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2)
+#else
+#define CONFIG_COMMANDS          ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT)
+#endif
+#define CONFIG_BOOTP_MASK        CONFIG_BOOTP_DEFAULT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ *  Board NAND Info.
+ */
+#define CFG_NAND_ADDR 0x04000000  /* physical address to access nand at CS0*/
+
+#define CFG_MAX_NAND_DEVICE 1	/* Max number of NAND devices */
+#define SECTORSIZE          512
+
+#define ADDR_COLUMN         1
+#define ADDR_PAGE           2
+#define ADDR_COLUMN_PAGE    3
+
+#define NAND_ChipID_UNKNOWN 0x00
+#define NAND_MAX_FLOORS     1
+#define NAND_MAX_CHIPS      1
+
+#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
+#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
+#define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
+#define NAND_WAIT_READY(nand)  udelay(10)
+
+#define NAND_NO_RB          1
+
+#define CFG_NAND_WP
+#define NAND_WP_OFF()  do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
+#define NAND_WP_ON()  do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
+
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+
+#define CONFIG_BOOTDELAY         3
+
+#ifdef NFS_BOOT_DEFAULTS
+#define CONFIG_BOOTARGS	         "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
+#else
+#define CONFIG_BOOTARGS          "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
+#endif
+
+#define CONFIG_NETMASK           255.255.254.0
+#define CONFIG_IPADDR            128.247.77.90
+#define CONFIG_SERVERIP          128.247.77.158
+#define CONFIG_BOOTFILE          "uImage"
+
+/*
+ * Miscellaneous configurable options
+ */
+#ifdef CONFIG_APTIX
+#define V_PROMPT                 "OMAP2420 Aptix # "
+#else
+#define V_PROMPT                 "OMAP242x H4 # "
+#endif
+
+#define CFG_LONGHELP             /* undef to save memory */
+#define CFG_PROMPT               V_PROMPT
+#define CFG_CBSIZE               256  /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE               (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS              16          /* max number of command args */
+#define CFG_BARGSIZE             CFG_CBSIZE  /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START        (OMAP2420_SDRC_CS0)  /* memtest works on */
+#define CFG_MEMTEST_END          (OMAP2420_SDRC_CS0+SZ_31M)
+
+#undef	CFG_CLKS_IN_HZ           /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR            (OMAP2420_SDRC_CS0) /* default load address */
+
+/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#ifdef CONFIG_APTIX
+#define V_PVT                    3
+#else
+#define V_PVT                    7  /* use with 12MHz/128 */
+#endif
+
+#define CFG_TIMERBASE            OMAP2420_GPT2
+#define CFG_PVT                  V_PVT  /* 2^(pvt+1) */
+#define CFG_HZ	                 ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE         SZ_128K /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ     SZ_4K   /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ     SZ_4K   /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS     2                 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1             OMAP2420_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE        SZ_32M            /* at least 32 meg */
+#define PHYS_SDRAM_2             OMAP2420_SDRC_CS1
+
+#define PHYS_FLASH_SECT_SIZE     SZ_128K
+#define PHYS_FLASH_1             H4_CS0_BASE	   /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE_1        SZ_32M
+#define PHYS_FLASH_2             (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
+#define PHYS_FLASH_SIZE_2        SZ_32M
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE           PHYS_FLASH_1
+#define CFG_MAX_FLASH_BANKS      2           /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT       (259)	     /* max number of sectors on one chip */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE /* Monitor at beginning of flash */
+#define CFG_MONITOR_LEN		SZ_128K      /* Reserve 1 sector */
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 }
+
+#ifdef CFG_NAND_BOOT
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_OFFSET	0x80000	/* environment starts here  */
+#else
+#define CFG_ENV_ADDR             (CFG_FLASH_BASE + SZ_128K)
+#define	CFG_ENV_IS_IN_FLASH      1
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_OFFSET	( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
+#endif
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION	1	/* Use hardware sector protection */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT     (100*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT     (100*CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_JFFS2_MEM_NAND
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor1"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor1=omap2420-1"
+#define MTDPARTS_DEFAULT	"mtdparts=omap2420-1:-(jffs2)"
+*/
+
+#endif							/* __CONFIG_H */
diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h
new file mode 100755
index 0000000..605563a
--- /dev/null
+++ b/include/configs/omap5912osk.h
@@ -0,0 +1,169 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core  */
+#define CONFIG_OMAP	1			/* in a TI OMAP core    */
+#define CONFIG_OMAP1610	1		/* 5912 is same as 1610  */
+#define CONFIG_OSK_OMAP5912	1	/*  a OSK Board  */
+
+/* input clock of PLL */
+/* the OMAP5912 OSK has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ	12000000
+
+#undef CONFIG_USE_IRQ	/* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+
+/*
+ * Hardware drivers
+ */
+/*
+*/
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE 0x04800300
+#define CONFIG_LAN91C96_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	(-4)
+#define CFG_NS16550_CLK	(48000000)	/* can be 12M/32Khz or 48Mhz */
+#define CFG_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart
+						on helen */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1	1	/* we use SERIAL 1 on OMAP5912 OSK */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE	115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_DHCP)
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+#include <configs/omap1510.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS	"mem=32M console=ttyS0,115200n8 noinitrd \
+				root=/dev/nfs rw nfsroot=157.87.82.48:\
+				/home/mwd/myfs/target ip=dhcp"
+#define CONFIG_NETMASK	255.255.254.0	/* talk on MY local net */
+#define CONFIG_IPADDR	156.117.97.156	/* static IP I currently own */
+#define CONFIG_SERVERIP	156.117.97.139	/* current IP of my dev pc */
+#define CONFIG_BOOTFILE	"uImage"	/* file to load */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	1	/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP	/* undef to save memory     */
+#define CFG_PROMPT	"OMAP5912 OSK # "	/* Monitor Command Prompt   */
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
+/* Print Buffer Size */
+#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS	16		/* max number of command args   */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START	0x10000000	/* memtest works on */
+#define CFG_MEMTEST_END	0x12000000	/* 32 MB in DRAM    */
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR	0x10000000	/* default load address */
+
+/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
+ * DPLL1. This time is further subdivided by a local divisor.
+ */
+#define CFG_TIMERBASE	0xFFFEC500	/* use timer 1 */
+#define CFG_PVT	7	/* 2^(pvt+1), divide by 256 */
+#define CFG_HZ	((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1	0x10000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
+
+#define PHYS_FLASH_1	0x00000000	/* Flash Bank #1 */
+
+#define CFG_FLASH_BASE	PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define PHYS_FLASH_SIZE	0x02000000	/* 32MB */
+#define CFG_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */
+/* addr of environment */
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + 0x020000)
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE	0x20000	/* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET	0x20000	/* environment starts here  */
+
+#endif							/* __CONFIG_H */
diff --git a/include/configs/omap730.h b/include/configs/omap730.h
new file mode 100755
index 0000000..03abcb3
--- /dev/null
+++ b/include/configs/omap730.h
@@ -0,0 +1,264 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   OMAP730 hardware map
+ *
+ * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
+ * Author: MPC-Data Limited
+ *	   Dave Peverley
+ *
+ *  This program is free software; you can redistribute	 it and/or modify it
+ *  under  the terms of	 the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the	License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED	  ``AS	IS'' AND   ANY	EXPRESS OR IMPLIED
+ *  WARRANTIES,	  INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO	EVENT  SHALL   THE AUTHOR  BE	 LIABLE FOR ANY	  DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED	  TO, PROCUREMENT OF  SUBSTITUTE GOODS	OR SERVICES; LOSS OF
+ *  USE, DATA,	OR PROFITS; OR	BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN	 CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __INCLUDED_OMAP730_H
+#define __INCLUDED_OMAP730_H
+
+#include <asm/arch/sizes.h>
+
+/***************************************************************************
+ * OMAP730 Configuration Registers
+ **************************************************************************/
+
+#define PERSEUS2_MPU_DEV_ID               ((unsigned int)(0xFFFE1000))
+#define PERSEUS2_GSM_DEV_ID0              ((unsigned int)(0xFFFE1000))
+#define PERSEUS2_GDM_DEV_ID1              ((unsigned int)(0xFFFE1002))
+#define DSP_CONF                          ((unsigned int)(0xFFFE1004))
+#define PERSEUS2_MPU_DIE_ID0              ((unsigned int)(0xFFFE1008))
+#define GSM_ASIC_CONF                     ((unsigned int)(0xFFFE1008))
+#define PERSEUS2_MPU_DIE_ID1              ((unsigned int)(0xFFFE100C))
+#define PERSEUS2_MODE1                    ((unsigned int)(0xFFFE1010))
+#define PERSEUS2_GSM_DIE_ID0              ((unsigned int)(0xFFFE1010))
+#define PERSEUS2_GSM_DIE_ID1              ((unsigned int)(0xFFFE1012))
+#define PERSEUS2_MODE2                    ((unsigned int)(0xFFFE1014))
+#define PERSEUS2_GSM_DIE_ID2              ((unsigned int)(0xFFFE1014))
+#define PERSEUS2_GSM_DIE_ID3              ((unsigned int)(0xFFFE1016))
+#define PERSEUS2_ANALOG_CELLS_CONF        ((unsigned int)(0xFFFE1018))
+#define SPECCTL                           ((unsigned int)(0xFFFE101C))
+#define SPARE1                            ((unsigned int)(0xFFFE1020))
+#define SPARE2                            ((unsigned int)(0xFFFE1024))
+#define GSM_PBG_IRQ                       ((unsigned int)(0xFFFE1028))
+#define DMA_REQ_CONF                      ((unsigned int)(0xFFFE1030))
+#define PE_CONF_NO_DUAL                   ((unsigned int)(0xFFFE1060))
+#define PERSEUS2_IO_CONF0                 ((unsigned int)(0xFFFE1070))
+#define PERSEUS2_IO_CONF1                 ((unsigned int)(0xFFFE1074))
+#define PERSEUS2_IO_CONF2                 ((unsigned int)(0xFFFE1078))
+#define PERSEUS2_IO_CONF3                 ((unsigned int)(0xFFFE107C))
+#define PERSEUS2_IO_CONF4                 ((unsigned int)(0xFFFE1080))
+#define PERSEUS2_IO_CONF5                 ((unsigned int)(0xFFFE1084))
+#define PERSEUS2_IO_CONF6                 ((unsigned int)(0xFFFE1088))
+#define PERSEUS2_IO_CONF7                 ((unsigned int)(0xFFFE108C))
+#define PERSEUS2_IO_CONF8                 ((unsigned int)(0xFFFE1090))
+#define PERSEUS2_IO_CONF9                 ((unsigned int)(0xFFFE1094))
+#define PERSEUS2_IO_CONF10                ((unsigned int)(0xFFFE1098))
+#define PERSEUS2_IO_CONF11                ((unsigned int)(0xFFFE109C))
+#define PERSEUS2_IO_CONF12                ((unsigned int)(0xFFFE10A0))
+#define PERSEUS2_IO_CONF13                ((unsigned int)(0xFFFE10A4))
+#define PERSEUS_PCC_CONF_REG              ((unsigned int)(0xFFFE10B4))
+#define BIST_STATUS_INTERNAL              ((unsigned int)(0xFFFE10B8))
+#define BIST_CONTROL                      ((unsigned int)(0xFFFE10C0))
+#define BOOT_ROM_REG                      ((unsigned int)(0xFFFE10C4))
+#define PRODUCTION_ID_REG                 ((unsigned int)(0xFFFE10C8))
+#define BIST_SECROM_SIGNATURE1_INTERNAL   ((unsigned int)(0xFFFE10D0))
+#define BIST_SECROM_SIGNATURE2_INTERNAL   ((unsigned int)(0xFFFE10D4))
+#define BIST_CONTROL_2                    ((unsigned int)(0xFFFE10D8))
+#define DEBUG1                            ((unsigned int)(0xFFFE10E0))
+#define DEBUG2                            ((unsigned int)(0xFFFE10E4))
+#define DEBUG_DMA_IRQ                     ((unsigned int)(0xFFFE10E8))
+
+/***************************************************************************
+ * OMAP730 EMIFS Registers                                       (TRM 2.5.7)
+ **************************************************************************/
+
+#define TCMIF_BASE                 0xFFFECC00
+
+#define EMIFS_LRUREG               (TCMIF_BASE + 0x04)
+#define EMIFS_CONFIG               (TCMIF_BASE + 0x0C)
+#define FLASH_CFG_0                (TCMIF_BASE + 0x10)
+#define FLASH_CFG_1                (TCMIF_BASE + 0x14)
+#define FLASH_CFG_2                (TCMIF_BASE + 0x18)
+#define FLASH_CFG_3                (TCMIF_BASE + 0x1C)
+#define FL_CFG_DYN_WAIT            (TCMIF_BASE + 0x40)
+#define EMIFS_TIMEOUT1_REG         (TCMIF_BASE + 0x28)
+#define EMIFS_TIMEOUT2_REG         (TCMIF_BASE + 0x2C)
+#define EMIFS_TIMEOUT3_REG         (TCMIF_BASE + 0x30)
+#define EMIFS_ABORT_ADDR           (TCMIF_BASE + 0x44)
+#define EMIFS_ABORT_TYPE           (TCMIF_BASE + 0x48)
+#define EMIFS_ABORT_TOUT           (TCMIF_BASE + 0x4C)
+#define FLASH_ACFG_0_1             (TCMIF_BASE + 0x50)
+#define FLASH_ACFG_1_1             (TCMIF_BASE + 0x54)
+#define FLASH_ACFG_2_1             (TCMIF_BASE + 0x58)
+#define FLASH_ACFG_3_1             (TCMIF_BASE + 0x5C)
+
+/***************************************************************************
+ * OMAP730 Interrupt handlers
+ **************************************************************************/
+
+#define OMAP_IH1_BASE		0xFFFECB00     /* MPU Level 1 IRQ handler */
+#define OMAP_IH2_BASE           0xfffe0000
+
+/***************************************************************************
+ * OMAP730 Timers
+ *
+ * There are three general purpose OS timers in the 730 that can be
+ * configured in autoreload or one-shot modes.
+ **************************************************************************/
+
+#define OMAP730_32kHz_TIMER_BASE  0xFFFB9000
+
+/* 32k Timer Registers */
+#define TIMER32k_CR               0x08
+#define TIMER32k_TVR              0x00
+#define TIMER32k_TCR              0x04
+
+/* 32k Timer Control Register definition */
+#define TIMER32k_TSS              (1<<0)
+#define TIMER32k_TRB              (1<<1)
+#define TIMER32k_INT              (1<<2)
+#define TIMER32k_ARL              (1<<3)
+
+/* MPU Timer base addresses  */
+#define OMAP730_MPUTIMER_BASE	0xfffec500
+#define OMAP730_MPUTIMER_OFF	0x00000100
+
+#define OMAP730_TIMER1_BASE	0xFFFEC500
+#define OMAP730_TIMER2_BASE	0xFFFEC600
+#define OMAP730_TIMER3_BASE	0xFFFEC700
+
+/* MPU Timer Register offsets */
+#define CNTL_TIMER	           0x00   /* MPU_CNTL_TIMER */
+#define LOAD_TIM	           0x04   /* MPU_LOAD_TIMER */
+#define READ_TIM	           0x08   /* MPU_READ_TIMER */
+
+/* MPU_CNTL_TIMER register bits */
+#define MPUTIM_FREE               (1<<6)
+#define MPUTIM_CLOCK_ENABLE       (1<<5)
+#define MPUTIM_PTV_MASK           (0x7<<PTV_BIT)
+#define MPUTIM_PTV_BIT            2
+#define MPUTIM_AR                 (1<<1)
+#define MPUTIM_ST                 (1<<0)
+
+/***************************************************************************
+ * OMAP730 GPIO
+ *
+ * The GPIO control is split over 6 register bases in the OMAP730 to allow
+ * access to all the (6 x 32) GPIO pins!
+ **************************************************************************/
+
+#define OMAP730_GPIO_BASE_1        0xFFFBC000
+#define OMAP730_GPIO_BASE_2        0xFFFBC800
+#define OMAP730_GPIO_BASE_3        0xFFFBD000
+#define OMAP730_GPIO_BASE_4        0xFFFBD800
+#define OMAP730_GPIO_BASE_5        0xFFFBE000
+#define OMAP730_GPIO_BASE_6        0xFFFBE800
+
+#define GPIO_DATA_INPUT            0x00
+#define GPIO_DATA_OUTPUT           0x04
+#define GPIO_DIRECTION_CONTROL     0x08
+#define GPIO_INTERRUPT_CONTROL     0x0C
+#define GPIO_INTERRUPT_MASK        0x10
+#define GPIO_INTERRUPT_STATUS      0x14
+
+#define GPIO_DATA_INPUT_1            ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_1           ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_1     ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_1     ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_1        ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_1      ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_2            ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_2           ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_2     ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_2     ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_2        ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_2      ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_3            ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_3           ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_3     ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_3     ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_3        ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_3      ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_4            ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_4           ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_4     ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_4     ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_4        ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_4      ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_5            ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_5           ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_5     ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_5     ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_5        ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_5      ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_STATUS))
+
+#define GPIO_DATA_INPUT_6            ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_INPUT))
+#define GPIO_DATA_OUTPUT_6           ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_OUTPUT))
+#define GPIO_DIRECTION_CONTROL_6     ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DIRECTION_CONTROL))
+#define GPIO_INTERRUPT_CONTROL_6     ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_CONTROL))
+#define GPIO_INTERRUPT_MASK_6        ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK))
+#define GPIO_INTERRUPT_STATUS_6      ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS))
+
+/***************************************************************************
+ * OMAP730 Watchdog timers
+ **************************************************************************/
+
+#define WDTIM_BASE                 0xFFFEC800
+#define WDTIM_CONTROL              (WDTIM_BASE + 0x00)    /* MPU_CNTL_TIMER */
+#define WDTIM_LOAD                 (WDTIM_BASE + 0x04)    /* MPU_LOAD_TIMER */
+#define WDTIM_READ                 (WDTIM_BASE + 0x04)    /* MPU_READ_TIMER */
+#define WDTIM_MODE                 (WDTIM_BASE + 0x08)    /* MPU_TIMER_MODE */
+
+/***************************************************************************
+ * OMAP730 Interrupt Registers
+ **************************************************************************/
+
+/* Interrupt Register offsets */
+
+#define IRQ_ITR                               0x00
+#define IRQ_MIR                               0x04
+#define IRQ_SIR_IRQ                           0x10
+#define IRQ_SIR_FIQ                           0x14
+#define IRQ_CONTROL_REG                       0x18
+#define IRQ_ILR0                              0x1C  /* ILRx == ILR0 + (0x4 * x) */
+#define IRQ_SIR                               0x9C  /* a.k.a.IRQ_ISR */
+#define IRQ_GMIR                              0xA0
+
+#define REG_IHL1_MIR  (OMAP_IH1_BASE + IRQ_MIR)
+#define REG_IHL2_MIR  (OMAP_IH2_BASE + IRQ_MIR)
+
+/***************************************************************************
+ * OMAP730 Intersystem Communication Register                      (TRM 4.5)
+ **************************************************************************/
+
+#define ICR_BASE                   0xFFFBB800
+
+#define M_ICR                      (ICR_BASE + 0x00)
+#define G_ICR                      (ICR_BASE + 0x02)
+#define M_CTL                      (ICR_BASE + 0x04)
+#define G_CTL                      (ICR_BASE + 0x06)
+#define PM_BA                      (ICR_BASE + 0x0A)
+#define DM_BA                      (ICR_BASE + 0x0C)
+#define RM_BA                      (ICR_BASE + 0x0E)
+#define SSPI_TAS                   (ICR_BASE + 0x12)
+
+#endif /* ! __INCLUDED_OMAP730_H */
diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h
new file mode 100755
index 0000000..fda55cf
--- /dev/null
+++ b/include/configs/omap730p2.h
@@ -0,0 +1,196 @@
+/*
+ * (C) Copyright 2003-2004
+ * MPC Data Limited (http://www.mpc-data.co.uk)
+ * Dave Peverley <dpeverley at mpc-data.co.uk>
+ *
+ * Configuation settings for the TI OMAP Perseus 2 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.		See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_ARM926EJS	   1	     /* This is an arm926ejs CPU core  */
+#define CONFIG_OMAP		   1	     /* in a TI OMAP core    */
+#define CONFIG_OMAP730		   1	     /* which is in a 730  */
+#define CONFIG_P2_OMAP730	   1	     /*	 a Perseus 2 Board  */
+
+/*
+ * Input clock of PLL
+ * The OMAP730 Perseus 2 has 13MHz input clock
+ */
+
+#define CONFIG_SYS_CLK_FREQ	   13000000
+
+#undef CONFIG_USE_IRQ			     /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG	   1	     /* enable passing of ATAGs	 */
+#define CONFIG_SETUP_MEMORY_TAGS   1
+
+/*
+ * Size of malloc() pool
+ */
+
+#define CFG_MALLOC_LEN		   (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	   128	     /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE	   0x04000300
+#define CONFIG_LAN91C96_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	   (1)
+#define CFG_NS16550_CLK		   (48000000)	  /* can be 12M/32Khz or 48Mhz */
+#define CFG_NS16550_COM1	   0xfffb0000	  /* uart1, bluetooth uart
+						   * on perseus */
+
+/*
+ * select serial console configuration
+ */
+
+#define CONFIG_SERIAL1		   1	     /* we use SERIAL 1 on OMAP730 Perseus 2 */
+
+#define CONFIG_CONS_INDEX	   1
+#define CONFIG_BAUDRATE		   115200
+#define CFG_BAUDRATE_TABLE	   { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_COMMANDS		   (CONFIG_CMD_DFL | CFG_CMD_DHCP)
+#define CONFIG_BOOTP_MASK	   CONFIG_BOOTP_DEFAULT
+
+/*
+ * This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+
+#include <cmd_confdefs.h>
+#include <configs/omap730.h>
+#include <configs/h2_p2_dbg_board.h>
+
+#define CONFIG_BOOTDELAY	   3
+#define CONFIG_BOOTARGS		   "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
+
+#define CONFIG_LOADADDR		   0x10000000
+
+#define CONFIG_ETHADDR
+#define CONFIG_NETMASK		   255.255.255.0
+#define CONFIG_IPADDR		   192.168.0.23
+#define CONFIG_SERVERIP		   192.150.0.100
+#define CONFIG_BOOTFILE		   "uImage"  /* File to load */
+
+#if defined (CONFIG_COMMANDS) && defined (CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	   115200    /* Speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	   1	     /* Which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CFG_LONGHELP				       /* undef to save memory	   */
+#define CFG_PROMPT		   "OMAP730 P2 # "     /* Monitor Command Prompt   */
+#define CFG_CBSIZE		   256		       /* Console I/O Buffer Size  */
+/* Print Buffer Size */
+#define CFG_PBSIZE		   (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS		   16		       /* max number of command args   */
+#define CFG_BARGSIZE		   CFG_CBSIZE	       /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START	   0x10000000	       /* memtest works on */
+#define CFG_MEMTEST_END		   0x12000000	       /* 32 MB in DRAM	   */
+
+#undef CFG_CLKS_IN_HZ		     /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		   0x10000000	       /* default load address */
+
+/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
+ * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
+ * local divisor.
+ */
+
+#define CFG_TIMERBASE		   0xFFFEC500	       /* use timer 1 */
+#define CFG_PVT			   7		       /* 2^(pvt+1), divide by 256 */
+#define CFG_HZ			   ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+
+#define CONFIG_STACKSIZE	   (128*1024)	  /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	   (4*1024)	  /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	   (4*1024)	  /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+#define CONFIG_NR_DRAM_BANKS	   1		  /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		   0x10000000	  /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	   0x02000000	  /* 32 MB */
+
+#if defined(CONFIG_CS0_BOOT)
+#define PHYS_FLASH_1		   0x0C000000
+#elif defined(CONFIG_CS3_BOOT)
+#define PHYS_FLASH_1		   0x00000000
+#else
+#error Unknown Boot Chip-Select number
+#endif
+
+#define CFG_FLASH_BASE		   PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CFG_MAX_FLASH_BANKS	   1		  /* max number of memory banks */
+#define PHYS_FLASH_SIZE		   0x02000000	  /* 32MB */
+#define CFG_MAX_FLASH_SECT	   (259)	  /* max number of sectors on one chip */
+/* addr of environment */
+#define CFG_ENV_ADDR		   (CFG_FLASH_BASE + 0x020000)
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	    (20*CFG_HZ)	  /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	    (20*CFG_HZ)	  /* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH	   1
+#define CFG_ENV_SIZE		   0x20000	  /* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET		   0x20000	  /* environment starts here  */
+
+#endif	  /* ! __CONFIG_H */
diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h
new file mode 100755
index 0000000..831d018
--- /dev/null
+++ b/include/configs/p3p440.h
@@ -0,0 +1,318 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * board/config_p3p440.h - configuration for Prodrive P3P440
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_P3P440		1	    /* Board is P3P440		*/
+#define CONFIG_440GP		1	    /* Specifc GP support	*/
+#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R	1	    /* Call misc_init_r		*/
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
+#define CFG_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
+#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
+#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
+#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
+#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
+#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
+
+#define CFG_USB_BASE	    (CFG_PERIPHERAL_BASE + 0x00000000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR	CFG_ISRAM_BASE  /* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x2000	    /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE	128	    /* num bytes initial data	*/
+
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0*/
+#define CFG_SDRAM_TABLE	{	\
+		{(256 << 20), 0x000C4001}, /* 256MB mode 3, 13x10(4) */	\
+		{(64 << 20),  0x00082001}} /* 64MB mode 2, 12x9(4)   */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_BAUDRATE_TABLE						\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,		\
+			57600, 115200, 230400, 460800, 921600 }
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs	*/
+
+/*-----------------------------------------------------------------------
+ * I2C RTC
+ *----------------------------------------------------------------------*/
+#define CONFIG_RTC_MAX6900	1		/* MAX6900 RTC		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (PCF8594C) for environment
+ *----------------------------------------------------------------------*/
+#define CFG_I2C_EEPROM_ADDR	0x54	/* EEPROM PCF8594C		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CFG_EEPROM_PAGE_WRITE_BITS 3	/* The Philips PCF8594C has	*/
+					/* 8 byte page write mode using */
+					/* last 3 bits of the address	*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	40   /* and takes up to 40 msec */
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/*-----------------------------------------------------------------------
+ * Default configuration (environment varibles...)
+ *----------------------------------------------------------------------*/
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=p3p440\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/p3p440/uImage\0"				\
+	"kernel_addr=ff800000\0"					\
+	"ramdisk_addr=ff810000\0"					\
+	"load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0"		\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0x1c	/* PHY address			*/
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	0x1d	/* EMAC1 PHY address		*/
+#define CONFIG_NET_MULTI	1
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI			            /* include pci support	        */
+#define CONFIG_PCI_PNP			        /* do pci plug-and-play         */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
+#define CFG_PCI_TARGET_INIT	            /* let board init pci target    */
+
+#define CONFIG_DISABLE_PISE_TEST	/* disable PISE test (PCIX only)*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH0		0xFF800000
+#define CFG_FLASH1		0xFF000000
+#define CFG_FLASH2		0xFE800000
+#define CFG_FLASH3		0xFE000000
+#define CFG_USB			0xF0000000
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x03050200
+#define CFG_EBC_PB0CR		(CFG_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB1AP		0x03050200
+#define CFG_EBC_PB1CR		(CFG_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB2AP		0x03050200
+#define CFG_EBC_PB2CR		(CFG_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB3AP		0x03050200
+#define CFG_EBC_PB3CR		(CFG_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 7 (USB controller) initialization				*/
+#define CFG_EBC_PB7AP		0x02015000
+#define CFG_EBC_PB7CR		(CFG_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH3, CFG_FLASH2, CFG_FLASH1, CFG_FLASH0 }
+
+#define CFG_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		(32<<10)	/* For AMCC 405 CPUs		*/
+#define CFG_CACHELINE_SIZE	32	/* ...					*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
new file mode 100755
index 0000000..ed1893f
--- /dev/null
+++ b/include/configs/pb1x00.h
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the dbau1x00 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
+#define CONFIG_PB1X00		1
+#define CONFIG_AU1X00		1  /* alchemy series cpu */
+
+#ifdef CONFIG_PB1000
+#define CONFIG_AU1000		1
+#else
+#ifdef CONFIG_PB1100
+#define CONFIG_AU1100		1
+#else
+#ifdef CONFIG_PB1500
+#define CONFIG_AU1500		1
+#else
+#error "No valid board set"
+#endif
+#endif
+#endif
+
+#define CONFIG_ETHADDR		DE:AD:BE:EF:01:01    /* Ethernet address */
+
+#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
+
+#define CONFIG_BAUDRATE		115200
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"addmisc=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate} "				\
+		"panic=1\0"						\
+	"bootfile=/vmlinux.img\0"				\
+	"load=tftp 80500000 ${u-boot}\0"				\
+	""
+/* Boot from NFS root */
+#define CONFIG_BOOTCOMMAND	"bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory      */
+#define	CFG_PROMPT		"Pb1x00 # "	/* Monitor Command Prompt    */
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args*/
+
+#define CFG_MALLOC_LEN		128*1024
+
+#define CFG_BOOTPARAMS_LEN	128*1024
+
+#define CFG_HZ			396000000      /* FIXME causes overflow in net.c */
+
+#define CFG_SDRAM_BASE		0x80000000     /* Cached addr */
+
+#define	CFG_LOAD_ADDR		0x81000000     /* default load address	*/
+
+#define CFG_MEMTEST_START	0x80100000
+#undef CFG_MEMTEST_START
+#define CFG_MEMTEST_START       0x80200000
+#define CFG_MEMTEST_END		0x83800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+
+#define PHYS_FLASH_1		0xbec00000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0xbfc00000 /* Flash Bank #2 */
+
+/* The following #defines are needed to get flash environment right */
+#define	CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MONITOR_LEN		(192 << 10)
+
+#define CFG_INIT_SP_OFFSET	0x4000000
+
+/* We boot from this flash, selected with dip switch */
+#define CFG_FLASH_BASE		PHYS_FLASH_2
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_NOWHERE	1
+
+/* Address and size of Primary Environment Sector	*/
+#define CFG_ENV_ADDR		0xB0030000
+#define CFG_ENV_SIZE		0x10000
+
+#define CONFIG_FLASH_16BIT
+
+#define CONFIG_NR_DRAM_BANKS	2
+
+#define CONFIG_NET_MULTI
+
+#define CONFIG_MEMSIZE_IN_BYTES
+
+
+/*---USB -------------------------------------------*/
+#if 0
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#else
+#define ADD_USB_CMD             0
+#endif
+
+/*---ATA PCMCIA ------------------------------------*/
+#if 0
+#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
+#define CFG_PCMCIA_MEM_ADDR 0x20000000
+#define CONFIG_PCMCIA_SLOT_A
+
+#define CONFIG_ATAPI 1
+#define CONFIG_MAC_PARTITION 1
+
+/* We run CF in "true ide" mode or a harddrive via pcmcia */
+#define CONFIG_IDE_PCMCIA 1
+
+/* We only support one slot for now */
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET     8
+
+/* Offset for normal register accesses  */
+#define CFG_ATA_REG_OFFSET      0
+
+/* Offset for alternate registers       */
+#define CFG_ATA_ALT_OFFSET      0x0100
+
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384
+#define CFG_ICACHE_SIZE		16384
+#define CFG_CACHELINE_SIZE	32
+
+#define CONFIG_COMMANDS	\
+  (((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_PING) & \
+ ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | CFG_CMD_IDE | \
+   CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \
+   CFG_CMD_BDI | CFG_CMD_BEDBUG)) | ADD_USB_CMD)
+#include <cmd_confdefs.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h
new file mode 100755
index 0000000..73aa3a8
--- /dev/null
+++ b/include/configs/pcu_e.h
@@ -0,0 +1,539 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Workaround for layout bug on prototype board
+ */
+#define	PCU_E_WITH_SWAPPED_CS	1
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860T CPU	*/
+#define CONFIG_MPC860T		1
+#define CONFIG_PCU_E		1	/* ...on a PCU E board		*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+
+#define CONFIG_BAUDRATE		9600
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp;"								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#define	CONFIG_PRAM		2048	/* reserve 2 MB "protected RAM"	*/
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define	CONFIG_SPI			/* enable SPI driver		*/
+#define	CONFIG_SPI_X			/* 16 bit EEPROM addressing	*/
+
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+
+/* ----------------------------------------------------------------
+ * Offset to initial SPI buffers in DPRAM (used if the environment
+ * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
+ * use at an early stage. It is used between the two initialization
+ * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
+ * far enough from the start of the data area (as well as from the
+ * stack pointer).
+ * ---------------------------------------------------------------- */
+#define CFG_SPI_INIT_OFFSET		0xB00
+
+#define CONFIG_COMMANDS		(	CONFIG_CMD_DFL	| \
+					CFG_CMD_BSP	| \
+					CFG_CMD_DATE	| \
+					CFG_CMD_DHCP	| \
+					CFG_CMD_EEPROM	| \
+					CFG_CMD_NFS	| \
+					CFG_CMD_SNTP	)
+
+#define CONFIG_BOOTP_MASK \
+    ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/
+
+#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+/* Ethernet hardware configuration done using port pins */
+#define CFG_PB_ETH_RESET	0x00000020		/* PB 26	*/
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_PA_ETH_MDDIS	0x4000			/* PA  1	*/
+#define CFG_PB_ETH_POWERDOWN	0x00000800		/* PB 20	*/
+#define CFG_PB_ETH_CFG1		0x00000400		/* PB 21	*/
+#define CFG_PB_ETH_CFG2		0x00000200		/* PB 22	*/
+#define CFG_PB_ETH_CFG3		0x00000100		/* PB 23	*/
+#else /* XXX */
+#define CFG_PB_ETH_MDDIS	0x00000010		/* PB 27	*/
+#define CFG_PB_ETH_POWERDOWN	0x00000100		/* PB 23	*/
+#define CFG_PB_ETH_CFG1		0x00000200		/* PB 22	*/
+#define CFG_PB_ETH_CFG2		0x00000400		/* PB 21	*/
+#define CFG_PB_ETH_CFG3		0x00000800		/* PB 20	*/
+#endif /* XXX */
+
+/* Ethernet settings:
+ * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
+ */
+#define CFG_ETH_MDDIS_VALUE	0
+#define CFG_ETH_CFG1_VALUE	1
+#define CFG_ETH_CFG2_VALUE	1
+#define CFG_ETH_CFG3_VALUE	1
+
+/* PUMA configuration */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_PB_PUMA_PROG	0x00000010		/* PB 27	*/
+#else /* XXX */
+#define CFG_PA_PUMA_PROG	0x4000			/* PA  1	*/
+#endif /* XXX */
+#define CFG_PC_PUMA_DONE	0x0008			/* PC 12	*/
+#define CFG_PC_PUMA_INIT	0x0004			/* PC 13	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFE000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Address accessed to reset the board - must not be mapped/assigned
+ */
+#define	CFG_RESET_ADDRESS	0xFEFFFFFF
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+/* this is an ugly hack needed because of the silly non-constant address map */
+#define CFG_FLASH_BASE		(0-flash_info[0].size-flash_info[1].size)
+
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	160	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	180000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#if 0
+/* Start port with environment in flash; switch to SPI EEPROM later */
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x2000	/* Total Size of Environment 		*/
+#define CFG_ENV_ADDR	    0xFFFFE000	/* Address    of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	0x2000	/* use the top-most 8k boot sector	*/
+#define	CFG_ENV_IS_EMBEDDED	1	/* short-cut compile-time test		*/
+#else
+/* Final version: environment in EEPROM */
+#define CFG_ENV_IS_IN_EEPROM	1
+#define CFG_I2C_EEPROM_ADDR	0
+#define CFG_I2C_EEPROM_ADDR_LEN	2
+#define CFG_ENV_OFFSET		1024
+#define CFG_ENV_SIZE		1024
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * External Arbitration max. priority (7),
+ * Debug pins configuration '11',
+ * Asynchronous external master enable.
+ */
+/* => 0x70600200 */
+#define CFG_SIUMCR	(SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* 0x00004080 */
+#define	CFG_PLPRCR_MF	0	/* (0+1) * 50 = 50 MHz Clock */
+#define CFG_PLPRCR							\
+		(	(CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) |		\
+			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
+			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
+			PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/	\
+		)
+
+#define	CONFIG_8xx_GCLK_FREQ	((CFG_PLPRCR_MF+1)*50000000)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ *
+ * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* 0x01800000 */
+#define CFG_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
+			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\
+			 SCCR_EBDF00 |   SCCR_DFSYNC00 |	\
+			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
+			 SCCR_DFNH000	|   SCCR_DFLCD100 |	\
+			 SCCR_DFALCD01)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ *
+ * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!!
+ *
+ * Don't expect the "date" command to work without a 32kHz clock input!
+ */
+/* 0x00C3 => 0x0003 */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register		19-4
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR 0x0000
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMDS 0
+
+/*-----------------------------------------------------------------------
+ *
+ * Interrupt Levels
+ *-----------------------------------------------------------------------
+ */
+#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define FLASH_BASE6_PRELIM	0xFF000000	/* FLASH bank #1	*/
+#else /* XXX */
+#define FLASH_BASE1_PRELIM	0xFF000000	/* FLASH bank #1	*/
+#endif /* XXX */
+
+/*
+ * used to re-map FLASH: restrict access enough but not too much to
+ * meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0xFF800000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+
+/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1			*/
+#define CFG_OR_TIMING_FLASH	(OR_SCY_8_CLK | OR_EHTR)
+
+#define CFG_OR0_REMAP	( CFG_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \
+				CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
+				CFG_OR_TIMING_FLASH)
+/* 16 bit, bank valid */
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_OR6_REMAP	CFG_OR0_REMAP
+#define CFG_OR6_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR6_PRELIM	((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#else /* XXX */
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+#endif /* XXX */
+
+/*
+ * BR2/OR2: SDRAM
+ *
+ * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
+ */
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define SDRAM_BASE5_PRELIM	0x00000000	/* SDRAM bank */
+#else /* XXX */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank */
+#endif /* XXX */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map 128 MB (>SDRAM_MAX_SIZE!) */
+#define SDRAM_TIMING		OR_CSNT_SAM	/* SDRAM-Timing */
+
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
+
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_OR5_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CFG_BR5_PRELIM	((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else /* XXX */
+#define CFG_OR2_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#endif /* XXX */
+
+/*
+ * BR3/OR3: CAN Controller
+ *	BR3: 0x10000401		OR3: 0xffff818a
+ */
+#define CAN_CTRLR_BASE		0x10000000	/* CAN Controller */
+#define CAN_CTRLR_OR_AM		0xFFFF8000	/* 32 kB */
+#define CAN_CTRLR_TIMING	(OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)
+
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_BR4_PRELIM		((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CFG_OR4_PRELIM		(CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
+#else /* XXX */
+#define CFG_BR3_PRELIM		((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CFG_OR3_PRELIM		(CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
+#endif /* XXX */
+
+/*
+ * BR4/OR4: PUMA Config
+ *
+ * Memory controller will be used in 2 modes:
+ *
+ * - "read" mode:
+ *	BR4: 0x10100801		OR4: 0xffff8530
+ * - "load" mode (chip select on UPM B):
+ *	BR4: 0x101008c1		OR4: 0xffff8630
+ *
+ * Default initialization is in "read" mode
+ */
+#define PUMA_CONF_BASE		0x10100000	/* PUMA Config */
+#define PUMA_CONF_OR_AM		0xFFFF8000	/* 32 kB */
+#define	PUMA_CONF_LOAD_TIMING	(OR_ACS_DIV2	 | OR_SCY_3_CLK)
+#define PUMA_CONF_READ_TIMING	(OR_G5LA | OR_BI | OR_SCY_3_CLK)
+
+#define PUMA_CONF_BR_LOAD	((PUMA_CONF_BASE & BR_BA_MSK) | \
+					BR_PS_16 | BR_MS_UPMB | BR_V)
+#define PUMA_CONF_OR_LOAD	(PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
+
+#define PUMA_CONF_BR_READ	((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define PUMA_CONF_OR_READ	(PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
+
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_BR3_PRELIM		PUMA_CONF_BR_READ
+#define CFG_OR3_PRELIM		PUMA_CONF_OR_READ
+#else /* XXX */
+#define CFG_BR4_PRELIM		PUMA_CONF_BR_READ
+#define CFG_OR4_PRELIM		PUMA_CONF_OR_READ
+#endif /* XXX */
+
+/*
+ * BR5/OR5: PUMA: SMA Bus 8 Bit
+ *	BR5: 0x10200401		OR5: 0xffe0010a
+ */
+#define PUMA_SMA8_BASE		0x10200000	/* PUMA SMA Bus 8 Bit */
+#define PUMA_SMA8_OR_AM		0xFFE00000	/* 2 MB */
+#define PUMA_SMA8_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
+
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_BR2_PRELIM		((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CFG_OR2_PRELIM		(PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
+#else /* XXX */
+#define CFG_BR5_PRELIM		((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define CFG_OR5_PRELIM		(PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
+#endif /* XXX */
+
+/*
+ * BR6/OR6: PUMA: SMA Bus 16 Bit
+ *	BR6: 0x10600801		OR6: 0xffe0010a
+ */
+#define PUMA_SMA16_BASE		0x10600000	/* PUMA SMA Bus 16 Bit */
+#define PUMA_SMA16_OR_AM	0xFFE00000	/* 2 MB */
+#define PUMA_SMA16_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
+
+#if PCU_E_WITH_SWAPPED_CS /* XXX */
+#define CFG_BR1_PRELIM		((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CFG_OR1_PRELIM		(PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
+#else /* XXX */
+#define CFG_BR6_PRELIM		((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CFG_OR6_PRELIM		(PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
+#endif /* XXX */
+
+/*
+ * BR7/OR7: PUMA: external Flash
+ *	BR7: 0x10a00801		OR7: 0xfe00010a
+ */
+#define PUMA_FLASH_BASE		0x10A00000	/* PUMA external Flash */
+#define PUMA_FLASH_OR_AM	0xFE000000	/* 32 MB */
+#define PUMA_FLASH_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)
+
+#define CFG_BR7_PRELIM		((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define CFG_OR7_PRELIM		(PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MPTPR	0x0200
+
+/*
+ * MAMR settings for SDRAM
+ * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10,
+ *		MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X
+ * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X
+ */
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	0x30	/* = 48 */
+
+#define CFG_MAMR	( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
+			  MAMR_AMA_TYPE_1	| \
+			  MAMR_G0CLA_A10	| \
+			  MAMR_RLFA_1X		| \
+			  MAMR_WLFA_1X		| \
+			  MAMR_TLFA_8X		)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h
new file mode 100755
index 0000000..fefdb3c
--- /dev/null
+++ b/include/configs/pf5200.h
@@ -0,0 +1,399 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * (c) 2005 esd gmbh Hannover
+ *
+ *
+ * from IceCube.h file
+ * by Reinhard Arlt reinhard.arlt@esd-electronics.com
+ *
+ *************************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_ICECUBE		1	/* ... on IceCube board */
+#define CONFIG_PF5200		1	/* ... on PF5200  board */
+#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	*/
+
+#define CFG_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#if 0				/* test-only */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#else
+#define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
+#endif
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#ifdef CONFIG_MPC5200		/* MPC5100 PCI is not supported yet. */
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_MII		1
+#if 0				/* test-only !!! */
+#define CONFIG_NET_MULTI	1
+#define CONFIG_EEPRO100		1
+#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+#define CONFIG_NS8382X		1
+#endif
+
+#define ADD_PCI_CMD		CFG_CMD_PCI
+
+#else				/* MPC5100 */
+
+#define ADD_PCI_CMD		0	/* no CFG_CMD_PCI */
+
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 0
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD		0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				 CFG_CMD_EEPROM	| \
+				 CFG_CMD_FAT	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_IDE	| \
+				 CFG_CMD_BSP	| \
+				 CFG_CMD_ELF	| \
+				 ADD_PCI_CMD	  )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#if (TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT16	1
+#endif
+#if (TEXT_BASE == 0xFF800000)	/* Boot low with  8 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT08	1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Welcome to ParaFinder pf5200;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=eth0\0" \
+	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
+	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
+	"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
+	"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
+	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
+	"loadaddr=01000000\0" \
+	"serverip=192.168.2.99\0" \
+	"gatewayip=10.0.0.79\0" \
+	"user=mu\0" \
+	"target=pf5200.esd\0" \
+	"script=pf5200.bat\0" \
+	"image=/tftpboot/vxWorks_pf5200\0" \
+	"ipaddr=10.0.13.196\0" \
+	"netmask=255.255.0.0\0" \
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
+
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133		/* define for 133MHz speed */
+#endif
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		86000	/* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	5
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CFG_I2C_MULTI_EEPROMS		1
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		0xFE000000
+#define CFG_FLASH_SIZE		0x02000000
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00000000)
+#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CFG_MAX_FLASH_SECT	512
+
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+/*
+ * Environment settings
+ */
+#if 1				/* test-only */
+#define CFG_ENV_IS_IN_FLASH	0
+#define CFG_ENV_SIZE		0x10000
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_OVERWRITE	1
+#else
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x0000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x0400	/* 8192 bytes may be used for env vars */
+				   /* total size of a CAT24WC32 is 8192 bytes */
+#define CONFIG_ENV_OVERWRITE	1
+#endif
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_UDP_CHECKSUM	1
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG	0x01052444
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x0004DD00
+
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CFG_CS1_START		0xfd000000
+#define CFG_CS1_SIZE		0x00010000
+#define CFG_CS1_CFG		0x10101410
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED		/* LED	 for ide not supported	*/
+
+#define	CONFIG_IDE_RESET	/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers						     */
+#define CFG_ATA_STRIDE		4
+
+/*-----------------------------------------------------------------------
+ * CPLD stuff
+ */
+#define CFG_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
+#define CFG_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */
+
+/* CPLD program pin configuration */
+#define CFG_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
+#define CFG_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
+#define CFG_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */
+
+#define JTAG_GPIO_ADDR_TMS	(CFG_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
+#define JTAG_GPIO_ADDR_TCK	(CFG_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
+#define JTAG_GPIO_ADDR_TDI	(CFG_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
+#define JTAG_GPIO_ADDR_TDO	(CFG_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */
+
+#define JTAG_GPIO_ADDR_CFG	(CFG_MBAR + 0xB00)
+#define JTAG_GPIO_CFG_SET	0x00000000
+#define JTAG_GPIO_CFG_RESET	0x00F00000
+
+#define JTAG_GPIO_ADDR_EN_TMS	(CFG_MBAR + 0xB04)
+#define JTAG_GPIO_TMS_EN_SET	0x20000000	/* Enable for GPIO */
+#define JTAG_GPIO_TMS_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TMS	(CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_TMS_DDR_SET	0x20000000	/* Set as output   */
+#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TCK	(CFG_MBAR + 0xC00)
+#define JTAG_GPIO_TCK_EN_SET	0x20000000	/* Enable for GPIO */
+#define JTAG_GPIO_TCK_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TCK	(CFG_MBAR + 0xC08)
+#define JTAG_GPIO_TCK_DDR_SET	0x20000000	/* Set as output   */
+#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDI	(CFG_MBAR + 0xC00)
+#define JTAG_GPIO_TDI_EN_SET	0x10000000	/* Enable as GPIO  */
+#define JTAG_GPIO_TDI_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDI	(CFG_MBAR + 0xC08)
+#define JTAG_GPIO_TDI_DDR_SET	0x10000000	/* Set as output   */
+#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDO	(CFG_MBAR + 0xB04)
+#define JTAG_GPIO_TDO_EN_SET	0x10000000	/* Enable as GPIO  */
+#define JTAG_GPIO_TDO_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDO	(CFG_MBAR + 0xB0C)
+#define JTAG_GPIO_TDO_DDR_SET	0x00000000
+#define JTAG_GPIO_TDO_DDR_RESET 0x10000000	/* Set as input	   */
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h
new file mode 100755
index 0000000..a6c2371
--- /dev/null
+++ b/include/configs/pleb2.h
@@ -0,0 +1,244 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuration settings for the PLEB 2 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA250		1	/* This is an PXA255 CPU    */
+#define CONFIG_PLEB2		1	/* on an PLEB2 Board	    */
+#undef CONFIG_LCD
+#undef CONFIG_MMC
+#define BOARD_LATE_INIT		1
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/* None - PLEB 2 doesn't have any of this.
+   #define CONFIG_DRIVER_LAN91C96
+   #define CONFIG_LAN91C96_BASE 0x0C000000 */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART	       1       /* we use FFUART on PLEB 2 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL & ~CFG_CMD_NET)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.0.0
+#define CONFIG_IPADDR		192.168.0.21
+#define CONFIG_SERVERIP		192.168.0.250
+#define CONFIG_BOOTCOMMAND	"bootm 40000"
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 prompt_ramdisk=0 load_ramdisk=1 console=ttyS0,115200"
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER		1
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#define CFG_LONGHELP				/* undef to save memory		*/
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
+#else
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_DEVICE_NULLDEV	1
+
+#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0xa2000000	/* default load address */
+
+#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x141		/* set core clock to 200/200/100 MHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
+#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
+#define PHYS_FLASH_SIZE		0x00800000 /* 4 MB */
+
+/* Not entirely sure about this - DS/CHC */
+#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE	0x00010000 /* 64 KB sectors (x2) */
+
+#define CFG_DRAM_BASE		PHYS_SDRAM_1
+#define CFG_DRAM_SIZE		PHYS_SDRAM_1_SIZE
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPSR0_VAL		0x00000000  /* Don't set anything */
+#define CFG_GPSR1_VAL		0x00000080
+#define CFG_GPSR2_VAL		0x00000000
+
+#define CFG_GPCR0_VAL		0x00000000  /* Don't clear anything */
+#define CFG_GPCR1_VAL		0x00000000
+#define CFG_GPCR2_VAL		0x00000000
+
+#define CFG_GPDR0_VAL		0x00000000
+#define CFG_GPDR1_VAL		0x000007C3
+#define CFG_GPDR2_VAL		0x00000000
+
+/* Edge detect registers (these are set by the kernel) */
+#define CFG_GRER0_VAL	    0x00000000
+#define CFG_GRER1_VAL	    0x00000000
+#define CFG_GRER2_VAL	    0x00000000
+#define CFG_GFER0_VAL	    0x00000000
+#define CFG_GFER1_VAL	    0x00000000
+#define CFG_GFER2_VAL	    0x00000000
+
+#define CFG_GAFR0_L_VAL		0x00000000
+#define CFG_GAFR0_U_VAL		0x00000000
+#define CFG_GAFR1_L_VAL		0x00008010  /* Use FF UART Send and Receive */
+#define CFG_GAFR1_U_VAL		0x00000000
+#define CFG_GAFR2_L_VAL		0x00000000
+#define CFG_GAFR2_U_VAL		0x00000000
+
+#define CFG_PSSR_VAL		0x20
+#define CFG_CCCR_VAL	    0x00000141	/* 100 MHz memory, 200 MHz CPU	*/
+#define CFG_CKEN_VAL	    0x00000060	/* FFUART and STUART enabled	*/
+#define CFG_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/
+
+/*
+ * Memory settings
+ */
+#define CFG_MSC0_VAL		0x00007FF0 /* Not properly calculated - FIXME (DS) */
+#define CFG_MSC1_VAL		0x00000000
+#define CFG_MSC2_VAL		0x00000000
+
+#define CFG_MDCNFG_VAL		0x00000aC9 /* Memory timings for the SDRAM.
+					      tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */
+
+#define CFG_MDREFR_VAL		0x00403018 /* Initial setting, individual	*/
+					   /* bits set in lowlevel_init.S	*/
+#define CFG_MDMRS_VAL		0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL		0x00000000  /* Hangover from Lubbock.
+					       Needs calculating. (DS/CHC) */
+#define CFG_MCMEM0_VAL		0x00010504
+#define CFG_MCMEM1_VAL		0x00010504
+#define CFG_MCATT0_VAL		0x00010504
+#define CFG_MCATT1_VAL		0x00010504
+#define CFG_MCIO0_VAL		0x00004715
+#define CFG_MCIO1_VAL		0x00004715
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+
+/* timeout values are in ticks */
+/* FIXME */
+#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+
+/* Flash protection */
+#define CFG_FLASH_PROTECTION	1
+
+/* FIXME */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x3C000)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment */
+#define CFG_ENV_SECT_SIZE	0x20000
+
+/* Option added to get around byte ordering issues in the flash driver */
+#define CFG_LITTLE_ENDIAN	1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
new file mode 100755
index 0000000..7579222
--- /dev/null
+++ b/include/configs/ppmc8260.h
@@ -0,0 +1,1006 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * Configuation settings for the WindRiver PPMC8260 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*****************************************************************************
+ *
+ * These settings must match the way _your_ board is set up
+ *
+ *****************************************************************************/
+
+/* What is the oscillator's (UX2) frequency in Hz? */
+#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
+
+/*-----------------------------------------------------------------------
+ * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
+ *-----------------------------------------------------------------------
+ * What should MODCK_H be? It is dependent on the oscillator
+ * frequency, MODCK[1-3], and desired CPM and core frequencies.
+ * Here are some example values (all frequencies are in MHz):
+ *
+ * MODCK_H   MODCK[1-3]	 Osc	CPM    Core  S2-6   S2-7   S2-8
+ * -------   ----------	 ---	---    ----  -----  -----  -----
+ * 0x2	     0x2	 33	133    133   Close  Open   Close
+ * 0x2	     0x3	 33	133    166   Close  Open   Open
+ * 0x2	     0x4	 33	133    200   Open   Close  Close
+ * 0x2	     0x5	 33	133    233   Open   Close  Open
+ * 0x2	     0x6	 33	133    266   Open   Open   Close
+ *
+ * 0x5	     0x5	 66	133    133   Open   Close  Open
+ * 0x5	     0x6	 66	133    166   Open   Open   Close
+ * 0x5	     0x7	 66	133    200   Open   Open   Open
+ * 0x6	     0x0	 66	133    233   Close  Close  Close
+ * 0x6	     0x1	 66	133    266   Close  Close  Open
+ * 0x6	     0x2	 66	133    300   Close  Open   Close
+ */
+#define CFG_PPMC_MODCK_H 0x05
+
+/* Define this if you want to boot from 0x00000100. If you don't define
+ * this, you will need to program the bootloader to 0xfff00000, and
+ * get the hardware reset config words at 0xfe000000. The simplest
+ * way to do that is to program the bootloader at both addresses.
+ * It is suggested that you just let U-Boot live at 0x00000000.
+ */
+#define CFG_PPMC_BOOT_LOW 1
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/ppmc8260/config.mk
+ * The main FLASH is whichever is connected to *CS0. U-Boot expects
+ * this to be the SIMM.
+ */
+#define CFG_FLASH0_BASE 0xFE000000
+#define CFG_FLASH0_SIZE 16
+
+/* What should be the base address of the first SDRAM DIMM and how big is
+ * it (in Mbytes)?
+*/
+#define CFG_SDRAM0_BASE 0x00000000
+#define CFG_SDRAM0_SIZE 128
+
+/* What should be the base address of the second SDRAM DIMM and how big is
+ * it (in Mbytes)?
+*/
+#define CFG_SDRAM1_BASE 0x08000000
+#define CFG_SDRAM1_SIZE 128
+
+/* What should be the base address of the on board SDRAM and how big is
+ * it (in Mbytes)?
+*/
+#define CFG_SDRAM2_BASE 0x38000000
+#define CFG_SDRAM2_SIZE 16
+
+/* What should be the base address of the MAILBOX  and how big is it
+ * (in Bytes)
+ * The eeprom lives at CFG_MAILBOX_BASE + 0x80000000
+ */
+#define CFG_MAILBOX_BASE 0x32000000
+#define CFG_MAILBOX_SIZE 8192
+
+/* What is the base address of the I/O select lines and how big is it
+ * (In Mbytes)?
+ */
+
+#define CFG_IOSELECT_BASE 0xE0000000
+#define CFG_IOSELECT_SIZE 32
+
+
+/* What should be the base address of the LEDs and switch S0?
+ * If you don't want them enabled, don't define this.
+ */
+#define CFG_LED_BASE 0xF1000000
+
+/*
+ * PPMC8260 with 256 16 MB DIMM:
+ *
+ *     0x0000 0000     Exception Vector code, 8k
+ *	     :
+ *     0x0000 1FFF
+ *     0x0000 2000     Free for Application Use
+ *	     :
+ *	     :
+ *
+ *	     :
+ *	     :
+ *     0x0FF5 FF30     Monitor Stack (Growing downward)
+ *		       Monitor Stack Buffer (0x80)
+ *     0x0FF5 FFB0     Board Info Data
+ *     0x0FF6 0000     Malloc Arena
+ *	     :		    CFG_ENV_SECT_SIZE, 256k
+ *	     :		    CFG_MALLOC_LEN,    128k
+ *     0x0FFC 0000     RAM Copy of Monitor Code
+ *	     :		    CFG_MONITOR_LEN,   256k
+ *     0x0FFF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
+ */
+
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ * The console can be on SMC1 or SMC2
+ */
+#define CONFIG_CONS_ON_SMC	1	/* define if console on SMC */
+#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on neither */
+#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+
+#undef	CONFIG_ETHER_ON_SCC		/* define if ethernet on SCC	*/
+#define CONFIG_ETHER_ON_FCC		/* define if ethernet on FCC	*/
+#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */
+#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
+#define CONFIG_MII			/* MII PHY management	*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+/*
+ * Port pins used for bit-banged MII communictions (if applicable).
+ */
+#define MDIO_PORT	2	/* Port C */
+#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
+#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
+			else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
+			else	iop->pdat &= ~0x00200000
+
+#define MIIDELAY	udelay(1)
+
+
+/* Define this to reserve an entire FLASH sector (256 KB) for
+ * environment variables. Otherwise, the environment will be
+ * put in the same sector as U-Boot, and changing variables
+ * will erase U-Boot temporarily
+ */
+#define CFG_ENV_IN_OWN_SECT	1
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* What should the console's baud rate be? */
+#define CONFIG_BAUDRATE		9600
+
+/* Ethernet MAC address */
+
+#define CONFIG_ETHADDR		00:a0:1e:90:2b:00
+
+/* Define this to set the last octet of the ethernet address
+ * from the DS0-DS7 switch and light the leds with the result
+ * The DS0-DS7 switch and the leds are backwards with respect
+ * to each other. DS7 is on the board edge side of both the
+ * led strip and the DS0-DS7 switch.
+ */
+#define CONFIG_MISC_INIT_R
+
+/* Set to a positive value to delay for running BOOTCOMMAND */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#if 0
+/* Be selective on what keys can delay or stop the autoboot process
+ *     To stop	use: " "
+ */
+# define CONFIG_AUTOBOOT_KEYED
+# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
+# define CONFIG_AUTOBOOT_STOP_STR	" "
+# undef CONFIG_AUTOBOOT_DELAY_STR
+# define DEBUG_BOOTKEYS		0
+#endif
+
+/* Define a command string that is automatically executed when no character
+ * is read on the console interface withing "Boot Delay" after reset.
+ */
+#undef	CONFIG_BOOT_ROOT_INITRD 	/* Use ram disk for the root file system */
+#define	CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
+
+#ifdef CONFIG_BOOT_ROOT_INITRD
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/ram0 rw " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_INITRD */
+
+#ifdef CONFIG_BOOT_ROOT_NFS
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_NFS */
+
+/* Add support for a few extra bootp options like:
+ *	- File size
+ *	- DNS
+ */
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE | \
+				 CONFIG_BOOTP_DNS)
+
+/* undef this to save memory */
+#define CFG_LONGHELP
+
+/* Monitor Command Prompt */
+#define CFG_PROMPT		"=> "
+
+/* What U-Boot subsytems do you want enabled? */
+#define CONFIG_COMMANDS		(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
+				CFG_CMD_ELF	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_ECHO	| \
+				CFG_CMD_REGINFO | \
+				CFG_CMD_MEMTEST | \
+				CFG_CMD_MII	| \
+				CFG_CMD_IMMAP)
+
+
+/* Where do the internal registers live? */
+#define CFG_IMMR		0xf0000000
+
+/*****************************************************************************
+ *
+ * You should not have to modify any of the following settings
+ *
+ *****************************************************************************/
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
+#define CONFIG_PPMC8260		1	/* on an Wind River PPMC8260 Board  */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size	     */
+#else
+#  define CFG_CBSIZE		256	/* Console I/O Buffer Size	     */
+#endif
+
+/* Print Buffer Size */
+#define CFG_PBSIZE	  (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+
+#define CFG_MAXARGS		32	/* max number of command args	*/
+
+#define CFG_BARGSIZE		CFG_CBSIZE /* Boot Argument Buffer Size	   */
+
+#define CFG_LOAD_ADDR		0x140000   /* default load address */
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_MEMTEST_START	0x2000	/* memtest works from the end of */
+					/* the exception vector table */
+					/* to the end of the DRAM  */
+					/* less monitor and malloc area */
+#define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
+#define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \
+				+ CFG_MALLOC_LEN \
+				+ CFG_ENV_SECT_SIZE \
+				+ CFG_STACK_USAGE )
+
+#define CFG_MEMTEST_END		( CFG_SDRAM_SIZE * 1024 * 1024 \
+				- CFG_MEM_END_USAGE )
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+/*
+ *  Attention: This is board specific
+ *  - RX clk is CLK11
+ *  - TX clk is CLK12
+ */
+#define CFG_CMXSCR_VALUE       (CMXSCR_RS1CS_CLK11  |\
+				CMXSCR_TS1CS_CLK12)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+/*
+ * Attention: this is board-specific
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+#define CFG_CMXFCR_MASK		(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+#define CFG_CPMFCR_RAMTYPE	0
+#define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#endif	/* CONFIG_ETHER_INDEX */
+
+#define CFG_FLASH_BASE	CFG_FLASH0_BASE
+#define CFG_FLASH_SIZE	CFG_FLASH0_SIZE
+#define CFG_SDRAM_BASE	CFG_SDRAM0_BASE
+#define CFG_SDRAM_SIZE	(CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+#if defined(CFG_PPMC_BOOT_LOW)
+#  define  CFG_PPMC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#else
+#  define  CFG_PPMC_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CFG_PPMC_BOOT_LOW) */
+
+/* get the HRCW ISB field from CFG_IMMR */
+#define CFG_PPMC_HRCW_IMMR	( ((CFG_IMMR & 0x10000000) >> 10) | \
+				  ((CFG_IMMR & 0x01000000) >>  7) | \
+				  ((CFG_IMMR & 0x00100000) >>  4) )
+
+#define CFG_HRCW_MASTER		( HRCW_EBM				| \
+				  HRCW_BPS11				| \
+				  HRCW_L2CPC10				| \
+				  HRCW_DPPC00				| \
+				  CFG_PPMC_HRCW_IMMR			| \
+				  HRCW_MMR00				| \
+				  HRCW_LBPC00				| \
+				  HRCW_APPC10				| \
+				  HRCW_CS10PC00				| \
+				  (CFG_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
+				  CFG_PPMC_HRCW_BOOT_FLAGS )
+
+/* no slaves */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ */
+#define CFG_MONITOR_BASE	CFG_FLASH0_BASE
+
+#ifndef CFG_MONITOR_BASE
+#define CFG_MONITOR_BASE	0x0ff80000
+#endif
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#  define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 374 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_FLASH_INCREMENT	0	/* there is only one bank		*/
+#define CFG_FLASH_PROTECTION	1	/* use hardware protection		*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
+
+
+#ifndef CFG_RAMBOOT
+
+#  define CFG_ENV_IS_IN_FLASH	1
+#  ifdef CFG_ENV_IN_OWN_SECT
+#    define CFG_ENV_ADDR	(CFG_MONITOR_BASE + 0x40000)
+#    define CFG_ENV_SECT_SIZE	0x40000
+#  else
+#    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
+#    define CFG_ENV_SIZE	0x1000	/* Total Size of Environment Sector	*/
+#    define CFG_ENV_SECT_SIZE	0x40000 /* see README - env sect real size	*/
+#  endif /* CFG_ENV_IN_OWN_SECT */
+
+#else
+#  define CFG_ENV_IS_IN_FLASH	1
+#  define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x40000)
+#define CFG_ENV_SIZE		0x1000
+#  define CFG_ENV_SECT_SIZE	0x40000
+#endif /* CFG_RAMBOOT */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT	(HID0_ICE  |\
+			 HID0_DCE  |\
+			 HID0_ICFI |\
+			 HID0_DCI  |\
+			 HID0_IFEM |\
+			 HID0_ABE)
+
+#define CFG_HID0_FINAL	(HID0_ICE  |\
+			 HID0_IFEM |\
+			 HID0_ABE  |\
+			 HID0_EMCP)
+#define CFG_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMR		0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR		(BCR_EBM      |\
+			 0x30000000)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ * Ref Section 4.3.2.6	page 4-31
+ *-----------------------------------------------------------------------
+ */
+
+#define CFG_SIUMCR	(SIUMCR_ESE	 |\
+			 SIUMCR_DPPC00	 |\
+			 SIUMCR_L2CPC10	 |\
+			 SIUMCR_LBPC00	 |\
+			 SIUMCR_APPC10	 |\
+			 SIUMCR_CS10PC00 |\
+			 SIUMCR_BCTLC00	 |\
+			 SIUMCR_MMR00)
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#define CFG_SYPCR	(SYPCR_SWTC |\
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWRI |\
+			 SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC	(TMCNTSC_SEC |\
+			 TMCNTSC_ALR |\
+			 TMCNTSC_TCF |\
+			 TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR	(PISCR_PS  |\
+			 PISCR_PTF |\
+			 PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SCCR	0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR	0
+
+/*
+ * Initialize Memory Controller:
+ *
+ * Bank Bus	Machine PortSz	Device
+ * ---- ---	------- ------	------
+ *  0	60x	GPCM	32 bit	FLASH (SIMM - 32MB) *
+ *  1	unused
+ *  2	60x	SDRAM	64 bit	SDRAM (DIMM - 128MB)
+ *  3	60x	SDRAM	64 bit	SDRAM (DIMM - 128MB)
+ *  4	Local	SDRAM	32 bit	SDRAM (on board - 16MB)
+ *  5	60x	GPCM	 8 bit	Mailbox/EEPROM (8KB)
+ *  6	60x	GPCM	 8 bit	FLASH  (on board - 2MB) *
+ *  7	60x	GPCM	 8 bit	LEDs, switches
+ *
+ *  (*) This configuration requires the PPMC8260 be configured
+ *	so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
+ *	the on board FLASH. In other words, JP24 should have
+ *	pins 1 and 2 jumpered and pins 3 and 4 jumpered.
+ *
+ */
+
+/*-----------------------------------------------------------------------
+ * BR0,BR1 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR0,OR1 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 0,1 - FLASH SIMM
+ *
+ * This expects the FLASH SIMM to be connected to *CS0
+ * It consists of 4 AM29F080B parts.
+ *
+ * Note: For the 4 MB SIMM, *CS1 is unused.
+ */
+
+/* BR0 is configured as follows:
+ *
+ *     - Base address of 0xFE000000
+ *     - 32 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR0_PRELIM	((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_32			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+/* OR0 is configured as follows:
+ *
+ *     - 32 MB
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 5
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+#define CFG_OR0_PRELIM	(MEG_TO_AM(CFG_FLASH0_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxG_TRLX			|\
+			 ORxG_EHTR)
+
+/*-----------------------------------------------------------------------
+ * BR2,BR3 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR2,OR3 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * Bank 2,3 - 128 MB SDRAM DIMM
+ */
+
+/* With a 128 MB DIMM, the BR2 is configured as follows:
+ *
+ *     - Base address of 0x00000000/0x08000000
+ *     - 64 bit port size (60x bus only)
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - SDRAM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR2_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+#define CFG_BR3_PRELIM	((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+/* With a 128 MB DIMM, the OR2 is configured as follows:
+ *
+ *     - 128 MB
+ *     - 4 internal banks per device
+ *     - Row start address bit is A8 with PSDMR[PBI] = 0
+ *     - 13 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+
+#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM0_SIZE)	|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A7		|\
+			 ORxS_NUMR_13)
+
+#define CFG_OR3_PRELIM	(MEG_TO_AM(CFG_SDRAM1_SIZE)	|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A7		|\
+			 ORxS_NUMR_13)
+
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x Bus SDRAM Mode Register
+ *     Ref: Section 10.3.3 on page 10-21
+ *-----------------------------------------------------------------------
+ */
+
+/* With a 128 MB DIMM, the PSDMR is configured as follows:
+ *
+ *     - Page Based Interleaving,
+ *     - Refresh Enable,
+ *     - Normal Operation
+ *     - Address Multiplexing where A5 is output on A14 pin
+ *	 (A6 on A15, and so on),
+ *     - use address pins A13-A15 as bank select,
+ *     - A9 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *	 is 3 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *	 2 clocks,
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - External Address Multiplexing enabled
+ *     - CAS Latency is 2.
+ */
+#define CFG_PSDMR	(PSDMR_RFEN	      |\
+			 PSDMR_SDAM_A14_IS_A5 |\
+			 PSDMR_BSMA_A13_A15   |\
+			 PSDMR_SDA10_PBI0_A9  |\
+			 PSDMR_RFRC_7_CLK     |\
+			 PSDMR_PRETOACT_3W    |\
+			 PSDMR_ACTTORW_2W     |\
+			 PSDMR_LDOTOPRE_1C    |\
+			 PSDMR_WRC_1C	      |\
+			 PSDMR_EAMUX	      |\
+			 PSDMR_CL_2)
+
+
+#define CFG_PSRT	0x0e
+#define CFG_MPTPR	MPTPR_PTP_DIV32
+
+
+/*-----------------------------------------------------------------------
+ * BR4 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR4 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * Bank 4 - On board SDRAM
+ *
+ */
+/* With 16 MB of onboard SDRAM	BR4 is configured as follows
+ *
+ *     - Base address 0x38000000
+ *     - 32 bit port size
+ *     - Data error checking disabled
+ *     - Read/Write access
+ *     - SDRAM local bus
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ *
+ */
+
+#define CFG_BR4_PRELIM	((CFG_SDRAM2_BASE & BRx_BA_MSK) |\
+			 BRx_PS_32			|\
+			 BRx_DECC_NONE			|\
+			 BRx_MS_SDRAM_L			|\
+			 BRx_V)
+
+/*
+ * With 16MB SDRAM, OR4 is configured as follows
+ *     - 4 internal banks per device
+ *     - Row start address bit is A10 with LSDMR[PBI] = 0
+ *     - 12 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+
+#define CFG_OR4_PRELIM	(MEG_TO_AM(CFG_SDRAM2_SIZE)	|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A10		|\
+			 ORxS_NUMR_12)
+
+
+/*-----------------------------------------------------------------------
+ * LSDMR - Local Bus SDRAM Mode Register
+ *     Ref: Section 10.3.4 on page 10-24
+ *-----------------------------------------------------------------------
+ */
+
+/* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
+ *
+ *     - Page Based Interleaving,
+ *     - Refresh Enable,
+ *     - Normal Operation
+ *     - Address Multiplexing where A5 is output on A13 pin
+ *	 (A6 on A15, and so on),
+ *     - use address pins A15-A17 as bank select,
+ *     - A11 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *	 is 2 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *	 2 clocks,
+ *     - SDRAM burst length is 8
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - External Address Multiplexing disabled
+ *     - CAS Latency is 2.
+ */
+#define CFG_LSDMR	(PSDMR_RFEN	      |\
+			 PSDMR_SDAM_A13_IS_A5 |\
+			 PSDMR_BSMA_A15_A17   |\
+			 PSDMR_SDA10_PBI0_A11 |\
+			 PSDMR_RFRC_7_CLK     |\
+			 PSDMR_PRETOACT_2W    |\
+			 PSDMR_ACTTORW_2W     |\
+			 PSDMR_BL	      |\
+			 PSDMR_LDOTOPRE_1C    |\
+			 PSDMR_WRC_1C	      |\
+			 PSDMR_CL_2)
+
+#define CFG_LSRT	0x0e
+
+/*-----------------------------------------------------------------------
+ * BR5 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR5 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * Bank 5 EEProm and Mailbox
+ *
+ * The EEPROM and mailbox live on the same chip select.
+ * the eeprom is selected if the MSb of the address is set and the mailbox is
+ * selected if the MSb of the address is clear.
+ *
+ */
+
+/* BR5 is configured as follows:
+ *
+ *     - Base address of 0x32000000/0xF2000000
+ *     - 8 bit
+ *     - Data error checking disabled
+ *     - Read/Write access
+ *     - GPCM 60x Bus
+ *     - SDRAM local bus
+ *     - No data pipelining is done
+ *     - Valid
+ */
+
+#define CFG_BR5_PRELIM	((CFG_MAILBOX_BASE & BRx_BA_MSK) |\
+			 BRx_PS_8			 |\
+			 BRx_DECC_NONE			 |\
+			 BRx_MS_GPCM_P			 |\
+			 BRx_V)
+/* OR5 is configured as follows
+ *     - buffer control enabled
+ *     - chip select negated normally
+ *     - CS output 1/2 clock after address
+ *     - 15 wait states
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+
+#define CFG_OR5_PRELIM ((P2SZ_TO_AM(CFG_MAILBOX_SIZE) & ~0x80000000) |\
+			 ORxG_ACS_DIV2				     |\
+			 ORxG_SCY_15_CLK			     |\
+			 ORxG_TRLX				     |\
+			 ORxG_EHTR)
+
+/*-----------------------------------------------------------------------
+ * BR6 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR6 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 6 - I/O select
+ *
+ */
+
+/* BR6 is configured as follows:
+ *
+ *     - Base address of 0xE0000000
+ *     - 16 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR6_PRELIM	((CFG_IOSELECT_BASE & BRx_BA_MSK) |\
+			   BRx_PS_16			  |\
+			   BRx_MS_GPCM_P		  |\
+			   BRx_V)
+
+/* OR6 is configured as follows
+ *     - buffer control enabled
+ *     - chip select negated normally
+ *     - CS output 1/2 clock after address
+ *     - 15 wait states
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+
+#define CFG_OR6_PRELIM (MEG_TO_AM(CFG_IOSELECT_SIZE) |\
+			 ORxG_ACS_DIV2		     |\
+			 ORxG_SCY_15_CLK	     |\
+			 ORxG_TRLX		     |\
+			 ORxG_EHTR)
+
+
+/*-----------------------------------------------------------------------
+ * BR7 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR7 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 7 - LEDs and switches
+ *
+ *  LEDs     are at 0x00001 (write only)
+ *  switches are at 0x00001 (read only)
+ */
+#ifdef CFG_LED_BASE
+
+/* BR7 is configured as follows:
+ *
+ *     - Base address of 0xA0000000
+ *     - 8 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR7_PRELIM	((CFG_LED_BASE & BRx_BA_MSK)	 |\
+			   BRx_PS_8			 |\
+			   BRx_DECC_NONE		 |\
+			   BRx_MS_GPCM_P		 |\
+			   BRx_V)
+
+/* OR7 is configured as follows:
+ *
+ *     - 1 byte
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 15
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+#define CFG_OR7_PRELIM	(ORxG_AM_MSK		       |\
+			 ORxG_CSNT		       |\
+			 ORxG_ACS_DIV1		       |\
+			 ORxG_SCY_15_CLK	       |\
+			 ORxG_TRLX		       |\
+			 ORxG_EHTR)
+#endif /* CFG_LED_BASE */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM	0x02	/* Software reboot		     */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/purple.h b/include/configs/purple.h
new file mode 100755
index 0000000..2ecb7fb
--- /dev/null
+++ b/include/configs/purple.h
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the PURPLE board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS32		1	/* MIPS 5Kc CPU core	*/
+#define CONFIG_PURPLE		1	/* on a PURPLE Board	*/
+
+#define CPU_CLOCK_RATE	125000000   /* 125 MHz clock for the MIPS core */
+#define ASC_CLOCK_RATE	 62500000   /* 62.5 MHz ASC clock              */
+
+#define INFINEON_EBU_BOOTCFG	0xE0CC
+
+#define CONFIG_STACKSIZE	(128 * 1024)
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BAUDRATE		19200
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0"				\
+	"addmisc=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate} "				\
+		"ethaddr=${ethaddr} "					\
+		"panic=1\0"						\
+	"flash_nfs=run nfsargs addip addmisc;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addmisc;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 80500000 ${bootfile};"				\
+		"run nfsargs addip addmisc;bootm\0"			\
+	"rootpath=/opt/eldk/mips_5KC\0"					\
+	"bootfile=/tftpboot/purple/uImage\0"				\
+	"kernel_addr=B0040000\0"					\
+	"ramdisk_addr=B0100000\0"					\
+	"u-boot=/tftpboot/purple/u-boot.bin\0"				\
+	"load=tftp 80500000 ${u-boot}\0"				\
+	"update=protect off 1:0-4;era 1:0-4;"				\
+		"cp.b 80500000 B0000000 ${filesize}\0"			\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_ELF)
+#include <cmd_confdefs.h>
+
+#define CFG_SDRAM_BASE		0x80000000
+
+#define CFG_INIT_SP_OFFSET      0x400000
+
+#define CFG_MALLOC_LEN		128*1024
+
+#define CFG_BOOTPARAMS_LEN	128*1024
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory      */
+#define	CFG_PROMPT		"PURPLE # "	/* Monitor Command Prompt    */
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size   */
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
+#define CFG_HZ			(CPU_CLOCK_RATE/2)
+#define	CFG_MAXARGS		16		/* max number of command args*/
+
+#define	CFG_LOAD_ADDR		0x80500000	/* default load address	*/
+
+#define CFG_MEMTEST_START	0x80200000
+#define CFG_MEMTEST_END		0x80800000
+
+#define	CONFIG_MISC_INIT_R
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	(35)	/* max number of sectors on one chip */
+
+#define PHYS_FLASH_1		0xb0000000 /* Flash Bank #1 */
+
+/* The following #defines are needed to get flash environment right */
+#define	CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MONITOR_LEN		(192 << 10)
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(6 * CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(6 * CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+
+/* Address and size of Primary Environment Sector	*/
+#define CFG_ENV_ADDR		0xB0008000
+#define CFG_ENV_SIZE		0x4000
+
+#define CONFIG_FLASH_32BIT
+#define CONFIG_NR_DRAM_BANKS	1
+
+#define CONFIG_PLB2800_ETHER
+#define CONFIG_NET_MULTI
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384
+#define CFG_ICACHE_SIZE		16384
+#define CFG_CACHELINE_SIZE	32
+
+/*
+ * Temporary buffer for serial data until the real serial driver
+ * is initialised (memtest will destroy this buffer)
+ */
+#define CFG_SCONSOLE_ADDR     (CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET - \
+			       CFG_DCACHE_SIZE / 2)
+#define CFG_SCONSOLE_SIZE     (CFG_DCACHE_SIZE / 4)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
new file mode 100755
index 0000000..e5e2772
--- /dev/null
+++ b/include/configs/pxa255_idp.h
@@ -0,0 +1,338 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copied from lubbock.h
+ *
+ * (C) Copyright 2004
+ * BEC Systems <http://bec-systems.com>
+ * Cliff Brake <cliff.brake@gmail.com>
+ * Configuation settings for the Accelent/Vibren PXA255 IDP
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/pxa-regs.h>
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#define CONFIG_INIT_CRITICAL			/* undef for developing */
+
+/*
+ * define the following to enable debug blinks.  A debug blink function
+ * must be defined in memsetup.S
+ */
+#undef DEBUG_BLINK_ENABLE
+#undef DEBUG_BLINKC_ENABLE
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA250		1	/* This is an PXA250 CPU    */
+
+#undef CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_SHARP_LM8V31
+#endif
+
+#define CONFIG_MMC		1
+#define BOARD_LATE_INIT		1
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * PXA250 IDP memory map information
+ */
+
+#define IDP_CS5_ETH_OFFSET	0x03400000
+
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE	(PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
+#define CONFIG_SMC_USE_32_BIT	1
+/* #define CONFIG_SMC_USE_IOFUNCS */
+
+/* the following has to be set high -- suspect something is wrong with
+ * with the tftp timeout routines. FIXME!!!
+ */
+#define CONFIG_NET_RETRY_COUNT	100
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART	       1       /* we use FFUART on LUBBOCK */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_DHCP )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTCOMMAND	"bootm 40000"
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
+#define CONFIG_CMDLINE_TAG
+
+/*
+ * Current memory map for Vibren supplied Linux images:
+ *
+ * Flash:
+ * 0 - 0x3ffff (size = 0x40000): bootloader
+ * 0x40000 - 0x13ffff (size = 0x100000): kernel
+ * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
+ *
+ * RAM:
+ * 0xa0008000 - kernel is loaded
+ * 0xa3000000 - Uboot runs (48MB into RAM)
+ *
+ */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"prog_boot_mmc="						\
+			"mw.b 0xa0000000 0xff 0x40000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0000000 u-boot.bin; "	\
+			"then "						\
+				"protect off 0x0 0x3ffff; "		\
+				"erase 0x0 0x3ffff; "			\
+				"cp.b 0xa0000000 0x0 0x40000; "		\
+				"reset;"				\
+			"fi\0"						\
+	"prog_uzImage_mmc="						\
+			"mw.b 0xa0000000 0xff 0x100000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0000000 uzImage; "	\
+			"then "						\
+				"protect off 0x40000 0xfffff; "		\
+				"erase 0x40000 0xfffff; "		\
+				"cp.b 0xa0000000 0x40000 0x100000; "	\
+			"fi\0"						\
+	"prog_jffs_mmc="						\
+			"mw.b 0xa0000000 0xff 0x1e00000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0000000 root.jffs; "	\
+			"then "						\
+				"protect off 0x140000 0x1f3ffff; "	\
+				"erase 0x140000 0x1f3ffff; "		\
+				"cp.b 0xa0000000 0x140000 0x1e00000; "	\
+			"fi\0"						\
+	"boot_mmc="							\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa1000000 uzImage && "	\
+			"then "						\
+				"bootm 0xa1000000; "			\
+			"fi\0"						\
+	"prog_boot_net="						\
+			"mw.b 0xa0000000 0xff 0x100000; "		\
+			"if	 bootp 0xa0000000 u-boot.bin; "		\
+			"then "						\
+				"protect off 0x0 0x3ffff; "		\
+				"erase 0x0 0x3ffff; "			\
+				"cp.b 0xa0000000 0x0 0x40000; "		\
+				"reset; "				\
+			"fi\0"						\
+	"prog_uzImage_net="						\
+			"mw.b 0xa0000000 0xff 0x100000; "		\
+			"if	 bootp 0xa0000000 uzImage; "		\
+			"then "						\
+				"protect off 0x40000 0xfffff; "		\
+				"erase 0x40000 0xfffff; "		\
+				"cp.b 0xa0000000 0x40000 0x100000; "	\
+			"fi\0"						\
+	"prog_jffs_net="						\
+			"mw.b 0xa0000000 0xff 0x1e00000; "		\
+			"if	 bootp 0xa0000000 root.jffs; "		\
+			"then "						\
+				"protect off 0x140000 0x1f3ffff; "	\
+				"erase 0x140000 0x1f3ffff; "		\
+				"cp.b 0xa0000000 0x140000 0x1e00000; "	\
+			"fi\0"
+
+
+/*	"erase_env="			*/
+/*			"protect off"	*/
+
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER		1
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#define CFG_LONGHELP				/* undef to save memory		*/
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT		"$ "		/* Monitor Command Prompt */
+#else
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_DEVICE_NULLDEV	1
+
+#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0xa0800000	/* default load address */
+
+#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
+
+#define RTC	1				/* enable 32KHz osc */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_MMC_BASE		0xF0000000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	4	   /* we have 1 banks of DRAM */
+#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
+#define PHYS_FLASH_SIZE		0x02000000 /* 32 MB */
+#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
+
+#define CFG_DRAM_BASE		0xa0000000
+#define CFG_DRAM_SIZE		0x04000000
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*
+ * GPIO settings
+ */
+
+#define CFG_GAFR0_L_VAL	0x80001005
+#define CFG_GAFR0_U_VAL	0xa5128012
+#define CFG_GAFR1_L_VAL	0x699a9558
+#define CFG_GAFR1_U_VAL	0xaaa5aa6a
+#define CFG_GAFR2_L_VAL	0xaaaaaaaa
+#define CFG_GAFR2_U_VAL	0x2
+#define CFG_GPCR0_VAL	0x1800400
+#define CFG_GPCR1_VAL	0x0
+#define CFG_GPCR2_VAL	0x0
+#define CFG_GPDR0_VAL	0xc1818440
+#define CFG_GPDR1_VAL	0xfcffab82
+#define CFG_GPDR2_VAL	0x1ffff
+#define CFG_GPSR0_VAL	0x8000
+#define CFG_GPSR1_VAL	0x3f0002
+#define CFG_GPSR2_VAL	0x1c000
+
+#define CFG_PSSR_VAL		0x20
+
+/*
+ * Memory settings
+ */
+#define CFG_MSC0_VAL		0x29DCA4D2
+#define CFG_MSC1_VAL		0x43AC494C
+#define CFG_MSC2_VAL		0x39D449D4
+#define CFG_MDCNFG_VAL		0x090009C9
+#define CFG_MDREFR_VAL		0x0085C017
+#define CFG_MDMRS_VAL		0x00220022
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL		0x00000003
+#define CFG_MCMEM0_VAL		0x00014405
+#define CFG_MCMEM1_VAL		0x00014405
+#define CFG_MCATT0_VAL		0x00014405
+#define CFG_MCATT1_VAL		0x00014405
+#define CFG_MCIO0_VAL		0x00014405
+#define CFG_MCIO1_VAL		0x00014405
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER	1
+
+#define CFG_MONITOR_BASE	0
+#define CFG_MONITOR_LEN		0x40000
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
+
+#define CFG_FLASH_USE_BUFFER_WRITE	1
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+
+/* put cfg at end of flash for now */
+#define CFG_ENV_IS_IN_FLASH	1
+ /* Addr of Environment Sector	*/
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
+#define CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SECT_SIZE	0x40000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/quantum.h b/include/configs/quantum.h
new file mode 100755
index 0000000..21ec5ac
--- /dev/null
+++ b/include/configs/quantum.h
@@ -0,0 +1,446 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ * changes for 16M board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#undef CONFIG_MPC860
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_RPXLITE		1	/* QUANTUM is the RPXlite clone */
+#define CONFIG_RMU		1   /* The QUNATUM is based on our RMU */
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+/* default developmenmt environment */
+
+#define CONFIG_ETHADDR 00:0B:17:00:00:00
+
+#define CONFIG_IPADDR  10.10.69.10
+#define CONFIG_SERVERIP 10.10.69.49
+#define CONFIG_NETMASK	255.255.255.0
+#define CONFIG_HOSTNAME QUANTUM
+#define CONFIG_ROOTPATH /opt/eldk/pcc_8xx
+
+#define CONFIG_BOOTARGS	 "root=/dev/ram rw"
+
+#define CONFIG_BOOTCOMMAND "bootm ff000000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+    "serial#=12345\0"		\
+	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
+	"ramargs=setenv bootargs root=/dev/ram rw\0" \
+    "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"
+
+/*
+ * Select the more full-featured memory test (Barr embedded systems)
+ */
+#define CFG_ALT_MEMTEST
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+
+/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
+#define CONFIG_RTC_M48T35A 1
+
+#if 0
+#define CONFIG_WATCHDOG 1		/* watchdog enabled		*/
+#else
+#undef CONFIG_WATCHDOG
+#endif
+
+/*  NVRAM and RTC */
+#define CFG_NVRAM_BASE_ADDR 0xFA000000
+#define CFG_NVRAM_SIZE 2048
+
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SNTP	)
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_AUTOBOOT_KEYED	/* Enable password protection */
+#define CONFIG_AUTOBOOT_PROMPT		"\nEnter password - autoboot in %d sec...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR	"system"
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00040000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x01f00000	/* 256K ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFA200000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE	0xFF000000
+
+#if 1
+    #define CFG_FLASH_CFI_DRIVER
+#else
+    #undef CFG_FLASH_CFI_DRIVER
+#endif
+
+
+#ifdef CFG_FLASH_CFI_DRIVER
+    #define CFG_FLASH_CFI 1
+    #undef CFG_FLASH_USE_BUFFER_WRITE
+    #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
+#endif
+
+/*%%% #define CFG_FLASH_BASE		0xFFF00000 */
+#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	0xFFF00000
+/*%%% #define CFG_MONITOR_BASE	CFG_FLASH_BASE */
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET	    0x00F40000	/*   Offset   of Environment Sector	absolute address 0xfff40000*/
+#define CFG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment Sector	*/
+#define CFG_ENV_SIZE		CFG_ENV_SECT_SIZE
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/* FPGA */
+#define CONFIG_MISC_INIT_R
+#define CFG_FPGA_SPARTAN2
+#define CFG_FPGA_PROG_FEEDBACK
+
+
+/*-----------------------------------------------------------------------
+ * Reset address
+ */
+#define CFG_RESET_ADDRESS	((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_MLRC10)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+/* up to 50 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+/* up to 50 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_COM00 | SCCR_TBS)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER 0x2002000F*/
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE_PRELIM	0xFE000000	/* FLASH base */
+#define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
+#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
+
+/*
+ * BR1 and OR1 (SDRAM)
+ *
+ */
+#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
+#define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000E00
+
+#define CFG_OR1_PRELIM	(0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
+#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/* RPXLITE mem setting */
+#define CFG_BR3_PRELIM	0xFA400001		/* FPGA */
+#define CFG_OR3_PRELIM	0xFFFF8910
+
+#define CFG_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
+#define CFG_OR4_PRELIM	0xFFFE0970
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	20
+
+/*
+ * Refresh clock Prescalar
+ */
+#define CFG_MPTPR	MPTPR_PTP_DIV2
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02	/* Software reboot			*/
+
+/*
+ * BCSRx
+ *
+ * Board Status and Control Registers
+ *
+ */
+
+#define BCSR0 0xFA400000
+#define BCSR1 0xFA400001
+#define BCSR2 0xFA400002
+#define BCSR3 0xFA400003
+
+#define BCSR0_ENMONXCVR 0x01	/* Monitor XVCR Control */
+#define BCSR0_ENNVRAM	0x02	/* CS4# Control */
+#define BCSR0_LED5	0x04	/* LED5 control 0='on' 1='off' */
+#define BCSR0_LED4	0x08	/* LED4 control 0='on' 1='off' */
+#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
+#define BCSR0_COLTEST	0x20
+#define BCSR0_ETHLPBK	0x40
+#define BCSR0_ETHEN	0x80
+
+#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
+#define BCSR1_PCVCTL6	0x02
+#define BCSR1_PCVCTL5	0x04
+#define BCSR1_PCVCTL4	0x08
+#define BCSR1_IPB5SEL	0x10
+
+#define BCSR2_ENPA5HDR	0x08	/* USB Control */
+#define BCSR2_ENUSBCLK	0x10
+#define BCSR2_USBPWREN	0x20
+#define BCSR2_USBSPD	0x40
+#define BCSR2_USBSUSP	0x80
+
+#define BCSR3_BWRTC	0x01	/* Real Time Clock Battery */
+#define BCSR3_BWNVR	0x02	/* NVRAM Battery */
+#define BCSR3_RDY_BSY	0x04	/* Flash Operation */
+#define BCSR3_RPXL	0x08	/* Reserved (reads back '1') */
+#define BCSR3_D27	0x10	/* Dip Switch settings */
+#define BCSR3_D26	0x20
+#define BCSR3_D25	0x40
+#define BCSR3_D24	0x80
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/rmu.h b/include/configs/rmu.h
new file mode 100755
index 0000000..b319cf4
--- /dev/null
+++ b/include/configs/rmu.h
@@ -0,0 +1,420 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#undef CONFIG_MPC860
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_RPXLITE		1	/* RMU is the RPXlite clone */
+#define CONFIG_RMU			1
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+
+#define CFG_I2C_SPEED		40000	/* 40 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+/* Software (bit-bang) I2C driver configuration */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+/* M41T11 Serial Access Timekeeper(R) SRAM */
+#define CONFIG_RTC_M41T11 1
+#define CFG_I2C_RTC_ADDR 0x68
+#define CFG_M41T11_BASE_YEAR 1900	/* play along with the linux driver */
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SNTP	)
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define	CONFIG_AUTOBOOT_KEYED		/* Enable password protection */
+#define	CONFIG_AUTOBOOT_PROMPT		"\nEnter password - autoboot in %d sec...\n"
+#define	CONFIG_AUTOBOOT_DELAY_STR	"system"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0040000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFA200000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		(0-flash_info[0].size)	/* Put flash at end	*/
+#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		((TEXT_BASE) + 0x40000)
+#define	CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Reset address
+ */
+#define	CFG_RESET_ADDRESS	((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_MLRC10)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+/* up to 50 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+/* up to 50 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_COM00 | SCCR_TBS)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE_PRELIM	0xFC000000	/* FLASH base - up to 64 MB of flash */
+#define CFG_PRELIM_OR_AM	0xFC000000	/* OR addr mask - map 64 MB */
+
+/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
+#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
+
+/*
+ * BR1 and OR1 (SDRAM)
+ *
+ */
+#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
+#define	SDRAM_MAX_SIZE		0x08000000	/* max 128 MB */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000E00
+
+#define CFG_OR1_PRELIM	(0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
+#define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/* RPXLITE mem setting */
+#define CFG_NVRAM_BASE	0xFA000000		/* NVRAM & SRAM base */
+/*      IMMR:		0xFA200000		   IMMR base address - see above */
+#define	CFG_BCSR_BASE	0xFA400000		/* BCSR base address */
+
+#define	CFG_BR3_PRELIM	(CFG_BCSR_BASE | BR_V)			/* BCSR */
+#define CFG_OR3_PRELIM	0xFFFF8910
+#define CFG_BR4_PRELIM  (CFG_NVRAM_BASE | BR_PS_8 | BR_V)	/* NVRAM & SRAM */
+#define CFG_OR4_PRELIM	0xFFFE0970
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	20
+
+/*
+ * Refresh clock Prescalar
+ */
+#define CFG_MPTPR	MPTPR_PTP_DIV2
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02	/* Software reboot			*/
+
+/*
+ * BCSRx
+ *
+ * Board Status and Control Registers
+ *
+ */
+
+#define BCSR0	(CFG_BCSR_BASE + 0)
+#define BCSR1	(CFG_BCSR_BASE + 1)
+#define BCSR2	(CFG_BCSR_BASE + 2)
+#define BCSR3	(CFG_BCSR_BASE + 3)
+
+#define BCSR0_ENMONXCVR	0x01	/* Monitor XVCR Control */
+#define BCSR0_ENNVRAM	0x02 	/* CS4# Control */
+#define BCSR0_LED5	0x04	/* LED5 control 0='on' 1='off' */
+#define BCSR0_LED4	0x08	/* LED4 control 0='on' 1='off' */
+#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
+#define BCSR0_COLTEST	0x20
+#define BCSR0_ETHLPBK	0x40
+#define BCSR0_ETHEN	0x80
+
+#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
+#define BCSR1_PCVCTL6	0x02
+#define BCSR1_PCVCTL5	0x04
+#define BCSR1_PCVCTL4	0x08
+#define BCSR1_IPB5SEL	0x10
+
+#define BCSR2_ENPA5HDR	0x08	/* USB Control */
+#define BCSR2_ENUSBCLK	0x10
+#define BCSR2_USBPWREN	0x20
+#define BCSR2_USBSPD	0x40
+#define BCSR2_USBSUSP	0x80
+
+#define BCSR3_BWRTC	0x01	/* Real Time Clock Battery */
+#define BCSR3_BWNVR	0x02	/* NVRAM Battery */
+#define BCSR3_RDY_BSY	0x04	/* Flash Operation */
+#define BCSR3_RPXL	0x08	/* Reserved (reads back '1') */
+#define BCSR3_D27	0x10	/* Dip Switch settings */
+#define BCSR3_D26	0x20
+#define BCSR3_D25	0x40
+#define BCSR3_D24	0x80
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h
new file mode 100755
index 0000000..6c9e392
--- /dev/null
+++ b/include/configs/rsdproto.h
@@ -0,0 +1,418 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the R&S Protocol Board board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
+#define CONFIG_RSD_PROTO	1	/* on a R&S Protocol Board      */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ */
+#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#define	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef 	CONFIG_CONS_NONE		/* define if console on neither */
+#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ethernet on SCC	*/
+#define	CONFIG_ETHER_ON_FCC		/* define if ethernet on FCC	*/
+#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */
+#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
+
+#if (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	(0)
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_INDEX */
+
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* enable I2C */
+#define CONFIG_HARD_I2C        	1	/* I2C with hardware support */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	50000000	/* in Hz */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL & ~CFG_CMD_KGDB)
+
+/* Define this if you want to boot from 0x00000100. If you don't define
+ * this, you will need to program the bootloader to 0xfff00000, and
+ * get the hardware reset config words at 0xfe000000. The simplest
+ * way to do that is to program the bootloader at both addresses.
+ * It is suggested that you just let U-Boot live at 0x00000000.
+ */
+#define CFG_RSD_BOOT_LOW 1
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOTARGS    	"devfs=mount root=ramfs"
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5a
+#define CONFIG_NETMASK          255.255.0.0
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000		/* decrementer freq: 1 ms ticks	*/
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_60X		0x00000000 /* SDRAM (60x Bus) */
+#define PHYS_SDRAM_60X_SIZE	0x08000000 /* 128 MB */
+
+#define PHYS_SDRAM_LOCAL	0x40000000 /* SDRAM (Local Bus) */
+#define PHYS_SDRAM_LOCAL_SIZE	0x04000000 /* 64 MB */
+
+#define PHYS_DPRAM_PCI       	0xE8000000 /* DPRAM PPC/PCI */
+#define PHYS_DPRAM_PCI_SIZE   	0x00020000 /* 128 KB */
+
+/*#define PHYS_DPRAM_PCI_SEM	0x04020000 / * DPRAM PPC/PCI Semaphore */
+/*#define PHYS_DPRAM_PCI_SEM_SIZE	0x00000001 / * 1 Byte */
+
+#define PHYS_DPRAM_SHARC       	0xE8100000 /* DPRAM PPC/Sharc */
+#define PHYS_DPRAM_SHARC_SIZE 	0x00040000 /* 256 KB */
+
+/*#define PHYS_DPRAM_SHARC_SEM	0x04140000 / * DPRAM PPC/Sharc Semaphore */
+/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
+
+#define PHYS_VIRTEX_REGISTER    0xE8300000 /* FPGA implemented register */
+#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100
+
+#define PHYS_USB		0x04200000 /* USB Controller (60x Bus) */
+#define PHYS_USB_SIZE		0x00000002 /* 2 Bytes */
+
+#define PHYS_IMMR		0xF0000000 /* Internal Memory Mapped Reg. */
+
+#define PHYS_FLASH		0xFF000000 /* Flash (60x Bus) */
+#define PHYS_FLASH_SIZE		0x01000000 /* 16 MB */
+
+#define CFG_IMMR		PHYS_IMMR
+
+/*-----------------------------------------------------------------------
+ * Reset Address
+ *
+ * In order to reset the CPU, U-Boot jumps to a special address which
+ * causes a machine check exception. The default address for this is
+ * CFG_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
+ * testing the monitor in RAM using a JTAG debugger.
+ *
+ * Just set CFG_RESET_ADDRESS to an address that you know is sure to
+ * cause a bus error on your hardware.
+ */
+#define CFG_RESET_ADDRESS	0x20000000
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+
+#if defined(CFG_RSD_BOOT_LOW)
+#  define  CFG_RSD_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#else
+#  define  CFG_RSD_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CFG_RSD_BOOT_LOW) */
+
+/* get the HRCW ISB field from CFG_IMMR */
+#define CFG_RSD_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
+			    ((CFG_IMMR & 0x01000000) >> 7)  |\
+			    ((CFG_IMMR & 0x00100000) >> 4) )
+
+#define CFG_HRCW_MASTER	(HRCW_L2CPC10 | \
+			 HRCW_DPPC11 | \
+			 CFG_RSD_HRCW_IMMR |\
+			 HRCW_MMR00 | \
+			 HRCW_APPC10 | \
+			 HRCW_CS10PC00 | \
+			 HRCW_MODCK_H0000 |\
+			 CFG_RSD_HRCW_BOOT_FLAGS)
+
+/* no slaves */
+#define CFG_HRCW_SLAVE1	0
+#define CFG_HRCW_SLAVE2	0
+#define CFG_HRCW_SLAVE3	0
+#define CFG_HRCW_SLAVE4	0
+#define CFG_HRCW_SLAVE5	0
+#define CFG_HRCW_SLAVE6	0
+#define CFG_HRCW_SLAVE7	0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CFG_RAMBOOT is platform dependend.
+ */
+#define	CFG_SDRAM_BASE		PHYS_SDRAM_60X
+#define CFG_FLASH_BASE		PHYS_FLASH
+/*#define	CFG_MONITOR_BASE	0x200000 */
+#define	CFG_MONITOR_BASE	CFG_FLASH_BASE
+#if CFG_MONITOR_BASE < CFG_FLASH_BASE
+#define CFG_RAMBOOT
+#endif
+#define	CFG_MONITOR_LEN		(160 << 10)	/* Reserve 160 kB for Monitor	*/
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	63	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	12000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	3000	/* Timeout for Flash Write (in ms)	*/
+
+/* turn off NVRAM env feature */
+#undef CONFIG_NVRAM_ENV
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR	(PHYS_FLASH + 0x28000)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	0x8000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
+#define CFG_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
+#define CFG_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMR		0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR		0x100c0000
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+
+#define CFG_SIUMCR	(SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
+					 SIUMCR_CS10PC01 | SIUMCR_BCTLC01)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
+			 SYPCR_SWRI | SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC	(TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SCCR	0x00000000
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR	0
+
+/*
+ * Init Memory Controller:
+ */
+
+#define CFG_PSDMR	0x494D2452
+#define CFG_LSDMR	0x49492552
+
+/* Flash */
+#define CFG_BR0_PRELIM	(PHYS_FLASH | BRx_V)
+#define CFG_OR0_PRELIM	(P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
+			 ORxG_BCTLD | \
+			 ORxG_SCY_5_CLK)
+
+/* DPRAM to the PCI BUS on the protocol board */
+#define CFG_BR1_PRELIM	(PHYS_DPRAM_PCI | BRx_V)
+#define CFG_OR1_PRELIM	(P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
+			 ORxG_ACS_DIV4)
+
+/* 60x Bus SDRAM */
+#define CFG_BR2_PRELIM	(PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
+#define CFG_OR2_PRELIM	(ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
+			 ORxS_BPD_4 | \
+			 ORxS_ROWST_PBI1_A2 | \
+			 ORxS_NUMR_13 | \
+			 ORxS_IBID)
+
+/* Virtex-FPGA - Register */
+#define CFG_BR3_PRELIM  (PHYS_VIRTEX_REGISTER | BRx_V)
+#define CFG_OR3_PRELIM  (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
+			 ORxG_SCY_1_CLK | \
+			 ORxG_ACS_DIV2 | \
+			 ORxG_CSNT )
+
+/* local bus SDRAM */
+#define CFG_BR4_PRELIM	(PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
+#define CFG_OR4_PRELIM	(ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
+			 ORxS_BPD_4 | \
+			 ORxS_ROWST_PBI1_A4 | \
+			 ORxS_NUMR_13)
+
+/* DPRAM to the Sharc-Bus on the protocol board */
+#define CFG_BR5_PRELIM	(PHYS_DPRAM_SHARC | BRx_V)
+#define CFG_OR5_PRELIM	(P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
+			 ORxG_ACS_DIV4)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
new file mode 100755
index 0000000..4e0cfdb
--- /dev/null
+++ b/include/configs/sacsng.h
@@ -0,0 +1,1074 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * Configuration settings for the WindRiver SBC8260 board.
+ *	See http://www.windriver.com/products/html/sbc8260.html
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG		      /* General debug */
+#undef DEBUG_BOOTP_EXT	      /* Debug received vendor fields */
+
+#undef CONFIG_LOGBUFFER       /* External logbuffer support */
+
+/*****************************************************************************
+ *
+ * These settings must match the way _your_ board is set up
+ *
+ *****************************************************************************/
+
+/* What is the oscillator's (UX2) frequency in Hz? */
+#define CONFIG_8260_CLKIN  66666600
+
+/*-----------------------------------------------------------------------
+ * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
+ *-----------------------------------------------------------------------
+ * What should MODCK_H be? It is dependent on the oscillator
+ * frequency, MODCK[1-3], and desired CPM and core frequencies.
+ * Here are some example values (all frequencies are in MHz):
+ *
+ * MODCK_H   MODCK[1-3]	 Osc	CPM    Core  S2-6   S2-7   S2-8
+ * -------   ----------	 ---	---    ----  -----  -----  -----
+ * 0x1	     0x5	 33	100    133   Open   Close  Open
+ * 0x1	     0x6	 33	100    166   Open   Open   Close
+ * 0x1	     0x7	 33	100    200   Open   Open   Open
+ *
+ * 0x2	     0x2	 33	133    133   Close  Open   Close
+ * 0x2	     0x3	 33	133    166   Close  Open   Open
+ * 0x2	     0x4	 33	133    200   Open   Close  Close
+ * 0x2	     0x5	 33	133    233   Open   Close  Open
+ * 0x2	     0x6	 33	133    266   Open   Open   Close
+ *
+ * 0x5	     0x5	 66	133    133   Open   Close  Open
+ * 0x5	     0x6	 66	133    166   Open   Open   Close
+ * 0x5	     0x7	 66	133    200   Open   Open   Open
+ * 0x6	     0x0	 66	133    233   Close  Close  Close
+ * 0x6	     0x1	 66	133    266   Close  Close  Open
+ * 0x6	     0x2	 66	133    300   Close  Open   Close
+ */
+#define CFG_SBC_MODCK_H 0x05
+
+/* Define this if you want to boot from 0x00000100. If you don't define
+ * this, you will need to program the bootloader to 0xfff00000, and
+ * get the hardware reset config words at 0xfe000000. The simplest
+ * way to do that is to program the bootloader at both addresses.
+ * It is suggested that you just let U-Boot live at 0x00000000.
+ */
+#define CFG_SBC_BOOT_LOW 1
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)?  This must contain TEXT_BASE from board/sacsng/config.mk
+ * The main FLASH is whichever is connected to *CS0.
+ */
+#define CFG_FLASH0_BASE 0x40000000
+#define CFG_FLASH0_SIZE 2
+
+/* What should the base address of the secondary FLASH be and how big
+ * is it (in Mbytes)?  The secondary FLASH is whichever is connected
+ * to *CS6.
+ */
+#define CFG_FLASH1_BASE 0x60000000
+#define CFG_FLASH1_SIZE 2
+
+/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
+ */
+#define CONFIG_VERY_BIG_RAM	1
+
+/* What should be the base address of SDRAM DIMM and how big is
+ * it (in Mbytes)?  This will normally auto-configure via the SPD.
+*/
+#define CFG_SDRAM0_BASE 0x00000000
+#define CFG_SDRAM0_SIZE 64
+
+/*
+ * Memory map example with 64 MB DIMM:
+ *
+ *     0x0000 0000     Exception Vector code, 8k
+ *	     :
+ *     0x0000 1FFF
+ *     0x0000 2000     Free for Application Use
+ *	     :
+ *	     :
+ *
+ *	     :
+ *	     :
+ *     0x03F5 FF30     Monitor Stack (Growing downward)
+ *		       Monitor Stack Buffer (0x80)
+ *     0x03F5 FFB0     Board Info Data
+ *     0x03F6 0000     Malloc Arena
+ *	     :		    CFG_ENV_SECT_SIZE, 16k
+ *	     :		    CFG_MALLOC_LEN,    128k
+ *     0x03FC 0000     RAM Copy of Monitor Code
+ *	     :		    CFG_MONITOR_LEN,   256k
+ *     0x03FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
+ */
+
+#define CONFIG_POST		(CFG_POST_MEMORY | \
+				 CFG_POST_CPU)
+
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ */
+#define CONFIG_CONS_ON_SMC	1	/* define if console on SMC */
+#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on neither */
+#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+
+#undef	CONFIG_ETHER_ON_SCC
+#define CONFIG_ETHER_ON_FCC
+#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */
+
+#ifdef	CONFIG_ETHER_ON_SCC
+#define CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
+#endif	/* CONFIG_ETHER_ON_SCC */
+
+#ifdef	CONFIG_ETHER_ON_FCC
+#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
+#undef  CONFIG_ETHER_LOOPBACK_TEST      /* Ethernet external loopback test */
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+/*
+ * Port pins used for bit-banged MII communictions (if applicable).
+ */
+
+#define MDIO_PORT	2	        /* Port A=0, B=1, C=2, D=3 */
+#define MDIO_ACTIVE	(iop->pdir |=  0x40000000)
+#define MDIO_TRISTATE	(iop->pdir &= ~0x40000000)
+#define MDIO_READ	((iop->pdat &  0x40000000) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  0x40000000; \
+			else	iop->pdat &= ~0x40000000
+
+#define MDC(bit)	if(bit) iop->pdat |=  0x80000000; \
+			else	iop->pdat &= ~0x80000000
+
+#define MIIDELAY	udelay(50)
+#endif	/* CONFIG_ETHER_ON_FCC */
+
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+
+/*
+ *  - RX clk is CLK11
+ *  - TX clk is CLK12
+ */
+# define CFG_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11  | CMXSCR_TS1CS_CLK12)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1	/* boot progress enabled	*/
+
+/*
+ * Configure for RAM tests.
+ */
+#undef  CFG_DRAM_TEST			/* calls other tests in board.c	*/
+
+
+/*
+ * Status LED for power up status feedback.
+ */
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#define STATUS_LED_PAR		im_ioport.iop_ppara
+#define STATUS_LED_DIR		im_ioport.iop_pdira
+#define STATUS_LED_ODR		im_ioport.iop_podra
+#define STATUS_LED_DAT		im_ioport.iop_pdata
+
+#define STATUS_LED_BIT		0x00000800	/* LED 0 is on PA.20	*/
+#define STATUS_LED_PERIOD	(CFG_HZ)
+#define STATUS_LED_STATE	STATUS_LED_OFF
+#define STATUS_LED_BIT1		0x00001000	/* LED 1 is on PA.19	*/
+#define STATUS_LED_PERIOD1	(CFG_HZ)
+#define STATUS_LED_STATE1	STATUS_LED_OFF
+#define STATUS_LED_BIT2		0x00002000	/* LED 2 is on PA.18	*/
+#define STATUS_LED_PERIOD2	(CFG_HZ/2)
+#define STATUS_LED_STATE2	STATUS_LED_ON
+
+#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+
+#define STATUS_LED_YELLOW	0
+#define STATUS_LED_GREEN	1
+#define STATUS_LED_RED		2
+#define STATUS_LED_BOOT		1
+
+
+/*
+ * Select SPI support configuration
+ */
+#define CONFIG_SOFT_SPI		/* Enable SPI driver */
+#define MAX_SPI_BYTES   4	/* Maximum number of bytes we can handle */
+#undef  DEBUG_SPI               /* Disable SPI debugging */
+
+/*
+ * Software (bit-bang) SPI driver configuration
+ */
+#ifdef CONFIG_SOFT_SPI
+
+/*
+ * Software (bit-bang) SPI driver configuration
+ */
+#define I2C_SCLK	0x00002000      /* PD 18: Shift clock */
+#define I2C_MOSI	0x00004000      /* PD 17: Master Out, Slave In */
+#define I2C_MISO	0x00008000      /* PD 16: Master In, Slave Out */
+
+#undef  SPI_INIT			/* no port initialization needed */
+#define SPI_READ        ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
+#define SPI_SDA(bit)    if(bit) immr->im_ioport.iop_pdatd |=  I2C_MOSI; \
+			else    immr->im_ioport.iop_pdatd &= ~I2C_MOSI
+#define SPI_SCL(bit)    if(bit) immr->im_ioport.iop_pdatd |=  I2C_SCLK; \
+			else    immr->im_ioport.iop_pdatd &= ~I2C_SCLK
+#define SPI_DELAY                       /* No delay is needed */
+#endif /* CONFIG_SOFT_SPI */
+
+
+/*
+ * select I2C support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#ifdef CONFIG_SOFT_I2C
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(20)	/* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+/* Define this to reserve an entire FLASH sector for
+ * environment variables. Otherwise, the environment will be
+ * put in the same sector as U-Boot, and changing variables
+ * will erase U-Boot temporarily
+ */
+#define CFG_ENV_IN_OWN_SECT	1
+
+/* Define this to contain any number of null terminated strings that
+ * will be part of the default enviroment compiled into the boot image.
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+"quiet=0\0" \
+"serverip=192.168.123.205\0" \
+"ipaddr=192.168.123.203\0" \
+"checkhostname=VR8500\0" \
+"reprog="\
+    "bootp; " \
+    "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
+    "protect off 60000000 6003FFFF; " \
+    "erase 60000000 6003FFFF; " \
+    "cp.b 140000 60000000 ${filesize}; " \
+    "protect on 60000000 6003FFFF\0" \
+"copyenv="\
+    "protect off 60040000 6004FFFF; " \
+    "erase 60040000 6004FFFF; " \
+    "cp.b 40040000 60040000 10000; " \
+    "protect on 60040000 6004FFFF\0" \
+"copyprog="\
+    "protect off 60000000 6003FFFF; " \
+    "erase 60000000 6003FFFF; " \
+    "cp.b 40000000 60000000 40000; " \
+    "protect on 60000000 6003FFFF\0" \
+"zapenv="\
+    "protect off 40040000 4004FFFF; " \
+    "erase 40040000 4004FFFF; " \
+    "protect on 40040000 4004FFFF\0" \
+"zapotherenv="\
+    "protect off 60040000 6004FFFF; " \
+    "erase 60040000 6004FFFF; " \
+    "protect on 60040000 6004FFFF\0" \
+"root-on-initrd="\
+    "setenv bootcmd "\
+    "version\\;" \
+    "echo\\;" \
+    "bootp\\;" \
+    "setenv bootargs root=/dev/ram0 rw quiet " \
+    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
+    "run boot-hook\\;" \
+    "bootm\0" \
+"root-on-initrd-debug="\
+    "setenv bootcmd "\
+    "version\\;" \
+    "echo\\;" \
+    "bootp\\;" \
+    "setenv bootargs root=/dev/ram0 rw debug " \
+    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
+    "run debug-hook\\;" \
+    "run boot-hook\\;" \
+    "bootm\0" \
+"root-on-nfs="\
+    "setenv bootcmd "\
+    "version\\;" \
+    "echo\\;" \
+    "bootp\\;" \
+    "setenv bootargs root=/dev/nfs rw quiet " \
+    "nfsroot=\\${serverip}:\\${rootpath} " \
+    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
+    "run boot-hook\\;" \
+    "bootm\0" \
+"root-on-nfs-debug="\
+    "setenv bootcmd "\
+    "version\\;" \
+    "echo\\;" \
+    "bootp\\;" \
+    "setenv bootargs root=/dev/nfs rw debug " \
+    "nfsroot=\\${serverip}:\\${rootpath} " \
+    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
+    "run debug-hook\\;" \
+    "run boot-hook\\;" \
+    "bootm\0" \
+"debug-checkout="\
+    "setenv checkhostname;" \
+    "setenv ethaddr 00:09:70:00:00:01;" \
+    "bootp;" \
+    "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
+    "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+    "run debug-hook;" \
+    "run boot-hook;" \
+    "bootm\0" \
+"debug-hook="\
+    "echo ipaddr    ${ipaddr};" \
+    "echo serverip  ${serverip};" \
+    "echo gatewayip ${gatewayip};" \
+    "echo netmask   ${netmask};" \
+    "echo hostname  ${hostname}\0" \
+"ana=run adc ; run dac\0" \
+"adc=run adc-12 ; run adc-34\0" \
+"adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \
+"adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \
+"dac=echo ### DAC ; imd.b 11 81 5\0" \
+"boot-hook=echo\0"
+
+/* What should the console's baud rate be? */
+#define CONFIG_BAUDRATE		9600
+
+/* Ethernet MAC address */
+#define CONFIG_ETHADDR		00:09:70:00:00:00
+
+/* The default Ethernet MAC address can be overwritten just once  */
+#ifdef  CONFIG_ETHADDR
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+#endif
+
+/*
+ * Define this to do some miscellaneous board-specific initialization.
+ */
+#define CONFIG_MISC_INIT_R
+
+/* Set to a positive value to delay for running BOOTCOMMAND */
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second */
+
+/* Be selective on what keys can delay or stop the autoboot process
+ *     To stop	use: " "
+ */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+#undef  CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define DEBUG_BOOTKEYS		0
+
+/* Define a command string that is automatically executed when no character
+ * is read on the console interface withing "Boot Delay" after reset.
+ */
+#undef	CONFIG_BOOT_ROOT_INITRD 	/* Use ram disk for the root file system */
+#define	CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
+
+#ifdef CONFIG_BOOT_ROOT_INITRD
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/ram0 rw quiet " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+	"run boot-hook;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_INITRD */
+
+#ifdef CONFIG_BOOT_ROOT_NFS
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+	"run boot-hook;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_NFS */
+
+#define CONFIG_BOOTP_RANDOM_DELAY       /* Randomize the BOOTP retry delay */
+
+/* Add support for a few extra bootp options like:
+ *	- File size
+ *	- DNS (up to 2 servers)
+ *      - Send hostname to DHCP server
+ */
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE | \
+				 CONFIG_BOOTP_DNS | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME)
+
+/* undef this to save memory */
+#define CFG_LONGHELP
+
+/* Monitor Command Prompt */
+#define CFG_PROMPT		"=> "
+
+#undef  CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2     "> "
+#endif
+
+/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
+ * of an image is printed by image commands like bootm or iminfo.
+ */
+#define CONFIG_TIMESTAMP
+
+/* If this variable is defined, an environment variable named "ver"
+ * is created by U-Boot showing the U-Boot version.
+ */
+#define CONFIG_VERSION_VARIABLE
+
+/* What U-Boot subsytems do you want enabled? */
+#ifdef CONFIG_ETHER_ON_FCC
+# define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
+				CFG_CMD_ELF	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_ECHO	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_SPI	| \
+				CFG_CMD_SDRAM   | \
+				CFG_CMD_REGINFO | \
+				CFG_CMD_IMMAP	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_MII	)
+#else
+# define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
+				CFG_CMD_ELF	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_ECHO	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_SPI	| \
+				CFG_CMD_SDRAM   | \
+				CFG_CMD_REGINFO | \
+				CFG_CMD_IMMAP	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_PING	)
+#endif /* CONFIG_ETHER_ON_FCC */
+
+/* Where do the internal registers live? */
+#define CFG_IMMR		0xF0000000
+
+#undef	CONFIG_WATCHDOG			/* disable the watchdog */
+
+/*****************************************************************************
+ *
+ * You should not have to modify any of the following settings
+ *
+ *****************************************************************************/
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
+#define CONFIG_SBC8260		1	/* on an EST SBC8260 Board  */
+#define CONFIG_SACSng		1	/* munged for the SACSng */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_BOOTM_HEADER_QUIET 1        /* Suppress the image header dump    */
+					/* in the bootm command.             */
+#define CFG_BOOTM_PROGESS_QUIET 1       /* Suppress the progress displays,   */
+					/* "## <message>" from the bootm cmd */
+#define CFG_BOOTP_CHECK_HOSTNAME 1      /* If checkhostname environment is   */
+					/* defined, then the hostname param  */
+					/* validated against checkhostname.  */
+#define CFG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up   */
+#define CFG_BOOTP_SHORT_RANDOM_DELAY 1  /* Use a short random delay value    */
+					/* (limited to maximum of 1024 msec) */
+#define CFG_CHK_FOR_ABORT_AT_LEAST_ONCE 1
+					/* Check for abort key presses       */
+					/* at least once in dependent of the */
+					/* CONFIG_BOOTDELAY value.           */
+#define CFG_CONSOLE_INFO_QUIET 1        /* Don't print console @ startup     */
+#define CFG_FAULT_ECHO_LINK_DOWN 1      /* Echo the inverted Ethernet link   */
+					/* state to the fault LED.           */
+#define CFG_FAULT_MII_ADDR 0x02         /* MII addr of the PHY to check for  */
+					/* the Ethernet link state.          */
+#define CFG_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing  */
+					/* until the TFTP is successful.     */
+#define CFG_STATUS_OFF_AFTER_NETBOOT 1  /* After a successful netboot,       */
+					/* turn off the STATUS LEDs.         */
+#define CFG_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on      */
+					/* incoming data.                    */
+#define CFG_TFTP_BLOCKS_PER_HASH 100    /* For every XX blocks, output a '#' */
+					/* to signify that tftp is moving.   */
+#define CFG_TFTP_HASHES_PER_FLASH 200   /* For every '#' hashes,             */
+					/* flash the status LED.             */
+#define CFG_TFTP_HASHES_PER_LINE 65     /* Only output XX '#'s per line      */
+					/* during the tftp file transfer.    */
+#define CFG_TFTP_PROGESS_QUIET 1        /* Suppress the progress displays    */
+					/* '#'s from the tftp command.       */
+#define CFG_TFTP_STATUS_QUIET 1         /* Suppress the status displays      */
+					/* issued during the tftp command.   */
+#define CFG_TFTP_TIMEOUT_COUNT 5        /* How many timeouts TFTP will allow */
+					/* before it gives up.               */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size	     */
+#else
+#  define CFG_CBSIZE		256	/* Console I/O Buffer Size	     */
+#endif
+
+/* Print Buffer Size */
+#define CFG_PBSIZE	  (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+
+#define CFG_MAXARGS		32	/* max number of command args	*/
+
+#define CFG_BARGSIZE		CFG_CBSIZE /* Boot Argument Buffer Size	   */
+
+#define CFG_LOAD_ADDR		0x400000   /* default load address */
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_ALT_MEMTEST                 /* Select full-featured memory test */
+#define CFG_MEMTEST_START	0x2000	/* memtest works from the end of */
+					/* the exception vector table */
+					/* to the end of the DRAM  */
+					/* less monitor and malloc area */
+#define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
+#define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \
+				+ CFG_MALLOC_LEN \
+				+ CFG_ENV_SECT_SIZE \
+				+ CFG_STACK_USAGE )
+
+#define CFG_MEMTEST_END		( CFG_SDRAM_SIZE * 1024 * 1024 \
+				- CFG_MEM_END_USAGE )
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_FLASH_BASE	CFG_FLASH0_BASE
+#define CFG_FLASH_SIZE	CFG_FLASH0_SIZE
+#define CFG_SDRAM_BASE	CFG_SDRAM0_BASE
+#define CFG_SDRAM_SIZE	CFG_SDRAM0_SIZE
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+#if defined(CFG_SBC_BOOT_LOW)
+#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#else
+#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CFG_SBC_BOOT_LOW) */
+
+/* get the HRCW ISB field from CFG_IMMR */
+#define CFG_SBC_HRCW_IMMR	( ((CFG_IMMR & 0x10000000) >> 10) | \
+				  ((CFG_IMMR & 0x01000000) >>  7) | \
+				  ((CFG_IMMR & 0x00100000) >>  4) )
+
+#define CFG_HRCW_MASTER		( HRCW_BPS10				| \
+				  HRCW_DPPC11				| \
+				  CFG_SBC_HRCW_IMMR			| \
+				  HRCW_MMR00				| \
+				  HRCW_LBPC11				| \
+				  HRCW_APPC10				| \
+				  HRCW_CS10PC00				| \
+				  (CFG_SBC_MODCK_H & HRCW_MODCK_H1111)	| \
+				  CFG_SBC_HRCW_BOOT_FLAGS )
+
+/* no slaves */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ */
+#define CFG_MONITOR_BASE	CFG_FLASH0_BASE
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#  define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#undef  CFG_FLASH_PROTECTION		/* use hardware protection		*/
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	(64+4)	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms)	*/
+
+#ifndef CFG_RAMBOOT
+#  define CFG_ENV_IS_IN_FLASH	1
+
+#  ifdef CFG_ENV_IN_OWN_SECT
+#    define CFG_ENV_ADDR	(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#    define CFG_ENV_SECT_SIZE	0x10000
+#  else
+#    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
+#    define CFG_ENV_SIZE	0x1000	/* Total Size of Environment Sector	*/
+#    define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sect real size	*/
+#  endif /* CFG_ENV_IN_OWN_SECT */
+
+#else
+#  define CFG_ENV_IS_IN_NVRAM	1
+#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#  define CFG_ENV_SIZE		0x200
+#endif /* CFG_RAMBOOT */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT	(HID0_ICE  |\
+			 HID0_DCE  |\
+			 HID0_ICFI |\
+			 HID0_DCI  |\
+			 HID0_IFEM |\
+			 HID0_ABE)
+
+#define CFG_HID0_FINAL	(HID0_ICE  |\
+			 HID0_IFEM |\
+			 HID0_ABE  |\
+			 HID0_EMCP)
+#define CFG_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMR		0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR		(BCR_ETM)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+
+#define CFG_SIUMCR	(SIUMCR_DPPC11	|\
+			 SIUMCR_L2CPC00 |\
+			 SIUMCR_APPC10	|\
+			 SIUMCR_MMR00)
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC |\
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWRI |\
+			 SYPCR_SWP  |\
+			 SYPCR_SWE)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC |\
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWRI |\
+			 SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC	(TMCNTSC_SEC |\
+			 TMCNTSC_ALR |\
+			 TMCNTSC_TCF |\
+			 TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR	(PISCR_PS  |\
+			 PISCR_PTF |\
+			 PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SCCR	0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR	0
+
+/*
+ * Initialize Memory Controller:
+ *
+ * Bank Bus	Machine PortSz	Device
+ * ---- ---	------- ------	------
+ *  0	60x	GPCM	16 bit	FLASH (primary flash - 2MB)
+ *  1	60x	GPCM	-- bit	(Unused)
+ *  2	60x	SDRAM	64 bit	SDRAM (DIMM)
+ *  3	60x	SDRAM	64 bit	SDRAM (DIMM)
+ *  4	60x	GPCM	-- bit	(Unused)
+ *  5	60x	GPCM	-- bit	(Unused)
+ *  6	60x	GPCM	16 bit	FLASH  (secondary flash - 2MB)
+ */
+
+/*-----------------------------------------------------------------------
+ * BR0,BR1 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR0,OR1 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 0 - Primary FLASH
+ */
+
+/* BR0 is configured as follows:
+ *
+ *     - Base address of 0x40000000
+ *     - 16 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR0_PRELIM	((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+/* OR0 is configured as follows:
+ *
+ *     - 4 MB
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 5
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+#define CFG_OR0_PRELIM	(MEG_TO_AM(CFG_FLASH0_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxG_TRLX			|\
+			 ORxG_EHTR)
+
+/*-----------------------------------------------------------------------
+ * BR2,BR3 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR2,OR3 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 2,3 - SDRAM DIMM
+ */
+
+/* The BR2 is configured as follows:
+ *
+ *     - Base address of 0x00000000
+ *     - 64 bit port size (60x bus only)
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - SDRAM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR2_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+#define CFG_BR3_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+/* With a 64 MB DIMM, the OR2 is configured as follows:
+ *
+ *     - 64 MB
+ *     - 4 internal banks per device
+ *     - Row start address bit is A8 with PSDMR[PBI] = 0
+ *     - 12 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+#if (CFG_SDRAM0_SIZE == 64)
+#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM0_SIZE)	|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A8		|\
+			 ORxS_NUMR_12)
+#else
+#error "INVALID SDRAM CONFIGURATION"
+#endif
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x Bus SDRAM Mode Register
+ *     Ref: Section 10.3.3 on page 10-21
+ *-----------------------------------------------------------------------
+ */
+
+/* Address that the DIMM SPD memory lives at.
+ */
+#define SDRAM_SPD_ADDR 0x50
+
+#if (CFG_SDRAM0_SIZE == 64)
+/* With a 64 MB DIMM, the PSDMR is configured as follows:
+ *
+ *     - Bank Based Interleaving,
+ *     - Refresh Enable,
+ *     - Address Multiplexing where A5 is output on A14 pin
+ *	 (A6 on A15, and so on),
+ *     - use address pins A14-A16 as bank select,
+ *     - A9 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *	 is 3 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *	 2 clocks,
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - CAS Latency is 2.
+ */
+#define CFG_PSDMR	(PSDMR_RFEN	      |\
+			 PSDMR_SDAM_A14_IS_A5 |\
+			 PSDMR_BSMA_A14_A16   |\
+			 PSDMR_SDA10_PBI0_A9  |\
+			 PSDMR_RFRC_7_CLK     |\
+			 PSDMR_PRETOACT_3W    |\
+			 PSDMR_ACTTORW_2W     |\
+			 PSDMR_LDOTOPRE_1C    |\
+			 PSDMR_WRC_1C	      |\
+			 PSDMR_CL_2)
+#else
+#error "INVALID SDRAM CONFIGURATION"
+#endif
+
+/*
+ * Shoot for approximately 1MHz on the prescaler.
+ */
+#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
+#define CFG_MPTPR	MPTPR_PTP_DIV64
+#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
+#define CFG_MPTPR	MPTPR_PTP_DIV32
+#else
+#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
+#define CFG_MPTPR	MPTPR_PTP_DIV32
+#endif
+#define CFG_PSRT	14
+
+
+/*-----------------------------------------------------------------------
+ * BR6 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR6 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 6 - Secondary FLASH
+ *
+ * The secondary FLASH is connected to *CS6
+ */
+#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
+
+/* BR6 is configured as follows:
+ *
+ *     - Base address of 0x60000000
+ *     - 16 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#  define CFG_BR6_PRELIM  ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
+			   BRx_PS_16			  |\
+			   BRx_MS_GPCM_P		  |\
+			   BRx_V)
+
+/* OR6 is configured as follows:
+ *
+ *     - 2 MB
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 5
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+#  define CFG_OR6_PRELIM  (MEG_TO_AM(CFG_FLASH1_SIZE)  |\
+			   ORxG_CSNT		       |\
+			   ORxG_ACS_DIV1	       |\
+			   ORxG_SCY_5_CLK	       |\
+			   ORxG_TRLX		       |\
+			   ORxG_EHTR)
+#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM	0x02	/* Software reboot		     */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h
new file mode 100755
index 0000000..beff28a
--- /dev/null
+++ b/include/configs/sbc405.h
@@ -0,0 +1,277 @@
+/*
+ * (C) Copyright 2001
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_SBC405		1	/* ...on a WR SBC405 board	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_PREBOOT	"echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo"
+
+#define CONFIG_RAMBOOT								\
+	"setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm ffc00000 ffca0000"
+#define CONFIG_NFSBOOT								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm ffc00000"
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND      "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx"      /* autoboot command     */
+
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_RESET_DELAY	300	/* Intel LXT971A needs this	*/
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \
+		"e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \
+		"f=0x08 tn=sbc405 o=emac \0" \
+	"env_startaddr=FF000000\0" \
+	"env_endaddr=FF03FFFF\0" \
+	"loadfile=vxWorks.st\0" \
+	"loadaddr=0x01000000\0" \
+	"net_load=tftpboot ${loadaddr} ${loadfile}\0" \
+	"uboot_startaddr=FFFC0000\0" \
+	"uboot_endaddr=FFFFFFFF\0" \
+	"update=tftp ${loadaddr} u-boot.bin;" \
+		"protect off ${uboot_startaddr} ${uboot_endaddr};" \
+		"era ${uboot_startaddr} ${uboot_endaddr};" \
+		"cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \
+		"protect on ${uboot_startaddr} ${uboot_endaddr}\0" \
+	"zapenv=protect off ${env_startaddr} ${env_endaddr};" \
+		"era ${env_startaddr} ${env_endaddr};" \
+		"protect on ${env_startaddr} ${env_endaddr}\0"
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_COMMANDS	( CONFIG_CMD_DFL	| \
+				CFG_CMD_BSP	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_SDRAM	| \
+				0 )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+#define CONFIG_ETHADDR	DE:AD:BE:EF:01:01	/* Ethernet address	*/
+#define CONFIG_IPADDR		192.168.193.102
+#define CONFIG_NETMASK		255.255.255.224
+#define CONFIG_SERVERIP		192.168.193.119
+#define CONFIG_GATEWAYIP	192.168.193.97
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#undef CFG_HUSH_PARSER			/* use "hush" command parser	*/
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef CFG_EXT_SERIAL_CLOCK		/* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
+#define CFG_BASE_BAUD		691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE					\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,	\
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR	0x100000	/* default load address */
+#define CFG_EXTBDINFO	1		/* To use extended board_info (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef  CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER	0	/* configure as pci adapter	*/
+#define PCI_HOST_FORCE		1	/* configure as pci host	*/
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID	0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CFG_PCI_SUBSYS_DEVICEID	0x0408	/* PCI Device ID: PMC-405	*/
+#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI	0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CFG_PCI_PTM2PCI	0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_MONITOR_BASE	0xFFFC0000
+#define CFG_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN	(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_BASE		0xFF000000
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)		*/
+#define CFG_FLASH_INCREMENT	0x01000000
+#undef CFG_FLASH_PROTECTION		/* don't use hardware protection	*/
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)		*/
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CFG_ENV_ADDR	CFG_FLASH_BASE	/* starting right at the beginning	*/
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0	/* starting right at the beginning	*/
+#define CFG_ENV_SECT_SIZE	0x40000	/* see README - env sector total size	*/
+#define CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...					*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+#define FLASH0_BA	CFG_FLASH_BASE		/* FLASH 0 Base Address		*/
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP	0x92015480
+#define CFG_EBC_PB0CR	FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CFG_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CFG_OCM_DATA_ADDR	0xF8000000
+#define CFG_OCM_DATA_SIZE	0x1000
+
+#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
+#define CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS	0x50
+#define CONFIG_SPD_EEPROM	1	/* use SPD EEPROM for setup		*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sbc8240.h b/include/configs/sbc8240.h
new file mode 100755
index 0000000..d891e07
--- /dev/null
+++ b/include/configs/sbc8240.h
@@ -0,0 +1,365 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Configuration settings for the sbc8240 board.
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8240		1
+#define CONFIG_WRSBC8240	1
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_PREBOOT  "echo;echo Welcome to U-Boot for the sbc8240;echo;echo Type \"? or help\" to get on-line help;echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_BOOTCOMMAND	"version;echo;tftpboot $loadaddr $loadfile;bootvx"	/* autoboot command	*/
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootargs=$fei(0,0)host:/T221ppc/target/config/sbc8240/vxWorks.st " \
+	       "e=192.168.193.102 h=192.168.193.99 u=target pw=hello f=0x08 " \
+	       "tn=sbc8240 o=fei \0" \
+	"env_startaddr=FFF70000\0" \
+	"env_endaddr=FFF7FFFF\0" \
+	"loadfile=vxWorks.st\0" \
+	"loadaddr=0x01000000\0" \
+	"net_load=tftpboot $loadaddr $loadfile\0" \
+	"uboot_startaddr=FFF00000\0" \
+	"uboot_endaddr=FFF3FFFF\0" \
+	"update=tftp $loadaddr /u-boot.bin;" \
+		"protect off $uboot_startaddr $uboot_endaddr;" \
+		"era $uboot_startaddr $uboot_endaddr;" \
+		"cp.b $loadaddr $uboot_startaddr $filesize;" \
+		"protect on $uboot_startaddr $uboot_endaddr\0" \
+	"zapenv=protect off $env_startaddr $env_endaddr;" \
+		"era $env_startaddr $env_endaddr;" \
+		"protect on $env_startaddr $env_endaddr\0"
+
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_COMMANDS	( CONFIG_CMD_DFL | \
+				  CFG_CMD_BSP    | \
+				  CFG_CMD_DIAG   | \
+				  CFG_CMD_ELF    | \
+				  CFG_CMD_ENV    | \
+				  CFG_CMD_FLASH  | \
+				  CFG_CMD_PCI    | \
+				  CFG_CMD_PING   | \
+				  CFG_CMD_SDRAM  | \
+				  0 )
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+#if 1
+#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#define CONFIG_ETHADDR          DE:AD:BE:EF:01:01    /* Ethernet address */
+#define CONFIG_IPADDR           192.168.193.102
+#define CONFIG_NETMASK          255.255.255.248
+#define CONFIG_SERVERIP         192.168.193.99
+
+#define CONFIG_STATUS_LED               /* Status LED enabled           */
+#define CONFIG_BOARD_SPECIFIC_LED       /* version has board specific leds */
+
+#define STATUS_LED_BIT          0x00000001
+#define STATUS_LED_PERIOD       (CFG_HZ / 2)
+#define STATUS_LED_STATE        STATUS_LED_BLINKING
+#define STATUS_LED_ACTIVE       0       /* LED on for bit == 0  */
+#define STATUS_LED_BOOT         0       /* LED 0 used for boot status */
+
+#ifndef __ASSEMBLY__
+/* LEDs */
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+	do { \
+		*((volatile char *) (CFG_LED_BASE)) ^= (_msk); \
+	} while(0)
+
+#define __led_set(_msk, _st) \
+	do { \
+		if ((_st)) \
+			*((volatile char *) (CFG_LED_BASE)) |= (_msk); \
+		else \
+			*((volatile char *) (CFG_LED_BASE)) &= ~(_msk); \
+	} while(0)
+
+#define __led_init(msk, st) __led_set(msk, st)
+
+#endif
+
+#define CONFIG_MISC_INIT_R
+#define CFG_LED_BASE	0xFFE80000
+
+/* Print Buffer Size
+ */
+#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE	    0x00000000
+#define CFG_FLASH_BASE	    0xFFF00000
+
+#define CFG_RESET_ADDRESS   0xFFF00100
+
+#define CFG_EUMB_ADDR	    0xFCE00000
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+
+#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+
+#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+	/* Maximum amount of RAM.
+	 */
+#define CFG_MAX_RAM_SIZE    0x10000000
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+	/* Size in bytes reserved for initial data
+	 */
+#define CFG_GBL_DATA_SIZE    128
+
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x1000
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	1
+
+#define CFG_NS16550_CLK		3686400
+
+#define CFG_NS16550_COM1	0xFFF80000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33000000
+#define CFG_HZ		     1000
+#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
+
+	/* Bit-field values for MCCR1.
+	 */
+#define CFG_ROMNAL	    0
+#define CFG_ROMFAL	    7
+
+	/* Bit-field values for MCCR2.
+	 */
+#define CFG_REFINT	    430	    /* Refresh interval			*/
+
+	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+	 */
+#define CFG_BSTOPRE	    192
+
+	/* Bit-field values for MCCR3.
+	 */
+#define CFG_REFREC	    2	    /* Refresh to activate interval	*/
+#define CFG_RDLAT	    3	    /* Data latancy from read command	*/
+
+	/* Bit-field values for MCCR4.
+	 */
+#define CFG_PRETOACT	    2	    /* Precharge to activate interval	*/
+#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
+#define CFG_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
+#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
+#define CFG_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
+#define CFG_ACTORW	    2
+#define CFG_REGISTERD_TYPE_BUFFER 1
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CFG_BANK0_START	    0x00000000
+#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE    1
+#define CFG_BANK1_START	    0x3ff00000
+#define CFG_BANK1_END	    0x3fffffff
+#define CFG_BANK1_ENABLE    0
+#define CFG_BANK2_START	    0x3ff00000
+#define CFG_BANK2_END	    0x3fffffff
+#define CFG_BANK2_ENABLE    0
+#define CFG_BANK3_START	    0x3ff00000
+#define CFG_BANK3_END	    0x3fffffff
+#define CFG_BANK3_ENABLE    0
+#define CFG_BANK4_START	    0x3ff00000
+#define CFG_BANK4_END	    0x3fffffff
+#define CFG_BANK4_ENABLE    0
+#define CFG_BANK5_START	    0x3ff00000
+#define CFG_BANK5_END	    0x3fffffff
+#define CFG_BANK5_ENABLE    0
+#define CFG_BANK6_START	    0x3ff00000
+#define CFG_BANK6_END	    0x3fffffff
+#define CFG_BANK6_ENABLE    0
+#define CFG_BANK7_START	    0x3ff00000
+#define CFG_BANK7_END	    0x3fffffff
+#define CFG_BANK7_ENABLE    0
+
+#define CFG_ODCR	    0xff
+
+#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L  CFG_IBAT0L
+#define CFG_DBAT0U  CFG_IBAT0U
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+#define CFG_DBAT2L  CFG_IBAT2L
+#define CFG_DBAT2U  CFG_IBAT2U
+#define CFG_DBAT3L  CFG_IBAT3L
+#define CFG_DBAT3U  CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* Max number of sectors in one bank	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM      CFG_FLASH_BASE  /* FLASH bank #0        */
+#define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
+
+	/* Warining: environment is not EMBEDDED in the U-Boot code.
+	 * It's stored in flash separately.
+	 */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0xFFF70000
+#define CFG_ENV_SIZE		0x4000	/* Size of the Environment		*/
+#define CFG_ENV_OFFSET		0	/* starting right at the beginning	*/
+#define CFG_ENV_SECT_SIZE	0x40000 /* Size of the Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI			/* include pci support			*/
+#define CONFIG_PCI_PNP                  /* we need Plug 'n Play */
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support */
+#define CONFIG_TULIP
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8       /* use 8 rx buffer on eepro100  */
+#endif /* __CONFIG_H */
diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h
new file mode 100755
index 0000000..180ce05
--- /dev/null
+++ b/include/configs/sbc8260.h
@@ -0,0 +1,1088 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * Configuration settings for the WindRiver SBC8260 board.
+ *	See http://www.windriver.com/products/html/sbc8260.html
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Enable debug prints */
+#undef DEBUG		      /* General debug */
+#undef DEBUG_BOOTP_EXT	      /* Debug received vendor fields */
+
+/*****************************************************************************
+ *
+ * These settings must match the way _your_ board is set up
+ *
+ *****************************************************************************/
+
+/* What is the oscillator's (UX2) frequency in Hz? */
+#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
+
+/*-----------------------------------------------------------------------
+ * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
+ *-----------------------------------------------------------------------
+ * What should MODCK_H be? It is dependent on the oscillator
+ * frequency, MODCK[1-3], and desired CPM and core frequencies.
+ * Here are some example values (all frequencies are in MHz):
+ *
+ * MODCK_H   MODCK[1-3]	 Osc	CPM    Core  S2-6   S2-7   S2-8
+ * -------   ----------	 ---	---    ----  -----  -----  -----
+ * 0x1	     0x5	 33	100    133   Open   Close  Open
+ * 0x1	     0x6	 33	100    166   Open   Open   Close
+ * 0x1	     0x7	 33	100    200   Open   Open   Open
+ *
+ * 0x2	     0x2	 33	133    133   Close  Open   Close
+ * 0x2	     0x3	 33	133    166   Close  Open   Open
+ * 0x2	     0x4	 33	133    200   Open   Close  Close
+ * 0x2	     0x5	 33	133    233   Open   Close  Open
+ * 0x2	     0x6	 33	133    266   Open   Open   Close
+ *
+ * 0x5	     0x5	 66	133    133   Open   Close  Open
+ * 0x5	     0x6	 66	133    166   Open   Open   Close
+ * 0x5	     0x7	 66	133    200   Open   Open   Open
+ * 0x6	     0x0	 66	133    233   Close  Close  Close
+ * 0x6	     0x1	 66	133    266   Close  Close  Open
+ * 0x6	     0x2	 66	133    300   Close  Open   Close
+ */
+#define CFG_SBC_MODCK_H 0x05
+
+/* Define this if you want to boot from 0x00000100. If you don't define
+ * this, you will need to program the bootloader to 0xfff00000, and
+ * get the hardware reset config words at 0xfe000000. The simplest
+ * way to do that is to program the bootloader at both addresses.
+ * It is suggested that you just let U-Boot live at 0x00000000.
+ */
+#define CFG_SBC_BOOT_LOW 1
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
+ * The main FLASH is whichever is connected to *CS0. U-Boot expects
+ * this to be the SIMM.
+ */
+#define CFG_FLASH0_BASE 0x40000000
+#define CFG_FLASH0_SIZE 4
+
+/* What should the base address of the secondary FLASH be and how big
+ * is it (in Mbytes)? The secondary FLASH is whichever is connected
+ * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
+ * want it enabled, don't define these constants.
+ */
+#define CFG_FLASH1_BASE 0x60000000
+#define CFG_FLASH1_SIZE 2
+
+/* What should be the base address of SDRAM DIMM and how big is
+ * it (in Mbytes)?
+*/
+#define CFG_SDRAM0_BASE 0x00000000
+#define CFG_SDRAM0_SIZE 64
+
+/* What should be the base address of the LEDs and switch S0?
+ * If you don't want them enabled, don't define this.
+ */
+#define CFG_LED_BASE 0xa0000000
+
+
+/*
+ * SBC8260 with 16 MB DIMM:
+ *
+ *     0x0000 0000     Exception Vector code, 8k
+ *	     :
+ *     0x0000 1FFF
+ *     0x0000 2000     Free for Application Use
+ *	     :
+ *	     :
+ *
+ *	     :
+ *	     :
+ *     0x00F5 FF30     Monitor Stack (Growing downward)
+ *		       Monitor Stack Buffer (0x80)
+ *     0x00F5 FFB0     Board Info Data
+ *     0x00F6 0000     Malloc Arena
+ *	     :		    CFG_ENV_SECT_SIZE, 256k
+ *	     :		    CFG_MALLOC_LEN,    128k
+ *     0x00FC 0000     RAM Copy of Monitor Code
+ *	     :		    CFG_MONITOR_LEN,   256k
+ *     0x00FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
+ */
+
+/*
+ * SBC8260 with 64 MB DIMM:
+ *
+ *     0x0000 0000     Exception Vector code, 8k
+ *	     :
+ *     0x0000 1FFF
+ *     0x0000 2000     Free for Application Use
+ *	     :
+ *	     :
+ *
+ *	     :
+ *	     :
+ *     0x03F5 FF30     Monitor Stack (Growing downward)
+ *		       Monitor Stack Buffer (0x80)
+ *     0x03F5 FFB0     Board Info Data
+ *     0x03F6 0000     Malloc Arena
+ *	     :		    CFG_ENV_SECT_SIZE, 256k
+ *	     :		    CFG_MALLOC_LEN,    128k
+ *     0x03FC 0000     RAM Copy of Monitor Code
+ *	     :		    CFG_MONITOR_LEN,   256k
+ *     0x03FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
+ */
+
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ */
+#define CONFIG_CONS_ON_SMC	1	/* define if console on SMC */
+#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on neither */
+#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+
+#undef	CONFIG_ETHER_ON_SCC
+#define CONFIG_ETHER_ON_FCC
+#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */
+
+#ifdef	CONFIG_ETHER_ON_SCC
+#define CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
+#endif	/* CONFIG_ETHER_ON_SCC */
+
+#ifdef	CONFIG_ETHER_ON_FCC
+#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
+#undef	CONFIG_ETHER_LOOPBACK_TEST	/* Ethernet external loopback test */
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+/*
+ * Port pins used for bit-banged MII communictions (if applicable).
+ */
+#define MDIO_PORT	2	/* Port C */
+#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
+#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
+			else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
+			else	iop->pdat &= ~0x00200000
+
+#define MIIDELAY	udelay(1)
+#endif	/* CONFIG_ETHER_ON_FCC */
+
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+
+/*
+ *  - RX clk is CLK11
+ *  - TX clk is CLK12
+ */
+# define CFG_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11  | CMXSCR_TS1CS_CLK12)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+/*
+ * Select SPI support configuration
+ */
+#undef  CONFIG_SPI			/* Disable SPI driver */
+
+/*
+ * Select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#ifdef CONFIG_SOFT_I2C
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+
+/* Define this to reserve an entire FLASH sector (256 KB) for
+ * environment variables. Otherwise, the environment will be
+ * put in the same sector as U-Boot, and changing variables
+ * will erase U-Boot temporarily
+ */
+#define CFG_ENV_IN_OWN_SECT	1
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* What should the console's baud rate be? */
+#define CONFIG_BAUDRATE		9600
+
+/* Ethernet MAC address
+ *     Note: We are using the EST Corporation OUI (00:a0:1e:xx:xx:xx)
+ *           http://standards.ieee.org/regauth/oui/index.shtml
+ */
+#define CONFIG_ETHADDR		00:a0:1e:a8:7b:cb
+
+/*
+ * Define this to set the last octet of the ethernet address from the
+ * DS0-DS7 switch and light the LEDs with the result. The DS0-DS7
+ * switch and the LEDs are backwards with respect to each other. DS7
+ * is on the board edge side of both the LED strip and the DS0-DS7
+ * switch.
+ */
+#undef	CONFIG_MISC_INIT_R
+
+/* Set to a positive value to delay for running BOOTCOMMAND */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+/* Be selective on what keys can delay or stop the autoboot process
+ *     To stop	use: " "
+ */
+#undef CONFIG_AUTOBOOT_KEYED
+#ifdef CONFIG_AUTOBOOT_KEYED
+#   define CONFIG_AUTOBOOT_PROMPT	"Autobooting in %d seconds, press \" \" to stop\n"
+#   define CONFIG_AUTOBOOT_STOP_STR	" "
+#   undef  CONFIG_AUTOBOOT_DELAY_STR
+#   define DEBUG_BOOTKEYS		0
+#endif
+
+/* Define this to contain any number of null terminated strings that
+ * will be part of the default enviroment compiled into the boot image.
+ *
+ * Variable		Usage
+ * --------------       -------------------------------------------------------
+ * serverip		server IP address
+ * ipaddr		my IP address
+ * reprog		Reload flash with a new copy of U-Boot
+ * zapenv		Erase the environment area in flash
+ * root-on-initrd       Set the bootcmd variable to allow booting of an initial
+ *                      ram disk.
+ * root-on-nfs          Set the bootcmd variable to allow booting of a NFS
+ *                      mounted root filesystem.
+ * boot-hook            Convenient stub to do something useful before the
+ *                      bootm command is executed.
+ *
+ * Example usage of root-on-initrd and root-on-nfs :
+ *
+ * Note: The lines have been wrapped to improved its readability.
+ *
+ * => printenv bootcmd
+ * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
+ * nfsroot=${serverip}:${rootpath}
+ * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
+ *
+ * => run root-on-initrd
+ * => printenv bootcmd
+ * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw
+ * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
+ *
+ * => run root-on-nfs
+ * => printenv bootcmd
+ * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
+ * nfsroot=${serverip}:${rootpath}
+ * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
+ *
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"serverip=192.168.123.205\0" \
+	"ipaddr=192.168.123.213\0" \
+	"reprog="\
+		"bootp;" \
+		"tftpboot 0x140000 /bdi2000/u-boot.bin;" \
+		"protect off 1:0;" \
+		"erase 1:0;" \
+		"cp.b 140000 40000000 ${filesize};" \
+		"protect on 1:0\0" \
+	"zapenv="\
+		"protect off 1:1;" \
+		"erase 1:1;" \
+		"protect on 1:1\0" \
+	"root-on-initrd="\
+		"setenv bootcmd "\
+		"version;" \
+		"echo;" \
+		"bootp;" \
+		"setenv bootargs root=/dev/ram0 rw " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+		"run boot-hook;" \
+		"bootm\0" \
+	"root-on-nfs="\
+		"setenv bootcmd "\
+		"version;" \
+		"echo;" \
+		"bootp;" \
+		"setenv bootargs root=/dev/nfs rw " \
+		"nfsroot=${serverip}:${rootpath} " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+		"run boot-hook;" \
+		"bootm\0" \
+	"boot-hook=echo\0"
+
+/* Define a command string that is automatically executed when no character
+ * is read on the console interface withing "Boot Delay" after reset.
+ */
+#undef	CONFIG_BOOT_ROOT_INITRD 	/* Use ram disk for the root file system */
+#define	CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
+
+#ifdef CONFIG_BOOT_ROOT_INITRD
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/ram0 rw " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_INITRD */
+
+#ifdef CONFIG_BOOT_ROOT_NFS
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_NFS */
+
+/* Add support for a few extra bootp options like:
+ *	- File size
+ *	- DNS (up to 2 servers)
+ *	- Send hostname to DHCP server
+ */
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
+				 CONFIG_BOOTP_BOOTFILESIZE | \
+				 CONFIG_BOOTP_DNS  | \
+				 CONFIG_BOOTP_DNS2 | \
+				 CONFIG_BOOTP_SEND_HOSTNAME)
+
+/* undef this to save memory */
+#define CFG_LONGHELP
+
+/* Monitor Command Prompt */
+#define CFG_PROMPT		"=> "
+
+#undef  CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
+ * of an image is printed by image commands like bootm or iminfo.
+ */
+#define CONFIG_TIMESTAMP
+
+/* If this variable is defined, an environment variable named "ver"
+ * is created by U-Boot showing the U-Boot version.
+ */
+#define CONFIG_VERSION_VARIABLE
+
+/* What U-Boot subsytems do you want enabled? */
+#ifdef CONFIG_ETHER_ON_FCC
+# define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_ECHO	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IMMAP	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO | \
+				CFG_CMD_SDRAM   )
+#else
+# define CONFIG_COMMANDS	(((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_ECHO	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IMMAP	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO | \
+				CFG_CMD_SDRAM   )
+#endif /* CONFIG_ETHER_ON_FCC */
+
+#undef CONFIG_WATCHDOG				/* disable the watchdog */
+
+/* Where do the internal registers live? */
+#define CFG_IMMR		0xF0000000
+
+/*****************************************************************************
+ *
+ * You should not have to modify any of the following settings
+ *
+ *****************************************************************************/
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
+#define CONFIG_SBC8260		1	/* on an EST SBC8260 Board  */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CBSIZE		1024	/* Console I/O Buffer Size	     */
+#else
+#  define CFG_CBSIZE		256	/* Console I/O Buffer Size	     */
+#endif
+
+/* Print Buffer Size */
+#define CFG_PBSIZE	  (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+
+#define CFG_MAXARGS		32	/* max number of command args	*/
+
+#define CFG_BARGSIZE		CFG_CBSIZE /* Boot Argument Buffer Size	   */
+
+#define CFG_LOAD_ADDR		0x400000   /* default load address */
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+#define CFG_ALT_MEMTEST			/* Select full-featured memory test */
+#define CFG_MEMTEST_START	0x2000	/* memtest works from the end of */
+					/* the exception vector table */
+					/* to the end of the DRAM  */
+					/* less monitor and malloc area */
+#define CFG_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
+#define CFG_MEM_END_USAGE	( CFG_MONITOR_LEN \
+				+ CFG_MALLOC_LEN \
+				+ CFG_ENV_SECT_SIZE \
+				+ CFG_STACK_USAGE )
+
+#define CFG_MEMTEST_END		( CFG_SDRAM_SIZE * 1024 * 1024 \
+				- CFG_MEM_END_USAGE )
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_FLASH_BASE	CFG_FLASH0_BASE
+#define CFG_FLASH_SIZE	CFG_FLASH0_SIZE
+#define CFG_SDRAM_BASE	CFG_SDRAM0_BASE
+#define CFG_SDRAM_SIZE	CFG_SDRAM0_SIZE
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+#if defined(CFG_SBC_BOOT_LOW)
+#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#else
+#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CFG_SBC_BOOT_LOW) */
+
+/* get the HRCW ISB field from CFG_IMMR */
+#define CFG_SBC_HRCW_IMMR	( ((CFG_IMMR & 0x10000000) >> 10) | \
+				  ((CFG_IMMR & 0x01000000) >>  7) | \
+				  ((CFG_IMMR & 0x00100000) >>  4) )
+
+#define CFG_HRCW_MASTER		( HRCW_BPS11				| \
+				  HRCW_DPPC11				| \
+				  CFG_SBC_HRCW_IMMR			| \
+				  HRCW_MMR00				| \
+				  HRCW_LBPC11				| \
+				  HRCW_APPC10				| \
+				  HRCW_CS10PC00				| \
+				  (CFG_SBC_MODCK_H & HRCW_MODCK_H1111)	| \
+				  CFG_SBC_HRCW_BOOT_FLAGS )
+
+/* no slaves */
+#define CFG_HRCW_SLAVE1		0
+#define CFG_HRCW_SLAVE2		0
+#define CFG_HRCW_SLAVE3		0
+#define CFG_HRCW_SLAVE4		0
+#define CFG_HRCW_SLAVE5		0
+#define CFG_HRCW_SLAVE6		0
+#define CFG_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
+#define CFG_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ */
+#define CFG_MONITOR_BASE	CFG_FLASH0_BASE
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#  define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	16	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms)	*/
+
+#ifndef CFG_RAMBOOT
+#  define CFG_ENV_IS_IN_FLASH	1
+
+#  ifdef CFG_ENV_IN_OWN_SECT
+#    define CFG_ENV_ADDR	(CFG_MONITOR_BASE + 0x40000)
+#    define CFG_ENV_SECT_SIZE	0x40000
+#  else
+#    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
+#    define CFG_ENV_SIZE	0x1000	/* Total Size of Environment Sector	*/
+#    define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sect real size	*/
+#  endif /* CFG_ENV_IN_OWN_SECT */
+
+#else
+#  define CFG_ENV_IS_IN_NVRAM	1
+#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+#  define CFG_ENV_SIZE		0x200
+#endif /* CFG_RAMBOOT */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT	(HID0_ICE  |\
+			 HID0_DCE  |\
+			 HID0_ICFI |\
+			 HID0_DCI  |\
+			 HID0_IFEM |\
+			 HID0_ABE)
+
+#define CFG_HID0_FINAL	(HID0_ICE  |\
+			 HID0_IFEM |\
+			 HID0_ABE  |\
+			 HID0_EMCP)
+#define CFG_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMR		0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR		(BCR_ETM)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+
+#define CFG_SIUMCR	(SIUMCR_DPPC11	|\
+			 SIUMCR_L2CPC00 |\
+			 SIUMCR_APPC10	|\
+			 SIUMCR_MMR00)
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC |\
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWRI |\
+			 SYPCR_SWP  |\
+			 SYPCR_SWE)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC |\
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWRI |\
+			 SYPCR_SWP)
+#endif	/* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC	(TMCNTSC_SEC |\
+			 TMCNTSC_ALR |\
+			 TMCNTSC_TCF |\
+			 TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR	(PISCR_PS  |\
+			 PISCR_PTF |\
+			 PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SCCR	0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR	0
+
+/*
+ * Initialize Memory Controller:
+ *
+ * Bank Bus	Machine PortSz	Device
+ * ---- ---	------- ------	------
+ *  0	60x	GPCM	32 bit	FLASH (SIMM - 4MB) *
+ *  1	60x	GPCM	32 bit	FLASH (SIMM - Unused)
+ *  2	60x	SDRAM	64 bit	SDRAM (DIMM - 16MB or 64MB)
+ *  3	60x	SDRAM	64 bit	SDRAM (DIMM - Unused)
+ *  4	Local	SDRAM	32 bit	SDRAM (on board - 4MB)
+ *  5	60x	GPCM	 8 bit	EEPROM (8KB)
+ *  6	60x	GPCM	 8 bit	FLASH  (on board - 2MB) *
+ *  7	60x	GPCM	 8 bit	LEDs, switches
+ *
+ *  (*) This configuration requires the SBC8260 be configured
+ *	so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
+ *	the on board FLASH. In other words, JP24 should have
+ *	pins 1 and 2 jumpered and pins 3 and 4 jumpered.
+ *
+ */
+
+/*-----------------------------------------------------------------------
+ * BR0,BR1 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR0,OR1 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 0,1 - FLASH SIMM
+ *
+ * This expects the FLASH SIMM to be connected to *CS0
+ * It consists of 4 AM29F080B parts.
+ *
+ * Note: For the 4 MB SIMM, *CS1 is unused.
+ */
+
+/* BR0 is configured as follows:
+ *
+ *     - Base address of 0x40000000
+ *     - 32 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR0_PRELIM	((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_32			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+/* OR0 is configured as follows:
+ *
+ *     - 4 MB
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 5
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+#define CFG_OR0_PRELIM	(MEG_TO_AM(CFG_FLASH0_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxG_TRLX			|\
+			 ORxG_EHTR)
+
+/*-----------------------------------------------------------------------
+ * BR2,BR3 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR2,OR3 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 2,3 - SDRAM DIMM
+ *
+ *     16MB DIMM: P/N
+ *     64MB DIMM: P/N  1W-8864X8-4-P1-EST
+ *
+ * Note: *CS3 is unused for this DIMM
+ */
+
+/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
+ *
+ *     - Base address of 0x00000000
+ *     - 64 bit port size (60x bus only)
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - SDRAM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR2_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+#define CFG_BR3_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+/* With a 16 MB DIMM, the OR2 is configured as follows:
+ *
+ *     - 16 MB
+ *     - 2 internal banks per device
+ *     - Row start address bit is A9 with PSDMR[PBI] = 0
+ *     - 11 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+#if (CFG_SDRAM0_SIZE == 16)
+#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM0_SIZE)	|\
+			 ORxS_BPD_2			|\
+			 ORxS_ROWST_PBI0_A9		|\
+			 ORxS_NUMR_11)
+#endif
+
+/* With a 64 MB DIMM, the OR2 is configured as follows:
+ *
+ *     - 64 MB
+ *     - 4 internal banks per device
+ *     - Row start address bit is A8 with PSDMR[PBI] = 0
+ *     - 12 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+#if (CFG_SDRAM0_SIZE == 64)
+#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM0_SIZE)	|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A8		|\
+			 ORxS_NUMR_12)
+#endif
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x Bus SDRAM Mode Register
+ *     Ref: Section 10.3.3 on page 10-21
+ *-----------------------------------------------------------------------
+ */
+
+/* Address that the DIMM SPD memory lives at.
+ */
+#define SDRAM_SPD_ADDR 0x54
+
+#if (CFG_SDRAM0_SIZE == 16)
+/* With a 16 MB DIMM, the PSDMR is configured as follows:
+ *
+ *     - Bank Based Interleaving,
+ *     - Refresh Enable,
+ *     - Address Multiplexing where A5 is output on A14 pin
+ *	 (A6 on A15, and so on),
+ *     - use address pins A16-A18 as bank select,
+ *     - A9 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *	 is 3 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *	 2 clocks,
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - CAS Latency is 2.
+ */
+#define CFG_PSDMR	(PSDMR_RFEN	      |\
+			 PSDMR_SDAM_A14_IS_A5 |\
+			 PSDMR_BSMA_A16_A18   |\
+			 PSDMR_SDA10_PBI0_A9  |\
+			 PSDMR_RFRC_7_CLK     |\
+			 PSDMR_PRETOACT_3W    |\
+			 PSDMR_ACTTORW_2W     |\
+			 PSDMR_LDOTOPRE_1C    |\
+			 PSDMR_WRC_1C	      |\
+			 PSDMR_CL_2)
+#endif
+
+#if (CFG_SDRAM0_SIZE == 64)
+/* With a 64 MB DIMM, the PSDMR is configured as follows:
+ *
+ *     - Bank Based Interleaving,
+ *     - Refresh Enable,
+ *     - Address Multiplexing where A5 is output on A14 pin
+ *	 (A6 on A15, and so on),
+ *     - use address pins A14-A16 as bank select,
+ *     - A9 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *	 is 3 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *	 2 clocks,
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - CAS Latency is 2.
+ */
+#define CFG_PSDMR	(PSDMR_RFEN	      |\
+			 PSDMR_SDAM_A14_IS_A5 |\
+			 PSDMR_BSMA_A14_A16   |\
+			 PSDMR_SDA10_PBI0_A9  |\
+			 PSDMR_RFRC_7_CLK     |\
+			 PSDMR_PRETOACT_3W    |\
+			 PSDMR_ACTTORW_2W     |\
+			 PSDMR_LDOTOPRE_1C    |\
+			 PSDMR_WRC_1C	      |\
+			 PSDMR_CL_2)
+#endif
+
+/*
+ * Shoot for approximately 1MHz on the prescaler.
+ */
+#if (CONFIG_8260_CLKIN == (66 * 1000 * 1000))
+#define CFG_MPTPR	MPTPR_PTP_DIV64
+#elif (CONFIG_8260_CLKIN == (33 * 1000 * 1000))
+#define CFG_MPTPR	MPTPR_PTP_DIV32
+#else
+#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
+#define CFG_MPTPR	MPTPR_PTP_DIV32
+#endif
+#define CFG_PSRT	14
+
+
+/* Bank 4 - On board SDRAM
+ *
+ * This is not implemented yet.
+ */
+
+/*-----------------------------------------------------------------------
+ * BR6 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR6 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 6 - On board FLASH
+ *
+ * This expects the on board FLASH SIMM to be connected to *CS6
+ * It consists of 1 AM29F016A part.
+ */
+#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
+
+/* BR6 is configured as follows:
+ *
+ *     - Base address of 0x60000000
+ *     - 8 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#  define CFG_BR6_PRELIM  ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
+			   BRx_PS_8			  |\
+			   BRx_MS_GPCM_P		  |\
+			   BRx_V)
+
+/* OR6 is configured as follows:
+ *
+ *     - 2 MB
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 5
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+#  define CFG_OR6_PRELIM  (MEG_TO_AM(CFG_FLASH1_SIZE)  |\
+			   ORxG_CSNT		       |\
+			   ORxG_ACS_DIV1	       |\
+			   ORxG_SCY_5_CLK	       |\
+			   ORxG_TRLX		       |\
+			   ORxG_EHTR)
+#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
+
+/*-----------------------------------------------------------------------
+ * BR7 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR7 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 7 - LEDs and switches
+ *
+ *  LEDs     are at 0x00001 (write only)
+ *  switches are at 0x00001 (read only)
+ */
+#ifdef CFG_LED_BASE
+
+/* BR7 is configured as follows:
+ *
+ *     - Base address of 0xA0000000
+ *     - 8 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#  define CFG_BR7_PRELIM  ((CFG_LED_BASE & BRx_BA_MSK)	 |\
+			   BRx_PS_8			 |\
+			   BRx_MS_GPCM_P		 |\
+			   BRx_V)
+
+/* OR7 is configured as follows:
+ *
+ *     - 1 byte
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 15
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+#  define CFG_OR7_PRELIM  (ORxG_AM_MSK		       |\
+			   ORxG_CSNT		       |\
+			   ORxG_ACS_DIV1	       |\
+			   ORxG_SCY_15_CLK	       |\
+			   ORxG_TRLX		       |\
+			   ORxG_EHTR)
+#endif /* CFG_LED_BASE */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM	0x02	/* Software reboot		     */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
new file mode 100755
index 0000000..5a434dc
--- /dev/null
+++ b/include/configs/sbc8560.h
@@ -0,0 +1,404 @@
+/*
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
+ * Added support for Wind River SBC8560 board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* mpc8560ads board configuration file */
+/* please refer to doc/README.mpc85xx for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE			*/
+#define CONFIG_E500		1	/* BOOKE e500 family		*/
+#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560		*/
+#define CONFIG_MPC85xx_REV1	1	/* MPC85xx Rev 1.0 chip		*/
+
+
+#define CONFIG_CPM2		1	/* has CPM2 */
+#define CONFIG_SBC8560		1	/* configuration for SBC8560 board */
+
+/* XXX flagging this as something I might want to delete */
+#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific	*/
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
+#undef	CONFIG_PCI			/* pci ethernet support		*/
+#undef  CONFIG_ETHER_ON_FCC		/* cpm FCC ethernet support	*/
+
+
+#define CONFIG_ENV_OVERWRITE
+
+/* Using Localbus SDRAM to emulate flash before we can program the flash,
+ * normally you need a flash-boot image(u-boot.bin), if so undef this.
+ */
+#undef CONFIG_RAM_AS_FLASH
+
+#if defined(CONFIG_PCI_66)		/* some PCI card is 33Mhz only	*/
+  #define CONFIG_SYS_CLK_FREQ	66000000/* sysclk for MPC85xx		*/
+#else
+  #define CONFIG_SYS_CLK_FREQ	33000000/* most pci cards are 33Mhz	*/
+#endif
+
+/* below can be toggled for performance analysis. otherwise use default */
+#define CONFIG_L2_CACHE			    /* toggle L2 cache		*/
+#undef	CONFIG_BTB			    /* toggle branch predition	*/
+#undef	CONFIG_ADDR_STREAMING		    /* toggle addr streaming	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
+
+#undef	CFG_DRAM_TEST			    /* memory test, takes time	*/
+#define CFG_MEMTEST_START	0x00200000  /* memtest region */
+#define CFG_MEMTEST_END		0x00400000
+
+#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
+     defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
+     defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
+#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
+#endif
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
+
+#if XXX
+  #define CFG_CCSRBAR		0xfdf00000	/* relocated CCSRBAR	*/
+#else
+  #define CFG_CCSRBAR		0xff700000	/* default CCSRBAR	*/
+#endif
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	 */
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+#define CFG_SDRAM_SIZE		512		/* DDR is 512MB */
+#define SPD_EEPROM_ADDRESS	0x55		/*  DDR DIMM */
+
+#undef  CONFIG_DDR_ECC				/* only for ECC DDR module	*/
+#undef  CONFIG_SPD_EEPROM			/* Use SPD EEPROM for DDR setup */
+
+#if defined(CONFIG_MPC85xx_REV1)
+  #define CONFIG_DDR_DLL			/* possible DLL fix needed	*/
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#if defined(CONFIG_RAM_AS_FLASH)
+  #define CFG_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
+  #define CFG_FLASH_BASE	0xf8000000      /* start of FLASH 8M  */
+  #define CFG_BR0_PRELIM	0xf8000801      /* port size 8bit */
+  #define CFG_OR0_PRELIM	0xf8000ff7	/* 8MB Flash		*/
+#else /* Boot from real Flash */
+  #define CFG_LBC_SDRAM_BASE	0xf8000000	/* Localbus SDRAM */
+  #define CFG_FLASH_BASE	0xff800000      /* start of FLASH 8M    */
+  #define CFG_BR0_PRELIM	0xff800801      /* port size 8bit      */
+  #define CFG_OR0_PRELIM	0xff800ff7	/* 8MB Flash		*/
+#endif
+#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB	*/
+
+/* local bus definitions */
+#define CFG_BR1_PRELIM		0xe4001801	/* 64M, 32-bit flash */
+#define CFG_OR1_PRELIM		0xfc000ff7
+
+#define CFG_BR2_PRELIM		0x00000000	/* CS2 not used */
+#define CFG_OR2_PRELIM		0x00000000
+
+#define CFG_BR3_PRELIM		0xf0001861	/* 64MB localbus SDRAM	*/
+#define CFG_OR3_PRELIM		0xfc000cc1
+
+#if defined(CONFIG_RAM_AS_FLASH)
+  #define CFG_BR4_PRELIM	0xf4001861	/* 64M localbus SDRAM */
+#else
+  #define CFG_BR4_PRELIM	0xf8001861	/* 64M localbus SDRAM */
+#endif
+#define CFG_OR4_PRELIM		0xfc000cc1
+
+#define CFG_BR5_PRELIM		0xfc000801	/* 16M CS5 misc devices */
+#if 1
+  #define CFG_OR5_PRELIM	0xff000ff7
+#else
+  #define CFG_OR5_PRELIM	0xff0000f0
+#endif
+
+#define CFG_BR6_PRELIM		0xe0001801	/* 64M, 32-bit flash */
+#define CFG_OR6_PRELIM		0xfc000ff7
+#define CFG_LBC_LCRR		0x00030002	/* local bus freq	*/
+#define CFG_LBC_LBCR		0x00000000
+#define CFG_LBC_LSRT		0x20000000
+#define CFG_LBC_MRTPR		0x20000000
+#define CFG_LBC_LSDMR_1		0x2861b723
+#define CFG_LBC_LSDMR_2		0x0861b723
+#define CFG_LBC_LSDMR_3		0x0861b723
+#define CFG_LBC_LSDMR_4		0x1861b723
+#define CFG_LBC_LSDMR_5		0x4061b723
+
+/* just hijack the MOT BCSR def for SBC8560 misc devices */
+#define CFG_BCSR		((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
+/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0x70000000	/* Initial RAM address	*/
+#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#undef  CONFIG_CONS_ON_SCC			/* define if console on SCC */
+#undef	CONFIG_CONS_NONE			/* define if console on something else */
+
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		1843200 /* get_bus_freq(0) */
+#define CONFIG_BAUDRATE		9600
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1	((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
+#define CFG_NS16550_COM2	((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define	 CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
+
+#define CFG_PCI_MEM_BASE	0xC0000000
+#define CFG_PCI_MEM_PHYS	0xC0000000
+#define CFG_PCI_MEM_SIZE	0x10000000
+
+#if defined(CONFIG_TSEC_ENET)		/* TSEC Ethernet port */
+
+#  define CONFIG_NET_MULTI	1
+#  define CONFIG_MII		1	/* MII PHY management		*/
+#  define CONFIG_MPC85xx_TSEC1
+#  define CONFIG_MPC85xx_TSEC1_NAME	"TSEC0"
+#  define TSEC1_PHY_ADDR	25
+#  define TSEC1_PHYIDX		0
+/* Options are: TSEC0 */
+#  define CONFIG_ETHPRIME		"TSEC0"
+
+#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
+
+  #undef  CONFIG_ETHER_NONE		/* define if ether on something else */
+  #define CONFIG_ETHER_ON_FCC2		/* cpm FCC ethernet support	*/
+  #define CONFIG_ETHER_INDEX	2	/* which channel for ether  */
+
+  #if (CONFIG_ETHER_INDEX == 2)
+    /*
+     * - Rx-CLK is CLK13
+     * - Tx-CLK is CLK14
+     * - Select bus for bd/buffers
+     * - Full duplex
+     */
+    #define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+    #define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+    #define CFG_CPMFCR_RAMTYPE	0
+    #define CFG_FCC_PSMR	(FCC_PSMR_FDE)
+
+  #elif (CONFIG_ETHER_INDEX == 3)
+    /* need more definitions here for FE3 */
+  #endif				/* CONFIG_ETHER_INDEX */
+
+  #define CONFIG_MII			/* MII PHY management */
+  #define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+  /*
+   * GPIO pins used for bit-banged MII communications
+   */
+  #define MDIO_PORT	2		/* Port C */
+  #define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
+  #define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
+  #define MDIO_READ	((iop->pdat &  0x00400000) != 0)
+
+  #define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
+			else	iop->pdat &= ~0x00400000
+
+  #define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
+			else	iop->pdat &= ~0x00200000
+
+  #define MIIDELAY	udelay(1)
+
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
+#if 0
+#define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
+#define CFG_FLASH_PROTECTION		/* use hardware protection		*/
+#endif
+#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	200000		/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	50000		/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
+
+#if 0
+/* XXX This doesn't work and I don't want to fix it */
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+  #define CFG_RAMBOOT
+#else
+  #undef  CFG_RAMBOOT
+#endif
+#endif
+
+/* Environment */
+#if !defined(CFG_RAMBOOT)
+  #if defined(CONFIG_RAM_AS_FLASH)
+    #define CFG_ENV_IS_NOWHERE
+    #define CFG_ENV_ADDR	(CFG_FLASH_BASE + 0x100000)
+    #define CFG_ENV_SIZE	0x2000
+  #else
+    #define CFG_ENV_IS_IN_FLASH	1
+    #define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
+    #define CFG_ENV_ADDR	(CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
+    #define CFG_ENV_SIZE	0x2000 /* CFG_ENV_SECT_SIZE */
+  #endif
+#else
+  #define CFG_NO_FLASH		1	/* Flash is not usable now	*/
+  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
+/*#define CONFIG_BOOTARGS      "root=/dev/ram rw console=ttyS0,115200"*/
+#define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xffa00000"
+#define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PCI | \
+				CFG_CMD_PING | CFG_CMD_I2C) & \
+				 ~(CFG_CMD_ENV | \
+				  CFG_CMD_LOADS ))
+  #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
+    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_MII | \
+				CFG_CMD_PING | CFG_CMD_I2C) & \
+				~(CFG_CMD_ENV))
+  #endif
+#else
+  #if defined(CONFIG_PCI)
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI | \
+				CFG_CMD_PING | CFG_CMD_I2C)
+  #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
+    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_MII | \
+				CFG_CMD_PING | CFG_CMD_I2C)
+  #endif
+#endif
+
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"SBC8560=> " /* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+  #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+  #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x1000000	/* default load address */
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+  #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+  #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+  #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*Note: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#  define CONFIG_ETHADDR	00:01:af:07:9b:8a
+#  define CONFIG_HAS_ETH1
+#  define CONFIG_ETH1ADDR	00:01:af:07:9b:8b
+#  define CONFIG_HAS_ETH2
+#  define CONFIG_ETH2ADDR	00:01:af:07:9b:8c
+#endif
+
+#define CONFIG_SERVERIP		192.168.0.131
+#define CONFIG_IPADDR		192.168.0.105
+#define CONFIG_GATEWAYIP	0.0.0.0
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_HOSTNAME		SBC8560
+#define CONFIG_ROOTPATH		/home/ppc
+#define CONFIG_BOOTFILE		pImage
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
new file mode 100755
index 0000000..d7d07a6
--- /dev/null
+++ b/include/configs/sc520_cdp.h
@@ -0,0 +1,222 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_X86		1	/* This is a X86 CPU		*/
+#define CONFIG_SC520		1	/* Include support for AMD SC520 */
+#define CONFIG_ALI152X		1	/* Include support for Ali 152x SIO */
+
+#define CFG_SDRAM_PRECHARGE_DELAY 6     /* 6T */
+#define CFG_SDRAM_REFRESH_RATE    78    /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
+#define CFG_SDRAM_RAS_CAS_DELAY   3     /* 3T */
+
+/* define at most one of these */
+#undef CFG_SDRAM_CAS_LATENCY_2T
+#define CFG_SDRAM_CAS_LATENCY_3T
+
+#define CFG_SC520_HIGH_SPEED    0       /* 100 or 133MHz */
+#define CFG_RESET_GENERIC       1       /* use tripple-fault to reset cpu */
+#undef  CFG_RESET_SC520                 /* use SC520 MMCR's to reset cpu */
+#undef  CFG_TIMER_SC520                 /* use SC520 swtimers */
+#define CFG_TIMER_GENERIC       1       /* use the i8254 PIT timers */
+#undef  CFG_TIMER_TSC                   /* use the Pentium TSC timers */
+#define  CFG_USE_SIO_UART       0       /* prefer the uarts on the SIO to those
+					 * in the SC520 on the CDP */
+
+#define CFG_STACK_SIZE          0x8000  /* Size of bootloader stack */
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+#define CONFIG_LAST_STAGE_INIT    1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_MALLOC_SIZE	(CFG_ENV_SIZE + 128*1024)
+
+
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_EEPROM)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	15
+#define CONFIG_BOOTARGS    	"root=/dev/mtdblock0 console=ttyS0,9600"
+/* #define CONFIG_BOOTCOMMAND	"bootm 38000000" */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x01000000	/* 1 ... 16 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1024		/* incrementer freq: 1kHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	4	   /* we have 4 banks of DRAM */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+
+#define CFG_MAX_FLASH_BANKS	3	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+
+#define CONFIG_SPI_EEPROM      /* Support for SPI EEPROMs (AT25128) */
+#define CONFIG_MW_EEPROM       /* Support for MicroWire EEPROMs (AT93LC46) */
+
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+
+/* Environment in EEPROM */
+#define CFG_ENV_IS_IN_EEPROM   1
+#define CONFIG_SPI
+#define CFG_ENV_SIZE	       0x4000	/* Total Size of Environment EEPROM 16k is SPI is used or 128 bytes if MW is used*/
+#define CFG_ENV_OFFSET         0
+#define CONFIG_SC520_CDP_USE_SPI  /* Store configuration in the SPI part */
+#undef CONFIG_SC520_CDP_USE_MW    /* Store configuration in the MicroWire part */
+#define CONFIG_SPI_X 1
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=SC520CDP Flash Bank #0"
+#define MTDPARTS_DEFAULT	"mtdparts=SC520CDP Flash Bank #0:-(jffs2)"
+*/
+
+/*-----------------------------------------------------------------------
+ * Device drivers
+ */
+#define CONFIG_NET_MULTI        /* Multi ethernet cards support */
+#define CONFIG_PCNET
+#define CONFIG_PCNET_79C973
+#define CONFIG_PCNET_79C975
+#define PCNET_HAS_PROM         1
+
+/************************************************************
+ * IDE/ATA stuff
+ ************************************************************/
+#define CFG_IDE_MAXBUS		1   /* max. 2 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
+/*#define CFG_ATA_IDE1_OFFSET	0x0170	/###* ide1 offset */
+#define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
+#define CFG_ATA_REG_OFFSET	0	/* reg offset */
+#define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */
+#define CFG_ATA_BASE_ADDR       0
+
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef  CONFIG_IDE_RESET		/* reset for ide unsupported...	*/
+#undef  CONFIG_IDE_RESET_ROUTINE	/* no special reset function */
+
+/************************************************************
+ * ATAPI support (experimental)
+ ************************************************************/
+#define CONFIG_ATAPI			/* enable ATAPI Support */
+
+/************************************************************
+ * DISK Partition support
+ ************************************************************/
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION /* Experimental */
+
+/************************************************************
+ * Video/Keyboard support
+ ************************************************************/
+#define CONFIG_VIDEO			/* To enable video controller support */
+#define CONFIG_I8042_KBD
+#define CFG_ISA_IO 0
+
+
+/************************************************************
+ * RTC
+ ***********************************************************/
+#define CONFIG_RTC_MC146818
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * PCI stuff
+ */
+#define CONFIG_PCI                                /* include pci support */
+#define CONFIG_PCI_PNP                            /* pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW
+
+#define	CFG_FIRST_PCI_IRQ   10
+#define	CFG_SECOND_PCI_IRQ  9
+#define CFG_THIRD_PCI_IRQ   11
+#define	CFG_FORTH_PCI_IRQ   15
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h
new file mode 100755
index 0000000..a8e3555
--- /dev/null
+++ b/include/configs/sc520_spunk.h
@@ -0,0 +1,225 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_X86		1	/* This is a X86 CPU		*/
+#define CONFIG_SC520		1	/* Include support for AMD SC520 */
+
+#define CFG_SDRAM_PRECHARGE_DELAY 6     /* 6T */
+#define CFG_SDRAM_REFRESH_RATE    78    /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
+#define CFG_SDRAM_RAS_CAS_DELAY   3     /* 3T */
+
+/* define at most one of these */
+#undef CFG_SDRAM_CAS_LATENCY_2T
+#define CFG_SDRAM_CAS_LATENCY_3T
+
+#define CFG_SC520_HIGH_SPEED    0       /* 100 or 133MHz */
+#define CFG_RESET_GENERIC       1       /* use tripple-fault to reset cpu */
+#undef  CFG_RESET_SC520                 /* use SC520 MMCR's to reset cpu */
+#undef  CFG_TIMER_SC520                 /* use SC520 swtimers */
+#define CFG_TIMER_GENERIC       1       /* use the i8254 PIT timers */
+#undef  CFG_TIMER_TSC                   /* use the Pentium TSC timers */
+
+#define CFG_STACK_SIZE          0x8000  /* Size of bootloader stack */
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+#define CONFIG_LAST_STAGE_INIT    1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_MALLOC_SIZE	(CFG_ENV_SIZE + 128*1024)
+
+
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_PCMCIA | CFG_CMD_EEPROM)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	15
+#define CONFIG_BOOTARGS    	"root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) "
+#define CONFIG_BOOTCOMMAND	"setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"boot > "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x01000000	/* 1 ... 16 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1024		/* incrementer freq: 1kHz */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	4	   /* we have 4 banks of DRAM */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+
+
+#define CONFIG_SPI_EEPROM       /* SPI EEPROMs such as AT25010 or AT25640 */
+#define CONFIG_MW_EEPROM        /* MicroWire EEPROMS such as AT93LC46 */
+#define CONFIG_DS1722           /* Dallas DS1722 SPI Temperature probe */
+
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+
+#if 0
+/* Environment in flash */
+#define CFG_ENV_IS_IN_FLASH     1
+# define CFG_ENV_ADDR		(0x387a0000)	/* Addr of Environment Sector	*/
+# define CFG_ENV_SIZE		0x20000	/* Total Size of Environment Sector (or 0x10000) */
+# define CFG_ENV_OFFSET         0
+
+#else
+/* Environment in EEPROM */
+
+# define CFG_ENV_IS_IN_EEPROM   1
+# define CONFIG_SPI
+# define CONFIG_SPI_X 1
+# define CFG_ENV_SIZE		0x2000	/* Total Size of Environment EEPROM	*/
+# define CFG_ENV_OFFSET         0x1c00
+
+#endif
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=sc520_spunk-0"
+#define MTDPARTS_DEFAULT	"mtdparts=sc520_spunk-0:-(jffs2)"
+*/
+
+/*-----------------------------------------------------------------------
+ * Device drivers
+ */
+#define CONFIG_NET_MULTI        /* Multi ethernet cards support */
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+
+/************************************************************
+ * IDE/ATA stuff
+ ************************************************************/
+#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+#define CFG_ATA_BASE_ADDR       0
+#define CFG_ATA_IDE0_OFFSET	0x01f0	/* ide0 offset */
+#define CFG_ATA_IDE1_OFFSET	0xe000	/* ide1 offset */
+#define CFG_ATA_DATA_OFFSET	0	/* data reg offset	*/
+#define CFG_ATA_REG_OFFSET	0	/* reg offset */
+#define CFG_ATA_ALT_OFFSET	0x200	/* alternate register offset */
+
+#define CFG_FIRST_PCMCIA_BUS    1
+
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef  CONFIG_IDE_RESET		/* reset for ide unsupported...	*/
+#undef  CONFIG_IDE_RESET_ROUTINE	/* no special reset function */
+
+#define CONFIG_IDE_TI_CARDBUS
+#define CFG_PCMCIA_CIS_WIN          0x27f00000
+#define CFG_PCMCIA_CIS_WIN_SIZE     0x00100000
+#define CFG_PCMCIA_IO_WIN           0xe000
+#define CFG_PCMCIA_IO_WIN_SIZE      16
+
+/************************************************************
+ * DISK Partition support
+ ************************************************************/
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION /* Experimental */
+
+
+/************************************************************
+ * RTC
+ ***********************************************************/
+#define CONFIG_RTC_MC146818
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * PCI stuff
+ */
+#define CONFIG_PCI                                /* include pci support */
+#define CONFIG_PCI_PNP                            /* pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW
+
+#define	CFG_FIRST_PCI_IRQ   9
+#define	CFG_SECOND_PCI_IRQ  10
+#define	CFG_THIRD_PCI_IRQ   11
+#define	CFG_FORTH_PCI_IRQ   12
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sc520_spunk_rel.h b/include/configs/sc520_spunk_rel.h
new file mode 100755
index 0000000..2e7a7e1
--- /dev/null
+++ b/include/configs/sc520_spunk_rel.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _outer_config
+#define _outer_config
+
+#include "sc520_spunk.h"
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND	"fsload boot/vmlinuz ; bootm"
+
+#endif
diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h
new file mode 100755
index 0000000..a4249c4
--- /dev/null
+++ b/include/configs/scb9328.h
@@ -0,0 +1,356 @@
+/*
+ * Copyright (C) 2003 ETC s.r.o.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Written by Peter Figuli <peposh@etc.sk>, 2003.
+ *
+ * 2003/13/06 Initial MP10 Support copied from wepep250
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARM920T		1     /* this is an ARM920T CPU	    */
+#define CONFIG_IMX		1     /* in a Motorola MC9328MXL Chip */
+#define CONFIG_SCB9328		1     /* on a scb9328tronix board */
+#undef	CONFIG_USE_IRQ		      /* don't need use IRQ/FIQ	   */
+
+#define CONFIG_IMX_SERIAL1
+/*
+ * Select serial console configuration
+ */
+
+
+/*
+ * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
+ * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
+ * functionality or size of u-boot code.
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL		\
+				& ~CFG_CMD_LOADS	\
+				& ~CFG_CMD_CONSOLE	\
+				& ~CFG_CMD_AUTOSCRIPT	\
+				| CFG_CMD_NET		\
+				| CFG_CMD_PING		\
+				| CFG_CMD_DHCP		\
+				)
+
+#include <cmd_confdefs.h>
+
+/*
+ * Boot options. Setting delay to -1 stops autostart count down.
+ * NOTE: Sending parameters to kernel depends on kernel version and
+ * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
+ * parameters at all! Do not get confused by them so.
+ */
+#define CONFIG_BOOTDELAY   -1
+#define CONFIG_BOOTARGS	   "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
+#define CONFIG_BOOTCOMMAND "bootm 10040000"
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_ETHADDR		80:81:82:83:84:85
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		10.10.10.9
+#define CONFIG_SERVERIP		10.10.10.10
+
+/*
+ * General options for u-boot. Modify to save memory foot print
+ */
+#define CFG_LONGHELP				      /* undef saves memory  */
+#define CFG_PROMPT		"scb9328> "	      /* prompt string	     */
+#define CFG_CBSIZE		256		      /* console I/O buffer  */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size   */
+#define CFG_MAXARGS		16		      /* max command args    */
+#define CFG_BARGSIZE		CFG_CBSIZE	      /* boot args buf size  */
+
+#define CFG_MEMTEST_START	0x08100000	      /* memtest test area   */
+#define CFG_MEMTEST_END		0x08F00000
+
+#undef	CFG_CLKS_IN_HZ			     /* use HZ for freq. display     */
+
+#define CFG_HZ			3686400	     /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x141	     /* core clock - register value  */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+/*
+ * Definitions related to passing arguments to kernel.
+ */
+#define CONFIG_CMDLINE_TAG	     1	 /* send commandline to Kernel	     */
+#define CONFIG_SETUP_MEMORY_TAGS     1	 /* send memory definition to kernel */
+#define CONFIG_INITRD_TAG	     1	 /* send initrd params		     */
+#undef	CONFIG_VFD			 /* do not send framebuffer setup    */
+
+
+/*
+ * Malloc pool need to host env + 128 Kb reserve for other allocations.
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + (128<<10) )
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE	(120<<10)      /* stack size		     */
+
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4<<10)	       /* IRQ stack		     */
+#define CONFIG_STACKSIZE_FIQ	(4<<10)	       /* FIQ stack		     */
+#endif
+
+/* SDRAM Setup Values
+0x910a8300 Precharge Command CAS 3
+0x910a8200 Precharge Command CAS 2
+
+0xa10a8300 AutoRefresh Command CAS 3
+0xa10a8200 Set AutoRefresh Command CAS 2 */
+
+#define PRECHARGE_CMD 0x910a8200
+#define AUTOREFRESH_CMD 0xa10a8200
+
+/*
+ * SDRAM Memory Map
+ */
+/* SH FIXME */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of SDRAM */
+#define SCB9328_SDRAM_1		0x08000000	/* SDRAM bank #1	   */
+#define SCB9328_SDRAM_1_SIZE	0x01000000	/* 16 MB		   */
+
+/*
+ * Flash Controller settings
+ */
+
+/*
+ * Hardware drivers
+ */
+
+
+/*
+ * Configuration for FLASH memory for the Synertronixx board
+ */
+
+/* #define SCB9328_FLASH_32M */
+
+/* 32MB */
+#ifdef SCB9328_FLASH_32M
+#define CFG_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
+#define CFG_MAX_FLASH_SECT		256	/* number of sector in FLASH bank    */
+#define SCB9328_FLASH_BUS_WIDTH		2	/* we use 16 bit FLASH memory...     */
+#define SCB9328_FLASH_INTERLEAVE	1	/* ... made of 1 chip		     */
+#define SCB9328_FLASH_BANK_SIZE	 0x02000000	/* size of one flash bank	     */
+#define SCB9328_FLASH_SECT_SIZE	 0x00020000	/* size of erase sector		     */
+#define SCB9328_FLASH_BASE	 0x10000000	/* location of flash memory	     */
+#define SCB9328_FLASH_UNLOCK		1	/* perform hw unlock first	     */
+#else
+
+/* 16MB */
+#define CFG_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
+#define CFG_MAX_FLASH_SECT		128	/* number of sector in FLASH bank    */
+#define SCB9328_FLASH_BUS_WIDTH		2	/* we use 16 bit FLASH memory...     */
+#define SCB9328_FLASH_INTERLEAVE	1	/* ... made of 1 chip		     */
+#define SCB9328_FLASH_BANK_SIZE	 0x01000000	/* size of one flash bank	     */
+#define SCB9328_FLASH_SECT_SIZE	 0x00020000	/* size of erase sector		     */
+#define SCB9328_FLASH_BASE	 0x10000000	/* location of flash memory	     */
+#define SCB9328_FLASH_UNLOCK		1	/* perform hw unlock first	     */
+#endif /* SCB9328_FLASH_32M */
+
+/* This should be defined if CFI FLASH device is present. Actually benefit
+   is not so clear to me. In other words we can provide more informations
+   to user, but this expects more complex flash handling we do not provide
+   now.*/
+#undef	CFG_FLASH_CFI
+
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)    /* timeout for Erase operation */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)    /* timeout for Write operation */
+
+#define CFG_FLASH_BASE		SCB9328_FLASH_BASE
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * Right now there is no gain for user, but later on booting kernel might be
+ * possible. Consider using XIP kernel running from flash to save RAM
+ * footprint.
+ * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
+ */
+#define CFG_JFFS2_FIRST_BANK		0
+#define CFG_JFFS2_FIRST_SECTOR		5
+#define CFG_JFFS2_NUM_BANKS		1
+
+/*
+ * Environment setup. Definitions of monitor location and size with
+ * definition of environment setup ends up in 2 possibilities.
+ * 1. Embeded environment - in u-boot code is space for environment
+ * 2. Environment is read from predefined sector of flash
+ * Right now we support 2. possiblity, but expecting no env placed
+ * on mentioned address right now. This also needs to provide whole
+ * sector for it - for us 256Kb is really waste of memory. U-boot uses
+ * default env. and until kernel parameters could be sent to kernel
+ * env. has no sense to us.
+ */
+
+/* Setup for PA23 which is Reset Default PA23 but has to become
+   CS5 */
+
+#define CFG_GPR_A_VAL		0x00800000
+#define CFG_GIUS_A_VAL		0x0043fffe
+
+#define CFG_MONITOR_BASE	0x10000000
+#define CFG_MONITOR_LEN		0x20000		/* 128b ( 1 flash sector )  */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0x10020000	/* absolute address for now  */
+#define CFG_ENV_SIZE		0x20000
+
+#define	 CONFIG_ENV_OVERWRITE  1		/* env is not writable now   */
+
+/*
+ * CSxU_VAL:
+ * 63| x	x x x | x x x x | x x  x    x | x x x x | x x x x | x x x x | x x x x | x x x x|32
+ *   |DTACK_SEL|0|BCD |	  BCS	| PSZ|PME|SYNC|	 DOL	| CNC|	  WSC	    | 0| WWS  |	  EDC  |
+ *
+ * CSxL_VAL:
+ * 31| x x x x | x x x x | x x x x | x x x x | x x x x |  x x x x | x x	 x x | x x  x	 x| 0
+ *   |	 OEA   |   OEN	 |   WEA   |   WEN   |	 CSA   |EBC| DSZ  | 0|SP|0|WP| 0 0|PA|CSEN|
+ */
+
+#define CFG_CS0U_VAL 0x000F2000
+#define CFG_CS0L_VAL 0x11110d01
+#define CFG_CS1U_VAL 0x000F0a00
+#define CFG_CS1L_VAL 0x11110601
+#define CFG_CS2U_VAL 0x0
+#define CFG_CS2L_VAL 0x0
+
+#define CFG_CS3U_VAL 0x000FFFFF
+#define CFG_CS3L_VAL 0x00000303
+
+#define CFG_CS4U_VAL 0x000F0a00
+#define CFG_CS4L_VAL 0x11110301
+
+/* CNC == 3 too long
+   #define CFG_CS5U_VAL 0x0000C210 */
+
+/* #define CFG_CS5U_VAL 0x00008400
+   mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
+   kaum langsamer ist */
+/* #define CFG_CS5U_VAL 0x00009400
+   #define CFG_CS5L_VAL 0x11010D03 */
+
+#define CFG_CS5U_VAL 0x00008400
+#define CFG_CS5L_VAL 0x00000D03
+
+#define CONFIG_DRIVER_DM9000		1
+#define CONFIG_DRIVER_DM9000		1
+#define CONFIG_DM9000_BASE		0x16000000
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE+4)
+/* #define CONFIG_DM9000_USE_8BIT */
+#define CONFIG_DM9000_USE_16BIT
+/* #define CONFIG_DM9000_USE_32BIT */
+
+/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
+   f_ref=16,777MHz
+
+   0x002a141f: 191,9944MHz
+   0x040b2007: 144MHz
+   0x042a141f: 96MHz
+   0x0811140d: 64MHz
+   0x040e200e: 150MHz
+   0x00321431: 200MHz
+
+   0x08001800: 64MHz mit 16er Quarz
+   0x04001800: 96MHz mit 16er Quarz
+   0x04002400: 144MHz mit 16er Quarz
+
+   31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
+      |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|	    */
+
+#define CPU200
+
+#ifdef CPU200
+#define CFG_MPCTL0_VAL 0x00321431
+#else
+#define CFG_MPCTL0_VAL 0x040e200e
+#endif
+
+/* #define BUS64 */
+#define BUS72
+
+#ifdef BUS72
+#define CFG_SPCTL0_VAL 0x04002400
+#endif
+
+#ifdef BUS96
+#define CFG_SPCTL0_VAL 0x04001800
+#endif
+
+#ifdef BUS64
+#define CFG_SPCTL0_VAL 0x08001800
+#endif
+
+/* Das ist der BCLK Divider, der aus der System PLL
+   BCLK und HCLK erzeugt:
+   31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
+   0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
+   0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
+   0x2f001003 : 192MHz/5=38,4MHz
+   0x2f000003 : 64MHz/1
+   Bit 22: SPLL Restart
+   Bit 21: MPLL Restart */
+
+#ifdef BUS64
+#define CFG_CSCR_VAL 0x2f030003
+#endif
+
+#ifdef BUS72
+#define CFG_CSCR_VAL 0x2f030403
+#endif
+
+/*
+ * Well this has to be defined, but on the other hand it is used differently
+ * one may expect. For instance loadb command do not cares :-)
+ * So advice is - do not relay on this...
+ */
+#define CFG_LOAD_ADDR 0x08400000
+
+#define MHZ16QUARZINUSE
+
+#ifdef MHZ16QUARZINUSE
+#define CONFIG_SYSPLL_CLK_FREQ 16000000
+#else
+#define CONFIG_SYSPLL_CLK_FREQ 16780000
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 16780000
+
+/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
+#define CFG_FMCR_VAL 0x00000001
+
+/* Bit[0:3] contain PERCLK1DIV for UART 1
+   0x000b00b ->b<- -> 192MHz/12=16MHz
+   0x000b00b ->8<- -> 144MHz/09=16MHz
+   0x000b00b ->3<- -> 64MHz/4=16MHz */
+
+#ifdef BUS96
+#define CFG_PCDR_VAL 0x000b00b5
+#endif
+
+#ifdef BUS64
+#define CFG_PCDR_VAL 0x000b00b3
+#endif
+
+#ifdef BUS72
+#define CFG_PCDR_VAL 0x000b00b8
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/shannon.h b/include/configs/shannon.h
new file mode 100755
index 0000000..572985b
--- /dev/null
+++ b/include/configs/shannon.h
@@ -0,0 +1,216 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Configuation settings for the Shannon/TuxScreen/IS2630 WebPhone Board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Since we use the Inferno-Loader to bring us to live,
+ * we skip the lowlevel init stuff.
+ * But U-Boot still relocates itself into RAM
+ */
+#define CONFIG_INFERNO			/* we are using the inferno bootldr */
+#define CONFIG_SKIP_LOWLEVEL_INIT	1
+#undef  CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SA1100		1	/* This is an SA1100 CPU	*/
+#define CONFIG_SHANNON		1	/* on an SHANNON/TuxScreen Board      */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_3C589	1
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL3          1	/* we use SERIAL 3  */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#if 0 /* XXX - cannot test IDE anyway, so disabled for now - wd */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL	| \
+				 CFG_CMD_PCMCIA	| \
+				 CFG_CMD_IDE)
+#endif /* 0 */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,115200"
+#define CONFIG_NETMASK          255.255.0.0
+#define CONFIG_BOOTCOMMAND	"help"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"TuxScreen # "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0xc0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xc0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0xd0000000	/* default load address	*/
+
+#define	CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x09		/* 190 MHz for Shannon */
+
+						/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_DOS_PARTITION	1		/* DOS partitiion support */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+/* BE CAREFUL */
+#define CONFIG_NR_DRAM_BANKS	4	   /* we have 4 banks of EDORAM */
+#define PHYS_SDRAM_1		0xc0000000 /* RAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x00400000 /* 4 MB */
+#define PHYS_SDRAM_2		0xc8000000 /* RAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x00400000 /* 4 MB */
+#define PHYS_SDRAM_3            0xd0000000 /* RAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE       0x00400000 /* 4 MB */
+#define PHYS_SDRAM_4            0xd8000000 /* RAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE       0x00400000 /* 4 MB */
+
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE		0x00400000 /* 4 MB */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	(31+4)	/* max number of sectors on one chip	*/
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#ifdef CONFIG_INFERNO
+/* we take the last sector, 128 KB in size, but we only use 4 KB of it for stack reasons */
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x003E0000)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+#else
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x1C000)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+
+/* we pick the upper one */
+
+#define CONFIG_PCMCIA_SLOT_A
+
+#define CFG_PCMCIA_IO_ADDR	(0x20000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0x24000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0x2C000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_MEM_ADDR	(0x28000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+
+/* in fact, MEM and ATTRB are swapped - has to be corrected soon in cmd_pcmcia or so */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+/* it's simple, all regs are in I/O space */
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_ATTRB_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	0
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0
+
+/*-----------------------------------------------------------------------
+ */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h
new file mode 100755
index 0000000..a137f9d
--- /dev/null
+++ b/include/configs/smdk2400.h
@@ -0,0 +1,191 @@
+/*
+ * (C) Copyright 2002-2005
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ *
+ * Configuation settings for the SAMSUNG board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T		1	/* This is an ARM920T core	*/
+#define CONFIG_S3C2400		1	/* in a SAMSUNG S3C2400 SoC	*/
+#define CONFIG_SMDK2400		1	/* on an SAMSUNG SMDK2400 Board */
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ	12000000 /* SMDK2400 has 12 MHz input clock */
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
+#define CS8900_BASE		0x07000300 /* agrees with WIN CE PA */
+#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SAMSUNG */
+
+#undef	CONFIG_HWFLOW			/* include RTS/CTS flow control support	*/
+
+#undef	CONFIG_MODEM_SUPPORT		/* enable modem initialization stuff */
+
+/*
+ * The following enables modem debugging stuff. The dbg() and
+ * 'char screen[1024]' are used for debug printfs. Unfortunately,
+ * it is usable only from BDI
+ */
+#undef CONFIG_MODEM_SUPPORT_DEBUG
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#define	CONFIG_TIMESTAMP	1	/* Print timestamp info for images */
+
+/* Use s3c2400's RTC */
+#define CONFIG_RTC_S3C24X0	1
+
+#ifndef USE_920T_MMU
+#define CONFIG_COMMANDS_tmp    ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
+				CFG_CMD_DATE	| \
+				CFG_CMD_SNTP	)
+#else
+#define CONFIG_COMMANDS_tmp    (CONFIG_CMD_DFL	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_SNTP	)
+#endif
+
+#ifdef CONFIG_HWFLOW
+#define CONFIG_COMMANDS		(CONFIG_COMMANDS_tmp | CFG_CMD_HWFLOW)
+#else
+#define CONFIG_COMMANDS		CONFIG_COMMANDS_tmp
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#if 0
+#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600"
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#endif
+#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_IPADDR		134.98.93.36
+#define CONFIG_SERVERIP		134.98.93.22
+#if 0
+#define CONFIG_BOOTFILE		"elinos-lart"
+#define CONFIG_BOOTCOMMAND	"tftp; bootm"
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"SMDK2400 # "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0c000000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0e000000	/* 32 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x0cf00000	/* default load address	*/
+
+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
+/* it to wrap 100 times (total 1562500) to get 1 sec. */
+#define	CFG_HZ			1562500
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x0c000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
+
+#define CFG_FLASH_BASE		0x00000000 /* Flash Bank #1 */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	(64)	/* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+
+/* Address and size of Primary Environment Sector	*/
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x40000)
+#define CFG_ENV_SIZE		0x40000
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
new file mode 100755
index 0000000..7edec0d
--- /dev/null
+++ b/include/configs/smdk2410.h
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <gj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * Configuation settings for the SAMSUNG SMDK2410 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
+#define	CONFIG_S3C2410		1	/* in a SAMSUNG S3C2410 SoC     */
+#define CONFIG_SMDK2410		1	/* on a SAMSUNG SMDK2410 Board  */
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ	12000000/* the SMDK2410 has 12MHz input clock */
+
+
+#define USE_920T_MMU		1
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
+#define CS8900_BASE		0x19000300
+#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SMDK2410 */
+
+/************************************************************
+ * RTC
+ ************************************************************/
+#define	CONFIG_RTC_S3C24X0	1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#define CONFIG_COMMANDS \
+			(CONFIG_CMD_DFL	 | \
+			CFG_CMD_CACHE	 | \
+			/*CFG_CMD_NAND	 |*/ \
+			/*CFG_CMD_EEPROM |*/ \
+			/*CFG_CMD_I2C	 |*/ \
+			/*CFG_CMD_USB	 |*/ \
+			CFG_CMD_REGINFO  | \
+			CFG_CMD_DATE	 | \
+			CFG_CMD_ELF)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+/*#define CONFIG_BOOTARGS    	"root=ramfs devfs=mount console=ttySA0,9600" */
+/*#define CONFIG_ETHADDR	08:00:3e:26:0a:5b */
+#define CONFIG_NETMASK          255.255.255.0
+#define CONFIG_IPADDR		10.0.0.110
+#define CONFIG_SERVERIP		10.0.0.1
+/*#define CONFIG_BOOTFILE	"elinos-lart" */
+/*#define CONFIG_BOOTCOMMAND	"tftp; bootm" */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"SMDK2410 # "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x30000000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x33000000	/* default load address	*/
+
+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
+/* it to wrap 100 times (total 1562500) to get 1 sec. */
+#define	CFG_HZ			1562500
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CONFIG_AMD_LV400	1	/* uncomment this if you have a LV400 flash */
+#if 0
+#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
+#endif
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#ifdef CONFIG_AMD_LV800
+#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
+#define CFG_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
+#endif
+#ifdef CONFIG_AMD_LV400
+#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
+#define CFG_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x070000) /* addr of environment */
+#endif
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h
new file mode 100755
index 0000000..3d907f8
--- /dev/null
+++ b/include/configs/sorcery.h
@@ -0,0 +1,297 @@
+/*
+ * (C) Copyright 2004
+ * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC8220		1
+#define CONFIG_SORCERY		1	/* Sorcery board */
+
+/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
+   determine the CPU speed. */
+#define CFG_MPC8220_CLKIN	60000000 /* ... running at 60MHz */
+#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	*/
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5   	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC */
+
+#define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/* PCI */
+#define CONFIG_PCI              1
+#define CONFIG_PCI_PNP          1
+
+#define CONFIG_PCI_MEM_BUS      0x80000000
+#define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE     0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x71000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_PCI_CFG_BUS	0x70000000
+#define CONFIG_PCI_CFG_PHYS	CONFIG_PCI_CFG_BUS
+#define CONFIG_PCI_CFG_SIZE	0x01000000
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BOOTD	| \
+				CFG_CMD_CACHE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_SNTP	| \
+				0)
+
+/*			CFG_CMD_MII	| \ */
+/*			       CFG_CMD_USB	| \ */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Default Environment
+ */
+#define CONFIG_BOOTDELAY	5    /* autoboot after 5 seconds */
+#define CONFIG_HOSTNAME		sorcery
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$serverip:$rootpath\0"				\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $bootargs "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
+		":$hostname:$netdev:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $kernel_addr\0"					\
+	"flash_self=run ramargs addip;"					\
+		"bootm $kernel_addr $ramdisk_addr\0"			\
+	"net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/sorcery/uImage\0"				\
+	"kernel_addr=FFE00000\0"					\
+	"ramdisk_addr=FFB00000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1
+#define CFG_I2C_MODULE		1
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Flexbus Chipselect configuration
+ * Beware: Some CS# seem to be mandatory (if these CS# are not set,
+ * board can hang-up in unpredictable place).
+ * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
+ */
+
+/* Flash */
+#define CFG_CS0_BASE		0xf800
+#define CFG_CS0_MASK		0x08000000 /* 128 MB (two chips) */
+#define CFG_CS0_CTRL		0x001019c0
+
+/* NVM */
+#define CFG_CS1_BASE		0xf7e8
+#define CFG_CS1_MASK		0x00040000 /* 256K */
+#define CFG_CS1_CTRL		0x00101940 /* 8bit port size */
+
+/* Atlas2 + Gemini */
+#define CFG_CS2_BASE		0xf7e7
+#define CFG_CS2_MASK		0x00010000 /* 64K*/
+#define CFG_CS2_CTRL		0x001011c0 /* 16bit port size */
+
+/* CAN Controller */
+#define CFG_CS3_BASE		0xf7e6
+#define CFG_CS3_MASK		0x00010000 /* 64K */
+#define CFG_CS3_CTRL		0x00102140 /* 8Bit port size */
+
+/* Foreign interface */
+#define CFG_CS4_BASE		0xf7e5
+#define CFG_CS4_MASK		0x00010000 /* 64K */
+#define CFG_CS4_CTRL		0x00101dc0 /* 16bit port size */
+
+/* CPLD */
+#define CFG_CS5_BASE		0xf7e4
+#define CFG_CS5_MASK		0x00010000 /* 64K */
+#define CFG_CS5_CTRL		0x001000c0 /* 16bit port size */
+
+#define CFG_FLASH0_BASE		(CFG_CS0_BASE << 16)
+#define CFG_FLASH_BASE		(CFG_FLASH0_BASE)
+
+#define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks */
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_BANKS_LIST 	{ CFG_FLASH_BASE,  \
+				CFG_FLASH_BASE+0x04000000 } /* two banks */
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x8000000 - 0x40000)
+#define CFG_ENV_SIZE		0x4000                       /* 16K */
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + 0x20000)
+#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
+
+#define CONFIG_ENV_OVERWRITE	1
+
+#if defined CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_EEPROM
+#elif defined CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_EEPROM
+#elif defined CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#endif
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+#define CFG_SRAM_BASE		(CFG_MBAR + 0x20000)
+#define CFG_SRAM_SIZE		0x8000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	(CFG_MBAR + 0x20000)
+#define CFG_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
+#define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
+
+/* SDRAM configuration (for SPD) */
+#define CFG_SDRAM_TOTAL_BANKS		1
+#define CFG_SDRAM_SPD_I2C_ADDR		0x50  		/* 7bit */
+#define CFG_SDRAM_SPD_SIZE		0x100
+#define CFG_SDRAM_CAS_LATENCY		5 		/* (CL=2.5)x2 */
+
+/* SDRAM drive strength register (for SSTL_2 class II)*/
+#define CFG_SDRAM_DRIVE_STRENGTH 	((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
+					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC8220_FEC	1
+#define CONFIG_FEC_10MBIT	1 /* Workaround for FEC 100Mbit problem */
+#define CONFIG_PHY_ADDR		0x1F
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			    /* undef to save memory	*/
+#define CFG_PROMPT		"=> "	    /* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	    /* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	    /* max number of command args   */
+#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START	0x00100000  /* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
+
+#define CFG_LOAD_ADDR		0x100000    /* default load address */
+
+#define CFG_HZ			1000	    /* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+
+/*
+#define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL          HID0_ICE
+*/
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/spieval.h b/include/configs/spieval.h
new file mode 100755
index 0000000..96cb6e4
--- /dev/null
+++ b/include/configs/spieval.h
@@ -0,0 +1,548 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
+#define CONFIG_TQM5200		1	/* ... on TQM5200 module */
+#undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules */
+#define CONFIG_STK52XX		1	/* ... on a STK52XX base board */
+#define CONFIG_STK52XX_REV100	1	/*  define for revision 100 baseboards */
+
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	6	/* console is on PSC6 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#ifdef CONFIG_STK52XX
+#undef CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
+#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
+#define CONFIG_PS2SERIAL	6	/* .. on PSC6			*/
+#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
+#define CONFIG_BOARD_EARLY_INIT_R
+#endif /* CONFIG_STK52XX */
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#ifdef CONFIG_STK52XX
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+/* #define CONFIG_PCI_SCAN_SHOW	1 */
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_EEPRO100		1
+#define CFG_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X		1
+#endif	/* CONFIG_STK52XX */
+
+#ifdef CONFIG_PCI
+#define ADD_PCI_CMD		CFG_CMD_PCI
+#else
+#define ADD_PCI_CMD		0
+#endif
+
+/*
+ * Video console
+ */
+#if 1
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501
+#define CONFIG_VIDEO_SM501_32BPP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CFG_CONSOLE_IS_IN_ENV
+#endif
+
+#ifdef CONFIG_VIDEO
+#define ADD_BMP_CMD		CFG_CMD_BMP
+#else
+#define ADD_BMP_CMD		0
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* USB */
+#ifdef CONFIG_STK52XX
+#define CONFIG_USB_OHCI
+#define ADD_USB_CMD		CFG_CMD_USB | CFG_CMD_FAT
+#define CONFIG_USB_STORAGE
+#else
+#define ADD_USB_CMD		0
+#endif
+
+/* POST support */
+#define CONFIG_POST		(CFG_POST_MEMORY   | \
+				 CFG_POST_CPU	   | \
+				 CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+
+/* IDE */
+#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
+#define ADD_IDE_CMD		(CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
+#else
+#define ADD_IDE_CMD		0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				ADD_BMP_CMD	| \
+				ADD_IDE_CMD	| \
+				ADD_PCI_CMD	| \
+				ADD_USB_CMD	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_ECHO	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_POST_DIAG | \
+				CFG_CMD_REGINFO | \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define	CONFIG_TIMESTAMP		/* display image timestamps */
+
+#if (TEXT_BASE == 0xFC000000)		/* Boot low */
+#   define CFG_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#if defined (CONFIG_TQM5200_AA)
+# define CONFIG_U_BOOT_SUFFIX	"-AA\0"
+#elif defined (CONFIG_TQM5200_AB)
+# define CONFIG_U_BOOT_SUFFIX	"-AB\0"
+#elif defined (CONFIG_TQM5200_AC)
+# define CONFIG_U_BOOT_SUFFIX	"-AC\0"
+#else
+# define CONFIG_U_BOOT_SUFFIX	"\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"bootfile=/tftpboot/tqm5200/uImage\0"				\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"u-boot=/tftpboot/tqm5200/u-boot.bin"	CONFIG_U_BOOT_SUFFIX	\
+	"update=protect off FC000000 FC05FFFF;"				\
+		"erase FC000000 FC05FFFF;"				\
+		"cp.b 200000 FC000000 ${filesize};"			\
+		"protect on FC000000 FC05FFFF\0"			\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133		/* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66			/* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#ifdef CONFIG_TQM5200_REV100
+#define CFG_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
+#else
+#define CFG_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
+#endif
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
+ * also). For other EEPROMs configuration should be verified. On Mini-FAP the
+ * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
+ * same configuration could be used.
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/*
+ * HW-Monitor configuration on Mini-FAP
+ */
+#if defined (CONFIG_MINIFAP)
+#define CFG_I2C_HWMON_ADDR		0x2C
+#endif
+
+/* List of I2C addresses to be verified by POST */
+#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB)
+#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
+				CFG_I2C_SLAVE }
+#elif defined (CONFIG_TQM5200_AC)
+#define I2C_ADDR_LIST	{	CFG_I2C_SLAVE }
+#endif
+
+#if defined (CONFIG_MINIFAP)
+#undef I2C_ADDR_LIST
+#define I2C_ADDR_LIST	{	CFG_I2C_EEPROM_ADDR,	\
+				CFG_I2C_HWMON_ADDR,	\
+				CFG_I2C_SLAVE }
+#endif
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver if no module variant is spezified */
+#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#undef CFG_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
+
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00760000 + 0x00800000)
+#else	/* CFG_LOWBOOT */
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
+#endif	/* CFG_LOWBOOT */
+#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SIZE		0x10000
+#define CFG_ENV_SECT_SIZE	0x20000
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ *
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
+ *	Bit 0 (mask: 0x80000000): 1
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ *	00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ *	      Use for REV200 STK52XX boards. Do not use with REV100 modules
+ *	      (because, there I2C1 is used as I2C bus)
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
+ *	000 -> All PSC2 pins are GIOPs
+ *	001 -> CAN1/2 on PSC2 pins
+ *	       Use for REV100 STK52xx boards
+ * use PSC6:
+ *   on STK52xx:
+ *	use as UART. Pins PSC6_0 to PSC6_3 are used.
+ *	Bits 9:11 (mask: 0x00700000):
+ *	   101 -> PSC6 : Extended POST test is not available
+ *   on MINI-FAP and TQM5200_IB:
+ *	use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
+ *	   000 -> PSC6 could not be used as UART, CODEC or IrDA
+ *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
+ *   tests.
+ */
+#if defined (CONFIG_MINIFAP)
+# define CFG_GPS_PORT_CONFIG	0x91000004
+#elif defined (CONFIG_STK52XX)
+# if defined (CONFIG_STK52XX_REV100)
+#  define CFG_GPS_PORT_CONFIG	0x81500014
+# else /* STK52xx REV200 and above */
+#  if defined (CONFIG_TQM5200_REV100)
+#   error TQM5200 REV100 not supported on STK52XX REV200 or above
+#  else/* TQM5200 REV200 and above */
+#   define CFG_GPS_PORT_CONFIG	0x91500004
+#  endif
+# endif
+#else  /* TMQ5200 Inbetriebnahme-Board */
+# define CFG_GPS_PORT_CONFIG	0x81000004
+#endif
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#ifdef CFG_PCISPEED_66
+#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
+#endif
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+/* automatic configuration of chip selects */
+#ifdef CONFIG_CS_AUTOCONF
+#define CONFIG_LAST_STAGE_INIT
+#endif
+
+/*
+ * SRAM - Do not map below 2 GB in address space, because this area is used
+ * for SDRAM autosizing.
+ */
+#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF)
+#define CFG_CS2_START		0xE5000000
+#ifdef CONFIG_TQM5200_AB
+#define CFG_CS2_SIZE		0x80000		/* 512 kByte */
+#else  /* CONFIG_CS_AUTOCONF */
+#define CFG_CS2_SIZE		0x100000	/* 1 MByte */
+#endif
+#define CFG_CS2_CFG		0x0004D930
+#endif
+
+/*
+ * Grafic controller - Do not map below 2 GB in address space, because this
+ * area is used for SDRAM autosizing.
+ */
+#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \
+    defined (CONFIG_CS_AUTOCONF)
+#define SM501_FB_BASE		0xE0000000
+#define CFG_CS1_START		(SM501_FB_BASE)
+#define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
+#define CFG_CS1_CFG		0x8F48FF70
+#define SM501_MMIO_BASE		CFG_CS1_START + 0x03E00000
+#endif
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers						     */
+#define CFG_ATA_STRIDE		4
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h
new file mode 100755
index 0000000..e218597
--- /dev/null
+++ b/include/configs/stxgp3.h
@@ -0,0 +1,389 @@
+/*
+ * (C) Copyright 2003 Embedded Edge, LLC
+ * Dan Malek <dan@embeddededge.com>
+ * Copied from ADS85xx.
+ * Updates for Silicon Tx GP3 8560 board.
+ *
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* mpc8560ads board configuration file */
+/* please refer to doc/README.mpc85xx for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE		*/
+#define CONFIG_E500		1	/* BOOKE e500 family	*/
+#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560	*/
+#define CONFIG_CPM2		1	/* has CPM2 */
+#define CONFIG_STXGP3		1	/* Silicon Tx GPPP board specific*/
+
+#undef  CONFIG_PCI	         	/* pci ethernet support	*/
+#define CONFIG_TSEC_ENET 		/* tsec ethernet support*/
+#undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
+#undef  CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_DDR_DLL                  /* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+
+/* sysclk for MPC85xx
+ */
+
+#define CONFIG_SYS_CLK_FREQ     33333333 /* most pci cards are 33Mhz */
+
+/* Blinkin' LEDs for Robert :-)
+*/
+#define CONFIG_SHOW_ACTIVITY 1
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE                     /* toggle L2 cache         */
+#define  CONFIG_BTB                          /* toggle branch predition */
+#define  CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
+
+#define CONFIG_BOARD_EARLY_INIT_F   1        /* Call board_pre_init      */
+
+#undef  CFG_DRAM_TEST                       /* memory test, takes time  */
+#define CFG_MEMTEST_START       0x00200000  /* memtest region */
+#define CFG_MEMTEST_END         0x00400000
+
+
+/* Localbus SDRAM is an option, not all boards have it.
+ * This address, however, is used to configure a 256M local bus
+ * window that includes the Config latch below.
+ */
+#define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
+#define CFG_LBC_SDRAM_SIZE	256		/* LBC SDRAM is 64MB	*/
+
+#define CFG_FLASH_BASE        0xff000000      /* start of FLASH 16M    */
+#define CFG_BR0_PRELIM        0xff001801      /* port size 32bit      */
+
+#define CFG_OR0_PRELIM          0xff000ff7      /* 16 MB Flash           */
+#define CFG_MAX_FLASH_BANKS	1		/* number of banks	*/
+#define CFG_MAX_FLASH_SECT	136		/* sectors per device   */
+#undef	CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/* The configuration latch is Chip Select 1.
+ * It's an 8-bit latch in the lower 8 bits of the word.
+ */
+#define CFG_BR1_PRELIM		0xfc001801	/* 32-bit port */
+#define CFG_OR1_PRELIM		0xffff0ff7      /* 64K is enough */
+#define CFG_LBC_LCLDEVS_BASE	0xfc000000	/* Base of localbus devices */
+
+#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor	*/
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef  CFG_RAMBOOT
+#endif
+
+#ifdef CFG_RAMBOOT
+#define CFG_CCSRBAR_DEFAULT 	0x40000000	/* CCSRBAR by BDI cfg	*/
+#else
+#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default	*/
+#endif
+#define CFG_CCSRBAR             0xfdf00000      /* relocated CCSRBAR    */
+#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
+
+
+/*
+ * DDR Setup
+ */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
+#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
+
+#define SPD_EEPROM_ADDRESS 	0x54     	/*  DDR DIMM */
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/* local bus definitions */
+#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM  */
+#define CFG_OR2_PRELIM		0xfc006901
+#define CFG_LBC_LCRR		0x00030004	/* local bus freq 	*/
+#define CFG_LBC_LBCR		0x00000000
+#define CFG_LBC_LSRT		0x20000000
+#define CFG_LBC_MRTPR		0x20000000
+#define CFG_LBC_LSDMR_1		0x2861b723
+#define CFG_LBC_LSDMR_2		0x0861b723
+#define CFG_LBC_LSDMR_3		0x0861b723
+#define CFG_LBC_LSDMR_4		0x1861b723
+#define CFG_LBC_LSDMR_5		0x4061b723
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 	1
+#define CFG_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
+#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_ON_SCC              	/* define if console on SCC */
+#undef  CONFIG_CONS_NONE                	/* define if console on something else */
+#define CONFIG_CONS_INDEX       2       	/* which serial channel for console */
+
+#define CONFIG_BAUDRATE	 	38400
+
+#define CFG_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define  CONFIG_HARD_I2C    		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#if 0
+#define CFG_I2C_NOPROBES        {0x00}  /* Don't probe these addrs */
+#else
+/* I did the 'if 0' so we could keep the syntax above if ever needed. */
+#undef CFG_I2C_NOPROBES
+#endif
+
+/* RapdIO Map configuration, mapped 1:1.
+*/
+#define CFG_RIO_MEM_BASE	0xc0000000
+#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
+#define CFG_RIO_MEM_SIZE	0x200000000	/* 512 M */
+
+/* Standard 8560 PCI addressing, mapped 1:1.
+*/
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCI1_IO_BASE	0xe2000000
+#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE	0x01000000	/* 16 M */
+
+#if defined(CONFIG_PCI) 		/* PCI Ethernet card */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+  #define PCI_ENET0_IOADDR    	0xe0000000
+  #define PCI_ENET0_MEMADDR     0xe0000000
+  #define PCI_IDSEL_NUMBER      0x0c 	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW
+#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI 	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+
+#define CONFIG_MPC85XX_TSEC1	1
+#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
+#define CONFIG_MPC85XX_TSEC2	1
+#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
+#undef CONFIG_MPS85XX_FEC
+
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		4
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
+
+#define CONFIG_ETHER_ON_FCC2             /* define if ether on FCC   */
+#undef  CONFIG_ETHER_NONE               /* define if ether on something else */
+#define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
+
+#if (CONFIG_ETHER_INDEX == 2)
+  /*
+   * - Rx-CLK is CLK13
+   * - Tx-CLK is CLK14
+   * - Select bus for bd/buffers
+   * - Full duplex
+   */
+  #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+  #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+  #define CFG_CPMFCR_RAMTYPE    0
+#if 0
+  #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
+#else
+  #define CFG_FCC_PSMR          0
+#endif
+  #define FETH2_RST		0x01
+#elif (CONFIG_ETHER_INDEX == 3)
+  /* need more definitions here for FE3 */
+  #define FETH3_RST		0x80
+#endif  				/* CONFIG_ETHER_INDEX */
+
+/* MDIO is done through the TSEC0 control.
+*/
+#define CONFIG_MII			/* MII PHY management */
+#undef CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+
+#endif
+
+/* Environment */
+/* We use the top boot sector flash, so we have some 16K sectors for env
+ */
+#ifndef CFG_RAMBOOT
+  #define CFG_ENV_IS_IN_FLASH	1
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x60000)
+  #define CFG_ENV_SECT_SIZE	0x4000	/* 16K (one top sector) for env */
+  #define CFG_ENV_SIZE		0x2000
+#else
+  #define CFG_NO_FLASH		1	/* Flash is not usable now	*/
+  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
+  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
+  #define CFG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
+#define CONFIG_BOOTCOMMAND	"bootm 0xff000000 0xff100000"
+#define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#if defined(CFG_RAMBOOT)
+  #if defined(CONFIG_PCI)
+  #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PCI | \
+				CFG_CMD_PING | CFG_CMD_I2C) & \
+				 ~(CFG_CMD_ENV | \
+				  CFG_CMD_LOADS ))
+  #elif defined(CONFIG_TSEC_ENET)
+  #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_PING | \
+				CFG_CMD_MII | CFG_CMD_I2C ) & \
+				~(CFG_CMD_ENV))
+  #elif defined(CONFIG_ETHER_ON_FCC)
+  #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_MII | \
+				CFG_CMD_PING | CFG_CMD_I2C) & \
+				~(CFG_CMD_ENV))
+  #endif
+#else
+  #if defined(CONFIG_PCI)
+  #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PCI | \
+				CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
+  #elif defined(CONFIG_TSEC_ENET)
+  #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_PING | \
+				CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
+  #elif defined(CONFIG_ETHER_ON_FCC)
+  #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL | CFG_CMD_MII | \
+				CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
+  #endif
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"GPPP=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x1000000	/* default load address */
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		32768
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*Note: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_ETHADDR	 00:e0:0c:07:9b:8a
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
+#endif
+
+#define CONFIG_SERVERIP 	192.168.85.1
+#define CONFIG_IPADDR  		192.168.85.60
+#define CONFIG_GATEWAYIP	192.168.85.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_HOSTNAME 	STX_GP3
+#define CONFIG_ROOTPATH 	/gppproot
+#define CONFIG_BOOTFILE 	uImage
+#define CONFIG_LOADADDR		0x1000000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
new file mode 100755
index 0000000..3ffe6b2
--- /dev/null
+++ b/include/configs/stxxtc.h
@@ -0,0 +1,588 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
+ * U-Boot port on STx XTc 8xx board
+ * Mostly copied from Panto's NETTA2 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC875		1	/* This is a MPC875 CPU		*/
+#define CONFIG_STXXTC		1	/* ...on a STx XTc  board	*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115.2kbps	*/
+
+#define CONFIG_XIN		10000000	/* 10 MHz input xtal */
+
+/* Select one of few clock rates defined later in this file.
+*/
+/* #define MPC8XX_HZ		50000000 */
+#define MPC8XX_HZ		66666666
+
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot; " 								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+#define CONFIG_AUTOSCRIPT
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
+
+#define CONFIG_BOOTP_MASK		(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define	CONFIG_NET_MULTI	1 	/* the only way to get the FEC in */
+#define	FEC_ENET		1	/* eth.c needs it that way... */
+#undef CFG_DISCOVER_PHY
+#define CONFIG_MII		1
+#undef CONFIG_RMII
+
+#define CONFIG_ETHER_ON_FEC1	1
+#define CONFIG_FEC1_PHY		1 	/* phy address of FEC */
+#undef CONFIG_FEC1_PHY_NORXERR
+
+#define CONFIG_ETHER_ON_FEC2	1
+#define CONFIG_FEC2_PHY		3
+#undef CONFIG_FEC2_PHY_NORXERR
+
+#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
+
+#define CONFIG_COMMANDS       ( CONFIG_CMD_DFL	| \
+				CFG_CMD_NAND	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_PING  	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NFS)
+
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_MISC_INIT_R
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"xtc> "		/* Monitor Command Prompt	*/
+
+#define CFG_HUSH_PARSER	1
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+
+/* yes this is weird, I know :) */
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE | 0x00F00000)
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+#define CFG_RESET_ADDRESS	0x80000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	0x10000
+
+#define	CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00000000)
+#define CFG_ENV_OFFSET		0
+#define	CFG_ENV_SIZE		0x4000
+
+#define CFG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x00010000)
+#define CFG_ENV_OFFSET_REDUND	0
+#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
+
+#define CFG_FLASH_CFI		1
+#define CFG_FLASH_CFI_DRIVER	1
+#undef CFG_FLASH_USE_BUFFER_WRITE 	/* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + 0x2000000 }
+
+#define CFG_FLASH_PROTECTION
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+#if CONFIG_XIN == 10000000
+
+#if MPC8XX_HZ == 50000000
+#define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 66666666
+#define CFG_PLPRCR	((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+		 	 PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 10MHz
+#endif
+#else
+#error unsupported freq for XIN (must be 10MHz)
+#endif
+
+
+/*
+ *-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ *
+ * Note: When TBS == 0 the timebase is independent of current cpu clock.
+ */
+
+#define SCCR_MASK	SCCR_EBDF11
+#if MPC8XX_HZ > 66666666
+#define CFG_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00 | SCCR_EBDF01)
+#else
+#define CFG_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x42000000	/* FLASH bank #1	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+
+#define FLASH_BANK_MAX_SIZE	0x01000000	/* max size per chip */
+
+#define CFG_REMAP_OR_AM		0x80000000
+#define CFG_PRELIM_OR_AM	(0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+#define CFG_OR1_PRELIM	((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CFG_OR_TIMING_FLASH)
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/*
+ * BR4 and OR4 (SDRAM)
+ *
+ */
+#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+
+#define CFG_OR4_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
+#define CFG_BR4_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CFG_MAMR_PTA		 234
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_LAST_STAGE_INIT		/* needed to reset the damn phys */
+
+/****************************************************************/
+
+#define NAND_SIZE	0x00010000	/* 64K */
+#define NAND_BASE	0xF1000000
+
+/****************************************************************/
+
+/* NAND */
+#define CFG_NAND_BASE		NAND_BASE
+#define CONFIG_MTD_NAND_ECC_JFFS2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_MTD_NAND_UNSAFE
+
+#define CFG_MAX_NAND_DEVICE	1
+#undef NAND_NO_RB
+
+#define SECTORSIZE		512
+#define ADDR_COLUMN		1
+#define ADDR_PAGE		2
+#define ADDR_COLUMN_PAGE	3
+#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_MAX_FLOORS		1
+#define NAND_MAX_CHIPS		1
+
+/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
+#define NAND_DISABLE_CE(nand) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) |=  (1 << (15 - 7)); \
+	} while(0)
+
+#define NAND_ENABLE_CE(nand) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
+	} while(0)
+
+#define NAND_CTL_CLRALE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
+	} while(0)
+
+#define NAND_CTL_SETALE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) |=  (1 << (15 - 15)); \
+	} while(0)
+
+#define NAND_CTL_CLRCLE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
+	} while(0)
+
+#define NAND_CTL_SETCLE(nandptr) \
+	do { \
+		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) |=  (1 << (31 - 23)); \
+	} while(0)
+
+#ifndef NAND_NO_RB
+#define NAND_WAIT_READY(nand) \
+	do { \
+		int _tries = 0; \
+		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
+			if (++_tries > 100000) \
+				break; \
+	} while (0)
+#else
+#define NAND_WAIT_READY(nand) udelay(12)
+#endif
+
+#define WRITE_NAND_COMMAND(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define WRITE_NAND_ADDRESS(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define WRITE_NAND(d, adr) \
+	do { \
+		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
+	} while(0)
+
+#define READ_NAND(adr) \
+	((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
+
+/*****************************************************************************/
+
+#define CFG_DIRECT_FLASH_TFTP
+#define CFG_DIRECT_NAND_TFTP
+
+/*****************************************************************************/
+
+/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
+ * CxOE and CxRESET.  We use the CxOE.
+ */
+#define STATUS_LED_BIT		0x00000080		/* bit 24 */
+
+#define STATUS_LED_PERIOD	(CFG_HZ / 2)
+#define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */
+
+#ifndef __ASSEMBLY__
+
+/* LEDs */
+
+/* led_id_t is unsigned int mask */
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+	do { \
+		((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
+	} while(0)
+
+#define __led_set(_msk, _st) \
+	do { \
+		if ((_st)) \
+			((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
+		else \
+			((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
+	} while(0)
+
+#define __led_init(msk, st) __led_set(msk, st)
+
+#endif
+
+/******************************************************************************/
+
+#define CFG_CONSOLE_IS_IN_ENV		1
+#define CFG_CONSOLE_OVERWRITE_ROUTINE	1
+#define CFG_CONSOLE_ENV_OVERWRITE	1
+
+/******************************************************************************/
+
+/* use board specific hardware */
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_SHOW_ACTIVITY
+
+/*****************************************************************************/
+
+#define CONFIG_AUTO_COMPLETE	1
+#define CONFIG_CRC32_VERIFY	1
+#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1
+
+/*****************************************************************************/
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,MPC870@0"
+#define OF_TBCLK		(MPC8XX_HZ / 16)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h
new file mode 100755
index 0000000..1ee6be1
--- /dev/null
+++ b/include/configs/suzaku.h
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MICROBLAZE	1	/* This is an MicroBlaze CPU	*/
+#define CONFIG_SUZAKU		1	/* on an SUZAKU Board		*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x80000000
+#define CFG_SDRAM_SIZE		0x01000000
+#define CFG_FLASH_BASE		0xfff00000
+#define CFG_FLASH_SIZE		0x00400000
+#define CFG_RESET_ADDRESS	0xfff00100
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CFG_MONITOR_BASE        (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - (1024 * 1024))
+#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 115200 }
+
+#define CONFIG_COMMANDS		(CONFIG__CMD_DFL)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CFG_UART1_BASE		(0xFFFF2000)
+#define CONFIG_SERIAL_BASE	CFG_UART1_BASE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT		"SUZAKU> "	/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size	*/
+#define CFG_MAXARGS		16		/* max number of command args	*/
+
+#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* default load address		*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	1	/* max number of sectors on one chip	*/
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_NOWHERE	1
+#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
+#define CFG_ENV_SECT_SIZE	0x10000	/* see README - env sector total size	*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+#define CFG_INIT_RAM_ADDR	0x80000000	/* inside of SDRAM */
+#define CFG_INIT_RAM_END	0x2000		/* End of used area in RAM */
+#define CFG_GBL_DATA_SIZE	128		/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h
new file mode 100755
index 0000000..7118f3f
--- /dev/null
+++ b/include/configs/svm_sc8xx.h
@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific,
+ *                  for SinoVee Microsystems SC8xx series SBC
+ *                  http://www.fel.com.cn (Chinese)
+ *                  http://www.sinovee.com (English)
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Custom configuration */
+/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */
+/* SC85T,SC860T, FEL8xx-AT(855T/860T) */
+/*#define CONFIG_FEL8xx_AT */
+/*#define CONFIG_LCD */
+/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */
+/* #define CONFIG_50MHz */
+/* #define CONFIG_66MHz */
+/* #define CONFIG_75MHz */
+#define CONFIG_80MHz
+/*#define CONFIG_100MHz */
+/* #define CONFIG_BUS_DIV2	1 */
+/* for BOOT device port size */
+/* #define CONFIG_BOOT_8B */
+#define CONFIG_BOOT_16B
+/* #define CONFIG_BOOT_32B */
+/* #define CONFIG_CAN_DRIVER */
+/* #define DEBUG */
+#define CONFIG_FEC_ENET
+
+/* #define CONFIG_SDRAM_16M */
+#define CONFIG_SDRAM_32M
+/* #define CONFIG_SDRAM_64M */
+#define CFG_RESET_ADDRESS 0xffffffff
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* #define CONFIG_MPC823		1 */
+/* #define CONFIG_MPC850		1 */
+#define CONFIG_MPC855		1
+/* #define CONFIG_MPC860		1 */
+/* #define CONFIG_MPC860T		1 */
+
+#undef	CONFIG_WATCHDOG			/* watchdog */
+
+#define CONFIG_SVM_SC8xx		1	/* ...on SVM SC8xx series 	*/
+
+#ifdef	CONFIG_LCD			/* with LCD controller ?	*/
+/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display	*/
+#endif
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		19200	/* console baudrate = 115kbps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOARD_TYPES      1       /* support board types          */
+
+#define CONFIG_PREBOOT	"echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_EXTRA_ENV_SETTINGS                                       \
+	"nfsargs=setenv bootargs root=/dev/nfs rw "                     \
+	 "nfsroot=${serverip}:${rootpath}\0"                     \
+	"ramargs=setenv bootargs root=/dev/ram rw\0"                    \
+	"addip=setenv bootargs ${bootargs} "                            \
+	       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
+		":${hostname}:${netdev}:off panic=1\0"                  \
+		"flash_nfs=run nfsargs addip;"                                  \
+	     "bootm ${kernel_addr}\0"                                \
+	"flash_self=run ramargs addip;"                                 \
+	       "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
+	"net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0"     \
+	"rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0"                                  \
+	"bootfile=pImage-sc855t\0"                           \
+	"kernel_addr=48000000\0"                                        \
+	"ramdisk_addr=48100000\0"                                       \
+	""
+#define CONFIG_BOOTCOMMAND							\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+
+#ifdef CONFIG_LCD
+# undef	 CONFIG_STATUS_LED		/* disturbs display		*/
+#else
+# define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#endif	/* CONFIG_LCD */
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV  | \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DOC	| \
+/*				CFG_CMD_IDE     |*/ \
+				CFG_CMD_DATE	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2     "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(384 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+
+#ifdef CONFIG_BOOT_8B
+#define	CFG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
+#elif defined (CONFIG_BOOT_16B)
+#define	CFG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
+#elif defined (CONFIG_BOOT_32B)
+#define	CFG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+#endif
+
+/* Address and size of Redundant Environment Sector     */
+#define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
+
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x46454C38	/* 'SVM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+/*#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+*/
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR 0xffffff88
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+/*#define CFG_SIUMCR 0x00610c00	*/
+#define CFG_SIUMCR 0x00000000
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	0x0001
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	0x00c3
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	0x0000
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#if defined (CONFIG_100MHz)
+#define CFG_PLPRCR 0x06301000
+#define CONFIG_8xx_GCLK_FREQ 100000000
+#elif defined (CONFIG_80MHz)
+#define CFG_PLPRCR 0x04f01000
+#define CONFIG_8xx_GCLK_FREQ 80000000
+#elif defined(CONFIG_75MHz)
+#define CFG_PLPRCR 0x04a00100
+#define CONFIG_8xx_GCLK_FREQ 75000000
+#elif defined(CONFIG_66MHz)
+#define CFG_PLPRCR 0x04101000
+#define CONFIG_8xx_GCLK_FREQ 66000000
+#elif defined(CONFIG_50MHz)
+#define CFG_PLPRCR 0x03101000
+#define CONFIG_8xx_GCLK_FREQ 50000000
+#endif
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#ifdef	CONFIG_BUS_DIV2
+#define CFG_SCCR	0x02020000 | SCCR_RTSEL
+#else			/* up to 50 MHz we use a 1:1 clock */
+#define CFG_SCCR    0x02000000 | SCCR_RTSEL
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD   	/* Use IDE with PC Card	Adapter	*/
+
+#define	CONFIG_IDE_8xx_DIRECT	1	/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1 	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_BASE_ADDR       0xFE100010
+#define CFG_ATA_IDE0_OFFSET     0x0000
+/*#define CFG_ATA_IDE1_OFFSET     0x0C00 */
+#define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O
+					   */
+#define CFG_ATA_REG_OFFSET      0x0200  /* Offset for normal register accesses
+					   */
+#define CFG_ATA_ALT_OFFSET      0x0210  /* Offset for alternate registers
+					   */
+#define CONFIG_ATAPI
+#define CFG_PIO_MODE 0
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CFG_DER	0x2002000F*/
+#define CFG_DER	0x0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#if defined(CONFIG_100MHz)
+#define CFG_OR_TIMING_FLASH 0x000002f4
+#define CFG_OR_TIMING_DOC   0x000002f4
+#define CFG_MxMR_PTx 0x61000000
+#define CFG_MPTPR 0x400
+
+#elif  defined(CONFIG_80MHz)
+#define CFG_OR_TIMING_FLASH 0x00000ff4
+#define CFG_OR_TIMING_DOC   0x000001f4
+#define CFG_MxMR_PTx 0x4e000000
+#define CFG_MPTPR 0x400
+
+#elif defined(CONFIG_75MHz)
+#define CFG_OR_TIMING_FLASH 0x000008f4
+#define CFG_OR_TIMING_DOC   0x000002f4
+#define CFG_MxMR_PTx 0x49000000
+#define CFG_MPTPR 0x400
+
+#elif defined(CONFIG_66MHz)
+#define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+	OR_SCY_3_CLK | OR_EHTR | OR_BI)
+/*#define CFG_OR_TIMING_FLASH 0x000001f4 */
+#define CFG_OR_TIMING_DOC   0x000003f4
+#define CFG_MxMR_PTx  0x40000000
+#define CFG_MPTPR 0x400
+
+#else		/*   50 MHz */
+#define CFG_OR_TIMING_FLASH 0x00000ff4
+#define CFG_OR_TIMING_DOC   0x000001f4
+#define CFG_MxMR_PTx  0x30000000
+#define CFG_MPTPR 0x400
+#endif	/*CONFIG_??MHz */
+
+
+#if  defined (CONFIG_BOOT_8B)   /* 512K X 8 ,29F040 , 2MB space */
+#define CFG_OR0_PRELIM	(0xffe00000 | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
+#elif  defined (CONFIG_BOOT_16B)   /* 29lv160 X 16 , 4MB space */
+#define CFG_OR0_PRELIM	(0xffc00000 | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
+#elif defined( CONFIG_BOOT_32B )  /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
+#define CFG_OR0_PRELIM	(0xfc000000 | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#else
+#error Boot device port size missing.
+#endif
+
+/*
+ * Disk-On-Chip configuration
+ */
+
+#define CFG_DOC_SHORT_TIMEOUT
+#define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices    */
+
+#define CFG_DOC_SUPPORT_2000
+#define CFG_DOC_SUPPORT_MILLENNIUM
+#define CFG_DOC_BASE 0x80000000
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h
new file mode 100755
index 0000000..dac1eb7
--- /dev/null
+++ b/include/configs/tb0229.h
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2003
+ * Masami Komiya <mkomiya@sonare.it>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Config header file for TANBAC TB0229 board using an VR4131 CPU module
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS32		1	/* MIPS 4Kc CPU core	*/
+#define CONFIG_TB0229		1	/* on a TB0229 Board	*/
+
+#ifndef CPU_CLOCK_RATE
+#define CPU_CLOCK_RATE	200000000	/* 200 MHz clock for the MIPS core */
+#endif
+#define CPU_TCLOCK_RATE 16588800	/* 16.5888 MHz for TClock */
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"boot\" for the network boot using DHCP, TFTP and NFS;" \
+	"echo Type \"run netboot_initrd\" for the network boot with initrd;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo Type \"run flash_local\" to mount local root filesystem;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netboot=dhcp;tftp;run netargs; bootm\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0"		\
+	"localargs=setenv bootargs root=1F02 ip=dhcp\0"			\
+	"addmisc=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate} "				\
+		"read-only=readonly\0"					\
+	"netargs=run nfsargs addmisc\0"					\
+	"flash_nfs=run nfsargs addmisc;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_local=run localargs addmisc;"				\
+		"bootm ${kernel_addr}\0"				\
+	"netboot_initrd=dhcp;tftp;tftp 80600000 initrd;"		\
+		"setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\
+		"run addmisc;"						\
+		"bootm 80400000 80600000\0"				\
+	"rootpath=/export/miniroot-mipsel\0"				\
+	"autoload=no\0"							\
+	"kernel_addr=BFC60000\0"					\
+	"ramdisk_addr=B0100000\0"					\
+	"u-boot=u-boot.bin\0"						\
+	"bootfile=uImage\0"						\
+	"load=dhcp;tftp 80400000 ${u-boot}\0"				\
+	"load_kernel=dhcp;tftp 80400000 ${bootfile}\0"			\
+	"update_uboot=run load;"					\
+		"protect off BFC00000 BFC3FFFF;"			\
+		"erase BFC00000 BFC3FFFF;"				\
+		"cp.b 80400000 BFC00000 ${filesize}\0"			\
+	"update_kernel=run load_kernel;"				\
+		"erase BFC60000 BFD5FFFF;"				\
+		"cp.b 80400000 BFC60000 ${filesize}\0"			\
+	"initenv=erase bfc40000 bfc5ffff\0"				\
+	""
+/*#define CONFIG_BOOTCOMMAND	"run flash_local" */
+#define CONFIG_BOOTCOMMAND	"run netboot"
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
+				 CFG_CMD_ASKENV | \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_PCI	| \
+				 CFG_CMD_ELF	)
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory	     */
+#define CFG_PROMPT		"# "		/* Monitor Command Prompt    */
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size   */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args*/
+
+#define CFG_MALLOC_LEN		128*1024
+
+#define CFG_BOOTPARAMS_LEN	128*1024
+
+#define CFG_HZ			(CPU_TCLOCK_RATE/4)
+
+#define CFG_SDRAM_BASE		0x80000000
+
+#define CFG_LOAD_ADDR		0x80400000	/* default load address */
+
+#define CFG_MEMTEST_START	0x80000000
+#define CFG_MEMTEST_END		0x80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+
+#define PHYS_FLASH_1		0xbfc00000 /* Flash Bank #1 */
+
+/* The following #defines are needed to get flash environment right */
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MONITOR_LEN		(192 << 10)
+
+#define CFG_INIT_SP_OFFSET	0x400000
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20 * CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_IS_IN_FLASH	1
+
+/* Address and size of Primary Environment Sector	*/
+#define CFG_ENV_ADDR		0xBFC40000
+#define CFG_ENV_SIZE		0x20000
+
+#define CFG_DIRECT_FLASH_TFTP
+
+#define CONFIG_NR_DRAM_BANKS	1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384
+#define CFG_ICACHE_SIZE		16384
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Serial Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	 1
+#define CFG_NS16550_CLK		 18432000
+#define CFG_NS16550_COM1	 0xaf000800
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ */
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+
+#define CONFIG_RTL8139
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/trab.h b/include/configs/trab.h
new file mode 100755
index 0000000..85ee756
--- /dev/null
+++ b/include/configs/trab.h
@@ -0,0 +1,430 @@
+/*
+ * (C) Copyright 2002-2005
+ * Gary Jennejohn <gj@denx.de>
+ *
+ * Configuation settings for the TRAB board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Default configuration is with 8 MB Flash, 32 MB RAM
+ */
+#if (!defined(CONFIG_FLASH_8MB)) && (!defined(CONFIG_FLASH_16MB))
+# define CONFIG_FLASH_8MB	/*  8 MB Flash	*/
+#endif
+#if (!defined(CONFIG_RAM_16MB)) && (!defined(CONFIG_RAM_32MB))
+# define CONFIG_RAM_32MB	/* 32 MB SDRAM	*/
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T		1	/* This is an arm920t CPU	*/
+#define CONFIG_S3C2400		1	/* in a SAMSUNG S3C2400 SoC	*/
+#define CONFIG_TRAB		1	/* on a TRAB Board		*/
+#undef CONFIG_TRAB_50MHZ		/* run the CPU at 50 MHz	*/
+#define LITTLEENDIAN		1	/* used by usb_ohci.c		*/
+
+/* automatic software updates (see board/trab/auto_update.c) */
+#define CONFIG_AUTO_UPDATE	1
+
+/* input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ	12000000 /* TRAB has 12 MHz input clock */
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+
+#define CFG_DEVICE_NULLDEV	 1	/* enble null device		*/
+#define CONFIG_SILENT_CONSOLE	 1	/* enable silent startup	*/
+
+#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+
+/***********************************************************
+ * I2C stuff:
+ * the TRAB is equipped with an ATMEL 24C04 EEPROM at
+ * address 0x54 with 8bit addressing
+ ***********************************************************/
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#define CFG_I2C_SPEED 		100000	/* I2C speed */
+#define CFG_I2C_SLAVE 		0x7F	/* I2C slave addr */
+
+#define CFG_I2C_EEPROM_ADDR	0x54	/* EEPROM address */
+#define CFG_I2C_EEPROM_ADDR_LEN	1	/* 1 address byte */
+
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
+#define CFG_EEPROM_PAGE_WRITE_BITS 3	/* 8 bytes page write mode on 24C04 */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* USB stuff */
+#define CONFIG_USB_OHCI		1
+#define CONFIG_USB_STORAGE	1
+#define CONFIG_DOS_PARTITION	1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_CS8900	1	/* we have a CS8900 on-board */
+#define CS8900_BASE		0x07000300 /* agrees with WIN CE PA */
+#define CS8900_BUS16		1 /* the Linux driver does accesses as shorts */
+
+#define CONFIG_DRIVER_S3C24X0_I2C 1	/* we use the buildin I2C controller */
+
+#define CONFIG_VFD		1	/* VFD linear frame buffer driver */
+#define VFD_TEST_LOGO		1	/* output a test logo to the VFDs */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		1	/* we use SERIAL 1 on TRAB */
+
+#define CONFIG_HWFLOW			/* include RTS/CTS flow control support	*/
+
+#define CONFIG_MODEM_SUPPORT	1	/* enable modem initialization stuff */
+
+#define	CONFIG_MODEM_KEY_MAGIC	"23"	/* hold down these keys to enable modem */
+
+/*
+ * The following enables modem debugging stuff. The dbg() and
+ * 'char screen[1024]' are used for debug printfs. Unfortunately,
+ * it is usable only from BDI
+ */
+#undef CONFIG_MODEM_SUPPORT_DEBUG
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#define	CONFIG_TIMESTAMP	1	/* Print timestamp info for images */
+
+/* Use s3c2400's RTC */
+#define CONFIG_RTC_S3C24X0	1
+
+#ifdef CONFIG_HWFLOW
+#define CONFIG_COMMANDS_ADD_HWFLOW	CFG_CMD_HWFLOW
+#else
+#define	CONFIG_COMMANDS_ADD_HWFLOW	0
+#endif
+
+#ifdef	CONFIG_VFD
+#define CONFIG_COMMANDS_ADD_VFD		CFG_CMD_VFD
+#else
+#define CONFIG_COMMANDS_ADD_VFD		0
+#endif
+
+#ifdef CONFIG_DRIVER_S3C24X0_I2C
+#define CONFIG_COMMANDS_ADD_EEPROM	CFG_CMD_EEPROM
+#define CONFIG_COMMANDS_I2C		CFG_CMD_I2C
+#else
+#define CONFIG_COMMANDS_ADD_EEPROM	0
+#define CONFIG_COMMANDS_I2C		0
+#endif
+
+#ifndef USE_920T_MMU
+#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
+				CONFIG_COMMANDS_ADD_HWFLOW	| \
+				CONFIG_COMMANDS_ADD_VFD		| \
+				CONFIG_COMMANDS_ADD_EEPROM	| \
+				CONFIG_COMMANDS_I2C		| \
+				CFG_CMD_BSP			| \
+				CFG_CMD_DATE			| \
+				CFG_CMD_DHCP			| \
+				CFG_CMD_FAT			| \
+				CFG_CMD_JFFS2			| \
+				CFG_CMD_NFS			| \
+				CFG_CMD_SNTP			| \
+				CFG_CMD_USB	)
+#else
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL			| \
+				CONFIG_COMMANDS_ADD_HWFLOW	| \
+				CONFIG_COMMANDS_ADD_VFD		| \
+				CONFIG_COMMANDS_ADD_EEPROM	| \
+				CONFIG_COMMANDS_I2C		| \
+				CFG_CMD_BSP			| \
+				CFG_CMD_DATE			| \
+				CFG_CMD_DHCP			| \
+				CFG_CMD_FAT			| \
+				CFG_CMD_JFFS2			| \
+				CFG_CMD_NFS			| \
+				CFG_CMD_SNTP			| \
+				CFG_CMD_USB	)
+#endif
+
+/* moved up */
+#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow to break in always */
+#define CONFIG_PREBOOT		"echo;echo *** booting ***;echo"
+#define CONFIG_BOOTARGS		"console=ttyS0"
+#define CONFIG_NETMASK		255.255.0.0
+#define CONFIG_IPADDR		192.168.3.68
+#define CONFIG_HOSTNAME		trab
+#define CONFIG_SERVERIP		192.168.3.1
+#define CONFIG_BOOTCOMMAND	"burn_in"
+
+#ifndef CONFIG_FLASH_8MB	/* current config: 16 MB flash */
+#ifdef CFG_HUSH_PARSER
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"nfs_args=setenv bootargs root=/dev/nfs rw " \
+		"nfsroot=$serverip:$rootpath\0" \
+	"rootpath=/opt/eldk/arm_920TDI\0" \
+	"ram_args=setenv bootargs root=/dev/ram rw\0" \
+	"add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
+	"add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \
+	"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
+	"load=tftp C100000 ${u-boot}\0" \
+	"update=protect off 0 5FFFF;era 0 5FFFF;" \
+		"cp.b C100000 0 $filesize\0" \
+	"loadfile=/tftpboot/TRAB/uImage\0" \
+	"loadaddr=c400000\0" \
+	"net_load=tftpboot $loadaddr $loadfile\0" \
+	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
+	"kernel_addr=00060000\0" \
+	"flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \
+	"mdm_init1=ATZ\0" \
+	"mdm_init2=ATS0=1\0" \
+	"mdm_flow_control=rts/cts\0"
+#else /* !CFG_HUSH_PARSER */
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"nfs_args=setenv bootargs root=/dev/nfs rw " \
+		"nfsroot=${serverip}:${rootpath}\0" \
+	"rootpath=/opt/eldk/arm_920TDI\0" \
+	"ram_args=setenv bootargs root=/dev/ram rw\0" \
+	"add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
+	"add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \
+	"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
+	"load=tftp C100000 ${u-boot}\0" \
+	"update=protect off 0 5FFFF;era 0 5FFFF;" \
+		"cp.b C100000 0 ${filesize}\0" \
+	"loadfile=/tftpboot/TRAB/uImage\0" \
+	"loadaddr=c400000\0" \
+	"net_load=tftpboot ${loadaddr} ${loadfile}\0" \
+	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
+	"kernel_addr=000C0000\0" \
+	"flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \
+	"mdm_init1=ATZ\0" \
+	"mdm_init2=ATS0=1\0" \
+	"mdm_flow_control=rts/cts\0"
+#endif	/* CFG_HUSH_PARSER */
+#else	/* CONFIG_FLASH_8MB 	 => 8 MB flash */
+#ifdef CFG_HUSH_PARSER
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"nfs_args=setenv bootargs root=/dev/nfs rw " \
+		"nfsroot=$serverip:$rootpath\0" \
+	"rootpath=/opt/eldk/arm_920TDI\0" \
+	"ram_args=setenv bootargs root=/dev/ram rw\0" \
+	"add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
+	"add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \
+	"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
+	"load=tftp C100000 ${u-boot}\0" \
+	"update=protect off 0 3FFFF;era 0 3FFFF;" \
+		"cp.b C100000 0 $filesize;" \
+		"setenv filesize;saveenv\0" \
+	"loadfile=/tftpboot/TRAB/uImage\0" \
+	"loadaddr=C400000\0" \
+	"net_load=tftpboot $loadaddr $loadfile\0" \
+	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
+	"kernel_addr=000C0000\0" \
+	"flash_nfs=run nfs_args add_net add_misc;bootm $kernel_addr\0" \
+	"mdm_init1=ATZ\0" \
+	"mdm_init2=ATS0=1\0" \
+	"mdm_flow_control=rts/cts\0"
+#else /* !CFG_HUSH_PARSER */
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"nfs_args=setenv bootargs root=/dev/nfs rw " \
+		"nfsroot=${serverip}:${rootpath}\0" \
+	"rootpath=/opt/eldk/arm_920TDI\0" \
+	"ram_args=setenv bootargs root=/dev/ram rw\0" \
+	"add_net=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
+	"add_misc=setenv bootargs ${bootargs} console=ttyS0 panic=1\0" \
+	"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
+	"load=tftp C100000 ${u-boot}\0" \
+	"update=protect off 0 3FFFF;era 0 3FFFF;" \
+		"cp.b C100000 0 ${filesize};" \
+		"setenv filesize;saveenv\0" \
+	"loadfile=/tftpboot/TRAB/uImage\0" \
+	"loadaddr=C400000\0" \
+	"net_load=tftpboot ${loadaddr} ${loadfile}\0" \
+	"net_nfs=run net_load nfs_args add_net add_misc;bootm\0" \
+	"kernel_addr=000C0000\0" \
+	"flash_nfs=run nfs_args add_net add_misc;bootm ${kernel_addr}\0" \
+	"mdm_init1=ATZ\0" \
+	"mdm_init2=ATS0=1\0" \
+	"mdm_flow_control=rts/cts\0"
+#endif /* CFG_HUSH_PARSER */
+#endif	/* CONFIG_FLASH_8MB */
+
+#if 1	/* feel free to disable for development */
+#define	CONFIG_AUTOBOOT_KEYED		/* Enable password protection	*/
+#define CONFIG_AUTOBOOT_PROMPT	"\nEnter password - autoboot in %d sec...\n"
+#define CONFIG_AUTOBOOT_DELAY_STR	"R"	/* 1st "password"	*/
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"TRAB # "	/* Monitor Command Prompt	*/
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0C000000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0D000000	/* 16 MB in DRAM	*/
+
+#undef CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x0CF00000	/* default load address	*/
+
+#ifdef CONFIG_TRAB_50MHZ
+/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
+/* it to wrap 100 times (total 1562500) to get 1 sec. */
+/* this should _really_ be calculated !! */
+#define	CFG_HZ			1562500
+#else
+/* the PWM TImer 4 uses a counter of 10390 for 10 ms, so we need */
+/* it to wrap 100 times (total 1039000) to get 1 sec. */
+/* this should _really_ be calculated !! */
+#define	CFG_HZ			1039000
+#endif
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/
+
+/*-----------------------------------------------------------------------
+ * burn-in test stuff.
+ *
+ * BURN_IN_CYCLE_DELAY defines the seconds to wait between each burn-in cycle
+ * Because the burn-in test itself causes also an delay of about 4 seconds,
+ * this time must be subtracted from the desired overall burn-in cycle time.
+ */
+#define BURN_IN_CYCLE_DELAY	296	/* seconds between burn-in cycles */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x0C000000	/* SDRAM Bank #1 */
+#ifndef CONFIG_RAM_16MB
+#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
+#else
+#define PHYS_SDRAM_1_SIZE	0x01000000	/* 16 MB */
+#endif
+
+#define CFG_FLASH_BASE		0x00000000	/* Flash Bank #1 */
+
+/* The following #defines are needed to get flash environment right */
+#define	CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MONITOR_LEN		(256 << 10)
+
+/* Dynamic MTD partition support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=0"
+
+/* production flash layout */
+#define MTDPARTS_DEFAULT	"mtdparts=0:32k(Firmware1)ro,"		\
+						"16k(Env1),"		\
+						"16k(Env2),"		\
+						"320k(Firmware2)ro,"	\
+						"896k(Kernel),"		\
+						"5376k(Root-FS),"	\
+						"1408k(JFFS2),"		\
+						"-(VFD)"
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#ifndef CONFIG_FLASH_8MB
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+#else
+#define CFG_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+#endif
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ) /* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+
+/* Address and size of Primary Environment Sector	*/
+#ifndef CONFIG_FLASH_8MB
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
+#define CFG_ENV_SIZE		0x4000
+#define CFG_ENV_SECT_SIZE	0x20000
+#else
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x4000)
+#define CFG_ENV_SIZE		0x4000
+#define CFG_ENV_SECT_SIZE	0x4000
+#endif
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/* Initial value of the on-board touch screen brightness */
+#define CFG_BRIGHTNESS 0x20
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/uc100.h b/include/configs/uc100.h
new file mode 100755
index 0000000..c4e629a
--- /dev/null
+++ b/include/configs/uc100.h
@@ -0,0 +1,507 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1
+#define CONFIG_MPC860T		1
+#define CONFIG_MPC862		1       /* enable 862 since the         */
+#define CONFIG_MPC857		1       /* 857 is a variant of the 862  */
+
+#define CONFIG_UC100		1	/* ...on a UC100 module	        */
+
+#define MPC8XX_FACT		4		/* Multiply by 4	*/
+#define MPC8XX_XIN		25000000	/* 25.0 MHz in		*/
+#define CONFIG_8xx_GCLK_FREQ	(MPC8XX_FACT * MPC8XX_XIN)
+				    /* define if cant' use get_gclk_freq */
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/uc100/uImage\0"				\
+	"kernel_addr=40000000\0"					\
+	"ramdisk_addr=40100000\0"					\
+	"load=tftp 100000 /tftpboot/uc100/u-boot.bin\0"			\
+	"update=protect off 40700000 4073ffff;era 40700000 4073ffff;"	\
+		"cp.b 100000 40700000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#undef CONFIG_STATUS_LED                /* no status-led                */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef CONFIG_RTC_MPC8xx
+#define CFG_I2C_RTC_ADDR	0x51	/* PCF8563 RTC			*/
+#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
+
+/*
+ * Power On Self Test support
+ */
+#define CONFIG_POST	      ( CFG_POST_CACHE		| \
+				CFG_POST_MEMORY		| \
+				CFG_POST_CPU		| \
+				CFG_POST_UART		| \
+				CFG_POST_SPR )
+#undef  CONFIG_POST
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG       CFG_CMD_DIAG
+#else
+#define CFG_CMD_POST_DIAG	0
+#endif
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE    | \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_POST_DIAG | \
+				CFG_CMD_SNTP	)
+
+#define CONFIG_NETCONSOLE
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE+0x00700000) /* resetvec fff00100*/
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*-----------------------------------------------------------------------
+ * Address accessed to reset the board - must not be mapped/assigned
+ */
+#define CFG_RESET_ADDRESS       0x90000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI				/* The flash is CFI compatible  */
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
+#define CFG_FLASH_CFI_AMD_RESET	1		/* AMD RESET for STM 29W320DB!  */
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE+CFG_MONITOR_LEN)
+#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	0x00000000
+#define CFG_SCCR        (SCCR_EBDF11)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CFG_OR_TIMING_FLASH	(0x00000d24)
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_BR1_PRELIM  0x00000081  /* Chip select for SDRAM (32 Bit, UPMA) */
+#define CFG_OR1_PRELIM  0xfc000a00
+#define CFG_BR2_PRELIM  0x80000001  /* Chip select for SRAM (32 Bit, GPCM) */
+#define CFG_OR2_PRELIM  0xfff00d24
+#define CFG_BR3_PRELIM  0x80600401  /* Chip select for Display (8 Bit, GPCM) */
+#define CFG_OR3_PRELIM  0xffff8f44
+#define CFG_BR4_PRELIM  0xc05108c1  /* Chip select for Interbus MPM (16 Bit, UPMB) */
+#define CFG_OR4_PRELIM  0xffff0300
+#define CFG_BR5_PRELIM  0xc0500401  /* Chip select for Interbus Status (8 Bit, GPCM) */
+#define CFG_OR5_PRELIM  0xffff8db0
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ *  50 MHz =>  50.000.000 / Divider =  98
+ *  66 Mhz =>  66.000.000 / Divider = 129
+ *  80 Mhz =>  80.000.000 / Divider = 156
+ * 100 Mhz => 100.000.000 / Divider = 195
+ */
+
+#define CFG_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CFG_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define	CFG_MAMR_VAL	0x30904114	/* for SDRAM */
+#define	CFG_MBMR_VAL	0xff001111	/* for Interbus-MPM */
+
+/*-----------------------------------------------------------------------
+ * I2C stuff
+ */
+
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
+
+#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SOFT_I2C */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (24C164)
+ */
+#define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM AT24C164		*/
+#define CFG_I2C_EEPROM_ADDR_LEN	1
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
+#define FEC_ENET
+#define CONFIG_MII
+#define CFG_DISCOVER_PHY	1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h
new file mode 100755
index 0000000..d312b65
--- /dev/null
+++ b/include/configs/utx8245.h
@@ -0,0 +1,420 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Gregory E. Allen, gallen@arlut.utexas.edu
+ * Matthew E. Karger, karger@arlut.utexas.edu
+ * Applied Research Laboratories, The University of Texas at Austin
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * Configuration settings for the utx8245 board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X		1
+#define CONFIG_MPC8245		1
+#define CONFIG_UTX8245		1
+#define DEBUG				1
+
+#define CONFIG_IDENT_STRING     " [UTX5] "
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		57600
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_AUTOBOOT_PROMPT 	"autoboot in %d seconds\n"
+#define CONFIG_BOOTCOMMAND	"run nfsboot"	/* autoboot command	*/
+#define CONFIG_BOOTARGS		"root=/dev/ram console=ttyS0,57600" /* RAMdisk */
+#define CONFIG_ETHADDR		00:AA:00:14:00:05	/* UTX5 */
+#define CONFIG_SERVERIP		10.8.17.105	/* Spree */
+#define CFG_TFTP_LOADADDR	10000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel_addr=FFA00000\0" \
+	"ramdisk_addr=FF800000\0" \
+	"u-boot_startaddr=FFB00000\0" \
+	"u-boot_endaddr=FFB2FFFF\0" \
+	"nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
+nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
+	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
+	"smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
+	"fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
+	"nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
+	"ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
+	"smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
+	"fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
+	"update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
+${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
+${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
+protect on ${u-boot_startaddr} ${u-boot_endaddr}"
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_COMMANDS		(CFG_CMD_DFL | CFG_CMD_BDI | CFG_CMD_PCI \
+								| CFG_CMD_FLASH | CFG_CMD_MEMORY \
+								| CFG_CMD_ENV | CFG_CMD_CONSOLE \
+								| CFG_CMD_LOADS | CFG_CMD_LOADB \
+								| CFG_CMD_IMI | CFG_CMD_CACHE \
+								| CFG_CMD_RUN | CFG_CMD_ECHO \
+								| CFG_CMD_REGINFO | CFG_CMD_NET\
+								| CFG_CMD_DHCP | CFG_CMD_I2C \
+								| CFG_CMD_DATE)
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT	"=> "			/* Monitor Command Prompt	*/
+#define CFG_CBSIZE	256				/* Console I/O Buffer Size	*/
+
+/* Print Buffer Size */
+#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
+
+
+/*-----------------------------------------------------------------------
+ * PCI configuration
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI				/* include pci support		*/
+#undef CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_EEPRO100_SROM_WRITE
+
+#define PCI_ENET0_IOADDR	0xF0000000
+#define PCI_ENET0_MEMADDR	0xF0000000
+
+#define PCI_FIREWIRE_IOADDR		0xF1000000
+#define PCI_FIREWIRE_MEMADDR	0xF1000000
+/*
+#define PCI_ENET0_IOADDR	0xFE000000
+#define PCI_ENET0_MEMADDR	0x80000000
+
+#define PCI_FIREWIRE_IOADDR	0x81000000
+#define PCI_FIREWIRE_MEMADDR	0x81000000
+*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE	    0x00000000
+#define CFG_MAX_RAM_SIZE    0x10000000	/* 256MB  */
+/*#define CFG_VERY_BIG_RAM	1 */
+
+/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
+ * is actually located at FFF00100.  Therefore, U-Boot is
+ * physically located at 0xFFB0_0000, but is also mirrored at
+ * 0xFFF0_0000.
+ */
+#define CFG_RESET_ADDRESS   0xFFF00100
+
+#define CFG_EUMB_ADDR	    0xFC000000
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+
+#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+
+/*#define CFG_DRAM_TEST		1 */
+#define CFG_MEMTEST_START   0x00003000	/* memtest works on	0...256 MB	*/
+#define CFG_MEMTEST_END	    0x0ff8ffa7	/* in SDRAM, skips exception */
+										/* vectors and U-Boot */
+
+
+/*--------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ *------------------------------------------------------------------*/
+#define CFG_INIT_DATA_SIZE    128	/* Size in bytes reserved for */
+									/* initial data */
+#define CFG_INIT_RAM_ADDR     0x40000000
+#define CFG_INIT_RAM_END      0x1000
+#define CFG_INIT_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_GBL_DATA_SIZE	128
+#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*--------------------------------------------------------------------
+ * NS16550 Configuration
+ *------------------------------------------------------------------*/
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE	1
+
+#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
+#	define CFG_NS16550_CLK		get_bus_freq(0)
+#else
+#	define CFG_NS16550_CLK 33000000
+#endif
+
+#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
+#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
+#define CFG_NS16550_COM3	0xFF000000
+#define CFG_NS16550_COM4	0xFF000008
+
+/*--------------------------------------------------------------------
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ *------------------------------------------------------------------*/
+
+#define CONFIG_SYS_CLK_FREQ  33000000
+#define CFG_HZ				1000
+
+/*#define CFG_ETH_DEV_FN	     0x7800 */
+/*#define CFG_ETH_IOBASE	     0x00104000 */
+
+/*--------------------------------------------------------------------
+ * I2C Configuration
+ *------------------------------------------------------------------*/
+#if 1
+#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
+#undef  CONFIG_SOFT_I2C				/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+#endif
+
+#define CONFIG_RTC_PCF8563	1		/* enable I2C support for */
+									/* Philips PCF8563 RTC */
+#define CFG_I2C_RTC_ADDR	0x51	/* Philips PCF8563 RTC address */
+
+/*--------------------------------------------------------------------
+ *	Memory Control Configuration Register values
+ *	- see sec. 4.12 of MPC8245 UM
+ *------------------------------------------------------------------*/
+
+/**** MCCR1 ****/
+#define CFG_ROMNAL	    0
+#define CFG_ROMFAL	    10		/* (tacc=70ns)*mem_freq - 2,
+									mem_freq = 100MHz */
+
+#define CFG_BANK7_ROW	0		/* SDRAM bank 7-0 row address */
+#define CFG_BANK6_ROW	0		/* 	bit count */
+#define CFG_BANK5_ROW	0
+#define CFG_BANK4_ROW	0
+#define CFG_BANK3_ROW	0
+#define CFG_BANK2_ROW	0
+#define CFG_BANK1_ROW	2
+#define CFG_BANK0_ROW	2
+
+/**** MCCR2, refresh interval clock cycles ****/
+#define CFG_REFINT	    480	    /* 33 MHz SDRAM clock was 480 */
+
+/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
+#define CFG_BSTOPRE	    1023	/* burst to precharge[0..9], */
+								/* sets open page interval */
+
+/**** MCCR3 ****/
+#define CFG_REFREC	    7	    /* Refresh to activate interval, trc */
+
+/**** MCCR4 ****/
+#define CFG_PRETOACT	    2	    /* trp */
+#define CFG_ACTTOPRE	    7	    /* trcd + (burst length - 1) + trdl */
+#define CFG_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
+#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type, sequential */
+#define CFG_ACTORW	    	2		/* trcd min */
+#define CFG_DBUS_SIZE2		1		/* set for 8-bit RCS1, clear for 32,64 */
+#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CFG_EXTROM	    0			/* we don't need extended ROM space */
+#define CFG_REGDIMM	    0
+
+/* calculate according to formula in sec. 6-22 of 8245 UM */
+#define CFG_PGMAX           50		/* how long the 8245 retains the */
+									/* currently accessed page in memory */
+									/* was 45 */
+
+#define CFG_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note */
+								/* bits 7,6, and 3-0 MUST be 0 */
+
+#if 0
+#define CFG_DLL_MAX_DELAY	0x04
+#else
+#define CFG_DLL_MAX_DELAY	0
+#endif
+#if 0							/* need for 33MHz SDRAM */
+#define CFG_DLL_EXTEND	0x80
+#else
+#define CFG_DLL_EXTEND	0
+#endif
+#define CFG_PCI_HOLD_DEL 0x20
+
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these values to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8245 user manual.
+ */
+
+#define CFG_BANK0_START	    0x00000000
+#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE/2 - 1)
+#define CFG_BANK0_ENABLE    1
+#define CFG_BANK1_START	    CFG_MAX_RAM_SIZE/2
+#define CFG_BANK1_END	    (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK1_ENABLE    1
+#define CFG_BANK2_START	    0x3ff00000		/* not available in this design */
+#define CFG_BANK2_END	    0x3fffffff
+#define CFG_BANK2_ENABLE    0
+#define CFG_BANK3_START	    0x3ff00000
+#define CFG_BANK3_END	    0x3fffffff
+#define CFG_BANK3_ENABLE    0
+#define CFG_BANK4_START	    0x3ff00000
+#define CFG_BANK4_END	    0x3fffffff
+#define CFG_BANK4_ENABLE    0
+#define CFG_BANK5_START	    0x3ff00000
+#define CFG_BANK5_END	    0x3fffffff
+#define CFG_BANK5_ENABLE    0
+#define CFG_BANK6_START	    0x3ff00000
+#define CFG_BANK6_END	    0x3fffffff
+#define CFG_BANK6_ENABLE    0
+#define CFG_BANK7_START	    0x3ff00000
+#define CFG_BANK7_END	    0x3fffffff
+#define CFG_BANK7_ENABLE    0
+
+/*--------------------------------------------------------------------*/
+/* 4.4 - Output Driver Control Register */
+/*--------------------------------------------------------------------*/
+#define CFG_ODCR	    0xe5
+
+/*--------------------------------------------------------------------*/
+/* 4.8 - Error Handling Registers */
+/*-------------------------------CFG_SDMODE_BURSTLEN-------------------------------------*/
+#define CFG_ERRENR1	0x11	/* enable SDRAM refresh overflow error */
+
+/* SDRAM 0-256 MB */
+#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+/*#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
+#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in dcache */
+#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+
+#define CFG_IBAT2L  (CFG_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT2U  (CFG_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI memory */
+/*#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
+/*#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
+
+/*Flash, config addrs, etc. */
+#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L  CFG_IBAT0L
+#define CFG_DBAT0U  CFG_IBAT0U
+#define CFG_DBAT1L  CFG_IBAT1L
+#define CFG_DBAT1U  CFG_IBAT1U
+#define CFG_DBAT2L  CFG_IBAT2L
+#define CFG_DBAT2U  CFG_IBAT2U
+#define CFG_DBAT3L  CFG_IBAT3L
+#define CFG_DBAT3U  CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE	    0xFF800000
+#define CFG_MAX_FLASH_BANKS	1			/* Max number of flash banks */
+
+/*	NOTE: environment is not EMBEDDED in the u-boot code.
+	It's stored in flash in its own separate sector.  */
+#define CFG_ENV_IS_IN_FLASH	    1
+
+#if 1	/* AMD AM29LV033C */
+#define CFG_MAX_FLASH_SECT	64		/* Max number of sectors in one bank */
+#define CFG_ENV_ADDR		0xFFBF0000	/* flash sector SA63 */
+#define CFG_ENV_SECT_SIZE	(64*1024)	/* Size of the Environment Sector */
+#else	/* AMD AM29LV116D */
+#define CFG_MAX_FLASH_SECT	35	/* Max number of sectors in one bank */
+#define CFG_ENV_ADDR		0xFF9FA000	/* flash sector SA33 */
+#define CFG_ENV_SECT_SIZE	(8*1024)	/* Size of the Environment Sector */
+#endif /* #if */
+
+#define CFG_ENV_SIZE		CFG_ENV_SECT_SIZE		/* Size of the Environment */
+#define CFG_ENV_OFFSET		0			/* starting right at the beginning */
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/v37.h b/include/configs/v37.h
new file mode 100755
index 0000000..a2e99b5
--- /dev/null
+++ b/include/configs/v37.h
@@ -0,0 +1,391 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_V37		1	/* ...on a Marel V37 board 	*/
+
+#define CONFIG_LCD
+#define CONFIG_SHARP_LQ084V1DG21
+#undef CONFIG_LCD_LOGO
+
+/*-----------------------------------------------------------------------------
+ * I2C Configuration
+ *-----------------------------------------------------------------------------
+ */
+#define CONFIG_I2C              1
+#define CFG_I2C_SLAVE           0x2
+
+#define	CONFIG_8xx_CONS_SMC1	1
+#undef	CONFIG_8xx_CONS_SMC2		/* Console is on SMC2		*/
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600	/* console baudrate = 115kbps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot; " 								\
+	"setenv bootargs console=tty0 "                                   \
+	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "		 	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " 	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_CAN_DRIVER	1	/* CAN Driver support enabled	*/
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_JFFS2	| \
+				CFG_CMD_DATE	)
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor1"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor1=v37-1"
+#define MTDPARTS_DEFAULT	"mtdparts=v37-1:-(jffs2)"
+*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE0		0x40000000
+#define CFG_FLASH_BASE1		0x60000000
+#define CFG_FLASH_BASE		CFG_FLASH_BASE1
+
+#if defined(DEBUG)
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE0
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_NVRAM	1
+#define	CFG_ENV_ADDR		0x80000000/* Address of Environment */
+#define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+#define CFG_ENV_OFFSET		0
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	0xFFFFFF88
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/*%%%#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+/*
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+*/
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+/* up to 50 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* up to 50 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_COM00 | SCCR_TBS)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/
+
+#define CFG_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
+
+#define CFG_OR_TIMING_FLASH 	0xF56
+
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V)
+
+#define CFG_OR5_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR5_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V)
+
+/*
+ * BR1 and OR1 (Battery backed SRAM)
+ */
+#define	CFG_BR1_PRELIM	0x80000401
+#define CFG_OR1_PRELIM	0xFFC00736
+
+/*
+ * BR2 and OR2 (SDRAM)
+ */
+#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB */
+
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/* Marel V37 mem setting */
+
+#define	CFG_BR3_CAN	0xC0000401
+#define CFG_OR3_CAN	0xFFFF0724
+
+/*
+#define	CFG_BR3_PRELIM	0xFA400001
+#define CFG_OR3_PRELIM	0xFFFF8910
+#define	CFG_BR4_PRELIM	0xFA000401
+#define CFG_OR4_PRELIM	0xFFFE0970
+*/
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+
+/*
+ * Refresh clock Prescalar
+ */
+#define CFG_MPTPR	MPTPR_PTP_DIV16
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 10 column SDRAM */
+#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |	\
+			 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/versatile.h b/include/configs/versatile.h
new file mode 100755
index 0000000..16db43b
--- /dev/null
+++ b/include/configs/versatile.h
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ * Configuration for Versatile PB.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core  */
+#define CONFIG_VERSATILE	1	/* in Versatile Platform Board	*/
+#define CONFIG_ARCH_VERSATILE   1	/* Specifically, a Versatile	*/
+
+
+#define CFG_MEMTEST_START       0x100000
+#define CFG_MEMTEST_END         0x10000000
+#define CFG_HZ                  (1000000 / 256)
+#define CFG_TIMERBASE           0x101E2000	/* Timer 0 and 1 base */
+
+#define CFG_TIMER_INTERVAL	10000
+#define CFG_TIMER_RELOAD	(CFG_TIMER_INTERVAL >> 4)	/* Divide by 16 */
+#define CFG_TIMER_CTRL          0x84				/* Enable, Clock / 16 */
+
+/*
+ * control registers
+ */
+#define VERSATILE_SCTL_BASE            0x101E0000	/* System controller */
+
+/*
+ * System controller bit assignment
+ */
+#define VERSATILE_REFCLK	0
+#define VERSATILE_TIMCLK	1
+
+#define VERSATILE_TIMER1_EnSel	15
+#define VERSATILE_TIMER2_EnSel	17
+#define VERSATILE_TIMER3_EnSel	19
+#define VERSATILE_TIMER4_EnSel	21
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_MISC_INIT_R		1	/* call misc_init_r during start up */
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC_USE_32_BIT
+#define CONFIG_SMC91111_BASE    	0x10010000
+#undef CONFIG_SMC91111_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK	24000000
+#define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
+#define CONFIG_CONS_INDEX	0
+
+#define CONFIG_BAUDRATE         38400
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CFG_SERIAL0		0x101F1000
+#define CFG_SERIAL1		0x101F2000
+
+#define CONFIG_COMMANDS	(CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV)
+
+/*#define CONFIG_COMMANDS	(CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) */
+
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0"
+/*#define CONFIG_BOOTCOMMAND "bootp ; bootm" */
+
+/*
+ * Static configuration when assigning fixed address
+ */
+/*#define CONFIG_NETMASK	255.255.255.0	/--* talk on MY local net */
+/*#define CONFIG_IPADDR		xx.xx.xx.xx	/--* static IP I currently own */
+/*#define CONFIG_SERVERIP	xx.xx.xx.xx	/--* current IP of my dev pc */
+#define CONFIG_BOOTFILE	    "/tftpboot/uImage" /* file to load */
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP	/* undef to save memory     */
+#define CFG_PROMPT	"Versatile # "	/* Monitor Command Prompt   */
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size  */
+/* Print Buffer Size */
+#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS	16		/* max number of command args   */
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size    */
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#define CFG_LOAD_ADDR	0x7fc0	/* default load address */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS    1	/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1            0x00000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE       0x08000000	/* 128 MB */
+
+#define CFG_FLASH_BASE          0x34000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define VERSATILE_SYS_BASE                    0x10000000
+#define VERSATILE_SYS_FLASH_OFFSET            0x4C
+#define VERSATILE_FLASHCTRL		      (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
+#define VERSATILE_FLASHPROG_FLVPPEN	      (1 << 0)	/* Enable writing to flash */
+
+#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define PHYS_FLASH_SIZE         0x34000000	/* 64MB */
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(20*CFG_HZ)	/* Timeout for Flash Write */
+#define CFG_MAX_FLASH_SECT	(256)
+
+#define PHYS_FLASH_1		(CFG_FLASH_BASE)
+
+#define CFG_ENV_IS_IN_FLASH     1               /* env in flash instead of CFG_ENV_IS_NOWHERE */
+#define CFG_ENV_SECT_SIZE       0x00020000      /* 256 KB sectors (x2) */
+#define CFG_ENV_SIZE            0x10000         /* Total Size of Environment Sector */
+#define CFG_ENV_OFFSET          0x01f00000      /* environment starts here  */
+#define CFG_ENV_ADDR            (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+
+#endif							/* __CONFIG_H */
diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h
new file mode 100755
index 0000000..c5ee78f
--- /dev/null
+++ b/include/configs/voiceblue.h
@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
+ *
+ * Configuation settings for the TI OMAP VoiceBlue board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/omap1510.h>
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM925T	1		/* This is an arm925t CPU */
+#define CONFIG_OMAP	1		/* in a TI OMAP core */
+#define CONFIG_OMAP1510 1		/* which is in a 5910 */
+
+/* Input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ	150000000	/* 150MHz input clock */
+#define CONFIG_XTAL_FREQ	12000000
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R		/* There is nothing to really init */
+#define BOARD_LATE_INIT			/* but we flash the LEDs here */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	SZ_64M
+
+#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1 */
+#define PHYS_FLASH_2		0x0c000000
+
+#define CFG_LOAD_ADDR		PHYS_SDRAM_1 + 0x400000	/* default load address */
+
+/*
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI			/* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER		/* Use the common driver */
+#define CFG_MAX_FLASH_BANKS	1
+#ifdef VOICEBLUE_SMALL_FLASH
+#define CFG_FLASH_BANKS_LIST	{ PHYS_FLASH_2 }
+#else
+#define CFG_FLASH_BANKS_LIST	{ PHYS_FLASH_1 }
+#endif
+
+/* FIXME: Does not work on AMD flash */
+/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */	/* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_SECT	512	/* max # of sectors on one chip */
+
+#define CFG_MONITOR_BASE	PHYS_FLASH_1
+#define CFG_MONITOR_LEN		SZ_128K
+
+/*
+ * Environment settings
+ */
+#ifdef VOICEBLUE_SMALL_FLASH
+#define CFG_ENV_IS_NOWHERE
+#define CFG_ENV_SIZE		SZ_1K
+#else
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + CFG_MONITOR_LEN)
+#define CFG_ENV_SIZE		SZ_8K
+#define CFG_ENV_SECT_SIZE	SZ_64K
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CFG_JFFS_CUSTOM_PART	/* see board/voiceblue/jffs2parts.c */
+#endif
+
+/*
+ * Size of malloc() pool and stack
+ */
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#ifdef VOICEBLUE_SMALL_FLASH
+#define CFG_MALLOC_LEN		(SZ_64K - CFG_GBL_DATA_SIZE)
+#define CONFIG_STACKSIZE	SZ_8K
+#else
+#define CFG_MALLOC_LEN		SZ_4M
+#define CONFIG_STACKSIZE	SZ_1M
+#endif
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE	0x08000300
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	(-4)
+#define CFG_NS16550_CLK		(CONFIG_XTAL_FREQ)	/* can be 12M/32Khz or 48Mhz  */
+#define CFG_NS16550_COM1	OMAP1510_UART1_BASE	/* uart1 */
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#ifdef VOICEBLUE_SMALL_FLASH
+#define CONFIG_COMMANDS		(CFG_CMD_BDI    |	\
+				 CFG_CMD_LOADB  |	\
+				 CFG_CMD_IMI    |	\
+				 CFG_CMD_FLASH  |	\
+				 CFG_CMD_MEMORY |	\
+				 CFG_CMD_NET    |	\
+				 CFG_CMD_BOOTD  |	\
+				 CFG_CMD_DHCP   |	\
+				 CFG_CMD_PING   |	\
+				 CFG_CMD_RUN)
+#else
+#define CONFIG_COMMANDS		(CFG_CMD_BDI    |	\
+				 CFG_CMD_LOADB  |	\
+				 CFG_CMD_IMI    |	\
+				 CFG_CMD_FLASH  |	\
+				 CFG_CMD_MEMORY |	\
+				 CFG_CMD_NET    |	\
+				 CFG_CMD_ENV    |	\
+				 CFG_CMD_BOOTD  |	\
+				 CFG_CMD_DHCP   |	\
+				 CFG_CMD_PING   |	\
+				 CFG_CMD_RUN    |	\
+				 CFG_CMD_JFFS2)
+#endif
+
+#define CONFIG_BOOTP_MASK	CONFIG_BOOTP_DEFAULT
+#define CONFIG_LOOPW
+
+#ifdef VOICEBLUE_SMALL_FLASH
+#define CONFIG_BOOTDELAY	0
+#undef  CONFIG_BOOTARGS		/* the preboot command will set bootargs*/
+#define CFG_AUTOLOAD		"n"	/* no autoload */
+#define CONFIG_PREBOOT		"run setup"
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"setup=setenv bootargs console=ttyS0,${baudrate} "	\
+		"root=/dev/nfs ip=dhcp\0"			\
+	"update=erase c000000 c03ffff; "			\
+		"cp.b 10400000 c000000 ${filesize}\0"
+#else
+#define CONFIG_BOOTDELAY	3
+#undef  CONFIG_BOOTARGS		/* boot command will set bootargs */
+#define CFG_AUTOLOAD		"n"	/* no autoload */
+#define CONFIG_BOOTCOMMAND	"run nboot"
+#define CONFIG_PREBOOT		"run setup"
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"ospart=0\0"						\
+	"swapos=no\0"						\
+	"setpart="						\
+	"if test $swapos = yes; then "				\
+		"if test $ospart -eq 0; then chpart 4; else chpart 3; fi; "\
+		"setenv swapos no; saveenv; "			\
+	"else "							\
+		"if test $ospart -eq 0; then chpart 3; else chpart 4; fi; "\
+	"fi\0"							\
+	"setup=setenv bootargs console=ttyS0,$baudrate "	\
+		"mtdparts=$mtdparts\0"				\
+	"nfsargs=run setpart; setenv bootargs $bootargs "	\
+		"root=/dev/nfs ip=dhcp\0"			\
+	"flashargs=run setpart; setenv bootargs $bootargs "	\
+		"root=/dev/mtdblock$partition ro "		\
+		"rootfstype=jffs2\0"				\
+	"nboot=run nfsargs; bootp; tftp; bootm\0"		\
+	"fboot=run flashargs; fsload /boot/uImage; bootm\0"
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#ifndef VOICEBLUE_SMALL_FLASH
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+#define CONFIG_AUTO_COMPLETE
+#endif
+#define CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT		"# "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	PHYS_SDRAM_1
+#define CFG_MEMTEST_END		PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
+ * This time is further subdivided by a local divisor.
+ */
+#define CFG_TIMERBASE		OMAP1510_TIMER1_BASE
+#define CFG_PVT			7		/* 2^(pvt+1), divide by 256 */
+#define CFG_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+#define OMAP5910_DPLL_DIV	1
+#define OMAP5910_DPLL_MUL	((CONFIG_SYS_CLK_FREQ * \
+				 (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
+
+#define OMAP5910_ARM_PER_DIV	2	/* CKL/4 */
+#define OMAP5910_LCD_DIV	2	/* CKL/4 */
+#define OMAP5910_ARM_DIV	0	/* CKL/1 */
+#define OMAP5910_DSP_DIV	0	/* CKL/1 */
+#define OMAP5910_TC_DIV		1	/* CKL/2 */
+#define OMAP5910_DSP_MMU_DIV	1	/* CKL/2 */
+#define OMAP5910_ARM_TIM_SEL	1	/* CKL used for MPU timers */
+
+#define OMAP5910_ARM_EN_CLK	0x03d6	/* 0000 0011 1101 0110b  Clock Enable */
+#define OMAP5910_ARM_CKCTL	((OMAP5910_ARM_PER_DIV)  |	\
+				 (OMAP5910_LCD_DIV << 2) |	\
+				 (OMAP5910_ARM_DIV << 4) |	\
+				 (OMAP5910_DSP_DIV << 6) |	\
+				 (OMAP5910_TC_DIV << 8) |	\
+				 (OMAP5910_DSP_MMU_DIV << 10) |	\
+				 (OMAP5910_ARM_TIM_SEL << 12))
+
+#define VOICEBLUE_LED_REG	0x04030000
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00040000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=voiceblue-0"
+#define MTDPARTS_DEFAULT	"mtdparts=voiceblue-0:128k(uboot),64k(env),64k(renv),-(jffs2)"
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/walnut.h b/include/configs/walnut.h
new file mode 100755
index 0000000..1171ee5
--- /dev/null
+++ b/include/configs/walnut.h
@@ -0,0 +1,337 @@
+/*
+ * (C) Copyright 2000-2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_WALNUT		1	/* ...on a WALNUT board		*/
+					/* ...and on a SYCAMORE board	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=walnut\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/walnut/uImage\0"				\
+	"kernel_addr=fff80000\0"					\
+	"ramdisk_addr=fff80000\0"					\
+	"load=tftp 100000 /tftpboot/walnut/u-boot.bin\0"		\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"				\
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
+
+#define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Walnut	*/
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO | \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+/*
+ * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#undef	CFG_EXT_SERIAL_CLOCK	       /* external serial clock */
+#undef	CFG_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
+#define CFG_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
+
+#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support	*/
+#define CONFIG_LOOPW		1	/* enable loopw command		*/
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CFG_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+#define CONFIG_NET_MULTI		/* needed for NetConsole	*/
+
+/*-----------------------------------------------------------------------
+ * I2C stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0xFFF80000
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
+
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ *	 supported for backward compatibility.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/
+#else
+#define CFG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	CFG_FLASH_BASE	/* FLASH bank #0		*/
+#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1		*/
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CFG_FLASH_ADDR0		0x5555
+#define CFG_FLASH_ADDR1		0x2aaa
+#define CFG_FLASH_WORD_SIZE	unsigned char
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
+#define CFG_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
+
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
+#define CFG_ENV_ADDR		\
+	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)	/* Env	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
+					/* have only 8kB, 16kB is save here	*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x9B015480
+#define CFG_EBC_PB0CR		0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit	*/
+
+#define CFG_EBC_PB1AP		0x02815480
+#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+#define CFG_EBC_PB2AP		0x04815A80
+#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
+
+#define CFG_EBC_PB3AP		0x01815280
+#define CFG_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+#define CFG_EBC_PB7AP		0x01815280
+#define CFG_EBC_PB7CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+
+/*-----------------------------------------------------------------------
+ * External peripheral base address
+ *-----------------------------------------------------------------------
+ */
+#define CFG_KEY_REG_BASE_ADDR	0xF0100000
+#define CFG_IR_REG_BASE_ADDR	0xF0200000
+#define CFG_FPGA_REG_BASE_ADDR	0xF0300000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CFG_INIT_DCACHE_CS	4	/* use cs # 4 for data cache memory    */
+
+#define CFG_INIT_RAM_ADDR	0x40000000  /* inside of SDRAM			   */
+#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
+#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS	0x50
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h
new file mode 100755
index 0000000..47251bb
--- /dev/null
+++ b/include/configs/wepep250.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2003 ETC s.r.o.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Written by Peter Figuli <peposh@etc.sk>, 2003.
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PXA250          1        /* this is an PXA250 CPU     */
+#define CONFIG_WEPEP250        1        /* config for wepep250 board */
+#undef  CONFIG_USE_IRQ                  /* don't need use IRQ/FIQ    */
+
+
+/*
+ * Select serial console configuration
+ */
+#define CONFIG_BTUART          1       /* BTUART is default on WEP dev board */
+#define CONFIG_BAUDRATE   115200
+
+
+/*
+ * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
+ * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
+ * functionality or size of u-boot code.
+ */
+#define CONFIG_COMMANDS         (CONFIG_CMD_DFL		\
+				& ~CFG_CMD_NET 		\
+				& ~CFG_CMD_LOADS	\
+				& ~CFG_CMD_CONSOLE	\
+				& ~CFG_CMD_AUTOSCRIPT	\
+/*				| CFG_CMD_JFFS2 */	\
+				)
+#include <cmd_confdefs.h>
+
+/*
+ * Boot options. Setting delay to -1 stops autostart count down.
+ * NOTE: Sending parameters to kernel depends on kernel version and
+ * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
+ * parameters at all! Do not get confused by them so.
+ */
+#define CONFIG_BOOTDELAY   -1
+#define CONFIG_BOOTARGS    "root=/dev/mtdblock2 mem=32m console=ttyS01,115200n8"
+#define CONFIG_BOOTCOMMAND "bootm 40000"
+
+
+/*
+ * General options for u-boot. Modify to save memory foot print
+ */
+#define CFG_LONGHELP                                  /* undef saves memory  */
+#define CFG_PROMPT              "WEP> "               /* prompt string       */
+#define CFG_CBSIZE              256                   /* console I/O buffer  */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size   */
+#define CFG_MAXARGS             16                    /* max command args    */
+#define CFG_BARGSIZE            CFG_CBSIZE            /* boot args buf size  */
+
+#define CFG_MEMTEST_START       0xa0400000            /* memtest test area   */
+#define CFG_MEMTEST_END         0xa0800000
+
+#undef  CFG_CLKS_IN_HZ                       /* use HZ for freq. display     */
+
+#define CFG_HZ                  3686400      /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED            0x141        /* core clock - register value  */
+
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Definitions related to passing arguments to kernel.
+ */
+#define CONFIG_CMDLINE_TAG           1   /* send commandline to Kernel       */
+#define CONFIG_SETUP_MEMORY_TAGS     1   /* send memory definition to kernel */
+#undef  CONFIG_INITRD_TAG                /* do not send initrd params        */
+#undef  CONFIG_VFD                       /* do not send framebuffer setup    */
+
+
+/*
+ * Malloc pool need to host env + 128 Kb reserve for other allocations.
+ */
+#define CFG_MALLOC_LEN	  (CFG_ENV_SIZE + (128<<10) )
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+#define CONFIG_STACKSIZE        (120<<10)      /* stack size */
+
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ    (4<<10)        /* IRQ stack  */
+#define CONFIG_STACKSIZE_FIQ    (4<<10)        /* FIQ stack  */
+#endif
+
+/*
+ * SDRAM Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS    1                /* we have 1 bank of SDRAM */
+#define WEP_SDRAM_1            0xa0000000        /* SDRAM bank #1           */
+#define WEP_SDRAM_1_SIZE       0x02000000        /* 32 MB ( 2 chip )        */
+#define WEP_SDRAM_2            0xa2000000        /* SDRAM bank #2           */
+#define WEP_SDRAM_2_SIZE       0x00000000        /* 0 MB                    */
+#define WEP_SDRAM_3            0xa8000000        /* SDRAM bank #3           */
+#define WEP_SDRAM_3_SIZE       0x00000000        /* 0 MB                    */
+#define WEP_SDRAM_4            0xac000000        /* SDRAM bank #4           */
+#define WEP_SDRAM_4_SIZE       0x00000000        /* 0 MB                    */
+
+#define CFG_DRAM_BASE           0xa0000000
+#define CFG_DRAM_SIZE           0x02000000
+
+/* Uncomment used SDRAM chip */
+#define WEP_SDRAM_K4S281633
+/*#define WEP_SDRAM_K4S561633*/
+
+
+/*
+ * Configuration for FLASH memory
+ */
+#define CFG_MAX_FLASH_BANKS    	1  	/* FLASH banks count (not chip count)*/
+#define CFG_MAX_FLASH_SECT     	128	/* number of sector in FLASH bank    */
+#define WEP_FLASH_BUS_WIDTH 	4	/* we use 32 bit FLASH memory...     */
+#define WEP_FLASH_INTERLEAVE	2	/* ... made of 2 chips */
+#define WEP_FLASH_BANK_SIZE  0x2000000  /* size of one flash bank*/
+#define WEP_FLASH_SECT_SIZE  0x0040000  /* size of erase sector */
+#define WEP_FLASH_BASE       0x0000000  /* location of flash memory */
+#define WEP_FLASH_UNLOCK        1       /* perform hw unlock first */
+
+
+/* This should be defined if CFI FLASH device is present. Actually benefit
+   is not so clear to me. In other words we can provide more informations
+   to user, but this expects more complex flash handling we do not provide
+   now.*/
+#undef  CFG_FLASH_CFI
+
+#define CFG_FLASH_ERASE_TOUT    (2*CFG_HZ)    /* timeout for Erase operation */
+#define CFG_FLASH_WRITE_TOUT    (2*CFG_HZ)    /* timeout for Write operation */
+
+#define CFG_FLASH_BASE          WEP_FLASH_BASE
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * Right now there is no gain for user, but later on booting kernel might be
+ * possible. Consider using XIP kernel running from flash to save RAM
+ * footprint.
+ * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
+ */
+#define CFG_JFFS2_FIRST_BANK		0
+#define CFG_JFFS2_FIRST_SECTOR		5
+#define CFG_JFFS2_NUM_BANKS		1
+
+/*
+ * Environment setup. Definitions of monitor location and size with
+ * definition of environment setup ends up in 2 possibilities.
+ * 1. Embeded environment - in u-boot code is space for environment
+ * 2. Environment is read from predefined sector of flash
+ * Right now we support 2. possiblity, but expecting no env placed
+ * on mentioned address right now. This also needs to provide whole
+ * sector for it - for us 256Kb is really waste of memory. U-boot uses
+ * default env. and until kernel parameters could be sent to kernel
+ * env. has no sense to us.
+ */
+
+#define CFG_MONITOR_BASE	PHYS_FLASH_1
+#define CFG_MONITOR_LEN		0x20000		/* 128kb ( 1 flash sector )  */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		0x20000	        /* absolute address for now  */
+#define CFG_ENV_SIZE		0x2000
+
+#undef  CONFIG_ENV_OVERWRITE                    /* env is not writable now   */
+
+/*
+ * Well this has to be defined, but on the other hand it is used differently
+ * one may expect. For instance loadb command do not cares :-)
+ * So advice is - do not relay on this...
+ */
+#define CFG_LOAD_ADDR        0x40000
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/wmt.h b/include/configs/wmt.h
new file mode 100755
index 0000000..6d56fd4
--- /dev/null
+++ b/include/configs/wmt.h
@@ -0,0 +1,354 @@
+/*
+ * Configuation settings for the WMT evaluation board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T    1	/* This is an ARM920T CPU core  */
+#define CONFIG_WMT        1	/* in a WMT SoC	*/
+
+/* input clock of PLL */
+/* the WMT EVB uses 250MHz clock */
+#define CONFIG_SYS_CLK_FREQ	250MHz
+
+#undef CONFIG_USE_IRQ	/* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1	/* send initrd params */
+
+/*
+ * USB device configuration
+ */
+#define CONFIG_USB_DEVICE	1
+//#define CONFIG_USB_TTY		1
+#define CONFIG_USBD_VENDORID		0x040d //WMT vendor , tmp
+#define CONFIG_USBD_PRODUCTID		0x885e //0x8950 //0x8435//0x8453
+#define CONFIG_USBD_MANUFACTURER	    "WonderMedia Technologies,Inc."
+#define CONFIG_USBD_PRODUCT_NAME 	"VT8950 USB Fastboot Device"
+#define CONFIG_WMT_UDC 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN	(CFG_ENV_SIZE + 2048*1024)//128*1024
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/* WMT UART */
+#define CFG_WMT_SERIAL
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1	1	/* we use SERIAL 1 on WMT EVB */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE	115200
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_AUTO_COMPLETE 1	/* add autocompletion support */
+#define CONFIG_HUSH_PARSER   1	/* use "hush" command parser 	*/
+/*
+*CharlesTu,2011.3.24,enable CMD_USB and usb storage ehci and uhci
+*/
+
+/* #define CONFIG_COMMANDS (CFG_CMD_NAND | CFG_CMD_DHCP | CFG_CMD_PING | CFG_CMD_MII | CONFIG_CMD_DFL) */
+#define CONFIG_COMMANDS		(CFG_CMD_MMC | \
+				CFG_CMD_FAT | \
+				CFG_CMD_IDE | \
+				CFG_CMD_DHCP | \
+				CFG_CMD_PING | \
+				CFG_CMD_MII | \
+				CONFIG_CMD_DFL | \
+				CFG_CMD_NAND | \
+				CFG_CMD_ENV | \
+				CFG_CMD_I2C | \
+				CFG_CMD_USB)
+
+//#define ET_DEBUG
+#define  CONFIG_USB_STORAGE 1
+#define CONFIG_DOS_PARTITION  1
+/*default ehci driver */
+#define CONFIG_USB_EHCI		1
+#define CONFIG_USB_UHCI		1
+#define CONFIG_CMD_FASTBOOT    1
+
+#define CONFIG_MMC 1
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_ZERO_BOOTDELAY_CHECK     /* check keypress when bootdelay = 0 */
+#define CONFIG_BOOTCOMMAND	"fastboot"
+/* {JHT 2007/07/26 Change the root=/dev/ram0 into root=dev/ram0 */
+/* -#define CONFIG_BOOTARGS "mem=128M root=/dev/ram0 rw initrd=0x01000000,32768K console=ttyS0,115200n8" */
+#define CONFIG_BOOTARGS		"mem=127M root=dev/ram0 rw initrd=0x01000000,32768K console=ttyS0,115200n8"
+/* }JHT-2007/07/26 */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_USB_ETHER_ASIX   1
+#define CONFIG_USB_ETHER_RTL8152   1
+#define CONFIG_CMD_NET 		 1
+#define CONFIG_CMD_PING 		 1
+#define CONFIG_CMD_DHCP            1
+
+/* disable VT6103X ethernet */
+#undef CONFIG_DRIVER_ETHER
+#ifdef CONFIG_DRIVER_ETHER
+#undef CONFIG_NET_MULTI 				/* Using WMT MAC */
+#undef CONFIG_USB_HOST_ETHER
+#else
+#define CONFIG_USB_HOST_ETHER  1 	/* Using usb ethernet adapter */
+#define CONFIG_NET_MULTI 		 1
+#endif
+
+#define CONFIG_ETHADDR    00:40:63:00:00:00
+#define CONFIG_NETMASK    255.255.255.0	/* talk on MY local net */
+#define CONFIG_IPADDR     192.168.1.2	  /* static IP I currently own */
+#define CONFIG_SERVERIP   192.168.1.1	  /* current IP of my dev pc */
+#define CONFIG_BOOTFILE   "uzImage.bin"	/* Name of the image to load with TFTP */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE  115200  /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	1	      /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                     /* undef to save memory     */
+#define CFG_PROMPT    "WMT # "           /* Monitor Command Prompt   */
+#define CFG_CBSIZE    1024               /* Console I/O Buffer Size  */
+/* Print Buffer Size */
+#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS	32                   /* max number of command args */
+#define CFG_BARGSIZE	CFG_CBSIZE         /* Boot Argument Buffer Size  */
+
+#define CFG_MEMTEST_START	0x00000000     /* memtest works on	*/
+#define CFG_MEMTEST_END		0x03F00000     /* 63 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ  /* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0x02000000	/* default load address	*/
+#define CONFIG_LOADADDR		CFG_LOAD_ADDR
+
+#define	CONFIG_VERSION_VARIABLE	1		/* include version env variable */
+
+#define CONFIG_ZDE_KERNEL_DEBUG			/* ZDE kernel debugging support */
+
+/* Give WMT TIMERBAES, Give Timer clock in Hz
+ * This time eat 12MHz clk and increase its count at 3MHz.
+ */
+#define	CFG_HZ			3000000		/* OS timer increase its count at 3MHz */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1      0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define PHYS_FLASH_1      0xFF000000 /* Flash Bank #1 */ /* nick span */
+#define PHYS_FLASH_2      0xFF800000 /* Flash Bank #2 */ /* nick span */
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+#if (NOR_BOOT_ERASE_SIZE_KB == 128)
+#define CFG_NOR_FLASH_BASE_3    0xFE000000 /* nor boot nor flash bank 3 addr*/
+#define CFG_NOR_FLASH_BASE_2    0xFC000000 /* nor boot nor flash bank 2 addr*/
+#define CFG_NOR_FLASH_BASE_1    0xFA000000 /* nor boot nor flash bank 1 addr*/
+#define CFG_NOR_FLASH_BASE_0    0xF8000000 /* nor boot nor flash bank 0 addr*/
+#define SPI_BOOT_FLASH_BASE_3   0xEE000000 /* spi boot nor flash bank 3 addr*/
+#define SPI_BOOT_FLASH_BASE_2   0xEC000000 /* spi boot nor flash bank 2 addr*/
+#define SPI_BOOT_FLASH_BASE_1   0xEA000000 /* spi boot nor flash bank 1 addr*/
+#define SPI_BOOT_FLASH_BASE_0   0xE8000000 /* spi boot nor flash bank 0 addr*/
+#else
+#define CFG_NOR_FLASH_BASE_3    0xFF800000 /* nor boot nor flash bank 3 addr*/
+#define CFG_NOR_FLASH_BASE_2    0xFF000000 /* nor boot nor flash bank 2 addr*/
+#define CFG_NOR_FLASH_BASE_1    0xFE800000 /* nor boot nor flash bank 1 addr*/
+#define CFG_NOR_FLASH_BASE_0    0xFE000000 /* nor boot nor flash bank 0 addr*/
+#define SPI_BOOT_FLASH_BASE_3   0xEF800000 /* spi boot nor flash bank 3 addr*/
+#define SPI_BOOT_FLASH_BASE_2   0xEF000000 /* spi boot nor flash bank 2 addr*/
+#define SPI_BOOT_FLASH_BASE_1   0xEE800000 /* spi boot nor flash bank 1 addr*/
+#define SPI_BOOT_FLASH_BASE_0   0xEE000000 /* spi boot nor flash bank 0 addr*/
+#endif
+
+#define NOR_FLASH_128K       0x0 /* nor flash offset address range 128K*/
+#define NOR_FLASH_256K       0x1 /* nor flash offset address range 256K*/
+#define NOR_FLASH_512K       0x2 /* nor flash offset address range 512K*/
+#define NOR_FLASH_1M         0x3 /* nor flash offset address range 1M*/
+#define NOR_FLASH_2M         0x4 /* nor flash offset address range 2M*/
+#define NOR_FLASH_4M         0x5 /* nor flash offset address range 4M*/
+#define NOR_FLASH_8M         0x6 /* nor flash offset address range 8M*/
+#define NOR_FLASH_16M        0x7 /* nor flash offset address range 16M*/
+#define NOR_FLASH_32M        0x8 /* nor flash offset address range 32M*/
+#define NOR_FLASH_64M        0x9 /* nor flash offset address range 64M*/
+#define NOR_FLASH_128M       0xa /* nor flash offset address range 128M*/
+#define NOR_FLASH_256M       0xb /* nor flash offset address range 256M*/
+#define NOR_FLASH_512M       0xc /* nor flash offset address range 512M*/
+#define NOR_FLASH_1G         0xd /* nor flash offset address range 1G*/
+#define NOR_FLASH_2G         0xe /* nor flash offset address range 2G*/
+#define NOR_FLASH_4G         0xf /* nor flash offset address range 4G*/
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	     1	/* max number of memory banks */
+#define CFG_MAX_SPI_FLASH_BANKS	 1	/* max number of spi flash banks*/
+#define CFG_MAX_NOR_FLASH_BANKS	 4	/* max number of nor flash banks */
+#define CFG_MAX_NAND_FLASH_BANKS 4	/* max number of nand flash banks */
+#if (CFG_MAX_FLASH_BANKS < CFG_MAX_SPI_FLASH_BANKS)
+	#undef CFG_MAX_FLASH_BANKS
+	#define CFG_MAX_FLASH_BANKS CFG_MAX_SPI_FLASH_BANKS
+#endif
+#if (CFG_MAX_FLASH_BANKS < CFG_MAX_NOR_FLASH_BANKS)
+	#undef CFG_MAX_FLASH_BANKS
+	#define CFG_MAX_FLASH_BANKS CFG_MAX_NOR_FLASH_BANKS
+#endif
+#if (CFG_MAX_FLASH_BANKS < CFG_MAX_NAND_FLASH_BANKS)
+	#undef CFG_MAX_FLASH_BANKS
+	#define CFG_MAX_FLASH_BANKS CFG_MAX_NAND_FLASH_BANKS
+#endif
+
+#define CFG_FLASH_PROTECTION 1
+#define PHYS_FLASH_SIZE		0x01000000	/* 16MB = 8MB X 2 */
+#define CFG_MAX_FLASH_SECT	(512)		  /* max number of sectors on one chip */
+/* addr of environment */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(3*CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(3*CFG_HZ)	/* Timeout for Flash Write */
+
+/* #define ENV_IS_EMBEDDED 1 */
+//#define CFG_NAND_BOOT
+#define CFG_MAX_NAND_DEVICE 2	/* Max number of NAND devices */
+#define NAND_ChipID_UNKNOWN	0x00
+#define SECTORSIZE          512
+#define NAND_MAX_FLOORS 1
+#define NAND_MAX_CHIPS 2
+/* ----------boot on nand flash---start---*/
+#ifdef CFG_NAND_BOOT
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_BLOCK_OFFSET    0x1  /* environment starts on block ? (1~9) */
+#define CFG_ENV_BLOCK_LENGTH    0x9  /* environment partition length 9 blocks */
+/* ----------boot on nand flash---end-----*/
+#else
+#define CFG_ENV_IS_IN_FLASH	1
+#if (NOR_BOOT_ERASE_SIZE_KB ==128)
+	#define CFG_ENV_SIZE      0x20000     /* Total Size of Environment Sector */
+	#define CFG_ENV_SECT_SIZE	0x20000     /* 64KB */
+	#define CFG_ENV_OFFSET    0x00FA0000  /* environment starts here  */
+#else
+	#define CFG_ENV_SIZE      0x10000     /* Total Size of Environment Sector */
+	#define CFG_ENV_SECT_SIZE	0x10000     /* 64KB */
+	#define CFG_ENV_OFFSET    0x00FD0000  /* environment starts here  */
+#endif
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+/* Address and size of Redundant Environment Sector */
+
+/**
+    otp partition [0xfffe0000, 0xffff0000) if defined CFG_ENV_OTP
+
+       512k Flash
+    +------------------------+ 0xffff,ffff
+    |                        | 
+    |  64k  W-Load           |
+    |                        |
+    +------------------------+ 0xffff,0000
+    |                        |
+    |  64k  OTP env          |
+    |                        |
+    +------------------------+ 0xfffe,0000
+    |                        |
+    |  64k  uboot env        |
+    |                        |
+    +------------------------+ 0xfffd,0000
+    |                        |
+    |                        |
+    |  320k uboot.bin        |
+    |                        |
+    |                        |
+    |                        |
+    ~~~~~~~~~~~~~~~~~~~~~~~~~~ 0xfff8,0000
+*/
+
+#if 0
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif
+
+#endif
+
+#define CONFIG_CRC32_VERIFY	1
+
+/*
+nand flash uboot info setting by Dannier Chen -start-
+*/
+#define REG_NFCR(nand_base_reg, NFCR0)         (REG32_PTR(__XDP_BASE_ADDR+NFCR0))
+/*
+nand flash uboot info setting by Dannier Chen -end-
+*/
+
+#define CFG_IDE_MAXBUS		1/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1/* max. 1 drive per IDE bus	*/
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	0
+#define CFG_ATA_BASE_ADDR	0xD8008170
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	0
+#define CFG_ATA_IDE0_OFFSET 0
+
+#define CFG_HUSH_PARSER	1 /* use "hush" command parser */
+#define CFG_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CFG_I2C_SLAVE		0x7F
+
+#define CONFIG_SPI
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"wmt.fb.param=1:0:0:0\0"		\
+
+#define CONFIG_BATT_UPI		1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
new file mode 100755
index 0000000..1039762
--- /dev/null
+++ b/include/configs/xaeniax.h
@@ -0,0 +1,557 @@
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * (C) Copyright 2004
+ * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the xaeniax board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA250		1	/* This is an PXA255 CPU    */
+#define CONFIG_XAENIAX		1	/* on a xaeniax board	    */
+
+
+#define BOARD_LATE_INIT		1
+
+
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_BTUART	       1       /* we use BTUART on XAENIAX */
+
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
+
+#define CONFIG_COMMANDS	       ((CONFIG_CMD_DFL & ~CFG_CMD_DTT) | \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_SNTP	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.68.201
+#define CONFIG_SERVERIP		192.168.68.62
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTCOMMAND	"bootm 0x00100000"
+#define CONFIG_BOOTARGS		"console=ttyS1,115200"
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 	1
+#define CONFIG_INITRD_TAG		1
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200			/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	1			/* which serial port to use */
+#endif
+
+/*
+ * Size of malloc() pool; this lives below the uppermost 128 KiB which are
+ * used for the RAM copy of the uboot code
+ */
+#define CFG_MALLOC_LEN	    (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory	*/
+#define CFG_HUSH_PARSER		1
+
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT		"u-boot$ "	/* Monitor Command Prompt */
+#else
+#define CFG_PROMPT		"u-boot=> "	/* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CFG_DEVICE_NULLDEV	1
+
+#define CFG_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+
+#undef	CFG_CLKS_IN_HZ				/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0xa1000000	/* default load address */
+
+#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks (partition) of DRAM */
+#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
+#define PHYS_FLASH_SIZE		0x02000000 /* 32 MB */
+#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
+
+#define CFG_DRAM_BASE		0xa0000000
+#define CFG_DRAM_SIZE		0x04000000
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1    /* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(25*CFG_HZ) /* Timeout for Flash Write */
+
+/* FIXME */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x40000			/* Total Size of Environment Sector	*/
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*
+ * SMSC91C111 Network Card
+ */
+#define CONFIG_DRIVER_SMC91111		1
+#define CONFIG_SMC91111_BASE		0x10000300  /* chip select 3         */
+#define CONFIG_SMC_USE_32_BIT		1          /* 32 bit bus  */
+#undef  CONFIG_SMC_91111_EXT_PHY		   /* we use internal phy   */
+#undef  CONFIG_SHOW_ACTIVITY
+#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */
+
+/*
+ * GPIO settings
+ */
+
+/*
+ * GP05 == nUSBReset  is 1
+ * GP10 == CFReset   is 1
+ * GP13 == nCFDataEnable is 1
+ * GP14 == nCFAddrEnable is 1
+ * GP15 == nCS1      is 1
+ * GP21 == ComBrdReset is 1
+ * GP24 == SFRM      is 1
+ * GP25 == TXD       is 1
+ * GP31 == SYNC      is 1
+ * GP33 == nCS5      is 1
+ * GP39 == FFTXD     is 1
+ * GP41 == RTS       is 1
+ * GP43 == BTTXD     is 1
+ * GP45 == BTRTS     is 1
+ * GP47 == TXD       is 1
+ * GP48 == nPOE      is 1
+ * GP49 == nPWE      is 1
+ * GP50 == nPIOR     is 1
+ * GP51 == nPIOW     is 1
+ * GP52 == nPCE[1]   is 1
+ * GP53 == nPCE[2]   is 1
+ * GP54 == nPSKTSEL  is 1
+ * GP55 == nPREG     is 1
+ * GP78 == nCS2      is 1
+ * GP79 == nCS3      is 1
+ * GP80 == nCS4      is 1
+ * GP82 == NSSPSFRM  is 1
+ * GP83 == NSSPTXD   is 1
+ */
+#define CFG_GPSR0_VAL		0x8320E420
+#define CFG_GPSR1_VAL		0x00FFAA82
+#define CFG_GPSR2_VAL		0x000DC000
+
+/*
+ * GP03 == LANReset  is 0
+ * GP06 == USBWakeUp  is 0
+ * GP11 == USBControl is 0
+ * GP12 == Buzzer     is 0
+ * GP16 == PWM0       is 0
+ * GP17 == PWM1       is 0
+ * GP23 == SCLK      is 0
+ * GP30 == SDATA_OUT is 0
+ * GP81 == NSSPCLK   is 0
+ */
+#define CFG_GPCR0_VAL		0x40C31848
+#define CFG_GPCR1_VAL		0x00000000
+#define CFG_GPCR2_VAL		0x00020000
+
+/*
+ * GP00 == CPUWakeUpUSB is input
+ * GP01 == GP reset is input
+ * GP02 == LANInterrupt is input
+ * GP03 == LANReset     is output
+ * GP04 == USBInterrupt is input
+ * GP05 == nUSBReset    is output
+ * GP06 == USBWakeUp    is output
+ * GP07 == CFReady/nBusy is input
+ * GP08 == nCFCardDetect1 is input
+ * GP09 == nCFCardDetect2 is input
+ * GP10 == nCFReset   is output
+ * GP11 == USBControl is output
+ * GP12 == Buzzer     is output
+ * GP13 == CFDataEnable is output
+ * GP14 == CFAddressEnable is output
+ * GP15 == nCS1      is output
+ * GP16 == PWM0      is output
+ * GP17 == PWM1      is output
+ * GP18 == RDY       is input
+ * GP19 == ReaderReady is input
+ * GP20 == ReaderReset is input
+ * GP21 == ComBrdReset is output
+ * GP23 == SCLK      is output
+ * GP24 == SFRM      is output
+ * GP25 == TXD       is output
+ * GP26 == RXD       is input
+ * GP27 == EXTCLK    is input
+ * GP28 == BITCLK    is output
+ * GP29 == SDATA_IN0 is input
+ * GP30 == SDATA_OUT is output
+ * GP31 == SYNC      is output
+ * GP32 == SYSSCLK   is output
+ * GP33 == nCS5      is output
+ * GP34 == FFRXD     is input
+ * GP35 == CTS       is input
+ * GP36 == DCD       is input
+ * GP37 == DSR       is input
+ * GP38 == RI        is input
+ * GP39 == FFTXD     is output
+ * GP40 == DTR       is output
+ * GP41 == RTS       is output
+ * GP42 == BTRXD     is input
+ * GP43 == BTTXD     is output
+ * GP44 == BTCTS     is input
+ * GP45 == BTRTS     is output
+ * GP46 == RXD       is input
+ * GP47 == TXD       is output
+ * GP48 == nPOE      is output
+ * GP49 == nPWE      is output
+ * GP50 == nPIOR     is output
+ * GP51 == nPIOW     is output
+ * GP52 == nPCE[1]   is output
+ * GP53 == nPCE[2]   is output
+ * GP54 == nPSKTSEL  is output
+ * GP55 == nPREG     is output
+ * GP56 == nPWAIT    is input
+ * GP57 == nPIOS16   is input
+ * GP58 == LDD[0]    is output
+ * GP59 == LDD[1]    is output
+ * GP60 == LDD[2]    is output
+ * GP61 == LDD[3]    is output
+ * GP62 == LDD[4]    is output
+ * GP63 == LDD[5]    is output
+ * GP64 == LDD[6]    is output
+ * GP65 == LDD[7]    is output
+ * GP66 == LDD[8]    is output
+ * GP67 == LDD[9]    is output
+ * GP68 == LDD[10]   is output
+ * GP69 == LDD[11]   is output
+ * GP70 == LDD[12]   is output
+ * GP71 == LDD[13]   is output
+ * GP72 == LDD[14]   is output
+ * GP73 == LDD[15]   is output
+ * GP74 == LCD_FCLK  is output
+ * GP75 == LCD_LCLK  is output
+ * GP76 == LCD_PCLK  is output
+ * GP77 == LCD_ACBIAS is output
+ * GP78 == nCS2      is output
+ * GP79 == nCS3      is output
+ * GP80 == nCS4      is output
+ * GP81 == NSSPCLK   is output
+ * GP82 == NSSPSFRM  is output
+ * GP83 == NSSPTXD   is output
+ * GP84 == NSSPRXD   is input
+ */
+#define CFG_GPDR0_VAL		0xD3E3FC68
+#define CFG_GPDR1_VAL		0xFCFFAB83
+#define CFG_GPDR2_VAL		0x000FFFFF
+
+/*
+ * GP01 == GP reset is AF01
+ * GP15 == nCS1     is AF10
+ * GP16 == PWM0     is AF10
+ * GP17 == PWM1     is AF10
+ * GP18 == RDY      is AF01
+ * GP23 == SCLK     is AF10
+ * GP24 == SFRM     is AF10
+ * GP25 == TXD      is AF10
+ * GP26 == RXD      is AF01
+ * GP27 == EXTCLK   is AF01
+ * GP28 == BITCLK   is AF01
+ * GP29 == SDATA_IN0 is AF10
+ * GP30 == SDATA_OUT is AF01
+ * GP31 == SYNC     is AF01
+ * GP32 == SYSCLK   is AF01
+ * GP33 == nCS5  is AF10
+ * GP34 == FFRXD is AF01
+ * GP35 == CTS   is AF01
+ * GP36 == DCD   is AF01
+ * GP37 == DSR   is AF01
+ * GP38 == RI    is AF01
+ * GP39 == FFTXD is AF10
+ * GP40 == DTR   is AF10
+ * GP41 == RTS   is AF10
+ * GP42 == BTRXD is AF01
+ * GP43 == BTTXD is AF10
+ * GP44 == BTCTS is AF01
+ * GP45 == BTRTS is AF10
+ * GP46 == RXD   is AF10
+ * GP47 == TXD   is AF01
+ * GP48 == nPOE  is AF10
+ * GP49 == nPWE  is AF10
+ * GP50 == nPIOR is AF10
+ * GP51 == nPIOW is AF10
+ * GP52 == nPCE[1] is AF10
+ * GP53 == nPCE[2] is AF10
+ * GP54 == nPSKTSEL is AF10
+ * GP55 == nPREG   is AF10
+ * GP56 == nPWAIT  is AF01
+ * GP57 == nPIOS16 is AF01
+ * GP58 == LDD[0]  is AF10
+ * GP59 == LDD[1]  is AF10
+ * GP60 == LDD[2]  is AF10
+ * GP61 == LDD[3]  is AF10
+ * GP62 == LDD[4]  is AF10
+ * GP63 == LDD[5]  is AF10
+ * GP64 == LDD[6]  is AF10
+ * GP65 == LDD[7]  is AF10
+ * GP66 == LDD[8]  is AF10
+ * GP67 == LDD[9]  is AF10
+ * GP68 == LDD[10] is AF10
+ * GP69 == LDD[11] is AF10
+ * GP70 == LDD[12] is AF10
+ * GP71 == LDD[13] is AF10
+ * GP72 == LDD[14] is AF10
+ * GP73 == LDD[15] is AF10
+ * GP74 == LCD_FCLK is AF10
+ * GP75 == LCD_LCLK is AF10
+ * GP76 == LCD_PCLK is AF10
+ * GP77 == LCD_ACBIAS is AF10
+ * GP78 == nCS2     is AF10
+ * GP79 == nCS3     is AF10
+ * GP80 == nCS4     is AF10
+ * GP81 == NSSPCLK  is AF01
+ * GP82 == NSSPSFRM is AF01
+ * GP83 == NSSPTXD  is AF01
+ * GP84 == NSSPRXD  is AF10
+ */
+#define CFG_GAFR0_L_VAL		0x80000004
+#define CFG_GAFR0_U_VAL		0x595A801A
+#define CFG_GAFR1_L_VAL		0x699A9559
+#define CFG_GAFR1_U_VAL		0xAAA5AAAA
+#define CFG_GAFR2_L_VAL		0xAAAAAAAA
+#define CFG_GAFR2_U_VAL		0x00000256
+
+/*
+ * clock settings
+ */
+/* RDH = 1
+ * PH  = 0
+ * VFS = 0
+ * BFS = 0
+ * SSS = 0
+ */
+#define CFG_PSSR_VAL		0x00000030
+
+#define CFG_CKEN_VAL            0x00000080  /*  */
+#define CFG_ICMR_VAL            0x00000000  /* No interrupts enabled        */
+
+
+/*
+ * Memory settings
+ *
+ * This is the configuration for nCS0/1 -> flash banks
+ * configuration for nCS1 :
+ * [31]    0    -
+ * [30:28] 000  -
+ * [27:24] 0000 -
+ * [23:20] 0000 -
+ * [19]    0    -
+ * [18:16] 000  -
+ * configuration for nCS0:
+ * [15]    0    - Slower Device
+ * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
+ * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns
+ * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?)
+ * [03]    0    - 32 Bit bus width
+ * [02:00] 010  - burst OF 4 ROM or FLASH
+*/
+#define CFG_MSC0_VAL		0x000023D2
+
+/* This is the configuration for nCS2/3 -> USB controller, LAN
+ * configuration for nCS3: LAN
+ * [31]    0    - Slower Device
+ * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
+ * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns
+ * [19]    0    - 32 Bit bus width
+ * [18:16] 100  - variable latency I/O
+ * configuration for nCS2: USB
+ * [15]    1    - Faster Device
+ * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
+ * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
+ * [03]    1    - 16 Bit bus width
+ * [02:00] 100  - variable latency I/O
+ */
+#define CFG_MSC1_VAL		0x1224A26C
+
+/* This is the configuration for nCS4/5 -> LAN
+ * configuration for nCS5:
+ * [31]    0    -
+ * [30:28] 000  -
+ * [27:24] 0000 -
+ * [23:20] 0000 -
+ * [19]    0    -
+ * [18:16] 000  -
+ * configuration for nCS4: LAN
+ * [15]    1    - Faster Device
+ * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
+ * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
+ * [03]    0    - 32 Bit bus width
+ * [02:00] 100  - variable latency I/O
+ */
+#define CFG_MSC2_VAL		0x00001224
+
+/* MDCNFG: SDRAM Configuration Register
+ *
+ * [31:29]   000 - reserved
+ * [28]      0	 - no SA1111 compatiblity mode
+ * [27]      0   - latch return data with return clock
+ * [26]      0   - alternate addressing for pair 2/3
+ * [25:24]   00  - timings
+ * [23]      0   - internal banks in lower partition 2/3 (not used)
+ * [22:21]   00  - row address bits for partition 2/3 (not used)
+ * [20:19]   00  - column address bits for partition 2/3 (not used)
+ * [18]      0   - SDRAM partition 2/3 width is 32 bit
+ * [17]      0   - SDRAM partition 3 disabled
+ * [16]      0   - SDRAM partition 2 disabled
+ * [15:13]   000 - reserved
+ * [12]      0	 - no SA1111 compatiblity mode
+ * [11]      1   - latch return data with return clock
+ * [10]      0   - no alternate addressing for pair 0/1
+ * [09:08]   10  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
+ * [7]       1   - 4 internal banks in lower partition pair
+ * [06:05]   10  - 13 row address bits for partition 0/1
+ * [04:03]   01  - 9 column address bits for partition 0/1
+ * [02]      0   - SDRAM partition 0/1 width is 32 bit
+ * [01]      0   - disable SDRAM partition 1
+ * [00]      1   - enable  SDRAM partition 0
+ */
+/* use the configuration above but disable partition 0 */
+#define CFG_MDCNFG_VAL		0x00000AC9
+
+/* MDREFR: SDRAM Refresh Control Register
+ *
+ * [32:26] 0     - reserved
+ * [25]    0     - K2FREE: not free running
+ * [24]    0     - K1FREE: not free running
+ * [23]    0     - K0FREE: not free running
+ * [22]    0     - SLFRSH: self refresh disabled
+ * [21]    0     - reserved
+ * [20]    1     - APD: auto power down
+ * [19]    0     - K2DB2: SDCLK2 is MemClk
+ * [18]    0     - K2RUN: disable SDCLK2
+ * [17]    0     - K1DB2: SDCLK1 is MemClk
+ * [16]    1     - K1RUN: enable SDCLK1
+ * [15]    1     - E1PIN: SDRAM clock enable
+ * [14]    0     - K0DB2: SDCLK0 is MemClk
+ * [13]    0     - K0RUN: disable SDCLK0
+ * [12]    0     - E0PIN: disable SDCKE0
+ * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
+ */
+#define CFG_MDREFR_VAL		0x00138018 /* mh: was 0x00118018 */
+
+/* MDMRS: Mode Register Set Configuration Register
+ *
+ * [31]      0       - reserved
+ * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
+ * [22:20]   011     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
+ * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
+ * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
+ * [15]      0       - reserved
+ * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
+ * [06:04]   011     - MDCL0:  SDRAM0/1 Cas Latency.
+ * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
+ * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
+ */
+#define CFG_MDMRS_VAL		0x00320032
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL		0x00000000
+#define CFG_MCMEM0_VAL		0x00010504
+#define CFG_MCMEM1_VAL		0x00010504
+#define CFG_MCATT0_VAL		0x00010504
+#define CFG_MCATT1_VAL		0x00010504
+#define CFG_MCIO0_VAL		0x00004715
+#define CFG_MCIO1_VAL		0x00004715
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
new file mode 100755
index 0000000..952f73b
--- /dev/null
+++ b/include/configs/xm250.h
@@ -0,0 +1,349 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA250	       1	/* This is an PXA250 CPU	*/
+#define CONFIG_XM250	       1	/* on a MicroSys XM250 Board	*/
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+/*
+ * Size of malloc() pool; this lives below the uppermost 128 KiB which are
+ * used for the RAM copy of the uboot code
+ *
+ */
+#define CFG_MALLOC_LEN		(256*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE		0x04000300
+#undef	CONFIG_SMC91111_EXT_PHY
+#define CONFIG_SMC_USE_32_BIT
+#undef	CONFIG_SHOW_ACTIVITY
+#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries		*/
+
+/*
+ * I2C bus
+ */
+#define CONFIG_HARD_I2C			1
+#define CFG_I2C_SPEED			50000
+#define CFG_I2C_SLAVE			0xfe
+
+#define CONFIG_RTC_PCF8563		1
+#define CFG_I2C_RTC_ADDR		0x51
+
+#define CFG_I2C_EEPROM_ADDR		0x58	/* A0 = 0 (hardwired)		*/
+#define CFG_EEPROM_PAGE_WRITE_BITS	4	/* 4 bits = 16 octets		*/
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* between stop and start	*/
+#define CFG_I2C_EEPROM_ADDR_LEN		1	/* length of address		*/
+#define CFG_EEPROM_SIZE			2048	/* size in bytes		*/
+#undef	CFG_I2C_INIT_BOARD			/* board has no own init	*/
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_FFUART	       1       /* we use FFUART */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
+				 CFG_CMD_ELF	| \
+				 CFG_CMD_EEPROM | \
+				 CFG_CMD_DATE	| \
+				 CFG_CMD_I2C	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP				/* undef to save memory		*/
+#define CFG_PROMPT		"=> "		/* Monitor Command Prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0xa0400000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM		*/
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		0xa3000000	/* default load address */
+
+#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED		0x161		/* set core clock to 400/400/100 MHz */
+
+						/* valid baudrates */
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Definitions related to passing arguments to kernel.
+ */
+#define CONFIG_CMDLINE_TAG	     1	 /* send commandline to Kernel		*/
+#define CONFIG_SETUP_MEMORY_TAGS     1	 /* send memory definition to kernel	*/
+#undef	CONFIG_INITRD_TAG		 /* do not send initrd params		*/
+#undef	CONFIG_VFD			 /* do not send framebuffer setup	*/
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	4
+#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1	*/
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB		*/
+#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2	*/
+#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB		*/
+#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3	*/
+#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB		*/
+#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4	*/
+#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB		*/
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1	*/
+#define PHYS_FLASH_2		0x04000000 /* Flash Bank #1	*/
+#define PHYS_FLASH_SIZE		0x01000000 /* 16 MB		*/
+#define PHYS_FLASH_BANK_SIZE	0x01000000 /* 16 MB Banks	*/
+#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
+
+#define CFG_DRAM_BASE		0xa0000000
+#define CFG_DRAM_SIZE		0x04000000
+
+#define CFG_FLASH_BASE		PHYS_FLASH_1
+
+/*
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1     /* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	128   /* max number of sectors on one chip	*/
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Erase	*/
+#define CFG_FLASH_WRITE_TOUT	(2*CFG_HZ)	/* Timeout for Flash Write	*/
+#define CFG_FLASH_LOCK_TOUT	(2*CFG_HZ)	/* Timeout for Flash Set Lock Bit */
+#define CFG_FLASH_UNLOCK_TOUT	(2*CFG_HZ)	/* Timeout for Flash Clear Lock Bits */
+#define CFG_FLASH_PROTECTION			/* "Real" (hardware) sectors protection */
+
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)	/* Addr of Environment Sector	*/
+#define CFG_ENV_SIZE		0x4000
+#define CFG_ENV_SECT_SIZE	0x40000				/* Size of the Environment Sector	*/
+#define CFG_MONITOR_LEN		0x20000				/* 128 KiB */
+
+/******************************************************************************
+ *
+ * CPU specific defines
+ *
+ ******************************************************************************/
+
+/*
+ * GPIO settings
+ *
+ * GPIO pin assignments
+ * GPIO	    Name	Dir Out AF
+ * 0	    NC
+ * 1	    NC
+ * 2	    SIRQ1	I
+ * 3	    SIRQ2	I
+ * 4	    SIRQ3	I
+ * 5	    DMAACK1	O   0
+ * 6	    DMAACK2	O   0
+ * 7	    DMAACK3	O   0
+ * 8	    TC1		O   0
+ * 9	    TC2		O   0
+ * 10	    TC3		O   0
+ * 11	    nDMAEN	O   1
+ * 12	    AENCTRL	O   0
+ * 13	    PLDTC	O   0
+ * 14	    ETHIRQ	I
+ * 15	    NC
+ * 16	    NC
+ * 17	    NC
+ * 18	    RDY		I
+ * 19	    DMASIO	I
+ * 20	    ETHIRQ	NC
+ * 21	    NC
+ * 22	    PGMEN	O   1	 FIXME for debug only enable flash
+ * 23	    NC
+ * 24	    NC
+ * 25	    NC
+ * 26	    NC
+ * 27	    NC
+ * 28	    NC
+ * 29	    NC
+ * 30	    NC
+ * 31	    NC
+ * 32	    NC
+ * 33	    NC
+ * 34	    FFRXD	I	01
+ * 35	    FFCTS	I	01
+ * 36	    FFDCD	I	01
+ * 37	    FFDSR	I	01
+ * 38	    FFRI	I	01
+ * 39	    FFTXD	O   1	10
+ * 40	    FFDTR	O   0	10
+ * 41	    FFRTS	O   0	10
+ * 42	    RS232FOFF	O   0	00
+ * 43	    NC
+ * 44	    NC
+ * 45	    IRSL0	O   0
+ * 46	    IRRX0	I	01
+ * 47	    IRTX0	O   0	10
+ * 48	    NC
+ * 49	    nIOWE	O   0
+ * 50	    NC
+ * 51	    NC
+ * 52	    NC
+ * 53	    NC
+ * 54	    NC
+ * 55	    NC
+ * 56	    NC
+ * 57	    NC
+ * 58	    DKDIRQ	I
+ * 59	    NC
+ * 60	    NC
+ * 61	    NC
+ * 62	    NC
+ * 63	    NC
+ * 64	    COMLED	O   0
+ * 65	    COMLED	O   0
+ * 66	    COMLED	O   0
+ * 67	    COMLED	O   0
+ * 68	    COMLED	O   0
+ * 69	    COMLED	O   0
+ * 70	    COMLED	O   0
+ * 71	    COMLED	O   0
+ * 72	    NC
+ * 73	    NC
+ * 74	    NC
+ * 75	    NC
+ * 76	    NC
+ * 77	    NC
+ * 78	    CSIO	O   1
+ * 79	    NC
+ * 80	    CSETH	O   1
+ *
+ * NOTE: All NC's are defined to be outputs
+ *
+ */
+/* Pin direction control */
+#define CFG_GPDR0_VAL	    0xd3808000
+#define CFG_GPDR1_VAL	    0xfcffab83
+#define CFG_GPDR2_VAL	    0x0001ffff
+/* Set and Clear registers */
+#define CFG_GPSR0_VAL	    0x00008000
+#define CFG_GPSR1_VAL	    0x00ff0002
+#define CFG_GPSR2_VAL	    0x0001c000
+#define CFG_GPCR0_VAL	    0x00000000
+#define CFG_GPCR1_VAL	    0x00000000
+#define CFG_GPCR2_VAL	    0x00000000
+/* Edge detect registers (these are set by the kernel) */
+#define CFG_GRER0_VAL	    0x00002180
+#define CFG_GRER1_VAL	    0x00000000
+#define CFG_GRER2_VAL	    0x00000000
+#define CFG_GFER0_VAL	    0x000043e0
+#define CFG_GFER1_VAL	    0x00000000
+#define CFG_GFER2_VAL	    0x00000000
+/* Alternate function registers */
+#define CFG_GAFR0_L_VAL	    0x80000004
+#define CFG_GAFR0_U_VAL	    0x595a8010
+#define CFG_GAFR1_L_VAL	    0x699a9559
+#define CFG_GAFR1_U_VAL	    0xaaa5aaaa
+#define CFG_GAFR2_L_VAL	    0xaaaaaaaa
+#define CFG_GAFR2_U_VAL	    0x00000002
+
+/*
+ * Clocks, power control and interrupts
+ */
+#define CFG_PSSR_VAL	    0x00000030
+#define CFG_CCCR_VAL	    0x00000161	/* 100 MHz memory, 400 MHz CPU, 400 Turbo  */
+#define CFG_CKEN_VAL	    0x000141ec	/* FFUART and STUART enabled	*/
+#define CFG_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/
+
+/* FIXME
+ *
+ * RTC settings
+ * Watchdog
+ *
+ */
+
+/*
+ * Memory settings
+ *
+ */
+#define CFG_MSC0_VAL	    0x122423f0	/* FLASH   / LAN	    (cs0)/(cS1)	  */
+#define CFG_MSC1_VAL	    0x35f4aa4c	/* USB	   / ST3+ST5	    (cs2)/(cS3)	  */
+#define CFG_MSC2_VAL	    0x35f435fc	/* IDE	   / BCR + WatchDog (cs4)/(cS5)	  */
+#define CFG_MDCNFG_VAL	    0x000009c9
+#define CFG_MDMRS_VAL	    0x00220022
+#define CFG_MDREFR_VAL	    0x000da018	/* Initial setting, individual bits set in lowlevel_init.S */
+
+/*
+ * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
+ */
+#define CFG_MECR_VAL	      0x00000000
+#define CFG_MCMEM0_VAL	      0x00010504
+#define CFG_MCMEM1_VAL	      0x00010504
+#define CFG_MCATT0_VAL	      0x00010504
+#define CFG_MCATT1_VAL	      0x00010504
+#define CFG_MCIO0_VAL	      0x00004715
+#define CFG_MCIO1_VAL	      0x00004715
+
+/* Board specific defines */
+
+#ifndef __ASSEMBLY__
+
+/* global prototypes */
+void led_code(int code, int color);
+
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h
new file mode 100755
index 0000000..dc702cf
--- /dev/null
+++ b/include/configs/xsengine.h
@@ -0,0 +1,191 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_PXA250			1		/* This is an PXA250 CPU    */
+#define CONFIG_XSENGINE			1
+#define CONFIG_MMC			1
+#define BOARD_POST_INIT			1
+#undef  CONFIG_USE_IRQ					/* we don't need IRQ/FIQ stuff */
+#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
+
+#undef  CONFIG_USE_IRQ					/* we don't need IRQ/FIQ stuff */
+#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED			0x161           /* set core clock to 400/200/100 MHz */
+
+#define CONFIG_NR_DRAM_BANKS		1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
+#define PHYS_SDRAM_2			0xa4000000	/* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 MB */
+#define PHYS_SDRAM_3			0xa8000000	/* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE		0x00000000	/* 0 MB */
+#define PHYS_SDRAM_4			0xac000000	/* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE		0x00000000	/* 0 MB */
+#define CFG_DRAM_BASE			0xa0000000
+#define CFG_DRAM_SIZE			0x04000000
+
+/* FLASH organization */
+#define CFG_MAX_FLASH_BANKS		1		/* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT		128		/* max number of sectors on one chip    */
+#define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
+#define PHYS_FLASH_2			0x00000000	/* Flash Bank #2 */
+#define PHYS_FLASH_SECT_SIZE		0x00020000	/* 127 KB sectors */
+#define CFG_FLASH_BASE			PHYS_FLASH_1
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor0=xsengine-0"
+#define MTDPARTS_DEFAULT	"mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)"
+*/
+
+/* Environment settings */
+#define CONFIG_ENV_OVERWRITE
+#define CFG_ENV_IS_IN_FLASH             1
+#define CFG_ENV_ADDR                    (PHYS_FLASH_1 + 0x40000)	/* Addr of Environment Sector (after monitor)*/
+#define CFG_ENV_SECT_SIZE               PHYS_FLASH_SECT_SIZE		/* Size of the Environment Sector */
+#define CFG_ENV_SIZE                    0x4000				/* 16kB Total Size of Environment Sector */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT		(75*CFG_HZ) 	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(50*CFG_HZ) 	/* Timeout for Flash Write */
+
+/* Size of malloc() pool */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 256*1024)
+#define CFG_GBL_DATA_SIZE		128		/* size in bytes reserved for initial data */
+
+/* Hardware drivers */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE		0x04000300
+#define CONFIG_SMC_USE_32_BIT 		1
+
+/* select serial console configuration */
+#define CONFIG_FFUART			1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_COMMANDS			(CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_PING | CFG_CMD_JFFS2)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ETHADDR			FF:FF:FF:FF:FF:FF
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_IPADDR			192.168.1.50
+#define CONFIG_SERVERIP			192.168.1.2
+#define CONFIG_BOOTARGS			"root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
+#define CONFIG_CMDLINE_TAG
+
+/* Miscellaneous configurable options */
+#define CFG_HUSH_PARSER			1
+#define CFG_PROMPT_HUSH_PS2		"> "
+#define CFG_LONGHELP								/* undef to save memory	*/
+#define CFG_PROMPT			"XS-Engine u-boot> "			/* Monitor Command Prompt */
+#define CFG_CBSIZE			256					/* Console I/O Buffer Size */
+#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) 	/* Print Buffer Size */
+#define CFG_MAXARGS			16					/* max number of command args */
+#define CFG_BARGSIZE			CFG_CBSIZE				/* Boot Argument Buffer Size */
+#define CFG_MEMTEST_START		0xA0400000				/* memtest works on     */
+#define CFG_MEMTEST_END			0xA0800000				/* 4 ... 8 MB in DRAM   */
+#undef  CFG_CLKS_IN_HZ          						/* everything, incl board info, in Hz */
+#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }	/* valid baudrates */
+#define CFG_MMC_BASE			0xF0000000
+#define CFG_LOAD_ADDR           	0xA0000000				/* load kernel to this address   */
+
+/* Stack sizes - The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
+#ifdef  CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
+#endif
+
+/* GP set register */
+#define CFG_GPSR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
+#define CFG_GPSR1_VAL			0x00020000	/* nPWE */
+#define CFG_GPSR2_VAL			0x0000C000	/* CS2, CS3 */
+
+/* GP clear register */
+#define CFG_GPCR0_VAL			0x00000000
+#define CFG_GPCR1_VAL			0x00000000
+#define CFG_GPCR2_VAL			0x00000000
+
+/* GP direction register */
+#define CFG_GPDR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
+#define CFG_GPDR1_VAL			0x00022A80	/* nPWE, FFUART + BTUART pins */
+#define CFG_GPDR2_VAL			0x0000C000  	/* CS2, CS3 */
+
+/* GP rising edge detect register */
+#define CFG_GRER0_VAL			0x00000000
+#define CFG_GRER1_VAL			0x00000000
+#define CFG_GRER2_VAL			0x00000000
+
+/* GP falling edge detect register */
+#define CFG_GFER0_VAL			0x00000000
+#define CFG_GFER1_VAL			0x00000000
+#define CFG_GFER2_VAL			0x00000000
+
+/* GP alternate function register */
+#define CFG_GAFR0_L_VAL			0x80000000	/* CS1 */
+#define CFG_GAFR0_U_VAL			0x00000010	/* RDY */
+#define CFG_GAFR1_L_VAL			0x09988050	/* FFUART + BTUART pins */
+#define CFG_GAFR1_U_VAL			0x00000008	/* nPWE */
+#define CFG_GAFR2_L_VAL			0xA0000000  	/* CS2, CS3 */
+#define CFG_GAFR2_U_VAL			0x00000000
+
+#define CFG_PSSR_VAL			0x00000020	/* Power manager sleep status */
+#define CFG_CCCR_VAL			0x00000161	/* 100 MHz memory, 400 MHz CPU  */
+#define CFG_CKEN_VAL			0x000000C0	/* BTUART and FFUART enabled    */
+#define CFG_ICMR_VAL			0x00000000	/* No interrupts enabled        */
+
+/* Memory settings */
+#define CFG_MSC0_VAL			0x25F425F0
+
+/* MDCNFG: SDRAM Configuration Register */
+#define CFG_MDCNFG_VAL			0x000009C9
+
+/* MDREFR: SDRAM Refresh Control Register */
+#define CFG_MDREFR_VAL			0x00018018
+
+/* MDMRS: Mode Register Set Configuration Register */
+#define CFG_MDMRS_VAL			0x00220022
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h
new file mode 100755
index 0000000..d3e9671
--- /dev/null
+++ b/include/configs/yellowstone.h
@@ -0,0 +1,315 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * yellowstone.h - configuration for YELLOWSTONE board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_YOLLOWSTONE	1	/* Board is Yellowstone         */
+#define CONFIG_440GR		1	/* Specific PPC440EP support    */
+#define CONFIG_4xx		1	/* ... PPC4xx family	        */
+#define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
+#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
+#define CFG_FLASH_BASE	        0xfc000000	    /* start of FLASH	*/
+#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
+#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
+#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
+
+/*Don't change either of these*/
+#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
+#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
+/*Don't change either of these*/
+
+#define CFG_USB_DEVICE          0x50000000
+#define CFG_NVRAM_BASE_ADDR     0x80000000
+#define CFG_BCSR_BASE	        (CFG_NVRAM_BASE_ADDR | 0x2000)
+#define CFG_BOOT_BASE_ADDR      0xf0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CFG_INIT_RAM_END	(8 << 10)
+#define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI     1
+/*define this if you want console on UART1*/
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+#define CFG_FLASH_CFI_AMD_RESET 1		/* AMD RESET for STM 29W320DB!	*/
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM	       /* Don't use SPD EEPROM for setup    */
+#define CFG_KBYTES_SDRAM        (128 * 1024)    /* 128MB		    */
+#define CFG_SDRAM_BANKS	        (2)
+
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE		0x200	    /* Size of Environment vars */
+#define CFG_ENV_OFFSET		0x0
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=yellowstone\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/yellowstone/uImage\0"			\
+	"kernel_addr=fc000000\0"					\
+	"ramdisk_addr=fc100000\0"					\
+	"load=tftp 100000 /tftpboot/yellowstone/u-boot.bin\0"		\
+	"update=protect off fff80000 ffffffff;era fff80000 ffffffff;"	\
+		"cp.b 100000 fff80000 80000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_NET_MULTI        1	/* required for netconsole      */
+#define CONFIG_PHY1_ADDR        3
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef CONFIG_440EP
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/*Comment this out to enable USB 1.1 device*/
+#define USB_2_0_DEVICE
+#endif /*CONFIG_440EP*/
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#else
+#define CONFIG_HW_WATCHDOG			/* watchdog */
+#endif
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SDRAM)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI          1       /* support kdi files            */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
new file mode 100755
index 0000000..a67b834
--- /dev/null
+++ b/include/configs/yosemite.h
@@ -0,0 +1,320 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * yosemite.h - configuration for YOSEMITE board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_YOSEMITE		1	/* Board is Yosemite            */
+#define CONFIG_440EP		1	/* Specific PPC440EP support    */
+#define CONFIG_4xx		1	/* ... PPC4xx family	        */
+#define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
+#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
+#define CFG_FLASH_BASE	        0xfc000000	    /* start of FLASH	*/
+#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
+#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
+#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
+
+/*Don't change either of these*/
+#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
+#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
+/*Don't change either of these*/
+
+#define CFG_USB_DEVICE          0x50000000
+#define CFG_NVRAM_BASE_ADDR     0x80000000
+#define CFG_BCSR_BASE	        (CFG_NVRAM_BASE_ADDR | 0x2000)
+#define CFG_BOOT_BASE_ADDR      0xf0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CFG_INIT_RAM_END	(8 << 10)
+#define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CFG_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI     1
+/*define this if you want console on UART1*/
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+#define CFG_FLASH_CFI_AMD_RESET 1		/* AMD RESET for STM 29W320DB!	*/
+
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM	       /* Don't use SPD EEPROM for setup    */
+#define CFG_KBYTES_SDRAM        (128 * 1024)    /* 128MB		    */
+#define CFG_SDRAM_BANKS	        (2)
+
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_MULTI_EEPROMS
+#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+#define CFG_ENV_SIZE		0x200	    /* Size of Environment vars */
+#define CFG_ENV_OFFSET		0x0
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=yosemite\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/yosemite/uImage\0"				\
+	"kernel_addr=fc000000\0"					\
+	"ramdisk_addr=fc100000\0"					\
+	"load=tftp 100000 /tftpboot/yosemite/u-boot.bin\0"		\
+	"update=protect off fff80000 ffffffff;era fff80000 ffffffff;"	\
+		"cp.b 100000 fff80000 80000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_NET_MULTI        1	/* required for netconsole      */
+#define CONFIG_PHY1_ADDR        3
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef CONFIG_440EP
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/*Comment this out to enable USB 1.1 device*/
+#define USB_2_0_DEVICE
+#endif /*CONFIG_440EP*/
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#else
+#define CONFIG_HW_WATCHDOG			/* watchdog */
+#endif
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_EXT2	| \
+				CFG_CMD_USB	)
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI          1       /* support kdi files            */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/console.h b/include/console.h
new file mode 100755
index 0000000..06ec32a
--- /dev/null
+++ b/include/console.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CONSOLE_H_
+#define _CONSOLE_H_
+
+#include <devices.h>
+
+/*
+** VARIABLES
+*/
+
+extern device_t	*stdio_devices[] ;
+extern char *stdio_names[MAX_FILES] ;
+
+int console_realloc(int top);
+
+#endif
diff --git a/include/cramfs/cramfs_fs.h b/include/cramfs/cramfs_fs.h
new file mode 100755
index 0000000..9f1b1d5
--- /dev/null
+++ b/include/cramfs/cramfs_fs.h
@@ -0,0 +1,122 @@
+#ifndef __CRAMFS_H
+#define __CRAMFS_H
+
+#define CRAMFS_MAGIC		0x28cd3d45	/* some random number */
+#define CRAMFS_SIGNATURE	"Compressed ROMFS"
+
+/*
+ * Width of various bitfields in struct cramfs_inode.
+ * Primarily used to generate warnings in mkcramfs.
+ */
+#define CRAMFS_MODE_WIDTH	16
+#define CRAMFS_UID_WIDTH	16
+#define CRAMFS_SIZE_WIDTH	24
+#define CRAMFS_GID_WIDTH	8
+#define CRAMFS_NAMELEN_WIDTH	6
+#define CRAMFS_OFFSET_WIDTH	26
+
+/*
+ * Since inode.namelen is a unsigned 6-bit number, the maximum cramfs
+ * path length is 63 << 2 = 252.
+ */
+#define CRAMFS_MAXPATHLEN (((1 << CRAMFS_NAMELEN_WIDTH) - 1) << 2)
+
+/*
+ * Reasonably terse representation of the inode data.
+ */
+struct cramfs_inode {
+	u32 mode:CRAMFS_MODE_WIDTH, uid:CRAMFS_UID_WIDTH;
+
+	/* SIZE for device files is i_rdev */
+	u32 size:CRAMFS_SIZE_WIDTH, gid:CRAMFS_GID_WIDTH;
+
+	/* NAMELEN is the length of the file name, divided by 4 and
+	   rounded up.	(cramfs doesn't support hard links.) */
+	/* OFFSET: For symlinks and non-empty regular files, this
+	   contains the offset (divided by 4) of the file data in
+	   compressed form (starting with an array of block pointers;
+	   see README).	 For non-empty directories it is the offset
+	   (divided by 4) of the inode of the first file in that
+	   directory.  For anything else, offset is zero. */
+	u32 namelen:CRAMFS_NAMELEN_WIDTH, offset:CRAMFS_OFFSET_WIDTH;
+};
+
+struct cramfs_info {
+	u32 crc;
+	u32 edition;
+	u32 blocks;
+	u32 files;
+};
+
+/*
+ * Superblock information at the beginning of the FS.
+ */
+struct cramfs_super {
+	u32 magic;			/* 0x28cd3d45 - random number */
+	u32 size;			/* length in bytes */
+	u32 flags;			/* feature flags */
+	u32 future;			/* reserved for future use */
+	u8 signature[16];		/* "Compressed ROMFS" */
+	struct cramfs_info fsid;	/* unique filesystem info */
+	u8 name[16];			/* user-defined name */
+	struct cramfs_inode root;	/* root inode data */
+};
+
+/*
+ * Feature flags
+ *
+ * 0x00000000 - 0x000000ff: features that work for all past kernels
+ * 0x00000100 - 0xffffffff: features that don't work for past kernels
+ */
+#define CRAMFS_FLAG_FSID_VERSION_2	0x00000001	/* fsid version #2 */
+#define CRAMFS_FLAG_SORTED_DIRS		0x00000002	/* sorted dirs */
+#define CRAMFS_FLAG_HOLES		0x00000100	/* support for holes */
+#define CRAMFS_FLAG_WRONG_SIGNATURE	0x00000200	/* reserved */
+#define CRAMFS_FLAG_SHIFTED_ROOT_OFFSET 0x00000400	/* shifted root fs */
+
+/*
+ * Valid values in super.flags.	 Currently we refuse to mount
+ * if (flags & ~CRAMFS_SUPPORTED_FLAGS).  Maybe that should be
+ * changed to test super.future instead.
+ */
+#define CRAMFS_SUPPORTED_FLAGS	( 0x000000ff \
+				| CRAMFS_FLAG_HOLES \
+				| CRAMFS_FLAG_WRONG_SIGNATURE \
+				| CRAMFS_FLAG_SHIFTED_ROOT_OFFSET )
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define CRAMFS_16(x)	(x)
+#define CRAMFS_24(x)	(x)
+#define CRAMFS_32(x)	(x)
+#define CRAMFS_GET_NAMELEN(x)	((x)->namelen)
+#define CRAMFS_GET_OFFSET(x)	((x)->offset)
+#define CRAMFS_SET_OFFSET(x,y)	((x)->offset = (y))
+#define CRAMFS_SET_NAMELEN(x,y) ((x)->namelen = (y))
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#ifdef __KERNEL__
+#define CRAMFS_16(x)	swab16(x)
+#define CRAMFS_24(x)	((swab32(x)) >> 8)
+#define CRAMFS_32(x)	swab32(x)
+#else /* not __KERNEL__ */
+#define CRAMFS_16(x)	bswap_16(x)
+#define CRAMFS_24(x)	((bswap_32(x)) >> 8)
+#define CRAMFS_32(x)	bswap_32(x)
+#endif /* not __KERNEL__ */
+#define CRAMFS_GET_NAMELEN(x)	(((u8*)(x))[8] & 0x3f)
+#define CRAMFS_GET_OFFSET(x)	((CRAMFS_24(((u32*)(x))[2] & 0xffffff) << 2) |\
+				 ((((u32*)(x))[2] & 0xc0000000) >> 30))
+#define CRAMFS_SET_NAMELEN(x,y)	(((u8*)(x))[8] = (((0x3f & (y))) | \
+						  (0xc0 & ((u8*)(x))[8])))
+#define CRAMFS_SET_OFFSET(x,y)	(((u32*)(x))[2] = (((y) & 3) << 30) | \
+				 CRAMFS_24((((y) & 0x03ffffff) >> 2)) | \
+				 (((u32)(((u8*)(x))[8] & 0x3f)) << 24))
+#else
+#error "__BYTE_ORDER must be __LITTLE_ENDIAN or __BIG_ENDIAN"
+#endif
+
+/* Uncompression interfaces to the underlying zlib */
+int cramfs_uncompress_block(void *dst, void *src, int srclen);
+int cramfs_uncompress_init(void);
+int cramfs_uncompress_exit(void);
+
+#endif	/* __CRAMFS_H */
diff --git a/include/cramfs/cramfs_fs_sb.h b/include/cramfs/cramfs_fs_sb.h
new file mode 100755
index 0000000..bc23f94
--- /dev/null
+++ b/include/cramfs/cramfs_fs_sb.h
@@ -0,0 +1,19 @@
+#ifndef _CRAMFS_FS_SB
+#define _CRAMFS_FS_SB
+
+/*
+ * cramfs super-block data in memory
+ */
+struct cramfs_sb_info {
+			unsigned long magic;
+			unsigned long size;
+			unsigned long blocks;
+			unsigned long files;
+			unsigned long flags;
+#ifdef CONFIG_CRAMFS_LINEAR
+			unsigned long linear_phys_addr;
+			char *        linear_virt_addr;
+#endif
+};
+
+#endif
diff --git a/include/dataflash.h b/include/dataflash.h
new file mode 100755
index 0000000..650454e
--- /dev/null
+++ b/include/dataflash.h
@@ -0,0 +1,178 @@
+/*
+ * (C) Copyright 2003
+ * Data Flash Atmel Description File
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* File Name		: dataflash.h					*/
+/* Object		: Data Flash Atmel Description File		*/
+/* Translator		:						*/
+/*									*/
+/* 1.0 03/04/01 HI	: Creation					*/
+/* 1.2 20/10/02 FB	: Adapatation Service and Lib v3		*/
+/*----------------------------------------------------------------------*/
+
+#ifndef _DataFlash_h
+#define _DataFlash_h
+
+
+#include <asm/arch/hardware.h>
+#include "config.h"
+
+/*number of protected area*/
+#define NB_DATAFLASH_AREA	4
+
+/*define the area structure*/
+typedef struct {
+	unsigned long start;
+	unsigned long end;
+	unsigned char protected;
+} dataflash_protect_t;
+
+typedef unsigned int AT91S_DataFlashStatus;
+
+/*----------------------------------------------------------------------*/
+/* DataFlash Structures							*/
+/*----------------------------------------------------------------------*/
+
+/*---------------------------------------------*/
+/* DataFlash Descriptor Structure Definition   */
+/*---------------------------------------------*/
+typedef struct _AT91S_DataflashDesc {
+	unsigned char *tx_cmd_pt;
+	unsigned int tx_cmd_size;
+	unsigned char *rx_cmd_pt;
+	unsigned int rx_cmd_size;
+	unsigned char *tx_data_pt;
+	unsigned int tx_data_size;
+	unsigned char *rx_data_pt;
+	unsigned int rx_data_size;
+	volatile unsigned char state;
+	volatile unsigned char DataFlash_state;
+	unsigned char command[8];
+} AT91S_DataflashDesc, *AT91PS_DataflashDesc;
+
+/*---------------------------------------------*/
+/* DataFlash device definition structure       */
+/*---------------------------------------------*/
+typedef struct _AT91S_Dataflash {
+	int pages_number;			/* dataflash page number */
+	int pages_size;				/* dataflash page size */
+	int page_offset;			/* page offset in command */
+	int byte_mask;				/* byte mask in command */
+	int cs;
+	dataflash_protect_t area_list[NB_DATAFLASH_AREA]; /* area protection status */
+} AT91S_DataflashFeatures, *AT91PS_DataflashFeatures;
+
+/*---------------------------------------------*/
+/* DataFlash Structure Definition	       */
+/*---------------------------------------------*/
+typedef struct _AT91S_DataFlash {
+	AT91PS_DataflashDesc pDataFlashDesc;	/* dataflash descriptor */
+	AT91PS_DataflashFeatures pDevice;	/* Pointer on a dataflash features array */
+} AT91S_DataFlash, *AT91PS_DataFlash;
+
+
+typedef struct _AT91S_DATAFLASH_INFO {
+
+	AT91S_DataflashDesc Desc;
+	AT91S_DataflashFeatures Device; /* Pointer on a dataflash features array */
+	unsigned long logical_address;
+	unsigned int id;			/* device id */
+} AT91S_DATAFLASH_INFO, *AT91PS_DATAFLASH_INFO;
+
+
+/*-------------------------------------------------------------------------------------------------*/
+
+#define AT45DB161	0x2c
+#define AT45DB321	0x34
+#define AT45DB642	0x3c
+#define AT45DB128	0x10
+
+#define AT91C_DATAFLASH_TIMEOUT		10000	/* For AT91F_DataFlashWaitReady */
+
+/* DataFlash return value */
+#define DATAFLASH_BUSY			0x00
+#define DATAFLASH_OK			0x01
+#define DATAFLASH_ERROR			0x02
+#define DATAFLASH_MEMORY_OVERFLOW	0x03
+#define DATAFLASH_BAD_COMMAND		0x04
+#define DATAFLASH_BAD_ADDRESS		0x05
+
+
+/* Driver State */
+#define IDLE		0x0
+#define BUSY		0x1
+#define ERROR		0x2
+
+/* DataFlash Driver State */
+#define GET_STATUS	0x0F
+
+/*-------------------------------------------------------------------------------------------------*/
+/* Command Definition										   */
+/*-------------------------------------------------------------------------------------------------*/
+
+/* READ COMMANDS */
+#define DB_CONTINUOUS_ARRAY_READ	0xE8	/* Continuous array read */
+#define DB_BURST_ARRAY_READ		0xE8	/* Burst array read */
+#define DB_PAGE_READ			0xD2	/* Main memory page read */
+#define DB_BUF1_READ			0xD4	/* Buffer 1 read */
+#define DB_BUF2_READ			0xD6	/* Buffer 2 read */
+#define DB_STATUS			0xD7	/* Status Register */
+
+/* PROGRAM and ERASE COMMANDS */
+#define DB_BUF1_WRITE			0x84	/* Buffer 1 write */
+#define DB_BUF2_WRITE			0x87	/* Buffer 2 write */
+#define DB_BUF1_PAGE_ERASE_PGM		0x83	/* Buffer 1 to main memory page program with built-In erase */
+#define DB_BUF1_PAGE_ERASE_FASTPGM	0x93	/* Buffer 1 to main memory page program with built-In erase, Fast program */
+#define DB_BUF2_PAGE_ERASE_PGM		0x86	/* Buffer 2 to main memory page program with built-In erase */
+#define DB_BUF2_PAGE_ERASE_FASTPGM	0x96	/* Buffer 1 to main memory page program with built-In erase, Fast program */
+#define DB_BUF1_PAGE_PGM		0x88	/* Buffer 1 to main memory page program without built-In erase */
+#define DB_BUF1_PAGE_FASTPGM		0x98	/* Buffer 1 to main memory page program without built-In erase, Fast program */
+#define DB_BUF2_PAGE_PGM		0x89	/* Buffer 2 to main memory page program without built-In erase */
+#define DB_BUF2_PAGE_FASTPGM		0x99	/* Buffer 1 to main memory page program without built-In erase, Fast program */
+#define DB_PAGE_ERASE			0x81	/* Page Erase */
+#define DB_BLOCK_ERASE			0x50	/* Block Erase */
+#define DB_PAGE_PGM_BUF1		0x82	/* Main memory page through buffer 1 */
+#define DB_PAGE_FASTPGM_BUF1		0x92	/* Main memory page through buffer 1, Fast program */
+#define DB_PAGE_PGM_BUF2		0x85	/* Main memory page through buffer 2 */
+#define DB_PAGE_FastPGM_BUF2		0x95	/* Main memory page through buffer 2, Fast program */
+
+/* ADDITIONAL COMMANDS */
+#define DB_PAGE_2_BUF1_TRF		0x53	/* Main memory page to buffer 1 transfert */
+#define DB_PAGE_2_BUF2_TRF		0x55	/* Main memory page to buffer 2 transfert */
+#define DB_PAGE_2_BUF1_CMP		0x60	/* Main memory page to buffer 1 compare */
+#define DB_PAGE_2_BUF2_CMP		0x61	/* Main memory page to buffer 2 compare */
+#define DB_AUTO_PAGE_PGM_BUF1		0x58	/* Auto page rewrite throught buffer 1 */
+#define DB_AUTO_PAGE_PGM_BUF2		0x59	/* Auto page rewrite throught buffer 2 */
+
+/*-------------------------------------------------------------------------------------------------*/
+
+extern int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr, unsigned long size);
+extern int prot_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr);
+extern int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr);
+extern int addr_dataflash (unsigned long addr);
+extern int read_dataflash (unsigned long addr, unsigned long size, char *result);
+extern int write_dataflash (unsigned long addr, unsigned long dest, unsigned long size);
+extern void dataflash_print_info (void);
+extern void dataflash_perror (int err);
+
+#endif
diff --git a/include/devices.h b/include/devices.h
new file mode 100755
index 0000000..2d9e282
--- /dev/null
+++ b/include/devices.h
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <lists.h>
+
+#ifndef _DEVICES_H_
+#define _DEVICES_H_
+
+/*
+ * CONSOLE DEVICES
+ */
+
+#define DEV_FLAGS_INPUT	 0x00000001	/* Device can be used as input	console */
+#define DEV_FLAGS_OUTPUT 0x00000002	/* Device can be used as output console */
+#define DEV_FLAGS_SYSTEM 0x80000000	/* Device is a system device		*/
+#define DEV_EXT_VIDEO	 0x00000001	/* Video extensions supported		*/
+
+/* Device information */
+typedef struct {
+	int	flags;			/* Device flags: input/output/system	*/
+	int	ext;			/* Supported extensions			*/
+	char	name[16];		/* Device name				*/
+
+/* GENERAL functions */
+
+	int (*start) (void);		/* To start the device			*/
+	int (*stop) (void);		/* To stop the device			*/
+
+/* OUTPUT functions */
+
+	void (*putc) (const char c);	/* To put a char			*/
+	void (*puts) (const char *s);	/* To put a string (accelerator)	*/
+
+/* INPUT functions */
+
+	int (*tstc) (void);		/* To test if a char is ready...	*/
+	int (*getc) (void);		/* To get that char			*/
+
+/* Other functions */
+
+	void *priv;			/* Private extensions			*/
+} device_t;
+
+/*
+ * VIDEO EXTENSIONS
+ */
+#define VIDEO_FORMAT_RGB_INDEXED	0x0000
+#define VIDEO_FORMAT_RGB_DIRECTCOLOR	0x0001
+#define VIDEO_FORMAT_YUYV_4_4_4		0x0010
+#define VIDEO_FORMAT_YUYV_4_2_2		0x0011
+
+typedef struct {
+	void *address;			/* Address of framebuffer		*/
+	ushort	width;			/* Horizontal resolution		*/
+	ushort	height;			/* Vertical resolution			*/
+	uchar	format;			/* Format				*/
+	uchar	colors;			/* Colors number or color depth		*/
+	void (*setcolreg) (int, int, int, int);
+	void (*getcolreg) (int, void *);
+} video_ext_t;
+
+/*
+ * VARIABLES
+ */
+extern list_t devlist;
+extern device_t *stdio_devices[];
+extern char *stdio_names[MAX_FILES];
+
+/*
+ * PROTOTYPES
+ */
+int	device_register (device_t * dev);
+int	devices_init (void);
+int	devices_done (void);
+int	device_deregister(char *devname);
+#ifdef CONFIG_LCD
+int	drv_lcd_init (void);
+#endif
+#ifdef CONFIG_VFD
+int	drv_vfd_init (void);
+#endif
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+int	drv_video_init (void);
+#endif
+#ifdef CONFIG_KEYBOARD
+int	drv_keyboard_init (void);
+#endif
+#ifdef CONFIG_USB_TTY
+int	drv_usbtty_init (void);
+#endif
+#ifdef CONFIG_NETCONSOLE
+int	drv_nc_init (void);
+#endif
+
+#endif	/* _DEVICES_H_ */
diff --git a/include/div64.h b/include/div64.h
new file mode 100755
index 0000000..d833144
--- /dev/null
+++ b/include/div64.h
@@ -0,0 +1,49 @@
+#ifndef _ASM_GENERIC_DIV64_H
+#define _ASM_GENERIC_DIV64_H
+/*
+ * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
+ * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
+ *
+ * The semantics of do_div() are:
+ *
+ * uint32_t do_div(uint64_t *n, uint32_t base)
+ * {
+ *	uint32_t remainder = *n % base;
+ *	*n = *n / base;
+ *	return remainder;
+ * }
+ *
+ * NOTE: macro parameter n is evaluated multiple times,
+ *       beware of side effects!
+ */
+
+#include <linux/types.h>
+
+extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
+
+/* The unnecessary pointer compare is there
+ * to check for type safety (n must be 64bit)
+ */
+# define do_div(n,base) ({				\
+	uint32_t __base = (base);			\
+	uint32_t __rem;					\
+	(void)(((typeof((n)) *)0) == ((uint64_t *)0));	\
+	if (((n) >> 32) == 0) {			\
+		__rem = (uint32_t)(n) % __base;		\
+		(n) = (uint32_t)(n) / __base;		\
+	} else						\
+		__rem = __div64_32(&(n), __base);	\
+	__rem;						\
+ })
+
+/* Wrapper for do_div(). Doesn't modify dividend and returns
+ * the result, not reminder.
+ */
+static inline uint64_t lldiv(uint64_t dividend, uint32_t divisor)
+{
+	uint64_t __res = dividend;
+	do_div(__res, divisor);
+	return(__res);
+}
+
+#endif /* _ASM_GENERIC_DIV64_H */
diff --git a/include/dm9161.h b/include/dm9161.h
new file mode 100755
index 0000000..f5bfb19
--- /dev/null
+++ b/include/dm9161.h
@@ -0,0 +1,130 @@
+/*
+ * NOTE:	DAVICOM ethernet Physical layer
+ *
+ * Version:	@(#)DM9161.h	1.0.0	01/10/2001
+ *
+ * Authors:	ATMEL Rousset
+ *
+ *
+ *		This program is free software; you can redistribute it and/or
+ *		modify it under the terms of the GNU General Public License
+ *		as published by the Free Software Foundation; either version
+ *		2 of the License, or (at your option) any later version.
+ */
+
+
+/* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */
+
+#define	DM9161_BMCR 		0	/* Basic Mode Control Register */
+#define DM9161_BMSR		1	/* Basic Mode Status Register */
+#define DM9161_PHYID1		2	/* PHY Idendifier Register 1 */
+#define DM9161_PHYID2		3	/* PHY Idendifier Register 2 */
+#define DM9161_ANAR		4	/* Auto_Negotiation Advertisement Register  */
+#define DM9161_ANLPAR		5	/* Auto_negotiation Link Partner Ability Register */
+#define DM9161_ANER		6	/* Auto-negotiation Expansion Register  */
+#define DM9161_DSCR		16	/* Specified Configuration Register */
+#define DM9161_DSCSR		17	/* Specified Configuration and Status Register */
+#define DM9161_10BTCSR		18	/* 10BASE-T Configuration and Satus Register */
+#define DM9161_MDINTR		21	/* Specified Interrupt Register */
+#define DM9161_RECR		22	/* Specified Receive Error Counter Register */
+#define DM9161_DISCR		23	/* Specified Disconnect Counter Register */
+#define DM9161_RLSR		24	/* Hardware Reset Latch State Register */
+
+
+/* --Bit definitions: DM9161_BMCR */
+#define DM9161_RESET   	         (1 << 15)	/* 1= Software Reset; 0=Normal Operation */
+#define DM9161_LOOPBACK	         (1 << 14)	/* 1=loopback Enabled; 0=Normal Operation */
+#define DM9161_SPEED_SELECT      (1 << 13)	/* 1=100Mbps; 0=10Mbps */
+#define DM9161_AUTONEG	         (1 << 12)
+#define DM9161_POWER_DOWN        (1 << 11)
+#define DM9161_ISOLATE           (1 << 10)
+#define DM9161_RESTART_AUTONEG   (1 << 9)
+#define DM9161_DUPLEX_MODE       (1 << 8)
+#define DM9161_COLLISION_TEST    (1 << 7)
+
+/*--Bit definitions: DM9161_BMSR */
+#define DM9161_100BASE_T4        (1 << 15)
+#define DM9161_100BASE_TX_FD     (1 << 14)
+#define DM9161_100BASE_T4_HD     (1 << 13)
+#define DM9161_10BASE_T_FD       (1 << 12)
+#define DM9161_10BASE_T_HD       (1 << 11)
+#define DM9161_MF_PREAMB_SUPPR   (1 << 6)
+#define DM9161_AUTONEG_COMP      (1 << 5)
+#define DM9161_REMOTE_FAULT      (1 << 4)
+#define DM9161_AUTONEG_ABILITY   (1 << 3)
+#define DM9161_LINK_STATUS       (1 << 2)
+#define DM9161_JABBER_DETECT     (1 << 1)
+#define DM9161_EXTEND_CAPAB      (1 << 0)
+
+/*--definitions: DM9161_PHYID1 */
+#define DM9161_PHYID1_OUI	 0x606E
+#define DM9161_LSB_MASK	         0x3F
+
+/*--Bit definitions: DM9161_ANAR, DM9161_ANLPAR */
+#define DM9161_NP               (1 << 15)
+#define DM9161_ACK              (1 << 14)
+#define DM9161_RF               (1 << 13)
+#define DM9161_FCS              (1 << 10)
+#define DM9161_T4               (1 << 9)
+#define DM9161_TX_FDX           (1 << 8)
+#define DM9161_TX_HDX           (1 << 7)
+#define DM9161_10_FDX           (1 << 6)
+#define DM9161_10_HDX           (1 << 5)
+#define DM9161_AN_IEEE_802_3	0x0001
+
+/*--Bit definitions: DM9161_ANER */
+#define DM9161_PDF              (1 << 4)
+#define DM9161_LP_NP_ABLE       (1 << 3)
+#define DM9161_NP_ABLE          (1 << 2)
+#define DM9161_PAGE_RX          (1 << 1)
+#define DM9161_LP_AN_ABLE       (1 << 0)
+
+/*--Bit definitions: DM9161_DSCR */
+#define DM9161_BP4B5B           (1 << 15)
+#define DM9161_BP_SCR           (1 << 14)
+#define DM9161_BP_ALIGN         (1 << 13)
+#define DM9161_BP_ADPOK         (1 << 12)
+#define DM9161_REPEATER         (1 << 11)
+#define DM9161_TX               (1 << 10)
+#define DM9161_RMII_ENABLE      (1 << 8)
+#define DM9161_F_LINK_100       (1 << 7)
+#define DM9161_SPLED_CTL        (1 << 6)
+#define DM9161_COLLED_CTL       (1 << 5)
+#define DM9161_RPDCTR_EN        (1 << 4)
+#define DM9161_SM_RST           (1 << 3)
+#define DM9161_MFP SC           (1 << 2)
+#define DM9161_SLEEP            (1 << 1)
+#define DM9161_RLOUT            (1 << 0)
+
+/*--Bit definitions: DM9161_DSCSR */
+#define DM9161_100FDX           (1 << 15)
+#define DM9161_100HDX           (1 << 14)
+#define DM9161_10FDX            (1 << 13)
+#define DM9161_10HDX            (1 << 12)
+
+/*--Bit definitions: DM9161_10BTCSR */
+#define DM9161_LP_EN           (1 << 14)
+#define DM9161_HBE             (1 << 13)
+#define DM9161_SQUELCH         (1 << 12)
+#define DM9161_JABEN           (1 << 11)
+#define DM9161_10BT_SER        (1 << 10)
+#define DM9161_POLR            (1 << 0)
+
+
+/*--Bit definitions: DM9161_MDINTR */
+#define DM9161_INTR_PEND       (1 << 15)
+#define DM9161_FDX_MASK        (1 << 11)
+#define DM9161_SPD_MASK        (1 << 10)
+#define DM9161_LINK_MASK       (1 << 9)
+#define DM9161_INTR_MASK       (1 << 8)
+#define DM9161_FDX_CHANGE      (1 << 4)
+#define DM9161_SPD_CHANGE      (1 << 3)
+#define DM9161_LINK_CHANGE     (1 << 2)
+#define DM9161_INTR_STATUS     (1 << 0)
+
+
+/******************  function prototypes **********************/
+unsigned int  dm9161_IsPhyConnected(AT91PS_EMAC p_mac);
+unsigned char dm9161_GetLinkSpeed(AT91PS_EMAC p_mac);
+unsigned char dm9161_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
+unsigned char dm9161_InitPhy(AT91PS_EMAC p_mac);
diff --git a/include/dma.h b/include/dma.h
new file mode 100755
index 0000000..18f50f9
--- /dev/null
+++ b/include/dma.h
@@ -0,0 +1,436 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/

+

+#ifndef __DMA_H__

+#define __DMA_H__

+

+

+/***********************************************

+* The VT3426 has 16 internal DMA channels.

+*************************************************/

+#define DMA_CHANNELS    2

+#define MAX_DMA_CHANNELS DMA_CHANNELS

+#define DMA_INT0 17

+#define DMA_INT1 27

+#define DMA_INT2 34

+#define DMA_INT3 40

+#define DMA_INT4 41

+#define DMA_INT5 45

+#define DMA_INT6 46

+#define DMA_INT7 51

+#define DMA_INT8 92

+#define DMA_INT9 93

+#define DMA_INT10 94

+#define DMA_INT11 95

+#define DMA_INT12 96

+#define DMA_INT13 97

+#define DMA_INT14 98

+#define DMA_INT15 99

+

+

+/***********************************************

+* The DMA MEMORY REGISTER BASE ADDRESS.

+*************************************************/

+#define DMA_MEMREG_BASEADDR	0x5000000 /*80MB*/

+#define DMA_DES0_BASEADDR 0x5800000 /*88MB*/

+#define DMA_DES12_BASEADDR 0x5B00000 /*91MB*/

+

+/**************************************

+ This is the maximum DMA address that can be DMAd to.

+***************************************/

+#define MAX_DMA_ADDRESS		0x00FFFFFF

+

+/*************************************

+*  DMA_TCR_CHX_VAL

+*  DMA Transfer Count

+**************************************/

+/* Reserved [31:24] */

+#define DMA_TCR_MASK                        0x00FFFFFF      /* [23:00] -- Mask   */

+

+/************************************

+*

+*  DMA GLOBAL CONTROL

+*

+*************************************/

+#define DMA_SW_RST	BIT8

+#define DMA_BIG_ENDIAN	BIT1

+#define DMA_GLOBAL_EN	BIT0

+/************************************

+*

+*  DMA_INTERRUPT ENABLE

+*

+*************************************/

+#define CH00_INT_EN	BIT0

+#define CH01_INT_EN	BIT1

+#define CH02_INT_EN	BIT2

+#define CH03_INT_EN	BIT3

+#define CH04_INT_EN	BIT4

+#define CH05_INT_EN	BIT5

+#define CH06_INT_EN	BIT6

+#define CH07_INT_EN	BIT7

+#define CH08_INT_EN	BIT8

+#define CH09_INT_EN	BIT9

+#define CH10_INT_EN	BIT10

+#define CH11_INT_EN	BIT11

+#define CH12_INT_EN	BIT12

+#define CH13_INT_EN	BIT13

+#define CH14_INT_EN	BIT14

+#define CH15_INT_EN	BIT15

+#define ALL_INT_EN	0x0000FFFF

+

+/************************************

+*

+*  DMA_INTERRUPT STATUS

+*

+*************************************/

+#define CH00_INT_STS	BIT0

+#define CH01_INT_STS	BIT1

+#define CH02_INT_STS	BIT2

+#define CH03_INT_STS	BIT3

+#define CH04_INT_STS	BIT4

+#define CH05_INT_STS	BIT5

+#define CH06_INT_STS	BIT6

+#define CH07_INT_STS	BIT7

+#define CH08_INT_STS	BIT8

+#define CH09_INT_STS	BIT9

+#define CH10_INT_STS	BIT10

+#define CH11_INT_STS	BIT11

+#define CH12_INT_STS	BIT12

+#define CH13_INT_STS	BIT13

+#define CH14_INT_STS	BIT14

+#define CH15_INT_STS	BIT15

+#define ALL_INT_CLEAR	0x0000FFFF

+

+/************************************

+*

+*  DMA SCHEDULE SCHEME

+*

+*************************************/

+#define SCHEDULE_RR_DISABLE	BIT0

+#define TIMER_1_SHIFT	16

+#define TIMER_2_SHIFT	8

+/************************************

+*

+*  DMA_CCR SETTIGN

+*

+*************************************/

+/*WRAP MODE [31:30]*/

+#define DMA_WRAP_1	0x00000000

+#define DMA_WRAP_2	BIT30

+#define DMA_WRAP_4	BIT31

+#define DMA_WRAP_8	(BIT31|BIT30)

+#define DMA_WRQP_MASK	0xC0000000

+/*BUST[29:28]*/

+#define DMA_BURST_1	0x00000000

+#define DMA_BURST_4	BIT28

+#define DMA_BURST_8	BIT29

+#define DMA_BURST_MASK	0x30000000

+/*TRANSFER SIZE[[27:26]*/

+#define DMA_SIZE_8	0x00000000

+#define DMA_SIZE_16	BIT26

+#define DMA_SIZE_32	BIT27

+#define DMA_SIZE_MASK	0x0C000000

+/*/1/2 addr mode[25:24]*/

+#define DMA_WRAP_MODE	0x00000000

+#define DMA_INC_MODE	BIT24

+#define DMA_SG_MODE	BIT25

+#define DMA_UP_MEMREG_EN BIT15

+#define DMA_ADDR_MODE_MASK	0x03000000

+/*SW REQUEST ENABLE[23]*/

+#define DMA_SW_REQ	BIT23

+#define DMA_SW_REQ_MASK	0x00800000

+/*DMA 1/2 TRANS DIRECTION[22]*/

+#define DEVICE_TO_MEM	BIT22

+#define DEVICE_TO_MEM_MASK	0x00400000

+/*DMA REQ NUM[20:16]*/

+#define DMA_REQ_ID_SHIFT	16

+#define DMA_REQ_ID_MASK		0x000F8000

+

+/*DMA complete BIT*/

+#define DMA_P0_COMPLETE	BIT9	   /*0:complete 1:did't complete*/

+#define DMA_P1_COMPLETE	BIT8

+

+#define SYSTEM_DMA_RUN	BIT7

+#define DMA_RUN_MASK	0x00000080

+#define DMA_WAKE BIT6

+#define DMA_WAKE_MASK	0x00000040

+#define DMA_ACTIVE	BIT4

+#define DMA_ACTIVE_MASK	0x00000010

+#define DMA_USER_SET_MASK	0xFFFE0000

+

+/*DMA ERROR ID[3:0]*/

+#define DMA_EVT_ID_MASK	0x0000000F

+#define DMA_EVT_NO_STATUS	0

+#define DMA_EVT_REG	1

+#define DMA_EVT_FF_UNDERRUN	2

+#define DMA_EVT_FF_OVERRUN	3

+#define DMA_EVT_DESP_READ	4

+#define DMA_EVT_DESP_WRITE	5

+#define DMA_EVT_MR_READ		6

+#define DMA_EVT_MR_WRITE	7

+#define DMA_EVT_DATA_READ	8

+#define DMA_EVT_DATA_WRITE	9

+#define DMA_EVT_SUCCESS		15

+

+

+/*****************************************

+	DMA data transfer size

+******************************************/

+#define SIZE_1B             	0x00000001

+#define SIZE_2B             	0x00000002

+#define SIZE_4B             	0x00000004

+#define SIZE_8B             	0x00000008

+#define SIZE_16B           	0x00000010

+#define SIZE_32B            	0x00000020

+#define SIZE_64B            	0x00000040

+#define SIZE_128B           	0x00000080

+#define SIZE_256B           	0x00000100

+#define SIZE_512B           	0x00000200

+#define SIZE_1KB            	0x00000400

+#define SIZE_2KB            	0x00000800

+#define SIZE_4KB            	0x00001000

+#define SIZE_8KB            	0x00002000

+#define SIZE_16KB           	0x00004000

+#define SIZE_32KB           	0x00008000

+#define SIZE_64KB           	0x00010000

+#define SIZE_128KB          	0x00020000

+#define SIZE_256KB          	0x00040000

+#define SIZE_512KB          	0x00080000

+#define SIZE_1MB            	0x00100000

+#define SIZE_2MB            	0x00200000

+#define SIZE_4MB            	0x00400000

+#define SIZE_8MB            	0x00800000

+#define SIZE_16MB           	0x01000000

+#define SIZE_32MB           	0x02000000

+#define SIZE_64MB           	0x04000000

+#define SIZE_128MB          0x08000000

+#define SIZE_256MB          0x10000000

+#define SIZE_512MB          0x20000000

+#define SIZE_1GB            	0x40000000

+#define SIZE_2GB            	0x80000000

+#define TRAN_SIZE	SIZE_2KB

+

+/*****************************************

+	DMA descript setting

+******************************************/

+#define DMA_DES_END	BIT31

+#define DMA_FORMAT_DES1	BIT30

+#define DMA_INTEN_DES	BIT16

+#define DMA_DES0_SIZE 0x8	/*8 byte*/

+#define DMA_DES1_SIZE 0x10	/*16 byte*/

+/*************************************************

+*

+*	DMA Controller Register Set

+*

+**************************************************/

+

+struct DMA_MEM_REG_GROUP {

+	volatile unsigned long DMA_IF0RBR_CH;

+	volatile unsigned long DMA_IF0DAR_CH;

+	volatile unsigned long DMA_IF0BAR_CH;

+	volatile unsigned long DMA_IF0CPR_CH;

+	volatile unsigned long DMA_IF1RBR_CH;

+	volatile unsigned long DMA_IF1DAR_CH;

+	volatile unsigned long DMA_IF1BAR_CH;

+	volatile unsigned long DMA_IF1CPR_CH;

+};

+struct DMA_MEM_REG {

+	struct DMA_MEM_REG_GROUP MEM_REG_GROUP[DMA_CHANNELS];

+};

+

+struct DMA_REG {

+	volatile unsigned long RESERVED[0x10];/*0x00-0x3F*/

+	volatile unsigned long DMA_GCR; /*0x40-0x43*/

+	volatile unsigned long DMA_MRPR;/*0x44-0x47*/

+	volatile unsigned long DMA_IER; /*0x48-0x4B*/

+	volatile unsigned long DMA_ISR; /*0x4C-0x4F*/

+	volatile unsigned long DMA_TMR; /*0x50-0x53*/

+	volatile unsigned long RESERVED_1[0xB];/*0x54-0x7F*/

+	volatile unsigned long DMA_CCR_CH[0x10];/*0x80-0xBF*/

+	volatile unsigned long RESERVED_2[0x10];/*0xC0-0xFF*/

+};

+

+struct DMA_DES_FMT0 {

+	volatile unsigned long REQCNT;

+	volatile unsigned long DATAADDR;

+};

+struct DMA_DES_FMT1 {

+	volatile unsigned long REQCNT;

+	volatile unsigned long DATAADDR;

+	volatile unsigned long BRADDR;

+	volatile unsigned long RESERVED;

+

+};

+

+struct desp_stack{

+    unsigned int addr_base;

+    unsigned int length;

+    unsigned int cur_index;

+    unsigned int head_index;

+    unsigned int freedesp_num;

+    unsigned int mem_startaddr;

+    unsigned int mem_length;

+};

+

+struct DMA_DESCRIPT_ADDR {

+	volatile unsigned long DES_0;

+	volatile unsigned long DES_1_2;

+	struct desp_stack despstack_0;

+	struct desp_stack despstack_1_2;

+};

+/**************************************************

+*All possible devices a DMA channel can be attached to.

+***************************************************/

+enum dma_device {

+	SPI0_DMA_TX_REQ = 0 , /*spi0tx*/

+	SPI0_DMA_RX_REQ = 1 , /*spi0rx*/

+	SPI1_DMA_TX_REQ = 2 , /*spi1tx*/

+	SPI1_DMA_RX_REQ = 3 , /*spi1tx*/

+	SPI2_DMA_TX_REQ = 4 , /*spi2rx*/

+	SPI2_DMA_RX_REQ = 5 , /*spi2rx*/

+	UART_0_TX_DMA_REQ = 6,/* uart0*/

+	UART_0_RX_DMA_REQ = 7,/* uart0*/

+	UART_1_TX_DMA_REQ = 8,/* uart1*/

+	UART_1_RX_DMA_REQ = 9,/* uart1*/

+	UART_2_TX_DMA_REQ = 10,/* uart2*/

+	UART_2_RX_DMA_REQ = 11,/* uart2*/

+	UART_3_TX_DMA_REQ = 12,/* uart3*/

+	UART_3_RX_DMA_REQ = 13,/* uart3*/

+	I2S_TX_DMA_REQ = 14 ,/* i2s*/

+	I2S_RX_DMA_REQ = 15 ,/* i2s*/

+	UART_4_TX_DMA_REQ = 16,/* uart4*/

+	UART_4_RX_DMA_REQ = 17,/* uart4*/

+	AC97_PCM_TX_DMA_REQ = 18,/*AC97*/

+	AC97_PCM_RX_DMA_REQ = 19,/*AC97*/

+	AC97_MIC_DMA_REQ = 20, /*AC97 MIC*/

+	UART_5_TX_DMA_REQ = 29,/* uart5*/

+	UART_5_RX_DMA_REQ = 30,/* uart5*/

+	MEMORY_DMA_REQ = 32,/* memory*/

+	DEVICE_RESERVED = 33 /* reserved*/

+};

+

+/******************************************************************************

+* DMA channel structure.

+*******************************************************************************/

+struct dma_device_cfg{

+	enum dma_device	DeviceReqType;

+	unsigned long DefaultCCR;

+	unsigned long MIF0addr;

+	unsigned long MIF1addr;

+};

+

+struct DMA_INFO{

+	unsigned long  channel_no;       	/* channel no*/

+	struct DMA_REG *regs;           		/* points to appropriate DMA registers*/

+	struct DMA_MEM_REG *mem_regs;           /*points to DMA memory registers*/

+	const char *device_id;      		/* device name*/

+	//void (*callback)(void);		/* to call when buffers are done*/

+	enum dma_device device_no;    		/* device no*/

+	struct dma_device_cfg device_cfg;  	/* device cfg*/

+	int in_use;                 			/* Does someone own the channel*/

+	int descript_cnt;                 			/* count of queued buffers*/

+	struct DMA_DESCRIPT_ADDR DES_ADDR;

+};

+

+struct dma_state{

+	unsigned int request_chans;

+	struct DMA_REG *regs;

+};

+

+

+

+extern unsigned int dma_irq_mapping[] ;

+

+void init_dma(void);

+

+void disable_dma(void);

+

+void enable_dma(void);

+

+int request_dma(unsigned int *channel, const char *device_id, enum dma_device device);

+

+void clear_dma(unsigned int ch);

+

+void free_dma(unsigned int ch);

+

+int setup_dma(unsigned int ch, struct dma_device_cfg device_cfg);

+

+

+int dma_busy(unsigned int ch);

+

+int dma_complete(unsigned int ch);

+

+int start_dma(unsigned long ch, unsigned long dma_ptr1, unsigned long dma_ptr2, unsigned long size);

+

+void handle_dma_irq(unsigned long ch);

+

+/****************************************************

+

+*Function phototype in Dmaif.c

+

+*****************************************************/

+

+//void dma_initialization(IN int FunctionNumber);

+

+//void dma_startio(void);

+

+//void dma_diagio(struct diag *pdiag);

+

+//void free_dma_channels(void);

+

+void wake_dma_channel(unsigned int);

+

+//unsigned int dma_dump_regs(void);

+

+//unsigned int bus_size32_test(unsigned int);

+

+//unsigned int bus_size16_test(unsigned int);

+

+//unsigned int bus_size8_test(unsigned int);

+

+//unsigned int mix_des_test(unsigned int);

+

+//unsigned int wakeup_channel_test(unsigned int);

+

+//unsigned int all_channels_test(void);

+

+//unsigned int dma_fixed_priority_test(void);

+

+//unsigned int dma_rotating_priority_test(void);

+

+//unsigned int dma_channel_interrupt_test(int ch);

+

+//unsigned int bus_halfword_test(unsigned int);

+

+//unsigned int bus_32bit_byte_test(unsigned int);

+

+//unsigned int bus_16bit_byte_test(unsigned int);

+

+int prepare_dma_descript(unsigned int, unsigned int, unsigned int);

+

+int prepare_dma_long_descript(unsigned int start_descript, unsigned int branch_descript,

+	unsigned int start_addr, unsigned int size, unsigned int last_des);

+

+void add_descript(unsigned int, unsigned int, unsigned int, unsigned int);

+

+void init_descriptstack(unsigned int ch);

+void reset_descriptstack(unsigned int ch);

+void free_descriptstack(unsigned int ch);

+int set_descript(struct desp_stack * pdesp_stack, unsigned int start_addr, unsigned int size);

+int handle_transfer(unsigned long ch, unsigned long dma_ptr1, unsigned long dma_ptr2, unsigned long size);

+#endif  /* __DMA_H__ */

+

diff --git a/include/dtt.h b/include/dtt.h
new file mode 100755
index 0000000..a17aa67
--- /dev/null
+++ b/include/dtt.h
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen,  Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Digital Thermometers and Thermostats.
+ */
+#ifndef _DTT_H_
+#define _DTT_H_
+
+#if defined(CONFIG_DTT_LM75) || \
+    defined(CONFIG_DTT_DS1621) || \
+    defined(CONFIG_DTT_ADM1021)
+
+#define CONFIG_DTT				/* We have a DTT */
+
+#ifndef CONFIG_DTT_ADM1021
+#define DTT_COMMERCIAL_MAX_TEMP	70		/* 0 - +70 C */
+#define DTT_INDUSTRIAL_MAX_TEMP	85		/* -40 - +85 C */
+#define DTT_AUTOMOTIVE_MAX_TEMP	105		/* -40 - +105 C */
+#ifndef CFG_DTT_MAX_TEMP
+#define CFG_DTT_MAX_TEMP DTT_COMMERCIAL_MAX_TEMP
+#endif
+#ifndef CFG_DTT_HYSTERESIS
+#define CFG_DTT_HYSTERESIS	5		/* 5 C */
+#endif
+#endif /* CONFIG_DTT_ADM1021 */
+
+extern int dtt_init (void);
+extern int dtt_read(int sensor, int reg);
+extern int dtt_write(int sensor, int reg, int val);
+extern int dtt_get_temp(int sensor);
+#endif
+
+#if defined(CONFIG_DTT_LM75)
+#define DTT_READ_TEMP		0x0
+#define DTT_CONFIG		0x1
+#define DTT_TEMP_HYST		0x2
+#define DTT_TEMP_SET		0x3
+#endif
+
+#if defined(CONFIG_DTT_DS1621)
+#define DTT_READ_TEMP		0xAA
+#define DTT_READ_COUNTER	0xA8
+#define DTT_READ_SLOPE		0xA9
+#define DTT_WRITE_START_CONV	0xEE
+#define DTT_WRITE_STOP_CONV	0x22
+#define DTT_TEMP_HIGH		0xA1
+#define DTT_TEMP_LOW		0xA2
+#define DTT_CONFIG		0xAC
+#endif
+
+#if defined(CONFIG_DTT_ADM1021)
+#define DTT_READ_LOC_VALUE	0x00
+#define DTT_READ_REM_VALUE	0x01
+#define DTT_READ_STATUS		0x02
+#define DTT_READ_CONFIG		0x03
+#define DTT_READ_CONVRATE	0x04
+#define DTT_READ_LOC_HIGHLIM	0x05
+#define DTT_READ_LOC_LOWLIM	0x06
+#define DTT_READ_REM_HIGHLIM	0x07
+#define DTT_READ_REM_LOWLIM	0x08
+#define DTT_READ_DEVID		0xfe
+
+#define DTT_WRITE_CONFIG	0x09
+#define DTT_WRITE_CONVRATE	0x0a
+#define DTT_WRITE_LOC_HIGHLIM	0x0b
+#define DTT_WRITE_LOC_LOWLIM	0x0c
+#define DTT_WRITE_REM_HIGHLIM	0x0d
+#define DTT_WRITE_REM_LOWLIM	0x0e
+#define DTT_WRITE_ONESHOT	0x0f
+
+#define DTT_STATUS_BUSY		0x80	/* 1=ADC Converting */
+#define DTT_STATUS_LHIGH	0x40	/* 1=Local High Temp Limit Tripped */
+#define DTT_STATUS_LLOW		0x20	/* 1=Local Low Temp Limit Tripped */
+#define DTT_STATUS_RHIGH	0x10	/* 1=Remote High Temp Limit Tripped */
+#define DTT_STATUS_RLOW		0x08	/* 1=Remote Low Temp Limit Tripped */
+#define DTT_STATUS_OPEN		0x04	/* 1=Remote Sensor Open-Circuit */
+
+#define DTT_CONFIG_ALERT_MASKED	0x80	/* 0=ALERT Enabled, 1=ALERT Masked */
+#define DTT_CONFIG_STANDBY	0x40	/* 0=Run, 1=Standby */
+
+#define DTT_ADM1021_DEVID	0x41
+#endif
+
+#endif /* _DTT_H_ */
diff --git a/include/e500.h b/include/e500.h
new file mode 100755
index 0000000..8e3bf8c
--- /dev/null
+++ b/include/e500.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2003 Motorola,Inc.
+ * Xianghua Xiao(x.xiao@motorola.com)
+ */
+
+#ifndef	__E500_H__
+#define __E500_H__
+
+#ifndef __ASSEMBLY__
+
+typedef struct
+{
+  unsigned long freqProcessor;
+  unsigned long freqSystemBus;
+} MPC85xx_SYS_INFO;
+
+#endif  /* _ASMLANGUAGE */
+
+/* Motorola E500 core provides 16 TLB1 entries; they can be used for
+ * initial memory mapping like legacy BAT registers do. Usually we
+ * use four MAS registers(MAS0-3) to operate on TLB1 entries.
+ *
+ * While there are 16 Entries with variable Page Sizes in TLB1,
+ * there are also 256 Entries with fixed 4K pages in TLB0.
+ *
+ * We also need LAWs(Local Access Window) to associate a range of
+ * the local 32-bit address space with a particular target interface
+ * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM.
+ *
+ * We put TLB1/LAW code here because memory mapping is board-specific
+ * instead of cpu-specific.
+ *
+ * While these macros are all nominally for TLB1 by name, they can
+ * also be used for TLB0 as well.
+ */
+
+
+/*
+ * Convert addresses to Effective and Real Page Numbers.
+ * Grab the high 20-bits and shift 'em down, dropping the "byte offset".
+ */
+#define E500_TLB_EPN(addr)	(((addr) >> 12) & 0xfffff)
+#define E500_TLB_RPN(addr)	(((addr) >> 12) & 0xfffff)
+
+
+/* MAS0
+ * tlbsel(TLB Select):0,1
+ * esel(Entry Select): 0,1,2,...,15 for TLB1
+ * nv(Next victim):0,1
+ */
+#define TLB1_MAS0(tlbsel,esel,nv) \
+			((((tlbsel) << 28) & MAS0_TLBSEL)       |\
+			(((esel) << 16) & MAS0_ESEL )           |\
+			(nv) )
+
+
+/* MAS1
+ * v(TLB valid bit):0,1
+ * iprot(invalidate protect):0,1
+ * tid(translation identity):8bit to match process IDs
+ * ts(translation space,comparing with MSR[IS,DS]): 0,1
+ * tsize(translation size):1,2,...,9(4K,16K,64K,256K,1M,4M,16M,64M,256M)
+ */
+#define TLB1_MAS1(v,iprot,tid,ts,tsize) \
+			((((v) << 31) & MAS1_VALID)             |\
+			(((iprot) << 30) & MAS1_IPROT)          |\
+			(((tid) << 16) & MAS1_TID)              |\
+			(((ts) << 12) & MAS1_TS)                |\
+			(((tsize) << 8) & MAS1_TSIZE) )
+
+
+/* MAS2
+ * epn(effective page number):20bits
+ * sharen(Shared cache state):0,1
+ * x0,x1(implementation specific page attribute):0,1
+ * w,i,m,g,e(write-through,cache-inhibited,memory coherency,guarded,
+ *      endianness):0,1
+ */
+#define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \
+			((((epn) << 12) & MAS2_EPN)             |\
+			(((sharen) << 9) & MAS2_SHAREN)         |\
+			(((x0) << 6) & MAS2_X0)                 |\
+			(((x1) << 5) & MAS2_X1)                 |\
+			(((w) << 4) & MAS2_W)                   |\
+			(((i) << 3) & MAS2_I)                   |\
+			(((m) << 2) & MAS2_M)                   |\
+			(((g) << 1) & MAS2_G)                   |\
+			(e) )
+
+
+/* MAS3
+ * rpn(real page number):20bits
+ * u0-u3(user bits, useful for page table management in OS):0,1
+ * ux,sx,uw,sw,ur,sr(permission bits, user and supervisor read,
+ *      write,execute permission).
+ */
+#define TLB1_MAS3(rpn,u0,u1,u2,u3,ux,sx,uw,sw,ur,sr) \
+			((((rpn) << 12) & MAS3_RPN)             |\
+			(((u0) << 9) & MAS3_U0)                 |\
+			(((u1) << 8) & MAS3_U1)                 |\
+			(((u2) << 7) & MAS3_U2)                 |\
+			(((u3) << 6) & MAS3_U3)                 |\
+			(((ux) << 5) & MAS3_UX)                 |\
+			(((sx) << 4) & MAS3_SX)                 |\
+			(((uw) << 3) & MAS3_UW)                 |\
+			(((sw) << 2) & MAS3_SW)                 |\
+			(((ur) << 1) & MAS3_UR)                 |\
+			(sr) )
+
+
+#define RESET_VECTOR	0xfffffffc
+#define CACHELINE_MASK	(CFG_CACHELINE_SIZE - 1) /* Address mask for cache
+						     line aligned data. */
+
+#endif	/* __E500_H__ */
diff --git a/include/elf.h b/include/elf.h
new file mode 100755
index 0000000..d0febc5
--- /dev/null
+++ b/include/elf.h
@@ -0,0 +1,606 @@
+/*
+ * Copyright (c) 1995, 1996, 2001, 2002
+ * Erik Theisen.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This is the ELF ABI header file
+ * formerly known as "elf_abi.h".
+ */
+
+#ifndef _ELF_H
+#define _ELF_H
+
+#if defined(__BEOS__)	 || \
+    defined(__NetBSD__)  || \
+    defined(__FreeBSD__) || \
+    defined(__sun__)	 || \
+    defined(__APPLE__)
+#include <inttypes.h>
+#elif defined(__linux__) && defined(USE_HOSTCC)
+#include <stdint.h>
+#elif defined(__WIN32__)
+#include <unistd.h>
+typedef 	 unsigned char	 uint8_t;
+typedef 	 unsigned short  uint16_t;
+typedef 	 unsigned int	 uint32_t;
+#endif
+
+/*
+ *  This version doesn't work for 64-bit ABIs - Erik.
+ */
+
+/*
+ * These typedefs need to be handled better.
+ */
+typedef uint32_t	Elf32_Addr;	/* Unsigned program address */
+typedef uint32_t	Elf32_Off;	/* Unsigned file offset */
+typedef int32_t		Elf32_Sword;	/* Signed large integer */
+typedef uint32_t	Elf32_Word;	/* Unsigned large integer */
+typedef uint16_t	Elf32_Half;	/* Unsigned medium integer */
+
+/* e_ident[] identification indexes */
+#define EI_MAG0		0		/* file ID */
+#define EI_MAG1		1		/* file ID */
+#define EI_MAG2		2		/* file ID */
+#define EI_MAG3		3		/* file ID */
+#define EI_CLASS	4		/* file class */
+#define EI_DATA		5		/* data encoding */
+#define EI_VERSION	6		/* ELF header version */
+#define EI_OSABI	7		/* OS/ABI specific ELF extensions */
+#define EI_ABIVERSION	8		/* ABI target version */
+#define EI_PAD		9		/* start of pad bytes */
+#define EI_NIDENT	16		/* Size of e_ident[] */
+
+/* e_ident[] magic number */
+#define	ELFMAG0		0x7f		/* e_ident[EI_MAG0] */
+#define	ELFMAG1		'E'		/* e_ident[EI_MAG1] */
+#define	ELFMAG2		'L'		/* e_ident[EI_MAG2] */
+#define	ELFMAG3		'F'		/* e_ident[EI_MAG3] */
+#define	ELFMAG		"\177ELF"	/* magic */
+#define	SELFMAG		4		/* size of magic */
+
+/* e_ident[] file class */
+#define	ELFCLASSNONE	0		/* invalid */
+#define	ELFCLASS32	1		/* 32-bit objs */
+#define	ELFCLASS64	2		/* 64-bit objs */
+#define	ELFCLASSNUM	3		/* number of classes */
+
+/* e_ident[] data encoding */
+#define ELFDATANONE	0		/* invalid */
+#define ELFDATA2LSB	1		/* Little-Endian */
+#define ELFDATA2MSB	2		/* Big-Endian */
+#define ELFDATANUM	3		/* number of data encode defines */
+
+/* e_ident[] OS/ABI specific ELF extensions */
+#define ELFOSABI_NONE		0	/* No extension specified */
+#define ELFOSABI_HPUX		1	/* Hewlett-Packard HP-UX */
+#define ELFOSABI_NETBSD		2	/* NetBSD */
+#define ELFOSABI_LINUX		3	/* Linux */
+#define ELFOSABI_SOLARIS	6	/* Sun Solaris */
+#define ELFOSABI_AIX		7	/* AIX */
+#define ELFOSABI_IRIX		8	/* IRIX */
+#define ELFOSABI_FREEBSD	9	/* FreeBSD */
+#define ELFOSABI_TRU64		10	/* Compaq TRU64 UNIX */
+#define ELFOSABI_MODESTO	11	/* Novell Modesto */
+#define ELFOSABI_OPENBSD	12	/* OpenBSD */
+/* 64-255 Architecture-specific value range */
+
+/* e_ident[] ABI Version */
+#define ELFABIVERSION		0
+
+/* e_ident */
+#define IS_ELF(ehdr) ((ehdr).e_ident[EI_MAG0] == ELFMAG0 && \
+		      (ehdr).e_ident[EI_MAG1] == ELFMAG1 && \
+		      (ehdr).e_ident[EI_MAG2] == ELFMAG2 && \
+		      (ehdr).e_ident[EI_MAG3] == ELFMAG3)
+
+/* ELF Header */
+typedef struct elfhdr{
+	unsigned char	e_ident[EI_NIDENT]; /* ELF Identification */
+	Elf32_Half	e_type;		/* object file type */
+	Elf32_Half	e_machine;	/* machine */
+	Elf32_Word	e_version;	/* object file version */
+	Elf32_Addr	e_entry;	/* virtual entry point */
+	Elf32_Off	e_phoff;	/* program header table offset */
+	Elf32_Off	e_shoff;	/* section header table offset */
+	Elf32_Word	e_flags;	/* processor-specific flags */
+	Elf32_Half	e_ehsize;	/* ELF header size */
+	Elf32_Half	e_phentsize;	/* program header entry size */
+	Elf32_Half	e_phnum;	/* number of program header entries */
+	Elf32_Half	e_shentsize;	/* section header entry size */
+	Elf32_Half	e_shnum;	/* number of section header entries */
+	Elf32_Half	e_shstrndx;	/* section header table's "section
+					   header string table" entry offset */
+} Elf32_Ehdr;
+
+/* e_type */
+#define ET_NONE		0		/* No file type */
+#define ET_REL		1		/* relocatable file */
+#define ET_EXEC		2		/* executable file */
+#define ET_DYN		3		/* shared object file */
+#define ET_CORE		4		/* core file */
+#define ET_NUM		5		/* number of types */
+#define ET_LOOS		0xfe00		/* reserved range for operating */
+#define ET_HIOS		0xfeff		/*  system specific e_type */
+#define ET_LOPROC	0xff00		/* reserved range for processor */
+#define ET_HIPROC	0xffff		/*  specific e_type */
+
+/* e_machine */
+#define EM_NONE		0		/* No Machine */
+#define EM_M32		1		/* AT&T WE 32100 */
+#define EM_SPARC	2		/* SPARC */
+#define EM_386		3		/* Intel 80386 */
+#define EM_68K		4		/* Motorola 68000 */
+#define EM_88K		5		/* Motorola 88000 */
+#if 0
+#define EM_486		6		/* RESERVED - was Intel 80486 */
+#endif
+#define EM_860		7		/* Intel 80860 */
+#define EM_MIPS		8		/* MIPS R3000 Big-Endian only */
+#define EM_S370		9		/* IBM System/370 Processor */
+#define EM_MIPS_RS4_BE	10		/* MIPS R4000 Big-Endian */
+#if 0
+#define EM_SPARC64	11		/* RESERVED - was SPARC v9
+					     64-bit unoffical */
+#endif
+/* RESERVED 11-14 for future use */
+#define EM_PARISC	15		/* HPPA */
+/* RESERVED 16 for future use */
+#define EM_VPP500	17		/* Fujitsu VPP500 */
+#define EM_SPARC32PLUS	18		/* Enhanced instruction set SPARC */
+#define EM_960		19		/* Intel 80960 */
+#define EM_PPC		20		/* PowerPC */
+#define EM_PPC64	21		/* 64-bit PowerPC */
+#define EM_S390		22		/* IBM System/390 Processor */
+/* RESERVED 23-35 for future use */
+#define EM_V800		36		/* NEC V800 */
+#define EM_FR20		37		/* Fujitsu FR20 */
+#define EM_RH32		38		/* TRW RH-32 */
+#define EM_RCE		39		/* Motorola RCE */
+#define EM_ARM		40		/* Advanced Risc Machines ARM */
+#define EM_ALPHA	41		/* Digital Alpha */
+#define EM_SH		42		/* Hitachi SH */
+#define EM_SPARCV9	43		/* SPARC Version 9 */
+#define EM_TRICORE	44		/* Siemens TriCore embedded processor */
+#define EM_ARC		45		/* Argonaut RISC Core */
+#define EM_H8_300	46		/* Hitachi H8/300 */
+#define EM_H8_300H	47		/* Hitachi H8/300H */
+#define EM_H8S		48		/* Hitachi H8S */
+#define EM_H8_500	49		/* Hitachi H8/500 */
+#define EM_IA_64	50		/* Intel Merced */
+#define EM_MIPS_X	51		/* Stanford MIPS-X */
+#define EM_COLDFIRE	52		/* Motorola Coldfire */
+#define EM_68HC12	53		/* Motorola M68HC12 */
+#define EM_MMA		54		/* Fujitsu MMA Multimedia Accelerator*/
+#define EM_PCP		55		/* Siemens PCP */
+#define EM_NCPU		56		/* Sony nCPU embeeded RISC */
+#define EM_NDR1		57		/* Denso NDR1 microprocessor */
+#define EM_STARCORE	58		/* Motorola Start*Core processor */
+#define EM_ME16		59		/* Toyota ME16 processor */
+#define EM_ST100	60		/* STMicroelectronic ST100 processor */
+#define EM_TINYJ	61		/* Advanced Logic Corp. Tinyj emb.fam*/
+#define EM_X86_64	62		/* AMD x86-64 */
+#define EM_PDSP		63		/* Sony DSP Processor */
+/* RESERVED 64,65 for future use */
+#define EM_FX66		66		/* Siemens FX66 microcontroller */
+#define EM_ST9PLUS	67		/* STMicroelectronics ST9+ 8/16 mc */
+#define EM_ST7		68		/* STmicroelectronics ST7 8 bit mc */
+#define EM_68HC16	69		/* Motorola MC68HC16 microcontroller */
+#define EM_68HC11	70		/* Motorola MC68HC11 microcontroller */
+#define EM_68HC08	71		/* Motorola MC68HC08 microcontroller */
+#define EM_68HC05	72		/* Motorola MC68HC05 microcontroller */
+#define EM_SVX		73		/* Silicon Graphics SVx */
+#define EM_ST19		74		/* STMicroelectronics ST19 8 bit mc */
+#define EM_VAX		75		/* Digital VAX */
+#define EM_CHRIS	76		/* Axis Communications embedded proc. */
+#define EM_JAVELIN	77		/* Infineon Technologies emb. proc. */
+#define EM_FIREPATH	78		/* Element 14 64-bit DSP Processor */
+#define EM_ZSP		79		/* LSI Logic 16-bit DSP Processor */
+#define EM_MMIX		80		/* Donald Knuth's edu 64-bit proc. */
+#define EM_HUANY	81		/* Harvard University mach-indep objs */
+#define EM_PRISM	82		/* SiTera Prism */
+#define EM_AVR		83		/* Atmel AVR 8-bit microcontroller */
+#define EM_FR30		84		/* Fujitsu FR30 */
+#define EM_D10V		85		/* Mitsubishi DV10V */
+#define EM_D30V		86		/* Mitsubishi DV30V */
+#define EM_V850		87		/* NEC v850 */
+#define EM_M32R		88		/* Mitsubishi M32R */
+#define EM_MN10300	89		/* Matsushita MN10200 */
+#define EM_MN10200	90		/* Matsushita MN10200 */
+#define EM_PJ		91		/* picoJava */
+#define EM_NUM		92		/* number of machine types */
+
+/* Version */
+#define EV_NONE		0		/* Invalid */
+#define EV_CURRENT	1		/* Current */
+#define EV_NUM		2		/* number of versions */
+
+/* Section Header */
+typedef struct {
+	Elf32_Word	sh_name;	/* name - index into section header
+					   string table section */
+	Elf32_Word	sh_type;	/* type */
+	Elf32_Word	sh_flags;	/* flags */
+	Elf32_Addr	sh_addr;	/* address */
+	Elf32_Off	sh_offset;	/* file offset */
+	Elf32_Word	sh_size;	/* section size */
+	Elf32_Word	sh_link;	/* section header table index link */
+	Elf32_Word	sh_info;	/* extra information */
+	Elf32_Word	sh_addralign;	/* address alignment */
+	Elf32_Word	sh_entsize;	/* section entry size */
+} Elf32_Shdr;
+
+/* Special Section Indexes */
+#define SHN_UNDEF	0		/* undefined */
+#define SHN_LORESERVE	0xff00		/* lower bounds of reserved indexes */
+#define SHN_LOPROC	0xff00		/* reserved range for processor */
+#define SHN_HIPROC	0xff1f		/*   specific section indexes */
+#define SHN_LOOS	0xff20		/* reserved range for operating */
+#define SHN_HIOS	0xff3f		/*   specific semantics */
+#define SHN_ABS		0xfff1		/* absolute value */
+#define SHN_COMMON	0xfff2		/* common symbol */
+#define SHN_XINDEX	0xffff		/* Index is an extra table */
+#define SHN_HIRESERVE	0xffff		/* upper bounds of reserved indexes */
+
+/* sh_type */
+#define SHT_NULL	0		/* inactive */
+#define SHT_PROGBITS	1		/* program defined information */
+#define SHT_SYMTAB	2		/* symbol table section */
+#define SHT_STRTAB	3		/* string table section */
+#define SHT_RELA	4		/* relocation section with addends*/
+#define SHT_HASH	5		/* symbol hash table section */
+#define SHT_DYNAMIC	6		/* dynamic section */
+#define SHT_NOTE	7		/* note section */
+#define SHT_NOBITS	8		/* no space section */
+#define SHT_REL		9		/* relation section without addends */
+#define SHT_SHLIB	10		/* reserved - purpose unknown */
+#define SHT_DYNSYM	11		/* dynamic symbol table section */
+#define SHT_INIT_ARRAY	14		/* Array of constructors */
+#define SHT_FINI_ARRAY	15		/* Array of destructors */
+#define SHT_PREINIT_ARRAY 16		/* Array of pre-constructors */
+#define SHT_GROUP	17		/* Section group */
+#define SHT_SYMTAB_SHNDX 18		/* Extended section indeces */
+#define SHT_NUM		19		/* number of section types */
+#define SHT_LOOS	0x60000000	/* Start OS-specific */
+#define SHT_HIOS	0x6fffffff	/* End OS-specific */
+#define SHT_LOPROC	0x70000000	/* reserved range for processor */
+#define SHT_HIPROC	0x7fffffff	/*  specific section header types */
+#define SHT_LOUSER	0x80000000	/* reserved range for application */
+#define SHT_HIUSER	0xffffffff	/*  specific indexes */
+
+/* Section names */
+#define ELF_BSS         ".bss"		/* uninitialized data */
+#define ELF_COMMENT	".comment"	/* version control information */
+#define ELF_DATA        ".data"		/* initialized data */
+#define ELF_DATA1       ".data1"	/* initialized data */
+#define ELF_DEBUG       ".debug"	/* debug */
+#define ELF_DYNAMIC     ".dynamic"	/* dynamic linking information */
+#define ELF_DYNSTR      ".dynstr"	/* dynamic string table */
+#define ELF_DYNSYM      ".dynsym"	/* dynamic symbol table */
+#define ELF_FINI        ".fini"		/* termination code */
+#define ELF_FINI_ARRAY	".fini_array"	/* Array of destructors */
+#define ELF_GOT         ".got"		/* global offset table */
+#define ELF_HASH        ".hash"		/* symbol hash table */
+#define ELF_INIT        ".init"		/* initialization code */
+#define ELF_INIT_ARRAY	".init_array"	/* Array of constuctors */
+#define ELF_INTERP	".interp"	/* Pathname of program interpreter */
+#define ELF_LINE	".line"		/* Symbolic line numnber information */
+#define ELF_NOTE	".note"		/* Contains note section */
+#define ELF_PLT		".plt"		/* Procedure linkage table */
+#define ELF_PREINIT_ARRAY ".preinit_array" /* Array of pre-constructors */
+#define ELF_REL_DATA    ".rel.data"	/* relocation data */
+#define ELF_REL_FINI    ".rel.fini"	/* relocation termination code */
+#define ELF_REL_INIT    ".rel.init"	/* relocation initialization code */
+#define ELF_REL_DYN     ".rel.dyn"	/* relocaltion dynamic link info */
+#define ELF_REL_RODATA  ".rel.rodata"	/* relocation read-only data */
+#define ELF_REL_TEXT    ".rel.text"	/* relocation code */
+#define ELF_RODATA      ".rodata"	/* read-only data */
+#define ELF_RODATA1     ".rodata1"	/* read-only data */
+#define ELF_SHSTRTAB    ".shstrtab"	/* section header string table */
+#define ELF_STRTAB      ".strtab"	/* string table */
+#define ELF_SYMTAB      ".symtab"	/* symbol table */
+#define ELF_SYMTAB_SHNDX ".symtab_shndx"/* symbol table section index */
+#define ELF_TBSS	".tbss"		/* thread local uninit data */
+#define ELF_TDATA	".tdata"	/* thread local init data */
+#define ELF_TDATA1	".tdata1"	/* thread local init data */
+#define ELF_TEXT        ".text"		/* code */
+
+/* Section Attribute Flags - sh_flags */
+#define SHF_WRITE	0x1		/* Writable */
+#define SHF_ALLOC	0x2		/* occupies memory */
+#define SHF_EXECINSTR	0x4		/* executable */
+#define SHF_MERGE	0x10		/* Might be merged */
+#define SHF_STRINGS	0x20		/* Contains NULL terminated strings */
+#define SHF_INFO_LINK	0x40		/* sh_info contains SHT index */
+#define SHF_LINK_ORDER	0x80		/* Preserve order after combining*/
+#define SHF_OS_NONCONFORMING 0x100	/* Non-standard OS specific handling */
+#define SHF_GROUP	0x200		/* Member of section group */
+#define SHF_TLS		0x400		/* Thread local storage */
+#define SHF_MASKOS	0x0ff00000	/* OS specific */
+#define SHF_MASKPROC	0xf0000000	/* reserved bits for processor */
+					/*  specific section attributes */
+
+/* Section Group Flags */
+#define GRP_COMDAT	0x1		/* COMDAT group */
+#define GRP_MASKOS	0x0ff00000	/* Mask OS specific flags */
+#define GRP_MASKPROC	0xf0000000	/* Mask processor specific flags */
+
+/* Symbol Table Entry */
+typedef struct elf32_sym {
+	Elf32_Word	st_name;	/* name - index into string table */
+	Elf32_Addr	st_value;	/* symbol value */
+	Elf32_Word	st_size;	/* symbol size */
+	unsigned char	st_info;	/* type and binding */
+	unsigned char	st_other;	/* 0 - no defined meaning */
+	Elf32_Half	st_shndx;	/* section header index */
+} Elf32_Sym;
+
+/* Symbol table index */
+#define STN_UNDEF	0		/* undefined */
+
+/* Extract symbol info - st_info */
+#define ELF32_ST_BIND(x)	((x) >> 4)
+#define ELF32_ST_TYPE(x)	(((unsigned int) x) & 0xf)
+#define ELF32_ST_INFO(b,t)	(((b) << 4) + ((t) & 0xf))
+#define ELF32_ST_VISIBILITY(x)	((x) & 0x3)
+
+/* Symbol Binding - ELF32_ST_BIND - st_info */
+#define STB_LOCAL	0		/* Local symbol */
+#define STB_GLOBAL	1		/* Global symbol */
+#define STB_WEAK	2		/* like global - lower precedence */
+#define STB_NUM		3		/* number of symbol bindings */
+#define STB_LOOS	10		/* reserved range for operating */
+#define STB_HIOS	12		/*   system specific symbol bindings */
+#define STB_LOPROC	13		/* reserved range for processor */
+#define STB_HIPROC	15		/*  specific symbol bindings */
+
+/* Symbol type - ELF32_ST_TYPE - st_info */
+#define STT_NOTYPE	0		/* not specified */
+#define STT_OBJECT	1		/* data object */
+#define STT_FUNC	2		/* function */
+#define STT_SECTION	3		/* section */
+#define STT_FILE	4		/* file */
+#define STT_NUM		5		/* number of symbol types */
+#define STT_TLS		6		/* Thread local storage symbol */
+#define STT_LOOS	10		/* reserved range for operating */
+#define STT_HIOS	12		/*  system specific symbol types */
+#define STT_LOPROC	13		/* reserved range for processor */
+#define STT_HIPROC	15		/*  specific symbol types */
+
+/* Symbol visibility - ELF32_ST_VISIBILITY - st_other */
+#define STV_DEFAULT	0		/* Normal visibility rules */
+#define STV_INTERNAL	1		/* Processor specific hidden class */
+#define STV_HIDDEN	2		/* Symbol unavailable in other mods */
+#define STV_PROTECTED	3		/* Not preemptible, not exported */
+
+
+/* Relocation entry with implicit addend */
+typedef struct
+{
+	Elf32_Addr	r_offset;	/* offset of relocation */
+	Elf32_Word	r_info;		/* symbol table index and type */
+} Elf32_Rel;
+
+/* Relocation entry with explicit addend */
+typedef struct
+{
+	Elf32_Addr	r_offset;	/* offset of relocation */
+	Elf32_Word	r_info;		/* symbol table index and type */
+	Elf32_Sword	r_addend;
+} Elf32_Rela;
+
+/* Extract relocation info - r_info */
+#define ELF32_R_SYM(i)		((i) >> 8)
+#define ELF32_R_TYPE(i)		((unsigned char) (i))
+#define ELF32_R_INFO(s,t) 	(((s) << 8) + (unsigned char)(t))
+
+/* Program Header */
+typedef struct {
+	Elf32_Word	p_type;		/* segment type */
+	Elf32_Off	p_offset;	/* segment offset */
+	Elf32_Addr	p_vaddr;	/* virtual address of segment */
+	Elf32_Addr	p_paddr;	/* physical address - ignored? */
+	Elf32_Word	p_filesz;	/* number of bytes in file for seg. */
+	Elf32_Word	p_memsz;	/* number of bytes in mem. for seg. */
+	Elf32_Word	p_flags;	/* flags */
+	Elf32_Word	p_align;	/* memory alignment */
+} Elf32_Phdr;
+
+/* Segment types - p_type */
+#define PT_NULL		0		/* unused */
+#define PT_LOAD		1		/* loadable segment */
+#define PT_DYNAMIC	2		/* dynamic linking section */
+#define PT_INTERP	3		/* the RTLD */
+#define PT_NOTE		4		/* auxiliary information */
+#define PT_SHLIB	5		/* reserved - purpose undefined */
+#define PT_PHDR		6		/* program header */
+#define PT_TLS		7		/* Thread local storage template */
+#define PT_NUM		8		/* Number of segment types */
+#define PT_LOOS		0x60000000	/* reserved range for operating */
+#define PT_HIOS		0x6fffffff	/*   system specific segment types */
+#define PT_LOPROC	0x70000000	/* reserved range for processor */
+#define PT_HIPROC	0x7fffffff	/*  specific segment types */
+
+/* Segment flags - p_flags */
+#define PF_X		0x1		/* Executable */
+#define PF_W		0x2		/* Writable */
+#define PF_R		0x4		/* Readable */
+#define PF_MASKOS	0x0ff00000	/* OS specific segment flags */
+#define PF_MASKPROC	0xf0000000	/* reserved bits for processor */
+					/*  specific segment flags */
+/* Dynamic structure */
+typedef struct
+{
+	Elf32_Sword	d_tag;		/* controls meaning of d_val */
+	union
+	{
+		Elf32_Word	d_val;	/* Multiple meanings - see d_tag */
+		Elf32_Addr	d_ptr;	/* program virtual address */
+	} d_un;
+} Elf32_Dyn;
+
+extern Elf32_Dyn	_DYNAMIC[];
+
+/* Dynamic Array Tags - d_tag */
+#define DT_NULL		0		/* marks end of _DYNAMIC array */
+#define DT_NEEDED	1		/* string table offset of needed lib */
+#define DT_PLTRELSZ	2		/* size of relocation entries in PLT */
+#define DT_PLTGOT	3		/* address PLT/GOT */
+#define DT_HASH		4		/* address of symbol hash table */
+#define DT_STRTAB	5		/* address of string table */
+#define DT_SYMTAB	6		/* address of symbol table */
+#define DT_RELA		7		/* address of relocation table */
+#define DT_RELASZ	8		/* size of relocation table */
+#define DT_RELAENT	9		/* size of relocation entry */
+#define DT_STRSZ	10		/* size of string table */
+#define DT_SYMENT	11		/* size of symbol table entry */
+#define DT_INIT		12		/* address of initialization func. */
+#define DT_FINI		13		/* address of termination function */
+#define DT_SONAME	14		/* string table offset of shared obj */
+#define DT_RPATH	15		/* string table offset of library
+					   search path */
+#define DT_SYMBOLIC	16		/* start sym search in shared obj. */
+#define DT_REL		17		/* address of rel. tbl. w addends */
+#define DT_RELSZ	18		/* size of DT_REL relocation table */
+#define DT_RELENT	19		/* size of DT_REL relocation entry */
+#define DT_PLTREL	20		/* PLT referenced relocation entry */
+#define DT_DEBUG	21		/* bugger */
+#define DT_TEXTREL	22		/* Allow rel. mod. to unwritable seg */
+#define DT_JMPREL	23		/* add. of PLT's relocation entries */
+#define DT_BIND_NOW	24		/* Process relocations of object */
+#define DT_INIT_ARRAY	25		/* Array with addresses of init fct */
+#define DT_FINI_ARRAY	26		/* Array with addresses of fini fct */
+#define DT_INIT_ARRAYSZ	27		/* Size in bytes of DT_INIT_ARRAY */
+#define DT_FINI_ARRAYSZ	28		/* Size in bytes of DT_FINI_ARRAY */
+#define DT_RUNPATH	29		/* Library search path */
+#define DT_FLAGS	30		/* Flags for the object being loaded */
+#define DT_ENCODING	32		/* Start of encoded range */
+#define DT_PREINIT_ARRAY 32		/* Array with addresses of preinit fct*/
+#define DT_PREINIT_ARRAYSZ 33		/* size in bytes of DT_PREINIT_ARRAY */
+#define DT_NUM		34		/* Number used. */
+#define DT_LOOS		0x60000000	/* reserved range for OS */
+#define DT_HIOS		0x6fffffff	/*   specific dynamic array tags */
+#define DT_LOPROC	0x70000000	/* reserved range for processor */
+#define DT_HIPROC	0x7fffffff	/*  specific dynamic array tags */
+
+/* Dynamic Tag Flags - d_un.d_val */
+#define DF_ORIGIN	0x01		/* Object may use DF_ORIGIN */
+#define DF_SYMBOLIC	0x02		/* Symbol resolutions starts here */
+#define DF_TEXTREL	0x04		/* Object contains text relocations */
+#define DF_BIND_NOW	0x08		/* No lazy binding for this object */
+#define DF_STATIC_TLS	0x10		/* Static thread local storage */
+
+/* Standard ELF hashing function */
+unsigned long elf_hash(const unsigned char *name);
+
+#define ELF_TARG_VER	1	/* The ver for which this code is intended */
+
+/*
+ * XXX - PowerPC defines really don't belong in here,
+ * but we'll put them in for simplicity.
+ */
+
+/* Values for Elf32/64_Ehdr.e_flags.  */
+#define EF_PPC_EMB              0x80000000      /* PowerPC embedded flag */
+
+/* Cygnus local bits below */
+#define EF_PPC_RELOCATABLE      0x00010000      /* PowerPC -mrelocatable flag*/
+#define EF_PPC_RELOCATABLE_LIB  0x00008000      /* PowerPC -mrelocatable-lib
+						   flag */
+
+/* PowerPC relocations defined by the ABIs */
+#define R_PPC_NONE              0
+#define R_PPC_ADDR32            1       /* 32bit absolute address */
+#define R_PPC_ADDR24            2       /* 26bit address, 2 bits ignored.  */
+#define R_PPC_ADDR16            3       /* 16bit absolute address */
+#define R_PPC_ADDR16_LO         4       /* lower 16bit of absolute address */
+#define R_PPC_ADDR16_HI         5       /* high 16bit of absolute address */
+#define R_PPC_ADDR16_HA         6       /* adjusted high 16bit */
+#define R_PPC_ADDR14            7       /* 16bit address, 2 bits ignored */
+#define R_PPC_ADDR14_BRTAKEN    8
+#define R_PPC_ADDR14_BRNTAKEN   9
+#define R_PPC_REL24             10      /* PC relative 26 bit */
+#define R_PPC_REL14             11      /* PC relative 16 bit */
+#define R_PPC_REL14_BRTAKEN     12
+#define R_PPC_REL14_BRNTAKEN    13
+#define R_PPC_GOT16             14
+#define R_PPC_GOT16_LO          15
+#define R_PPC_GOT16_HI          16
+#define R_PPC_GOT16_HA          17
+#define R_PPC_PLTREL24          18
+#define R_PPC_COPY              19
+#define R_PPC_GLOB_DAT          20
+#define R_PPC_JMP_SLOT          21
+#define R_PPC_RELATIVE          22
+#define R_PPC_LOCAL24PC         23
+#define R_PPC_UADDR32           24
+#define R_PPC_UADDR16           25
+#define R_PPC_REL32             26
+#define R_PPC_PLT32             27
+#define R_PPC_PLTREL32          28
+#define R_PPC_PLT16_LO          29
+#define R_PPC_PLT16_HI          30
+#define R_PPC_PLT16_HA          31
+#define R_PPC_SDAREL16          32
+#define R_PPC_SECTOFF           33
+#define R_PPC_SECTOFF_LO        34
+#define R_PPC_SECTOFF_HI        35
+#define R_PPC_SECTOFF_HA        36
+/* Keep this the last entry.  */
+#define R_PPC_NUM               37
+
+/* The remaining relocs are from the Embedded ELF ABI, and are not
+   in the SVR4 ELF ABI.  */
+#define R_PPC_EMB_NADDR32       101
+#define R_PPC_EMB_NADDR16       102
+#define R_PPC_EMB_NADDR16_LO    103
+#define R_PPC_EMB_NADDR16_HI    104
+#define R_PPC_EMB_NADDR16_HA    105
+#define R_PPC_EMB_SDAI16        106
+#define R_PPC_EMB_SDA2I16       107
+#define R_PPC_EMB_SDA2REL       108
+#define R_PPC_EMB_SDA21         109     /* 16 bit offset in SDA */
+#define R_PPC_EMB_MRKREF        110
+#define R_PPC_EMB_RELSEC16      111
+#define R_PPC_EMB_RELST_LO      112
+#define R_PPC_EMB_RELST_HI      113
+#define R_PPC_EMB_RELST_HA      114
+#define R_PPC_EMB_BIT_FLD       115
+#define R_PPC_EMB_RELSDA        116     /* 16 bit relative offset in SDA */
+
+/* Diab tool relocations.  */
+#define R_PPC_DIAB_SDA21_LO     180     /* like EMB_SDA21, but lower 16 bit */
+#define R_PPC_DIAB_SDA21_HI     181     /* like EMB_SDA21, but high 16 bit */
+#define R_PPC_DIAB_SDA21_HA     182     /* like EMB_SDA21, adjusted high 16 */
+#define R_PPC_DIAB_RELSDA_LO    183     /* like EMB_RELSDA, but lower 16 bit */
+#define R_PPC_DIAB_RELSDA_HI    184     /* like EMB_RELSDA, but high 16 bit */
+#define R_PPC_DIAB_RELSDA_HA    185     /* like EMB_RELSDA, adjusted high 16 */
+
+/* This is a phony reloc to handle any old fashioned TOC16 references
+   that may still be in object files.  */
+#define R_PPC_TOC16             255
+
+#endif /* _ELF_H */
diff --git a/include/environment.h b/include/environment.h
new file mode 100755
index 0000000..7ce7cba
--- /dev/null
+++ b/include/environment.h
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ENVIRONMENT_H_
+#define _ENVIRONMENT_H_	1
+
+/*======rockpzhang======*/
+extern struct hsearch_data env_htab;
+/*======*/
+
+
+/**************************************************************************
+ *
+ * The "environment" is stored as a list of '\0' terminated
+ * "name=value" strings. The end of the list is marked by a double
+ * '\0'. New entries are always added at the end. Deleting an entry
+ * shifts the remaining entries to the front. Replacing an entry is a
+ * combination of deleting the old value and adding the new one.
+ *
+ * The environment is preceeded by a 32 bit CRC over the data part.
+ *
+ **************************************************************************
+ */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_OFFSET
+#  define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
+# endif
+# if !defined(CFG_ENV_ADDR_REDUND) && defined(CFG_ENV_OFFSET_REDUND)
+#  define CFG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + CFG_ENV_OFFSET_REDUND)
+# endif
+# if defined(CFG_ENV_SECT_SIZE) || defined(CFG_ENV_SIZE)
+#  ifndef  CFG_ENV_SECT_SIZE
+#   define CFG_ENV_SECT_SIZE	CFG_ENV_SIZE
+#  endif
+#  ifndef  CFG_ENV_SIZE
+#   define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+#  endif
+# else
+#  error "Both CFG_ENV_SECT_SIZE and CFG_ENV_SIZE undefined"
+# endif
+# if defined(CFG_ENV_ADDR_REDUND) && !defined(CFG_ENV_SIZE_REDUND)
+#  define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
+# endif
+# if (CFG_ENV_ADDR >= CFG_MONITOR_BASE) && \
+     (CFG_ENV_ADDR+CFG_ENV_SIZE) <= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#  define ENV_IS_EMBEDDED	1
+# endif
+# if defined(CFG_ENV_ADDR_REDUND) || defined(CFG_ENV_OFFSET_REDUND)
+#  define CFG_REDUNDAND_ENVIRONMENT	1
+# endif
+#endif	/* CFG_ENV_IS_IN_FLASH */
+
+
+#ifdef CFG_REDUNDAND_ENVIRONMENT
+# define ENV_HEADER_SIZE	(sizeof(unsigned long) + 1)
+#else
+# define ENV_HEADER_SIZE	(sizeof(unsigned long))
+#endif
+
+
+#define ENV_SIZE (CFG_ENV_SIZE - ENV_HEADER_SIZE)
+
+typedef	struct environment_s {
+	unsigned long	crc;		/* CRC32 over data bytes	*/
+#ifdef CFG_REDUNDAND_ENVIRONMENT
+	unsigned char	flags;		/* active/obsolete flags	*/
+#endif
+	unsigned char	data[ENV_SIZE]; /* Environment data		*/
+} env_t;
+
+#endif	/* _ENVIRONMENT_H_ */
diff --git a/include/errno.h b/include/errno.h
new file mode 100755
index 0000000..1edf25e
--- /dev/null
+++ b/include/errno.h
@@ -0,0 +1,9 @@
+#ifndef _ERRNO_H
+
+#include <asm-arm/errno.h>
+
+extern int errno;
+
+#define __set_errno(val) do { errno = val; } while (0)
+
+#endif /* _ERRNO_H */
diff --git a/include/exports.h b/include/exports.h
new file mode 100755
index 0000000..9695455
--- /dev/null
+++ b/include/exports.h
@@ -0,0 +1,46 @@
+#ifndef __EXPORTS_H__
+#define __EXPORTS_H__
+
+#ifndef __ASSEMBLY__
+
+#include <common.h>
+
+/* These are declarations of exported functions available in C code */
+unsigned long get_version(void);
+int  getc(void);
+int  tstc(void);
+void putc(const char);
+void puts(const char*);
+int printf(const char* fmt, ...);
+void install_hdlr(int, interrupt_handler_t*, void*);
+void free_hdlr(int);
+void *malloc(size_t);
+void free(void*);
+void udelay(unsigned long);
+unsigned long get_timer(unsigned long);
+void vprintf(const char *, va_list);
+void do_reset (void);
+#if (CONFIG_COMMANDS & CFG_CMD_I2C)
+int i2c_write (uchar, uint, int , uchar* , int);
+int i2c_read (uchar, uint, int , uchar* , int);
+#endif	/* CFG_CMD_I2C */
+
+void app_startup(char **);
+
+#endif    /* ifndef __ASSEMBLY__ */
+
+enum {
+#define EXPORT_FUNC(x) XF_ ## x ,
+#include <_exports.h>
+#undef EXPORT_FUNC
+
+	XF_MAX
+};
+
+#define XF_VERSION	2
+
+#if defined(CONFIG_I386)
+extern gd_t *global_data;
+#endif
+
+#endif	/* __EXPORTS_H__ */
diff --git a/include/ext2fs.h b/include/ext2fs.h
new file mode 100755
index 0000000..de935b0
--- /dev/null
+++ b/include/ext2fs.h
@@ -0,0 +1,81 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 2000, 2001  Free Software Foundation, Inc.
+ *
+ *  (C) Copyright 2003 Sysgo Real-Time Solutions, AG <www.elinos.com>
+ *  Pavel Bartusek <pba@sysgo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* An implementation for the Ext2FS filesystem ported from GRUB.
+ * Some parts of this code (mainly the structures and defines) are
+ * from the original ext2 fs code, as found in the linux kernel.
+ */
+
+
+#define SECTOR_SIZE		0x200
+#define SECTOR_BITS		9
+
+/* Error codes */
+typedef enum
+{
+  ERR_NONE = 0,
+  ERR_BAD_FILENAME,
+  ERR_BAD_FILETYPE,
+  ERR_BAD_GZIP_DATA,
+  ERR_BAD_GZIP_HEADER,
+  ERR_BAD_PART_TABLE,
+  ERR_BAD_VERSION,
+  ERR_BELOW_1MB,
+  ERR_BOOT_COMMAND,
+  ERR_BOOT_FAILURE,
+  ERR_BOOT_FEATURES,
+  ERR_DEV_FORMAT,
+  ERR_DEV_VALUES,
+  ERR_EXEC_FORMAT,
+  ERR_FILELENGTH,
+  ERR_FILE_NOT_FOUND,
+  ERR_FSYS_CORRUPT,
+  ERR_FSYS_MOUNT,
+  ERR_GEOM,
+  ERR_NEED_LX_KERNEL,
+  ERR_NEED_MB_KERNEL,
+  ERR_NO_DISK,
+  ERR_NO_PART,
+  ERR_NUMBER_PARSING,
+  ERR_OUTSIDE_PART,
+  ERR_READ,
+  ERR_SYMLINK_LOOP,
+  ERR_UNRECOGNIZED,
+  ERR_WONT_FIT,
+  ERR_WRITE,
+  ERR_BAD_ARGUMENT,
+  ERR_UNALIGNED,
+  ERR_PRIVILEGED,
+  ERR_DEV_NEED_INIT,
+  ERR_NO_DISK_SPACE,
+  ERR_NUMBER_OVERFLOW,
+
+  MAX_ERR_NUM
+} ext2fs_error_t;
+
+
+extern int ext2fs_set_blk_dev(block_dev_desc_t *rbdd, int part);
+extern int ext2fs_ls (char *dirname);
+extern int ext2fs_open (char *filename);
+extern int ext2fs_read (char *buf, unsigned len);
+extern int ext2fs_mount (unsigned part_length);
+extern int ext2fs_close(void);
diff --git a/include/ext4fs.h b/include/ext4fs.h
new file mode 100755
index 0000000..dad2d87
--- /dev/null
+++ b/include/ext4fs.h
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * Ext4 Extent data structures are taken from  original ext4 fs code
+ * as found in the linux kernel.
+ *
+ * Copyright (c) 2003-2006, Cluster File Systems, Inc, info@clusterfs.com
+ * Written by Alex Tomas <alex@clusterfs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __EXT4__
+#define __EXT4__
+#include <ext_common.h>
+
+#define EXT4_EXTENTS_FL		0x00080000 /* Inode uses extents */
+#define EXT4_EXT_MAGIC			0xf30a
+#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM	0x0010
+#define EXT4_FEATURE_INCOMPAT_EXTENTS	0x0040
+#define EXT4_INDIRECT_BLOCKS		12
+
+#define EXT4_BG_INODE_UNINIT		0x0001
+#define EXT4_BG_BLOCK_UNINIT		0x0002
+#define EXT4_BG_INODE_ZEROED		0x0004
+
+/*
+ * ext4_inode has i_block array (60 bytes total).
+ * The first 12 bytes store ext4_extent_header;
+ * the remainder stores an array of ext4_extent.
+ */
+
+/*
+ * This is the extent on-disk structure.
+ * It's used at the bottom of the tree.
+ */
+struct ext4_extent {
+	__le32	ee_block;	/* first logical block extent covers */
+	__le16	ee_len;		/* number of blocks covered by extent */
+	__le16	ee_start_hi;	/* high 16 bits of physical block */
+	__le32	ee_start_lo;	/* low 32 bits of physical block */
+};
+
+/*
+ * This is index on-disk structure.
+ * It's used at all the levels except the bottom.
+ */
+struct ext4_extent_idx {
+	__le32	ei_block;	/* index covers logical blocks from 'block' */
+	__le32	ei_leaf_lo;	/* pointer to the physical block of the next *
+				 * level. leaf or next index could be there */
+	__le16	ei_leaf_hi;	/* high 16 bits of physical block */
+	__u16	ei_unused;
+};
+
+/* Each block (leaves and indexes), even inode-stored has header. */
+struct ext4_extent_header {
+	__le16	eh_magic;	/* probably will support different formats */
+	__le16	eh_entries;	/* number of valid entries */
+	__le16	eh_max;		/* capacity of store in entries */
+	__le16	eh_depth;	/* has tree real underlying blocks? */
+	__le32	eh_generation;	/* generation of the tree */
+};
+
+struct ext_filesystem {
+	/* Total Sector of partition */
+	uint32_t total_sect;//uint64_t
+	/* Block size  of partition */
+	uint32_t blksz;
+	/* Inode size of partition */
+	uint32_t inodesz;
+	/* Sectors per Block */
+	uint32_t sect_perblk;
+	/* Group Descriptor Block Number */
+	uint32_t gdtable_blkno;
+	/* Total block groups of partition */
+	uint32_t no_blkgrp;
+	/* No of blocks required for bgdtable */
+	uint32_t no_blk_pergdt;
+	/* Superblock */
+	struct ext2_sblock *sb;
+	/* Block group descritpor table */
+	struct ext2_block_group *bgd;
+	char *gdtable;
+
+	/* Block Bitmap Related */
+	unsigned char **blk_bmaps;
+	long int curr_blkno;
+	uint16_t first_pass_bbmap;
+
+	/* Inode Bitmap Related */
+	unsigned char **inode_bmaps;
+	int curr_inode_no;
+	uint16_t first_pass_ibmap;
+
+	/* Journal Related */
+
+	/* Block Device Descriptor */
+	block_dev_desc_t *dev_desc;
+};
+
+extern struct ext2_data *ext4fs_root;
+extern struct ext2fs_node *ext4fs_file;
+
+extern struct ext2_inode *g_parent_inode;
+extern int gd_index;
+extern int gindex;
+
+int ext4fs_init(void);
+void ext4fs_deinit(void);
+int ext4fs_filename_check(char *filename);
+int ext4fs_write(const char *fname, unsigned char *buffer,
+				unsigned long sizebytes);
+
+struct ext_filesystem *get_fs(void);
+int ext4fs_open(const char *filename);
+int ext4fs_read(char *buf, unsigned len);
+int ext4fs_mount(unsigned part_length);
+void ext4fs_close(void);
+int ext4fs_ls(const char *dirname);
+void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot);
+int ext4fs_devread(int sector, int byte_offset, int byte_len, char *buf);
+void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
+long int read_allocated_block(struct ext2_inode *inode, int fileblock);
+#endif
diff --git a/include/ext_common.h b/include/ext_common.h
new file mode 100755
index 0000000..0e96de8
--- /dev/null
+++ b/include/ext_common.h
@@ -0,0 +1,202 @@
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * Data structures and headers for ext4 support have been taken from
+ * ext2 ls load support in Uboot
+ *
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * based on code from grub2 fs/ext2.c and fs/fshelp.c by
+ * GRUB  --  GRand Unified Bootloader
+ * Copyright (C) 2003, 2004  Free Software Foundation, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __EXT_COMMON__
+#define __EXT_COMMON__
+#include <command.h>
+#define SECTOR_SIZE		0x200
+#define SECTOR_BITS		9
+
+/* Magic value used to identify an ext2 filesystem.  */
+#define	EXT2_MAGIC			0xEF53
+/* Amount of indirect blocks in an inode.  */
+#define INDIRECT_BLOCKS			12
+/* Maximum lenght of a pathname.  */
+#define EXT2_PATH_MAX				4096
+/* Maximum nesting of symlinks, used to prevent a loop.  */
+#define	EXT2_MAX_SYMLINKCNT		8
+
+/* Filetype used in directory entry.  */
+#define	FILETYPE_UNKNOWN		0
+#define	FILETYPE_REG			1
+#define	FILETYPE_DIRECTORY		2
+#define	FILETYPE_SYMLINK		7
+
+/* Filetype information as used in inodes.  */
+#define FILETYPE_INO_MASK		0170000
+#define FILETYPE_INO_REG		0100000
+#define FILETYPE_INO_DIRECTORY		0040000
+#define FILETYPE_INO_SYMLINK		0120000
+#define EXT2_ROOT_INO			2 /* Root inode */
+
+/* Bits used as offset in sector */
+#define DISK_SECTOR_BITS		9
+/* The size of an ext2 block in bytes.  */
+#define EXT2_BLOCK_SIZE(data)	   (1 << LOG2_BLOCK_SIZE(data))
+
+/* Log2 size of ext2 block in 512 blocks.  */
+#define LOG2_EXT2_BLOCK_SIZE(data) (__le32_to_cpu \
+				(data->sblock.log2_block_size) + 1)
+
+/* Log2 size of ext2 block in bytes.  */
+#define LOG2_BLOCK_SIZE(data)	   (__le32_to_cpu \
+		(data->sblock.log2_block_size) + 10)
+#define INODE_SIZE_FILESYSTEM(data)	(__le32_to_cpu \
+			(data->sblock.inode_size))
+
+#define EXT2_FT_DIR	2
+#define SUCCESS	1
+
+/* Macro-instructions used to manage several block sizes  */
+#define EXT2_MIN_BLOCK_LOG_SIZE	10 /* 1024 */
+#define EXT2_MAX_BLOCK_LOG_SIZE	16 /* 65536 */
+#define EXT2_MIN_BLOCK_SIZE		(1 << EXT2_MIN_BLOCK_LOG_SIZE)
+#define EXT2_MAX_BLOCK_SIZE		(1 << EXT2_MAX_BLOCK_LOG_SIZE)
+
+/* The ext2 superblock.  */
+struct ext2_sblock {
+	uint32_t total_inodes;
+	uint32_t total_blocks;
+	uint32_t reserved_blocks;
+	uint32_t free_blocks;
+	uint32_t free_inodes;
+	uint32_t first_data_block;
+	uint32_t log2_block_size;
+	uint32_t log2_fragment_size;
+	uint32_t blocks_per_group;
+	uint32_t fragments_per_group;
+	uint32_t inodes_per_group;
+	uint32_t mtime;
+	uint32_t utime;
+	uint16_t mnt_count;
+	uint16_t max_mnt_count;
+	uint16_t magic;
+	uint16_t fs_state;
+	uint16_t error_handling;
+	uint16_t minor_revision_level;
+	uint32_t lastcheck;
+	uint32_t checkinterval;
+	uint32_t creator_os;
+	uint32_t revision_level;
+	uint16_t uid_reserved;
+	uint16_t gid_reserved;
+	uint32_t first_inode;
+	uint16_t inode_size;
+	uint16_t block_group_number;
+	uint32_t feature_compatibility;
+	uint32_t feature_incompat;
+	uint32_t feature_ro_compat;
+	uint32_t unique_id[4];
+	char volume_name[16];
+	char last_mounted_on[64];
+	uint32_t compression_info;
+};
+
+//group descriptor struct
+struct ext2_block_group {
+	__u32 block_id;	/* Blocks bitmap block */
+	__u32 inode_id;	/* Inodes bitmap block */
+	__u32 inode_table_id;	/* Inodes table block */
+	__u16 free_blocks;	/* Free blocks count */
+	__u16 free_inodes;	/* Free inodes count */
+	__u16 used_dir_cnt;	/* Directories count */
+	__u16 bg_flags;
+	__u32 bg_reserved[2];
+	__u16 bg_itable_unused; /* Unused inodes count */
+	__u16 bg_checksum;	/* crc16(s_uuid+grouo_num+group_desc)*/
+};
+
+/* The ext2 inode. */
+struct ext2_inode {
+	uint16_t mode;
+	uint16_t uid;
+	uint32_t size;
+	uint32_t atime;
+	uint32_t ctime;
+	uint32_t mtime;
+	uint32_t dtime;
+	uint16_t gid;
+	uint16_t nlinks;
+	uint32_t blockcnt;	/* Blocks of 512 bytes!! */
+	uint32_t flags;
+	uint32_t osd1;
+	union {
+		struct datablocks {
+			uint32_t dir_blocks[INDIRECT_BLOCKS];
+			uint32_t indir_block;
+			uint32_t double_indir_block;
+			uint32_t triple_indir_block;
+		} blocks;
+		char symlink[60];
+	} b;
+	uint32_t version;
+	uint32_t acl;
+	uint32_t dir_acl;
+	uint32_t fragment_addr;
+	uint32_t osd2[3];
+};
+
+/* The header of an ext2 directory entry. */
+struct ext2_dirent {
+	uint32_t inode;
+	uint16_t direntlen;
+	uint8_t namelen;
+	uint8_t filetype;
+};
+
+struct ext2fs_node {
+	struct ext2_data *data;
+	struct ext2_inode inode;
+	int ino;
+	int inode_read;
+};
+
+/* Information about a "mounted" ext2 filesystem. */
+struct ext2_data {
+	struct ext2_sblock sblock;
+	struct ext2_inode *inode;
+	struct ext2fs_node diropen;
+};
+
+extern unsigned long part_offset;
+
+int do_ext2ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_ext2load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc,
+					char *const argv[]);
+int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc,
+				char *const argv[]);
+int do_ext_load(cmd_tbl_t *cmdtp, int flag, int argc,
+					char *const argv[]);
+int do_ext_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+#endif
diff --git a/include/fastboot.h b/include/fastboot.h
new file mode 100755
index 0000000..596f777
--- /dev/null
+++ b/include/fastboot.h
@@ -0,0 +1,411 @@
+/*
+ * (C) Copyright 2008 - 2009
+ * Windriver, <www.windriver.com>
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * The logical naming of flash comes from the Android project
+ * Thse structures and functions that look like fastboot_flash_*
+ * They come from bootloader/legacy/include/boot/flash.h
+ *
+ * The boot_img_hdr structure and associated magic numbers also
+ * come from the Android project.  They are from
+ * system/core/mkbootimg/bootimg.h
+ *
+ * Here are their copyrights
+ *
+ * Copyright (C) 2008 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#ifndef FASTBOOT_H
+#define FASTBOOT_H
+
+#include <common.h>
+#include <command.h>
+
+/* This is the interface file between the common cmd_fastboot.c and
+   the board specific support.
+
+   To use this interface, define CONFIG_FASTBOOT in your board config file.
+   An example is include/configs/omap3430labrador.h
+   ...
+   #define CONFIG_FASTBOOT	        1    / * Using fastboot interface * /
+   ...
+
+   An example of the board specific spupport for omap3 is found at
+   cpu/omap3/fastboot.c
+
+*/
+
+/* From fastboot client.. */
+#define FASTBOOT_INTERFACE_CLASS     0xff
+#define FASTBOOT_INTERFACE_SUB_CLASS 0x42
+#define FASTBOOT_INTERFACE_PROTOCOL  0x03
+
+#define FASTBOOT_VERSION "0.5"
+
+/* The fastboot client uses a value of 2048 for the
+   page size of it boot.img file format.
+   Reset this in your board config file as needed. */
+#ifndef CONFIG_FASTBOOT_MKBOOTIMAGE_PAGE_SIZE
+#define CONFIG_FASTBOOT_MKBOOTIMAGE_PAGE_SIZE 2048
+#endif
+
+/* Fastboot bulk packet sizes */
+#define	CONFIG_USBD_FASTBOOT_BULK_PKTSIZE_HS	512
+#define	CONFIG_USBD_FASTBOOT_BULK_PKTSIZE_FS	64
+
+/* Flags */
+#define	FASTBOOT_FLAG_RESPONSE	1
+#define	FASTBOOT_FLAG_DOWNLOAD	1
+
+/* To change design of memory handling (SD/MMC, NAND) faster, if required */
+
+//#define FASTBOOT_PORT_WMT_NAND_FLASHING  0  //Charles
+//#define FASTBOOT_PORT_WMT_EMMC_FLASHING  1  //Charles
+
+/* To activate-deactivate fastboot upload command (not part of OmapZoom) */
+// #define	FASTBOOT_UPLOAD
+//typedef enum { NAND=0, EMMC=1} storage_medium_type;
+#define NAND 0
+#define EMMC 1
+
+#define FASTBOOT_RESPONSE_BUF_SZ 64
+
+struct cmd_fastboot_interface{
+
+	/* A getvar string for the product name
+	   It can have a maximum of 60 characters
+
+	   Set by board	*/
+	char *product_name;
+
+	/* A getvar string for the serial number
+	   It can have a maximum of 60 characters
+
+	   Set by board */
+	char *serial_no;
+
+	/* Nand block size
+	   Supports the write option WRITE_NEXT_GOOD_BLOCK
+
+	   Set by board */
+	unsigned int nand_block_size;
+
+	/* Nand oob size
+	   Set by board */
+	unsigned int nand_oob_size;
+
+	/* Transfer buffer, for handling flash updates
+	   Should be multiple of the nand_block_size
+	   Care should be take so it does not overrun bootloader memory
+	   Controlled by the configure variable CONFIG_FASTBOOT_TRANSFER_BUFFER
+
+	   Set by board */
+	unsigned char *transfer_buffer;
+
+	/* How big is the transfer buffer
+	   Controlled by the configure variable
+	   CONFIG_FASTBOOT_TRANSFER_BUFFER_SIZE
+
+	   Set by board	*/
+	unsigned int transfer_buffer_size;
+
+	/* Download size, if download has to be done. This can be checked to find
+		whether next packet is a command or a data */
+	unsigned int d_size;
+
+	/* Data downloaded so far */
+	unsigned int d_bytes;
+
+	/* Upload size, if download has to be done */
+	unsigned int u_size;
+
+	/* Data uploaded so far */
+	unsigned int u_bytes;
+
+	/* XXX: what should be the size, 64 or 65 ? */
+	//char response[65];
+	char response[FASTBOOT_RESPONSE_BUF_SZ+1];
+
+	/* Indicate response to be sent, data to be recieved */
+	unsigned int flag;
+
+	/* configuration status  */
+	unsigned int configured;
+
+//#ifdef	FASTBOOT_PORT_WMT_NAND_FLASHING
+	unsigned int download_bytes_unpadded;
+//#endif
+
+	unsigned int exit;
+	//storage_medium_type storage_medium;
+	unsigned char storage_medium;
+};
+
+/* Android-style flash naming */
+typedef struct fastboot_ptentry fastboot_ptentry;
+
+/* flash partitions are defined in terms of blocks
+** (flash erase units)
+*/
+struct fastboot_ptentry{
+
+	/* The logical name for this partition, null terminated */
+	char name[16];
+	/* The start wrt the nand part, must be multiple of nand block size */
+	__u64 start;
+	/* The length of the partition, must be multiple of nand block size */
+	__u64 length;
+	/* Controls the details of how operations are done on the partition
+	   See the FASTBOOT_PTENTRY_FLAGS_*'s defined below */
+	unsigned int flags;
+};
+
+typedef struct system_entry system_entry;
+/*define for system image*/
+struct system_entry{
+
+	char name[16];
+	unsigned int image_start;
+	unsigned int image_size;
+	unsigned int sig_start;
+	unsigned int sig_length;
+	unsigned int flash_start;
+	unsigned int flash_end;
+	unsigned int flags;
+};
+
+
+/* Lower byte shows if the read/write/erase operation in
+   repeated.  The base address is incremented.
+   Either 0 or 1 is ok for a default */
+
+#define	FASTBOOT_PTENTRY_FLAGS_REPEAT_MASK(n)	(n & 0x0f)
+#define	FASTBOOT_PTENTRY_FLAGS_REPEAT_4		0x00000004
+
+/* Writes happen a block at a time.
+   If the write fails, go to next block
+   NEXT_GOOD_BLOCK and CONTIGOUS_BLOCK can not both be set */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_NEXT_GOOD_BLOCK  0x00000010
+
+/* Find a contiguous block big enough for a the whole file
+   NEXT_GOOD_BLOCK and CONTIGOUS_BLOCK can not both be set */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_CONTIGUOUS_BLOCK 0x00000020
+
+/* Sets the ECC to software before writing
+   HW and SW ECC should not both be set. */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_SW_ECC           0x00000040
+
+/* Sets the ECC to hardware before writing
+   HW and SW ECC should not both be set. */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC           0x00000080
+
+/* Sets the ECC to hardware before writing
+   HW and SW ECC should not both be set. */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_HW_BCH4_ECC      0x00000100
+
+/* Sets the ECC to hardware before writing
+   HW and SW ECC should not both be set. */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_HW_BCH8_ECC      0x00000200
+
+/* Sets the ECC to hardware before writing
+   HW and SW ECC should not both be set. */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_HW_BCH16_ECC     0x00000400
+
+/* Write the file with write.i */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_I                0x00000800
+
+/* Write the file with write.jffs2 */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_JFFS2            0x00001000
+
+/* Write the file as a series of variable/value pairs
+   using the setenv and saveenv commands */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_ENV              0x00002000
+
+/* Status values */
+#define FASTBOOT_OK			0
+#define FASTBOOT_ERROR			-1
+#define FASTBOOT_DISCONNECT		1
+#define FASTBOOT_INACTIVE		2
+
+/* Android bootimage file format */
+#define FASTBOOT_BOOT_MAGIC            "ANDROID!"
+#define FASTBOOT_BOOT_MAGIC_SIZE       8
+#define FASTBOOT_BOOT_NAME_SIZE        16
+#define FASTBOOT_BOOT_ARGS_SIZE        512
+
+struct fastboot_boot_img_hdr {
+	unsigned char magic[FASTBOOT_BOOT_MAGIC_SIZE];
+
+	unsigned kernel_size;  /* size in bytes */
+	unsigned kernel_addr;  /* physical load addr */
+
+	unsigned ramdisk_size; /* size in bytes */
+	unsigned ramdisk_addr; /* physical load addr */
+
+	unsigned second_size;  /* size in bytes */
+	unsigned second_addr;  /* physical load addr */
+
+	unsigned tags_addr;    /* physical addr for kernel tags */
+	unsigned page_size;    /* flash page size we assume */
+	unsigned unused[2];    /* future expansion: should be 0 */
+
+	unsigned char name[FASTBOOT_BOOT_NAME_SIZE]; /* asciiz product name */
+
+	unsigned char cmdline[FASTBOOT_BOOT_ARGS_SIZE];
+
+	unsigned id[8]; /* timestamp / checksum / sha1 / etc */
+};
+
+#ifdef	CONFIG_CMD_FASTBOOT
+/* A board specific test if u-boot should go into the fastboot command
+   ahead of the bootcmd
+   Returns 0 to continue with normal u-boot flow
+   Returns 1 to execute fastboot */
+extern int fastboot_preboot(void);
+
+/* Initizes the board specific fastboot
+   Returns 0 on success
+   Returns 1 on failure */
+extern int fastboot_init(struct cmd_fastboot_interface *interface);
+
+/* Cleans up the board specific fastboot */
+extern void fastboot_shutdown(void);
+
+/*
+ * Handles board specific usb protocol exchanges
+ * Returns 0 on success
+ * Returns 1 on disconnects, break out of loop
+ * Returns 2 if no USB activity detected
+ * Returns -1 on failure, unhandled usb requests and other error conditions
+*/
+extern int fastboot_poll(void);
+
+/* Is this high speed (2.0) or full speed (1.1) ?
+   Returns 0 on full speed
+   Returns 1 on high speed */
+extern int fastboot_is_highspeed(void);
+
+/* Return the size of the fifo */
+extern int fastboot_fifo_size(void);
+
+/* Send a status reply to the client app
+   buffer does not have to be null terminated.
+   buffer_size must be not be larger than what is returned by
+   fastboot_fifo_size
+   Returns 0 on success
+   Returns 1 on failure */
+extern int fastboot_tx_status(const char *buffer, unsigned int buffer_size);
+
+/*
+ * Send some data to the client app
+ * buffer does not have to be null terminated.
+ * buffer_size can be larger than what is returned by
+ * fastboot_fifo_size
+ * Returns number of bytes written
+ */
+extern int fastboot_tx(unsigned char *buffer, unsigned int buffer_size);
+
+/* A board specific variable handler.
+   The size of the buffers is governed by the fastboot spec.
+   rx_buffer is at most 57 bytes
+   tx_buffer is at most 60 bytes
+   Returns 0 on success
+   Returns 1 on failure */
+extern int fastboot_getvar(const char *rx_buffer, char *tx_buffer);
+
+/* The Android-style flash handling */
+
+/* tools to populate and query the partition table */
+extern void fastboot_flash_reset_ptn(void);
+
+extern void fastboot_flash_add_ptn(fastboot_ptentry *ptn);
+extern fastboot_ptentry *fastboot_flash_find_ptn(const char *name);
+extern fastboot_ptentry *fastboot_flash_get_ptn(unsigned n);
+extern unsigned int fastboot_flash_get_ptn_count(void);
+extern void fastboot_flash_dump_ptn(void);
+
+extern int fastboot_flash_init(void);
+extern int fastboot_flash_erase(fastboot_ptentry *ptn);
+extern int fastboot_flash_read_ext(fastboot_ptentry *ptn,
+				   unsigned extra_per_page, unsigned offset,
+				   void *data, unsigned bytes);
+#define fastboot_flash_read(ptn, offset, data, bytes) \
+  flash_read_ext(ptn, 0, offset, data, bytes)
+extern int fastboot_flash_write(fastboot_ptentry *ptn, unsigned extra_per_page,
+				const void *data, unsigned bytes);
+int parse_fb_param(char *name);
+struct fb_operation_t {
+	unsigned char enable;
+	unsigned char device;
+	unsigned char controller;	
+	unsigned char part_type;
+};
+
+
+#else
+
+/* Stubs for when CONFIG_FASTBOOT is not defined */
+#define fastboot_preboot() 0
+#define fastboot_init(a) 1
+#define fastboot_shutdown()
+#define fastboot_poll() 1
+#define fastboot_is_highspeed() 0
+#define fastboot_fifo_size() 0
+#define fastboot_tx_status(a, b) 1
+#define fastboot_getvar(a, b) 1
+#define fastboot_tx(a, b) 1
+
+#define fastboot_flash_add_ptn(a)
+#define fastboot_flash_find_ptn(a) NULL
+#define fastboot_flash_get_ptn(a) NULL
+#define fastboot_flash_get_ptn_count() 0
+#define fastboot_flash_dump_ptn()
+#define fastboot_flash_init()
+#define fastboot_flash_erase(a) 1
+#define fastboot_flash_read_ext(a, b, c, d, e) 0
+#define fastboot_flash_read(a, b, c, d, e) 0
+#define fastboot_flash_write(a, b, c, d) 0
+
+#endif /* CONFIG_FASTBOOT */
+#endif /* FASTBOOT_H */
diff --git a/include/fat.h b/include/fat.h
new file mode 100755
index 0000000..6b54288
--- /dev/null
+++ b/include/fat.h
@@ -0,0 +1,324 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+/*
+ * R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg
+ *
+ * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6
+ * 2003-03-10 - kharris@nexus-tech.net - ported to u-boot
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _FAT_H_
+#define _FAT_H_
+
+#include <asm/byteorder.h>
+
+#define CONFIG_SUPPORT_VFAT
+
+#define VFAT_MAXLEN_BYTES	256 /* Maximum LFN buffer in bytes */
+#define VFAT_MAXSEQ		9   /* Up to 9 of 13 2-byte UTF-16 entries */
+#define PREFETCH_BLOCKS		2
+
+#define MAX_CLUSTSIZE	65536
+#define DIRENTSPERBLOCK	(mydata->sect_size / sizeof(dir_entry))
+#define DIRENTSPERCLUST	((mydata->clust_size * mydata->sect_size) / \
+			 sizeof(dir_entry))
+
+#define FATBUFBLOCKS	6
+#define FATBUFSIZE	(mydata->sect_size * FATBUFBLOCKS)
+#define FAT12BUFSIZE	((FATBUFSIZE*2)/3)
+#define FAT16BUFSIZE	(FATBUFSIZE/2)
+#define FAT32BUFSIZE	(FATBUFSIZE/4)
+
+
+/* Filesystem identifiers */
+#define FAT12_SIGN	"FAT12   "
+#define FAT16_SIGN	"FAT16   "
+#define FAT32_SIGN	"FAT32   "
+#define SIGNLEN		8
+
+/* File attributes */
+#define ATTR_RO	1
+#define ATTR_HIDDEN	2
+#define ATTR_SYS	4
+#define ATTR_VOLUME	8
+#define ATTR_DIR	16
+#define ATTR_ARCH	32
+
+#define ATTR_VFAT	(ATTR_RO | ATTR_HIDDEN | ATTR_SYS | ATTR_VOLUME)
+
+#define DELETED_FLAG	((char)0xe5) /* Marks deleted files when in name[0] */
+#define aRING		0x05	     /* Used as special character in name[0] */
+
+/*
+ * Indicates that the entry is the last long entry in a set of long
+ * dir entries
+ */
+#define LAST_LONG_ENTRY_MASK	0x40
+
+/* Flags telling whether we should read a file or list a directory */
+#define LS_NO		0
+#define LS_YES		1
+#define LS_DIR		1
+#define LS_ROOT		2
+
+#define ISDIRDELIM(c)	((c) == '/' || (c) == '\\')
+
+#define FSTYPE_NONE	(-1)
+
+#if defined(__linux__) && defined(__KERNEL__)
+#define FAT2CPU16	le16_to_cpu
+#define FAT2CPU32	le32_to_cpu
+#else
+#if __LITTLE_ENDIAN
+#define FAT2CPU16(x)	(x)
+#define FAT2CPU32(x)	(x)
+#else
+#define FAT2CPU16(x)	((((x) & 0x00ff) << 8) | (((x) & 0xff00) >> 8))
+#define FAT2CPU32(x)	((((x) & 0x000000ff) << 24)  |	\
+			 (((x) & 0x0000ff00) << 8)  |	\
+			 (((x) & 0x00ff0000) >> 8)  |	\
+			 (((x) & 0xff000000) >> 24))
+#endif
+#endif
+
+#define TOLOWER(c)	if((c) >= 'A' && (c) <= 'Z'){(c)+=('a' - 'A');}
+#define TOUPPER(c)	if ((c) >= 'a' && (c) <= 'z') \
+				(c) -= ('a' - 'A');
+#define START(dent)	(FAT2CPU16((dent)->start) \
+			+ (mydata->fatsize != 32 ? 0 : \
+			  (FAT2CPU16((dent)->starthi) << 16)))
+#define CHECK_CLUST(x, fatsize) ((x) <= 1 || \
+				(x) >= ((fatsize) != 32 ? 0xfff0 : 0xffffff0))
+
+
+#define STORE_LE(field, value) \
+do { \
+	if (sizeof(field) == 4) \
+		field = cpu_to_le32(value); \
+	else if (sizeof(field) == 2) \
+		field = cpu_to_le16(value); \
+	else if (sizeof(field) == 1) \
+		field = (value); \
+	else {\
+		printf("STORE_LE error\n"); \
+		return -1;  }\
+} while (0)
+
+typedef struct fat32_fsinfo {
+	uint32_t signature1;		 /* 0x52,0x52,0x41,0x61, "RRaA" */
+	uint32_t reserved1[128 - 8];
+	uint32_t signature2;		 /* 0x72,0x72,0x61,0x41, "rrAa" */
+	uint32_t free_clusters; 	 /* free cluster count.  -1 if unknown */
+	uint32_t next_cluster;		 /* most recently allocated cluster */
+	uint32_t reserved2[3];
+	uint16_t reserved3; 		 /* 1fc */
+	uint16_t boot_sign; 		 /* 1fe */
+} fat32_fsinfo;
+
+
+typedef struct boot_sector {
+	__u8	ignored[3];	/* Bootstrap code */
+	char	system_id[8];	/* Name of fs */
+	__u8	sector_size[2];	/* Bytes/sector */
+	__u8	cluster_size;	/* Sectors/cluster */
+	__u16	reserved;	/* Number of reserved sectors */
+	__u8	fats;		/* Number of FATs */
+	__u8	dir_entries[2];	/* Number of root directory entries */
+	__u8	sectors[2];	/* Number of sectors */
+	__u8	media;		/* Media code */
+	__u16	fat_length;	/* Sectors/FAT */
+	__u16	secs_track;	/* Sectors/track */
+	__u16	heads;		/* Number of heads */
+	__u32	hidden;		/* Number of hidden sectors */
+	__u32	total_sect;	/* Number of sectors (if sectors == 0) */
+
+	/* FAT32 only */
+	__u32	fat32_length;	/* Sectors/FAT */
+	__u16	flags;		/* Bit 8: fat mirroring, low 4: active fat */
+	__u8	version[2];	/* Filesystem version */
+	__u32	root_cluster;	/* First cluster in root directory */
+	__u16	info_sector;	/* Filesystem info sector */
+	__u16	backup_boot;	/* Backup boot sector */
+	__u16	reserved2[6];	/* Unused */
+} boot_sector;
+
+typedef struct boot_sector32 {
+	__u8	ignored[3];	/* Bootstrap code */
+	char	system_id[8];	/* Name of fs */
+	__u8	sector_size[2];	/* Bytes/sector */
+	__u8	cluster_size;	/* Sectors/cluster */
+	__u16	reserved;	/* Number of reserved sectors */
+	__u8	fats;		/* Number of FATs */
+	__u8	dir_entries[2];	/* Number of root directory entries */
+	__u8	sectors[2];	/* Number of sectors */
+	__u8	media;		/* Media code */
+	__u16	fat_length;	/* Sectors/FAT */
+	__u16	secs_track;	/* Sectors/track */
+	__u16	heads;		/* Number of heads */
+	__u32	hidden;		/* Number of hidden sectors */
+	__u32	total_sect;	/* Number of sectors (if sectors == 0) */
+
+	/* FAT32 only */
+	__u32	fat32_length;	/* Sectors/FAT */
+	__u16	flags;		/* Bit 8: fat mirroring, low 4: active fat */
+	__u8	version[2];	/* Filesystem version */
+	__u32	root_cluster;	/* First cluster in root directory */
+	__u16	info_sector;	/* Filesystem info sector */
+	__u16	backup_boot;	/* Backup boot sector */
+	__u16	reserved2[6];	/* Unused */
+
+	
+	__u8    drive_number;
+	__u8    NTreserved;
+	__u8    boot_signature;
+	__u8   	volumeID[4];
+	__u8    volumelabel[11];
+	__u16    filesystype[4];
+} boot_sector32;
+
+typedef struct boot_sector16or12 {
+	__u8	ignored[3];	/* Bootstrap code */
+	char	system_id[8];	/* Name of fs */
+	__u8	sector_size[2];	/* Bytes/sector */
+	__u8	cluster_size;	/* Sectors/cluster */
+	__u16	reserved;	/* Number of reserved sectors */
+	__u8	fats;		/* Number of FATs */
+	__u8	dir_entries[2];	/* Number of root directory entries */
+	__u8	sectors[2];	/* Number of sectors */
+	__u8	media;		/* Media code */
+	__u16	fat_length;	/* Sectors/FAT */
+	__u16	secs_track;	/* Sectors/track */
+	__u16	heads;		/* Number of heads */
+	__u32	hidden;		/* Number of hidden sectors */
+	__u32	total_sect;	/* Number of sectors (if sectors == 0) */
+
+	__u8    drive_number;
+	__u8    NTreserved;
+	__u8    boot_signature;
+	__u8   volumeID[4];
+	__u8    volumelabel[11];
+	__u16    filesystype[4];
+
+} boot_sector16or12;
+
+
+typedef struct volume_info
+{
+	__u8 drive_number;	/* BIOS drive number */
+	__u8 reserved;		/* Unused */
+	__u8 ext_boot_sign;	/* 0x29 if fields below exist (DOS 3.3+) */
+	__u8 volume_id[4];	/* Volume ID number */
+	char volume_label[11];	/* Volume label */
+	char fs_type[8];	/* Typically FAT12, FAT16, or FAT32 */
+	/* Boot code comes next, all but 2 bytes to fill up sector */
+	/* Boot sign comes last, 2 bytes */
+} volume_info;
+
+typedef struct dir_entry {
+	char	name[8],ext[3];	/* Name and extension */
+	__u8	attr;		/* Attribute bits */
+	__u8	lcase;		/* Case for base and extension */
+	__u8	ctime_ms;	/* Creation time, milliseconds */
+	__u16	ctime;		/* Creation time */
+	__u16	cdate;		/* Creation date */
+	__u16	adate;		/* Last access date */
+	__u16	starthi;	/* High 16 bits of cluster in FAT32 */
+	__u16	time,date,start;/* Time, date and first cluster */
+	__u32	size;		/* File size in bytes */
+} dir_entry;
+
+typedef struct dir_slot {
+	__u8	id;		/* Sequence number for slot */
+	__u8	name0_4[10];	/* First 5 characters in name */
+	__u8	attr;		/* Attribute byte */
+	__u8	reserved;	/* Unused */
+	__u8	alias_checksum;/* Checksum for 8.3 alias */
+	__u8	name5_10[12];	/* 6 more characters in name */
+	__u16	start;		/* Unused */
+	__u8	name11_12[4];	/* Last 2 characters in name */
+} dir_slot;
+
+/*
+ * Private filesystem parameters
+ *
+ * Note: FAT buffer has to be 32 bit aligned
+ * (see FAT32 accesses)
+ */
+typedef struct {
+	__u8	*fatbuf;	/* Current FAT buffer */
+	int	fatsize;	/* Size of FAT in bits */
+	__u32	fatlength;	/* Length of FAT in sectors */
+	__u16	fat_sect;	/* Starting sector of the FAT */
+	__u32	rootdir_sect;	/* Start sector of root directory */
+	__u16	sect_size;	/* Size of sectors in bytes */
+	__u16	clust_size;	/* Size of clusters in sectors */
+	int	data_begin;	/* The sector of the first cluster, can be negative */
+	int	fatbufnum;	/* Used by get_fatent, init to -1 */
+} fsdata;
+
+typedef int	(file_detectfs_func)(void);
+typedef int	(file_ls_func)(const char *dir);
+typedef long	(file_read_func)(const char *filename, void *buffer,
+				 unsigned long maxsize);
+
+struct filesystem {
+	file_detectfs_func	*detect;
+	file_ls_func		*ls;
+	file_read_func		*read;
+	const char		name[12];
+};
+
+/* FAT tables */
+file_detectfs_func	file_fat_detectfs;
+file_ls_func		file_fat_ls;
+file_read_func		file_fat_read;
+
+/* Currently this doesn't check if the dir exists or is valid... */
+int file_cd(const char *path);
+int file_fat_detectfs(void);
+int file_fat_ls(const char *dir);
+long file_fat_read_at(const char *filename, unsigned long pos, void *buffer,
+		      unsigned long maxsize);
+long file_fat_read(const char *filename, void *buffer, unsigned long maxsize);
+const char *file_getfsname(int idx);
+int fat_register_device(block_dev_desc_t *dev_desc, int part_no);
+int fatpre_register_device(block_dev_desc_t * dev_desc, int part_no);
+int file_fat_write(const char *filename, void *buffer, unsigned long maxsize);
+int format_fat32(void);
+int format_fat16(void);
+int format_fat12(void);
+#endif /* _FAT_H_ */
+
diff --git a/include/fdc.h b/include/fdc.h
new file mode 100755
index 0000000..b66f202
--- /dev/null
+++ b/include/fdc.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2002
+ * Stäubli Faverges - <www.staubli.com>
+ * Pierre AUBERT  p.aubert@staubli.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FDC_H_
+#define _FDC_H_
+
+/* Functions prototype                                                       */
+int fdc_fdos_init (int drive);
+int fdc_fdos_seek (int where);
+int fdc_fdos_read (void *buffer, int len);
+
+int dos_open(char *name);
+int dos_read (ulong addr);
+int dos_dir (void);
+
+#endif
diff --git a/include/flash.h b/include/flash.h
new file mode 100755
index 0000000..45713f0
--- /dev/null
+++ b/include/flash.h
@@ -0,0 +1,485 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify it under the
+ * terms of the GNU General Public License as published by the Free Software Foundation,
+ * either version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * WonderMedia Technologies, Inc.
+ * 10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ */
+
+#ifndef _FLASH_H_
+#define _FLASH_H_
+
+#ifndef CFG_NO_FLASH
+/*-----------------------------------------------------------------------
+ * FLASH Info: contains chip specific data, per FLASH bank
+ */
+
+typedef struct {
+	ulong	size;           /* total bank size in bytes	*/
+	ushort	sector_count;	/* number of erase units    */
+	ulong	flash_id;       /* combined device & manufacturer code	*/
+	ulong	start[CFG_MAX_FLASH_SECT];   /* physical sector start addresses */
+	uchar	protect[CFG_MAX_FLASH_SECT]; /* sector protection status	*/
+#ifdef CFG_FLASH_CFI
+	uchar	 portwidth;         /* the width of the port         */
+	uchar	 chipwidth;         /* the width of the chip         */
+	ushort buffer_size;       /* # of bytes in write buffer    */
+	ulong	 erase_blk_tout;    /* maximum block erase timeout   */
+	ulong	 write_tout;        /* maximum write timeout         */
+	ulong	 buffer_write_tout; /* maximum buffer write timeout  */
+	ushort vendor;            /* the primary vendor id         */
+	ushort cmd_reset;         /* Vendor specific reset command */
+	ushort interface;         /* used for x8/x16 adjustments   */
+#endif
+} flash_info_t;
+
+/*
+ * Values for the width of the port
+ */
+#define FLASH_CFI_8BIT		0x01
+#define FLASH_CFI_16BIT		0x02
+#define FLASH_CFI_32BIT		0x04
+#define FLASH_CFI_64BIT		0x08
+/*
+ * Values for the width of the chip
+ */
+#define FLASH_CFI_BY8   0x01
+#define FLASH_CFI_BY16  0x02
+#define FLASH_CFI_BY32  0x04
+#define FLASH_CFI_BY64  0x08
+/* convert between bit value and numeric value */
+#define CFI_FLASH_SHIFT_WIDTH	3
+/*
+ * Values for the flash device interface
+ */
+#define FLASH_CFI_X8     0x00
+#define FLASH_CFI_X16    0x01
+#define FLASH_CFI_X8X16  0x02
+
+/* convert between bit value and numeric value */
+#define CFI_FLASH_SHIFT_WIDTH	3
+/* Prototypes */
+
+extern unsigned long flash_init(void);
+extern void flash_print_info(flash_info_t *);
+extern int flash_erase(flash_info_t *, int, int);
+extern int flash_sect_erase(ulong addr_first, ulong addr_last);
+extern int flash_sect_protect(int flag, ulong addr_first, ulong addr_last);
+
+/* common/flash.c */
+extern void flash_protect(int flag, ulong from, ulong to, flash_info_t *info);
+extern int flash_write(char *, ulong, ulong);
+extern flash_info_t *addr2info(ulong);
+extern int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+
+/* board/?/flash.c */
+#if defined(CFG_FLASH_PROTECTION)
+extern int flash_real_protect(flash_info_t *info, long sector, int prot);
+extern void flash_read_user_serial(flash_info_t *info, void * buffer, int offset, int len);
+extern void flash_read_factory_serial(flash_info_t *info, void * buffer, int offset, int len);
+#endif	/* CFG_FLASH_PROTECTION */
+
+/*-----------------------------------------------------------------------
+ * return codes from flash_write():
+ */
+#define ERR_OK				0
+#define ERR_TIMOUT			1
+#define ERR_NOT_ERASED			2
+#define ERR_PROTECTED			4
+#define ERR_INVAL			8
+#define ERR_ALIGN			16
+#define ERR_UNKNOWN_FLASH_VENDOR	32
+#define ERR_UNKNOWN_FLASH_TYPE		64
+#define ERR_PROG_ERROR			128
+
+/*-----------------------------------------------------------------------
+ * Protection Flags for flash_protect():
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/*-----------------------------------------------------------------------
+ * Device IDs
+ */
+
+#define AMD_MANUFACT	 0x00010001	/* AMD	   manuf. ID in D23..D16, D7..D0 */
+#define FUJ_MANUFACT	 0x00040004	/* FUJITSU manuf. ID in D23..D16, D7..D0 */
+#define ATM_MANUFACT	 0x001F001F	/* ATMEL */
+#define STM_MANUFACT	 0x00200020	/* STM (Thomson) manuf. ID in D23.. -"- */
+#define SST_MANUFACT	 0x00BF00BF	/* SST	   manuf. ID in D23..D16, D7..D0 */
+#define MT_MANUFACT	   0x00890089	/* MT	   manuf. ID in D23..D16, D7..D0 */
+#define INTEL_MANUFACT 0x00890089	/* INTEL   manuf. ID in D23..D16, D7..D0 */
+#define INTEL_ALT_MANU 0x00B000B0	/* alternate INTEL namufacturer ID	*/
+#define MX_MANUFACT	   0x00C200C2	/* MXIC	   manuf. ID in D23..D16, D7..D0 */
+#define TOSH_MANUFACT	 0x00980098	/* TOSHIBA manuf. ID in D23..D16, D7..D0 */
+#define MT2_MANUFACT	 0x002C002C	/* alternate MICRON manufacturer ID*/
+#define EXCEL_MANUFACT 0x004A004A	/* Excel Semiconductor			*/
+#define EON_MANUFACT   0x007F007F	/* Excel Semiconductor			*/
+#define NUM_MANUFACT	 0x00200020	/* numonyx Semiconductor		*/
+
+					/* Micron Technologies (INTEL compat.)	*/
+#define MT_ID_28F400_T	0x44704470	/* 28F400B3 ID ( 4 M, top boot sector)	*/
+#define MT_ID_28F400_B	0x44714471	/* 28F400B3 ID ( 4 M, bottom boot sect) */
+
+#define AMD_ID_LV040B	0x4F		/* 29LV040B ID				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define AMD_ID_F033C	0xA3		/* 29LV033C ID				*/
+					/* 32 Mbit, 4Mbits x 8,			*/
+					/* 64 64K x 8 uniform sectors		*/
+#define AMD_ID_F065D	0x93		/* 29LV065D ID				*/
+					/* 64 Mbit, 8Mbits x 8,			*/
+					/* 126 64K x 8 uniform sectors		*/
+#define ATM_ID_LV040	0x13		/* 29LV040B ID				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define AMD_ID_F040B	0xA4		/* 29F040B ID				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define STM_ID_M29W040B 0xE3		/* M29W040B ID				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define AMD_ID_F080B	0xD5		/* 29F080  ID  ( 1 M)			*/
+					/* 8 Mbit, 512K x 16,			*/
+					/* 8 64K x 16 uniform sectors		*/
+#define AMD_ID_F016D	0xAD		/* 29F016  ID  ( 2 M x 8)		*/
+#define AMD_ID_F032B	0x41		/* 29F032  ID  ( 4 M x 8)		*/
+#define AMD_ID_LV116DT	0xC7		/* 29LV116DT   ( 2 M x 8, top boot sect) */
+#define AMD_ID_LV116DB	0x4C		/* 29LV116DB   ( 2 M x 8, bottom boot sect) */
+#define AMD_ID_LV016B	0xc8		/* 29LV016 ID  ( 2 M x 8)		*/
+
+#define AMD_ID_PL160CB	0x22452245	/* 29PL160CB ID (16 M, bottom boot sect */
+
+#define AMD_ID_LV400T	0x22B922B9	/* 29LV400T ID ( 4 M, top boot sector)	*/
+#define AMD_ID_LV400B	0x22BA22BA	/* 29LV400B ID ( 4 M, bottom boot sect) */
+
+#define AMD_ID_LV033C	0xA3		/* 29LV033C ID ( 4 M x 8)		*/
+#define AMD_ID_LV065D	0x93		/* 29LV065D ID ( 8 M x 8)		*/
+
+#define AMD_ID_LV800T	0x22DA22DA	/* 29LV800T ID ( 8 M, top boot sector)	*/
+#define AMD_ID_LV800B	0x225B225B	/* 29LV800B ID ( 8 M, bottom boot sect) */
+
+#define AMD_ID_LV160T	0x22C422C4	/* 29LV160T ID (16 M, top boot sector)	*/
+#define AMD_ID_LV160B	0x22492249	/* 29LV160B ID (16 M, bottom boot sect) */
+
+#define AMD_ID_DL163T	0x22282228	/* 29DL163T ID (16 M, top boot sector)	*/
+#define AMD_ID_DL163B	0x222B222B	/* 29DL163B ID (16 M, bottom boot sect) */
+
+#define AMD_ID_LV320T	0x22F622F6	/* 29LV320T ID (32 M, top boot sector)	*/
+#define MX_ID_LV320T	0x22A722A7	/* 29LV320T by Macronix, AMD compatible */
+#define AMD_ID_LV320B	0x22F922F9	/* 29LV320B ID (32 M, bottom boot sect) */
+#define MX_ID_LV320B	0x22A822A8	/* 29LV320B by Macronix, AMD compatible */
+
+#define AMD_ID_DL322T	0x22552255	/* 29DL322T ID (32 M, top boot sector)	*/
+#define AMD_ID_DL322B	0x22562256	/* 29DL322B ID (32 M, bottom boot sect) */
+#define AMD_ID_DL323T	0x22502250	/* 29DL323T ID (32 M, top boot sector)	*/
+#define AMD_ID_DL323B	0x22532253	/* 29DL323B ID (32 M, bottom boot sect) */
+#define AMD_ID_DL324T	0x225C225C	/* 29DL324T ID (32 M, top boot sector)	*/
+#define AMD_ID_DL324B	0x225F225F	/* 29DL324B ID (32 M, bottom boot sect) */
+
+#define AMD_ID_DL640	0x227E227E	/* 29DL640D ID (64 M, dual boot sectors)*/
+#define AMD_ID_MIRROR	0x227E227E	/* 1st ID word for MirrorBit family */
+#define AMD_ID_DL640G_2 0x22022202	/* 2nd ID word for AM29DL640G  at 0x38 */
+#define AMD_ID_DL640G_3 0x22012201	/* 3rd ID word for AM29DL640G  at 0x3c */
+#define AMD_ID_LV640U_2 0x220C220C	/* 2nd ID word for AM29LV640M  at 0x38 */
+#define AMD_ID_LV640U_3 0x22012201	/* 3rd ID word for AM29LV640M  at 0x3c */
+#define AMD_ID_LV640MT_2 0x22102210	/* 2nd ID word for AM29LV640MT at 0x38 */
+#define AMD_ID_LV640MT_3 0x22012201	/* 3rd ID word for AM29LV640MT at 0x3c */
+#define AMD_ID_LV640MB_2 0x22102210	/* 2nd ID word for AM29LV640MB at 0x38 */
+#define AMD_ID_LV640MB_3 0x22002200	/* 3rd ID word for AM29LV640MB at 0x3c */
+#define AMD_ID_LV128U_2 0x22122212	/* 2nd ID word for AM29LV128M  at 0x38 */
+#define AMD_ID_LV128U_3 0x22002200	/* 3rd ID word for AM29LV128M  at 0x3c */
+#define AMD_ID_LV256U_2 0x22122212	/* 2nd ID word for AM29LV256M  at 0x38 */
+#define AMD_ID_LV256U_3 0x22012201	/* 3rd ID word for AM29LV256M  at 0x3c */
+#define AMD_ID_GL064M_2 0x22132213	/* 2nd ID word for S29GL064M-R6 */
+#define AMD_ID_GL064M_3 0x22012201	/* 3rd ID word for S29GL064M-R6 */
+#define AMD_ID_GL064MT_2 0x22102210	/* 2nd ID word for S29GL064M-R3 (top boot sector) */
+#define AMD_ID_GL064MT_3 0x22012201	/* 3rd ID word for S29GL064M-R3 (top boot sector) */
+
+#define AMD_ID_LV320B_2 0x221A221A	/* 2d ID word for AM29LV320MB at 0x38 */
+#define AMD_ID_LV320B_3 0x22002200	/* 3d ID word for AM29LV320MB at 0x3c */
+
+#define AMD_ID_LV640U	0x22D722D7	/* 29LV640U ID (64 M, uniform sectors)	*/
+#define AMD_ID_LV650U	0x22D722D7	/* 29LV650U ID (64 M, uniform sectors)	*/
+
+#define ATM_ID_BV1614	0x000000C0	/* 49BV1614  ID */
+#define ATM_ID_BV1614A	0x000000C8	/* 49BV1614A ID */
+#define ATM_ID_BV6416	0x000000D6	/* 49BV6416  ID */
+
+#define FUJI_ID_29F800BA  0x22582258	/* MBM29F800BA ID  (8M) */
+#define FUJI_ID_29F800TA  0x22D622D6	/* MBM29F800TA ID  (8M) */
+#define FUJI_ID_29LV650UE 0x22d722d7	/* MBM29LV650UE/651UE ID (8M = 128 x 32kWord) */
+
+#define SST_ID_xF200A	0x27892789	/* 39xF200A ID ( 2M = 128K x 16 )	*/
+#define SST_ID_xF400A	0x27802780	/* 39xF400A ID ( 4M = 256K x 16 )	*/
+#define SST_ID_xF800A	0x27812781	/* 39xF800A ID ( 8M = 512K x 16 )	*/
+#define SST_ID_xF160A	0x27822782	/* 39xF800A ID (16M =	1M x 16 )	*/
+#define SST_ID_xF1601	0x234B234B	/* 39xF1601 ID (16M =	1M x 16 )	*/
+#define SST_ID_xF1602	0x234A234A	/* 39xF1602 ID (16M =	1M x 16 )	*/
+#define SST_ID_xF3201	0x235B235B	/* 39xF3201 ID (32M =	2M x 16 )	*/
+#define SST_ID_xF3202	0x235A235A	/* 39xF3202 ID (32M =	2M x 16 )	*/
+#define SST_ID_xF6401	0x236B236B	/* 39xF6401 ID (64M =	4M x 16 )	*/
+#define SST_ID_xF6402	0x236A236A	/* 39xF6402 ID (64M =	4M x 16 )	*/
+#define SST_ID_xF040	0xBFD7BFD7	/* 39xF040 ID (512KB = 4Mbit x 8)	*/
+#define SST_ID_49LF004B 0X60
+
+#define STM_ID_F040B	0xE2		/* M29F040B ID ( 4M = 512K x 8	)	*/
+					/* 8 64K x 8 uniform sectors		*/
+
+#define STM_ID_x800AB	0x005B005B	/* M29W800AB ID (8M = 512K x 16 )	*/
+#define STM_ID_29W320DT 0x22CA22CA	/* M29W320DT ID (32 M, top boot sector) */
+#define STM_ID_29W320DB 0x22CB22CB	/* M29W320DB ID (32 M, bottom boot sect)	*/
+#define STM_ID_29W040B	0x00E300E3	/* M29W040B ID (4M = 512K x 8)	*/
+
+#define INTEL_ID_28F016S    0x66a066a0	/* 28F016S[VS] ID (16M = 512k x 16)	*/
+#define INTEL_ID_28F800B3T  0x88928892	/*  8M = 512K x 16 top boot sector	*/
+#define INTEL_ID_28F800B3B  0x88938893	/*  8M = 512K x 16 bottom boot sector	*/
+#define INTEL_ID_28F160B3T  0x88908890	/*  16M = 1M x 16 top boot sector	*/
+#define INTEL_ID_28F160B3B  0x88918891	/*  16M = 1M x 16 bottom boot sector	*/
+#define INTEL_ID_28F320B3T  0x88968896	/*  32M = 2M x 16 top boot sector	*/
+#define INTEL_ID_28F320B3B  0x88978897	/*  32M = 2M x 16 bottom boot sector	*/
+#define INTEL_ID_28F640B3T  0x88988898	/*  64M = 4M x 16 top boot sector	*/
+#define INTEL_ID_28F640B3B  0x88998899	/*  64M = 4M x 16 bottom boot sector	*/
+#define INTEL_ID_28F160F3B  0x88F488F4	/*  16M = 1M x 16 bottom boot sector	*/
+
+#define INTEL_ID_28F800C3T  0x88C088C0	/*  8M = 512K x 16 top boot sector	*/
+#define INTEL_ID_28F800C3B  0x88C188C1	/*  8M = 512K x 16 bottom boot sector	*/
+#define INTEL_ID_28F160C3T  0x88C288C2	/*  16M = 1M x 16 top boot sector	*/
+#define INTEL_ID_28F160C3B  0x88C388C3	/*  16M = 1M x 16 bottom boot sector	*/
+#define INTEL_ID_28F320C3T  0x88C488C4	/*  32M = 2M x 16 top boot sector	*/
+#define INTEL_ID_28F320C3B  0x88C588C5	/*  32M = 2M x 16 bottom boot sector	*/
+#define INTEL_ID_28F640C3T  0x88CC88CC	/*  64M = 4M x 16 top boot sector	*/
+#define INTEL_ID_28F640C3B  0x88CD88CD	/*  64M = 4M x 16 bottom boot sector	*/
+
+#define INTEL_ID_28F128J3   0x89188918	/*  16M = 8M x 16 x 128 */
+#define INTEL_ID_28F320J5   0x00140014	/*  32M = 128K x  32	*/
+#define INTEL_ID_28F640J5   0x00150015	/*  64M = 128K x  64	*/
+#define INTEL_ID_28F320J3A  0x00160016	/*  32M = 128K x  32	*/
+#define INTEL_ID_28F640J3A  0x00170017	/*  64M = 128K x  64	*/
+#define INTEL_ID_28F128J3A  0x00180018	/* 128M = 128K x 128	*/
+#define INTEL_ID_28F256L18T 0x880D880D	/* 256M = 128K x 255 + 32k x 4 */
+#define INTEL_ID_28F64K3    0x88018801	/*  64M =  32K x 255 + 32k x 4 */
+#define INTEL_ID_28F128K3   0x88028802	/* 128M =  64K x 255 + 32k x 4 */
+#define INTEL_ID_28F256K3   0x88038803	/* 256M = 128K x 255 + 32k x 4 */
+
+#define INTEL_ID_28F160S3   0x00D000D0	/*  16M = 512K x  32 (64kB x 32)	*/
+#define INTEL_ID_28F320S3   0x00D400D4	/*  32M = 512K x  64 (64kB x 64)	*/
+
+/* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */
+#define SHARP_ID_28F016SCL  0xAAAAAAAA	/* LH28F016SCT-L95 2Mx8, 32 64k blocks	*/
+#define SHARP_ID_28F016SCZ  0xA0A0A0A0	/* LH28F016SCT-Z4  2Mx8, 32 64k blocks	*/
+#define SHARP_ID_28F008SC   0xA6A6A6A6	/* LH28F008SCT-L12 1Mx8, 16 64k blocks	*/
+					/* LH28F008SCR-L85 1Mx8, 16 64k blocks	*/
+
+#define TOSH_ID_FVT160	0xC2		/* TC58FVT160 ID (16 M, top )		*/
+#define TOSH_ID_FVB160	0x43		/* TC58FVT160 ID (16 M, bottom )	*/
+
+#define EON_ID_LV640U   0x22D722D7
+#define EON_ID_LV640T   0x22C922C9
+#define EON_ID_LV640H   0x227E227E
+#define EON_ID_LV640B   0x22CB22CB
+#define NUM_ID_W640GT   0x227E227E
+#define NUM_ID_W128G    0x227E227E
+#define NUM_ID_W128G    0x227E227E
+
+#define MX_ID_GL256E    0x227E227E
+/*#define MX_ID_LV640B   0x22CB22CB*/
+/*#define MX_ID_LV640T   0x22C922C9*/
+#define NOR_IDALL(x, y)	((x<<16)|y)
+
+/* MKid_DEVid1 : DEVICE CODE CYCLE 1 + CYCLE 2 */
+/* NUMONYX */
+#define	NX_M29W640GT	0x22102201 /*   8 MB */
+#define	NX_M29W640GB	0x22102200 /*   8 MB */
+#define	NX_M29W640GH	0x220C2201 /*   8 MB */
+#define	NX_M29W640GL	0x220C2200 /*   8 MB */
+#define	NX_M29W128GH	0x22212201 /*  16 MB */
+#define	NX_M29W128GL	0x22212200 /*  16 MB */
+/*-----------------------------------------------------------------------
+ * Internal FLASH identification codes
+ *
+ * Be careful when adding new type! Odd numbers are "bottom boot sector" types!
+ */
+
+#define FLASH_AM040	0x0001		/* AMD Am29F040B, Am29LV040B		*/
+					/* Bright Micro BM29F040		*/
+					/* Fujitsu MBM29F040A			*/
+					/* STM M29W040B				*/
+					/* SGS Thomson M29F040B			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define FLASH_AM400T	0x0002		/* AMD AM29LV400			*/
+#define FLASH_AM400B	0x0003
+#define FLASH_AM800T	0x0004		/* AMD AM29LV800			*/
+#define FLASH_AM800B	0x0005
+#define FLASH_AM116DT	0x0026		/* AMD AM29LV116DT (2Mx8bit) */
+#define FLASH_AM116DB	0x0027		/* AMD AM29LV116DB (2Mx8bit) */
+#define FLASH_AM160T	0x0006		/* AMD AM29LV160			*/
+#define FLASH_AM160LV	0x0046		/* AMD29LV160DB (2M = 2Mx8bit ) */
+#define FLASH_AM160B	0x0007
+#define FLASH_AM320T	0x0008		/* AMD AM29LV320			*/
+#define FLASH_AM320B	0x0009
+
+#define FLASH_AM080	0x000A		/* AMD Am29F080B			*/
+					/* 16 64K x 8 uniform sectors		*/
+
+#define FLASH_AMDL322T	0x0010		/* AMD AM29DL322			*/
+#define FLASH_AMDL322B	0x0011
+#define FLASH_AMDL323T	0x0012		/* AMD AM29DL323			*/
+#define FLASH_AMDL323B	0x0013
+#define FLASH_AMDL324T	0x0014		/* AMD AM29DL324			*/
+#define FLASH_AMDL324B	0x0015
+
+#define FLASH_AMDLV033C 0x0018
+#define FLASH_AMDLV065D 0x001A
+
+#define FLASH_AMDL640	0x0016		/* AMD AM29DL640D			*/
+#define FLASH_AMD016	0x0018		/* AMD AM29F016D			*/
+#define FLASH_AMDL640MB 0x0019		/* AMD AM29LV640MB (64M, bottom boot sect)*/
+#define FLASH_AMDL640MT 0x001A		/* AMD AM29LV640MT (64M, top boot sect) */
+
+#define FLASH_SST200A	0x0040		/* SST 39xF200A ID (  2M = 128K x 16 )	*/
+#define FLASH_SST400A	0x0042		/* SST 39xF400A ID (  4M = 256K x 16 )	*/
+#define FLASH_SST800A	0x0044		/* SST 39xF800A ID (  8M = 512K x 16 )	*/
+#define FLASH_SST160A	0x0046		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
+#define FLASH_SST320	0x0048		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
+#define FLASH_SST640	0x004A		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
+#define FLASH_SST040	0x000E		/* SST 39xF040 ID (512KB = 4Mbit x 8 )	*/
+#define FLASH_49LF004B 0X0060           /* 512 KB*/
+
+#define FLASH_STM800AB	0x0051		/* STM M29WF800AB  (  8M = 512K x 16 )	*/
+#define FLASH_STMW320DT 0x0052		/* STM M29W320DT   (32 M, top boot sector)	*/
+#define FLASH_STMW320DB 0x0053		/* STM M29W320DB   (32 M, bottom boot sect)*/
+#define FLASH_STM320DB	0x00CB		/* STM M29W320DB (4M = 64K x 64, bottom)*/
+#define FLASH_STM800DT	0x00D7		/* STM M29W800DT (1M = 64K x 16, top)	*/
+#define FLASH_STM800DB	0x005B		/* STM M29W800DB (1M = 64K x 16, bottom)*/
+
+#define FLASH_28F400_T	0x0062		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
+#define FLASH_28F400_B	0x0063		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
+
+#define FLASH_INTEL800T 0x0074		/* INTEL 28F800B3T (  8M = 512K x 16 )	*/
+#define FLASH_INTEL800B 0x0075		/* INTEL 28F800B3B (  8M = 512K x 16 )	*/
+#define FLASH_INTEL160T 0x0076		/* INTEL 28F160B3T ( 16M =  1 M x 16 )	*/
+#define FLASH_INTEL160B 0x0077		/* INTEL 28F160B3B ( 16M =  1 M x 16 )	*/
+#define FLASH_INTEL320T 0x0078		/* INTEL 28F320B3T ( 32M =  2 M x 16 )	*/
+#define FLASH_INTEL320B 0x0079		/* INTEL 28F320B3B ( 32M =  2 M x 16 )	*/
+#define FLASH_INTEL640T 0x007A		/* INTEL 28F320B3T ( 64M =  4 M x 16 )	*/
+#define FLASH_INTEL640B 0x007B		/* INTEL 28F320B3B ( 64M =  4 M x 16 )	*/
+
+#define FLASH_28F008S5	0x0080		/* Intel 28F008S5  (  1M =  64K x 16 )	*/
+#define FLASH_28F016SV	0x0081		/* Intel 28F016SV  ( 16M = 512k x 32 )	*/
+#define FLASH_28F800_B	0x0083		/* Intel E28F800B  (  1M = ? )		*/
+#define FLASH_AM29F800B 0x0084		/* AMD Am29F800BB  (  1M = ? )		*/
+#define FLASH_28F320J5	0x0085		/* Intel 28F320J5  (  4M = 128K x 32 )	*/
+#define FLASH_28F160S3	0x0086		/* Intel 28F160S3  ( 16M = 512K x 32 )	*/
+#define FLASH_28F320S3	0x0088		/* Intel 28F320S3  ( 32M = 512K x 64 )	*/
+#define FLASH_AM640U	0x0090		/* AMD Am29LV640U  ( 64M = 4M x 16 )	*/
+#define FLASH_AM033C	0x0091		/* AMD AM29LV033   ( 32M = 4M x 8 )	*/
+#define FLASH_LH28F016SCT 0x0092	/* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
+#define FLASH_28F160F3B 0x0093		/* Intel 28F160F3B ( 16M = 1M x 16 )	*/
+#define FLASH_AM065D	0x0093
+
+#define FLASH_28F640J5	0x0099		/* INTEL 28F640J5  ( 64M = 128K x  64)	*/
+
+#define FLASH_28F800C3T 0x009A		/* Intel 28F800C3T (  8M = 512K x 16 )	*/
+#define FLASH_28F800C3B 0x009B		/* Intel 28F800C3B (  8M = 512K x 16 )	*/
+#define FLASH_28F160C3T 0x009C		/* Intel 28F160C3T ( 16M = 1M x 16 )	*/
+#define FLASH_28F160C3B 0x009D		/* Intel 28F160C3B ( 16M = 1M x 16 )	*/
+#define FLASH_28F320C3T 0x009E		/* Intel 28F320C3T ( 32M = 2M x 16 )	*/
+#define FLASH_28F320C3B 0x009F		/* Intel 28F320C3B ( 32M = 2M x 16 )	*/
+#define FLASH_28F640C3T 0x00A0		/* Intel 28F640C3T ( 64M = 4M x 16 )	*/
+#define FLASH_28F640C3B 0x00A1		/* Intel 28F640C3B ( 64M = 4M x 16 )	*/
+#define FLASH_AMLV320U	0x00A2		/* AMD 29LV320M	   ( 32M = 2M x 16 )	*/
+
+#define FLASH_AM033	0x00A3		/* AMD AmL033C90V1   (32M = 4M x 8)	*/
+#define FLASH_AM065	0x0093		/* AMD AmL065DU12RI  (64M = 8M x 8)	*/
+#define FLASH_AT040	0x00A5		/* Amtel AT49LV040   (4M = 512K x 8)	*/
+
+#define FLASH_AMLV640U	0x00A4		/* AMD 29LV640M	   ( 64M = 4M x 16 )	*/
+#define FLASH_AMLV128U	0x00A6		/* AMD 29LV128M	   ( 128M = 8M x 16 )	*/
+#define FLASH_AMLV320B	0x00A7		/* AMD 29LV320MB   ( 32M = 2M x 16 )	*/
+#define FLASH_AMLV320T	0x00A8		/* AMD 29LV320MT   ( 32M = 2M x 16 )	*/
+#define FLASH_AMLV256U	0x00AA		/* AMD 29LV256M	   ( 256M = 16M x 16 )	*/
+#define FLASH_MXLV320B	0x00AB		/* MX  29LV320MB   ( 32M = 2M x 16 )	*/
+#define FLASH_MXLV320T	0x00AC		/* MX  29LV320MT   ( 32M = 2M x 16 )	*/
+#define FLASH_28F256L18T 0x00B0		/* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
+#define FLASH_AMDL163T	0x00B2		/* AMD AM29DL163T (2M x 16 )			*/
+#define FLASH_AMDL163B	0x00B3
+#define FLASH_28F64K3	0x00B4		/* Intel 28F64K3   (  64M)		*/
+#define FLASH_28F128K3	0x00B6		/* Intel 28F128K3  ( 128M = 8M x 16 )	*/
+#define FLASH_28F256K3	0x00B8		/* Intel 28F256K3  ( 256M = 16M x 16 )	*/
+
+#define FLASH_28F320J3A 0x00C0		/* INTEL 28F320J3A ( 32M = 128K x  32)	*/
+#define FLASH_28F640J3A 0x00C2		/* INTEL 28F640J3A ( 64M = 128K x  64)	*/
+#define FLASH_28F128J3A 0x00C4		/* INTEL 28F128J3A (128M = 128K x 128)	*/
+
+#define FLASH_FUJLV650	0x00D0		/* Fujitsu MBM 29LV650UE/651UE		*/
+#define FLASH_MT28S4M16LC 0x00E1	/* Micron MT28S4M16LC			*/
+#define FLASH_S29GL064M 0x00F0		/* Spansion S29GL064M-R6		*/
+#define FLASH_EON29LV640U  0x00f1
+#define FLASH_EON29LV640H  0x00f2
+#define FLASH_EON29LV640B  0x00f3
+#define FLASH_MX29LV640B  0x00f4
+#define FLASH_MX29LV640T  0x00f5
+#define FLASH_NUM29W640GT  0x00f6
+#define FLASH_NUM29W640GB  0x00f7
+#define FLASH_NUM29W640GHL  0x00f8
+#define FLASH_NUM29W128GHL  0x00f9
+#define FLASH_MX29GL256E 0x00fa
+
+
+#define FLASH_UNKNOWN	0xFFFFFFFF	/* unknown flash type			*/
+
+/*
+ *  manufacturer offsets
+ */
+#define FLASH_MAN_AMD	0x00000000	/* AMD					*/
+#define FLASH_MAN_FUJ	0x00010000	/* Fujitsu				*/
+#define FLASH_MAN_BM	0x00020000	/* Bright Microelectronics		*/
+#define FLASH_MAN_MX	0x00030000	/* MXIC					*/
+#define FLASH_MAN_STM	0x00040000
+#define FLASH_MAN_TOSH	0x00050000	/* Toshiba				*/
+#define FLASH_MAN_EXCEL 0x00060000	/* Excel Semiconductor			*/
+#define FLASH_MAN_SST	0x00100000
+#define FLASH_MAN_INTEL 0x00300000
+#define FLASH_MAN_MT	0x00400000
+#define FLASH_MAN_SHARP 0x00500000
+#define FLASH_MAN_ATM	0x00600000
+#define FLASH_MAN_EON   0X00700000
+#define FLASH_MAN_NUM   0X00800000
+
+#define FLASH_TYPEMASK	0x0000FFFF	/* extract FLASH type	information	*/
+#define FLASH_VENDMASK	0xFFFF0000	/* extract FLASH vendor information	*/
+
+#define FLASH_AMD_COMP	0x000FFFFF	/* Up to this ID, FLASH is compatible	*/
+					/* with AMD, Fujitsu and SST		*/
+					/* (JEDEC standard commands ?)		*/
+
+#define FLASH_BTYPE	0x0001		/* mask for bottom boot sector type	*/
+
+/*-----------------------------------------------------------------------
+ * Timeout constants:
+ *
+ * We can't find any specifications for maximum chip erase times,
+ * so these values are guestimates.
+ */
+#define FLASH_ERASE_TIMEOUT	120000	/* timeout for erasing in ms		*/
+#define FLASH_WRITE_TIMEOUT	500	/* timeout for writes  in ms		*/
+
+#endif /* !CFG_NO_FLASH */
+
+#endif /* _FLASH_H_ */
diff --git a/include/fpga.h b/include/fpga.h
new file mode 100755
index 0000000..a038aa1
--- /dev/null
+++ b/include/fpga.h
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <linux/types.h>               /* for ulong typedef */
+
+#ifndef _FPGA_H_
+#define _FPGA_H_
+
+#ifndef CONFIG_MAX_FPGA_DEVICES
+#define CONFIG_MAX_FPGA_DEVICES		5
+#endif
+
+/* these probably belong somewhere else */
+#ifndef FALSE
+#define FALSE	(0)
+#endif
+#ifndef TRUE
+#define TRUE 	(!FALSE)
+#endif
+
+/* CONFIG_FPGA bit assignments */
+#define CFG_FPGA_MAN(x)	(x)
+#define CFG_FPGA_DEV(x)	((x) << 8 )
+#define CFG_FPGA_IF(x)	((x) << 16 )
+
+/* FPGA Manufacturer bits in CONFIG_FPGA */
+#define CFG_FPGA_XILINX 		CFG_FPGA_MAN( 0x1 )
+#define CFG_FPGA_ALTERA			CFG_FPGA_MAN( 0x2 )
+
+
+/* fpga_xxxx function return value definitions */
+#define FPGA_SUCCESS         0
+#define FPGA_FAIL           -1
+
+/* device numbers must be non-negative */
+#define FPGA_INVALID_DEVICE -1
+
+/* root data type defintions */
+typedef enum {                 /* typedef fpga_type */
+	fpga_min_type,             /* range check value */
+    fpga_xilinx,               /* Xilinx Family) */
+    fpga_altera,               /* unimplemented */
+    fpga_undefined             /* invalid range check value */
+} fpga_type;                   /* end, typedef fpga_type */
+
+typedef struct {               /* typedef fpga_desc */
+    fpga_type   devtype;       /* switch value to select sub-functions */
+    void *      devdesc;       /* real device descriptor */
+} fpga_desc;                   /* end, typedef fpga_desc */
+
+
+/* root function definitions */
+extern void fpga_init( ulong reloc_off );
+extern int fpga_add( fpga_type devtype, void *desc );
+extern int fpga_count( void );
+extern int fpga_load( int devnum, void *buf, size_t bsize );
+extern int fpga_dump( int devnum, void *buf, size_t bsize );
+extern int fpga_info( int devnum );
+
+#endif	/* _FPGA_H_ */
diff --git a/include/ft_build.h b/include/ft_build.h
new file mode 100755
index 0000000..9104b1a
--- /dev/null
+++ b/include/ft_build.h
@@ -0,0 +1,66 @@
+/*
+ * OF Flat tree builder
+ *
+ */
+
+#ifndef FT_BUILD_H
+#define FT_BUILD_H
+
+#include <linux/types.h>
+#include <asm/u-boot.h>
+
+/* Definitions used by the flattened device tree */
+#define OF_DT_HEADER		0xd00dfeed	/* marker */
+#define OF_DT_BEGIN_NODE	0x1	/* Start of node, full name */
+#define OF_DT_END_NODE		0x2	/* End node */
+#define OF_DT_PROP		0x3	/* Property: name off, size,
+					 * content */
+#define OF_DT_NOP		0x4	/* nop */
+#define OF_DT_END		0x9
+
+#define OF_DT_VERSION		0x10
+
+struct boot_param_header {
+	u32 magic;		/* magic word OF_DT_HEADER */
+	u32 totalsize;		/* total size of DT block */
+	u32 off_dt_struct;	/* offset to structure */
+	u32 off_dt_strings;	/* offset to strings */
+	u32 off_mem_rsvmap;	/* offset to memory reserve map */
+	u32 version;		/* format version */
+	u32 last_comp_version;	/* last compatible version */
+	/* version 2 fields below */
+	u32 boot_cpuid_phys;	/* Physical CPU id we're booting on */
+	/* version 3 fields below */
+	u32 dt_strings_size;	/* size of the DT strings block */
+};
+
+struct ft_cxt {
+	struct boot_param_header *bph;
+	int max_size;		/* maximum size of tree */
+	int overflow;		/* set when this happens */
+	u8 *p, *pstr, *pres;	/* running pointers */
+	u8 *p_begin, *pstr_begin, *pres_begin;	/* starting pointers */
+	u8 *p_anchor;		/* start of constructed area */
+	int struct_size, strings_size, res_size;
+};
+
+void ft_begin_node(struct ft_cxt *cxt, const char *name);
+void ft_end_node(struct ft_cxt *cxt);
+
+void ft_begin_tree(struct ft_cxt *cxt);
+int ft_end_tree(struct ft_cxt *cxt);
+
+void ft_nop(struct ft_cxt *cxt);
+void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz);
+void ft_prop_str(struct ft_cxt *cxt, const char *name, const char *str);
+void ft_prop_int(struct ft_cxt *cxt, const char *name, int val);
+void ft_begin(struct ft_cxt *cxt, void *blob, int max_size);
+void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size);
+
+void ft_setup(void *blob, int size, bd_t * bd);
+
+void ft_dump_blob(const void *bphp);
+void ft_merge_blob(struct ft_cxt *cxt, void *blob);
+void *ft_get_prop(void *bphp, const char *propname, int *szp);
+
+#endif
diff --git a/include/galileo/core.h b/include/galileo/core.h
new file mode 100755
index 0000000..0735d07
--- /dev/null
+++ b/include/galileo/core.h
@@ -0,0 +1,218 @@
+/* Core.h - Basic core logic functions and definitions */
+
+/* Copyright Galileo Technology. */
+
+/*
+DESCRIPTION
+This header file contains simple read/write macros for addressing
+the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
+space). The macros take care of Big/Little endian conversions.
+*/
+
+#ifndef __INCcoreh
+#define __INCcoreh
+
+/* includes */
+#include "gt64260R.h"
+
+extern unsigned int INTERNAL_REG_BASE_ADDR;
+
+/*
+ * GT-6426x variants
+ */
+#define GT_64260	0  /* includes both 64260A and 64260B */
+#define GT_64261	1
+
+#if (CFG_GT_6426x == GT_64260)
+#ifdef CONFIG_ETHER_PORT_MII
+#define GAL_ETH_DEVS 2
+#else
+#define GAL_ETH_DEVS 3
+#endif
+#elif (CFG_GT_6426x == GT_64261)
+#define GAL_ETH_DEVS 2
+#else
+#define GAL_ETH_DEVS 3	/* default to a 64260 */
+#endif
+
+/****************************************/
+/*          GENERAL Definitions			*/
+/****************************************/
+
+#define NO_BIT          0x00000000
+#define BIT0            0x00000001
+#define BIT1            0x00000002
+#define BIT2            0x00000004
+#define BIT3            0x00000008
+#define BIT4            0x00000010
+#define BIT5            0x00000020
+#define BIT6            0x00000040
+#define BIT7            0x00000080
+#define BIT8            0x00000100
+#define BIT9            0x00000200
+#define BIT10           0x00000400
+#define BIT11           0x00000800
+#define BIT12           0x00001000
+#define BIT13           0x00002000
+#define BIT14           0x00004000
+#define BIT15           0x00008000
+#define BIT16           0x00010000
+#define BIT17           0x00020000
+#define BIT18           0x00040000
+#define BIT19           0x00080000
+#define BIT20           0x00100000
+#define BIT21           0x00200000
+#define BIT22           0x00400000
+#define BIT23           0x00800000
+#define BIT24           0x01000000
+#define BIT25           0x02000000
+#define BIT26           0x04000000
+#define BIT27           0x08000000
+#define BIT28           0x10000000
+#define BIT29           0x20000000
+#define BIT30           0x40000000
+#define BIT31           0x80000000
+
+#define _1K             0x00000400
+#define _2K             0x00000800
+#define _4K             0x00001000
+#define _8K             0x00002000
+#define _16K            0x00004000
+#define _32K            0x00008000
+#define _64K            0x00010000
+#define _128K           0x00020000
+#define _256K           0x00040000
+#define _512K           0x00080000
+
+#define _1M             0x00100000
+#define _2M             0x00200000
+#define _3M             0x00300000
+#define _4M             0x00400000
+#define _5M             0x00500000
+#define _6M             0x00600000
+#define _7M             0x00700000
+#define _8M             0x00800000
+#define _9M             0x00900000
+#define _10M            0x00a00000
+#define _11M            0x00b00000
+#define _12M            0x00c00000
+#define _13M            0x00d00000
+#define _14M            0x00e00000
+#define _15M            0x00f00000
+#define _16M            0x01000000
+
+#define _32M            0x02000000
+#define _64M            0x04000000
+#define _128M           0x08000000
+#define _256M           0x10000000
+#define _512M           0x20000000
+
+#define _1G             0x40000000
+#define _2G             0x80000000
+
+typedef enum _bool{false,true} bool;
+
+/* Little to Big endian conversion macros */
+
+#ifdef LE /* Little Endian */
+#define SHORT_SWAP(X) (X)
+#define WORD_SWAP(X) (X)
+#define LONG_SWAP(X) ((l64)(X))
+
+#else    /* Big Endian */
+#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
+
+#define WORD_SWAP(X) (((X)&0xff)<<24)+      \
+		    (((X)&0xff00)<<8)+      \
+		    (((X)&0xff0000)>>8)+    \
+		    (((X)&0xff000000)>>24)
+
+#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+               \
+			    (((X)&0xff00ULL)<<40)+              \
+			    (((X)&0xff0000ULL)<<24)+            \
+			    (((X)&0xff000000ULL)<<8)+           \
+			    (((X)&0xff00000000ULL)>>8)+         \
+			    (((X)&0xff0000000000ULL)>>24)+      \
+			    (((X)&0xff000000000000ULL)>>40)+    \
+			    (((X)&0xff00000000000000ULL)>>56))
+
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+/* Those two definitions were defined to be compatible with MIPS */
+#define NONE_CACHEABLE		0x00000000
+#define CACHEABLE			0x00000000
+
+/* 750 cache line */
+#define CACHE_LINE_SIZE 32
+#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
+#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
+
+/* Read/Write to/from GT`s internal registers */
+#define GT_REG_READ(offset, pData)                                          \
+*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE |                     \
+		INTERNAL_REG_BASE_ADDR | (offset))) ) ;                                              \
+*pData = WORD_SWAP(*pData)
+
+#define GTREGREAD(offset)                                                   \
+	 (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE |            \
+		   INTERNAL_REG_BASE_ADDR | (offset))) ))
+
+#define GT_REG_WRITE(offset, data)                                          \
+*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) =                   \
+		    WORD_SWAP(data)
+
+/* Write 32/16/8 bit */
+#define WRITE_CHAR(address, data)                                           \
+	*((unsigned char *)(address)) = data
+#define WRITE_SHORT(address, data)                                          \
+	*((unsigned short *)(address)) = data
+#define WRITE_WORD(address, data)                                           \
+	*((unsigned int *)(address)) = data
+
+/* Read 32/16/8 bits - returns data in variable. */
+#define READ_CHAR(address, pData)                                           \
+	*pData = *((volatile unsigned char *)(address))
+
+#define READ_SHORT(address, pData)                                          \
+	*pData = *((volatile unsigned short *)(address))
+
+#define READ_WORD(address, pData)                                           \
+	*pData = *((volatile unsigned int *)(address))
+
+/* Read 32/16/8 bit - returns data direct. */
+#define READCHAR(address)                                                   \
+	*((volatile unsigned char *)((address) | NONE_CACHEABLE))
+
+#define READSHORT(address)                                                  \
+	*((volatile unsigned short *)((address) | NONE_CACHEABLE))
+
+#define READWORD(address)                                                   \
+	*((volatile unsigned int *)((address) | NONE_CACHEABLE))
+
+/* Those two Macros were defined to be compatible with MIPS */
+#define VIRTUAL_TO_PHY(x)    (((unsigned int)x) & 0xffffffff)
+#define PHY_TO_VIRTUAL(x)    (((unsigned int)x) | NONE_CACHEABLE)
+
+/*  SET_REG_BITS(regOffset,bits) -
+   gets register offset and bits: a 32bit value. It set to logic '1' in the
+   internal register the bits which given as an input example:
+   SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+   '1' in register 0x840 while the other bits stays as is. */
+#define SET_REG_BITS(regOffset,bits) \
+	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR |  \
+	regOffset) |= (unsigned int)WORD_SWAP(bits)
+
+/*  RESET_REG_BITS(regOffset,bits) -
+   gets register offset and bits: a 32bit value. It set to logic '0' in the
+   internal register the bits which given as an input example:
+   RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+   '0' in register 0x840 while the other bits stays as is. */
+#define RESET_REG_BITS(regOffset,bits) \
+	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR   \
+	| regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
+
+#endif /* __INCcoreh */
diff --git a/include/galileo/gt64260R.h b/include/galileo/gt64260R.h
new file mode 100755
index 0000000..ebf087a
--- /dev/null
+++ b/include/galileo/gt64260R.h
@@ -0,0 +1,1194 @@
+/* gt64260R.h - GT64260 Internal registers definition file */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCgt64260rh
+#define __INCgt64260rh
+
+#ifndef GT64260
+#define GT64260
+#endif
+
+/* CPU MASTER CONTROL REGISTER */
+#define	CPU_CONFIGURATION	0x0
+#define	CPU_MASTER_CONTROL	0x160
+
+/****************************************/
+/* Processor Address Space				*/
+/****************************************/
+
+/* Sdram's BAR'S */
+#define SCS_0_LOW_DECODE_ADDRESS							0x008
+#define SCS_0_HIGH_DECODE_ADDRESS							0x010
+#define SCS_1_LOW_DECODE_ADDRESS							0x208
+#define SCS_1_HIGH_DECODE_ADDRESS							0x210
+#define SCS_2_LOW_DECODE_ADDRESS							0x018
+#define SCS_2_HIGH_DECODE_ADDRESS							0x020
+#define SCS_3_LOW_DECODE_ADDRESS							0x218
+#define SCS_3_HIGH_DECODE_ADDRESS							0x220
+/* Devices BAR'S */
+#define CS_0_LOW_DECODE_ADDRESS							    0x028
+#define CS_0_HIGH_DECODE_ADDRESS							0x030
+#define CS_1_LOW_DECODE_ADDRESS							    0x228
+#define CS_1_HIGH_DECODE_ADDRESS							0x230
+#define CS_2_LOW_DECODE_ADDRESS							    0x248
+#define CS_2_HIGH_DECODE_ADDRESS							0x250
+#define CS_3_LOW_DECODE_ADDRESS							    0x038
+#define CS_3_HIGH_DECODE_ADDRESS							0x040
+#define BOOTCS_LOW_DECODE_ADDRESS							0x238
+#define BOOTCS_HIGH_DECODE_ADDRESS							0x240
+
+#define PCI_0I_O_LOW_DECODE_ADDRESS							0x048
+#define PCI_0I_O_HIGH_DECODE_ADDRESS						0x050
+#define PCI_0MEMORY0_LOW_DECODE_ADDRESS						0x058
+#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS					0x060
+#define PCI_0MEMORY1_LOW_DECODE_ADDRESS						0x080
+#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS					0x088
+#define PCI_0MEMORY2_LOW_DECODE_ADDRESS						0x258
+#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS					0x260
+#define PCI_0MEMORY3_LOW_DECODE_ADDRESS						0x280
+#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS					0x288
+
+#define PCI_1I_O_LOW_DECODE_ADDRESS							0x090
+#define PCI_1I_O_HIGH_DECODE_ADDRESS						0x098
+#define PCI_1MEMORY0_LOW_DECODE_ADDRESS						0x0a0
+#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS					0x0a8
+#define PCI_1MEMORY1_LOW_DECODE_ADDRESS						0x0b0
+#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS					0x0b8
+#define PCI_1MEMORY2_LOW_DECODE_ADDRESS						0x2a0
+#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS					0x2a8
+#define PCI_1MEMORY3_LOW_DECODE_ADDRESS						0x2b0
+#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS					0x2b8
+
+
+#define INTERNAL_SPACE_DECODE								0x068
+
+#define CPU_0_LOW_DECODE_ADDRESS                            0x290
+#define CPU_0_HIGH_DECODE_ADDRESS                           0x298
+#define CPU_1_LOW_DECODE_ADDRESS                            0x2c0
+#define CPU_1_HIGH_DECODE_ADDRESS                           0x2c8
+
+#define PCI_0I_O_ADDRESS_REMAP								0x0f0
+#define PCI_0MEMORY0_ADDRESS_REMAP  			   			0x0f8
+#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP			   			0x320
+#define PCI_0MEMORY1_ADDRESS_REMAP  			   			0x100
+#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP			   			0x328
+#define PCI_0MEMORY2_ADDRESS_REMAP  			   			0x2f8
+#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP			   			0x330
+#define PCI_0MEMORY3_ADDRESS_REMAP  			   			0x300
+#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP			   			0x338
+
+#define PCI_1I_O_ADDRESS_REMAP								0x108
+#define PCI_1MEMORY0_ADDRESS_REMAP  				   		0x110
+#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP				   		0x340
+#define PCI_1MEMORY1_ADDRESS_REMAP  					   	0x118
+#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP					   	0x348
+#define PCI_1MEMORY2_ADDRESS_REMAP  					   	0x310
+#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP					   	0x350
+#define PCI_1MEMORY3_ADDRESS_REMAP  					   	0x318
+#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP					   	0x358
+
+
+/****************************************/
+/* CPU Sync Barrier             		*/
+/****************************************/
+
+#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER					0x0c0
+#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER					0x0c8
+
+
+/****************************************/
+/* CPU Access Protect             		*/
+/****************************************/
+
+#define CPU_LOW_PROTECT_ADDRESS_0                           0x180
+#define CPU_HIGH_PROTECT_ADDRESS_0                          0x188
+#define CPU_LOW_PROTECT_ADDRESS_1                           0x190
+#define CPU_HIGH_PROTECT_ADDRESS_1                          0x198
+#define CPU_LOW_PROTECT_ADDRESS_2                           0x1a0
+#define CPU_HIGH_PROTECT_ADDRESS_2                          0x1a8
+#define CPU_LOW_PROTECT_ADDRESS_3                           0x1b0
+#define CPU_HIGH_PROTECT_ADDRESS_3                          0x1b8
+#define CPU_LOW_PROTECT_ADDRESS_4                           0x1c0
+#define CPU_HIGH_PROTECT_ADDRESS_4                          0x1c8
+#define CPU_LOW_PROTECT_ADDRESS_5                           0x1d0
+#define CPU_HIGH_PROTECT_ADDRESS_5                          0x1d8
+#define CPU_LOW_PROTECT_ADDRESS_6                           0x1e0
+#define CPU_HIGH_PROTECT_ADDRESS_6                          0x1e8
+#define CPU_LOW_PROTECT_ADDRESS_7                           0x1f0
+#define CPU_HIGH_PROTECT_ADDRESS_7                          0x1f8
+
+
+/****************************************/
+/*          Snoop Control          		*/
+/****************************************/
+
+#define SNOOP_BASE_ADDRESS_0                                0x380
+#define SNOOP_TOP_ADDRESS_0                                 0x388
+#define SNOOP_BASE_ADDRESS_1                                0x390
+#define SNOOP_TOP_ADDRESS_1                                 0x398
+#define SNOOP_BASE_ADDRESS_2                                0x3a0
+#define SNOOP_TOP_ADDRESS_2                                 0x3a8
+#define SNOOP_BASE_ADDRESS_3                                0x3b0
+#define SNOOP_TOP_ADDRESS_3                                 0x3b8
+
+/****************************************/
+/*          CPU Error Report       		*/
+/****************************************/
+
+#define CPU_ERROR_ADDRESS_LOW 							    0x070
+#define CPU_ERROR_ADDRESS_HIGH 							    0x078
+#define CPU_ERROR_DATA_LOW                                  0x128
+#define CPU_ERROR_DATA_HIGH                                 0x130
+#define CPU_ERROR_PARITY                                    0x138
+#define CPU_ERROR_CAUSE                                     0x140
+#define CPU_ERROR_MASK                                      0x148
+
+/****************************************/
+/*          Pslave Debug           		*/
+/****************************************/
+
+#define X_0_ADDRESS                                         0x360
+#define X_0_COMMAND_ID                                      0x368
+#define X_1_ADDRESS                                         0x370
+#define X_1_COMMAND_ID                                      0x378
+#define WRITE_DATA_LOW                                      0x3c0
+#define WRITE_DATA_HIGH                                     0x3c8
+#define WRITE_BYTE_ENABLE                                   0x3e0
+#define READ_DATA_LOW                                       0x3d0
+#define READ_DATA_HIGH                                      0x3d8
+#define READ_ID                                             0x3e8
+
+
+/****************************************/
+/* SDRAM and Device Address Space		*/
+/****************************************/
+
+
+/****************************************/
+/* SDRAM Configuration			*/
+/****************************************/
+
+
+#define SDRAM_CONFIGURATION				0x448
+#define SDRAM_OPERATION_MODE				0x474
+#define SDRAM_ADDRESS_DECODE				0x47c
+#define SDRAM_UMA_CONTROL				0x4a4
+#define SDRAM_CROSS_BAR_CONTROL_LOW			0x4a8
+#define SDRAM_CROSS_BAR_CONTROL_HIGH			0x4ac
+#define SDRAM_CROSS_BAR_TIMEOUT				0x4b0
+#define SDRAM_TIMING					0x4b4
+
+
+/****************************************/
+/* SDRAM Parameters			*/
+/****************************************/
+
+#define SDRAM_BANK0PARAMETERS				0x44C
+#define SDRAM_BANK1PARAMETERS				0x450
+#define SDRAM_BANK2PARAMETERS				0x454
+#define SDRAM_BANK3PARAMETERS				0x458
+
+
+/****************************************/
+/* SDRAM Error Report 			*/
+/****************************************/
+
+#define SDRAM_ERROR_DATA_LOW                                0x484
+#define SDRAM_ERROR_DATA_HIGH                               0x480
+#define SDRAM_AND_DEVICE_ERROR_ADDRESS                      0x490
+#define SDRAM_RECEIVED_ECC                                  0x488
+#define SDRAM_CALCULATED_ECC                                0x48c
+#define SDRAM_ECC_CONTROL                                   0x494
+#define SDRAM_ECC_ERROR_COUNTER                             0x498
+
+
+/****************************************/
+/* SDunit Debug (for internal use)	*/
+/****************************************/
+
+#define X0_ADDRESS                                          0x500
+#define X0_COMMAND_AND_ID                                   0x504
+#define X0_WRITE_DATA_LOW                                   0x508
+#define X0_WRITE_DATA_HIGH                                  0x50c
+#define X0_WRITE_BYTE_ENABLE                                0x518
+#define X0_READ_DATA_LOW                                    0x510
+#define X0_READ_DATA_HIGH                                   0x514
+#define X0_READ_ID                                          0x51c
+#define X1_ADDRESS                                          0x520
+#define X1_COMMAND_AND_ID                                   0x524
+#define X1_WRITE_DATA_LOW                                   0x528
+#define X1_WRITE_DATA_HIGH                                  0x52c
+#define X1_WRITE_BYTE_ENABLE                                0x538
+#define X1_READ_DATA_LOW                                    0x530
+#define X1_READ_DATA_HIGH                                   0x534
+#define X1_READ_ID                                          0x53c
+#define X0_SNOOP_ADDRESS                                    0x540
+#define X0_SNOOP_COMMAND                                    0x544
+#define X1_SNOOP_ADDRESS                                    0x548
+#define X1_SNOOP_COMMAND                                    0x54c
+
+
+/****************************************/
+/* Device Parameters					*/
+/****************************************/
+
+#define DEVICE_BANK0PARAMETERS								0x45c
+#define DEVICE_BANK1PARAMETERS								0x460
+#define DEVICE_BANK2PARAMETERS								0x464
+#define DEVICE_BANK3PARAMETERS								0x468
+#define DEVICE_BOOT_BANK_PARAMETERS							0x46c
+#define DEVICE_CONTROL                                      0x4c0
+#define DEVICE_CROSS_BAR_CONTROL_LOW                        0x4c8
+#define DEVICE_CROSS_BAR_CONTROL_HIGH                       0x4cc
+#define DEVICE_CROSS_BAR_TIMEOUT                            0x4c4
+
+
+/****************************************/
+/* Device Interrupt 					*/
+/****************************************/
+
+#define DEVICE_INTERRUPT_CAUSE                              0x4d0
+#define DEVICE_INTERRUPT_MASK                               0x4d4
+#define DEVICE_ERROR_ADDRESS                                0x4d8
+
+/****************************************/
+/* DMA Record							*/
+/****************************************/
+
+#define CHANNEL0_DMA_BYTE_COUNT						0x800
+#define CHANNEL1_DMA_BYTE_COUNT	 							0x804
+#define CHANNEL2_DMA_BYTE_COUNT	 							0x808
+#define CHANNEL3_DMA_BYTE_COUNT	 							0x80C
+#define CHANNEL4_DMA_BYTE_COUNT								0x900
+#define CHANNEL5_DMA_BYTE_COUNT	 							0x904
+#define CHANNEL6_DMA_BYTE_COUNT	 							0x908
+#define CHANNEL7_DMA_BYTE_COUNT	 							0x90C
+#define CHANNEL0_DMA_SOURCE_ADDRESS							0x810
+#define CHANNEL1_DMA_SOURCE_ADDRESS							0x814
+#define CHANNEL2_DMA_SOURCE_ADDRESS							0x818
+#define CHANNEL3_DMA_SOURCE_ADDRESS							0x81C
+#define CHANNEL4_DMA_SOURCE_ADDRESS							0x910
+#define CHANNEL5_DMA_SOURCE_ADDRESS							0x914
+#define CHANNEL6_DMA_SOURCE_ADDRESS							0x918
+#define CHANNEL7_DMA_SOURCE_ADDRESS							0x91C
+#define CHANNEL0_DMA_DESTINATION_ADDRESS					0x820
+#define CHANNEL1_DMA_DESTINATION_ADDRESS					0x824
+#define CHANNEL2_DMA_DESTINATION_ADDRESS					0x828
+#define CHANNEL3_DMA_DESTINATION_ADDRESS					0x82C
+#define CHANNEL4_DMA_DESTINATION_ADDRESS					0x920
+#define CHANNEL5_DMA_DESTINATION_ADDRESS					0x924
+#define CHANNEL6_DMA_DESTINATION_ADDRESS					0x928
+#define CHANNEL7_DMA_DESTINATION_ADDRESS					0x92C
+#define CHANNEL0NEXT_RECORD_POINTER							0x830
+#define CHANNEL1NEXT_RECORD_POINTER							0x834
+#define CHANNEL2NEXT_RECORD_POINTER							0x838
+#define CHANNEL3NEXT_RECORD_POINTER							0x83C
+#define CHANNEL4NEXT_RECORD_POINTER							0x930
+#define CHANNEL5NEXT_RECORD_POINTER							0x934
+#define CHANNEL6NEXT_RECORD_POINTER							0x938
+#define CHANNEL7NEXT_RECORD_POINTER							0x93C
+#define CHANNEL0CURRENT_DESCRIPTOR_POINTER					0x870
+#define CHANNEL1CURRENT_DESCRIPTOR_POINTER					0x874
+#define CHANNEL2CURRENT_DESCRIPTOR_POINTER					0x878
+#define CHANNEL3CURRENT_DESCRIPTOR_POINTER					0x87C
+#define CHANNEL4CURRENT_DESCRIPTOR_POINTER					0x970
+#define CHANNEL5CURRENT_DESCRIPTOR_POINTER					0x974
+#define CHANNEL6CURRENT_DESCRIPTOR_POINTER					0x978
+#define CHANNEL7CURRENT_DESCRIPTOR_POINTER					0x97C
+#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS                0x890
+#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS                0x894
+#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS                0x898
+#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS                0x89c
+#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS                0x990
+#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS                0x994
+#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS                0x998
+#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS                0x99c
+#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x8a0
+#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x8a4
+#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x8a8
+#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x8ac
+#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x9a0
+#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x9a4
+#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x9a8
+#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS           0x9ac
+#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b0
+#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b4
+#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8b8
+#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x8bc
+#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b0
+#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b4
+#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9b8
+#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS   0x9bc
+
+/****************************************/
+/* DMA Channel Control					*/
+/****************************************/
+
+#define CHANNEL0CONTROL 									0x840
+#define CHANNEL0CONTROL_HIGH								0x880
+#define CHANNEL1CONTROL 									0x844
+#define CHANNEL1CONTROL_HIGH								0x884
+#define CHANNEL2CONTROL 									0x848
+#define CHANNEL2CONTROL_HIGH								0x888
+#define CHANNEL3CONTROL 									0x84C
+#define CHANNEL3CONTROL_HIGH								0x88C
+
+#define CHANNEL4CONTROL 									0x940
+#define CHANNEL4CONTROL_HIGH								0x980
+#define CHANNEL5CONTROL 									0x944
+#define CHANNEL5CONTROL_HIGH								0x984
+#define CHANNEL6CONTROL 									0x948
+#define CHANNEL6CONTROL_HIGH								0x988
+#define CHANNEL7CONTROL 									0x94C
+#define CHANNEL7CONTROL_HIGH								0x98C
+
+
+/****************************************/
+/* DMA Arbiter							*/
+/****************************************/
+
+#define ARBITER_CONTROL_0_3									0x860
+#define ARBITER_CONTROL_4_7									0x960
+
+
+/****************************************/
+/* DMA Interrupt						*/
+/****************************************/
+
+#define CHANELS0_3_INTERRUPT_CAUSE                          0x8c0
+#define CHANELS0_3_INTERRUPT_MASK                           0x8c4
+#define CHANELS0_3_ERROR_ADDRESS                            0x8c8
+#define CHANELS0_3_ERROR_SELECT                             0x8cc
+#define CHANELS4_7_INTERRUPT_CAUSE                          0x9c0
+#define CHANELS4_7_INTERRUPT_MASK                           0x9c4
+#define CHANELS4_7_ERROR_ADDRESS                            0x9c8
+#define CHANELS4_7_ERROR_SELECT                             0x9cc
+
+
+/****************************************/
+/* DMA Debug (for internal use)         */
+/****************************************/
+
+#define DMA_X0_ADDRESS                                      0x8e0
+#define DMA_X0_COMMAND_AND_ID                               0x8e4
+#define DMA_X0_WRITE_DATA_LOW                               0x8e8
+#define DMA_X0_WRITE_DATA_HIGH                              0x8ec
+#define DMA_X0_WRITE_BYTE_ENABLE                            0x8f8
+#define DMA_X0_READ_DATA_LOW                                0x8f0
+#define DMA_X0_READ_DATA_HIGH                               0x8f4
+#define DMA_X0_READ_ID                                      0x8fc
+#define DMA_X1_ADDRESS                                      0x9e0
+#define DMA_X1_COMMAND_AND_ID                               0x9e4
+#define DMA_X1_WRITE_DATA_LOW                               0x9e8
+#define DMA_X1_WRITE_DATA_HIGH                              0x9ec
+#define DMA_X1_WRITE_BYTE_ENABLE                            0x9f8
+#define DMA_X1_READ_DATA_LOW                                0x9f0
+#define DMA_X1_READ_DATA_HIGH                               0x9f4
+#define DMA_X1_READ_ID                                      0x9fc
+
+/****************************************/
+/* Timer_Counter 						*/
+/****************************************/
+
+#define TIMER_COUNTER0										0x850
+#define TIMER_COUNTER1										0x854
+#define TIMER_COUNTER2										0x858
+#define TIMER_COUNTER3										0x85C
+#define TIMER_COUNTER_0_3_CONTROL							0x864
+#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE					0x868
+#define TIMER_COUNTER_0_3_INTERRUPT_MASK      				0x86c
+#define TIMER_COUNTER4										0x950
+#define TIMER_COUNTER5										0x954
+#define TIMER_COUNTER6										0x958
+#define TIMER_COUNTER7										0x95C
+#define TIMER_COUNTER_4_7_CONTROL							0x964
+#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE					0x968
+#define TIMER_COUNTER_4_7_INTERRUPT_MASK      				0x96c
+
+/****************************************/
+/* PCI Slave Address Decoding           */
+/****************************************/
+
+#define PCI_0SCS_0_BANK_SIZE								0xc08
+#define PCI_1SCS_0_BANK_SIZE								0xc88
+#define PCI_0SCS_1_BANK_SIZE								0xd08
+#define PCI_1SCS_1_BANK_SIZE								0xd88
+#define PCI_0SCS_2_BANK_SIZE								0xc0c
+#define PCI_1SCS_2_BANK_SIZE								0xc8c
+#define PCI_0SCS_3_BANK_SIZE								0xd0c
+#define PCI_1SCS_3_BANK_SIZE								0xd8c
+#define PCI_0CS_0_BANK_SIZE							    	0xc10
+#define PCI_1CS_0_BANK_SIZE							    	0xc90
+#define PCI_0CS_1_BANK_SIZE							    	0xd10
+#define PCI_1CS_1_BANK_SIZE							    	0xd90
+#define PCI_0CS_2_BANK_SIZE							    	0xd18
+#define PCI_1CS_2_BANK_SIZE							    	0xd98
+#define PCI_0CS_3_BANK_SIZE					        		0xc14
+#define PCI_1CS_3_BANK_SIZE					        		0xc94
+#define PCI_0CS_BOOT_BANK_SIZE							    0xd14
+#define PCI_1CS_BOOT_BANK_SIZE							    0xd94
+#define PCI_0P2P_MEM0_BAR_SIZE                              0xd1c
+#define PCI_1P2P_MEM0_BAR_SIZE                              0xd9c
+#define PCI_0P2P_MEM1_BAR_SIZE                              0xd20
+#define PCI_1P2P_MEM1_BAR_SIZE                              0xda0
+#define PCI_0P2P_I_O_BAR_SIZE                               0xd24
+#define PCI_1P2P_I_O_BAR_SIZE                               0xda4
+#define PCI_0CPU_BAR_SIZE                                   0xd28
+#define PCI_1CPU_BAR_SIZE                                   0xda8
+#define PCI_0DAC_SCS_0_BANK_SIZE                            0xe00
+#define PCI_1DAC_SCS_0_BANK_SIZE                            0xe80
+#define PCI_0DAC_SCS_1_BANK_SIZE                            0xe04
+#define PCI_1DAC_SCS_1_BANK_SIZE                            0xe84
+#define PCI_0DAC_SCS_2_BANK_SIZE                            0xe08
+#define PCI_1DAC_SCS_2_BANK_SIZE                            0xe88
+#define PCI_0DAC_SCS_3_BANK_SIZE                            0xe0c
+#define PCI_1DAC_SCS_3_BANK_SIZE                            0xe8c
+#define PCI_0DAC_CS_0_BANK_SIZE                             0xe10
+#define PCI_1DAC_CS_0_BANK_SIZE                             0xe90
+#define PCI_0DAC_CS_1_BANK_SIZE                             0xe14
+#define PCI_1DAC_CS_1_BANK_SIZE                             0xe94
+#define PCI_0DAC_CS_2_BANK_SIZE                             0xe18
+#define PCI_1DAC_CS_2_BANK_SIZE                             0xe98
+#define PCI_0DAC_CS_3_BANK_SIZE                             0xe1c
+#define PCI_1DAC_CS_3_BANK_SIZE                             0xe9c
+#define PCI_0DAC_BOOTCS_BANK_SIZE                           0xe20
+#define PCI_1DAC_BOOTCS_BANK_SIZE                           0xea0
+#define PCI_0DAC_P2P_MEM0_BAR_SIZE                          0xe24
+#define PCI_1DAC_P2P_MEM0_BAR_SIZE                          0xea4
+#define PCI_0DAC_P2P_MEM1_BAR_SIZE                          0xe28
+#define PCI_1DAC_P2P_MEM1_BAR_SIZE                          0xea8
+#define PCI_0DAC_CPU_BAR_SIZE                               0xe2c
+#define PCI_1DAC_CPU_BAR_SIZE                               0xeac
+#define PCI_0EXPANSION_ROM_BAR_SIZE                         0xd2c
+#define PCI_1EXPANSION_ROM_BAR_SIZE                         0xdac
+#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 					0xc3c
+#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 					0xcbc
+#define PCI_0SCS_0_BASE_ADDRESS_REMAP						0xc48
+#define PCI_1SCS_0_BASE_ADDRESS_REMAP						0xcc8
+#define PCI_0SCS_1_BASE_ADDRESS_REMAP						0xd48
+#define PCI_1SCS_1_BASE_ADDRESS_REMAP						0xdc8
+#define PCI_0SCS_2_BASE_ADDRESS_REMAP						0xc4c
+#define PCI_1SCS_2_BASE_ADDRESS_REMAP						0xccc
+#define PCI_0SCS_3_BASE_ADDRESS_REMAP						0xd4c
+#define PCI_1SCS_3_BASE_ADDRESS_REMAP						0xdcc
+#define PCI_0CS_0_BASE_ADDRESS_REMAP						0xc50
+#define PCI_1CS_0_BASE_ADDRESS_REMAP						0xcd0
+#define PCI_0CS_1_BASE_ADDRESS_REMAP						0xd50
+#define PCI_1CS_1_BASE_ADDRESS_REMAP						0xdd0
+#define PCI_0CS_2_BASE_ADDRESS_REMAP						0xd58
+#define PCI_1CS_2_BASE_ADDRESS_REMAP						0xdd8
+#define PCI_0CS_3_BASE_ADDRESS_REMAP           				0xc54
+#define PCI_1CS_3_BASE_ADDRESS_REMAP           				0xcd4
+#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP      				0xd54
+#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP      				0xdd4
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW                0xd5c
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW                0xddc
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH               0xd60
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH               0xde0
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW                0xd64
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW                0xde4
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH               0xd68
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH               0xde8
+#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP                     0xd6c
+#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP                     0xdec
+#define PCI_0CPU_BASE_ADDRESS_REMAP                         0xd70
+#define PCI_1CPU_BASE_ADDRESS_REMAP                         0xdf0
+#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP                   0xf00
+#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP                   0xff0
+#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP                   0xf04
+#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP                   0xf84
+#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP                   0xf08
+#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP                   0xf88
+#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP                   0xf0c
+#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP                   0xf8c
+#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP                    0xf10
+#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP                    0xf90
+#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP                    0xf14
+#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP                    0xf94
+#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP                    0xf18
+#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP                    0xf98
+#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP                    0xf1c
+#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP                    0xf9c
+#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP                  0xf20
+#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP                  0xfa0
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW            0xf24
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW            0xfa4
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH           0xf28
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH           0xfa8
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW            0xf2c
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW            0xfac
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH           0xf30
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH           0xfb0
+#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP                     0xf34
+#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP                     0xfb4
+#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP               0xf38
+#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP               0xfb8
+#define PCI_0ADDRESS_DECODE_CONTROL                         0xd3c
+#define PCI_1ADDRESS_DECODE_CONTROL                         0xdbc
+
+/****************************************/
+/* PCI Control                          */
+/****************************************/
+
+#define PCI_0COMMAND										0xc00
+#define PCI_1COMMAND										0xc80
+#define PCI_0MODE                                           0xd00
+#define PCI_1MODE                                           0xd80
+#define PCI_0TIMEOUT_RETRY									0xc04
+#define PCI_1TIMEOUT_RETRY									0xc84
+#define PCI_0READ_BUFFER_DISCARD_TIMER                      0xd04
+#define PCI_1READ_BUFFER_DISCARD_TIMER                      0xd84
+#define MSI_0TRIGGER_TIMER                                  0xc38
+#define MSI_1TRIGGER_TIMER                                  0xcb8
+#define PCI_0ARBITER_CONTROL                                0x1d00
+#define PCI_1ARBITER_CONTROL                                0x1d80
+/* changing untill here */
+#define PCI_0CROSS_BAR_CONTROL_LOW                           0x1d08
+#define PCI_0CROSS_BAR_CONTROL_HIGH                          0x1d0c
+#define PCI_0CROSS_BAR_TIMEOUT                               0x1d04
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW             0x1d18
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH            0x1d1c
+#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER                   0x1d10
+#define PCI_0P2P_CONFIGURATION                               0x1d14
+#define PCI_0ACCESS_CONTROL_BASE_0_LOW                       0x1e00
+#define PCI_0ACCESS_CONTROL_BASE_0_HIGH                      0x1e04
+#define PCI_0ACCESS_CONTROL_TOP_0                            0x1e08
+#define PCI_0ACCESS_CONTROL_BASE_1_LOW                       0x1e10
+#define PCI_0ACCESS_CONTROL_BASE_1_HIGH                      0x1e14
+#define PCI_0ACCESS_CONTROL_TOP_1                            0x1e18
+#define PCI_0ACCESS_CONTROL_BASE_2_LOW                       0x1e20
+#define PCI_0ACCESS_CONTROL_BASE_2_HIGH                      0x1e24
+#define PCI_0ACCESS_CONTROL_TOP_2                            0x1e28
+#define PCI_0ACCESS_CONTROL_BASE_3_LOW                       0x1e30
+#define PCI_0ACCESS_CONTROL_BASE_3_HIGH                      0x1e34
+#define PCI_0ACCESS_CONTROL_TOP_3                            0x1e38
+#define PCI_0ACCESS_CONTROL_BASE_4_LOW                       0x1e40
+#define PCI_0ACCESS_CONTROL_BASE_4_HIGH                      0x1e44
+#define PCI_0ACCESS_CONTROL_TOP_4                            0x1e48
+#define PCI_0ACCESS_CONTROL_BASE_5_LOW                       0x1e50
+#define PCI_0ACCESS_CONTROL_BASE_5_HIGH                      0x1e54
+#define PCI_0ACCESS_CONTROL_TOP_5                            0x1e58
+#define PCI_0ACCESS_CONTROL_BASE_6_LOW                       0x1e60
+#define PCI_0ACCESS_CONTROL_BASE_6_HIGH                      0x1e64
+#define PCI_0ACCESS_CONTROL_TOP_6                            0x1e68
+#define PCI_0ACCESS_CONTROL_BASE_7_LOW                       0x1e70
+#define PCI_0ACCESS_CONTROL_BASE_7_HIGH                      0x1e74
+#define PCI_0ACCESS_CONTROL_TOP_7                            0x1e78
+#define PCI_1CROSS_BAR_CONTROL_LOW                           0x1d88
+#define PCI_1CROSS_BAR_CONTROL_HIGH                          0x1d8c
+#define PCI_1CROSS_BAR_TIMEOUT                               0x1d84
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW             0x1d98
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH            0x1d9c
+#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER                   0x1d90
+#define PCI_1P2P_CONFIGURATION                               0x1d94
+#define PCI_1ACCESS_CONTROL_BASE_0_LOW                       0x1e80
+#define PCI_1ACCESS_CONTROL_BASE_0_HIGH                      0x1e84
+#define PCI_1ACCESS_CONTROL_TOP_0                            0x1e88
+#define PCI_1ACCESS_CONTROL_BASE_1_LOW                       0x1e90
+#define PCI_1ACCESS_CONTROL_BASE_1_HIGH                      0x1e94
+#define PCI_1ACCESS_CONTROL_TOP_1                            0x1e98
+#define PCI_1ACCESS_CONTROL_BASE_2_LOW                       0x1ea0
+#define PCI_1ACCESS_CONTROL_BASE_2_HIGH                      0x1ea4
+#define PCI_1ACCESS_CONTROL_TOP_2                            0x1ea8
+#define PCI_1ACCESS_CONTROL_BASE_3_LOW                       0x1eb0
+#define PCI_1ACCESS_CONTROL_BASE_3_HIGH                      0x1eb4
+#define PCI_1ACCESS_CONTROL_TOP_3                            0x1eb8
+#define PCI_1ACCESS_CONTROL_BASE_4_LOW                       0x1ec0
+#define PCI_1ACCESS_CONTROL_BASE_4_HIGH                      0x1ec4
+#define PCI_1ACCESS_CONTROL_TOP_4                            0x1ec8
+#define PCI_1ACCESS_CONTROL_BASE_5_LOW                       0x1ed0
+#define PCI_1ACCESS_CONTROL_BASE_5_HIGH                      0x1ed4
+#define PCI_1ACCESS_CONTROL_TOP_5                            0x1ed8
+#define PCI_1ACCESS_CONTROL_BASE_6_LOW                       0x1ee0
+#define PCI_1ACCESS_CONTROL_BASE_6_HIGH                      0x1ee4
+#define PCI_1ACCESS_CONTROL_TOP_6                            0x1ee8
+#define PCI_1ACCESS_CONTROL_BASE_7_LOW                       0x1ef0
+#define PCI_1ACCESS_CONTROL_BASE_7_HIGH                      0x1ef4
+#define PCI_1ACCESS_CONTROL_TOP_7                            0x1ef8
+
+/****************************************/
+/* PCI Snoop Control                    */
+/****************************************/
+
+#define PCI_0SNOOP_CONTROL_BASE_0_LOW                        0x1f00
+#define PCI_0SNOOP_CONTROL_BASE_0_HIGH                       0x1f04
+#define PCI_0SNOOP_CONTROL_TOP_0                             0x1f08
+#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW                      0x1f10
+#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH                     0x1f14
+#define PCI_0SNOOP_CONTROL_TOP_1                             0x1f18
+#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW                      0x1f20
+#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH                     0x1f24
+#define PCI_0SNOOP_CONTROL_TOP_2                             0x1f28
+#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW                      0x1f30
+#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH                     0x1f34
+#define PCI_0SNOOP_CONTROL_TOP_3                             0x1f38
+#define PCI_1SNOOP_CONTROL_BASE_0_LOW                        0x1f80
+#define PCI_1SNOOP_CONTROL_BASE_0_HIGH                       0x1f84
+#define PCI_1SNOOP_CONTROL_TOP_0                             0x1f88
+#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW                      0x1f90
+#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH                     0x1f94
+#define PCI_1SNOOP_CONTROL_TOP_1                             0x1f98
+#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW                      0x1fa0
+#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH                     0x1fa4
+#define PCI_1SNOOP_CONTROL_TOP_2                             0x1fa8
+#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW                      0x1fb0
+#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH                     0x1fb4
+#define PCI_1SNOOP_CONTROL_TOP_3                             0x1fb8
+
+/****************************************/
+/* PCI Configuration Address            */
+/****************************************/
+
+#define PCI_0CONFIGURATION_ADDRESS 							0xcf8
+#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER           	0xcfc
+#define PCI_1CONFIGURATION_ADDRESS 							0xc78
+#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER           	0xc7c
+#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER			0xc34
+#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER			0xcb4
+
+/****************************************/
+/* PCI Error Report                     */
+/****************************************/
+
+#define PCI_0SERR_MASK										 0xc28
+#define PCI_0ERROR_ADDRESS_LOW                               0x1d40
+#define PCI_0ERROR_ADDRESS_HIGH                              0x1d44
+#define PCI_0ERROR_DATA_LOW                                  0x1d48
+#define PCI_0ERROR_DATA_HIGH                                 0x1d4c
+#define PCI_0ERROR_COMMAND                                   0x1d50
+#define PCI_0ERROR_CAUSE                                     0x1d58
+#define PCI_0ERROR_MASK                                      0x1d5c
+#define PCI_1SERR_MASK										 0xca8
+#define PCI_1ERROR_ADDRESS_LOW                               0x1dc0
+#define PCI_1ERROR_ADDRESS_HIGH                              0x1dc4
+#define PCI_1ERROR_DATA_LOW                                  0x1dc8
+#define PCI_1ERROR_DATA_HIGH                                 0x1dcc
+#define PCI_1ERROR_COMMAND                                   0x1dd0
+#define PCI_1ERROR_CAUSE                                     0x1dd8
+#define PCI_1ERROR_MASK                                      0x1ddc
+
+
+/****************************************/
+/* Lslave Debug  (for internal use)     */
+/****************************************/
+
+#define L_SLAVE_X0_ADDRESS                                  0x1d20
+#define L_SLAVE_X0_COMMAND_AND_ID                           0x1d24
+#define L_SLAVE_X1_ADDRESS                                  0x1d28
+#define L_SLAVE_X1_COMMAND_AND_ID                           0x1d2c
+#define L_SLAVE_WRITE_DATA_LOW                              0x1d30
+#define L_SLAVE_WRITE_DATA_HIGH                             0x1d34
+#define L_SLAVE_WRITE_BYTE_ENABLE                           0x1d60
+#define L_SLAVE_READ_DATA_LOW                               0x1d38
+#define L_SLAVE_READ_DATA_HIGH                              0x1d3c
+#define L_SLAVE_READ_ID                                     0x1d64
+
+/****************************************/
+/* PCI Configuration Function 0         */
+/****************************************/
+
+#define PCI_DEVICE_AND_VENDOR_ID 							0x000
+#define PCI_STATUS_AND_COMMAND								0x004
+#define PCI_CLASS_CODE_AND_REVISION_ID				        0x008
+#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 		0x00C
+#define PCI_SCS_0_BASE_ADDRESS	    						0x010
+#define PCI_SCS_1_BASE_ADDRESS 							    0x014
+#define PCI_SCS_2_BASE_ADDRESS 							    0x018
+#define PCI_SCS_3_BASE_ADDRESS      						0x01C
+#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS	0x020
+#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS		0x024
+#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID			0x02C
+#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER				0x030
+#define PCI_CAPABILTY_LIST_POINTER                          0x034
+#define PCI_INTERRUPT_PIN_AND_LINE 						    0x03C
+#define PCI_POWER_MANAGEMENT_CAPABILITY                     0x040
+#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL             0x044
+#define PCI_VPD_ADDRESS                                     0x048
+#define PCI_VPD_DATA                                        0x04c
+#define PCI_MSI_MESSAGE_CONTROL                             0x050
+#define PCI_MSI_MESSAGE_ADDRESS                             0x054
+#define PCI_MSI_MESSAGE_UPPER_ADDRESS                       0x058
+#define PCI_MSI_MESSAGE_DATA                                0x05c
+#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY                 0x058
+
+/****************************************/
+/* PCI Configuration Function 1         */
+/****************************************/
+
+#define PCI_CS_0_BASE_ADDRESS	    						0x110
+#define PCI_CS_1_BASE_ADDRESS 							    0x114
+#define PCI_CS_2_BASE_ADDRESS 							    0x118
+#define PCI_CS_3_BASE_ADDRESS     					        0x11c
+#define PCI_BOOTCS_BASE_ADDRESS                     	    0x120
+
+/****************************************/
+/* PCI Configuration Function 2         */
+/****************************************/
+
+#define PCI_P2P_MEM0_BASE_ADDRESS	    					0x210
+#define PCI_P2P_MEM1_BASE_ADDRESS 							0x214
+#define PCI_P2P_I_O_BASE_ADDRESS 							0x218
+#define PCI_CPU_BASE_ADDRESS      						    0x21c
+
+/****************************************/
+/* PCI Configuration Function 4         */
+/****************************************/
+
+#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 						0x410
+#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH					    0x414
+#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW   				    0x418
+#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH  				    0x41c
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW              	    0x420
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH             	    0x424
+
+
+/****************************************/
+/* PCI Configuration Function 5         */
+/****************************************/
+
+#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 						0x510
+#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH					    0x514
+#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW   				    0x518
+#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH  				    0x51c
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW              	    0x520
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH             	    0x524
+
+
+/****************************************/
+/* PCI Configuration Function 6         */
+/****************************************/
+
+#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 						0x610
+#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH					    0x614
+#define PCI_DAC_CS_1_BASE_ADDRESS_LOW   				    0x618
+#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH  				    0x61c
+#define PCI_DAC_CS_2_BASE_ADDRESS_LOW            	        0x620
+#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH           	        0x624
+
+/****************************************/
+/* PCI Configuration Function 7         */
+/****************************************/
+
+#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 						0x710
+#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH					    0x714
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW   				    0x718
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH  				    0x71c
+#define PCI_DAC_CPU_BASE_ADDRESS_LOW            	        0x720
+#define PCI_DAC_CPU_BASE_ADDRESS_HIGH           	        0x724
+
+/****************************************/
+/* Interrupts 				*/
+/****************************************/
+
+#define LOW_INTERRUPT_CAUSE_REGISTER   						0xc18
+#define HIGH_INTERRUPT_CAUSE_REGISTER						0xc68
+#define CPU_INTERRUPT_MASK_REGISTER_LOW						0xc1c
+#define CPU_INTERRUPT_MASK_REGISTER_HIGH					0xc6c
+#define CPU_SELECT_CAUSE_REGISTER							0xc70
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW				0xc24
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH				0xc64
+#define PCI_0SELECT_CAUSE                                   0xc74
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW				0xca4
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH				0xce4
+#define PCI_1SELECT_CAUSE                                   0xcf4
+#define CPU_INT_0_MASK                                      0xe60
+#define CPU_INT_1_MASK                                      0xe64
+#define CPU_INT_2_MASK                                      0xe68
+#define CPU_INT_3_MASK                                      0xe6c
+
+/****************************************/
+/* I20 Support registers				*/
+/****************************************/
+
+#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE					0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE  				0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 				0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE  				0x01C
+#define INBOUND_DOORBELL_REGISTER_PCI_SIDE  				0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE  			0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE			0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 				0x02C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE   		0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE   		0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE  		0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE   	0x044
+#define QUEUE_CONTROL_REGISTER_PCI_SIDE 					0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 				0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE			0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE  		0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 		0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 		0x06C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE		0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE		0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE		0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE		0x07C
+
+#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE					0x1C10
+#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE  				0x1C14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 				0x1C18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE  				0x1C1C
+#define INBOUND_DOORBELL_REGISTER_CPU_SIDE  				0x1C20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE  			0x1C24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE			0x1C28
+#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 				0x1C2C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE   		0x1C30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE   		0x1C34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE  		0x1C40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE   	0x1C44
+#define QUEUE_CONTROL_REGISTER_CPU_SIDE 					0x1C50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 				0x1C54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE			0x1C60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE  		0x1C64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 		0x1C68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 		0x1C6C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE		0x1C78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE		0x1C7C
+
+/****************************************/
+/* Communication Unit Registers         */
+/****************************************/
+
+#define ETHERNET_0_ADDRESS_CONTROL_LOW						0xf200
+#define ETHERNET_0_ADDRESS_CONTROL_HIGH                     0xf204
+#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf208
+#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf20c
+#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf210
+#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf214
+#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS              0xf218
+#define ETHERNET_1_ADDRESS_CONTROL_LOW                      0xf220
+#define ETHERNET_1_ADDRESS_CONTROL_HIGH                     0xf224
+#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf228
+#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf22c
+#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf230
+#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf234
+#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS              0xf238
+#define ETHERNET_2_ADDRESS_CONTROL_LOW                      0xf240
+#define ETHERNET_2_ADDRESS_CONTROL_HIGH                     0xf244
+#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS          0xf248
+#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS         0xf24c
+#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS      0xf250
+#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS     0xf254
+#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS              0xf258
+#define MPSC_0_ADDRESS_CONTROL_LOW                          0xf280
+#define MPSC_0_ADDRESS_CONTROL_HIGH                         0xf284
+#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf288
+#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf28c
+#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf290
+#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf294
+#define MPSC_1_ADDRESS_CONTROL_LOW                          0xf2c0
+#define MPSC_1_ADDRESS_CONTROL_HIGH                         0xf2c4
+#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS              0xf2c8
+#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS             0xf2cc
+#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS          0xf2d0
+#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS         0xf2d4
+#define SERIAL_INIT_PCI_HIGH_ADDRESS                        0xf320
+#define SERIAL_INIT_LAST_DATA                               0xf324
+#define SERIAL_INIT_STATUS_AND_CONTROL                      0xf328
+#define COMM_UNIT_ARBITER_CONTROL                           0xf300
+#define COMM_UNIT_CROSS_BAR_TIMEOUT                         0xf304
+#define COMM_UNIT_INTERRUPT_CAUSE                           0xf310
+#define COMM_UNIT_INTERRUPT_MASK                            0xf314
+#define COMM_UNIT_ERROR_ADDRESS                             0xf314
+
+/****************************************/
+/* Cunit Debug  (for internal use)     */
+/****************************************/
+
+#define CUNIT_ADDRESS                                       0xf340
+#define CUNIT_COMMAND_AND_ID                                0xf344
+#define CUNIT_WRITE_DATA_LOW                                0xf348
+#define CUNIT_WRITE_DATA_HIGH                               0xf34c
+#define CUNIT_WRITE_BYTE_ENABLE                             0xf358
+#define CUNIT_READ_DATA_LOW                                 0xf350
+#define CUNIT_READ_DATA_HIGH                                0xf354
+#define CUNIT_READ_ID                                       0xf35c
+
+/****************************************/
+/* Fast Ethernet Unit Registers         */
+/****************************************/
+
+/* Ethernet */
+
+#define ETHERNET_PHY_ADDRESS_REGISTER                       0x2000
+#define ETHERNET_SMI_REGISTER                               0x2010
+
+/* Ethernet 0 */
+
+#define ETHERNET0_PORT_CONFIGURATION_REGISTER               0x2400
+#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER        0x2408
+#define ETHERNET0_PORT_COMMAND_REGISTER                     0x2410
+#define ETHERNET0_PORT_STATUS_REGISTER                      0x2418
+#define ETHERNET0_SERIAL_PARAMETRS_REGISTER                 0x2420
+#define ETHERNET0_HASH_TABLE_POINTER_REGISTER               0x2428
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW           0x2430
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH          0x2438
+#define ETHERNET0_SDMA_CONFIGURATION_REGISTER               0x2440
+#define ETHERNET0_SDMA_COMMAND_REGISTER                     0x2448
+#define ETHERNET0_INTERRUPT_CAUSE_REGISTER                  0x2450
+#define ETHERNET0_INTERRUPT_MASK_REGISTER                   0x2458
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0              0x2480
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1              0x2484
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2              0x2488
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3              0x248c
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0            0x24a0
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1            0x24a4
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2            0x24a8
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3            0x24ac
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0            0x24e0
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1            0x24e4
+#define ETHERNET0_MIB_COUNTER_BASE                          0x2500
+
+/* Ethernet 1 */
+
+#define ETHERNET1_PORT_CONFIGURATION_REGISTER               0x2800
+#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER        0x2808
+#define ETHERNET1_PORT_COMMAND_REGISTER                     0x2810
+#define ETHERNET1_PORT_STATUS_REGISTER                      0x2818
+#define ETHERNET1_SERIAL_PARAMETRS_REGISTER                 0x2820
+#define ETHERNET1_HASH_TABLE_POINTER_REGISTER               0x2828
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW           0x2830
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH          0x2838
+#define ETHERNET1_SDMA_CONFIGURATION_REGISTER               0x2840
+#define ETHERNET1_SDMA_COMMAND_REGISTER                     0x2848
+#define ETHERNET1_INTERRUPT_CAUSE_REGISTER                  0x2850
+#define ETHERNET1_INTERRUPT_MASK_REGISTER                   0x2858
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0              0x2880
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1              0x2884
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2              0x2888
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3              0x288c
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0            0x28a0
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1            0x28a4
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2            0x28a8
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3            0x28ac
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0            0x28e0
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1            0x28e4
+#define ETHERNET1_MIB_COUNTER_BASE                          0x2900
+
+/* Ethernet 2 */
+
+#define ETHERNET2_PORT_CONFIGURATION_REGISTER               0x2c00
+#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER        0x2c08
+#define ETHERNET2_PORT_COMMAND_REGISTER                     0x2c10
+#define ETHERNET2_PORT_STATUS_REGISTER                      0x2c18
+#define ETHERNET2_SERIAL_PARAMETRS_REGISTER                 0x2c20
+#define ETHERNET2_HASH_TABLE_POINTER_REGISTER               0x2c28
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW           0x2c30
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH          0x2c38
+#define ETHERNET2_SDMA_CONFIGURATION_REGISTER               0x2c40
+#define ETHERNET2_SDMA_COMMAND_REGISTER                     0x2c48
+#define ETHERNET2_INTERRUPT_CAUSE_REGISTER                  0x2c50
+#define ETHERNET2_INTERRUPT_MASK_REGISTER                   0x2c58
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0              0x2c80
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1              0x2c84
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2              0x2c88
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3              0x2c8c
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0            0x2ca0
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1            0x2ca4
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2            0x2ca8
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3            0x2cac
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0            0x2ce0
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1            0x2ce4
+#define ETHERNET2_MIB_COUNTER_BASE                          0x2d00
+
+/****************************************/
+/* SDMA Registers                       */
+/****************************************/
+
+#define SDMA_GROUP_CONFIGURATION_REGISTER                   0xb1f0
+#define CHANNEL0_CONFIGURATION_REGISTER                     0x4000
+#define CHANNEL0_COMMAND_REGISTER                           0x4008
+#define CHANNEL0_RX_CMD_STATUS                              0x4800
+#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES                 0x4804
+#define CHANNEL0_RX_BUFFER_POINTER                          0x4808
+#define CHANNEL0_RX_NEXT_POINTER                            0x480c
+#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER              0x4810
+#define CHANNEL0_TX_CMD_STATUS                              0x4C00
+#define CHANNEL0_TX_PACKET_SIZE                             0x4C04
+#define CHANNEL0_TX_BUFFER_POINTER                          0x4C08
+#define CHANNEL0_TX_NEXT_POINTER                            0x4C0c
+#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER              0x4c10
+#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER                0x4c14
+#define CHANNEL1_CONFIGURATION_REGISTER                     0x5000
+#define CHANNEL1_COMMAND_REGISTER                           0x5008
+#define CHANNEL1_RX_CMD_STATUS                              0x5800
+#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES                 0x5804
+#define CHANNEL1_RX_BUFFER_POINTER                          0x5808
+#define CHANNEL1_RX_NEXT_POINTER                            0x580c
+#define CHANNEL1_TX_CMD_STATUS                              0x5C00
+#define CHANNEL1_TX_PACKET_SIZE                             0x5C04
+#define CHANNEL1_TX_BUFFER_POINTER                          0x5C08
+#define CHANNEL1_TX_NEXT_POINTER                            0x5C0c
+#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER              0x5810
+#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER              0x5c10
+#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER                0x5c14
+#define CHANNEL2_CONFIGURATION_REGISTER                     0x6000
+#define CHANNEL2_COMMAND_REGISTER                           0x6008
+#define CHANNEL2_RX_CMD_STATUS                              0x6800
+#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES                 0x6804
+#define CHANNEL2_RX_BUFFER_POINTER                          0x6808
+#define CHANNEL2_RX_NEXT_POINTER                            0x680c
+#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER              0x6810
+#define CHANNEL2_TX_CMD_STATUS                              0x6C00
+#define CHANNEL2_TX_PACKET_SIZE                             0x6C04
+#define CHANNEL2_TX_BUFFER_POINTER                          0x6C08
+#define CHANNEL2_TX_NEXT_POINTER                            0x6C0c
+#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER              0x6810
+#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER              0x6c10
+#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER                0x6c14
+
+/* SDMA Interrupt */
+
+#define SDMA_CAUSE                                          0xb820
+#define SDMA_MASK                                           0xb8a0
+
+
+/****************************************/
+/* Baude Rate Generators Registers      */
+/****************************************/
+
+/* BRG 0 */
+
+#define BRG0_CONFIGURATION_REGISTER                         0xb200
+#define BRG0_BAUDE_TUNING_REGISTER                          0xb204
+
+/* BRG 1 */
+
+#define BRG1_CONFIGURATION_REGISTER                         0xb208
+#define BRG1_BAUDE_TUNING_REGISTER                          0xb20c
+
+/* BRG 2 */
+
+#define BRG2_CONFIGURATION_REGISTER                         0xb210
+#define BRG2_BAUDE_TUNING_REGISTER                          0xb214
+
+/* BRG Interrupts */
+
+#define BRG_CAUSE_REGISTER                                  0xb834
+#define BRG_MASK_REGISTER                                   0xb8b4
+
+/* MISC */
+
+#define MAIN_ROUTING_REGISTER                               0xb400
+#define RECEIVE_CLOCK_ROUTING_REGISTER                      0xb404
+#define TRANSMIT_CLOCK_ROUTING_REGISTER                     0xb408
+#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER            0xb40c
+#define WATCHDOG_CONFIGURATION_REGISTER                     0xb410
+#define WATCHDOG_VALUE_REGISTER                             0xb414
+
+
+/****************************************/
+/* Flex TDM Registers                   */
+/****************************************/
+
+/* FTDM Port */
+
+#define FLEXTDM_TRANSMIT_READ_POINTER                       0xa800
+#define FLEXTDM_RECEIVE_READ_POINTER                        0xa804
+#define FLEXTDM_CONFIGURATION_REGISTER                      0xa808
+#define FLEXTDM_AUX_CHANNELA_TX_REGISTER                    0xa80c
+#define FLEXTDM_AUX_CHANNELA_RX_REGISTER                    0xa810
+#define FLEXTDM_AUX_CHANNELB_TX_REGISTER                    0xa814
+#define FLEXTDM_AUX_CHANNELB_RX_REGISTER                    0xa818
+
+/* FTDM Interrupts */
+
+#define FTDM_CAUSE_REGISTER                                 0xb830
+#define FTDM_MASK_REGISTER                                  0xb8b0
+
+
+/****************************************/
+/* GPP Interface Registers              */
+/****************************************/
+
+#define GPP_IO_CONTROL                                      0xf100
+#define GPP_LEVEL_CONTROL                                   0xf110
+#define GPP_VALUE                                           0xf104
+#define GPP_INTERRUPT_CAUSE                                 0xf108
+#define GPP_INTERRUPT_MASK                                  0xf10c
+
+#define MPP_CONTROL0                                        0xf000
+#define MPP_CONTROL1                                        0xf004
+#define MPP_CONTROL2                                        0xf008
+#define MPP_CONTROL3                                        0xf00c
+#define DEBUG_PORT_MULTIPLEX                                0xf014
+#define SERIAL_PORT_MULTIPLEX                               0xf010
+
+/****************************************/
+/* I2C Registers                        */
+/****************************************/
+
+#define I2C_SLAVE_ADDRESS                                   0xc000
+#define I2C_EXTENDED_SLAVE_ADDRESS                          0xc040
+#define I2C_DATA                                            0xc004
+#define I2C_CONTROL                                         0xc008
+#define I2C_STATUS_BAUDE_RATE                               0xc00C
+#define I2C_SOFT_RESET                                      0xc01c
+
+/****************************************/
+/* MPSC Registers                       */
+/****************************************/
+
+/* MPSC0  */
+
+#define MPSC0_MAIN_CONFIGURATION_LOW                        0x8000
+#define MPSC0_MAIN_CONFIGURATION_HIGH                       0x8004
+#define MPSC0_PROTOCOL_CONFIGURATION                        0x8008
+#define CHANNEL0_REGISTER1                                  0x800c
+#define CHANNEL0_REGISTER2                                  0x8010
+#define CHANNEL0_REGISTER3                                  0x8014
+#define CHANNEL0_REGISTER4                                  0x8018
+#define CHANNEL0_REGISTER5                                  0x801c
+#define CHANNEL0_REGISTER6                                  0x8020
+#define CHANNEL0_REGISTER7                                  0x8024
+#define CHANNEL0_REGISTER8                                  0x8028
+#define CHANNEL0_REGISTER9                                  0x802c
+#define CHANNEL0_REGISTER10                                 0x8030
+#define CHANNEL0_REGISTER11                                 0x8034
+
+/* MPSC1  */
+
+#define MPSC1_MAIN_CONFIGURATION_LOW                        0x8840
+#define MPSC1_MAIN_CONFIGURATION_HIGH                       0x8844
+#define MPSC1_PROTOCOL_CONFIGURATION                        0x8848
+#define CHANNEL1_REGISTER1                                  0x884c
+#define CHANNEL1_REGISTER2                                  0x8850
+#define CHANNEL1_REGISTER3                                  0x8854
+#define CHANNEL1_REGISTER4                                  0x8858
+#define CHANNEL1_REGISTER5                                  0x885c
+#define CHANNEL1_REGISTER6                                  0x8860
+#define CHANNEL1_REGISTER7                                  0x8864
+#define CHANNEL1_REGISTER8                                  0x8868
+#define CHANNEL1_REGISTER9                                  0x886c
+#define CHANNEL1_REGISTER10                                 0x8870
+#define CHANNEL1_REGISTER11                                 0x8874
+
+/* MPSC2  */
+
+#define MPSC2_MAIN_CONFIGURATION_LOW                        0x9040
+#define MPSC2_MAIN_CONFIGURATION_HIGH                       0x9044
+#define MPSC2_PROTOCOL_CONFIGURATION                        0x9048
+#define CHANNEL2_REGISTER1                                  0x904c
+#define CHANNEL2_REGISTER2                                  0x9050
+#define CHANNEL2_REGISTER3                                  0x9054
+#define CHANNEL2_REGISTER4                                  0x9058
+#define CHANNEL2_REGISTER5                                  0x905c
+#define CHANNEL2_REGISTER6                                  0x9060
+#define CHANNEL2_REGISTER7                                  0x9064
+#define CHANNEL2_REGISTER8                                  0x9068
+#define CHANNEL2_REGISTER9                                  0x906c
+#define CHANNEL2_REGISTER10                                 0x9070
+#define CHANNEL2_REGISTER11                                 0x9074
+
+/* MPSCs Interupts  */
+
+#define MPSC0_CAUSE                                         0xb824
+#define MPSC0_MASK                                          0xb8a4
+#define MPSC1_CAUSE                                         0xb828
+#define MPSC1_MASK                                          0xb8a8
+#define MPSC2_CAUSE                                         0xb82c
+#define MPSC2_MASK                                          0xb8ac
+
+#endif /* __INCgt64260rh */
diff --git a/include/galileo/memory.h b/include/galileo/memory.h
new file mode 100755
index 0000000..0c46c24
--- /dev/null
+++ b/include/galileo/memory.h
@@ -0,0 +1,85 @@
+/* Memory.h - Memory mappings and remapping functions declarations */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCmemoryh
+#define __INCmemoryh
+
+/* includes */
+
+#include "core.h"
+
+/* defines */
+
+#define DONT_MODIFY     0xffffffff
+#define PARITY_SUPPORT  0x40000000
+
+#define _8BIT           0x00000000
+#define _16BIT          0x00100000
+#define _32BIT          0x00200000
+#define _64BIT          0x00300000
+
+/* typedefs */
+
+ typedef struct deviceParam
+{                               /* boundary values  */
+    unsigned int    turnOff;    /* 0x0 - 0xf        */
+    unsigned int    acc2First;  /* 0x0 - 0x1f       */
+    unsigned int    acc2Next;   /* 0x0 - 0x1f       */
+    unsigned int    ale2Wr;     /* 0x0 - 0xf        */
+    unsigned int    wrLow;      /* 0x0 - 0xf        */
+    unsigned int    wrHigh;     /* 0x0 - 0xf        */
+    unsigned int    deviceWidth;    /* in Bytes  */
+} DEVICE_PARAM;
+
+typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
+typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
+
+typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2,       \
+				   MEM_REGION3,MEM_REGION4,MEM_REGION5,       \
+				   MEM_REGION6,MEM_REGION7}                   \
+				   MEMORY_PROTECT_REGION;
+typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN}           \
+			    MEMORY_ACCESS;
+typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN}              \
+			   MEMORY_ACCESS_WRITE;
+typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN}       \
+				  MEMORY_CACHE_PROTECT;
+typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB}        \
+			       MEMORY_SNOOP_TYPE;
+typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1,         \
+				 MEM_SNOOP_REGION2,MEM_SNOOP_REGION3}         \
+				 MEMORY_SNOOP_REGION;
+
+/* functions */
+unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
+unsigned int memoryGetDeviceBaseAddress(DEVICE device);
+unsigned int memoryGetBankSize(MEMORY_BANK bank);
+unsigned int memoryGetDeviceSize(DEVICE device);
+unsigned int memoryGetDeviceWidth(DEVICE device);
+
+/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
+bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
+bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
+
+/* Change the Internal Register Base Address to a new given Address. */
+bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
+/* returns internal Register Space Base Address. */
+unsigned int memoryGetInternalRegistersSpace(void);
+/* Configurate the protection feature to a given space. */
+bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
+			    MEMORY_ACCESS memoryAccess,
+			    MEMORY_ACCESS_WRITE memoryWrite,
+			    MEMORY_CACHE_PROTECT cacheProtection,
+			    unsigned int baseAddress,
+			    unsigned int regionLength);
+/* Configurate the snoop feature to a given space. */
+bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
+			      MEMORY_SNOOP_TYPE snoopType,
+			      unsigned int baseAddress,
+			      unsigned int regionLength);
+
+bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
+bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
+bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
+#endif  /* __INCmemoryh */
diff --git a/include/galileo/pci.h b/include/galileo/pci.h
new file mode 100755
index 0000000..6ed8b95
--- /dev/null
+++ b/include/galileo/pci.h
@@ -0,0 +1,113 @@
+/* PCI.h - PCI functions header file */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCpcih
+#define __INCpcih
+
+/* includes */
+
+#include "core.h"
+#include "memory.h"
+
+/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
+#define PCI_MAX_DEVICES 22
+
+
+/* Macros */
+#define     SELF                    32
+
+/* Defines for the access regions. */
+#define     PREFETCH_ENABLE                 BIT12
+#define     PREFETCH_DISABLE                NO_BIT
+#define     DELAYED_READ_ENABLE             BIT13
+/* #define     CACHING_ENABLE                  BIT14 */
+/* aggressive prefetch: PCI slave prefetch two burst in advance*/
+#define     AGGRESSIVE_PREFETCH              BIT16
+/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
+#define     READ_LINE_AGGRESSIVE_PREFETCH   BIT17
+/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
+#define     READ_MULTI_AGGRESSIVE_PREFETCH  BIT18
+#define     MAX_BURST_4                     NO_BIT
+#define     MAX_BURST_8                     BIT20  /* Bits[21:20] = 01 */
+#define     MAX_BURST_16                    BIT21  /* Bits[21:20] = 10 */
+#define     PCI_BYTE_SWAP                   NO_BIT /* Bits[25:24] = 00 */
+#define     PCI_NO_SWAP                     BIT24  /* Bits[25:24] = 01 */
+#define     PCI_BYTE_AND_WORD_SWAP          BIT25  /* Bits[25:24] = 10 */
+#define     PCI_WORD_SWAP                  (BIT24 | BIT25) /* Bits[25:24] = 11 */
+#define     PCI_ACCESS_PROTECT              BIT28
+#define     PCI_WRITE_PROTECT               BIT29
+
+/* typedefs */
+
+typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
+				REGION6,REGION7} PCI_ACCESS_REGIONS;
+
+typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
+typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
+
+typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
+			    PCI_SNOOP_TYPE;
+typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
+			      PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
+			      PCI_SNOOP_REGION;
+
+typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
+typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
+			 PCI_REGION2,PCI_REGION3,
+			 PCI_IO}
+			 PCI_REGION;
+
+/* read/write configuration registers on local PCI bus. */
+void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
+		       unsigned int pciDevNum, unsigned int data);
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum);
+
+/* read/write configuration registers on another PCI bus. */
+void pciOverBridgeWriteConfigReg(PCI_HOST host,
+				 unsigned int regOffset,
+				 unsigned int pciDevNum,
+				 unsigned int busNum,unsigned int data);
+unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
+					unsigned int regOffset,
+					unsigned int pciDevNum,
+					unsigned int busNum);
+
+/*      Master`s memory space   */
+bool pciMapSpace(PCI_HOST host, PCI_REGION region,
+		unsigned int remapBase,
+		unsigned int deviceBase,
+		unsigned int deviceLength);
+unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
+unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
+
+/*      Slave`s memory space   */
+void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
+		      unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
+
+/* PCI region options */
+
+bool  pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
+	unsigned int features, unsigned int baseAddress,
+	unsigned int regionLength);
+
+void  pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
+
+/* PCI arbiter */
+
+bool pciArbiterEnable(PCI_HOST host);
+bool pciArbiterDisable(PCI_HOST host);
+bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5);
+bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength);
+
+#endif /* __INCpcih */
diff --git a/include/hush.h b/include/hush.h
new file mode 100755
index 0000000..20e48db
--- /dev/null
+++ b/include/hush.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _HUSH_H_
+#define _HUSH_H_
+
+#define FLAG_EXIT_FROM_LOOP 1
+#define FLAG_PARSE_SEMICOLON (1 << 1)	  /* symbol ';' is special for parser */
+#define FLAG_REPARSING       (1 << 2)	  /* >=2nd pass */
+
+extern int u_boot_hush_start(void);
+extern int parse_string_outer(char *, int);
+extern int parse_file_outer(void);
+
+#endif
diff --git a/include/i2c.h b/include/i2c.h
new file mode 100755
index 0000000..2ac30bb
--- /dev/null
+++ b/include/i2c.h
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2001
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * The original I2C interface was
+ *   (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
+ *   AIRVENT SAM s.p.a - RIMINI(ITALY)
+ * but has been changed substantially.
+ */
+
+#ifndef _I2C_H_
+#define _I2C_H_
+
+/*
+ * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
+ *
+ * The implementation MUST NOT use static or global variables if the
+ * I2C routines are used to read SDRAM configuration information
+ * because this is done before the memories are initialized. Limited
+ * use of stack-based variables are OK (the initial stack size is
+ * limited).
+ *
+ * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
+ */
+
+/*
+ * Configuration items.
+ */
+#define I2C_RXTX_LEN	128	/* maximum tx/rx buffer length */
+
+/*
+ * Initialization, must be called once on start up, may be called
+ * repeatedly to change the speed and slave addresses.
+ */
+void i2c_init(int speed, int slaveaddr);
+void i2c1_init(int speed, int slaveaddr);
+void i2c2_init(int speed, int slaveaddr);
+void i2c3_init(int speed, int slaveaddr);
+#ifdef CFG_I2C_INIT_BOARD
+void i2c_init_board(void);
+#endif
+
+/*
+ * Probe the given I2C chip address.  Returns 0 if a chip responded,
+ * not 0 on failure.
+ */
+int i2c_probe(uchar chip);
+
+/*
+ * Read/Write interface:
+ *   chip:    I2C chip address, range 0..127
+ *   addr:    Memory (register) address within the chip
+ *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
+ *              memories, 0 for register type devices with only one
+ *              register)
+ *   buffer:  Where to read/write the data
+ *   len:     How many bytes to read/write
+ *
+ *   Returns: 0 on success, not 0 on failure
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
+
+/*
+ * Utility routines to read/write registers.
+ */
+uchar i2c_reg_read (uchar chip, uchar reg);
+void  i2c_reg_write(uchar chip, uchar reg, uchar val);
+
+#endif	/* _I2C_H_ */
diff --git a/include/i8042.h b/include/i8042.h
new file mode 100755
index 0000000..f77239f
--- /dev/null
+++ b/include/i8042.h
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* i8042.h - Intel 8042 keyboard driver header */
+
+#ifndef _I8042_H_
+#define _I8042_H_
+
+#ifdef __I386__
+#include <common.h>
+#include <asm/io.h>
+#define in8(p) inb(p)
+#define out8(p,v) outb(v,p)
+#endif
+
+/* defines */
+
+#define I8042_DATA_REG      (CFG_ISA_IO + 0x0060)    /* keyboard i/o buffer */
+#define I8042_STATUS_REG    (CFG_ISA_IO + 0x0064)    /* keyboard status read */
+#define I8042_COMMAND_REG   (CFG_ISA_IO + 0x0064)    /* keyboard ctrl write */
+
+#define KBD_US              0        /* default US layout */
+#define KBD_GER             1        /* german layout */
+
+#define KBD_TIMEOUT         1000     /* 1 sec */
+#define KBD_RESET_TRIES     3
+
+#define AS                  0        /* normal character index */
+#define SH                  1        /* shift index */
+#define CN                  2        /* control index */
+#define NM                  3        /* numeric lock index */
+#define AK                  4        /* right alt key */
+#define CP                  5        /* capslock index */
+#define ST                  6        /* stop output index */
+#define EX                  7        /* extended code index */
+#define ES                  8        /* escape and extended code index */
+
+#define NORMAL              0x0000    /* normal key */
+#define STP                 0x0001    /* scroll lock stop output*/
+#define NUM                 0x0002    /* numeric lock */
+#define CAPS                0x0004    /* capslock */
+#define SHIFT               0x0008    /* shift */
+#define CTRL                0x0010    /* control*/
+#define EXT                 0x0020    /* extended scan code 0xe0 */
+#define ESC                 0x0040    /* escape key press */
+#define E1                  0x0080    /* extended scan code 0xe1 */
+#define BRK                 0x0100    /* make break flag for keyboard */
+#define ALT                 0x0200    /* right alt */
+
+/* exports */
+
+int i8042_kbd_init(void);
+int i8042_tstc(void);
+int i8042_getc(void);
+
+#endif /* _I8042_H_ */
diff --git a/include/ide.h b/include/ide.h
new file mode 100755
index 0000000..dfef32f
--- /dev/null
+++ b/include/ide.h
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	_IDE_H
+#define _IDE_H
+
+#define	IDE_BUS(dev)	(dev >> 1)
+
+#ifdef CONFIG_IDE_LED
+
+/*
+ * LED Port
+ */
+#define	LED_PORT	((uchar *)(PER8_BASE + 0x3000))
+#define LED_IDE1	0x01
+#define LED_IDE2	0x02
+#define	DEVICE_LED(d)	((d & 2) | ((d & 2) == 0)) /* depends on bit positions! */
+
+#endif /* CONFIG_IDE_LED */
+
+#ifdef CFG_64BIT_LBA
+typedef uint64_t lbaint_t;
+#else
+typedef ulong lbaint_t;
+#endif
+
+/*
+ * Function Prototypes
+ */
+
+void  ide_init  (void);
+ulong ide_read	(int device, lbaint_t blknr, ulong blkcnt, ulong *buffer);
+ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer);
+
+#endif /* _IDE_H */
diff --git a/include/image.h b/include/image.h
new file mode 100755
index 0000000..af37bca
--- /dev/null
+++ b/include/image.h
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __IMAGE_H__
+#define __IMAGE_H__
+
+/*
+ * Operating System Codes
+ */
+#define IH_OS_INVALID		0	/* Invalid OS	*/
+#define IH_OS_OPENBSD		1	/* OpenBSD	*/
+#define IH_OS_NETBSD		2	/* NetBSD	*/
+#define IH_OS_FREEBSD		3	/* FreeBSD	*/
+#define IH_OS_4_4BSD		4	/* 4.4BSD	*/
+#define IH_OS_LINUX		5	/* Linux	*/
+#define IH_OS_SVR4		6	/* SVR4		*/
+#define IH_OS_ESIX		7	/* Esix		*/
+#define IH_OS_SOLARIS		8	/* Solaris	*/
+#define IH_OS_IRIX		9	/* Irix		*/
+#define IH_OS_SCO		10	/* SCO		*/
+#define IH_OS_DELL		11	/* Dell		*/
+#define IH_OS_NCR		12	/* NCR		*/
+#define IH_OS_LYNXOS		13	/* LynxOS	*/
+#define IH_OS_VXWORKS		14	/* VxWorks	*/
+#define IH_OS_PSOS		15	/* pSOS		*/
+#define IH_OS_QNX		16	/* QNX		*/
+#define IH_OS_U_BOOT		17	/* Firmware	*/
+#define IH_OS_RTEMS		18	/* RTEMS	*/
+#define IH_OS_ARTOS		19	/* ARTOS	*/
+#define IH_OS_UNITY		20	/* Unity OS	*/
+
+/*
+ * CPU Architecture Codes (supported by Linux)
+ */
+#define IH_CPU_INVALID		0	/* Invalid CPU	*/
+#define IH_CPU_ALPHA		1	/* Alpha	*/
+#define IH_CPU_ARM		2	/* ARM		*/
+#define IH_CPU_I386		3	/* Intel x86	*/
+#define IH_CPU_IA64		4	/* IA64		*/
+#define IH_CPU_MIPS		5	/* MIPS		*/
+#define IH_CPU_MIPS64		6	/* MIPS	 64 Bit */
+#define IH_CPU_PPC		7	/* PowerPC	*/
+#define IH_CPU_S390		8	/* IBM S390	*/
+#define IH_CPU_SH		9	/* SuperH	*/
+#define IH_CPU_SPARC		10	/* Sparc	*/
+#define IH_CPU_SPARC64		11	/* Sparc 64 Bit */
+#define IH_CPU_M68K		12	/* M68K		*/
+#define IH_CPU_NIOS		13	/* Nios-32	*/
+#define IH_CPU_MICROBLAZE	14	/* MicroBlaze   */
+#define IH_CPU_NIOS2		15	/* Nios-II	*/
+
+/*
+ * Image Types
+ *
+ * "Standalone Programs" are directly runnable in the environment
+ *	provided by U-Boot; it is expected that (if they behave
+ *	well) you can continue to work in U-Boot after return from
+ *	the Standalone Program.
+ * "OS Kernel Images" are usually images of some Embedded OS which
+ *	will take over control completely. Usually these programs
+ *	will install their own set of exception handlers, device
+ *	drivers, set up the MMU, etc. - this means, that you cannot
+ *	expect to re-enter U-Boot except by resetting the CPU.
+ * "RAMDisk Images" are more or less just data blocks, and their
+ *	parameters (address, size) are passed to an OS kernel that is
+ *	being started.
+ * "Multi-File Images" contain several images, typically an OS
+ *	(Linux) kernel image and one or more data images like
+ *	RAMDisks. This construct is useful for instance when you want
+ *	to boot over the network using BOOTP etc., where the boot
+ *	server provides just a single image file, but you want to get
+ *	for instance an OS kernel and a RAMDisk image.
+ *
+ *	"Multi-File Images" start with a list of image sizes, each
+ *	image size (in bytes) specified by an "uint32_t" in network
+ *	byte order. This list is terminated by an "(uint32_t)0".
+ *	Immediately after the terminating 0 follow the images, one by
+ *	one, all aligned on "uint32_t" boundaries (size rounded up to
+ *	a multiple of 4 bytes - except for the last file).
+ *
+ * "Firmware Images" are binary images containing firmware (like
+ *	U-Boot or FPGA images) which usually will be programmed to
+ *	flash memory.
+ *
+ * "Script files" are command sequences that will be executed by
+ *	U-Boot's command interpreter; this feature is especially
+ *	useful when you configure U-Boot to use a real shell (hush)
+ *	as command interpreter (=> Shell Scripts).
+ */
+
+#define IH_TYPE_INVALID		0	/* Invalid Image		*/
+#define IH_TYPE_STANDALONE	1	/* Standalone Program		*/
+#define IH_TYPE_KERNEL		2	/* OS Kernel Image		*/
+#define IH_TYPE_RAMDISK		3	/* RAMDisk Image		*/
+#define IH_TYPE_MULTI		4	/* Multi-File Image		*/
+#define IH_TYPE_FIRMWARE	5	/* Firmware Image		*/
+#define IH_TYPE_SCRIPT		6	/* Script file			*/
+#define IH_TYPE_FILESYSTEM	7	/* Filesystem Image (any type)	*/
+
+/*
+ * Compression Types
+ */
+#define IH_COMP_NONE		0	/*  No	 Compression Used	*/
+#define IH_COMP_GZIP		1	/* gzip	 Compression Used	*/
+#define IH_COMP_BZIP2		2	/* bzip2 Compression Used	*/
+
+#define IH_MAGIC	0x27051956	/* Image Magic Number		*/
+#define IH_NMLEN		32	/* Image Name Length		*/
+
+/*
+ * all data in network byte order (aka natural aka bigendian)
+ */
+
+typedef struct image_header {
+	uint32_t	ih_magic;	/* Image Header Magic Number	*/
+	uint32_t	ih_hcrc;	/* Image Header CRC Checksum	*/
+	uint32_t	ih_time;	/* Image Creation Timestamp	*/
+	uint32_t	ih_size;	/* Image Data Size		*/
+	uint32_t	ih_load;	/* Data	 Load  Address		*/
+	uint32_t	ih_ep;		/* Entry Point Address		*/
+	uint32_t	ih_dcrc;	/* Image Data CRC Checksum	*/
+	uint8_t		ih_os;		/* Operating System		*/
+	uint8_t		ih_arch;	/* CPU architecture		*/
+	uint8_t		ih_type;	/* Image Type			*/
+	uint8_t		ih_comp;	/* Compression Type		*/
+	uint8_t		ih_name[IH_NMLEN];	/* Image Name		*/
+} image_header_t;
+
+
+#endif	/* __IMAGE_H__ */
diff --git a/include/ioports.h b/include/ioports.h
new file mode 100755
index 0000000..d7e19e1
--- /dev/null
+++ b/include/ioports.h
@@ -0,0 +1,55 @@
+/*
+ * definitions for MPC8260 I/O Ports
+ *
+ * (in addition to those provided in <asm/immap_8260.h>)
+ *
+ * Murray.Jensen@cmst.csiro.au, 20-Oct-00
+ */
+
+/*
+ * this structure mirrors the layout of the five port registers in
+ * the internal memory map - see iop8260_t in <asm/immap_8260.h>
+ */
+typedef struct {
+    unsigned int pdir;		/* Port Data Direction Register (35-3) */
+    unsigned int ppar;		/* Port Pin Assignment Register (35-4) */
+    unsigned int psor;		/* Port Special Options Register (35-5) */
+    unsigned int podr;		/* Port Open Drain Register (35-2) */
+    unsigned int pdat;		/* Port Data Register (35-3) */
+} ioport_t;
+
+/*
+ * this macro calculates the address within the internal
+ * memory map (im) of the set of registers for a port (idx)
+ *
+ * the internal memory map aligns the above structure on
+ * a 0x20 byte boundary
+ */
+#ifdef CONFIG_MPC85xx
+#define ioport_addr(im, idx) (ioport_t *)((uint)&((im)->im_cpm.im_cpm_iop) + ((idx)*0x20))
+#else
+#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
+#endif
+
+/*
+ * this structure provides configuration
+ * information for one port pin
+ */
+typedef struct {
+    unsigned char conf:1;	/* if 1, configure this port */
+    unsigned char ppar:1;	/* Port Pin Assignment Register (35-4) */
+    unsigned char psor:1;	/* Port Special Options Register (35-2) */
+    unsigned char pdir:1;	/* Port Data Direction Register (35-3) */
+    unsigned char podr:1;	/* Port Open Drain Register (35-2) */
+    unsigned char pdat:1;	/* Port Data Register (35-2) */
+} iop_conf_t;
+
+/*
+ * a table that contains configuration information for all 32 pins
+ * of all four MPC8260 I/O ports.
+ *
+ * NOTE: in the second dimension of this table, index 0 refers to pin 31
+ * and index 31 refers to pin 0. this made the code in the table look more
+ * like the table in the 8260UM (and in the hymod manuals).
+ */
+extern const iop_conf_t iop_conf_tab[4][32];
diff --git a/include/jffs2/compr_rubin.h b/include/jffs2/compr_rubin.h
new file mode 100755
index 0000000..f26f476
--- /dev/null
+++ b/include/jffs2/compr_rubin.h
@@ -0,0 +1,11 @@
+/* Rubin encoder/decoder header       */
+/* work started at   : aug   3, 1994  */
+/* last modification : aug  15, 1994  */
+/* $Id: compr_rubin.h,v 1.1 2002/01/16 23:34:32 nyet Exp $ */
+
+#define RUBIN_REG_SIZE   16
+#define UPPER_BIT_RUBIN    (((long) 1)<<(RUBIN_REG_SIZE-1))
+#define LOWER_BITS_RUBIN   ((((long) 1)<<(RUBIN_REG_SIZE-1))-1)
+
+void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out,
+		   unsigned long sourcelen, unsigned long dstlen);
diff --git a/include/jffs2/jffs2.h b/include/jffs2/jffs2.h
new file mode 100755
index 0000000..d142cd1
--- /dev/null
+++ b/include/jffs2/jffs2.h
@@ -0,0 +1,218 @@
+/*
+ * JFFS2 -- Journalling Flash File System, Version 2.
+ *
+ * Copyright (C) 2001 Red Hat, Inc.
+ *
+ * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
+ *
+ * The original JFFS, from which the design for JFFS2 was derived,
+ * was designed and implemented by Axis Communications AB.
+ *
+ * The contents of this file are subject to the Red Hat eCos Public
+ * License Version 1.1 (the "Licence"); you may not use this file
+ * except in compliance with the Licence.  You may obtain a copy of
+ * the Licence at http://www.redhat.com/
+ *
+ * Software distributed under the Licence is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
+ * See the Licence for the specific language governing rights and
+ * limitations under the Licence.
+ *
+ * The Original Code is JFFS2 - Journalling Flash File System, version 2
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use your
+ * version of this file under the RHEPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the RHEPL or the GPL.
+ *
+ * $Id: jffs2.h,v 1.2 2002/01/17 00:53:20 nyet Exp $
+ *
+ */
+
+#ifndef __LINUX_JFFS2_H__
+#define __LINUX_JFFS2_H__
+
+#include <asm/types.h>
+#include <jffs2/load_kernel.h>
+
+#define JFFS2_SUPER_MAGIC 0x72b6
+
+/* Values we may expect to find in the 'magic' field */
+#define JFFS2_OLD_MAGIC_BITMASK 0x1984
+#define JFFS2_MAGIC_BITMASK 0x1985
+#define KSAMTIB_CIGAM_2SFFJ 0x5981 /* For detecting wrong-endian fs */
+#define JFFS2_EMPTY_BITMASK 0xffff
+#define JFFS2_DIRTY_BITMASK 0x0000
+
+/* We only allow a single char for length, and 0xFF is empty flash so
+   we don't want it confused with a real length. Hence max 254.
+*/
+#define JFFS2_MAX_NAME_LEN 254
+
+/* How small can we sensibly write nodes? */
+#define JFFS2_MIN_DATA_LEN 128
+
+#define JFFS2_COMPR_NONE	0x00
+#define JFFS2_COMPR_ZERO	0x01
+#define JFFS2_COMPR_RTIME	0x02
+#define JFFS2_COMPR_RUBINMIPS	0x03
+#define JFFS2_COMPR_COPY	0x04
+#define JFFS2_COMPR_DYNRUBIN	0x05
+#define JFFS2_COMPR_ZLIB	0x06
+#if defined(CONFIG_JFFS2_LZO_LZARI)
+#define JFFS2_COMPR_LZO		0x07
+#define JFFS2_COMPR_LZARI	0x08
+#define JFFS2_NUM_COMPR		9
+#else
+#define JFFS2_NUM_COMPR		7
+#endif
+
+/* Compatibility flags. */
+#define JFFS2_COMPAT_MASK 0xc000      /* What do to if an unknown nodetype is found */
+#define JFFS2_NODE_ACCURATE 0x2000
+/* INCOMPAT: Fail to mount the filesystem */
+#define JFFS2_FEATURE_INCOMPAT 0xc000
+/* ROCOMPAT: Mount read-only */
+#define JFFS2_FEATURE_ROCOMPAT 0x8000
+/* RWCOMPAT_COPY: Mount read/write, and copy the node when it's GC'd */
+#define JFFS2_FEATURE_RWCOMPAT_COPY 0x4000
+/* RWCOMPAT_DELETE: Mount read/write, and delete the node when it's GC'd */
+#define JFFS2_FEATURE_RWCOMPAT_DELETE 0x0000
+
+#define JFFS2_NODETYPE_DIRENT (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 1)
+#define JFFS2_NODETYPE_INODE (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 2)
+#define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3)
+#define JFFS2_NODETYPE_PADDING (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 4)
+
+/* Maybe later... */
+/*#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) */
+/*#define JFFS2_NODETYPE_OPTIONS (JFFS2_FEATURE_RWCOMPAT_COPY | JFFS2_NODE_ACCURATE | 4) */
+
+/* Same as the non_ECC versions, but with extra space for real
+ * ECC instead of just the checksum. For use on NAND flash
+ */
+/*#define JFFS2_NODETYPE_DIRENT_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 5) */
+/*#define JFFS2_NODETYPE_INODE_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 6) */
+
+#define JFFS2_INO_FLAG_PREREAD	  1	/* Do read_inode() for this one at
+					   mount time, don't wait for it to
+					   happen later */
+#define JFFS2_INO_FLAG_USERCOMPR  2	/* User has requested a specific
+					   compression type */
+
+
+struct jffs2_unknown_node
+{
+	/* All start like this */
+	__u16 magic;
+	__u16 nodetype;
+	__u32 totlen; /* So we can skip over nodes we don't grok */
+	__u32 hdr_crc;
+} __attribute__((packed));
+
+struct jffs2_raw_dirent
+{
+	__u16 magic;
+	__u16 nodetype;	/* == JFFS_NODETYPE_DIRENT */
+	__u32 totlen;
+	__u32 hdr_crc;
+	__u32 pino;
+	__u32 version;
+	__u32 ino; /* == zero for unlink */
+	__u32 mctime;
+	__u8 nsize;
+	__u8 type;
+	__u8 unused[2];
+	__u32 node_crc;
+	__u32 name_crc;
+	__u8 name[0];
+} __attribute__((packed));
+
+/* The JFFS2 raw inode structure: Used for storage on physical media.  */
+/* The uid, gid, atime, mtime and ctime members could be longer, but
+   are left like this for space efficiency. If and when people decide
+   they really need them extended, it's simple enough to add support for
+   a new type of raw node.
+*/
+struct jffs2_raw_inode
+{
+	__u16 magic;      /* A constant magic number.  */
+	__u16 nodetype;   /* == JFFS_NODETYPE_INODE */
+	__u32 totlen;     /* Total length of this node (inc data, etc.) */
+	__u32 hdr_crc;
+	__u32 ino;        /* Inode number.  */
+	__u32 version;    /* Version number.  */
+	__u32 mode;       /* The file's type or mode.  */
+	__u16 uid;        /* The file's owner.  */
+	__u16 gid;        /* The file's group.  */
+	__u32 isize;      /* Total resultant size of this inode (used for truncations)  */
+	__u32 atime;      /* Last access time.  */
+	__u32 mtime;      /* Last modification time.  */
+	__u32 ctime;      /* Change time.  */
+	__u32 offset;     /* Where to begin to write.  */
+	__u32 csize;      /* (Compressed) data size */
+	__u32 dsize;	  /* Size of the node's data. (after decompression) */
+	__u8 compr;       /* Compression algorithm used */
+	__u8 usercompr;	  /* Compression algorithm requested by the user */
+	__u16 flags;	  /* See JFFS2_INO_FLAG_* */
+	__u32 data_crc;   /* CRC for the (compressed) data.  */
+	__u32 node_crc;   /* CRC for the raw inode (excluding data)  */
+/*	__u8 data[dsize]; */
+} __attribute__((packed));
+
+union jffs2_node_union {
+	struct jffs2_raw_inode i;
+	struct jffs2_raw_dirent d;
+	struct jffs2_unknown_node u;
+} __attribute__((packed));
+
+enum
+  {
+    DT_UNKNOWN = 0,
+# define DT_UNKNOWN     DT_UNKNOWN
+    DT_FIFO = 1,
+# define DT_FIFO        DT_FIFO
+    DT_CHR = 2,
+# define DT_CHR         DT_CHR
+    DT_DIR = 4,
+# define DT_DIR         DT_DIR
+    DT_BLK = 6,
+# define DT_BLK         DT_BLK
+    DT_REG = 8,
+# define DT_REG         DT_REG
+    DT_LNK = 10,
+# define DT_LNK         DT_LNK
+    DT_SOCK = 12,
+# define DT_SOCK        DT_SOCK
+    DT_WHT = 14
+# define DT_WHT         DT_WHT
+  };
+
+
+u32 jffs2_1pass_ls(struct part_info *part,const char *fname);
+u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname);
+u32 jffs2_1pass_info(struct part_info *part);
+
+void rtime_decompress(unsigned char *data_in, unsigned char *cpage_out,
+		u32 srclen, u32 destlen);
+void rubin_do_decompress(unsigned char *bits, unsigned char *in,
+		unsigned char *page_out, __u32 destlen);
+void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out,
+		unsigned long sourcelen, unsigned long dstlen);
+long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out,
+		__u32 srclen, __u32 destlen);
+#if defined(CONFIG_JFFS2_LZO_LZARI)
+int lzo_decompress(unsigned char *data_in, unsigned char *cpage_out,
+		u32 srclen, u32 destlen);
+int lzari_decompress(unsigned char *data_in, unsigned char *cpage_out,
+		u32 srclen, u32 destlen);
+#endif
+
+char *mkmodestr(unsigned long mode, char *str);
+#endif /* __LINUX_JFFS2_H__ */
diff --git a/include/jffs2/jffs2_1pass.h b/include/jffs2/jffs2_1pass.h
new file mode 100755
index 0000000..5bc3e66
--- /dev/null
+++ b/include/jffs2/jffs2_1pass.h
@@ -0,0 +1,3 @@
+u32 jffs2_1pass_ls(struct part_info *part,const char *fname);
+u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname);
+u32 jffs2_1pass_info(struct part_info *part);
diff --git a/include/jffs2/load_kernel.h b/include/jffs2/load_kernel.h
new file mode 100755
index 0000000..882a80e
--- /dev/null
+++ b/include/jffs2/load_kernel.h
@@ -0,0 +1,73 @@
+#ifndef load_kernel_h
+#define load_kernel_h
+/*-------------------------------------------------------------------------
+ * Filename:      load_kernel.h
+ * Version:       $Id: load_kernel.h,v 1.3 2002/01/25 01:34:11 nyet Exp $
+ * Copyright:     Copyright (C) 2001, Russ Dill
+ * Author:        Russ Dill <Russ.Dill@asu.edu>
+ * Description:   header for load kernel modules
+ *-----------------------------------------------------------------------*/
+/*
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/list.h>
+
+/* mtd device types */
+#define MTD_DEV_TYPE_NOR      0x0001
+#define MTD_DEV_TYPE_NAND     0x0002
+#define MTD_DEV_TYPE(type) ((type == MTD_DEV_TYPE_NAND) ? "nand" : "nor")
+
+struct mtd_device {
+	struct list_head link;
+	struct mtdids *id;		/* parent mtd id entry */
+	u16 num_parts;			/* number of partitions on this device */
+	struct list_head parts;		/* partitions */
+};
+
+struct part_info {
+	struct list_head link;
+	char *name;			/* partition name */
+	u8 auto_name;			/* set to 1 for generated name */
+	u32 size;			/* total size of the partition */
+	u32 offset;			/* offset within device */
+	void *jffs2_priv;		/* used internaly by jffs2 */
+	u32 mask_flags;			/* kernel MTD mask flags */
+	struct mtd_device *dev;		/* parent device */
+};
+
+struct mtdids {
+	struct list_head link;
+	u8 type;			/* device type */
+	u8 num;				/* device number */
+	u32 size;			/* device size */
+	char *mtd_id;			/* linux kernel device id */
+};
+
+#define ldr_strlen	strlen
+#define ldr_strncmp	strncmp
+#define ldr_memcpy	memcpy
+#define putstr(x)	printf("%s", x)
+#define mmalloc		malloc
+#define UDEBUG		printf
+
+#define putnstr(str, size)	printf("%*.*s", size, size, str)
+#define ldr_output_string(x)	puts(x)
+#define putLabeledWord(x, y)	printf("%s %08x\n", x, (unsigned int)y)
+#define led_blink(x, y, z, a)
+
+#endif /* load_kernel_h */
diff --git a/include/jffs2/mini_inflate.h b/include/jffs2/mini_inflate.h
new file mode 100755
index 0000000..f79aac7
--- /dev/null
+++ b/include/jffs2/mini_inflate.h
@@ -0,0 +1,82 @@
+/*-------------------------------------------------------------------------
+ * Filename:      mini_inflate.h
+ * Version:       $Id: mini_inflate.h,v 1.2 2002/01/17 00:53:20 nyet Exp $
+ * Copyright:     Copyright (C) 2001, Russ Dill
+ * Author:        Russ Dill <Russ.Dill@asu.edu>
+ * Description:   Mini deflate implementation
+ *-----------------------------------------------------------------------*/
+/*
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+typedef __SIZE_TYPE__ size;
+
+#define NO_ERROR 0
+#define COMP_UNKNOWN 1	 /* The specififed bytype is invalid */
+#define CODE_NOT_FOUND 2 /* a huffman code in the stream could not be decoded */
+#define TOO_MANY_BITS 3	 /* pull_bits was passed an argument that is too
+			  * large */
+
+/* This struct represents an entire huffman code set. It has various lookup
+ * tables to speed decoding */
+struct huffman_set {
+	int bits;	 /* maximum bit length */
+	int num_symbols; /* Number of symbols this code can represent */
+	int *lengths;	 /* The bit length of symbols */
+	int *symbols;	 /* All of the symbols, sorted by the huffman code */
+	int *count;	 /* the number of codes of this bit length */
+	int *first;	 /* the first code of this bit length */
+	int *pos;	 /* the symbol that first represents (in the symbols
+			  * array) */
+};
+
+struct bitstream {
+	unsigned char *data; /* increments as we move from byte to byte */
+	unsigned char bit;   /* 0 to 7 */
+	void *(*memcpy)(void *, const void *, size);
+	unsigned long decoded; /* The number of bytes decoded */
+	int error;
+
+	int  distance_count[16];
+	int  distance_first[16];
+	int  distance_pos[16];
+	int  distance_lengths[32];
+	int  distance_symbols[32];
+
+	int  code_count[8];
+	int  code_first[8];
+	int  code_pos[8];
+	int  code_lengths[19];
+	int  code_symbols[19];
+
+	int  length_count[16];
+	int  length_first[16];
+	int  length_pos[16];
+	int  length_lengths[288];
+	int  length_symbols[288];
+
+	struct huffman_set codes;
+	struct huffman_set lengths;
+	struct huffman_set distance;
+};
+
+#define NO_COMP 0
+#define FIXED_COMP 1
+#define DYNAMIC_COMP 2
+
+long decompress_block(unsigned char *dest, unsigned char *source,
+		      void *(*inflate_memcpy)(void *dest, const void *src, size n));
diff --git a/include/keyboard.h b/include/keyboard.h
new file mode 100755
index 0000000..88ae12b
--- /dev/null
+++ b/include/keyboard.h
@@ -0,0 +1,22 @@
+#ifndef __KEYBOARD_H
+#define __KEYBOARD_H
+
+#ifdef CONFIG_PS2MULT
+#include <ps2mult.h>
+#endif
+
+#if !defined(kbd_request_region) || \
+    !defined(kbd_request_irq) || \
+    !defined(kbd_read_input) || \
+    !defined(kbd_read_status) || \
+    !defined(kbd_write_output) || \
+    !defined(kbd_write_command)
+#error PS/2 low level routines not defined
+#endif
+
+extern int kbd_init (void);
+extern void handle_scancode(unsigned char scancode);
+extern int kbd_init_hw(void);
+extern void pckbd_leds(unsigned char leds);
+
+#endif /* __KEYBOARD_H */
diff --git a/include/kgdb.h b/include/kgdb.h
new file mode 100755
index 0000000..f543cd6
--- /dev/null
+++ b/include/kgdb.h
@@ -0,0 +1,70 @@
+#ifndef __KGDB_H__
+#define __KGDB_H__
+
+#include <asm/ptrace.h>
+
+#define KGDBERR_BADPARAMS	1
+#define KGDBERR_NOTHEXDIG	2
+#define KGDBERR_MEMFAULT	3
+#define KGDBERR_NOSPACE		4
+#define KGDBERR_ALIGNFAULT	5
+
+#define KGDBDATA_MAXREGS	8
+#define KGDBDATA_MAXPRIV	8
+
+#define KGDBEXIT_TYPEMASK	0xff
+
+#define KGDBEXIT_KILL		0
+#define KGDBEXIT_CONTINUE	1
+#define KGDBEXIT_SINGLE		2
+
+#define KGDBEXIT_WITHADDR	0x100
+
+typedef
+	struct {
+		int num;
+		unsigned long val;
+	}
+kgdb_reg;
+
+typedef
+	struct {
+		int sigval;
+		int extype;
+		unsigned long exaddr;
+		int nregs;
+		kgdb_reg regs[KGDBDATA_MAXREGS];
+		unsigned long private[KGDBDATA_MAXPRIV];
+	}
+kgdb_data;
+
+/* these functions are provided by the generic kgdb support */
+extern void kgdb_init(void);
+extern void kgdb_error(int);
+extern int kgdb_output_string(const char *, unsigned int);
+extern void breakpoint(void);
+
+/* these functions are provided by the platform specific kgdb support */
+extern void kgdb_flush_cache_range(void *, void *);
+extern void kgdb_flush_cache_all(void);
+extern int kgdb_setjmp(long *);
+extern void kgdb_longjmp(long *, int);
+extern void kgdb_enter(struct pt_regs *, kgdb_data *);
+extern void kgdb_exit(struct pt_regs *, kgdb_data *);
+extern int kgdb_getregs(struct pt_regs *, char *, int);
+extern void kgdb_putreg(struct pt_regs *, int, char *, int);
+extern void kgdb_putregs(struct pt_regs *, char *, int);
+extern int kgdb_trap(struct pt_regs *);
+extern void kgdb_breakpoint(int argc, char *argv[]);
+
+/* these functions are provided by the platform serial driver */
+extern void kgdb_serial_init(void);
+extern int getDebugChar(void);
+extern void putDebugChar(int);
+extern void putDebugStr(const char *);
+extern void kgdb_interruptible(int);
+
+/* this is referenced in the trap handler for the platform */
+extern int (*debugger_exception_handler)(struct pt_regs *);
+
+#endif /* __KGDB_H__ */
diff --git a/include/lcd.h b/include/lcd.h
new file mode 100755
index 0000000..7e23736
--- /dev/null
+++ b/include/lcd.h
@@ -0,0 +1,283 @@
+/*
+ * MPC823 and PXA LCD Controller
+ *
+ * Modeled after video interface by Paolo Scaffardi
+ *
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _LCD_H_
+#define _LCD_H_
+
+extern char lcd_is_enabled;
+
+extern int lcd_line_length;
+extern int lcd_color_fg;
+extern int lcd_color_bg;
+
+/*
+ * Frame buffer memory information
+ */
+extern void *lcd_base;		/* Start of framebuffer memory	*/
+extern void *lcd_console_address;	/* Start of console buffer	*/
+
+extern short console_col;
+extern short console_row;
+
+#if defined CONFIG_MPC823
+/*
+ * LCD controller stucture for MPC823 CPU
+ */
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 640) */
+	ushort	vl_row;		/* Number of rows (i.e. 480) */
+	ushort	vl_width;	/* Width of display area in millimeters */
+	ushort	vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u_char	vl_clkp;	/* Clock polarity */
+	u_char	vl_oep;		/* Output Enable polarity */
+	u_char	vl_hsp;		/* Horizontal Sync polarity */
+	u_char	vl_vsp;		/* Vertical Sync polarity */
+	u_char	vl_dp;		/* Data polarity */
+	u_char	vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
+	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
+	u_char	vl_splt;	/* Split display, 0 = single-scan, 1 = dual-scan */
+	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
+	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
+
+	/* Horizontal control register. Timing from data sheet */
+	ushort	vl_wbl;		/* Wait between lines */
+
+	/* Vertical control register */
+	u_char	vl_vpw;		/* Vertical sync pulse width */
+	u_char	vl_lcdac;	/* LCD AC timing */
+	u_char	vl_wbf;		/* Wait between frames */
+} vidinfo_t;
+
+extern vidinfo_t panel_info;
+
+#elif defined CONFIG_PXA250
+/*
+ * PXA LCD DMA descriptor
+ */
+struct pxafb_dma_descriptor {
+	u_long	fdadr;		/* Frame descriptor address register */
+	u_long	fsadr;		/* Frame source address register */
+	u_long	fidr;		/* Frame ID register */
+	u_long	ldcmd;		/* Command register */
+};
+
+/*
+ * PXA LCD info
+ */
+struct pxafb_info {
+
+	/* Misc registers */
+	u_long	reg_lccr3;
+	u_long	reg_lccr2;
+	u_long	reg_lccr1;
+	u_long	reg_lccr0;
+	u_long	fdadr0;
+	u_long	fdadr1;
+
+	/* DMA descriptors */
+	struct	pxafb_dma_descriptor *	dmadesc_fblow;
+	struct	pxafb_dma_descriptor *	dmadesc_fbhigh;
+	struct	pxafb_dma_descriptor *	dmadesc_palette;
+
+	u_long	screen;		/* physical address of frame buffer */
+	u_long	palette;	/* physical address of palette memory */
+	u_int	palette_size;
+};
+
+/*
+ * LCD controller stucture for PXA CPU
+ */
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 640) */
+	ushort	vl_row;		/* Number of rows (i.e. 480) */
+	ushort	vl_width;	/* Width of display area in millimeters */
+	ushort	vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u_char	vl_clkp;	/* Clock polarity */
+	u_char	vl_oep;		/* Output Enable polarity */
+	u_char	vl_hsp;		/* Horizontal Sync polarity */
+	u_char	vl_vsp;		/* Vertical Sync polarity */
+	u_char	vl_dp;		/* Data polarity */
+	u_char	vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
+	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
+	u_char	vl_splt;	/* Split display, 0 = single-scan, 1 = dual-scan */
+	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
+	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
+
+	/* Horizontal control register. Timing from data sheet */
+	ushort	vl_hpw;		/* Horz sync pulse width */
+	u_char	vl_blw;		/* Wait before of line */
+	u_char	vl_elw;		/* Wait end of line */
+
+	/* Vertical control register. */
+	u_char	vl_vpw;		/* Vertical sync pulse width */
+	u_char	vl_bfw;		/* Wait before of frame */
+	u_char	vl_efw;		/* Wait end of frame */
+
+	/* PXA LCD controller params */
+	struct	pxafb_info pxa;
+} vidinfo_t;
+
+extern vidinfo_t panel_info;
+
+#endif /* CONFIG_MPC823 or CONFIG_PXA250 */
+
+/* Video functions */
+
+#if defined(CONFIG_RBC823)
+void	lcd_disable	(void);
+#endif
+
+
+/* int	lcd_init	(void *lcdbase); */
+void	lcd_putc	(const char c);
+void	lcd_puts	(const char *s);
+void	lcd_printf	(const char *fmt, ...);
+
+
+/************************************************************************/
+/* ** BITMAP DISPLAY SUPPORT						*/
+/************************************************************************/
+#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
+# include <bmp_layout.h>
+# include <asm/byteorder.h>
+#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */
+
+/*
+ *  Information about displays we are using. This is for configuring
+ *  the LCD controller and memory allocation. Someone has to know what
+ *  is connected, as we can't autodetect anything.
+ */
+#define CFG_HIGH	0	/* Pins are active high			*/
+#define CFG_LOW		1	/* Pins are active low			*/
+
+#define LCD_MONOCHROME	0
+#define LCD_COLOR2	1
+#define LCD_COLOR4	2
+#define LCD_COLOR8	3
+#define LCD_COLOR16	4
+
+/*----------------------------------------------------------------------*/
+#if defined(CONFIG_LCD_INFO_BELOW_LOGO)
+# define LCD_INFO_X		0
+# define LCD_INFO_Y		(BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT)
+#elif defined(CONFIG_LCD_LOGO)
+# define LCD_INFO_X		(BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH)
+# define LCD_INFO_Y		(VIDEO_FONT_HEIGHT)
+#else
+# define LCD_INFO_X		(VIDEO_FONT_WIDTH)
+# define LCD_INFO_Y		(VIDEO_FONT_HEIGHT)
+#endif
+
+/* Default to 8bpp if bit depth not specified */
+#ifndef LCD_BPP
+# define LCD_BPP			LCD_COLOR8
+#endif
+#ifndef LCD_DF
+# define LCD_DF			1
+#endif
+
+/* Calculate nr. of bits per pixel  and nr. of colors */
+#define NBITS(bit_code)		(1 << (bit_code))
+#define NCOLORS(bit_code)	(1 << NBITS(bit_code))
+
+/************************************************************************/
+/* ** CONSOLE CONSTANTS							*/
+/************************************************************************/
+#if LCD_BPP == LCD_MONOCHROME
+
+/*
+ * Simple black/white definitions
+ */
+# define CONSOLE_COLOR_BLACK	0
+# define CONSOLE_COLOR_WHITE	1	/* Must remain last / highest	*/
+
+#elif LCD_BPP == LCD_COLOR8
+
+/*
+ * 8bpp color definitions
+ */
+# define CONSOLE_COLOR_BLACK	0
+# define CONSOLE_COLOR_RED	1
+# define CONSOLE_COLOR_GREEN	2
+# define CONSOLE_COLOR_YELLOW	3
+# define CONSOLE_COLOR_BLUE	4
+# define CONSOLE_COLOR_MAGENTA	5
+# define CONSOLE_COLOR_CYAN	6
+# define CONSOLE_COLOR_GREY	14
+# define CONSOLE_COLOR_WHITE	15	/* Must remain last / highest	*/
+
+#else
+
+/*
+ * 16bpp color definitions
+ */
+# define CONSOLE_COLOR_BLACK	0x0000
+# define CONSOLE_COLOR_WHITE	0xffff	/* Must remain last / highest	*/
+
+#endif /* color definitions */
+
+/************************************************************************/
+#ifndef PAGE_SIZE
+# define PAGE_SIZE	4096
+#endif
+
+/************************************************************************/
+/* ** CONSOLE DEFINITIONS & FUNCTIONS					*/
+/************************************************************************/
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
+# define CONSOLE_ROWS		((panel_info.vl_row-BMP_LOGO_HEIGHT) \
+					/ VIDEO_FONT_HEIGHT)
+#else
+# define CONSOLE_ROWS		(panel_info.vl_row / VIDEO_FONT_HEIGHT)
+#endif
+
+#define CONSOLE_COLS		(panel_info.vl_col / VIDEO_FONT_WIDTH)
+#define CONSOLE_ROW_SIZE	(VIDEO_FONT_HEIGHT * lcd_line_length)
+#define CONSOLE_ROW_FIRST	(lcd_console_address)
+#define CONSOLE_ROW_SECOND	(lcd_console_address + CONSOLE_ROW_SIZE)
+#define CONSOLE_ROW_LAST	(lcd_console_address + CONSOLE_SIZE \
+					- CONSOLE_ROW_SIZE)
+#define CONSOLE_SIZE		(CONSOLE_ROW_SIZE * CONSOLE_ROWS)
+#define CONSOLE_SCROLL_SIZE	(CONSOLE_SIZE - CONSOLE_ROW_SIZE)
+
+#if LCD_BPP == LCD_MONOCHROME
+# define COLOR_MASK(c)		((c)	  | (c) << 1 | (c) << 2 | (c) << 3 | \
+				 (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
+#elif LCD_BPP == LCD_COLOR8
+# define COLOR_MASK(c)		(c)
+#else
+# error Unsupported LCD BPP.
+#endif
+
+/************************************************************************/
+
+#endif	/* _LCD_H_ */
diff --git a/include/lcdvideo.h b/include/lcdvideo.h
new file mode 100755
index 0000000..f0640a5
--- /dev/null
+++ b/include/lcdvideo.h
@@ -0,0 +1,69 @@
+/*
+ * MPC823 LCD and Video Controller
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ */
+#ifndef __LCDVIDEO_H__
+#define __LCDVIDEO_H__
+
+
+/* LCD Controller Configuration Register.
+*/
+#define LCCR_BNUM	((uint)0xfffe0000)
+#define LCCR_EIEN	((uint)0x00010000)
+#define LCCR_IEN	((uint)0x00008000)
+#define LCCR_IRQL	((uint)0x00007000)
+#define LCCR_CLKP	((uint)0x00000800)
+#define LCCR_OEP	((uint)0x00000400)
+#define LCCR_HSP	((uint)0x00000200)
+#define LCCR_VSP	((uint)0x00000100)
+#define LCCR_DP		((uint)0x00000080)
+#define LCCR_BPIX	((uint)0x00000060)
+#define LCCR_LBW	((uint)0x00000010)
+#define LCCR_SPLT	((uint)0x00000008)
+#define LCCR_CLOR	((uint)0x00000004)
+#define LCCR_TFT	((uint)0x00000002)
+#define LCCR_PON	((uint)0x00000001)
+
+/* Define the bit shifts to load values into the register.
+*/
+#define LCDBIT(BIT, VAL)	((VAL) << (31 - BIT))
+
+#define LCCR_BNUM_BIT	((uint)14)
+#define LCCR_EIEN_BIT	((uint)15)
+#define LCCR_IEN_BIT	((uint)16)
+#define LCCR_IROL_BIT	((uint)19)
+#define LCCR_CLKP_BIT	((uint)20)
+#define LCCR_OEP_BIT	((uint)21)
+#define LCCR_HSP_BIT	((uint)22)
+#define LCCR_VSP_BIT	((uint)23)
+#define LCCR_DP_BIT	((uint)24)
+#define LCCR_BPIX_BIT	((uint)26)
+#define LCCR_LBW_BIT	((uint)27)
+#define LCCR_SPLT_BIT	((uint)28)
+#define LCCR_CLOR_BIT	((uint)29)
+#define LCCR_TFT_BIT	((uint)30)
+#define LCCR_PON_BIT	((uint)31)
+
+/* LCD Horizontal control register.
+*/
+#define LCHCR_BO	((uint)0x01000000)
+#define LCHCR_AT	((uint)0x00e00000)
+#define LCHCR_HPC	((uint)0x001ffc00)
+#define LCHCR_WBL	((uint)0x000003ff)
+
+#define LCHCR_AT_BIT	((uint)10)
+#define LCHCR_HPC_BIT	((uint)21)
+#define LCHCR_WBL_BIT	((uint)31)
+
+/* LCD Vertical control register.
+*/
+#define LCVCR_VPW	((uint)0xf0000000)
+#define LCVCR_LCD_AC	((uint)0x01e00000)
+#define LCVCR_VPC	((uint)0x001ff800)
+#define LCVCR_WBF	((uint)0x000003ff)
+
+#define LCVCR_VPW_BIT	((uint)3)
+#define LCVCR_LCD_AC_BIT ((uint)10)
+#define LCVCR_VPC_BIT	((uint)20)
+
+#endif /* __LCDVIDEO_H__ */
diff --git a/include/lh7a400.h b/include/lh7a400.h
new file mode 100755
index 0000000..d1e70a2
--- /dev/null
+++ b/include/lh7a400.h
@@ -0,0 +1,75 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * lh7a400 SoC interface
+ */
+
+#ifndef __LH7A400_H__
+#define __LH7A400_H__
+
+#include "lh7a40x.h"
+
+/* Interrupt Controller (userguide 8.2.1) */
+typedef struct {
+	volatile u32  intsr;
+	volatile u32  intrsr;
+	volatile u32  intens;
+	volatile u32  intenc;
+	volatile u32  rsvd1;
+	volatile u32  rsvd2;
+	volatile u32  rsvd3;
+} /*__attribute__((__packed__))*/ lh7a400_interrupt_t;
+#define LH7A400_INTERRUPT_BASE    (0x80000500)
+#define LH7A400_INTERRUPT_PTR     ((lh7a400_interrupt_t*) LH7A400_INTERRUPT_BASE)
+
+/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */
+typedef struct {
+	lh7a40x_dmachan_t  chan[15];
+	volatile u32       glblint;
+	volatile u32       rsvd1;
+	volatile u32       rsvd2;
+	volatile u32       rsvd3;
+} /*__attribute__((__packed__))*/ lh7a400_dma_t;
+
+#define LH7A400_DMA_BASE      (0x80002800)
+#define DMA_USBTX_OFFSET      (0x000)
+#define DMA_USBRX_OFFSET      (0x040)
+#define DMA_MMCTX_OFFSET      (0x080)
+#define DMA_MMCRX_OFFSET      (0x0C0)
+#define DMA_AC97_BASE         (0x80002A00)
+
+#define LH7A400_DMA_PTR    ((lh7a400_dma_t*) LH7A400_DMA_BASE)
+#define LH7A400_DMA_USBTX \
+	((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBTX_OFFSET))
+#define LH7A400_DMA_USBRX \
+	((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBRX_OFFSET))
+#define LH7A400_DMA_MMCTX \
+	((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCTX_OFFSET))
+#define LH7A400_DMA_MMCRX \
+	((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCRX_OFFSET))
+#define LH7A400_AC97RX(n) \
+	((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \
+	((2*n) * sizeof(lh7a400_dmachan_t))))
+#define LH7A400_AC97TX(n) \
+	((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \
+	(((2*n)+1) * sizeof(lh7a400_dmachan_t))))
+
+#endif  /* __LH7A400_H__ */
diff --git a/include/lh7a404.h b/include/lh7a404.h
new file mode 100755
index 0000000..4098af3
--- /dev/null
+++ b/include/lh7a404.h
@@ -0,0 +1,83 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * lh7a404 SoC interface
+ */
+
+#ifndef __LH7A404_H__
+#define __LH7A404_H__
+
+#include "lh7a40x.h"
+
+/* Interrupt Controller (userguide 8.2.1) */
+typedef struct {
+	volatile u32  irqstatus;
+	volatile u32  fiqstatus;
+	volatile u32  rawintr;
+	volatile u32  intsel;
+	volatile u32  inten;
+	volatile u32  intenclr;
+	volatile u32  softint;
+	volatile u32  softintclr;
+	volatile u32  protect;
+	volatile u32  unused1;
+	volatile u32  unused2;
+	volatile u32  vectaddr;
+	volatile u32  nvaddr;
+	volatile u32  unused3[32];
+	volatile u32  vad[16];
+	volatile u32  unused4[44];
+	volatile u32  vectcntl[16];
+	volatile u32  unused5[44];
+	volatile u32  itcr;
+	volatile u32  itip1;
+	volatile u32  itip2;
+	volatile u32  itop1;
+	volatile u32  itop2;
+	volatile u32  unused6[333];
+	volatile u32  periphid[4];
+	volatile u32  pcellid[4];
+} /*__attribute__((__packed__))*/ lh7a404_vic_t;
+#define LH7A404_VIC_BASE	(0x80008000)
+#define LH7A400_VIC_PTR(x)  ((lh7a404_vic_t*)(LH7A400_VIC_BASE + (x*0x2000)))
+
+
+typedef struct {
+	lh7a40x_dmachan_t  m2p0_tx;
+	lh7a40x_dmachan_t  m2p1_rx;
+	lh7a40x_dmachan_t  m2p2_tx;
+	lh7a40x_dmachan_t  m2p3_rx;
+	lh7a40x_dmachan_t  m2m0;
+	lh7a40x_dmachan_t  m2m1;
+	lh7a40x_dmachan_t  unused1;
+	lh7a40x_dmachan_t  unused2;
+	lh7a40x_dmachan_t  m2p5_rx;
+	lh7a40x_dmachan_t  m2p4_tx;
+	lh7a40x_dmachan_t  m2p7_rx;
+	lh7a40x_dmachan_t  m2p6_tx;
+	lh7a40x_dmachan_t  m2p9_rx;
+	lh7a40x_dmachan_t  m2p8_tx;
+	volatile u32       chanarb;
+	volatile u32       glblint;
+} /*__attribute__((__packed__))*/ lh7a400_dma_t;
+
+
+#endif  /* __LH7A404_H__ */
diff --git a/include/lh7a40x.h b/include/lh7a40x.h
new file mode 100755
index 0000000..c897a7c
--- /dev/null
+++ b/include/lh7a40x.h
@@ -0,0 +1,279 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * lh7a40x SoC series common interface
+ */
+
+#ifndef __LH7A40X_H__
+#define __LH7A40X_H__
+
+/* (SMC) Static Memory Controller (usersguide 4.2.1) */
+typedef struct {
+	volatile u32  attib;
+	volatile u32  com;
+	volatile u32  io;
+	volatile u32  rsvd1;
+} /*__attribute__((__packed__))*/ lh7a40x_pccard_t;
+
+typedef struct {
+	volatile u32      bcr[8];
+	lh7a40x_pccard_t  pccard[2];
+	volatile u32	  pcmciacon;
+} /*__attribute__((__packed__))*/ lh7a40x_smc_t;
+#define LH7A40X_SMC_BASE  (0x80002000)
+#define LH7A40X_SMC_PTR   ((lh7a40x_smc_t*) LH7A40X_SMC_BASE)
+
+/* (SDMC) Synchronous Dynamic Ram Controller (usersguide 5.3.1) */
+typedef struct {
+	volatile u32  rsvd1;
+	volatile u32  gblcnfg;
+	volatile u32  rfshtmr;
+	volatile u32  bootstat;
+	volatile u32  sdcsc[4];
+} /*__attribute__((__packed__))*/ lh7a40x_sdmc_t;
+#define LH7A40X_SDMC_BASE  (0x80002400)
+#define LH7A40X_SDMC_PTR   ((lh7a40x_sdmc_t*) LH7A40X_SDMC_BASE)
+
+/* (CSC) Clock and State Controller (userguide 6.2.1) */
+typedef struct {
+	volatile u32  pwrsr;
+	volatile u32  pwrcnt;
+	volatile u32  halt;
+	volatile u32  stby;
+	volatile u32  bleoi;
+	volatile u32  mceoi;
+	volatile u32  teoi;
+	volatile u32  stfclr;
+	volatile u32  clkset;
+	volatile u32  scrreg[2];
+	volatile u32  rsvd1;
+	volatile u32  usbreset;
+} /*__attribute__((__packed__))*/ lh7a40x_csc_t;
+#define LH7A40X_STPWR_BASE  (0x80000400)
+#define LH7A40X_CSC_PTR     ((lh7a40x_csc_t*) LH7A40X_STPWR_BASE)
+
+#define CLKSET_SMCROM		(0x01000000)
+#define CLKSET_PS		(0x000C0000)
+#define CLKSET_PS_0		(0x00000000)
+#define CLKSET_PS_1		(0x00040000)
+#define CLKSET_PS_2		(0x00080000)
+#define CLKSET_PS_3		(0x000C0000)
+#define CLKSET_PCLKDIV		(0x00030000)
+#define CLKSET_PCLKDIV_2	(0x00000000)
+#define CLKSET_PCLKDIV_4	(0x00010000)
+#define CLKSET_PCLKDIV_8	(0x00020000)
+#define CLKSET_MAINDIV2		(0x0000f800)
+#define CLKSET_MAINDIV1		(0x00000780)
+#define CLKSET_PREDIV		(0x0000007C)
+#define CLKSET_HCLKDIV		(0x00000003)
+
+/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */
+typedef struct {
+	volatile u32  maxcnt;
+	volatile u32  base;
+	volatile u32  current;
+	volatile u32  rsvd1;
+} lh7a40x_dmabuf_t;
+
+typedef struct {
+	volatile u32      control;
+	volatile u32      interrupt;
+	volatile u32      rsvd1;
+	volatile u32      status;
+	volatile u32      rsvd2;
+	volatile u32      remain;
+	volatile u32      rsvd3;
+	volatile u32      rsvd4;
+	lh7a40x_dmabuf_t  buf[2];
+} /*__attribute__((__packed__))*/ lh7a40x_dmachan_t;
+
+
+/* (WDT) Watchdog Timer (userguide 11.2.1) */
+typedef struct {
+	volatile u32  ctl;
+	volatile u32  rst;
+	volatile u32  status;
+	volatile u32  count[4];
+} /*__attribute__((__packed__))*/ lh7a40x_wdt_t;
+#define LH7A40X_WDT_BASE    (0x80001400)
+#define LH7A40X_WDT_PTR     ((lh7a40x_wdt_t*) LH7A40X_WDT_BASE)
+
+/* (RTC) Real Time Clock (lh7a400 userguide 12.2.1, lh7a404 userguide 13.2.1) */
+typedef struct {
+	volatile u32  rtcdr;
+	volatile u32  rtclr;
+	volatile u32  rtcmr;
+	volatile u32  unk1;
+	volatile u32  rtcstat_eoi;
+	volatile u32  rtccr;
+	volatile u32  rsvd1[58];
+} /*__attribute__((__packed__))*/ lh7a40x_rtc_t;
+#define LH7A40X_RTC_BASE    (0x80000D00)
+#define LH7A40X_RTC_PTR     ((lh7a40x_rtc_t*) LH7A40X_RTC_BASE)
+
+/* Timers (lh7a400 userguide 13.2.1, lh7a404 userguide 11.2.1) */
+typedef struct {
+	volatile u32  load;
+	volatile u32  value;
+	volatile u32  control;
+	volatile u32  tceoi;
+} /*__attribute__((__packed__))*/ lh7a40x_timer_t;
+
+typedef struct {
+	lh7a40x_timer_t  timer1;
+	volatile u32     rsvd1[4];
+	lh7a40x_timer_t  timer2;
+	volatile u32     unk1[4];
+	volatile u32     bzcon;
+	volatile u32     unk2[15];
+	lh7a40x_timer_t  timer3;
+	/*volatile u32     rsvd2;*/
+} /*__attribute__((__packed__))*/ lh7a40x_timers_t;
+#define LH7A40X_TIMERS_BASE    (0x80000C00)
+#define LH7A40X_TIMERS_PTR     ((lh7a40x_timers_t*) LH7A40X_TIMERS_BASE)
+
+#define TIMER_EN	(0x00000080)
+#define TIMER_PER	(0x00000040)
+#define TIMER_FREE	(0x00000000)
+#define TIMER_CLK508K	(0x00000008)
+#define TIMER_CLK2K	(0x00000000)
+
+/* (SSP) Sychronous Serial Ports (lh7a400 userguide 14.2.1, lh7a404 userguide 14.2.1) */
+typedef struct {
+	volatile u32  cr0;
+	volatile u32  cr1;
+	volatile u32  irr_roeoi;
+	volatile u32  dr;
+	volatile u32  cpr;
+	volatile u32  sr;
+	/*volatile u32  rsvd1[58];*/
+} /*__attribute__((__packed__))*/ lh7a40x_ssp_t;
+#define LH7A40X_SSP_BASE    (0x80000B00)
+#define LH7A40X_SSP_PTR     ((lh7a40x_ssp_t*) LH7A40X_SSP_BASE)
+
+/* (UART) Universal Asychronous Receiver/Transmitter (lh7a400 userguide 15.2.1, lh7a404 userguide 15.2.1) */
+typedef struct {
+	volatile u32  data;
+	volatile u32  fcon;
+	volatile u32  brcon;
+	volatile u32  con;
+	volatile u32  status;
+	volatile u32  rawisr;
+	volatile u32  inten;
+	volatile u32  isr;
+	volatile u32  rsvd1[56];
+} /*__attribute__((__packed__))*/ lh7a40x_uart_t;
+#define LH7A40X_UART_BASE    (0x80000600)
+#define LH7A40X_UART_PTR(n) \
+	((lh7a40x_uart_t*) (LH7A40X_UART_BASE + ((n-1) * sizeof(lh7a40x_uart_t))))
+
+#define UART_BE		(0x00000800)      /* the rx error bits */
+#define UART_OE		(0x00000400)
+#define UART_PE		(0x00000200)
+#define UART_FE		(0x00000100)
+
+#define UART_WLEN	(0x00000060)	/* fcon bits */
+#define UART_WLEN_8	(0x00000060)
+#define UART_WLEN_7	(0x00000040)
+#define UART_WLEN_6	(0x00000020)
+#define UART_WLEN_5	(0x00000000)
+#define UART_FEN	(0x00000010)
+#define UART_STP2	(0x00000008)
+#define UART_STP2_2	(0x00000008)
+#define UART_STP2_1	(0x00000000)
+#define UART_EPS	(0x00000004)
+#define UART_EPS_EVEN	(0x00000004)
+#define UART_EPS_ODD	(0x00000000)
+#define UART_PEN	(0x00000002)
+#define UART_BRK	(0x00000001)
+
+#define UART_BAUDDIV	(0x0000ffff)	/* brcon bits */
+
+#define UART_SIRBD	(0x00000080)	/* con bits */
+#define UART_LBE	(0x00000040)
+#define UART_MXP	(0x00000020)
+#define UART_TXP	(0x00000010)
+#define UART_RXP	(0x00000008)
+#define UART_SIRLP	(0x00000004)
+#define UART_SIRD	(0x00000002)
+#define UART_EN		(0x00000001)
+
+#define UART_TXFE	(0x00000080)	/* status bits */
+#define UART_RXFF	(0x00000040)
+#define UART_TXFF	(0x00000020)
+#define UART_RXFE	(0x00000010)
+#define UART_BUSY	(0x00000008)
+#define UART_DCD	(0x00000004)
+#define UART_DSR	(0x00000002)
+#define UART_CTS	(0x00000001)
+
+#define UART_MSEOI	(0xfffffff0)	/* rawisr interrupt bits */
+
+#define UART_RTI	(0x00000008)	/* generic interrupt bits */
+#define UART_MI		(0x00000004)
+#define UART_TI		(0x00000002)
+#define UART_RI		(0x00000001)
+
+/* (GPIO) General Purpose IO and External Interrupts (userguide 16.2.1) */
+typedef struct {
+	volatile u32  pad;
+	volatile u32  pbd;
+	volatile u32  pcd;
+	volatile u32  pdd;
+	volatile u32  padd;
+	volatile u32  pbdd;
+	volatile u32  pcdd;
+	volatile u32  pddd;
+	volatile u32  ped;
+	volatile u32  pedd;
+	volatile u32  kbdctl;
+	volatile u32  pinmux;
+	volatile u32  pfd;
+	volatile u32  pfdd;
+	volatile u32  pgd;
+	volatile u32  pgdd;
+	volatile u32  phd;
+	volatile u32  phdd;
+	volatile u32  rsvd1;
+	volatile u32  inttype1;
+	volatile u32  inttype2;
+	volatile u32  gpiofeoi;
+	volatile u32  gpiointen;
+	volatile u32  intstatus;
+	volatile u32  rawintstatus;
+	volatile u32  gpiodb;
+	volatile u32  papd;
+	volatile u32  pbpd;
+	volatile u32  pcpd;
+	volatile u32  pdpd;
+	volatile u32  pepd;
+	volatile u32  pfpd;
+	volatile u32  pgpd;
+	volatile u32  phpd;
+} /*__attribute__((__packed__))*/ lh7a40x_gpioint_t;
+#define LH7A40X_GPIOINT_BASE    (0x80000E00)
+#define LH7A40X_GPIOINT_PTR     ((lh7a40x_gpioint_t*) LH7A40X_GPIOINT_BASE)
+
+/* Embedded SRAM */
+#define CFG_SRAM_BASE	(0xB0000000)
+#define CFG_SRAM_SIZE	(80*1024)	/* 80kB */
+
+#endif  /* __LH7A40X_H__ */
diff --git a/include/linux/aes.h b/include/linux/aes.h
new file mode 100644
index 0000000..a69376a
--- /dev/null
+++ b/include/linux/aes.h
@@ -0,0 +1,213 @@
+/**
+ * \file aes.h
+ *
+ * \brief AES block cipher
+ *
+ *  Copyright (C) 2006-2013, Brainspark B.V.
+ *
+ *  This file is part of PolarSSL (http://www.polarssl.org)
+ *  Lead Maintainer: Paul Bakker <polarssl_maintainer at polarssl.org>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef POLARSSL_AES_H
+#define POLARSSL_AES_H
+
+#include "config.h"
+
+//#include <string.h>
+
+#if defined(_MSC_VER) && !defined(EFIX64) && !defined(EFI32)
+#include <basetsd.h>
+typedef UINT32 uint32_t;
+#else
+//#include <inttypes.h>
+#include <linux/types.h>
+#endif
+
+/* padlock.c and aesni.c rely on these values! */
+#define AES_ENCRYPT     1
+#define AES_DECRYPT     0
+
+#define POLARSSL_ERR_AES_INVALID_KEY_LENGTH                -0x0020  /**< Invalid key length. */
+#define POLARSSL_ERR_AES_INVALID_INPUT_LENGTH              -0x0022  /**< Invalid data input length. */
+
+#if !defined(POLARSSL_AES_ALT)
+// Regular implementation
+//
+
+#define POLARSSL_CIPHER_MODE_CBC
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          AES context structure
+ *
+ * \note           buf is able to hold 32 extra bytes, which can be used:
+ *                 - for alignment purposes if VIA padlock is used, and/or
+ *                 - to simplify key expansion in the 256-bit case by
+ *                 generating an extra round key
+ */
+typedef struct
+{
+    int nr;                     /*!<  number of rounds  */
+    uint32_t *rk;               /*!<  AES round keys    */
+    uint32_t buf[68];           /*!<  unaligned data    */
+}
+aes_context;
+
+/**
+ * \brief          AES key schedule (encryption)
+ *
+ * \param ctx      AES context to be initialized
+ * \param key      encryption key
+ * \param keysize  must be 128, 192 or 256
+ *
+ * \return         0 if successful, or POLARSSL_ERR_AES_INVALID_KEY_LENGTH
+ */
+int aes_setkey_enc( aes_context *ctx, const unsigned char *key, unsigned int keysize );
+
+/**
+ * \brief          AES key schedule (decryption)
+ *
+ * \param ctx      AES context to be initialized
+ * \param key      decryption key
+ * \param keysize  must be 128, 192 or 256
+ *
+ * \return         0 if successful, or POLARSSL_ERR_AES_INVALID_KEY_LENGTH
+ */
+int aes_setkey_dec( aes_context *ctx, const unsigned char *key, unsigned int keysize );
+
+/**
+ * \brief          AES-ECB block encryption/decryption
+ *
+ * \param ctx      AES context
+ * \param mode     AES_ENCRYPT or AES_DECRYPT
+ * \param input    16-byte input block
+ * \param output   16-byte output block
+ *
+ * \return         0 if successful
+ */
+int aes_crypt_ecb( aes_context *ctx,
+                    int mode,
+                    const unsigned char input[16],
+                    unsigned char output[16] );
+
+#if defined(POLARSSL_CIPHER_MODE_CBC)
+/**
+ * \brief          AES-CBC buffer encryption/decryption
+ *                 Length should be a multiple of the block
+ *                 size (16 bytes)
+ *
+ * \param ctx      AES context
+ * \param mode     AES_ENCRYPT or AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful, or POLARSSL_ERR_AES_INVALID_INPUT_LENGTH
+ */
+int aes_crypt_cbc( aes_context *ctx,
+                    int mode,
+                    size_t length,
+                    unsigned char iv[16],
+                    const unsigned char *input,
+                    unsigned char *output );
+#endif /* POLARSSL_CIPHER_MODE_CBC */
+
+/**
+ * \brief          AES-CFB128 buffer encryption/decryption.
+ *
+ * Note: Due to the nature of CFB you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
+ *
+ * \param ctx      AES context
+ * \param mode     AES_ENCRYPT or AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv_off   offset in IV (updated after use)
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful
+ */
+int aes_crypt_cfb128( aes_context *ctx,
+                       int mode,
+                       size_t length,
+                       size_t *iv_off,
+                       unsigned char iv[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+
+/**
+ * \brief               AES-CTR buffer encryption/decryption
+ *
+ * Warning: You have to keep the maximum use of your counter in mind!
+ *
+ * Note: Due to the nature of CTR you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
+ *
+ * \param ctx           AES context
+ * \param length        The length of the data
+ * \param nc_off        The offset in the current stream_block (for resuming
+ *                      within current cipher stream). The offset pointer to
+ *                      should be 0 at the start of a stream.
+ * \param nonce_counter The 128-bit nonce and counter.
+ * \param stream_block  The saved stream-block for resuming. Is overwritten
+ *                      by the function.
+ * \param input         The input data stream
+ * \param output        The output data stream
+ *
+ * \return         0 if successful
+ */
+int aes_crypt_ctr( aes_context *ctx,
+                       size_t length,
+                       size_t *nc_off,
+                       unsigned char nonce_counter[16],
+                       unsigned char stream_block[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+
+#ifdef __cplusplus
+}
+#endif
+
+#else  /* POLARSSL_AES_ALT */
+#include "aes_alt.h"
+#endif /* POLARSSL_AES_ALT */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int aes_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* aes.h */
diff --git a/include/linux/bitops.h b/include/linux/bitops.h
new file mode 100755
index 0000000..1abba4c
--- /dev/null
+++ b/include/linux/bitops.h
@@ -0,0 +1,101 @@
+#ifndef _LINUX_BITOPS_H
+#define _LINUX_BITOPS_H
+
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+static inline int generic_ffs(int x)
+{
+	int r = 1;
+
+	if (!x)
+		return 0;
+	if (!(x & 0xffff)) {
+		x >>= 16;
+		r += 16;
+	}
+	if (!(x & 0xff)) {
+		x >>= 8;
+		r += 8;
+	}
+	if (!(x & 0xf)) {
+		x >>= 4;
+		r += 4;
+	}
+	if (!(x & 3)) {
+		x >>= 2;
+		r += 2;
+	}
+	if (!(x & 1)) {
+		x >>= 1;
+		r += 1;
+	}
+	return r;
+}
+
+static inline int generic_fls(int x)
+{
+        int r = 32;
+
+        if (!x)
+                return 0;
+        if (!(x & 0xffff0000u)) {
+                x <<= 16;
+                r -= 16;
+        }
+        if (!(x & 0xff000000u)) {
+                x <<= 8;
+                r -= 8;
+        }
+        if (!(x & 0xf0000000u)) {
+                x <<= 4;
+                r -= 4;
+        }
+        if (!(x & 0xc0000000u)) {
+                x <<= 2;
+                r -= 2;
+        }
+        if (!(x & 0x80000000u)) {
+                x <<= 1;
+                r -= 1;
+        }
+        return r;
+}
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+static inline unsigned int generic_hweight32(unsigned int w)
+{
+	unsigned int res = (w & 0x55555555) + ((w >> 1) & 0x55555555);
+	res = (res & 0x33333333) + ((res >> 2) & 0x33333333);
+	res = (res & 0x0F0F0F0F) + ((res >> 4) & 0x0F0F0F0F);
+	res = (res & 0x00FF00FF) + ((res >> 8) & 0x00FF00FF);
+	return (res & 0x0000FFFF) + ((res >> 16) & 0x0000FFFF);
+}
+
+static inline unsigned int generic_hweight16(unsigned int w)
+{
+	unsigned int res = (w & 0x5555) + ((w >> 1) & 0x5555);
+	res = (res & 0x3333) + ((res >> 2) & 0x3333);
+	res = (res & 0x0F0F) + ((res >> 4) & 0x0F0F);
+	return (res & 0x00FF) + ((res >> 8) & 0x00FF);
+}
+
+static inline unsigned int generic_hweight8(unsigned int w)
+{
+	unsigned int res = (w & 0x55) + ((w >> 1) & 0x55);
+	res = (res & 0x33) + ((res >> 2) & 0x33);
+	return (res & 0x0F) + ((res >> 4) & 0x0F);
+}
+
+#include <asm/bitops.h>
+
+#define fls generic_fls
+
+#endif
diff --git a/include/linux/byteorder/big_endian.h b/include/linux/byteorder/big_endian.h
new file mode 100755
index 0000000..19b0c86
--- /dev/null
+++ b/include/linux/byteorder/big_endian.h
@@ -0,0 +1,69 @@
+#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H
+#define _LINUX_BYTEORDER_BIG_ENDIAN_H
+
+#ifndef __BIG_ENDIAN
+#define __BIG_ENDIAN 4321
+#endif
+#ifndef __BIG_ENDIAN_BITFIELD
+#define __BIG_ENDIAN_BITFIELD
+#endif
+#define	__BYTE_ORDER	__BIG_ENDIAN
+
+#include <linux/byteorder/swab.h>
+
+#define __constant_htonl(x) ((__u32)(x))
+#define __constant_ntohl(x) ((__u32)(x))
+#define __constant_htons(x) ((__u16)(x))
+#define __constant_ntohs(x) ((__u16)(x))
+#define __constant_cpu_to_le64(x) ___swab64((x))
+#define __constant_le64_to_cpu(x) ___swab64((x))
+#define __constant_cpu_to_le32(x) ___swab32((x))
+#define __constant_le32_to_cpu(x) ___swab32((x))
+#define __constant_cpu_to_le16(x) ___swab16((x))
+#define __constant_le16_to_cpu(x) ___swab16((x))
+#define __constant_cpu_to_be64(x) ((__u64)(x))
+#define __constant_be64_to_cpu(x) ((__u64)(x))
+#define __constant_cpu_to_be32(x) ((__u32)(x))
+#define __constant_be32_to_cpu(x) ((__u32)(x))
+#define __constant_cpu_to_be16(x) ((__u16)(x))
+#define __constant_be16_to_cpu(x) ((__u16)(x))
+#define __cpu_to_le64(x) __swab64((x))
+#define __le64_to_cpu(x) __swab64((x))
+#define __cpu_to_le32(x) __swab32((x))
+#define __le32_to_cpu(x) __swab32((x))
+#define __cpu_to_le16(x) __swab16((x))
+#define __le16_to_cpu(x) __swab16((x))
+#define __cpu_to_be64(x) ((__u64)(x))
+#define __be64_to_cpu(x) ((__u64)(x))
+#define __cpu_to_be32(x) ((__u32)(x))
+#define __be32_to_cpu(x) ((__u32)(x))
+#define __cpu_to_be16(x) ((__u16)(x))
+#define __be16_to_cpu(x) ((__u16)(x))
+#define __cpu_to_le64p(x) __swab64p((x))
+#define __le64_to_cpup(x) __swab64p((x))
+#define __cpu_to_le32p(x) __swab32p((x))
+#define __le32_to_cpup(x) __swab32p((x))
+#define __cpu_to_le16p(x) __swab16p((x))
+#define __le16_to_cpup(x) __swab16p((x))
+#define __cpu_to_be64p(x) (*(__u64*)(x))
+#define __be64_to_cpup(x) (*(__u64*)(x))
+#define __cpu_to_be32p(x) (*(__u32*)(x))
+#define __be32_to_cpup(x) (*(__u32*)(x))
+#define __cpu_to_be16p(x) (*(__u16*)(x))
+#define __be16_to_cpup(x) (*(__u16*)(x))
+#define __cpu_to_le64s(x) __swab64s((x))
+#define __le64_to_cpus(x) __swab64s((x))
+#define __cpu_to_le32s(x) __swab32s((x))
+#define __le32_to_cpus(x) __swab32s((x))
+#define __cpu_to_le16s(x) __swab16s((x))
+#define __le16_to_cpus(x) __swab16s((x))
+#define __cpu_to_be64s(x) do {} while (0)
+#define __be64_to_cpus(x) do {} while (0)
+#define __cpu_to_be32s(x) do {} while (0)
+#define __be32_to_cpus(x) do {} while (0)
+#define __cpu_to_be16s(x) do {} while (0)
+#define __be16_to_cpus(x) do {} while (0)
+
+#include <linux/byteorder/generic.h>
+
+#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */
diff --git a/include/linux/byteorder/generic.h b/include/linux/byteorder/generic.h
new file mode 100755
index 0000000..cff850f
--- /dev/null
+++ b/include/linux/byteorder/generic.h
@@ -0,0 +1,180 @@
+#ifndef _LINUX_BYTEORDER_GENERIC_H
+#define _LINUX_BYTEORDER_GENERIC_H
+
+/*
+ * linux/byteorder_generic.h
+ * Generic Byte-reordering support
+ *
+ * Francois-Rene Rideau <fare@tunes.org> 19970707
+ *    gathered all the good ideas from all asm-foo/byteorder.h into one file,
+ *    cleaned them up.
+ *    I hope it is compliant with non-GCC compilers.
+ *    I decided to put __BYTEORDER_HAS_U64__ in byteorder.h,
+ *    because I wasn't sure it would be ok to put it in types.h
+ *    Upgraded it to 2.1.43
+ * Francois-Rene Rideau <fare@tunes.org> 19971012
+ *    Upgraded it to 2.1.57
+ *    to please Linus T., replaced huge #ifdef's between little/big endian
+ *    by nestedly #include'd files.
+ * Francois-Rene Rideau <fare@tunes.org> 19971205
+ *    Made it to 2.1.71; now a facelift:
+ *    Put files under include/linux/byteorder/
+ *    Split swab from generic support.
+ *
+ * TODO:
+ *   = Regular kernel maintainers could also replace all these manual
+ *    byteswap macros that remain, disseminated among drivers,
+ *    after some grep or the sources...
+ *   = Linus might want to rename all these macros and files to fit his taste,
+ *    to fit his personal naming scheme.
+ *   = it seems that a few drivers would also appreciate
+ *    nybble swapping support...
+ *   = every architecture could add their byteswap macro in asm/byteorder.h
+ *    see how some architectures already do (i386, alpha, ppc, etc)
+ *   = cpu_to_beXX and beXX_to_cpu might some day need to be well
+ *    distinguished throughout the kernel. This is not the case currently,
+ *    since little endian, big endian, and pdp endian machines needn't it.
+ *    But this might be the case for, say, a port of Linux to 20/21 bit
+ *    architectures (and F21 Linux addict around?).
+ */
+
+/*
+ * The following macros are to be defined by <asm/byteorder.h>:
+ *
+ * Conversion of long and short int between network and host format
+ *	ntohl(__u32 x)
+ *	ntohs(__u16 x)
+ *	htonl(__u32 x)
+ *	htons(__u16 x)
+ * It seems that some programs (which? where? or perhaps a standard? POSIX?)
+ * might like the above to be functions, not macros (why?).
+ * if that's true, then detect them, and take measures.
+ * Anyway, the measure is: define only ___ntohl as a macro instead,
+ * and in a separate file, have
+ * unsigned long inline ntohl(x){return ___ntohl(x);}
+ *
+ * The same for constant arguments
+ *	__constant_ntohl(__u32 x)
+ *	__constant_ntohs(__u16 x)
+ *	__constant_htonl(__u32 x)
+ *	__constant_htons(__u16 x)
+ *
+ * Conversion of XX-bit integers (16- 32- or 64-)
+ * between native CPU format and little/big endian format
+ * 64-bit stuff only defined for proper architectures
+ *	cpu_to_[bl]eXX(__uXX x)
+ *	[bl]eXX_to_cpu(__uXX x)
+ *
+ * The same, but takes a pointer to the value to convert
+ *	cpu_to_[bl]eXXp(__uXX x)
+ *	[bl]eXX_to_cpup(__uXX x)
+ *
+ * The same, but change in situ
+ *	cpu_to_[bl]eXXs(__uXX x)
+ *	[bl]eXX_to_cpus(__uXX x)
+ *
+ * See asm-foo/byteorder.h for examples of how to provide
+ * architecture-optimized versions
+ *
+ */
+
+
+#if defined(__KERNEL__)
+/*
+ * inside the kernel, we can use nicknames;
+ * outside of it, we must avoid POSIX namespace pollution...
+ */
+#define cpu_to_le64 __cpu_to_le64
+#define le64_to_cpu __le64_to_cpu
+#define cpu_to_le32 __cpu_to_le32
+#define le32_to_cpu __le32_to_cpu
+#define cpu_to_le16 __cpu_to_le16
+#define le16_to_cpu __le16_to_cpu
+#define cpu_to_be64 __cpu_to_be64
+#define be64_to_cpu __be64_to_cpu
+#define cpu_to_be32 __cpu_to_be32
+#define be32_to_cpu __be32_to_cpu
+#define cpu_to_be16 __cpu_to_be16
+#define be16_to_cpu __be16_to_cpu
+#define cpu_to_le64p __cpu_to_le64p
+#define le64_to_cpup __le64_to_cpup
+#define cpu_to_le32p __cpu_to_le32p
+#define le32_to_cpup __le32_to_cpup
+#define cpu_to_le16p __cpu_to_le16p
+#define le16_to_cpup __le16_to_cpup
+#define cpu_to_be64p __cpu_to_be64p
+#define be64_to_cpup __be64_to_cpup
+#define cpu_to_be32p __cpu_to_be32p
+#define be32_to_cpup __be32_to_cpup
+#define cpu_to_be16p __cpu_to_be16p
+#define be16_to_cpup __be16_to_cpup
+#define cpu_to_le64s __cpu_to_le64s
+#define le64_to_cpus __le64_to_cpus
+#define cpu_to_le32s __cpu_to_le32s
+#define le32_to_cpus __le32_to_cpus
+#define cpu_to_le16s __cpu_to_le16s
+#define le16_to_cpus __le16_to_cpus
+#define cpu_to_be64s __cpu_to_be64s
+#define be64_to_cpus __be64_to_cpus
+#define cpu_to_be32s __cpu_to_be32s
+#define be32_to_cpus __be32_to_cpus
+#define cpu_to_be16s __cpu_to_be16s
+#define be16_to_cpus __be16_to_cpus
+#endif
+
+
+/*
+ * Handle ntohl and suches. These have various compatibility
+ * issues - like we want to give the prototype even though we
+ * also have a macro for them in case some strange program
+ * wants to take the address of the thing or something..
+ *
+ * Note that these used to return a "long" in libc5, even though
+ * long is often 64-bit these days.. Thus the casts.
+ *
+ * They have to be macros in order to do the constant folding
+ * correctly - if the argument passed into a inline function
+ * it is no longer constant according to gcc..
+ */
+
+#undef ntohl
+#undef ntohs
+#undef htonl
+#undef htons
+
+/*
+ * Do the prototypes. Somebody might want to take the
+ * address or some such sick thing..
+ */
+#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2)
+extern __u32			ntohl(__u32);
+extern __u32			htonl(__u32);
+#else
+extern unsigned long int	ntohl(unsigned long int);
+extern unsigned long int	htonl(unsigned long int);
+#endif
+extern unsigned short int	ntohs(unsigned short int);
+extern unsigned short int	htons(unsigned short int);
+
+
+#if defined(__GNUC__) && (__GNUC__ >= 2)
+
+#define ___htonl(x) __cpu_to_be32(x)
+#define ___htons(x) __cpu_to_be16(x)
+#define ___ntohl(x) __be32_to_cpu(x)
+#define ___ntohs(x) __be16_to_cpu(x)
+
+#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2)
+#define htonl(x) ___htonl(x)
+#define ntohl(x) ___ntohl(x)
+#else
+#define htonl(x) ((unsigned long)___htonl(x))
+#define ntohl(x) ((unsigned long)___ntohl(x))
+#endif
+#define htons(x) ___htons(x)
+#define ntohs(x) ___ntohs(x)
+
+#endif /* OPTIMIZE */
+
+
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
diff --git a/include/linux/byteorder/little_endian.h b/include/linux/byteorder/little_endian.h
new file mode 100755
index 0000000..a46f3ec
--- /dev/null
+++ b/include/linux/byteorder/little_endian.h
@@ -0,0 +1,69 @@
+#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+
+#ifndef __LITTLE_ENDIAN
+#define __LITTLE_ENDIAN 1234
+#endif
+#ifndef __LITTLE_ENDIAN_BITFIELD
+#define __LITTLE_ENDIAN_BITFIELD
+#endif
+#define	__BYTE_ORDER	__LITTLE_ENDIAN
+
+#include <linux/byteorder/swab.h>
+
+#define __constant_htonl(x) ___constant_swab32((x))
+#define __constant_ntohl(x) ___constant_swab32((x))
+#define __constant_htons(x) ___constant_swab16((x))
+#define __constant_ntohs(x) ___constant_swab16((x))
+#define __constant_cpu_to_le64(x) ((__u64)(x))
+#define __constant_le64_to_cpu(x) ((__u64)(x))
+#define __constant_cpu_to_le32(x) ((__u32)(x))
+#define __constant_le32_to_cpu(x) ((__u32)(x))
+#define __constant_cpu_to_le16(x) ((__u16)(x))
+#define __constant_le16_to_cpu(x) ((__u16)(x))
+#define __constant_cpu_to_be64(x) ___constant_swab64((x))
+#define __constant_be64_to_cpu(x) ___constant_swab64((x))
+#define __constant_cpu_to_be32(x) ___constant_swab32((x))
+#define __constant_be32_to_cpu(x) ___constant_swab32((x))
+#define __constant_cpu_to_be16(x) ___constant_swab16((x))
+#define __constant_be16_to_cpu(x) ___constant_swab16((x))
+#define __cpu_to_le64(x) ((__u64)(x))
+#define __le64_to_cpu(x) ((__u64)(x))
+#define __cpu_to_le32(x) ((__u32)(x))
+#define __le32_to_cpu(x) ((__u32)(x))
+#define __cpu_to_le16(x) ((__u16)(x))
+#define __le16_to_cpu(x) ((__u16)(x))
+#define __cpu_to_be64(x) __swab64((x))
+#define __be64_to_cpu(x) __swab64((x))
+#define __cpu_to_be32(x) __swab32((x))
+#define __be32_to_cpu(x) __swab32((x))
+#define __cpu_to_be16(x) __swab16((x))
+#define __be16_to_cpu(x) __swab16((x))
+#define __cpu_to_le64p(x) (*(__u64*)(x))
+#define __le64_to_cpup(x) (*(__u64*)(x))
+#define __cpu_to_le32p(x) (*(__u32*)(x))
+#define __le32_to_cpup(x) (*(__u32*)(x))
+#define __cpu_to_le16p(x) (*(__u16*)(x))
+#define __le16_to_cpup(x) (*(__u16*)(x))
+#define __cpu_to_be64p(x) __swab64p((x))
+#define __be64_to_cpup(x) __swab64p((x))
+#define __cpu_to_be32p(x) __swab32p((x))
+#define __be32_to_cpup(x) __swab32p((x))
+#define __cpu_to_be16p(x) __swab16p((x))
+#define __be16_to_cpup(x) __swab16p((x))
+#define __cpu_to_le64s(x) do {} while (0)
+#define __le64_to_cpus(x) do {} while (0)
+#define __cpu_to_le32s(x) do {} while (0)
+#define __le32_to_cpus(x) do {} while (0)
+#define __cpu_to_le16s(x) do {} while (0)
+#define __le16_to_cpus(x) do {} while (0)
+#define __cpu_to_be64s(x) __swab64s((x))
+#define __be64_to_cpus(x) __swab64s((x))
+#define __cpu_to_be32s(x) __swab32s((x))
+#define __be32_to_cpus(x) __swab32s((x))
+#define __cpu_to_be16s(x) __swab16s((x))
+#define __be16_to_cpus(x) __swab16s((x))
+
+#include <linux/byteorder/generic.h>
+
+#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */
diff --git a/include/linux/byteorder/swab.h b/include/linux/byteorder/swab.h
new file mode 100755
index 0000000..b1d570e
--- /dev/null
+++ b/include/linux/byteorder/swab.h
@@ -0,0 +1,158 @@
+#ifndef _LINUX_BYTEORDER_SWAB_H
+#define _LINUX_BYTEORDER_SWAB_H
+
+/*
+ * linux/byteorder/swab.h
+ * Byte-swapping, independently from CPU endianness
+ *	swabXX[ps]?(foo)
+ *
+ * Francois-Rene Rideau <fare@tunes.org> 19971205
+ *    separated swab functions from cpu_to_XX,
+ *    to clean up support for bizarre-endian architectures.
+ *
+ * See asm-i386/byteorder.h and suches for examples of how to provide
+ * architecture-dependent optimized versions
+ *
+ */
+
+/* casts are necessary for constants, because we never know how for sure
+ * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way.
+ */
+#define ___swab16(x) \
+	((__u16)( \
+		(((__u16)(x) & (__u16)0x00ffU) << 8) | \
+		(((__u16)(x) & (__u16)0xff00U) >> 8) ))
+#define ___swab32(x) \
+	((__u32)( \
+		(((__u32)(x) & (__u32)0x000000ffUL) << 24) | \
+		(((__u32)(x) & (__u32)0x0000ff00UL) <<  8) | \
+		(((__u32)(x) & (__u32)0x00ff0000UL) >>  8) | \
+		(((__u32)(x) & (__u32)0xff000000UL) >> 24) ))
+#define ___swab64(x) \
+	((__u64)( \
+		(__u64)(((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \
+		(__u64)(((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \
+		(__u64)(((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \
+		(__u64)(((__u64)(x) & (__u64)0x00000000ff000000ULL) <<  8) | \
+		(__u64)(((__u64)(x) & (__u64)0x000000ff00000000ULL) >>  8) | \
+		(__u64)(((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \
+		(__u64)(((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \
+		(__u64)(((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56) ))
+
+/*
+ * provide defaults when no architecture-specific optimization is detected
+ */
+#ifndef __arch__swab16
+#  define __arch__swab16(x) ___swab16(x)
+#endif
+#ifndef __arch__swab32
+#  define __arch__swab32(x) ___swab32(x)
+#endif
+#ifndef __arch__swab64
+#  define __arch__swab64(x) ___swab64(x)
+#endif
+
+#ifndef __arch__swab16p
+#  define __arch__swab16p(x) __swab16(*(x))
+#endif
+#ifndef __arch__swab32p
+#  define __arch__swab32p(x) __swab32(*(x))
+#endif
+#ifndef __arch__swab64p
+#  define __arch__swab64p(x) __swab64(*(x))
+#endif
+
+#ifndef __arch__swab16s
+#  define __arch__swab16s(x) do { *(x) = __swab16p((x)); } while (0)
+#endif
+#ifndef __arch__swab32s
+#  define __arch__swab32s(x) do { *(x) = __swab32p((x)); } while (0)
+#endif
+#ifndef __arch__swab64s
+#  define __arch__swab64s(x) do { *(x) = __swab64p((x)); } while (0)
+#endif
+
+
+/*
+ * Allow constant folding
+ */
+#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__)
+#  define __swab16(x) \
+(__builtin_constant_p((__u16)(x)) ? \
+ ___swab16((x)) : \
+ __fswab16((x)))
+#  define __swab32(x) \
+(__builtin_constant_p((__u32)(x)) ? \
+ ___swab32((x)) : \
+ __fswab32((x)))
+#  define __swab64(x) \
+(__builtin_constant_p((__u64)(x)) ? \
+ ___swab64((x)) : \
+ __fswab64((x)))
+#else
+#  define __swab16(x) __fswab16(x)
+#  define __swab32(x) __fswab32(x)
+#  define __swab64(x) __fswab64(x)
+#endif /* OPTIMIZE */
+
+
+static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x)
+{
+	return __arch__swab16(x);
+}
+static __inline__ __u16 __swab16p(__u16 *x)
+{
+	return __arch__swab16p(x);
+}
+static __inline__ void __swab16s(__u16 *addr)
+{
+	__arch__swab16s(addr);
+}
+
+static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x)
+{
+	return __arch__swab32(x);
+}
+static __inline__ __u32 __swab32p(__u32 *x)
+{
+	return __arch__swab32p(x);
+}
+static __inline__ void __swab32s(__u32 *addr)
+{
+	__arch__swab32s(addr);
+}
+
+#ifdef __BYTEORDER_HAS_U64__
+static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x)
+{
+#  ifdef __SWAB_64_THRU_32__
+	__u32 h = x >> 32;
+	__u32 l = x & ((1ULL<<32)-1);
+	return (((__u64)__swab32(l)) << 32) | ((__u64)(__swab32(h)));
+#  else
+	return __arch__swab64(x);
+#  endif
+}
+static __inline__ __u64 __swab64p(__u64 *x)
+{
+	return __arch__swab64p(x);
+}
+static __inline__ void __swab64s(__u64 *addr)
+{
+	__arch__swab64s(addr);
+}
+#endif /* __BYTEORDER_HAS_U64__ */
+
+#if defined(__KERNEL__)
+#define swab16 __swab16
+#define swab32 __swab32
+#define swab64 __swab64
+#define swab16p __swab16p
+#define swab32p __swab32p
+#define swab64p __swab64p
+#define swab16s __swab16s
+#define swab32s __swab32s
+#define swab64s __swab64s
+#endif
+
+#endif /* _LINUX_BYTEORDER_SWAB_H */
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
new file mode 100755
index 0000000..73dcf80
--- /dev/null
+++ b/include/linux/compiler-gcc.h
@@ -0,0 +1,87 @@
+#ifndef __LINUX_COMPILER_H
+#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead."
+#endif
+
+/*
+ * Common definitions for all gcc versions go here.
+ */
+
+
+/* Optimization barrier */
+/* The "volatile" is due to gcc bugs */
+#define barrier() __asm__ __volatile__("": : :"memory")
+
+/*
+ * This macro obfuscates arithmetic on a variable address so that gcc
+ * shouldn't recognize the original var, and make assumptions about it.
+ *
+ * This is needed because the C standard makes it undefined to do
+ * pointer arithmetic on "objects" outside their boundaries and the
+ * gcc optimizers assume this is the case. In particular they
+ * assume such arithmetic does not wrap.
+ *
+ * A miscompilation has been observed because of this on PPC.
+ * To work around it we hide the relationship of the pointer and the object
+ * using this macro.
+ *
+ * Versions of the ppc64 compiler before 4.1 had a bug where use of
+ * RELOC_HIDE could trash r30. The bug can be worked around by changing
+ * the inline assembly constraint from =g to =r, in this particular
+ * case either is valid.
+ */
+#define RELOC_HIDE(ptr, off)					\
+  ({ unsigned long __ptr;					\
+    __asm__ ("" : "=r"(__ptr) : "0"(ptr));		\
+    (typeof(ptr)) (__ptr + (off)); })
+
+/* &a[0] degrades to a pointer: a different type from an array */
+#define __must_be_array(a) \
+  BUILD_BUG_ON_ZERO(__builtin_types_compatible_p(typeof(a), typeof(&a[0])))
+
+/*
+ * Force always-inline if the user requests it so via the .config,
+ * or if gcc is too old:
+ */
+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \
+    !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
+# define inline		inline		__attribute__((always_inline))
+# define __inline__	__inline__	__attribute__((always_inline))
+# define __inline	__inline	__attribute__((always_inline))
+#endif
+
+#define __deprecated			__attribute__((deprecated))
+#define __packed			__attribute__((packed))
+#define __weak				__attribute__((weak))
+
+/*
+ * it doesn't make sense on ARM (currently the only user of __naked) to trace
+ * naked functions because then mcount is called without stack and frame pointer
+ * being set up and there is no chance to restore the lr register to the value
+ * before mcount was called.
+ */
+#define __naked				__attribute__((naked)) notrace
+
+#define __noreturn			__attribute__((noreturn))
+
+/*
+ * From the GCC manual:
+ *
+ * Many functions have no effects except the return value and their
+ * return value depends only on the parameters and/or global
+ * variables.  Such a function can be subject to common subexpression
+ * elimination and loop optimization just as an arithmetic operator
+ * would be.
+ * [...]
+ */
+#define __pure				__attribute__((pure))
+#define __aligned(x)			__attribute__((aligned(x)))
+#define __printf(a,b)			__attribute__((format(printf,a,b)))
+#define  noinline			__attribute__((noinline))
+#define __attribute_const__		__attribute__((__const__))
+#define __maybe_unused			__attribute__((unused))
+#define __always_unused			__attribute__((unused))
+
+#define __gcc_header(x) #x
+#define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h)
+#define gcc_header(x) _gcc_header(x)
+#include gcc_header(__GNUC__)
diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h
new file mode 100755
index 0000000..94dea3f
--- /dev/null
+++ b/include/linux/compiler-gcc4.h
@@ -0,0 +1,61 @@
+#ifndef __LINUX_COMPILER_H
+#error "Please don't include <linux/compiler-gcc4.h> directly, include <linux/compiler.h> instead."
+#endif
+
+/* GCC 4.1.[01] miscompiles __weak */
+#ifdef __KERNEL__
+# if __GNUC_MINOR__ == 1 && __GNUC_PATCHLEVEL__ <= 1
+#  error Your version of gcc miscompiles the __weak directive
+# endif
+#endif
+
+#define __used			__attribute__((__used__))
+#define __must_check 		__attribute__((warn_unused_result))
+#define __compiler_offsetof(a,b) __builtin_offsetof(a,b)
+#define __always_inline		inline __attribute__((always_inline))
+
+/*
+ * A trick to suppress uninitialized variable warning without generating any
+ * code
+ */
+#define uninitialized_var(x) x = x
+
+#if __GNUC_MINOR__ >= 3
+/* Mark functions as cold. gcc will assume any path leading to a call
+   to them will be unlikely.  This means a lot of manual unlikely()s
+   are unnecessary now for any paths leading to the usual suspects
+   like BUG(), printk(), panic() etc. [but let's keep them for now for
+   older compilers]
+
+   Early snapshots of gcc 4.3 don't support this and we can't detect this
+   in the preprocessor, but we can live with this because they're unreleased.
+   Maketime probing would be overkill here.
+
+   gcc also has a __attribute__((__hot__)) to move hot functions into
+   a special section, but I don't see any sense in this right now in
+   the kernel context */
+#define __cold			__attribute__((__cold__))
+
+
+#if __GNUC_MINOR__ >= 5
+/*
+ * Mark a position in code as unreachable.  This can be used to
+ * suppress control flow warnings after asm blocks that transfer
+ * control elsewhere.
+ *
+ * Early snapshots of gcc 4.5 don't support this and we can't detect
+ * this in the preprocessor, but we can live with this because they're
+ * unreleased.  Really, we need to have autoconf for the kernel.
+ */
+#define unreachable() __builtin_unreachable()
+#endif
+
+#endif
+
+#if __GNUC_MINOR__ > 0
+#define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
+#endif
+#if __GNUC_MINOR__ >= 4
+#define __compiletime_warning(message) __attribute__((warning(message)))
+#define __compiletime_error(message) __attribute__((error(message)))
+#endif
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
new file mode 100755
index 0000000..5be3dab
--- /dev/null
+++ b/include/linux/compiler.h
@@ -0,0 +1,303 @@
+#ifndef __LINUX_COMPILER_H
+#define __LINUX_COMPILER_H
+
+#ifndef __ASSEMBLY__
+
+#ifdef __CHECKER__
+# define __user		__attribute__((noderef, address_space(1)))
+# define __kernel	/* default address space */
+# define __safe		__attribute__((safe))
+# define __force	__attribute__((force))
+# define __nocast	__attribute__((nocast))
+# define __iomem	__attribute__((noderef, address_space(2)))
+# define __acquires(x)	__attribute__((context(x,0,1)))
+# define __releases(x)	__attribute__((context(x,1,0)))
+# define __acquire(x)	__context__(x,1)
+# define __release(x)	__context__(x,-1)
+# define __cond_lock(x,c)	((c) ? ({ __acquire(x); 1; }) : 0)
+extern void __chk_user_ptr(const volatile void __user *);
+extern void __chk_io_ptr(const volatile void __iomem *);
+#else
+# define __user
+# define __kernel
+# define __safe
+# define __force
+# define __nocast
+# define __iomem
+# define __chk_user_ptr(x) (void)0
+# define __chk_io_ptr(x) (void)0
+# define __builtin_warning(x, y...) (1)
+# define __acquires(x)
+# define __releases(x)
+# define __acquire(x) (void)0
+# define __release(x) (void)0
+# define __cond_lock(x,c) (c)
+#endif
+
+#ifdef __KERNEL__
+
+#ifdef __GNUC__
+#include <linux/compiler-gcc.h>
+#endif
+
+#define notrace __attribute__((no_instrument_function))
+
+/* Intel compiler defines __GNUC__. So we will overwrite implementations
+ * coming from above header files here
+ */
+#ifdef __INTEL_COMPILER
+# include <linux/compiler-intel.h>
+#endif
+
+/*
+ * Generic compiler-dependent macros required for kernel
+ * build go below this comment. Actual compiler/compiler version
+ * specific implementations come from the above header files
+ */
+
+struct ftrace_branch_data {
+	const char *func;
+	const char *file;
+	unsigned line;
+	union {
+		struct {
+			unsigned long correct;
+			unsigned long incorrect;
+		};
+		struct {
+			unsigned long miss;
+			unsigned long hit;
+		};
+		unsigned long miss_hit[2];
+	};
+};
+
+/*
+ * Note: DISABLE_BRANCH_PROFILING can be used by special lowlevel code
+ * to disable branch tracing on a per file basis.
+ */
+#if defined(CONFIG_TRACE_BRANCH_PROFILING) \
+    && !defined(DISABLE_BRANCH_PROFILING) && !defined(__CHECKER__)
+void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
+
+#define likely_notrace(x)	__builtin_expect(!!(x), 1)
+#define unlikely_notrace(x)	__builtin_expect(!!(x), 0)
+
+#define __branch_check__(x, expect) ({					\
+			int ______r;					\
+			static struct ftrace_branch_data		\
+				__attribute__((__aligned__(4)))		\
+				__attribute__((section("_ftrace_annotated_branch"))) \
+				______f = {				\
+				.func = __func__,			\
+				.file = __FILE__,			\
+				.line = __LINE__,			\
+			};						\
+			______r = likely_notrace(x);			\
+			ftrace_likely_update(&______f, ______r, expect); \
+			______r;					\
+		})
+
+/*
+ * Using __builtin_constant_p(x) to ignore cases where the return
+ * value is always the same.  This idea is taken from a similar patch
+ * written by Daniel Walker.
+ */
+# ifndef likely
+#  define likely(x)	(__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 1))
+# endif
+# ifndef unlikely
+#  define unlikely(x)	(__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 0))
+# endif
+
+#ifdef CONFIG_PROFILE_ALL_BRANCHES
+/*
+ * "Define 'is'", Bill Clinton
+ * "Define 'if'", Steven Rostedt
+ */
+#define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) )
+#define __trace_if(cond) \
+	if (__builtin_constant_p((cond)) ? !!(cond) :			\
+	({								\
+		int ______r;						\
+		static struct ftrace_branch_data			\
+			__attribute__((__aligned__(4)))			\
+			__attribute__((section("_ftrace_branch")))	\
+			______f = {					\
+				.func = __func__,			\
+				.file = __FILE__,			\
+				.line = __LINE__,			\
+			};						\
+		______r = !!(cond);					\
+		______f.miss_hit[______r]++;					\
+		______r;						\
+	}))
+#endif /* CONFIG_PROFILE_ALL_BRANCHES */
+
+#else
+# define likely(x)	__builtin_expect(!!(x), 1)
+# define unlikely(x)	__builtin_expect(!!(x), 0)
+#endif
+
+/* Optimization barrier */
+#ifndef barrier
+# define barrier() __memory_barrier()
+#endif
+
+/* Unreachable code */
+#ifndef unreachable
+# define unreachable() do { } while (1)
+#endif
+
+#ifndef RELOC_HIDE
+# define RELOC_HIDE(ptr, off)					\
+  ({ unsigned long __ptr;					\
+     __ptr = (unsigned long) (ptr);				\
+    (typeof(ptr)) (__ptr + (off)); })
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+/*
+ * Allow us to mark functions as 'deprecated' and have gcc emit a nice
+ * warning for each use, in hopes of speeding the functions removal.
+ * Usage is:
+ * 		int __deprecated foo(void)
+ */
+#ifndef __deprecated
+# define __deprecated		/* unimplemented */
+#endif
+
+#ifdef MODULE
+#define __deprecated_for_modules __deprecated
+#else
+#define __deprecated_for_modules
+#endif
+
+#ifndef __must_check
+#define __must_check
+#endif
+
+#ifndef CONFIG_ENABLE_MUST_CHECK
+#undef __must_check
+#define __must_check
+#endif
+#ifndef CONFIG_ENABLE_WARN_DEPRECATED
+#undef __deprecated
+#undef __deprecated_for_modules
+#define __deprecated
+#define __deprecated_for_modules
+#endif
+
+/*
+ * Allow us to avoid 'defined but not used' warnings on functions and data,
+ * as well as force them to be emitted to the assembly file.
+ *
+ * As of gcc 3.4, static functions that are not marked with attribute((used))
+ * may be elided from the assembly file.  As of gcc 3.4, static data not so
+ * marked will not be elided, but this may change in a future gcc version.
+ *
+ * NOTE: Because distributions shipped with a backported unit-at-a-time
+ * compiler in gcc 3.3, we must define __used to be __attribute__((used))
+ * for gcc >=3.3 instead of 3.4.
+ *
+ * In prior versions of gcc, such functions and data would be emitted, but
+ * would be warned about except with attribute((unused)).
+ *
+ * Mark functions that are referenced only in inline assembly as __used so
+ * the code is emitted even though it appears to be unreferenced.
+ */
+#ifndef __used
+# define __used			/* unimplemented */
+#endif
+
+#ifndef __maybe_unused
+# define __maybe_unused		/* unimplemented */
+#endif
+
+#ifndef __always_unused
+# define __always_unused	/* unimplemented */
+#endif
+
+#ifndef noinline
+#define noinline
+#endif
+
+/*
+ * Rather then using noinline to prevent stack consumption, use
+ * noinline_for_stack instead.  For documentaiton reasons.
+ */
+#define noinline_for_stack noinline
+
+#ifndef __always_inline
+#define __always_inline inline
+#endif
+
+#endif /* __KERNEL__ */
+
+/*
+ * From the GCC manual:
+ *
+ * Many functions do not examine any values except their arguments,
+ * and have no effects except the return value.  Basically this is
+ * just slightly more strict class than the `pure' attribute above,
+ * since function is not allowed to read global memory.
+ *
+ * Note that a function that has pointer arguments and examines the
+ * data pointed to must _not_ be declared `const'.  Likewise, a
+ * function that calls a non-`const' function usually must not be
+ * `const'.  It does not make sense for a `const' function to return
+ * `void'.
+ */
+#ifndef __attribute_const__
+# define __attribute_const__	/* unimplemented */
+#endif
+
+/*
+ * Tell gcc if a function is cold. The compiler will assume any path
+ * directly leading to the call is unlikely.
+ */
+
+#ifndef __cold
+#define __cold
+#endif
+
+/* Simple shorthand for a section definition */
+#ifndef __section
+# define __section(S) __attribute__ ((__section__(#S)))
+#endif
+
+/* Are two types/vars the same type (ignoring qualifiers)? */
+#ifndef __same_type
+# define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
+#endif
+
+/* Compile time object size, -1 for unknown */
+#ifndef __compiletime_object_size
+# define __compiletime_object_size(obj) -1
+#endif
+#ifndef __compiletime_warning
+# define __compiletime_warning(message)
+#endif
+#ifndef __compiletime_error
+# define __compiletime_error(message)
+#endif
+
+/*
+ * Prevent the compiler from merging or refetching accesses.  The compiler
+ * is also forbidden from reordering successive instances of ACCESS_ONCE(),
+ * but only when the compiler is aware of some particular ordering.  One way
+ * to make the compiler aware of ordering is to put the two invocations of
+ * ACCESS_ONCE() in different C statements.
+ *
+ * This macro does absolutely -nothing- to prevent the CPU from reordering,
+ * merging, or refetching absolutely anything at any time.  Its main intended
+ * use is to mediate communication between process-level code and irq/NMI
+ * handlers, all running on the same CPU.
+ */
+#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
+
+#endif /* __LINUX_COMPILER_H */
diff --git a/include/linux/config.h b/include/linux/config.h
new file mode 100755
index 0000000..a0194cb
--- /dev/null
+++ b/include/linux/config.h
@@ -0,0 +1,6 @@
+#ifndef _LINUX_CONFIG_H
+#define _LINUX_CONFIG_H
+
+/* #include <linux/autoconf.h> */
+
+#endif
diff --git a/include/linux/crc32.h b/include/linux/crc32.h
new file mode 100755
index 0000000..ac4aed1
--- /dev/null
+++ b/include/linux/crc32.h
@@ -0,0 +1,27 @@
+/*
+ * crc32.h
+ * See linux/lib/crc32.c for license and changes
+ */
+#ifndef _LINUX_CRC32_H
+#define _LINUX_CRC32_H
+
+#include <linux/types.h>
+/* #include <linux/bitrev.h> */
+
+extern u32  crc32_le(u32 crc, unsigned char const *p, size_t len);
+/* extern u32  crc32_be(u32 crc, unsigned char const *p, size_t len); */
+
+#define crc32(seed, data, length)  crc32_le(seed, (unsigned char const *)data, length)
+
+/*
+ * Helpers for hash table generation of ethernet nics:
+ *
+ * Ethernet sends the least significant bit of a byte first, thus crc32_le
+ * is used. The output of crc32_le is bit reversed [most significant bit
+ * is in bit nr 0], thus it must be reversed before use. Except for
+ * nics that bit swap the result internally...
+ */
+/* #define ether_crc(length, data)    bitrev32(crc32_le(~0, data, length)) */
+/* #define ether_crc_le(length, data) crc32_le(~0, data, length) */
+
+#endif /* _LINUX_CRC32_H */
diff --git a/include/linux/ctype.h b/include/linux/ctype.h
new file mode 100755
index 0000000..43701ea
--- /dev/null
+++ b/include/linux/ctype.h
@@ -0,0 +1,67 @@
+#ifndef _LINUX_CTYPE_H
+#define _LINUX_CTYPE_H
+
+/*
+ * NOTE! This ctype does not handle EOF like the standard C
+ * library is required to.
+ */
+
+#define _U	0x01	/* upper */
+#define _L	0x02	/* lower */
+#define _D	0x04	/* digit */
+#define _C	0x08	/* cntrl */
+#define _P	0x10	/* punct */
+#define _S	0x20	/* white space (space/lf/tab) */
+#define _X	0x40	/* hex digit */
+#define _SP	0x80	/* hard space (0x20) */
+
+extern unsigned char _ctype[];
+
+#define __ismask(x) (_ctype[(int)(unsigned char)(x)])
+
+#define isalnum(c)	((__ismask(c)&(_U|_L|_D)) != 0)
+#define isalpha(c)	((__ismask(c)&(_U|_L)) != 0)
+#define iscntrl(c)	((__ismask(c)&(_C)) != 0)
+#define isdigit(c)	((__ismask(c)&(_D)) != 0)
+#define isgraph(c)	((__ismask(c)&(_P|_U|_L|_D)) != 0)
+#define islower(c)	((__ismask(c)&(_L)) != 0)
+#define isprint(c)	((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0)
+#define ispunct(c)	((__ismask(c)&(_P)) != 0)
+#define isspace(c)	((__ismask(c)&(_S)) != 0)
+#define isupper(c)	((__ismask(c)&(_U)) != 0)
+#define isxdigit(c)	((__ismask(c)&(_D|_X)) != 0)
+
+
+/*======rockpzhang======*/
+/*
+ * Rather than doubling the size of the _ctype lookup table to hold a 'blank'
+ * flag, just check for space or tab.
+ */
+#define isblank(c)	(c == ' ' || c == '\t')
+/*============*/
+
+
+
+
+
+#define isascii(c) (((unsigned char)(c))<=0x7f)
+#define toascii(c) (((unsigned char)(c))&0x7f)
+
+static inline unsigned char __tolower(unsigned char c)
+{
+	if (isupper(c))
+		c -= 'A'-'a';
+	return c;
+}
+
+static inline unsigned char __toupper(unsigned char c)
+{
+	if (islower(c))
+		c -= 'a'-'A';
+	return c;
+}
+
+#define tolower(c) __tolower(c)
+#define toupper(c) __toupper(c)
+
+#endif
diff --git a/include/linux/list.h b/include/linux/list.h
new file mode 100755
index 0000000..42b3c62
--- /dev/null
+++ b/include/linux/list.h
@@ -0,0 +1,421 @@
+#ifndef _LINUX_LIST_H
+#define _LINUX_LIST_H
+
+#ifndef ARCH_HAS_PREFETCH
+#define ARCH_HAS_PREFETCH
+static inline void prefetch(const void *x) {;}
+#endif
+
+/*
+ * Simple doubly linked list implementation.
+ *
+ * Some of the internal functions ("__xxx") are useful when
+ * manipulating whole lists rather than single entries, as
+ * sometimes we already know the next/prev entries and we can
+ * generate better code by using them directly rather than
+ * using the generic single-entry routines.
+ */
+
+struct list_head {
+	struct list_head *next, *prev;
+};
+
+#define LIST_HEAD_INIT(name) { &(name), &(name) }
+
+#define LIST_HEAD(name) \
+	struct list_head name = LIST_HEAD_INIT(name)
+
+#define INIT_LIST_HEAD(ptr) do { \
+	(ptr)->next = (ptr); (ptr)->prev = (ptr); \
+} while (0)
+
+/*
+ * Insert a new entry between two known consecutive entries.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+static inline void __list_add(struct list_head *new,
+			      struct list_head *prev,
+			      struct list_head *next)
+{
+	next->prev = new;
+	new->next = next;
+	new->prev = prev;
+	prev->next = new;
+}
+
+/**
+ * list_add - add a new entry
+ * @new: new entry to be added
+ * @head: list head to add it after
+ *
+ * Insert a new entry after the specified head.
+ * This is good for implementing stacks.
+ */
+static inline void list_add(struct list_head *new, struct list_head *head)
+{
+	__list_add(new, head, head->next);
+}
+
+/**
+ * list_add_tail - add a new entry
+ * @new: new entry to be added
+ * @head: list head to add it before
+ *
+ * Insert a new entry before the specified head.
+ * This is useful for implementing queues.
+ */
+static inline void list_add_tail(struct list_head *new, struct list_head *head)
+{
+	__list_add(new, head->prev, head);
+}
+
+/*
+ * Delete a list entry by making the prev/next entries
+ * point to each other.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+static inline void __list_del(struct list_head *prev, struct list_head *next)
+{
+	next->prev = prev;
+	prev->next = next;
+}
+
+/**
+ * list_del - deletes entry from list.
+ * @entry: the element to delete from the list.
+ * Note: list_empty on entry does not return true after this, the entry is in an undefined state.
+ */
+static inline void list_del(struct list_head *entry)
+{
+	__list_del(entry->prev, entry->next);
+	entry->next = (void *) 0;
+	entry->prev = (void *) 0;
+}
+
+/**
+ * list_replace - replace old entry by new one
+ * @old : the element to be replaced
+ * @new : the new element to insert
+ *
+ * If @old was empty, it will be overwritten.
+ */
+static inline void list_replace(struct list_head *old,
+                                struct list_head *new)
+{
+        new->next = old->next;
+        new->next->prev = new;
+        new->prev = old->prev;
+        new->prev->next = new;
+}
+/**
+ * list_del_init - deletes entry from list and reinitialize it.
+ * @entry: the element to delete from the list.
+ */
+static inline void list_del_init(struct list_head *entry)
+{
+	__list_del(entry->prev, entry->next);
+	INIT_LIST_HEAD(entry);
+}
+
+/**
+ * list_move - delete from one list and add as another's head
+ * @list: the entry to move
+ * @head: the head that will precede our entry
+ */
+static inline void list_move(struct list_head *list, struct list_head *head)
+{
+	__list_del(list->prev, list->next);
+	list_add(list, head);
+}
+
+/**
+ * list_move_tail - delete from one list and add as another's tail
+ * @list: the entry to move
+ * @head: the head that will follow our entry
+ */
+static inline void list_move_tail(struct list_head *list,
+				  struct list_head *head)
+{
+	__list_del(list->prev, list->next);
+	list_add_tail(list, head);
+}
+
+/**
+ * list_empty - tests whether a list is empty
+ * @head: the list to test.
+ */
+static inline int list_empty(struct list_head *head)
+{
+	return head->next == head;
+}
+
+static inline void __list_splice(struct list_head *list,
+				 struct list_head *head)
+{
+	struct list_head *first = list->next;
+	struct list_head *last = list->prev;
+	struct list_head *at = head->next;
+
+	first->prev = head;
+	head->next = first;
+
+	last->next = at;
+	at->prev = last;
+}
+
+/**
+ * list_splice - join two lists
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ */
+static inline void list_splice(struct list_head *list, struct list_head *head)
+{
+	if (!list_empty(list))
+		__list_splice(list, head);
+}
+
+/**
+ * list_splice_init - join two lists and reinitialise the emptied list.
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ *
+ * The list at @list is reinitialised
+ */
+static inline void list_splice_init(struct list_head *list,
+				    struct list_head *head)
+{
+	if (!list_empty(list)) {
+		__list_splice(list, head);
+		INIT_LIST_HEAD(list);
+	}
+}
+
+/**
+ * list_entry - get the struct for this entry
+ * @ptr:	the &struct list_head pointer.
+ * @type:	the type of the struct this is embedded in.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_entry(ptr, type, member) \
+	((type *)((char *)(ptr)-(unsigned long)(&((type *)0)->member)))
+
+/**
+ * list_for_each	-	iterate over a list
+ * @pos:	the &struct list_head to use as a loop counter.
+ * @head:	the head for your list.
+ */
+#define list_for_each(pos, head) \
+	for (pos = (head)->next, prefetch(pos->next); pos != (head); \
+		pos = pos->next, prefetch(pos->next))
+/**
+ * list_for_each_prev	-	iterate over a list backwards
+ * @pos:	the &struct list_head to use as a loop counter.
+ * @head:	the head for your list.
+ */
+#define list_for_each_prev(pos, head) \
+	for (pos = (head)->prev, prefetch(pos->prev); pos != (head); \
+		pos = pos->prev, prefetch(pos->prev))
+
+/**
+ * list_for_each_safe	-	iterate over a list safe against removal of list entry
+ * @pos:	the &struct list_head to use as a loop counter.
+ * @n:		another &struct list_head to use as temporary storage
+ * @head:	the head for your list.
+ */
+#define list_for_each_safe(pos, n, head) \
+	for (pos = (head)->next, n = pos->next; pos != (head); \
+		pos = n, n = pos->next)
+
+/**
+ * list_for_each_entry	-	iterate over list of given type
+ * @pos:	the type * to use as a loop counter.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_for_each_entry(pos, head, member)				\
+	for (pos = list_entry((head)->next, typeof(*pos), member),	\
+		     prefetch(pos->member.next);			\
+	     &pos->member != (head);					\
+	     pos = list_entry(pos->member.next, typeof(*pos), member),	\
+		     prefetch(pos->member.next))
+
+/**
+ * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry
+ * @pos:	the type * to use as a loop counter.
+ * @n:		another type * to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_for_each_entry_safe(pos, n, head, member)			\
+	for (pos = list_entry((head)->next, typeof(*pos), member),	\
+		n = list_entry(pos->member.next, typeof(*pos), member); \
+	     &pos->member != (head);					\
+	     pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
+ * list_for_each_entry_continue -	iterate over list of given type
+ *			continuing after existing point
+ * @pos:	the type * to use as a loop counter.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_for_each_entry_continue(pos, head, member)			\
+	for (pos = list_entry(pos->member.next, typeof(*pos), member),	\
+		     prefetch(pos->member.next);			\
+	     &pos->member != (head);					\
+	     pos = list_entry(pos->member.next, typeof(*pos), member),	\
+		     prefetch(pos->member.next))
+
+/*
+ * Double linked lists with a single pointer list head.
+ * Mostly useful for hash tables where the two pointer list head is
+ * too wasteful.
+ * You lose the ability to access the tail in O(1).
+ */
+
+struct hlist_head {
+	struct hlist_node *first;
+};
+
+struct hlist_node {
+	struct hlist_node *next, **pprev;
+};
+
+#define HLIST_HEAD_INIT { .first = NULL }
+#define HLIST_HEAD(name) struct hlist_head name = {  .first = NULL }
+#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL)
+static inline void INIT_HLIST_NODE(struct hlist_node *h)
+{
+	h->next = NULL;
+	h->pprev = NULL;
+}
+
+static inline int hlist_unhashed(const struct hlist_node *h)
+{
+	return !h->pprev;
+}
+
+static inline int hlist_empty(const struct hlist_head *h)
+{
+	return !h->first;
+}
+
+static inline void __hlist_del(struct hlist_node *n)
+{
+	struct hlist_node *next = n->next;
+	struct hlist_node **pprev = n->pprev;
+	*pprev = next;
+	if (next)
+		next->pprev = pprev;
+}
+
+static inline void hlist_del(struct hlist_node *n)
+{
+	__hlist_del(n);
+	n->next = 0;
+	n->pprev = 0;
+}
+
+static inline void hlist_del_init(struct hlist_node *n)
+{
+	if (!hlist_unhashed(n)) {
+		__hlist_del(n);
+		INIT_HLIST_NODE(n);
+	}
+}
+
+static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h)
+{
+	struct hlist_node *first = h->first;
+	n->next = first;
+	if (first)
+		first->pprev = &n->next;
+	h->first = n;
+	n->pprev = &h->first;
+}
+
+/* next must be != NULL */
+static inline void hlist_add_before(struct hlist_node *n,
+					struct hlist_node *next)
+{
+	n->pprev = next->pprev;
+	n->next = next;
+	next->pprev = &n->next;
+	*(n->pprev) = n;
+}
+
+static inline void hlist_add_after(struct hlist_node *n,
+					struct hlist_node *next)
+{
+	next->next = n->next;
+	n->next = next;
+	next->pprev = &n->next;
+
+	if(next->next)
+		next->next->pprev  = &next->next;
+}
+
+#define hlist_entry(ptr, type, member) container_of(ptr,type,member)
+
+#define hlist_for_each(pos, head) \
+	for (pos = (head)->first; pos && ({ prefetch(pos->next); 1; }); \
+	     pos = pos->next)
+
+#define hlist_for_each_safe(pos, n, head) \
+	for (pos = (head)->first; pos && ({ n = pos->next; 1; }); \
+	     pos = n)
+
+/**
+ * hlist_for_each_entry	- iterate over list of given type
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_node to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the hlist_node within the struct.
+ */
+#define hlist_for_each_entry(tpos, pos, head, member)			 \
+	for (pos = (head)->first;					 \
+	     pos && ({ prefetch(pos->next); 1;}) &&			 \
+		({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
+	     pos = pos->next)
+
+/**
+ * hlist_for_each_entry_continue - iterate over a hlist continuing after current point
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_node to use as a loop cursor.
+ * @member:	the name of the hlist_node within the struct.
+ */
+#define hlist_for_each_entry_continue(tpos, pos, member)		 \
+	for (pos = (pos)->next;						 \
+	     pos && ({ prefetch(pos->next); 1;}) &&			 \
+		({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
+	     pos = pos->next)
+
+/**
+ * hlist_for_each_entry_from - iterate over a hlist continuing from current point
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_node to use as a loop cursor.
+ * @member:	the name of the hlist_node within the struct.
+ */
+#define hlist_for_each_entry_from(tpos, pos, member)			 \
+	for (; pos && ({ prefetch(pos->next); 1;}) &&			 \
+		({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
+	     pos = pos->next)
+
+/**
+ * hlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_node to use as a loop cursor.
+ * @n:		another &struct hlist_node to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the hlist_node within the struct.
+ */
+#define hlist_for_each_entry_safe(tpos, pos, n, head, member)		 \
+	for (pos = (head)->first;					 \
+	     pos && ({ n = pos->next; 1; }) &&				 \
+		({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
+	     pos = n)
+#endif
diff --git a/include/linux/lzo.h b/include/linux/lzo.h
new file mode 100755
index 0000000..88687fa
--- /dev/null
+++ b/include/linux/lzo.h
@@ -0,0 +1,48 @@
+#ifndef __LZO_H__
+#define __LZO_H__
+/*
+ *  LZO Public Kernel Interface
+ *  A mini subset of the LZO real-time data compression library
+ *
+ *  Copyright (C) 1996-2005 Markus F.X.J. Oberhumer <markus@oberhumer.com>
+ *
+ *  The full LZO package can be found at:
+ *  http://www.oberhumer.com/opensource/lzo/
+ *
+ *  Changed for kernel use by:
+ *  Nitin Gupta <nitingupta910@gmail.com>
+ *  Richard Purdie <rpurdie@openedhand.com>
+ */
+
+#define LZO1X_MEM_COMPRESS	(16384 * sizeof(unsigned char *))
+#define LZO1X_1_MEM_COMPRESS	LZO1X_MEM_COMPRESS
+
+#define lzo1x_worst_compress(x) ((x) + ((x) / 16) + 64 + 3)
+
+/* This requires 'workmem' of size LZO1X_1_MEM_COMPRESS */
+int lzo1x_1_compress(const unsigned char *src, size_t src_len,
+			unsigned char *dst, size_t *dst_len, void *wrkmem);
+
+/* safe decompression with overrun testing */
+int lzo1x_decompress_safe(const unsigned char *src, size_t src_len,
+			unsigned char *dst, size_t *dst_len);
+
+/* decompress lzop format */
+int lzop_decompress(const unsigned char *src, size_t src_len,
+		    unsigned char *dst, size_t *dst_len);
+
+/*
+ * Return values (< 0 = Error)
+ */
+#define LZO_E_OK			0
+#define LZO_E_ERROR			(-1)
+#define LZO_E_OUT_OF_MEMORY		(-2)
+#define LZO_E_NOT_COMPRESSIBLE		(-3)
+#define LZO_E_INPUT_OVERRUN		(-4)
+#define LZO_E_OUTPUT_OVERRUN		(-5)
+#define LZO_E_LOOKBEHIND_OVERRUN	(-6)
+#define LZO_E_EOF_NOT_FOUND		(-7)
+#define LZO_E_INPUT_NOT_CONSUMED	(-8)
+#define LZO_E_NOT_YET_IMPLEMENTED	(-9)
+
+#endif
diff --git a/include/linux/math64.h b/include/linux/math64.h
new file mode 100755
index 0000000..6d760d7
--- /dev/null
+++ b/include/linux/math64.h
@@ -0,0 +1,85 @@
+#ifndef _LINUX_MATH64_H
+#define _LINUX_MATH64_H
+
+#include <linux/types.h>
+
+#if BITS_PER_LONG == 64
+
+/**
+ * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
+ *
+ * This is commonly provided by 32bit archs to provide an optimized 64bit
+ * divide.
+ */
+static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
+{
+	*remainder = dividend % divisor;
+	return dividend / divisor;
+}
+
+/**
+ * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
+ */
+static inline s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder)
+{
+	*remainder = dividend % divisor;
+	return dividend / divisor;
+}
+
+/**
+ * div64_u64 - unsigned 64bit divide with 64bit divisor
+ */
+static inline u64 div64_u64(u64 dividend, u64 divisor)
+{
+	return dividend / divisor;
+}
+
+#elif BITS_PER_LONG == 32
+
+#ifndef div_u64_rem
+static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
+{
+	*remainder = do_div(dividend, divisor);
+	return dividend;
+}
+#endif
+
+#ifndef div_s64_rem
+extern s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder);
+#endif
+
+#ifndef div64_u64
+extern u64 div64_u64(u64 dividend, u64 divisor);
+#endif
+
+#endif /* BITS_PER_LONG */
+
+/**
+ * div_u64 - unsigned 64bit divide with 32bit divisor
+ *
+ * This is the most common 64bit divide and should be used if possible,
+ * as many 32bit archs can optimize this variant better than a full 64bit
+ * divide.
+ */
+#ifndef div_u64
+static inline u64 div_u64(u64 dividend, u32 divisor)
+{
+	u32 remainder;
+	return div_u64_rem(dividend, divisor, &remainder);
+}
+#endif
+
+/**
+ * div_s64 - signed 64bit divide with 32bit divisor
+ */
+#ifndef div_s64
+static inline s64 div_s64(s64 dividend, s32 divisor)
+{
+	s32 remainder;
+	return div_s64_rem(dividend, divisor, &remainder);
+}
+#endif
+
+u32 iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder);
+
+#endif /* _LINUX_MATH64_H */
diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h
new file mode 100755
index 0000000..227feeb
--- /dev/null
+++ b/include/linux/mc146818rtc.h
@@ -0,0 +1,98 @@
+/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
+ * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
+ * derived from Data Sheet, Copyright Motorola 1984 (!).
+ * It was written to be part of the Linux operating system.
+ */
+/* permission is hereby granted to copy, modify and redistribute this code
+ * in terms of the GNU Library General Public License, Version 2 or later,
+ * at your option.
+ */
+
+#ifndef _MC146818RTC_H
+#define _MC146818RTC_H
+
+#include <asm/io.h>
+#include <linux/rtc.h>          /* get the user-level API */
+#include <asm/mc146818rtc.h>        /* register access macros */
+
+/**********************************************************************
+ * register summary
+ **********************************************************************/
+#define RTC_SECONDS     0
+#define RTC_SECONDS_ALARM   1
+#define RTC_MINUTES     2
+#define RTC_MINUTES_ALARM   3
+#define RTC_HOURS       4
+#define RTC_HOURS_ALARM     5
+/* RTC_*_alarm is always true if 2 MSBs are set */
+# define RTC_ALARM_DONT_CARE    0xC0
+
+#define RTC_DAY_OF_WEEK     6
+#define RTC_DAY_OF_MONTH    7
+#define RTC_MONTH       8
+#define RTC_YEAR        9
+
+/* control registers - Moto names
+ */
+#define RTC_REG_A       10
+#define RTC_REG_B       11
+#define RTC_REG_C       12
+#define RTC_REG_D       13
+
+/**********************************************************************
+ * register details
+ **********************************************************************/
+#define RTC_FREQ_SELECT RTC_REG_A
+
+/* update-in-progress  - set to "1" 244 microsecs before RTC goes off the bus,
+ * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
+ * totalling to a max high interval of 2.228 ms.
+ */
+# define RTC_UIP        0x80
+# define RTC_DIV_CTL        0x70
+   /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
+#  define RTC_REF_CLCK_4MHZ 0x00
+#  define RTC_REF_CLCK_1MHZ 0x10
+#  define RTC_REF_CLCK_32KHZ    0x20
+   /* 2 values for divider stage reset, others for "testing purposes only" */
+#  define RTC_DIV_RESET1    0x60
+#  define RTC_DIV_RESET2    0x70
+  /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
+# define RTC_RATE_SELECT    0x0F
+
+/**********************************************************************/
+#define RTC_CONTROL RTC_REG_B
+# define RTC_SET 0x80       /* disable updates for clock setting */
+# define RTC_PIE 0x40       /* periodic interrupt enable */
+# define RTC_AIE 0x20       /* alarm interrupt enable */
+# define RTC_UIE 0x10       /* update-finished interrupt enable */
+# define RTC_SQWE 0x08      /* enable square-wave output */
+# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
+# define RTC_24H 0x02       /* 24 hour mode - else hours bit 7 means pm */
+# define RTC_DST_EN 0x01    /* auto switch DST - works f. USA only */
+
+/**********************************************************************/
+#define RTC_INTR_FLAGS  RTC_REG_C
+/* caution - cleared by read */
+# define RTC_IRQF 0x80      /* any of the following 3 is active */
+# define RTC_PF 0x40
+# define RTC_AF 0x20
+# define RTC_UF 0x10
+
+/**********************************************************************/
+#define RTC_VALID   RTC_REG_D
+# define RTC_VRT 0x80       /* valid RAM and time */
+/**********************************************************************/
+
+/* example: !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY)
+ * determines if the following two #defines are needed
+ */
+#ifndef BCD_TO_BIN
+#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
+#endif
+
+#ifndef BIN_TO_BCD
+#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
+#endif
+
+#endif /* _MC146818RTC_H */
diff --git a/include/linux/mii.h b/include/linux/mii.h
new file mode 100755
index 0000000..8b92692
--- /dev/null
+++ b/include/linux/mii.h
@@ -0,0 +1,191 @@
+/*
+ * linux/mii.h: definitions for MII-compatible transceivers
+ * Originally drivers/net/sunhme.h.
+ *
+ * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef __LINUX_MII_H__
+#define __LINUX_MII_H__
+
+/* Generic MII registers. */
+
+#define MII_BMCR	    0x00	/* Basic mode control register */
+#define MII_BMSR	    0x01	/* Basic mode status register  */
+#define MII_PHYSID1	    0x02	/* PHYS ID 1		       */
+#define MII_PHYSID2	    0x03	/* PHYS ID 2		       */
+#define MII_ADVERTISE	    0x04	/* Advertisement control reg   */
+#define MII_LPA		    0x05	/* Link partner ability reg    */
+#define MII_EXPANSION	    0x06	/* Expansion register	       */
+#define MII_CTRL1000	    0x09	/* 1000BASE-T control	       */
+#define MII_STAT1000	    0x0a	/* 1000BASE-T status	       */
+#define MII_ESTATUS	    0x0f	/* Extended Status */
+#define MII_DCOUNTER	    0x12	/* Disconnect counter	       */
+#define MII_FCSCOUNTER	    0x13	/* False carrier counter       */
+#define MII_NWAYTEST	    0x14	/* N-way auto-neg test reg     */
+#define MII_RERRCOUNTER     0x15	/* Receive error counter       */
+#define MII_SREVISION	    0x16	/* Silicon revision	       */
+#define MII_RESV1	    0x17	/* Reserved...		       */
+#define MII_LBRERROR	    0x18	/* Lpback, rx, bypass error    */
+#define MII_PHYADDR	    0x19	/* PHY address		       */
+#define MII_RESV2	    0x1a	/* Reserved...		       */
+#define MII_TPISTATUS	    0x1b	/* TPI status for 10mbps       */
+#define MII_NCONFIG	    0x1c	/* Network interface config    */
+
+/* Basic mode control register. */
+#define BMCR_RESV		0x003f	/* Unused...		       */
+#define BMCR_SPEED1000		0x0040	/* MSB of Speed (1000)	       */
+#define BMCR_CTST		0x0080	/* Collision test	       */
+#define BMCR_FULLDPLX		0x0100	/* Full duplex		       */
+#define BMCR_ANRESTART		0x0200	/* Auto negotiation restart    */
+#define BMCR_ISOLATE		0x0400	/* Disconnect DP83840 from MII */
+#define BMCR_PDOWN		0x0800	/* Powerdown the DP83840       */
+#define BMCR_ANENABLE		0x1000	/* Enable auto negotiation     */
+#define BMCR_SPEED100		0x2000	/* Select 100Mbps	       */
+#define BMCR_LOOPBACK		0x4000	/* TXD loopback bits	       */
+#define BMCR_RESET		0x8000	/* Reset the DP83840	       */
+
+/* Basic mode status register. */
+#define BMSR_ERCAP		0x0001	/* Ext-reg capability	       */
+#define BMSR_JCD		0x0002	/* Jabber detected	       */
+#define BMSR_LSTATUS		0x0004	/* Link status		       */
+#define BMSR_ANEGCAPABLE	0x0008	/* Able to do auto-negotiation */
+#define BMSR_RFAULT		0x0010	/* Remote fault detected       */
+#define BMSR_ANEGCOMPLETE	0x0020	/* Auto-negotiation complete   */
+#define BMSR_RESV		0x00c0	/* Unused...		       */
+#define BMSR_ESTATEN		0x0100	/* Extended Status in R15 */
+#define BMSR_100HALF2		0x0200	/* Can do 100BASE-T2 HDX */
+#define BMSR_100FULL2		0x0400	/* Can do 100BASE-T2 FDX */
+#define BMSR_10HALF		0x0800	/* Can do 10mbps, half-duplex  */
+#define BMSR_10FULL		0x1000	/* Can do 10mbps, full-duplex  */
+#define BMSR_100HALF		0x2000	/* Can do 100mbps, half-duplex */
+#define BMSR_100FULL		0x4000	/* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4		0x8000	/* Can do 100mbps, 4k packets  */
+
+/* Advertisement control register. */
+#define ADVERTISE_SLCT		0x001f	/* Selector bits	       */
+#define ADVERTISE_CSMA		0x0001	/* Only selector supported     */
+#define ADVERTISE_10HALF	0x0020	/* Try for 10mbps half-duplex  */
+#define ADVERTISE_1000XFULL	0x0020	/* Try for 1000BASE-X full-duplex */
+#define ADVERTISE_10FULL	0x0040	/* Try for 10mbps full-duplex  */
+#define ADVERTISE_1000XHALF	0x0040	/* Try for 1000BASE-X half-duplex */
+#define ADVERTISE_100HALF	0x0080	/* Try for 100mbps half-duplex */
+#define ADVERTISE_1000XPAUSE	0x0080	/* Try for 1000BASE-X pause    */
+#define ADVERTISE_100FULL	0x0100	/* Try for 100mbps full-duplex */
+#define ADVERTISE_1000XPSE_ASYM 0x0100	/* Try for 1000BASE-X asym pause */
+#define ADVERTISE_100BASE4	0x0200	/* Try for 100mbps 4k packets  */
+#define ADVERTISE_PAUSE_CAP	0x0400	/* Try for pause	       */
+#define ADVERTISE_PAUSE_ASYM	0x0800	/* Try for asymetric pause     */
+#define ADVERTISE_RESV		0x1000	/* Unused...		       */
+#define ADVERTISE_RFAULT	0x2000	/* Say we can detect faults    */
+#define ADVERTISE_LPACK		0x4000	/* Ack link partners response  */
+#define ADVERTISE_NPAGE		0x8000	/* Next page bit	       */
+
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
+			ADVERTISE_CSMA)
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+		       ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/* Link partner ability register. */
+#define LPA_SLCT		0x001f	/* Same as advertise selector  */
+#define LPA_10HALF		0x0020	/* Can do 10mbps half-duplex   */
+#define LPA_1000XFULL		0x0020	/* Can do 1000BASE-X full-duplex */
+#define LPA_10FULL		0x0040	/* Can do 10mbps full-duplex   */
+#define LPA_1000XHALF		0x0040	/* Can do 1000BASE-X half-duplex */
+#define LPA_100HALF		0x0080	/* Can do 100mbps half-duplex  */
+#define LPA_1000XPAUSE		0x0080	/* Can do 1000BASE-X pause     */
+#define LPA_100FULL		0x0100	/* Can do 100mbps full-duplex  */
+#define LPA_1000XPAUSE_ASYM	0x0100	/* Can do 1000BASE-X pause asym*/
+#define LPA_100BASE4		0x0200	/* Can do 100mbps 4k packets   */
+#define LPA_PAUSE_CAP		0x0400	/* Can pause		       */
+#define LPA_PAUSE_ASYM		0x0800	/* Can pause asymetrically     */
+#define LPA_RESV		0x1000	/* Unused...		       */
+#define LPA_RFAULT		0x2000	/* Link partner faulted        */
+#define LPA_LPACK		0x4000	/* Link partner acked us       */
+#define LPA_NPAGE		0x8000	/* Next page bit	       */
+
+#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
+#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+/* Expansion register for auto-negotiation. */
+#define EXPANSION_NWAY		0x0001	/* Can do N-way auto-nego      */
+#define EXPANSION_LCWP		0x0002	/* Got new RX page code word   */
+#define EXPANSION_ENABLENPAGE	0x0004	/* This enables npage words    */
+#define EXPANSION_NPCAPABLE	0x0008	/* Link partner supports npage */
+#define EXPANSION_MFAULTS	0x0010	/* Multiple faults detected    */
+#define EXPANSION_RESV		0xffe0	/* Unused...		       */
+
+#define ESTATUS_1000_TFULL	0x2000	/* Can do 1000BT Full */
+#define ESTATUS_1000_THALF	0x1000	/* Can do 1000BT Half */
+
+/* N-way test register. */
+#define NWAYTEST_RESV1		0x00ff	/* Unused...		       */
+#define NWAYTEST_LOOPBACK	0x0100	/* Enable loopback for N-way   */
+#define NWAYTEST_RESV2		0xfe00	/* Unused...		       */
+
+/* 1000BASE-T Control register */
+#define ADVERTISE_1000FULL	0x0200	/* Advertise 1000BASE-T full duplex */
+#define ADVERTISE_1000HALF	0x0100	/* Advertise 1000BASE-T half duplex */
+
+/* 1000BASE-T Status register */
+#define LPA_1000LOCALRXOK	0x2000	/* Link partner local receiver status */
+#define LPA_1000REMRXOK		0x1000	/* Link partner remote receiver status */
+#define LPA_1000FULL		0x0800	/* Link partner 1000BASE-T full duplex */
+#define LPA_1000HALF		0x0400	/* Link partner 1000BASE-T half duplex */
+
+/* Flow control flags */
+#define FLOW_CTRL_TX		0x01
+#define FLOW_CTRL_RX		0x02
+
+/**
+ * mii_nway_result
+ * @negotiated: value of MII ANAR and'd with ANLPAR
+ *
+ * Given a set of MII abilities, check each bit and returns the
+ * currently supported media, in the priority order defined by
+ * IEEE 802.3u.  We use LPA_xxx constants but note this is not the
+ * value of LPA solely, as described above.
+ *
+ * The one exception to IEEE 802.3u is that 100baseT4 is placed
+ * between 100T-full and 100T-half.  If your phy does not support
+ * 100T4 this is fine. If your phy places 100T4 elsewhere in the
+ * priority order, you will need to roll your own function.
+ */
+static inline unsigned int mii_nway_result (unsigned int negotiated)
+{
+	unsigned int ret;
+
+	if (negotiated & LPA_100FULL)
+		ret = LPA_100FULL;
+	else if (negotiated & LPA_100BASE4)
+		ret = LPA_100BASE4;
+	else if (negotiated & LPA_100HALF)
+		ret = LPA_100HALF;
+	else if (negotiated & LPA_10FULL)
+		ret = LPA_10FULL;
+	else
+		ret = LPA_10HALF;
+
+	return ret;
+}
+
+/**
+ * mii_duplex
+ * @duplex_lock: Non-zero if duplex is locked at full
+ * @negotiated: value of MII ANAR and'd with ANLPAR
+ *
+ * A small helper function for a common case.  Returns one
+ * if the media is operating or locked at full duplex, and
+ * returns zero otherwise.
+ */
+static inline unsigned int mii_duplex (unsigned int duplex_lock,
+				       unsigned int negotiated)
+{
+	if (duplex_lock)
+		return 1;
+	if (mii_nway_result(negotiated) & LPA_DUPLEX)
+		return 1;
+	return 0;
+}
+
+#endif /* __LINUX_MII_H__ */
diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h
new file mode 100755
index 0000000..ebf9a76
--- /dev/null
+++ b/include/linux/mtd/doc2000.h
@@ -0,0 +1,151 @@
+
+/* Linux driver for Disk-On-Chip 2000       */
+/* (c) 1999 Machine Vision Holdings, Inc.   */
+/* Author: David Woodhouse <dwmw2@mvhi.com> */
+/* $Id: doc2000.h,v 1.15 2001/09/19 00:22:15 dwmw2 Exp $ */
+
+#ifndef __MTD_DOC2000_H__
+#define __MTD_DOC2000_H__
+
+struct DiskOnChip;
+
+#include <linux/mtd/nftl.h>
+
+#define DoC_Sig1 0
+#define DoC_Sig2 1
+
+#define DoC_ChipID		0x1000
+#define DoC_DOCStatus		0x1001
+#define DoC_DOCControl		0x1002
+#define DoC_FloorSelect		0x1003
+#define DoC_CDSNControl		0x1004
+#define DoC_CDSNDeviceSelect 	0x1005
+#define DoC_ECCConf 		0x1006
+#define DoC_2k_ECCStatus	0x1007
+
+#define DoC_CDSNSlowIO		0x100d
+#define DoC_ECCSyndrome0	0x1010
+#define DoC_ECCSyndrome1	0x1011
+#define DoC_ECCSyndrome2	0x1012
+#define DoC_ECCSyndrome3	0x1013
+#define DoC_ECCSyndrome4	0x1014
+#define DoC_ECCSyndrome5	0x1015
+#define DoC_AliasResolution 	0x101b
+#define DoC_ConfigInput		0x101c
+#define DoC_ReadPipeInit 	0x101d
+#define DoC_WritePipeTerm 	0x101e
+#define DoC_LastDataRead 	0x101f
+#define DoC_NOP 		0x1020
+
+#define DoC_Mil_CDSN_IO 	0x0800
+#define DoC_2k_CDSN_IO 		0x1800
+
+#define ReadDOC_(adr, reg)      ((volatile unsigned char)(*(volatile __u8 *)(((unsigned long)adr)+((reg)))))
+#define WriteDOC_(d, adr, reg)  do{ *(volatile __u8 *)(((unsigned long)adr)+((reg))) = (__u8)d; eieio();} while(0)
+
+#define DOC_IOREMAP_LEN		0x4000
+
+/* These are provided to directly use the DoC_xxx defines */
+#define ReadDOC(adr, reg)      ReadDOC_(adr,DoC_##reg)
+#define WriteDOC(d, adr, reg)  WriteDOC_(d,adr,DoC_##reg)
+
+#define DOC_MODE_RESET 		0
+#define DOC_MODE_NORMAL 	1
+#define DOC_MODE_RESERVED1 	2
+#define DOC_MODE_RESERVED2 	3
+
+#define DOC_MODE_MDWREN 	4
+#define DOC_MODE_CLR_ERR 	0x80
+
+#define DOC_ChipID_UNKNOWN 	0x00
+#define DOC_ChipID_Doc2k 	0x20
+#define DOC_ChipID_DocMil 	0x30
+
+#define CDSN_CTRL_FR_B 		0x80
+#define CDSN_CTRL_ECC_IO 	0x20
+#define CDSN_CTRL_FLASH_IO 	0x10
+#define CDSN_CTRL_WP 		0x08
+#define CDSN_CTRL_ALE 		0x04
+#define CDSN_CTRL_CLE 		0x02
+#define CDSN_CTRL_CE 		0x01
+
+#define DOC_ECC_RESET 		0
+#define DOC_ECC_ERROR 		0x80
+#define DOC_ECC_RW 		0x20
+#define DOC_ECC__EN 		0x08
+#define DOC_TOGGLE_BIT 		0x04
+#define DOC_ECC_RESV 		0x02
+#define DOC_ECC_IGNORE		0x01
+
+/* We have to also set the reserved bit 1 for enable */
+#define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV)
+#define DOC_ECC_DIS (DOC_ECC_RESV)
+
+#define MAX_FLOORS 4
+#define MAX_CHIPS 4
+
+#define MAX_FLOORS_MIL 4
+#define MAX_CHIPS_MIL 1
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+struct DiskOnChip {
+	unsigned long physadr;
+	unsigned long virtadr;
+	unsigned long totlen;
+	char* name;
+	char ChipID; /* Type of DiskOnChip */
+	int ioreg;
+
+	char* chips_name;
+	unsigned long mfr; /* Flash IDs - only one type of flash per device */
+	unsigned long id;
+	int chipshift;
+	char page256;
+	char pageadrlen;
+	unsigned long erasesize;
+
+	int curfloor;
+	int curchip;
+
+	int numchips;
+	struct Nand *chips;
+
+	int nftl_found;
+	struct NFTLrecord nftl;
+};
+
+#define SECTORSIZE 512
+
+/* Return codes from doc_write(), doc_read(), and doc_erase().
+ */
+#define DOC_OK		0
+#define DOC_EIO		1
+#define DOC_EINVAL	2
+#define DOC_EECC	3
+#define DOC_ETIMEOUT	4
+
+/*
+ * Function Prototypes
+ */
+int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]);
+
+int doc_rw(struct DiskOnChip* this, int cmd, loff_t from, size_t len,
+	   size_t *retlen, u_char *buf);
+int doc_read_ecc(struct DiskOnChip* this, loff_t from, size_t len,
+		 size_t *retlen, u_char *buf, u_char *eccbuf);
+int doc_write_ecc(struct DiskOnChip* this, loff_t to, size_t len,
+		  size_t *retlen, const u_char *buf, u_char *eccbuf);
+int doc_read_oob(struct DiskOnChip* this, loff_t ofs, size_t len,
+		 size_t *retlen, u_char *buf);
+int doc_write_oob(struct DiskOnChip* this, loff_t ofs, size_t len,
+		  size_t *retlen, const u_char *buf);
+int doc_erase (struct DiskOnChip* this, loff_t ofs, size_t len);
+
+void doc_probe(unsigned long physadr);
+
+void doc_print(struct DiskOnChip*);
+
+#endif /* __MTD_DOC2000_H__ */
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
new file mode 100755
index 0000000..f365744
--- /dev/null
+++ b/include/linux/mtd/nand.h
@@ -0,0 +1,430 @@
+/*
+ *  linux/include/linux/mtd/nand.h
+ *
+ *  Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
+ *                     Steven J. Hill <sjhill@cotw.com>
+ *		       Thomas Gleixner <gleixner@autronix.de>
+ *
+ * $Id: nand.h,v 1.7 2003/07/24 23:30:46 a0384864 Exp $
+ *
+ *  Copyright (c) 2008 WonderMedia Technologies, Inc.
+ *
+ *  This program is free software: you can redistribute it and/or modify it under the
+ *  terms of the GNU General Public License as published by the Free Software Foundation,
+ *  either version 2 of the License, or (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+ *  PARTICULAR PURPOSE.  See the GNU General Public License for more details.
+ *  You should have received a copy of the GNU General Public License along with
+ *  this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  WonderMedia Technologies, Inc.
+ *  10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+ *
+ *  Info:
+ *   Contains standard defines and IDs for NAND flash devices
+ *
+ *  Changelog:
+ *   01-31-2000 DMW     Created
+ *   09-18-2000 SJH     Moved structure out of the Disk-On-Chip drivers
+ *			so it can be used by other NAND flash device
+ *			drivers. I also changed the copyright since none
+ *			of the original contents of this file are specific
+ *			to DoC devices. David can whack me with a baseball
+ *			bat later if I did something naughty.
+ *   10-11-2000 SJH     Added private NAND flash structure for driver
+ *   10-24-2000 SJH     Added prototype for 'nand_scan' function
+ *   10-29-2001 TG	changed nand_chip structure to support
+ *			hardwarespecific function for accessing control lines
+ *   02-21-2002 TG	added support for different read/write adress and
+ *			ready/busy line access function
+ *   02-26-2002 TG	added chip_delay to nand_chip structure to optimize
+ *			command delay times for different chips
+ *   04-28-2002 TG	OOB config defines moved from nand.c to avoid duplicate
+ *			defines in jffs2/wbuf.c
+ */
+#ifndef __LINUX_MTD_NAND_H
+#define __LINUX_MTD_NAND_H
+
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0		0
+#define NAND_CMD_READ1		1
+#define NAND_CMD_PAGEPROG	0x10
+#define NAND_CMD_READOOB	0x50
+#define NAND_CMD_ERASE1		0x60
+#define NAND_CMD_STATUS		0x70
+#define NAND_CMD_SEQIN		0x80
+#define NAND_CMD_READID		0x90
+#define NAND_CMD_ERASE2		0xd0
+#define NAND_CMD_RESET		0xff
+
+/*
+ * Enumeration for NAND flash chip state
+ */
+enum nand_state_t {
+	FL_READY,
+	FL_READING,
+	FL_WRITING,
+	FL_ERASING,
+	FL_SYNCING
+};
+
+/*
+ * NAND Private Flash Chip Data
+ *
+ * Structure overview:
+ *
+ *  IO_ADDR - address to access the 8 I/O lines of the flash device
+ *
+ *  hwcontrol - hardwarespecific function for accesing control-lines
+ *
+ *  dev_ready - hardwarespecific function for accesing device ready/busy line
+ *
+ *  chip_lock - spinlock used to protect access to this structure
+ *
+ *  wq - wait queue to sleep on if a NAND operation is in progress
+ *
+ *  state - give the current state of the NAND device
+ *
+ *  page_shift - number of address bits in a page (column address bits)
+ *
+ *  data_buf - data buffer passed to/from MTD user modules
+ *
+ *  data_cache - data cache for redundant page access and shadow for
+ *		 ECC failure
+ *
+ *  ecc_code_buf - used only for holding calculated or read ECCs for
+ *                 a page read or written when ECC is in use
+ *
+ *  reserved - padding to make structure fall on word boundary if
+ *             when ECC is in use
+ */
+
+#ifdef CFG_WMT_NFC
+
+#define __NFC_BASE 0xd8009000
+
+struct WMT_NFC_t {
+	struct WMT_NFC_CFG	*const reg; /* register set */
+	unsigned int	ecc_type;
+};
+
+struct WMT_NFC_t nfc = {
+	(struct WMT_NFC_CFG *)(__NFC_BASE),
+#ifdef CONFIG_NFC_HW_ECC
+	USE_HW_ECC
+#else
+	USE_SW_ECC
+#endif
+};
+
+#endif
+
+struct Nand {
+	char floor, chip;
+	unsigned long curadr;
+	unsigned char curmode;
+	/* Also some erase/write/pipeline info when we get that far */
+};
+
+struct nand_oobinfo {
+	unsigned int useecc;
+	unsigned int eccbytes;
+	unsigned int oobfree[8][2];
+	unsigned int eccpos[48];
+};
+
+struct nand_oobfree {
+	unsigned int offset;
+	unsigned int length;
+};
+
+struct nand_ecclayout {
+	unsigned int eccbytes;
+	unsigned int eccpos[128];
+	unsigned int oobavail;
+	struct nand_oobfree oobfree[8];	
+};
+
+struct nand_ecc_ctrl {
+	unsigned int steps;
+	unsigned int size;
+	unsigned int bytes;
+	unsigned int total;
+	struct nand_ecclayout *layout;
+};
+
+#define DWORD	unsigned int
+#define MAX_PRODUCT_NAME_LENGTH 0x20
+
+struct nand_chip {
+	DWORD dwFlashID;       /*composed by the first byte and the second byte*/
+	DWORD dwBlockCount;      /*how many blocks one chip have*/
+	DWORD dwPageSize;       /*page size*/
+	
+	DWORD dwSpareSize;       /*spare area size*/
+	DWORD dwBlockSize;       /*block size*/
+	DWORD dwAddressCycle;      /*address cycle 4 or 5*/
+	DWORD dwBI0Position;      /*BI0 page postion in block*/
+	DWORD dwBI1Position;      /*BI1 page postion in block*/
+	DWORD dwBIOffset;       /*BI offset in page*/
+	DWORD dwDataWidth;      /*data with X8 or X16*/
+	DWORD dwPageProgramLimit;     /*chip can program PAGE_PROGRAM_LIMIT times within the same page*/
+	DWORD dwSeqRowReadSupport;    /*whether support sequential row read, 1 = support 0 = not support*/
+	DWORD dwSeqPageProgram;     /*chip need sequential page program in a block. 1 = need*/
+	DWORD dwNandType;       /*MLC or SLC*/
+	DWORD dwECCBitNum;      /*ECC bit number needed*/
+	DWORD dwRWTimming;
+	DWORD dwTwbTwhrTadl;      		//NFC write TADL timeing config
+	DWORD dwDDR;      		  //NFC support toshia ddr(toggle) mode = 1 not support = 0
+	DWORD dwRetry;    		  //NFC Read Retry support = 1 no
+	int dwRdmz; 			//NFC Randomizer support = 1,
+	DWORD dwFlashID2;      //composed by additional 2 bytes of ID from original 4 bytes.
+	DWORD dwSpeedUpCmd;		/* supprot speed up nand command ex: 2-plane cache read and so on.. */
+	char cProductName[MAX_PRODUCT_NAME_LENGTH]; /*product name. for example "HYNIX_NF_HY27UF081G2A"*/
+	/*other informations*/
+	unsigned int  col; /* addr_cycle; */
+	unsigned int  row; /* page_cycle; */
+
+	unsigned int col_offset;
+	//unsigned int 	page[2];
+	//unsigned int  bbpos;
+	//struct WMT_nand_flash_dev *nand_dev_info;
+	int (*nfc_read_page)(struct nand_chip *nand, unsigned int start, unsigned int maddr, unsigned int len);
+	int (*update_table_inflash)(struct nand_chip *nand, unsigned int last, int chip);
+	int (*update_table_inram)(struct nand_chip *nand, unsigned int addr, int chip);
+	int (*isbadblock)(struct nand_chip *nand, unsigned int addr, int chip);
+	DWORD dwPageSizeControl;
+	DWORD dwPageCount;
+	DWORD dwSectorCount;
+	DWORD dwECCType;
+	DWORD dwSectorSize;
+	int nChipOffset;
+	int nChipCnt;
+	DWORD dwSectorCntPerPage;
+	DWORD dwTBLItemCntPerPage;     /* 4 blocks for 1 item*/
+	DWORD dwReservedBlockCnt;
+	DWORD dwECCENGINBitNum;
+	/*------------above is defined by WMT---------------------------*/
+	/*------------below is defined by open source-------------------*/
+	int oob_flag;// write oob data in page program function
+	int pagebuf;
+	int    page_shift;
+	u_char *data_buf;
+	u_char *data_cache;
+	int    cache_page;
+	u_char ecc_code_buf[6];
+	u_char *buffers;
+	u_char *oob_poi;
+	struct nand_ecc_ctrl ecc;
+	u_char reserved[2];
+	char   ChipID; /* Type of DiskOnChip */
+	struct Nand *chips;
+	int  chipshift;
+	char *chips_name;
+	unsigned long erasesize;
+	unsigned long mfr; /* Flash IDs - only one type of flash per device */
+	unsigned long id;
+	unsigned int  id2;
+	char *name;
+	int  numchips;
+	char page256;
+	char pageadrlen;
+	unsigned long IO_ADDR;  /* address to access the 8 I/O lines to the flash device */
+	long long totlen;
+	uint oobblock;  /* Size of OOB blocks (e.g. 512) */
+	uint oobsize;   /* Amount of OOB data per block (e.g. 16) */
+	uint eccsize;
+	uint ooblen;
+	int bus16;
+	int realplanenum;
+	int unc_banks;
+	int cur_page; /* current read/write page */
+	int bbt_sw_rdmz; /* a mode to read bbt with sw rdmz */
+	uint oobblock_K;
+	uint oobblock_valid;
+	uint erasesize_valid;
+	uint l_oobblock;/*logical page size that kernel use*/
+	uint l_erasesize;/*logical block size that kernel use*/
+};
+
+//#define BOOT_MAGIC "ANDROID!"
+#define BOOT_MAGIC_SIZE 8
+#define BOOT_NAME_SIZE 16
+#define BOOT_ARGS_SIZE 512
+struct boot_img_hdr
+{
+    unsigned char magic[BOOT_MAGIC_SIZE];
+
+    unsigned kernel_size;  /* size in bytes */
+    unsigned kernel_addr;  /* physical load addr */
+
+    unsigned ramdisk_size; /* size in bytes */
+    unsigned ramdisk_addr; /* physical load addr */
+
+    unsigned second_size;  /* size in bytes */
+    unsigned second_addr;  /* physical load addr */
+
+    unsigned tags_addr;    /* physical addr for kernel tags */
+    unsigned page_size;    /* flash page size we assume */
+    unsigned unused[2];    /* future expansion: should be 0 */
+
+    unsigned char name[BOOT_NAME_SIZE]; /* asciiz product name */
+    
+    unsigned char cmdline[BOOT_ARGS_SIZE];
+
+    unsigned id[8]; /* timestamp / checksum / sha1 / etc */
+};
+
+// read retry
+#define ESLC_MODE 0
+#define READ_RETRY_MODE 1
+#define TEST_MODE 2
+#define DEFAULT_VALUE 0
+#define ECC_ERROR_VALUE 1
+
+//All
+struct nand_read_retry_param {
+	char magic[32];
+	unsigned int  nand_id;
+	unsigned int  nand_id_5th;
+	unsigned int  eslc_reg_num;
+	unsigned char eslc_offset[32];
+	unsigned char eslc_def_value[32];
+	unsigned char eslc_set_value[32];
+	unsigned int  retry_reg_num;
+	unsigned char  retry_offset[32];
+	unsigned char retry_def_value[32];
+	unsigned char retry_value[256];
+	unsigned int otp_len;
+	unsigned char otp_offset[32];
+	unsigned char otp_data[32];
+	unsigned int total_try_times;
+	int cur_try_times;
+	int (*set_parameter)(struct nand_chip *nand, int mode, int def_mode);
+	int (*get_parameter)(struct nand_chip *nand, int mode);
+	int (*get_otp_table)(struct nand_chip *nand);
+	int retry; //1: in retry mode 
+	int read_table;
+};
+
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA	0x98
+#define NAND_MFR_SAMSUNG	0xec
+#define NAND_MFR_HYNIX    0xad
+
+/*
+ * NAND Flash Device ID Structure
+ *
+ * Structure overview:
+ *
+ *  name - Complete name of device
+ *
+ *  manufacture_id - manufacturer ID code of device.
+ *
+ *  model_id - model ID code of device.
+ *
+ *  chipshift - total number of address bits for the device which
+ *              is used to calculate address offsets and the total
+ *              number of bytes the device is capable of.
+ *
+ *  page256 - denotes if flash device has 256 byte pages or not.
+ *
+ *  pageadrlen - number of bytes minus one needed to hold the
+ *               complete address into the flash array. Keep in
+ *               mind that when a read or write is done to a
+ *               specific address, the address is input serially
+ *               8 bits at a time. This structure member is used
+ *               by the read/write routines as a loop index for
+ *               shifting the address out 8 bits at a time.
+ *
+ *  erasesize - size of an erase block in the flash device.
+ */
+struct nand_flash_dev {
+	char *name;
+	int manufacture_id;
+	int model_id;
+	int chipshift;
+	char page256;
+	char pageadrlen;
+	unsigned long erasesize;
+	int bus16;
+};
+
+
+
+/* Nand Product Table          We take HYNIX_NF_HY27UF081G2A for example.*/
+
+struct WMT_nand_flash_dev{
+ DWORD dwFlashID;            //composed by 4 bytes of ID. For example:0xADF1801D
+ DWORD dwBlockCount;      //block count of one chip. For example: 1024
+ DWORD dwPageSize;       //page size. For example:2048(other value can be 512 or 4096)
+ DWORD dwSpareSize;       //spare area size. For example:16(almost all kinds of nand is 16)
+ DWORD dwBlockSize;       //block size = dwPageSize * PageCntPerBlock. For example:131072
+ DWORD dwAddressCycle;      //address cycle 4 or 5
+ DWORD dwBI0Position;      //BI0 page postion in block
+ DWORD dwBI1Position;      //BI1 page postion in block
+ DWORD dwBIOffset;       //BI offset in page
+ DWORD dwDataWidth;      //data with X8 or X16
+ DWORD dwPageProgramLimit;     //chip can program PAGE_PROGRAM_LIMIT times within the same page
+ DWORD dwSeqRowReadSupport;    //whether support sequential row read, 1 = support 0 = not support
+ DWORD dwSeqPageProgram;     //chip need sequential page program in a block. 1 = need
+ DWORD dwNandType;       //MLC or SLC
+ DWORD dwECCBitNum;      //ECC bit number needed
+ DWORD dwRWTimming;     //NFC Read/Write Pulse width and Read/Write hold time. default =0x12121010
+ DWORD dwTwbTwhrTadl;   //NFC byte 3: TWB, byte 2:TWHR, byte 1-0: TADL (refer flash datasheet).
+ DWORD dwDDR;      		  //NFC support toshia ddr(toggle) mode = 1 not support = 0
+ DWORD dwRetry;    		  //NFC Read Retry support = 1 no
+ DWORD dwRdmz; 			//NFC Randomizer support = 1,
+ DWORD dwFlashID2;      //composed by additional 2 bytes of ID from original 4 bytes.
+ DWORD dwSpeedUpCmd;		/* supprot speed up nand command ex: 2-plane cache read and so on.. */
+ char ProductName[MAX_PRODUCT_NAME_LENGTH]; //product name. for example "HYNIX_NF_HY27UF081G2A"
+};
+
+
+/*
+* Constants for oob configuration
+*/
+#define NAND_NOOB_ECCPOS0		0
+#define NAND_NOOB_ECCPOS1		1
+#define NAND_NOOB_ECCPOS2		2
+#define NAND_NOOB_ECCPOS3		3
+#define NAND_NOOB_ECCPOS4		6
+#define NAND_NOOB_ECCPOS5		7
+#define NAND_NOOB_BADBPOS		-1
+#define NAND_NOOB_ECCVPOS		-1
+
+#define NAND_JFFS2_OOB_ECCPOS0		0
+#define NAND_JFFS2_OOB_ECCPOS1		1
+#define NAND_JFFS2_OOB_ECCPOS2		2
+#define NAND_JFFS2_OOB_ECCPOS3		3
+#define NAND_JFFS2_OOB_ECCPOS4		6
+#define NAND_JFFS2_OOB_ECCPOS5		7
+#define NAND_JFFS2_OOB_BADBPOS		5
+#define NAND_JFFS2_OOB_ECCVPOS		4
+
+#define NAND_JFFS2_OOB8_FSDAPOS		6
+#define NAND_JFFS2_OOB16_FSDAPOS	8
+#define NAND_JFFS2_OOB8_FSDALEN		2
+#define NAND_JFFS2_OOB16_FSDALEN	8
+
+unsigned long nand_probe(unsigned long physadr);
+int hynix_set_parameter(struct nand_chip *nand, int mode, int def_mode);
+int hynix_get_parameter(struct nand_chip *nand, int mode);
+int hynix_get_otp(struct nand_chip *nand);
+int toshiba_get_parameter(struct nand_chip *nand, int mode);
+int toshiba_set_parameter(struct nand_chip *nand, int mode, int def);
+
+int wmt_nand_read(int dev, unsigned int addr, char *filename, int bytes);
+int wmt_nand_write(int dev, unsigned int addr, char *filename, int bytes);
+
+unsigned long get_nand_data_tol_size(void);
+unsigned int get_nand_blk_KB_size(void);
+unsigned long get_nand_valid_partial_write_size(unsigned long buffer_bound_MB);
+
+#endif /* __LINUX_MTD_NAND_H */
diff --git a/include/linux/mtd/nand_ids.h b/include/linux/mtd/nand_ids.h
new file mode 100755
index 0000000..6c66ae5
--- /dev/null
+++ b/include/linux/mtd/nand_ids.h
@@ -0,0 +1,497 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+/*
+ *  u-boot/include/linux/mtd/nand_ids.h
+ *
+ *  Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
+ *                     Steven J. Hill <sjhill@cotw.com>
+ *
+ * $Id: nand_ids.h,v 1.1 2000/10/13 16:16:26 mdeans Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Info:
+ *   Contains standard defines and IDs for NAND flash devices
+ *
+ *  Changelog:
+ *   01-31-2000 DMW     Created
+ *   09-18-2000 SJH     Moved structure out of the Disk-On-Chip drivers
+ *			so it can be used by other NAND flash device
+ *			drivers. I also changed the copyright since none
+ *			of the original contents of this file are specific
+ *			to DoC devices. David can whack me with a baseball
+ *			bat later if I did something naughty.
+ *   10-11-2000 SJH     Added private NAND flash structure for driver
+ *   2000-10-13 BE      Moved out of 'nand.h' - avoids duplication.
+ */
+
+#ifndef __LINUX_MTD_NAND_IDS_H
+#define __LINUX_MTD_NAND_IDS_H
+#if 0
+static struct nand_flash_dev nand_flash_ids[] = {
+	{"Toshiba TC5816BDC",     NAND_MFR_TOSHIBA, 0x64, 21, 1, 2, 0x1000, 0},
+	{"Toshiba TC5832DC",      NAND_MFR_TOSHIBA, 0x6b, 22, 0, 2, 0x2000, 0},
+	{"Toshiba TH58V128DC",    NAND_MFR_TOSHIBA, 0x73, 24, 0, 2, 0x4000, 0},
+	{"Toshiba TC58256FT/DC",  NAND_MFR_TOSHIBA, 0x75, 25, 0, 2, 0x4000, 0},
+	{"Toshiba TH58512FT",     NAND_MFR_TOSHIBA, 0x76, 26, 0, 3, 0x4000, 0},
+	{"Toshiba TC58V32DC",     NAND_MFR_TOSHIBA, 0xe5, 22, 0, 2, 0x2000, 0},
+	{"Toshiba TC58V64AFT/DC", NAND_MFR_TOSHIBA, 0xe6, 23, 0, 2, 0x2000, 0},
+	{"Toshiba TC58V16BDC",    NAND_MFR_TOSHIBA, 0xea, 21, 1, 2, 0x1000, 0},
+	{"Toshiba TH58100FT",     NAND_MFR_TOSHIBA, 0x79, 27, 0, 3, 0x4000, 0},
+	{"Samsung KM29N16000",    NAND_MFR_SAMSUNG, 0x64, 21, 1, 2, 0x1000, 0},
+	{"Samsung unknown 4Mb",   NAND_MFR_SAMSUNG, 0x6b, 22, 0, 2, 0x2000, 0},
+	{"Samsung KM29U128T",     NAND_MFR_SAMSUNG, 0x73, 24, 0, 2, 0x4000, 0},
+	{"Samsung KM29U256T",     NAND_MFR_SAMSUNG, 0x75, 25, 0, 2, 0x4000, 0},
+	{"Samsung unknown 64Mb",  NAND_MFR_SAMSUNG, 0x76, 26, 0, 3, 0x4000, 0},
+	{"Samsung KM29W32000",    NAND_MFR_SAMSUNG, 0xe3, 22, 0, 2, 0x2000, 0},
+	{"Samsung unknown 4Mb",   NAND_MFR_SAMSUNG, 0xe5, 22, 0, 2, 0x2000, 0},
+	{"Samsung KM29U64000",    NAND_MFR_SAMSUNG, 0xe6, 23, 0, 2, 0x2000, 0},
+	{"Samsung KM29W16000",    NAND_MFR_SAMSUNG, 0xea, 21, 1, 2, 0x1000, 0},
+	{"Samsung K9F5616Q0C",    NAND_MFR_SAMSUNG, 0x45, 25, 0, 2, 0x4000, 1},
+	{"Samsung K9K1216Q0C",    NAND_MFR_SAMSUNG, 0x46, 26, 0, 3, 0x4000, 1},
+	{0,}
+};
+#endif
+#define MLC 1
+#define SLC 0
+#define WD8 0
+struct WMT_nand_id{
+	unsigned int id;
+	unsigned int id1;
+	unsigned short pageSize;
+	unsigned short oobSize;
+	unsigned short pageCnt;
+	unsigned short eccMode;
+};
+struct WMT_nand_id id_table[] = {
+	{0xADD7949A, 0x74420000,  8192, 448, 256, 24},//"H27UBG8T2ATR"},     
+	{0xADD5949A, 0x74420000,  8192, 448, 256, 24},//"H27UAG8T2BTR-BC"},  
+	{0xADD794DA, 0x74C30000,  8192, 640, 256, 24},//"H27UBG8T2BTR"},     
+	{0xADD79491, 0x00000000,  8192, 640, 256, 40},//"H27UBG8T2CTR-F20"}, 
+	{0xADDE94DA, 0x00000000,  8192, 640, 256, 40},//"H27UCG8T2ATR-F20"}, 
+	{0xADDE94EB, 0x74440000, 16384,1280, 256, 40},//"H27UCG8T2BTR-F20"}, 
+	//Samsung
+	{0xECD58472, 0x00000000,  8192, 436, 128, 24},//"K9GAG08U0E"},
+	{0xECD7947A, 0x54430000,  8192, 448, 128, 24},//"K9GBG08U0A"},
+	{0xECD59476, 0x00000000,  8192, 448, 128, 24},//"K9GAG08U0F"},
+	{0xECD7947E, 0x64440000,  8192,1024, 128, 40},//"K9GBG08U0B"},
+	{0xECDED57A, 0x58430000,  8192, 640, 128, 24},//"K9LCG08U0A"},
+	{0xECDED57E, 0x68440000,  8192,1024, 128, 40},//"K9LCG08U0B"},
+	//Toshiba               
+	{0x98D59432, 0x00000000,  8192, 448, 128, 24},//"TC58NVG4D2FTA00"},
+	{0x98D58432, 0x72560000,  8192, 640, 128, 40},//"TC58NVG4D2HTA00"},
+	{0x98DE8493, 0x72570000, 16384,1280, 256, 40},//"TC58NVG6DCJTA00"},
+	{0x98D79432, 0x76550000,  8192, 448, 128, 24},//"TC58NVG5D2FTAI0"},
+	{0x98D79432, 0x76560000,  8192, 640, 128, 40},//"TC58NVG5D2HTA00"},
+	{0x98D78493, 0x72570000, 16384,1280, 256, 40},//"TC58TEG5DCJTA00"},
+	{0x98DE9493, 0x76500000, 16384,1280, 256, 40},//"TC58TEG6DDKTA00"},
+	//Miron                 
+	{0x2C88044B, 0x00000000,  8192, 448, 256, 24},//"MT29F64G08CBAAA"},
+	{0x2C88044B, 0x00000000,  8192, 448, 256, 24},//"MT29F128G08CFAAA"}
+	{0x2C68044A, 0x00000000,  4096, 224, 256, 12},//"MT29F32G08CBACA"},
+	{0x2C64444B, 0xA9000000,  8192, 744, 256, 40},//"MT29F64G08CBABA"},
+	{0x2C44444B, 0xA9000000,  8192, 744, 256, 40},//"MT29F32G08CBADA"},
+	//Sandisk               
+	{0x45DE9493, 0x76570000, 16384,1280, 256, 40},//"SDTNQGAMA-008G"},
+	{0x45D78493, 0x72570000, 16384,1280, 256, 40},//"SDTNQFAMA-004G"},
+	//Intel                 
+	{0x8988244B, 0xA9000000,  8192, 448, 256, 24},//JS29F64G08AAME1"
+//{0x8988244B, 0xA9840000,  8192, 744, 256, 40},//JS29F64G08AAMF1"
+	{0}
+};
+
+
+static struct WMT_nand_flash_dev WMT_nand_flash_ids[] = {
+	//Hynix
+	{0xADD314A5, 4096, 2048,  64, 0x40000, 5, 125, 127, 0, WD8, 1, 0, 1, MLC,  4, 0x140A0C46, 0x64780046, 0, 0, 0, 0x00000000, 0x00000000, "HY27UT088G2M-T(P)"},
+	{0xADF1801D, 1024, 2048,  64, 0x20000, 4,   0,   1, 0, WD8, 4, 0, 1, SLC,  4, 0x140A0F64, 0x64780064, 0, 0, 0, 0x00000000, 0x00000000, "HY27UF081G2A"},
+	{0xADF1001D, 1024, 2048,  64, 0x20000, 4,   0,   1, 0, WD8, 4, 0, 1, SLC,  4, 0x140A0C46, 0x64780046, 0, 0, 0, 0x00000000, 0x00000000, "H27U1G8F2BFR"},
+	{0xADD59425, 4096, 4096, 218, 0x80000, 5, 125, 127, 0, WD8, 1, 0, 1, MLC, 12, 0x140A0F64, 0x64780064, 0, 0, 0, 0x00000000, 0x00000000, "HY27UAG8T2A"},
+	{0xADD7949A, 2048, 8192, 448,0x200000, 5,   0, 255, 0, WD8, 1, 0, 1, MLC, 24, 0x140A0C64, 0x64500064, 0, 0, 0, 0x74420000, 0x00000000, "H27UBG8T2ATR"},
+	{0xADD5949A, 1024, 8192, 448,0x200000, 5,   0, 255, 0, WD8, 1, 0, 1, MLC, 24, 0x140A0C64, 0x64640064, 0, 0, 0, 0x74420000, 0x00000000, "H27UAG8T2BTR-BC"},
+	{0xADD794DA, 2048, 8192, 640,0x200000, 5,   0, 255, 0, WD8, 1, 0, 1, MLC, 24, 0x10080AC8, 0x645000C8, 0, 1, 1, 0x74C30000, 0x00000000, "H27UBG8T2BTR"},
+	{0xADD79491, 2048, 8192, 640,0x200000, 5,   0, 255, 0, WD8, 1, 0, 1, MLC, 40, 0x100608C8, 0x647800C8, 0, 1, 1, 0x60440000, 0x00003FFF, "H27UBG8T2CTR-F20"},
+	{0xADDE94DA, 4096, 8192, 640,0x200000, 5,   0, 255, 0, WD8, 1, 0, 1, MLC, 40, 0x100608C8, 0x647800C8, 1, 1, 1, 0x74c40000, 0x00003FFF, "H27UCG8T2ATR-F20"},
+	{0xADDE94EB, 2048,16384,1280,0x400000, 5,   0, 255, 0, WD8, 1, 0, 1, MLC, 40, 0x100608C8, 0x647800C8, 0, 1, 1, 0x74440000, 0x00003FFF, "H27UCG8T2BTR-F20"},
+	//Samsung
+	{0xECD314A5, 4096, 2048,  64, 0x40000, 5, 127,   0, 0, WD8, 1, 0, 1, MLC,  4, 0x140A0C64, 0x64400064, 0, 0, 0, 0x00000000, 0x00000000, "K9G8G08X0A"},
+	{0xECD59429, 4096, 4096, 218, 0x80000, 5, 127,   0, 0, WD8, 1, 0, 1, MLC, 12, 0x140A0F64, 0x64400064, 0, 0, 0, 0x00000000, 0x00000000, "K9GAG08UXD"},
+	{0xECF10095, 1024, 2048,  64, 0x20000, 4,   0,   1, 0, WD8, 4, 0, 1, SLC,  4, 0x140a1464, 0x64400064, 0, 0, 0, 0x00000000, 0x00000000, "K9F1G08U0B"},
+	{0xECD514B6, 4096, 4096, 128, 0x80000, 5, 127,   0, 0, WD8, 1, 0, 1, MLC,  4, 0x140A0C64, 0x64400064, 0, 0, 0, 0x00000000, 0x00000000, "K9GAG08U0M"},
+	{0xECD755B6, 8192, 4096, 128, 0x80000, 5, 127,   0, 0, WD8, 1, 0, 1, MLC,  4, 0x140A0C64, 0x64400064, 0, 0, 0, 0x00000000, 0x00000000, "K9LBG08U0M"},
+	{0xECD58472, 2048, 8192, 436,0x100000, 5,   0, 127, 0, WD8, 1, 0, 1, MLC, 24, 0x140A0FFF, 0x6440012C, 0, 0, 0, 0x00000000, 0x00000000, "K9GAG08U0E"},
+	{0xECD7947A, 4096, 8192, 448,0x100000, 5,   0, 127, 0, WD8, 1, 0, 1, MLC, 24, 0x140A0FFF, 0x6478012C, 0, 0, 1, 0x54430000, 0x00003FFF, "K9GBG08U0A"},
+	{0xECD59476, 2048, 8192, 448,0x100000, 5,   0, 127, 0, WD8, 1, 0, 1, MLC, 24, 0x140A0CFF, 0x6478012C, 0, 0, 0, 0x00000000, 0x00000000, "K9GAG08U0F"},
+	{0xECD7947E, 4096, 8192,1024,0x100000, 5,   0, 127, 0, WD8, 1, 0, 1, MLC, 40, 0x140B0BFF, 0x6478012C, 0, 1, 1, 0x64440000, 0x00000000, "K9GBG08U0B"},
+	{0xECDED57A, 8192, 8192, 640,0x100000, 5,   0, 127, 0, WD8, 1, 0, 1, MLC, 24, 0x140A0CFF, 0x6478012C, 0, 0, 1, 0x58430000, 0x00000000, "K9LCG08U0A"},
+	{0xECDED57E, 8192, 8192,1024,0x100000, 5,   0, 127, 0, WD8, 1, 0, 1, MLC, 40, 0x140B0CFF, 0x6478012C, 0, 1, 1, 0x68440000, 0x00000000, "K9LCG08U0B"},
+	//Toshiba
+	{0x98D594BA, 4096, 4096, 218, 0x80000, 5,   0, 127, 0, WD8, 1, 0, 1, MLC, 12, 0x190F0F70, 0x64b40070, 0, 0, 0, 0x00000000, 0x00000000, "TC58NVG4D1DTG0"},
+	{0x98D19015, 1024, 2048,  64, 0x20000, 4,   0,   1, 0, WD8, 4, 0, 1, SLC,  4, 0x140A0C11, 0x64B40011, 0, 0, 0, 0x00000000, 0x00000000, "TC58NVG0S3ETA00"},
+	{0x98D59432, 2048, 8192, 448,0x100000, 5,   0, 127, 0, WD8, 1, 0, 1, MLC, 24, 0x140A0C84, 0x64B40084, 0, 0, 0, 0x76550000, 0x00000000, "TC58NVG4D2FTA00"},
+	{0x98D58432, 2048, 8192, 640,0x100000, 5,   0, 127, 0, WD8, 1, 0, 1, MLC, 40, 0x190A0FFF, 0x64B4012C, 0, 1, 1, 0x72560000, 0x00000000, "TC58NVG4D2HTA00"},
+	{0x98DE8493, 2048,16384,1280,0x400000, 5,   0, 255, 0, WD8, 1, 0, 1, MLC, 40, 0x10070AFF, 0x64B4012C, 0, 1, 1, 0x72570000, 0x00000000, "TC58NVG6DCJTA00"},
+	{0x98DE8493, 2048,16384,1280,0x400000, 5,   0, 255, 0, WD8, 1, 0, 1, MLC, 40, 0x10070AFF, 0x64B4012C, 2, 1, 1, 0x72D70000, 0x00000000, "TC58NVG6DCJTA00-DDR"},
+	{0x98D79432, 4096, 8192, 448,0x100000, 5,   0, 127, 0, WD8, 1, 0, 1, MLC, 24, 0x140A0C78, 0x64FF0078, 0, 0, 0, 0x76550000, 0x00000000, "TC58NVG5D2FTAI0"},
+	{0x98D79432, 4096, 8192, 640,0x100000, 5,   0, 127, 0, WD8, 1, 0, 1, MLC, 40, 0x10070AFF, 0x64B4012C, 0, 1, 1, 0x76560000, 0x00000000, "TC58NVG5D2HTA00"},
+	{0x98D78493, 1024,16384,1280,0x400000, 5,   0, 255, 0, WD8, 1, 0, 1, MLC, 40, 0x10070AFF, 0x6478012C, 0, 1, 1, 0x72570000, 0x00000000, "TC58TEG5DCJTA00"},
+	{0x98DE9493, 2048,16384,1280,0x400000, 5,   0, 255, 0, WD8, 1, 0, 1, MLC, 40, 0x14070A12, 0x6478012C, 1, 1, 1, 0x76570000, 0x00000000, "TC58TEG6DDKTA00"},
+	{0x98D78493, 1024,16384,1280,0x400000, 5,   0, 255, 0, WD8, 1, 0, 1, MLC, 40, 0x10070A12, 0x6478012C, 1, 1, 1, 0x72500000, 0x00000000, "TC58TEG5DCKTA00"},
+	//Miron
+	{0x2C88044B, 4096, 8192, 448,0x200000, 5,   0, 255, 0, WD8, 1, 0, 1, MLC, 24, 0x321E32C8, 0x647800C8, 0, 0, 0, 0xA9000000, 0x00000000, "MT29F64G08CBAAA"},
+	{0x2C88044B, 4096, 8192, 448,0x200000, 5,   0, 255, 0, WD8, 1, 0, 1, MLC, 24, 0x321E32C8, 0x647800C8, 0, 0, 0, 0xA9000000, 0x00000000, "MT29F128G08CFAAA"},
+	{0x2C48044A, 2048, 4096, 224,0x100000, 5,   0,   1, 0, WD8, 1, 0, 1, MLC, 12, 0x321E32C8, 0x647800C8, 0, 0, 0, 0xA5000000, 0x00003FFF, "MT29F16G08CBACA"},
+	{0x2C68044A, 4096, 4096, 224,0x100000, 5,   0,   1, 0, WD8, 1, 0, 1, MLC, 12, 0x321E32C8, 0x647800C8, 0, 0, 0, 0xA9000000, 0x00003FFF, "MT29F32G08CBACA"},
+	{0x2C64444B, 4096, 8192, 744,0x200000, 5,   0,   1, 0, WD8, 1, 0, 1, MLC, 40, 0x321E32C8, 0x647800C8, 0, 1, 0, 0xA9000000, 0x00000000, "MT29F64G08CBABA"},
+	{0x2C44444B, 2048, 8192, 744,0x200000, 5,   0,   1, 0, WD8, 1, 0, 1, MLC, 40, 0x321E32C8, 0x647800C8, 0, 1, 0, 0xA9000000, 0x00000000, "MT29F32G08CBADA"},
+	//Sandisk
+	{0x45DE9493, 2048,16384,1280,0x400000, 5,   0,   1, 0, WD8, 1, 0, 1, MLC, 40, 0x10070AFF, 0x64B4012C, 1, 1, 1, 0x76570000, 0x00003FFF, "SDTNQGAMA-008G"},
+	{0x45D78493, 1024,16384,1280,0x400000, 5,   0,   1, 0, WD8, 1, 0, 1, MLC, 40, 0x10070AFF, 0x64B4012C, 1, 1, 1, 0x72570000, 0x00000000, "SDTNQFAMA-004G"},
+	//Intel
+	{0x8968044A, 4096, 4096, 224,0x100000, 5,   0,   1, 0, WD8, 1, 0, 1, MLC, 12, 0x321E32C8, 0x647800C8, 0, 0, 0, 0xA9000000, 0x00003FFF, "JS29F32G08AAME1"},
+	{0x8988244B, 4096, 8192, 448,0x200000, 5,   0,   1, 0, WD8, 1, 0, 1, MLC, 24, 0x10070A46, 0x64400046, 0, 0, 0, 0xA9000000, 0x00000000, "JS29F64G08AAME1"},
+	{0x8988244B, 4096, 8192, 744,0x200000, 5,   0,   1, 0, WD8, 1, 0, 1, MLC, 40, 0x10070A46, 0x64B40046, 0, 0, 0, 0xA9840000, 0x00000000, "JS29F64G08AAMF1"},
+	//Mxic
+	{0xC2F1801D, 1024, 2048,  64, 0x20000, 4,   0,   1, 0, WD8, 4, 0, 1, SLC,  4, 0x140A0F64, 0x64400064, 0, 0, 0, 0x00000000, 0x00000000, "MX30LF1G08AA"},
+	//Mira
+	{0x92F18095, 1024, 2048,  64, 0x20000, 4,   0,   1, 0, WD8, 4, 0, 1, SLC,  4, 0x140A0C64, 0x64400064, 0, 0, 0, 0x40000000, 0x00000000, "PSU1GA(3/4)0HT"},
+	{0,}
+	/*add new product item here.*/
+};
+/* Nand Product Table          We take HYNIX_NF_HY27UF081G2A for example.
+struct WMT_nand_flash_dev{
+ DWORD dwFlashID;            //composed by 4 bytes of ID. For example:0xADF1801D
+ DWORD dwBlockCount;      //block count of one chip. For example: 1024
+ DWORD dwPageSize;       //page size. For example:2048(other value can be 512 or 4096)
+ DWORD dwSpareSize;       //spare area size. For example:16(almost all kinds of nand is 16)
+ DWORD dwBlockSize;       //block size = dwPageSize * PageCntPerBlock. For example:131072
+ DWORD dwAddressCycle;      //address cycle 4 or 5
+ DWORD dwBI0Position;      //BI0 page postion in block
+ DWORD dwBI1Position;      //BI1 page postion in block
+ DWORD dwBIOffset;       //BI offset in page 0 or 2048
+ DWORD dwDataWidth;      //data with X8 = 0 or X16 = 1
+ DWORD dwPageProgramLimit;     //chip can program PAGE_PROGRAM_LIMIT times within the same page
+ DWORD dwSeqRowReadSupport;    //whether support sequential row read, 1 = support, 0 = not support
+ DWORD dwSeqPageProgram;     //chip need sequential page program in a block. 1 = need
+ DWORD dwNandType;       //MLC = 1 or SLC = 0
+ DWORD dwECCBitNum;      //ECC bit number needed
+ DWORD dwRWTimming;     //NFC Read/Write Pulse width and Read/Write hold time. default =0x12121010
+ DWORD dwTadl;      		//NFC write TADL timeing config
+ DWORD dwDDR;      		  //NFC support toshia ddr(toggle) mode = 1 not support = 0
+ DWORD dwRetry;    		  //NFC Read Retry support = 1 no
+ DWORD dwRdmz; 			//NFC Randomizer support = 1,
+ DWORD dwFlashID2;      //composed by additional 2 bytes of ID from original 4 bytes.
+ char ProductName[MAX_PRODUCT_NAME_LENGTH]; //product name. for example "HYNIX_NF_HY27UF081G2A"
+};
+*/
+
+int hynix_set_parameter(struct nand_chip *nand, int mode, int def_mode);
+int hynix_get_parameter(struct nand_chip *nand, int mode);
+int hynix_get_otp(struct nand_chip *nand);
+int toshiba_get_parameter(struct nand_chip *nand, int mode);
+int toshiba_set_parameter(struct nand_chip *nand, int mode, int def);
+int samsung_get_parameter(struct nand_chip *nand, int mode);
+int samsung_set_parameter(struct nand_chip *nand, int mode, int def_mode);
+int sandisk_get_parameter(struct nand_chip *nand, int mode);
+int sandisk_set_parameter(struct nand_chip *nand, int total_try_times, int def_value);
+int micron_get_parameter(struct nand_chip *nand, int mode);
+int micron_set_parameter(struct nand_chip *nand, int mode, int def_mode);
+struct nand_read_retry_param chip_table[] = {
+	//Hynix
+	{
+		.magic = "readretry", 
+		.nand_id = 0xADD794DA,
+		.nand_id_5th = 0x74C30000,
+		.eslc_reg_num = 5, 
+		.eslc_offset = {0xa0, 0xa1, 0xb0, 0xb1, 0xc9},
+		.eslc_set_value = {0x26, 0x26, 0x26, 0x26, 0x1}, 
+		.retry_reg_num = 4,
+		.retry_offset = {0xa7, 0xad, 0xae, 0xaf},
+		.retry_value = {0, 0x6,0xa, 0x6, 0x0, 0x3, 0x7, 0x8, 0, 0x6, 0xd, 0xf, 0x0, 0x9, 0x14, 0x17, 0x0, 0x0, 0x1a, 0x1e, 0x0, 0x0, 0x20, 0x25}, 
+		.total_try_times = 6, 
+		.cur_try_times = -1,
+		.set_parameter = hynix_set_parameter, 
+		.get_parameter = hynix_get_parameter,
+	},
+	{
+		.magic = "readretry", 
+		.nand_id = 0xADDE94DA, 
+		.nand_id_5th = 0x74c40000,
+		.eslc_reg_num = 4, 
+		.eslc_offset = {0xb0, 0xb1, 0xa0, 0xa1}, 
+		.eslc_set_value = {0xa, 0xa, 0xa, 0xa}, 
+		.retry_reg_num = 8, 
+		.retry_offset = {0xcc, 0xbf, 0xaa, 0xab, 0xcd, 0xad, 0xae, 0xaf}, 
+		.otp_len = 2,
+		.otp_offset = {0xff, 0xcc},
+		.otp_data = {0x40, 0x4d},
+		.total_try_times = 7, 
+		.cur_try_times = -1, 
+		.set_parameter = hynix_set_parameter, 
+		.get_parameter = hynix_get_parameter, 
+		.get_otp_table = hynix_get_otp, 
+	},
+	{
+		.magic = "readretry", 
+		.nand_id = 0xADDE94EB, 
+		.nand_id_5th = 0x74440000,
+		.eslc_reg_num = 4, 
+		.eslc_offset = {0xa0, 0xa1, 0xa7, 0xa8}, 
+		.eslc_set_value = {0xa, 0xa, 0xa, 0xa}, 
+		.retry_reg_num = 8, 
+		.retry_offset = {0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7}, 
+		.otp_len = 2,
+		.otp_offset = {0xae, 0xb0},
+		.otp_data = {0x00, 0x4d},
+		.total_try_times = 7, 
+		.cur_try_times = -1, 
+		.set_parameter = hynix_set_parameter, 
+		.get_parameter = hynix_get_parameter, 
+		.get_otp_table = hynix_get_otp, 
+	},
+	{
+		.magic = "readretry", 
+		.nand_id = 0xADD79491, 
+		.nand_id_5th = 0x60440000,
+		.eslc_reg_num = 4, 
+		.eslc_offset = {0xa0, 0xa1, 0xa7, 0xa8}, 
+		.eslc_set_value = {0xa, 0xa, 0xa, 0xa}, 
+		.retry_reg_num = 8, 
+		.retry_offset = {0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7}, 
+		.otp_len = 2,
+		.otp_offset = {0xae, 0xb0},
+		.otp_data = {0x00, 0x4d},
+		.total_try_times = 7, 
+		.cur_try_times = -1, 
+		.set_parameter = hynix_set_parameter, 
+		.get_parameter = hynix_get_parameter, 
+		.get_otp_table = hynix_get_otp, 
+	},
+	//Toshiba
+	{
+		.magic = "readretry", 
+		.nand_id = 0x98D58432, 
+		.nand_id_5th = 0x72560000,
+		.retry_reg_num = 4, 
+		.retry_offset = {4, 5, 6, 7},
+		.retry_value = {0, 0, 0, 0, 4, 4, 4, 4, 0x7c, 0x7c, 0x7c, 0x7c, 0x78, 0x78, 0x78, 0x78, 0x74, 0x74, 0x74, 0x74, 0x8, 0x8, 0x8, 0x8},
+		.total_try_times = 6,
+		.cur_try_times = 0,
+		.set_parameter = toshiba_set_parameter,
+		.get_parameter = toshiba_get_parameter,
+	},
+	{	//TC58NVG6DCJTA00
+		.magic = "readretry", 
+		.nand_id = 0x98DE8493,
+		.nand_id_5th = 0x72570000,
+		.retry_reg_num = 4, 
+		.retry_offset = {4, 5, 6, 7},
+		.retry_value = {0, 0, 0, 0, 4, 4, 4, 4, 0x7c, 0x7c, 0x7c, 0x7c, 0x78, 0x78, 0x78, 0x78, 0x74, 0x74, 0x74, 0x74, 0x8, 0x8, 0x8, 0x8},
+		.total_try_times = 6,
+		.cur_try_times = 0,
+		.set_parameter = toshiba_set_parameter,
+		.get_parameter = toshiba_get_parameter,
+	},
+	{	//TC58NVG6DCJTA00-DDR
+		.magic = "readretry", 
+		.nand_id = 0x98DE8493,
+		.nand_id_5th = 0x72D70000,
+		.retry_reg_num = 4, 
+		.retry_offset = {4, 5, 6, 7},
+		.retry_value = {0, 0, 0, 0, 4, 4, 4, 4, 0x7c, 0x7c, 0x7c, 0x7c, 0x78, 0x78, 0x78, 0x78, 0x74, 0x74, 0x74, 0x74, 0x8, 0x8, 0x8, 0x8},
+		.total_try_times = 6,
+		.cur_try_times = 0,
+		.set_parameter = toshiba_set_parameter,
+		.get_parameter = toshiba_get_parameter,
+	},
+	{
+		.magic = "readretry", 
+		.nand_id = 0x98DE9482, 
+		.nand_id_5th = 0x72570000,
+		.retry_reg_num = 4, 
+		.retry_offset = {4, 5, 6, 7},
+		.retry_value = {0, 0, 0, 0, 4, 4, 4, 4, 0x7c, 0x7c, 0x7c, 0x7c, 0x78, 0x78, 0x78, 0x78, 0x74, 0x74, 0x74, 0x74, 0x8, 0x8, 0x8, 0x8}, 
+		.total_try_times = 6, 
+		.cur_try_times = 0, 
+		.set_parameter = toshiba_set_parameter, 
+		.get_parameter = toshiba_get_parameter,
+	},
+	{
+		.magic = "readretry", 
+		.nand_id = 0x98D79432, 
+		.nand_id_5th = 0x76560000,
+		.retry_reg_num = 4, 
+		.retry_offset = {4, 5, 6, 7},
+		.retry_value = {0, 0, 0, 0, 4, 4, 4, 4, 0x7c, 0x7c, 0x7c, 0x7c, 0x78, 0x78, 0x78, 0x78, 0x74, 0x74, 0x74, 0x74, 0x8, 0x8, 0x8, 0x8},
+		.total_try_times = 6,
+		.cur_try_times = 0,
+		.set_parameter = toshiba_set_parameter,
+		.get_parameter = toshiba_get_parameter,
+	},
+	{
+		.magic = "readretry", 
+		.nand_id = 0x98D78493, 
+		.nand_id_5th = 0x72570000,
+		.retry_reg_num = 4, 
+		.retry_offset = {4, 5, 6, 7},
+		.retry_value = {0, 0, 0, 0, 4, 4, 4, 4, 0x7c, 0x7c, 0x7c, 0x7c, 0x78, 0x78, 0x78, 0x78, 0x74, 0x74, 0x74, 0x74, 0x8, 0x8, 0x8, 0x8},
+		.total_try_times = 6,
+		.cur_try_times = 0,
+		.set_parameter = toshiba_set_parameter,
+		.get_parameter = toshiba_get_parameter,
+	},
+	{
+		.magic = "readretry", 
+		.nand_id = 0x98D78493, 
+		.nand_id_5th = 0x72500000,
+		.retry_reg_num = 4, 
+		.retry_offset = {4, 5, 6, 7},
+		.retry_value = {0, 0, 0, 0, 4, 4, 4, 4, 0x7c, 0x7c, 0x7c, 0x7c, 0x78, 0x78, 0x78, 0x78, 0x74, 0x74, 0x74, 0x74, 0x8, 0x8, 0x8, 0x8},
+		.total_try_times = 6,
+		.cur_try_times = 0,
+		.set_parameter = toshiba_set_parameter,
+		.get_parameter = toshiba_get_parameter,
+	},
+	{
+		.magic = "readretry", 
+		.nand_id = 0x98DE9493, 
+		.nand_id_5th = 0x76570000,
+		.retry_reg_num = 4, 
+		.retry_offset = {4, 5, 6, 7},
+		.retry_value = {0, 0, 0, 0, 4, 4, 4, 4, 0x7c, 0x7c, 0x7c, 0x7c, 0x78, 0x78, 0x78, 0x78, 0x74, 0x74, 0x74, 0x74, 0x8, 0x8, 0x8, 0x8},
+		.total_try_times = 6,
+		.cur_try_times = 0,
+		.set_parameter = toshiba_set_parameter,
+		.get_parameter = toshiba_get_parameter,
+	},
+
+	//samsung
+	{
+		.magic = "readretry", 
+		.nand_id = 0xECD7947E, 
+		.nand_id_5th = 0x64440000,
+		.retry_reg_num = 4,
+		.retry_offset = {0xA7, 0xA4, 0xA5, 0xA6},
+		.retry_def_value = {0, 0, 0, 0},
+		.retry_value = {5, 0xA, 0, 0, 0x28, 0, 0xEC, 0xD8, 0xED, 0xF5, 0xED, 0xE6, 0xA, 0xF, 5, 0,
+										0xF, 0xA, 0xFB, 0xEC, 0xE8, 0xEF, 0xE8, 0xDC, 0xF1, 0xFB, 0xFE, 0xF0, 0xA, 0x0, 0xFB, 0xEC,
+										0xD0, 0xE2, 0xD0, 0xC2, 0x14, 0xF, 0xFB, 0xEC, 0xE8, 0xFB, 0xE8, 0xDC, 0x1E, 0x14, 0xFB, 0xEC,
+										0xFB, 0xFF, 0xFB, 0xF8, 0x7, 0xC, 0x2, 0},
+		.total_try_times = 14,
+		.cur_try_times = 0,
+		.set_parameter = samsung_set_parameter,
+		.get_parameter = samsung_get_parameter,
+	},
+	{
+		.magic = "readretry", 
+		.nand_id = 0xECDED57E, 
+		.nand_id_5th = 0x68440000,
+		.retry_reg_num = 4,
+		.retry_offset = {0xA7, 0xA4, 0xA5, 0xA6},
+		.retry_def_value = {0, 0, 0, 0},
+		.retry_value = {5, 0xA, 0, 0, 0x28, 0, 0xEC, 0xD8, 0xED, 0xF5, 0xED, 0xE6, 0xA, 0xF, 5, 0,
+										0xF, 0xA, 0xFB, 0xEC, 0xE8, 0xEF, 0xE8, 0xDC, 0xF1, 0xFB, 0xFE, 0xF0, 0xA, 0x0, 0xFB, 0xEC,
+										0xD0, 0xE2, 0xD0, 0xC2, 0x14, 0xF, 0xFB, 0xEC, 0xE8, 0xFB, 0xE8, 0xDC, 0x1E, 0x14, 0xFB, 0xEC,
+										0xFB, 0xFF, 0xFB, 0xF8, 0x7, 0xC, 0x2, 0},
+		.total_try_times = 14,
+		.cur_try_times = 0,
+		.set_parameter = samsung_set_parameter,
+		.get_parameter = samsung_get_parameter,
+	},
+	//Sandisk
+	{
+		.magic = "readretry", 
+		.nand_id = 0x45DE9493, 
+		.nand_id_5th = 0x76570000,
+		.retry_reg_num = 3, 
+		.retry_offset = {4, 5, 7},
+		.retry_def_value = {0, 0, 0, 0xFF, 0xFF},
+		.retry_value = {0xF0, 0, 0xF0, 0xE0, 0, 0xE0, 0xD0, 0, 0xD0, 0x10, 0, 0x10, 0x20, 0, 0x20, 0x30, 0, 0x30,
+										0xC0, 0, 0xD0, 0x00, 0, 0x10, 0x00, 0, 0x20, 0x10, 0, 0x20, 0xB0, 0, 0xD0, 0xA0, 0, 0xD0,
+										0x90, 0, 0xD0, 0xB0, 0, 0xC0, 0xA0, 0, 0xC0, 0x90, 0, 0xC0,//lower page retry parameter
+										0x00, 0xF0, 0, 0x0F, 0xE0, 0, 0x0F, 0xD0, 0, 0x0E, 0xE0, 0, 0x0E, 0xD0, 0, 0x0D, 0xF0, 0,
+										0x0D, 0xE0, 0, 0x0D, 0xD0, 0, 0x01, 0x10, 0, 0x02, 0x20, 0, 0x02, 0x10, 0, 0x03, 0x20, 0,
+										0x0F, 0x00, 0, 0x0E, 0xF0, 0, 0x0D, 0xC0, 0, 0x0F, 0xF0, 0, 0x01, 0x00, 0, 0x02, 0x00, 0,
+										0x0D, 0xB0, 0, 0x0C, 0xA0, 0},//upper page retry parameter
+		.otp_len = 9,
+		.otp_offset = {0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC},
+		.otp_data = {0, 0, 0, 0, 0, 0, 0, 0, 0},
+		.total_try_times = 0x1410,//bit15~8 for upper page, bit7~0 for lower page
+		.cur_try_times = -1,
+		.set_parameter = sandisk_set_parameter,
+		.get_parameter = sandisk_get_parameter,
+	},
+	{
+		.magic = "readretry",
+		.nand_id = 0x45D78493,
+		.nand_id_5th = 0x72570000,
+		.retry_reg_num = 3,
+		.retry_offset = {4, 5, 7},
+		.retry_def_value = {0, 0, 0, 0xFF, 0xFF},
+		.retry_value = {0xF0, 0, 0xF0, 0xE0, 0, 0xE0, 0xD0, 0, 0xD0, 0x10, 0, 0x10, 0x20, 0, 0x20, 0x30, 0, 0x30,
+										0xC0, 0, 0xD0, 0x00, 0, 0x10, 0x00, 0, 0x20, 0x10, 0, 0x20, 0xB0, 0, 0xD0, 0xA0, 0, 0xD0,
+										0x90, 0, 0xD0, 0xB0, 0, 0xC0, 0xA0, 0, 0xC0, 0x90, 0, 0xC0,//lower page retry parameter
+										0x00, 0xF0, 0, 0x0F, 0xE0, 0, 0x0F, 0xD0, 0, 0x0E, 0xE0, 0, 0x0E, 0xD0, 0, 0x0D, 0xF0, 0,
+										0x0D, 0xE0, 0, 0x0D, 0xD0, 0, 0x01, 0x10, 0, 0x02, 0x20, 0, 0x02, 0x10, 0, 0x03, 0x20, 0,
+										0x0F, 0x00, 0, 0x0E, 0xF0, 0, 0x0D, 0xC0, 0, 0x0F, 0xF0, 0, 0x01, 0x00, 0, 0x02, 0x00, 0,
+										0x0D, 0xB0, 0, 0x0C, 0xA0, 0},//upper page retry parameter
+		.otp_len = 9,
+		.otp_offset = {0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC},
+		.otp_data = {0, 0, 0, 0, 0, 0, 0, 0, 0},
+		.total_try_times = 0x1410,//bit15~8 for upper page, bit7~0 for lower page
+		.cur_try_times = -1,
+		.set_parameter = sandisk_set_parameter,
+		.get_parameter = sandisk_get_parameter,
+	},
+	
+	//Micron
+	{
+		.magic = "readretry", 
+		.nand_id = 0x2C64444B, 
+		.nand_id_5th = 0xA9000000,
+		.retry_reg_num = 1, 
+		.retry_offset = {0x89},
+		.retry_def_value = {0},
+		.retry_value = {1, 2, 3, 4, 5, 6, 7},
+		.total_try_times = 7,
+		.cur_try_times = 0,
+		.set_parameter = micron_set_parameter,
+		.get_parameter = micron_get_parameter,
+	},
+	{
+		.magic = "readretry", 
+		.nand_id = 0x2C44444B, 
+		.nand_id_5th = 0xA9000000,
+		.retry_reg_num = 1, 
+		.retry_offset = {0x89},
+		.retry_def_value = {0},
+		.retry_value = {1, 2, 3, 4, 5, 6, 7},
+		.total_try_times = 7,
+		.cur_try_times = 0,
+		.set_parameter = micron_set_parameter,
+		.get_parameter = micron_get_parameter,
+		.retry = 0,
+	},
+
+	{
+		.nand_id = 0,
+		.nand_id_5th = 0,
+	}
+};  
+#endif /* __LINUX_MTD_NAND_IDS_H */
diff --git a/include/linux/mtd/nftl.h b/include/linux/mtd/nftl.h
new file mode 100755
index 0000000..4381306
--- /dev/null
+++ b/include/linux/mtd/nftl.h
@@ -0,0 +1,105 @@
+
+/* Defines for NAND Flash Translation Layer  */
+/* (c) 1999 Machine Vision Holdings, Inc.    */
+/* Author: David Woodhouse <dwmw2@mvhi.com>  */
+/* $Id: nftl.h,v 1.10 2000/12/29 00:25:38 dwmw2 Exp $ */
+
+#ifndef __MTD_NFTL_H__
+#define __MTD_NFTL_H__
+
+/* Block Control Information */
+
+struct nftl_bci {
+	unsigned char ECCSig[6];
+	__u8 Status;
+	__u8 Status1;
+}__attribute__((packed));
+
+/* Unit Control Information */
+
+struct nftl_uci0 {
+	__u16 VirtUnitNum;
+	__u16 ReplUnitNum;
+	__u16 SpareVirtUnitNum;
+	__u16 SpareReplUnitNum;
+} __attribute__((packed));
+
+struct nftl_uci1 {
+	__u32 WearInfo;
+	__u16 EraseMark;
+	__u16 EraseMark1;
+} __attribute__((packed));
+
+struct nftl_uci2 {
+	__u16 FoldMark;
+	__u16 FoldMark1;
+	__u32 unused;
+} __attribute__((packed));
+
+union nftl_uci {
+	struct nftl_uci0 a;
+	struct nftl_uci1 b;
+	struct nftl_uci2 c;
+};
+
+struct nftl_oob {
+	struct nftl_bci b;
+	union nftl_uci u;
+};
+
+/* NFTL Media Header */
+
+struct NFTLMediaHeader {
+	char DataOrgID[6];
+	__u16 NumEraseUnits;
+	__u16 FirstPhysicalEUN;
+	__u32 FormattedSize;
+	unsigned char UnitSizeFactor;
+} __attribute__((packed));
+
+#define MAX_ERASE_ZONES (8192 - 512)
+
+#define ERASE_MARK 0x3c69
+#define SECTOR_FREE 0xff
+#define SECTOR_USED 0x55
+#define SECTOR_IGNORE 0x11
+#define SECTOR_DELETED 0x00
+
+#define FOLD_MARK_IN_PROGRESS 0x5555
+
+#define ZONE_GOOD 0xff
+#define ZONE_BAD_ORIGINAL 0
+#define ZONE_BAD_MARKED 7
+
+/* these info are used in ReplUnitTable */
+#define BLOCK_NIL          0xffff /* last block of a chain */
+#define BLOCK_FREE         0xfffe /* free block */
+#define BLOCK_NOTEXPLORED  0xfffd /* non explored block, only used during mounting */
+#define BLOCK_RESERVED     0xfffc /* bios block or bad block */
+
+struct NFTLrecord {
+	struct DiskOnChip *mtd;
+	__u16 MediaUnit, SpareMediaUnit;
+	__u32 EraseSize;
+	struct NFTLMediaHeader MediaHdr;
+	int usecount;
+	unsigned char heads;
+	unsigned char sectors;
+	unsigned short cylinders;
+	__u16 numvunits;
+	__u16 lastEUN;                  /* should be suppressed */
+	__u16 numfreeEUNs;
+	__u16 LastFreeEUN; 		/* To speed up finding a free EUN */
+	__u32 nr_sects;
+	int head,sect,cyl;
+	__u16 *EUNtable; 		/* [numvunits]: First EUN for each virtual unit  */
+	__u16 *ReplUnitTable; 		/* [numEUNs]: ReplUnitNumber for each */
+	unsigned int nb_blocks;		/* number of physical blocks */
+	unsigned int nb_boot_blocks;	/* number of blocks used by the bios */
+};
+
+#define MAX_NFTLS 16
+#define MAX_SECTORS_PER_UNIT 32
+#define NFTL_PARTN_BITS 4
+
+#endif /* __MTD_NFTL_H__ */
diff --git a/include/linux/mtd/ubi.h b/include/linux/mtd/ubi.h
new file mode 100755
index 0000000..4b3e06c
--- /dev/null
+++ b/include/linux/mtd/ubi.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) International Business Machines Corp., 2006
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ * the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Author: Artem Bityutskiy (Битюцкий �ртём)
+ */
+
+#ifndef __LINUX_UBI_H__
+#define __LINUX_UBI_H__
+
+/* #include <asm/ioctl.h> */
+#include <linux/types.h>
+#include <mtd/ubi-user.h>
+
+/*
+ * enum ubi_open_mode - UBI volume open mode constants.
+ *
+ * UBI_READONLY: read-only mode
+ * UBI_READWRITE: read-write mode
+ * UBI_EXCLUSIVE: exclusive mode
+ */
+enum {
+	UBI_READONLY = 1,
+	UBI_READWRITE,
+	UBI_EXCLUSIVE
+};
+
+/**
+ * struct ubi_volume_info - UBI volume description data structure.
+ * @vol_id: volume ID
+ * @ubi_num: UBI device number this volume belongs to
+ * @size: how many physical eraseblocks are reserved for this volume
+ * @used_bytes: how many bytes of data this volume contains
+ * @used_ebs: how many physical eraseblocks of this volume actually contain any
+ * data
+ * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME)
+ * @corrupted: non-zero if the volume is corrupted (static volumes only)
+ * @upd_marker: non-zero if the volume has update marker set
+ * @alignment: volume alignment
+ * @usable_leb_size: how many bytes are available in logical eraseblocks of
+ * this volume
+ * @name_len: volume name length
+ * @name: volume name
+ * @cdev: UBI volume character device major and minor numbers
+ *
+ * The @corrupted flag is only relevant to static volumes and is always zero
+ * for dynamic ones. This is because UBI does not care about dynamic volume
+ * data protection and only cares about protecting static volume data.
+ *
+ * The @upd_marker flag is set if the volume update operation was interrupted.
+ * Before touching the volume data during the update operation, UBI first sets
+ * the update marker flag for this volume. If the volume update operation was
+ * further interrupted, the update marker indicates this. If the update marker
+ * is set, the contents of the volume is certainly damaged and a new volume
+ * update operation has to be started.
+ *
+ * To put it differently, @corrupted and @upd_marker fields have different
+ * semantics:
+ *     o the @corrupted flag means that this static volume is corrupted for some
+ *       reasons, but not because an interrupted volume update
+ *     o the @upd_marker field means that the volume is damaged because of an
+ *       interrupted update operation.
+ *
+ * I.e., the @corrupted flag is never set if the @upd_marker flag is set.
+ *
+ * The @used_bytes and @used_ebs fields are only really needed for static
+ * volumes and contain the number of bytes stored in this static volume and how
+ * many eraseblock this data occupies. In case of dynamic volumes, the
+ * @used_bytes field is equivalent to @size*@usable_leb_size, and the @used_ebs
+ * field is equivalent to @size.
+ *
+ * In general, logical eraseblock size is a property of the UBI device, not
+ * of the UBI volume. Indeed, the logical eraseblock size depends on the
+ * physical eraseblock size and on how much bytes UBI headers consume. But
+ * because of the volume alignment (@alignment), the usable size of logical
+ * eraseblocks if a volume may be less. The following equation is true:
+ * 	@usable_leb_size = LEB size - (LEB size mod @alignment),
+ * where LEB size is the logical eraseblock size defined by the UBI device.
+ *
+ * The alignment is multiple to the minimal flash input/output unit size or %1
+ * if all the available space is used.
+ *
+ * To put this differently, alignment may be considered is a way to change
+ * volume logical eraseblock sizes.
+ */
+struct ubi_volume_info {
+	int ubi_num;
+	int vol_id;
+	int size;
+	long long used_bytes;
+	int used_ebs;
+	int vol_type;
+	int corrupted;
+	int upd_marker;
+	int alignment;
+	int usable_leb_size;
+	int name_len;
+	const char *name;
+	dev_t cdev;
+};
+
+/**
+ * struct ubi_device_info - UBI device description data structure.
+ * @ubi_num: ubi device number
+ * @leb_size: logical eraseblock size on this UBI device
+ * @min_io_size: minimal I/O unit size
+ * @ro_mode: if this device is in read-only mode
+ * @cdev: UBI character device major and minor numbers
+ *
+ * Note, @leb_size is the logical eraseblock size offered by the UBI device.
+ * Volumes of this UBI device may have smaller logical eraseblock size if their
+ * alignment is not equivalent to %1.
+ */
+struct ubi_device_info {
+	int ubi_num;
+	int leb_size;
+	int min_io_size;
+	int ro_mode;
+	dev_t cdev;
+};
+
+/* UBI descriptor given to users when they open UBI volumes */
+struct ubi_volume_desc;
+
+int ubi_get_device_info(int ubi_num, struct ubi_device_info *di);
+void ubi_get_volume_info(struct ubi_volume_desc *desc,
+			 struct ubi_volume_info *vi);
+struct ubi_volume_desc *ubi_open_volume(int ubi_num, int vol_id, int mode);
+struct ubi_volume_desc *ubi_open_volume_nm(int ubi_num, const char *name,
+					   int mode);
+void ubi_close_volume(struct ubi_volume_desc *desc);
+int ubi_leb_read(struct ubi_volume_desc *desc, int lnum, char *buf, int offset,
+		 int len, int check);
+int ubi_leb_write(struct ubi_volume_desc *desc, int lnum, const void *buf,
+		  int offset, int len, int dtype);
+int ubi_leb_change(struct ubi_volume_desc *desc, int lnum, const void *buf,
+		   int len, int dtype);
+int ubi_leb_erase(struct ubi_volume_desc *desc, int lnum);
+int ubi_leb_unmap(struct ubi_volume_desc *desc, int lnum);
+int ubi_leb_map(struct ubi_volume_desc *desc, int lnum, int dtype);
+int ubi_is_mapped(struct ubi_volume_desc *desc, int lnum);
+
+/*
+ * This function is the same as the 'ubi_leb_read()' function, but it does not
+ * provide the checking capability.
+ */
+static inline int ubi_read(struct ubi_volume_desc *desc, int lnum, char *buf,
+			   int offset, int len)
+{
+	return ubi_leb_read(desc, lnum, buf, offset, len, 0);
+}
+
+/*
+ * This function is the same as the 'ubi_leb_write()' functions, but it does
+ * not have the data type argument.
+ */
+static inline int ubi_write(struct ubi_volume_desc *desc, int lnum,
+			    const void *buf, int offset, int len)
+{
+	return ubi_leb_write(desc, lnum, buf, offset, len, UBI_UNKNOWN);
+}
+
+/*
+ * This function is the same as the 'ubi_leb_change()' functions, but it does
+ * not have the data type argument.
+ */
+static inline int ubi_change(struct ubi_volume_desc *desc, int lnum,
+				    const void *buf, int len)
+{
+	return ubi_leb_change(desc, lnum, buf, len, UBI_UNKNOWN);
+}
+
+#endif /* !__LINUX_UBI_H__ */
diff --git a/include/linux/posix_types.h b/include/linux/posix_types.h
new file mode 100755
index 0000000..bd37e1f
--- /dev/null
+++ b/include/linux/posix_types.h
@@ -0,0 +1,48 @@
+#ifndef _LINUX_POSIX_TYPES_H
+#define _LINUX_POSIX_TYPES_H
+
+#include <linux/stddef.h>
+
+/*
+ * This allows for 1024 file descriptors: if NR_OPEN is ever grown
+ * beyond that you'll have to change this too. But 1024 fd's seem to be
+ * enough even for such "real" unices like OSF/1, so hopefully this is
+ * one limit that doesn't have to be changed [again].
+ *
+ * Note that POSIX wants the FD_CLEAR(fd,fdsetp) defines to be in
+ * <sys/time.h> (and thus <linux/time.h>) - but this is a more logical
+ * place for them. Solved by having dummy defines in <sys/time.h>.
+ */
+
+/*
+ * Those macros may have been defined in <gnu/types.h>. But we always
+ * use the ones here.
+ */
+#undef __NFDBITS
+#define __NFDBITS	(8 * sizeof(unsigned long))
+
+#undef __FD_SETSIZE
+#define __FD_SETSIZE	1024
+
+#undef __FDSET_LONGS
+#define __FDSET_LONGS	(__FD_SETSIZE/__NFDBITS)
+
+#undef __FDELT
+#define	__FDELT(d)	((d) / __NFDBITS)
+
+#undef __FDMASK
+#define	__FDMASK(d)	(1UL << ((d) % __NFDBITS))
+
+typedef struct {
+	unsigned long fds_bits [__FDSET_LONGS];
+} __kernel_fd_set;
+
+/* Type of a signal handler.  */
+typedef void (*__kernel_sighandler_t)(int);
+
+/* Type of a SYSV IPC key.  */
+typedef int __kernel_key_t;
+
+#include <asm/posix_types.h>
+
+#endif /* _LINUX_POSIX_TYPES_H */
diff --git a/include/linux/rbtree.h b/include/linux/rbtree.h
new file mode 100755
index 0000000..6ff28e0
--- /dev/null
+++ b/include/linux/rbtree.h
@@ -0,0 +1,160 @@
+/*
+  Red Black Trees
+  (C) 1999  Andrea Arcangeli <andrea@suse.de>
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; if not, write to the Free Software
+  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+  linux/include/linux/rbtree.h
+
+  To use rbtrees you'll have to implement your own insert and search cores.
+  This will avoid us to use callbacks and to drop drammatically performances.
+  I know it's not the cleaner way,  but in C (not in C++) to get
+  performances and genericity...
+
+  Some example of insert and search follows here. The search is a plain
+  normal search over an ordered tree. The insert instead must be implemented
+  int two steps: as first thing the code must insert the element in
+  order as a red leaf in the tree, then the support library function
+  rb_insert_color() must be called. Such function will do the
+  not trivial work to rebalance the rbtree if necessary.
+
+-----------------------------------------------------------------------
+static inline struct page * rb_search_page_cache(struct inode * inode,
+						 unsigned long offset)
+{
+	struct rb_node * n = inode->i_rb_page_cache.rb_node;
+	struct page * page;
+
+	while (n)
+	{
+		page = rb_entry(n, struct page, rb_page_cache);
+
+		if (offset < page->offset)
+			n = n->rb_left;
+		else if (offset > page->offset)
+			n = n->rb_right;
+		else
+			return page;
+	}
+	return NULL;
+}
+
+static inline struct page * __rb_insert_page_cache(struct inode * inode,
+						   unsigned long offset,
+						   struct rb_node * node)
+{
+	struct rb_node ** p = &inode->i_rb_page_cache.rb_node;
+	struct rb_node * parent = NULL;
+	struct page * page;
+
+	while (*p)
+	{
+		parent = *p;
+		page = rb_entry(parent, struct page, rb_page_cache);
+
+		if (offset < page->offset)
+			p = &(*p)->rb_left;
+		else if (offset > page->offset)
+			p = &(*p)->rb_right;
+		else
+			return page;
+	}
+
+	rb_link_node(node, parent, p);
+
+	return NULL;
+}
+
+static inline struct page * rb_insert_page_cache(struct inode * inode,
+						 unsigned long offset,
+						 struct rb_node * node)
+{
+	struct page * ret;
+	if ((ret = __rb_insert_page_cache(inode, offset, node)))
+		goto out;
+	rb_insert_color(node, &inode->i_rb_page_cache);
+ out:
+	return ret;
+}
+-----------------------------------------------------------------------
+*/
+
+#ifndef	_LINUX_RBTREE_H
+#define	_LINUX_RBTREE_H
+
+#include <linux/stddef.h>
+
+struct rb_node
+{
+	unsigned long  rb_parent_color;
+#define	RB_RED		0
+#define	RB_BLACK	1
+	struct rb_node *rb_right;
+	struct rb_node *rb_left;
+} __attribute__((aligned(sizeof(long))));
+    /* The alignment might seem pointless, but allegedly CRIS needs it */
+
+struct rb_root
+{
+	struct rb_node *rb_node;
+};
+
+
+#define rb_parent(r)   ((struct rb_node *)((r)->rb_parent_color & ~3))
+#define rb_color(r)   ((r)->rb_parent_color & 1)
+#define rb_is_red(r)   (!rb_color(r))
+#define rb_is_black(r) rb_color(r)
+#define rb_set_red(r)  do { (r)->rb_parent_color &= ~1; } while (0)
+#define rb_set_black(r)  do { (r)->rb_parent_color |= 1; } while (0)
+
+static inline void rb_set_parent(struct rb_node *rb, struct rb_node *p)
+{
+	rb->rb_parent_color = (rb->rb_parent_color & 3) | (unsigned long)p;
+}
+static inline void rb_set_color(struct rb_node *rb, int color)
+{
+	rb->rb_parent_color = (rb->rb_parent_color & ~1) | color;
+}
+
+#define RB_ROOT	(struct rb_root) { NULL, }
+#define	rb_entry(ptr, type, member) container_of(ptr, type, member)
+
+#define RB_EMPTY_ROOT(root)	((root)->rb_node == NULL)
+#define RB_EMPTY_NODE(node)	(rb_parent(node) == node)
+#define RB_CLEAR_NODE(node)	(rb_set_parent(node, node))
+
+extern void rb_insert_color(struct rb_node *, struct rb_root *);
+extern void rb_erase(struct rb_node *, struct rb_root *);
+
+/* Find logical next and previous nodes in a tree */
+extern struct rb_node *rb_next(struct rb_node *);
+extern struct rb_node *rb_prev(struct rb_node *);
+extern struct rb_node *rb_first(struct rb_root *);
+extern struct rb_node *rb_last(struct rb_root *);
+
+/* Fast replacement of a single node without remove/rebalance/add/rebalance */
+extern void rb_replace_node(struct rb_node *victim, struct rb_node *new,
+			    struct rb_root *root);
+
+static inline void rb_link_node(struct rb_node * node, struct rb_node * parent,
+				struct rb_node ** rb_link)
+{
+	node->rb_parent_color = (unsigned long )parent;
+	node->rb_left = node->rb_right = NULL;
+
+	*rb_link = node;
+}
+
+#endif	/* _LINUX_RBTREE_H */
diff --git a/include/linux/rsa/asn1.h b/include/linux/rsa/asn1.h
new file mode 100755
index 0000000..20ced91
--- /dev/null
+++ b/include/linux/rsa/asn1.h
@@ -0,0 +1,244 @@
+/**
+ * \file asn1.h
+ *
+ * \brief Generic ASN.1 parsing
+ *
+ *  Copyright (C) 2006-2011, Brainspark B.V.
+ *
+ *  This file is part of PolarSSL (http://www.polarssl.org)
+ *  Lead Maintainer: Paul Bakker <polarssl_maintainer at polarssl.org>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef POLARSSL_ASN1_H
+#define POLARSSL_ASN1_H
+
+//#include "config.h"
+
+//#if defined(POLARSSL_BIGNUM_C)
+#include "bignum.h"
+//#endif
+
+//#include <string.h>
+
+/** 
+ * \addtogroup asn1_module
+ * \{ 
+ */
+ 
+/**
+ * \name ASN1 Error codes
+ * These error codes are OR'ed to X509 error codes for
+ * higher error granularity. 
+ * ASN1 is a standard to specify data structures.
+ * \{
+ */
+#define POLARSSL_ERR_ASN1_OUT_OF_DATA                      -0x0014  /**< Out of data when parsing an ASN1 data structure. */
+#define POLARSSL_ERR_ASN1_UNEXPECTED_TAG                   -0x0016  /**< ASN1 tag was of an unexpected value. */
+#define POLARSSL_ERR_ASN1_INVALID_LENGTH                   -0x0018  /**< Error when trying to determine the length or invalid length. */
+#define POLARSSL_ERR_ASN1_LENGTH_MISMATCH                  -0x001A  /**< Actual length differs from expected length. */
+#define POLARSSL_ERR_ASN1_INVALID_DATA                     -0x001C  /**< Data is invalid. (not used) */
+#define POLARSSL_ERR_ASN1_MALLOC_FAILED                    -0x001E  /**< Memory allocation failed */
+/* \} name */
+
+/**
+ * \name DER constants
+ * These constants comply with DER encoded the ANS1 type tags.
+ * DER encoding uses hexadecimal representation.
+ * An example DER sequence is:\n
+ * - 0x02 -- tag indicating INTEGER
+ * - 0x01 -- length in octets
+ * - 0x05 -- value
+ * Such sequences are typically read into \c ::x509_buf.
+ * \{
+ */
+#define ASN1_BOOLEAN                 0x01
+#define ASN1_INTEGER                 0x02
+#define ASN1_BIT_STRING              0x03
+#define ASN1_OCTET_STRING            0x04
+#define ASN1_NULL                    0x05
+#define ASN1_OID                     0x06
+#define ASN1_UTF8_STRING             0x0C
+#define ASN1_SEQUENCE                0x10
+#define ASN1_SET                     0x11
+#define ASN1_PRINTABLE_STRING        0x13
+#define ASN1_T61_STRING              0x14
+#define ASN1_IA5_STRING              0x16
+#define ASN1_UTC_TIME                0x17
+#define ASN1_GENERALIZED_TIME        0x18
+#define ASN1_UNIVERSAL_STRING        0x1C
+#define ASN1_BMP_STRING              0x1E
+#define ASN1_PRIMITIVE               0x00
+#define ASN1_CONSTRUCTED             0x20
+#define ASN1_CONTEXT_SPECIFIC        0x80
+/* \} name */
+/* \} addtogroup asn1_module */
+
+/** Returns the size of the binary string, without the trailing \\0 */
+#define OID_SIZE(x) (sizeof(x) - 1)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Functions to parse ASN.1 data structures
+ * \{
+ */
+
+/**
+ * Type-length-value structure that allows for ASN1 using DER.
+ */
+typedef struct _asn1_buf
+{
+    int tag;                /**< ASN1 type, e.g. ASN1_UTF8_STRING. */
+    size_t len;             /**< ASN1 length, e.g. in octets. */
+    unsigned char *p;       /**< ASN1 data, e.g. in ASCII. */
+}
+asn1_buf;
+
+/**
+ * Container for ASN1 bit strings.
+ */
+typedef struct _asn1_bitstring
+{
+    size_t len;                 /**< ASN1 length, e.g. in octets. */
+    unsigned char unused_bits;  /**< Number of unused bits at the end of the string */
+    unsigned char *p;           /**< Raw ASN1 data for the bit string */
+}
+asn1_bitstring;
+
+/**
+ * Container for a sequence of ASN.1 items
+ */
+typedef struct _asn1_sequence
+{
+    asn1_buf buf;                   /**< Buffer containing the given ASN.1 item. */
+    struct _asn1_sequence *next;    /**< The next entry in the sequence. */
+}
+asn1_sequence;
+
+/**
+ * Get the length of an ASN.1 element.
+ * Updates the pointer to immediately behind the length.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param len   The variable that will receive the value
+ *
+ * \return      0 if successful, POLARSSL_ERR_ASN1_OUT_OF_DATA on reaching
+ *              end of data, POLARSSL_ERR_ASN1_INVALID_LENGTH if length is
+ *              unparseable.
+ */
+int asn1_get_len( unsigned char **p,
+                  const unsigned char *end,
+                  size_t *len );
+
+/**
+ * Get the tag and length of the tag. Check for the requested tag.
+ * Updates the pointer to immediately behind the tag and length.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param len   The variable that will receive the length
+ * \param tag   The expected tag
+ *
+ * \return      0 if successful, POLARSSL_ERR_ASN1_UNEXPECTED_TAG if tag did
+ *              not match requested tag, or another specific ASN.1 error code.
+ */
+int asn1_get_tag( unsigned char **p,
+                  const unsigned char *end,
+                  size_t *len, int tag );
+
+/**
+ * Retrieve a boolean ASN.1 tag and its value.
+ * Updates the pointer to immediately behind the full tag.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param val   The variable that will receive the value
+ *
+ * \return      0 if successful or a specific ASN.1 error code.
+ */
+int asn1_get_bool( unsigned char **p,
+                   const unsigned char *end,
+                   int *val );
+
+/**
+ * Retrieve an integer ASN.1 tag and its value.
+ * Updates the pointer to immediately behind the full tag.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param val   The variable that will receive the value
+ *
+ * \return      0 if successful or a specific ASN.1 error code.
+ */
+int asn1_get_int( unsigned char **p,
+                  const unsigned char *end,
+                  int *val );
+
+/**
+ * Retrieve a bitstring ASN.1 tag and its value.
+ * Updates the pointer to immediately behind the full tag.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param bs    The variable that will receive the value
+ *
+ * \return      0 if successful or a specific ASN.1 error code.
+ */
+int asn1_get_bitstring( unsigned char **p, const unsigned char *end,
+                        asn1_bitstring *bs);
+
+/**
+ * Parses and splits an ASN.1 "SEQUENCE OF <tag>"
+ * Updated the pointer to immediately behind the full sequence tag.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param cur   First variable in the chain to fill
+ * \param tag   Type of sequence
+ *
+ * \return      0 if successful or a specific ASN.1 error code.
+ */
+int asn1_get_sequence_of( unsigned char **p,
+                          const unsigned char *end,
+                          asn1_sequence *cur,
+                          int tag);
+
+#if defined(POLARSSL_BIGNUM_C)
+/**
+ * Retrieve a MPI value from an integer ASN.1 tag.
+ * Updates the pointer to immediately behind the full tag.
+ *
+ * \param p     The position in the ASN.1 data
+ * \param end   End of data
+ * \param X     The MPI that will receive the value
+ *
+ * \return      0 if successful or a specific ASN.1 or MPI error code.
+ */
+int asn1_get_mpi( unsigned char **p,
+                  const unsigned char *end,
+                  mpi *X );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* asn1.h */
diff --git a/include/linux/rsa/base64.h b/include/linux/rsa/base64.h
new file mode 100755
index 0000000..355116d
--- /dev/null
+++ b/include/linux/rsa/base64.h
@@ -0,0 +1,87 @@
+/**
+ * \file base64.h
+ *
+ * \brief RFC 1521 base64 encoding/decoding
+ *
+ *  Copyright (C) 2006-2010, Brainspark B.V.
+ *
+ *  This file is part of PolarSSL (http://www.polarssl.org)
+ *  Lead Maintainer: Paul Bakker <polarssl_maintainer at polarssl.org>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef POLARSSL_BASE64_H
+#define POLARSSL_BASE64_H
+
+//#include <string.h>
+
+#define POLARSSL_ERR_BASE64_BUFFER_TOO_SMALL               -0x002A  /**< Output buffer too small. */
+#define POLARSSL_ERR_BASE64_INVALID_CHARACTER              -0x002C  /**< Invalid character in input. */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Encode a buffer into base64 format
+ *
+ * \param dst      destination buffer
+ * \param dlen     size of the buffer
+ * \param src      source buffer
+ * \param slen     amount of data to be encoded
+ *
+ * \return         0 if successful, or POLARSSL_ERR_BASE64_BUFFER_TOO_SMALL.
+ *                 *dlen is always updated to reflect the amount
+ *                 of data that has (or would have) been written.
+ *
+ * \note           Call this function with *dlen = 0 to obtain the
+ *                 required buffer size in *dlen
+ */
+int base64_encode( unsigned char *dst, size_t *dlen,
+                   const unsigned char *src, size_t slen );
+
+/**
+ * \brief          Decode a base64-formatted buffer
+ *
+ * \param dst      destination buffer
+ * \param dlen     size of the buffer
+ * \param src      source buffer
+ * \param slen     amount of data to be decoded
+ *
+ * \return         0 if successful, POLARSSL_ERR_BASE64_BUFFER_TOO_SMALL, or
+ *                 POLARSSL_ERR_BASE64_INVALID_DATA if the input data is not
+ *                 correct. *dlen is always updated to reflect the amount
+ *                 of data that has (or would have) been written.
+ *
+ * \note           Call this function with *dlen = 0 to obtain the
+ *                 required buffer size in *dlen
+ */
+int base64_decode( unsigned char *dst, size_t *dlen,
+                   const unsigned char *src, size_t slen );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int base64_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* base64.h */
diff --git a/include/linux/rsa/bignum.h b/include/linux/rsa/bignum.h
new file mode 100755
index 0000000..3b4d19c
--- /dev/null
+++ b/include/linux/rsa/bignum.h
@@ -0,0 +1,763 @@
+/**
+ * \file bignum.h
+ *
+ * \brief  Multi-precision integer library
+ *
+ *  Copyright (C) 2006-2010, Brainspark B.V.
+ *
+ *  This file is part of PolarSSL (http://www.polarssl.org)
+ *  Lead Maintainer: Paul Bakker <polarssl_maintainer at polarssl.org>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef POLARSSL_BIGNUM_H
+#define POLARSSL_BIGNUM_H
+
+//#include <common.h>
+//#include <command.h>
+#include <asm/io.h>
+
+//#include <stdio.h>
+//#include <string.h>
+
+//#include "config.h"
+
+#define POLARSSL_ERR_MPI_FILE_IO_ERROR                     -0x0002  /**< An error occurred while reading from or writing to a file. */
+#define POLARSSL_ERR_MPI_BAD_INPUT_DATA                    -0x0004  /**< Bad input parameters to function. */
+#define POLARSSL_ERR_MPI_INVALID_CHARACTER                 -0x0006  /**< There is an invalid character in the digit string. */
+#define POLARSSL_ERR_MPI_BUFFER_TOO_SMALL                  -0x0008  /**< The buffer is too small to write to. */
+#define POLARSSL_ERR_MPI_NEGATIVE_VALUE                    -0x000A  /**< The input arguments are negative or result in illegal output. */
+#define POLARSSL_ERR_MPI_DIVISION_BY_ZERO                  -0x000C  /**< The input argument for division is zero, which is not allowed. */
+#define POLARSSL_ERR_MPI_NOT_ACCEPTABLE                    -0x000E  /**< The input arguments are not acceptable. */
+#define POLARSSL_ERR_MPI_MALLOC_FAILED                     -0x0010  /**< Memory allocation failed. */
+
+#define MPI_CHK(f) if( ( ret = f ) != 0 ) goto cleanup
+
+/*
+ * Maximum size MPIs are allowed to grow to in number of limbs.
+ */
+#define POLARSSL_MPI_MAX_LIMBS                             10000
+
+/*
+ * Maximum window size used for modular exponentiation. Default: 6
+ * Minimum value: 1. Maximum value: 6.
+ *
+ * Result is an array of ( 2 << POLARSSL_MPI_WINDOW_SIZE ) MPIs used
+ * for the sliding window calculation. (So 64 by default)
+ *
+ * Reduction in size, reduces speed.
+ */
+#define POLARSSL_MPI_WINDOW_SIZE                           6        /**< Maximum windows size used. */
+
+/*
+ * Maximum size of MPIs allowed in bits and bytes for user-MPIs.
+ * ( Default: 512 bytes => 4096 bits )
+ *
+ * Note: Calculations can results temporarily in larger MPIs. So the number
+ * of limbs required (POLARSSL_MPI_MAX_LIMBS) is higher.
+ */
+#define POLARSSL_MPI_MAX_SIZE                              512      /**< Maximum number of bytes for usable MPIs. */
+#define POLARSSL_MPI_MAX_BITS                              ( 8 * POLARSSL_MPI_MAX_SIZE )    /**< Maximum number of bits for usable MPIs. */
+
+/*
+ * When reading from files with mpi_read_file() the buffer should have space
+ * for a (short) label, the MPI (in the provided radix), the newline
+ * characters and the '\0'.
+ *
+ * By default we assume at least a 10 char label, a minimum radix of 10
+ * (decimal) and a maximum of 4096 bit numbers (1234 decimal chars).
+ */
+#define POLARSSL_MPI_READ_BUFFER_SIZE                       1250   
+
+/*
+ * Define the base integer type, architecture-wise
+ */
+#if defined(POLARSSL_HAVE_INT8)
+typedef   signed char  t_sint;
+typedef unsigned char  t_uint;
+typedef unsigned short t_udbl;
+#else
+#if defined(POLARSSL_HAVE_INT16)
+typedef   signed short t_sint;
+typedef unsigned short t_uint;
+typedef unsigned long  t_udbl;
+#else
+  typedef   signed long t_sint;
+  typedef unsigned long t_uint;
+  #if defined(_MSC_VER) && defined(_M_IX86)
+  typedef unsigned __int64 t_udbl;
+  #else
+    #if defined(__GNUC__) && (                          \
+        defined(__amd64__) || defined(__x86_64__)    || \
+        defined(__ppc64__) || defined(__powerpc64__) || \
+        defined(__ia64__)  || defined(__alpha__)     || \
+        (defined(__sparc__) && defined(__arch64__))  || \
+        defined(__s390x__) )
+    typedef unsigned int t_udbl __attribute__((mode(TI)));
+    #define POLARSSL_HAVE_LONGLONG
+    #else
+      #if defined(POLARSSL_HAVE_LONGLONG)
+      typedef unsigned long long t_udbl;
+      #endif
+    #endif
+  #endif
+#endif
+#endif
+
+/**
+ * \brief          MPI structure
+ */
+typedef struct
+{
+    int s;              /*!<  integer sign      */
+    size_t n;           /*!<  total # of limbs  */
+    t_uint *p;          /*!<  pointer to limbs  */
+}
+mpi;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief           Initialize one MPI
+ *
+ * \param X         One MPI to initialize.
+ */
+void mpi_init( mpi *X );
+
+/**
+ * \brief          Unallocate one MPI
+ *
+ * \param X        One MPI to unallocate.
+ */
+void mpi_free( mpi *X );
+
+/**
+ * \brief          Enlarge to the specified number of limbs
+ *
+ * \param X        MPI to grow
+ * \param nblimbs  The target number of limbs
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_grow( mpi *X, size_t nblimbs );
+
+/**
+ * \brief          Copy the contents of Y into X
+ *
+ * \param X        Destination MPI
+ * \param Y        Source MPI
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_copy( mpi *X, const mpi *Y );
+
+/**
+ * \brief          Swap the contents of X and Y
+ *
+ * \param X        First MPI value
+ * \param Y        Second MPI value
+ */
+void mpi_swap( mpi *X, mpi *Y );
+
+/**
+ * \brief          Set value from integer
+ *
+ * \param X        MPI to set
+ * \param z        Value to use
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_lset( mpi *X, t_sint z );
+
+/*
+ * \brief          Get a specific bit from X
+ *
+ * \param X        MPI to use
+ * \param pos      Zero-based index of the bit in X
+ *
+ * \return         Either a 0 or a 1
+ */
+int mpi_get_bit( mpi *X, size_t pos );
+
+/*
+ * \brief          Set a bit of X to a specific value of 0 or 1
+ *
+ * \note           Will grow X if necessary to set a bit to 1 in a not yet
+ *                 existing limb. Will not grow if bit should be set to 0
+ *
+ * \param X        MPI to use
+ * \param pos      Zero-based index of the bit in X
+ * \param val      The value to set the bit to (0 or 1)
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed,
+ *                 POLARSSL_ERR_MPI_BAD_INPUT_DATA if val is not 0 or 1
+ */
+int mpi_set_bit( mpi *X, size_t pos, unsigned char val );
+
+/**
+ * \brief          Return the number of least significant bits
+ *
+ * \param X        MPI to use
+ */
+size_t mpi_lsb( const mpi *X );
+
+/**
+ * \brief          Return the number of most significant bits
+ *
+ * \param X        MPI to use
+ */
+size_t mpi_msb( const mpi *X );
+
+/**
+ * \brief          Return the total size in bytes
+ *
+ * \param X        MPI to use
+ */
+size_t mpi_size( const mpi *X );
+
+/**
+ * \brief          Import from an ASCII string
+ *
+ * \param X        Destination MPI
+ * \param radix    Input numeric base
+ * \param s        Null-terminated string buffer
+ *
+ * \return         0 if successful, or a POLARSSL_ERR_MPI_XXX error code
+ */
+int mpi_read_string( mpi *X, int radix, const char *s );
+
+/**
+ * \brief          Export into an ASCII string
+ *
+ * \param X        Source MPI
+ * \param radix    Output numeric base
+ * \param s        String buffer
+ * \param slen     String buffer size
+ *
+ * \return         0 if successful, or a POLARSSL_ERR_MPI_XXX error code.
+ *                 *slen is always updated to reflect the amount
+ *                 of data that has (or would have) been written.
+ *
+ * \note           Call this function with *slen = 0 to obtain the
+ *                 minimum required buffer size in *slen.
+ */
+int mpi_write_string( const mpi *X, int radix, char *s, size_t *slen );
+
+/**
+ * \brief          Read X from an opened file
+ *
+ * \param X        Destination MPI
+ * \param radix    Input numeric base
+ * \param fin      Input file handle
+ *
+ * \return         0 if successful, POLARSSL_ERR_MPI_BUFFER_TOO_SMALL if
+ *                 the file read buffer is too small or a
+ *                 POLARSSL_ERR_MPI_XXX error code
+ */
+//int mpi_read_file( mpi *X, int radix, FILE *fin );
+
+/**
+ * \brief          Write X into an opened file, or stdout if fout is NULL
+ *
+ * \param p        Prefix, can be NULL
+ * \param X        Source MPI
+ * \param radix    Output numeric base
+ * \param fout     Output file handle (can be NULL)
+ *
+ * \return         0 if successful, or a POLARSSL_ERR_MPI_XXX error code
+ *
+ * \note           Set fout == NULL to print X on the console.
+ */
+//int mpi_write_file( const char *p, const mpi *X, int radix, FILE *fout );
+
+/**
+ * \brief          Import X from unsigned binary data, big endian
+ *
+ * \param X        Destination MPI
+ * \param buf      Input buffer
+ * \param buflen   Input buffer size
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_read_binary( mpi *X, const unsigned char *buf, size_t buflen );
+
+/**
+ * \brief          Export X into unsigned binary data, big endian
+ *
+ * \param X        Source MPI
+ * \param buf      Output buffer
+ * \param buflen   Output buffer size
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_BUFFER_TOO_SMALL if buf isn't large enough
+ */
+int mpi_write_binary( const mpi *X, unsigned char *buf, size_t buflen );
+
+/**
+ * \brief          Left-shift: X <<= count
+ *
+ * \param X        MPI to shift
+ * \param count    Amount to shift
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_shift_l( mpi *X, size_t count );
+
+/**
+ * \brief          Right-shift: X >>= count
+ *
+ * \param X        MPI to shift
+ * \param count    Amount to shift
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_shift_r( mpi *X, size_t count );
+
+/**
+ * \brief          Compare unsigned values
+ *
+ * \param X        Left-hand MPI
+ * \param Y        Right-hand MPI
+ *
+ * \return         1 if |X| is greater than |Y|,
+ *                -1 if |X| is lesser  than |Y| or
+ *                 0 if |X| is equal to |Y|
+ */
+int mpi_cmp_abs( const mpi *X, const mpi *Y );
+
+/**
+ * \brief          Compare signed values
+ *
+ * \param X        Left-hand MPI
+ * \param Y        Right-hand MPI
+ *
+ * \return         1 if X is greater than Y,
+ *                -1 if X is lesser  than Y or
+ *                 0 if X is equal to Y
+ */
+int mpi_cmp_mpi( const mpi *X, const mpi *Y );
+
+/**
+ * \brief          Compare signed values
+ *
+ * \param X        Left-hand MPI
+ * \param z        The integer value to compare to
+ *
+ * \return         1 if X is greater than z,
+ *                -1 if X is lesser  than z or
+ *                 0 if X is equal to z
+ */
+int mpi_cmp_int( const mpi *X, t_sint z );
+
+/**
+ * \brief          Unsigned addition: X = |A| + |B|
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_add_abs( mpi *X, const mpi *A, const mpi *B );
+
+/**
+ * \brief          Unsigned substraction: X = |A| - |B|
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_NEGATIVE_VALUE if B is greater than A
+ */
+int mpi_sub_abs( mpi *X, const mpi *A, const mpi *B );
+
+/**
+ * \brief          Signed addition: X = A + B
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_add_mpi( mpi *X, const mpi *A, const mpi *B );
+
+/**
+ * \brief          Signed substraction: X = A - B
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_sub_mpi( mpi *X, const mpi *A, const mpi *B );
+
+/**
+ * \brief          Signed addition: X = A + b
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param b        The integer value to add
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_add_int( mpi *X, const mpi *A, t_sint b );
+
+/**
+ * \brief          Signed substraction: X = A - b
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param b        The integer value to subtract
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_sub_int( mpi *X, const mpi *A, t_sint b );
+
+/**
+ * \brief          Baseline multiplication: X = A * B
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_mul_mpi( mpi *X, const mpi *A, const mpi *B );
+
+/**
+ * \brief          Baseline multiplication: X = A * b
+ *                 Note: b is an unsigned integer type, thus
+ *                 Negative values of b are ignored.
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param b        The integer value to multiply with
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_mul_int( mpi *X, const mpi *A, t_sint b );
+
+/**
+ * \brief          Division by mpi: A = Q * B + R
+ *
+ * \param Q        Destination MPI for the quotient
+ * \param R        Destination MPI for the rest value
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed,
+ *                 POLARSSL_ERR_MPI_DIVISION_BY_ZERO if B == 0
+ *
+ * \note           Either Q or R can be NULL.
+ */
+int mpi_div_mpi( mpi *Q, mpi *R, const mpi *A, const mpi *B );
+
+/**
+ * \brief          Division by int: A = Q * b + R
+ *
+ * \param Q        Destination MPI for the quotient
+ * \param R        Destination MPI for the rest value
+ * \param A        Left-hand MPI
+ * \param b        Integer to divide by
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed,
+ *                 POLARSSL_ERR_MPI_DIVISION_BY_ZERO if b == 0
+ *
+ * \note           Either Q or R can be NULL.
+ */
+int mpi_div_int( mpi *Q, mpi *R, const mpi *A, t_sint b );
+
+/**
+ * \brief          Modulo: R = A mod B
+ *
+ * \param R        Destination MPI for the rest value
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed,
+ *                 POLARSSL_ERR_MPI_DIVISION_BY_ZERO if B == 0,
+ *                 POLARSSL_ERR_MPI_NEGATIVE_VALUE if B < 0
+ */
+int mpi_mod_mpi( mpi *R, const mpi *A, const mpi *B );
+
+/**
+ * \brief          Modulo: r = A mod b
+ *
+ * \param r        Destination t_uint
+ * \param A        Left-hand MPI
+ * \param b        Integer to divide by
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed,
+ *                 POLARSSL_ERR_MPI_DIVISION_BY_ZERO if b == 0,
+ *                 POLARSSL_ERR_MPI_NEGATIVE_VALUE if b < 0
+ */
+int mpi_mod_int( t_uint *r, const mpi *A, t_sint b );
+
+/**
+ * \brief          Sliding-window exponentiation: X = A^E mod N
+ *
+ * \param X        Destination MPI 
+ * \param A        Left-hand MPI
+ * \param E        Exponent MPI
+ * \param N        Modular MPI
+ * \param _RR      Speed-up MPI used for recalculations
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed,
+ *                 POLARSSL_ERR_MPI_BAD_INPUT_DATA if N is negative or even
+ *
+ * \note           _RR is used to avoid re-computing R*R mod N across
+ *                 multiple calls, which speeds up things a bit. It can
+ *                 be set to NULL if the extra performance is unneeded.
+ */
+int mpi_exp_mod( mpi *X, const mpi *A, const mpi *E, const mpi *N, mpi *_RR );
+
+/**
+ * \brief          Fill an MPI X with size bytes of random
+ *
+ * \param X        Destination MPI
+ * \param size     Size in bytes
+ * \param f_rng    RNG function
+ * \param p_rng    RNG parameter
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_fill_random( mpi *X, size_t size,
+                     int (*f_rng)(void *, unsigned char *, size_t),
+                     void *p_rng );
+
+/**
+ * \brief          Greatest common divisor: G = gcd(A, B)
+ *
+ * \param G        Destination MPI
+ * \param A        Left-hand MPI
+ * \param B        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed
+ */
+int mpi_gcd( mpi *G, const mpi *A, const mpi *B );
+
+/**
+ * \brief          Modular inverse: X = A^-1 mod N
+ *
+ * \param X        Destination MPI
+ * \param A        Left-hand MPI
+ * \param N        Right-hand MPI
+ *
+ * \return         0 if successful,
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed,
+ *                 POLARSSL_ERR_MPI_BAD_INPUT_DATA if N is negative or nil
+                   POLARSSL_ERR_MPI_NOT_ACCEPTABLE if A has no inverse mod N
+ */
+int mpi_inv_mod( mpi *X, const mpi *A, const mpi *N );
+
+/**
+ * \brief          Miller-Rabin primality test
+ *
+ * \param X        MPI to check
+ * \param f_rng    RNG function
+ * \param p_rng    RNG parameter
+ *
+ * \return         0 if successful (probably prime),
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed,
+ *                 POLARSSL_ERR_MPI_NOT_ACCEPTABLE if X is not prime
+ */
+int mpi_is_prime( mpi *X,
+                  int (*f_rng)(void *, unsigned char *, size_t),
+                  void *p_rng );
+
+/**
+ * \brief          Prime number generation
+ *
+ * \param X        Destination MPI
+ * \param nbits    Required size of X in bits ( 3 <= nbits <= POLARSSL_MPI_MAX_BITS )
+ * \param dh_flag  If 1, then (X-1)/2 will be prime too
+ * \param f_rng    RNG function
+ * \param p_rng    RNG parameter
+ *
+ * \return         0 if successful (probably prime),
+ *                 POLARSSL_ERR_MPI_MALLOC_FAILED if memory allocation failed,
+ *                 POLARSSL_ERR_MPI_BAD_INPUT_DATA if nbits is < 3
+ */
+int mpi_gen_prime( mpi *X, size_t nbits, int dh_flag,
+                   int (*f_rng)(void *, unsigned char *, size_t),
+                   void *p_rng );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int mpi_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#define __ARM__ 1
+#ifdef __ARM__
+#define MULADDC_INIT                            \
+    asm( "ldr    r0, %0         " :: "m" (s));  \
+    asm( "ldr    r1, %0         " :: "m" (d));  \
+    asm( "ldr    r2, %0         " :: "m" (c));  \
+    asm( "ldr    r3, %0         " :: "m" (b));
+
+#define MULADDC_CORE                            \
+    asm( "ldr    r4, [r0], #4   " );            \
+    asm( "mov    r5, #0         " );            \
+    asm( "ldr    r6, [r1]       " );            \
+    asm( "umlal  r2, r5, r3, r4 " );            \
+    asm( "adds   r7, r6, r2     " );            \
+    asm( "adc    r2, r5, #0     " );            \
+    asm( "str    r7, [r1], #4   " );
+
+#define MULADDC_STOP                            \
+    asm( "str    r2, %0         " : "=m" (c));  \
+    asm( "str    r1, %0         " : "=m" (d));  \
+    asm( "str    r0, %0         " : "=m" (s) :: \
+    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" );
+
+#endif
+
+#ifdef __i386__
+#define MULADDC_INIT                \
+    asm( "                          \
+        movl   %%ebx, %0;           \
+        movl   %5, %%esi;           \
+        movl   %6, %%edi;           \
+        movl   %7, %%ecx;           \
+        movl   %8, %%ebx;           \
+        "
+
+#define MULADDC_CORE                \
+        "                           \
+        lodsl;                      \
+        mull   %%ebx;               \
+        addl   %%ecx,   %%eax;      \
+        adcl   $0,      %%edx;      \
+        addl   (%%edi), %%eax;      \
+        adcl   $0,      %%edx;      \
+        movl   %%edx,   %%ecx;      \
+        stosl;                      \
+        "
+
+
+#define MULADDC_HUIT                    \
+        "                               \
+        movd     %%ecx,     %%mm1;      \
+        movd     %%ebx,     %%mm0;      \
+        movd     (%%edi),   %%mm3;      \
+        paddq    %%mm3,     %%mm1;      \
+        movd     (%%esi),   %%mm2;      \
+        pmuludq  %%mm0,     %%mm2;      \
+        movd     4(%%esi),  %%mm4;      \
+        pmuludq  %%mm0,     %%mm4;      \
+        movd     8(%%esi),  %%mm6;      \
+        pmuludq  %%mm0,     %%mm6;      \
+        movd     12(%%esi), %%mm7;      \
+        pmuludq  %%mm0,     %%mm7;      \
+        paddq    %%mm2,     %%mm1;      \
+        movd     4(%%edi),  %%mm3;      \
+        paddq    %%mm4,     %%mm3;      \
+        movd     8(%%edi),  %%mm5;      \
+        paddq    %%mm6,     %%mm5;      \
+        movd     12(%%edi), %%mm4;      \
+        paddq    %%mm4,     %%mm7;      \
+        movd     %%mm1,     (%%edi);    \
+        movd     16(%%esi), %%mm2;      \
+        pmuludq  %%mm0,     %%mm2;      \
+        psrlq    $32,       %%mm1;      \
+        movd     20(%%esi), %%mm4;      \
+        pmuludq  %%mm0,     %%mm4;      \
+        paddq    %%mm3,     %%mm1;      \
+        movd     24(%%esi), %%mm6;      \
+        pmuludq  %%mm0,     %%mm6;      \
+        movd     %%mm1,     4(%%edi);   \
+        psrlq    $32,       %%mm1;      \
+        movd     28(%%esi), %%mm3;      \
+        pmuludq  %%mm0,     %%mm3;      \
+        paddq    %%mm5,     %%mm1;      \
+        movd     16(%%edi), %%mm5;      \
+        paddq    %%mm5,     %%mm2;      \
+        movd     %%mm1,     8(%%edi);   \
+        psrlq    $32,       %%mm1;      \
+        paddq    %%mm7,     %%mm1;      \
+        movd     20(%%edi), %%mm5;      \
+        paddq    %%mm5,     %%mm4;      \
+        movd     %%mm1,     12(%%edi);  \
+        psrlq    $32,       %%mm1;      \
+        paddq    %%mm2,     %%mm1;      \
+        movd     24(%%edi), %%mm5;      \
+        paddq    %%mm5,     %%mm6;      \
+        movd     %%mm1,     16(%%edi);  \
+        psrlq    $32,       %%mm1;      \
+        paddq    %%mm4,     %%mm1;      \
+        movd     28(%%edi), %%mm5;      \
+        paddq    %%mm5,     %%mm3;      \
+        movd     %%mm1,     20(%%edi);  \
+        psrlq    $32,       %%mm1;      \
+        paddq    %%mm6,     %%mm1;      \
+        movd     %%mm1,     24(%%edi);  \
+        psrlq    $32,       %%mm1;      \
+        paddq    %%mm3,     %%mm1;      \
+        movd     %%mm1,     28(%%edi);  \
+        addl     $32,       %%edi;      \
+        addl     $32,       %%esi;      \
+        psrlq    $32,       %%mm1;      \
+        movd     %%mm1,     %%ecx;      \
+        "
+
+#define MULADDC_STOP            \
+        "                       \
+        emms;                   \
+        movl   %4, %%ebx;       \
+        movl   %%ecx, %1;       \
+        movl   %%edi, %2;       \
+        movl   %%esi, %3;       \
+        "                       \
+        : "=m" (t), "=m" (c), "=m" (d), "=m" (s)        \
+        : "m" (t), "m" (s), "m" (d), "m" (c), "m" (b)   \
+        : "eax", "ecx", "edx", "esi", "edi"             \
+    );
+
+#endif
+#endif /* bignum.h */
diff --git a/include/linux/rsa/dhm.h b/include/linux/rsa/dhm.h
new file mode 100755
index 0000000..0c8dd55
--- /dev/null
+++ b/include/linux/rsa/dhm.h
@@ -0,0 +1,153 @@
+/**
+ * \file dhm.h
+ *
+ * \brief Diffie-Hellman-Merkle key exchange
+ *
+ *  Copyright (C) 2006-2010, Brainspark B.V.
+ *
+ *  This file is part of PolarSSL (http://www.polarssl.org)
+ *  Lead Maintainer: Paul Bakker <polarssl_maintainer at polarssl.org>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef POLARSSL_DHM_H
+#define POLARSSL_DHM_H
+
+#include "bignum.h"
+
+/*
+ * DHM Error codes
+ */
+#define POLARSSL_ERR_DHM_BAD_INPUT_DATA                    -0x3080  /**< Bad input parameters to function. */
+#define POLARSSL_ERR_DHM_READ_PARAMS_FAILED                -0x3100  /**< Reading of the DHM parameters failed. */
+#define POLARSSL_ERR_DHM_MAKE_PARAMS_FAILED                -0x3180  /**< Making of the DHM parameters failed. */
+#define POLARSSL_ERR_DHM_READ_PUBLIC_FAILED                -0x3200  /**< Reading of the public values failed. */
+#define POLARSSL_ERR_DHM_MAKE_PUBLIC_FAILED                -0x3280  /**< Making of the public value failed. */
+#define POLARSSL_ERR_DHM_CALC_SECRET_FAILED                -0x3300  /**< Calculation of the DHM secret failed. */
+
+/**
+ * \brief          DHM context structure
+ */
+typedef struct
+{
+    size_t len; /*!<  size(P) in chars  */
+    mpi P;      /*!<  prime modulus     */
+    mpi G;      /*!<  generator         */
+    mpi X;      /*!<  secret value      */
+    mpi GX;     /*!<  self = G^X mod P  */
+    mpi GY;     /*!<  peer = G^Y mod P  */
+    mpi K;      /*!<  key = GY^X mod P  */
+    mpi RP;     /*!<  cached R^2 mod P  */
+}
+dhm_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Parse the ServerKeyExchange parameters
+ *
+ * \param ctx      DHM context
+ * \param p        &(start of input buffer)
+ * \param end      end of buffer
+ *
+ * \return         0 if successful, or an POLARSSL_ERR_DHM_XXX error code
+ */
+int dhm_read_params( dhm_context *ctx,
+                     unsigned char **p,
+                     const unsigned char *end );
+
+/**
+ * \brief          Setup and write the ServerKeyExchange parameters
+ *
+ * \param ctx      DHM context
+ * \param x_size   private value size in bytes
+ * \param output   destination buffer
+ * \param olen     number of chars written
+ * \param f_rng    RNG function
+ * \param p_rng    RNG parameter
+ *
+ * \note           This function assumes that ctx->P and ctx->G
+ *                 have already been properly set (for example
+ *                 using mpi_read_string or mpi_read_binary).
+ *
+ * \return         0 if successful, or an POLARSSL_ERR_DHM_XXX error code
+ */
+int dhm_make_params( dhm_context *ctx, int x_size,
+                     unsigned char *output, size_t *olen,
+                     int (*f_rng)(void *, unsigned char *, size_t),
+                     void *p_rng );
+
+/**
+ * \brief          Import the peer's public value G^Y
+ *
+ * \param ctx      DHM context
+ * \param input    input buffer
+ * \param ilen     size of buffer
+ *
+ * \return         0 if successful, or an POLARSSL_ERR_DHM_XXX error code
+ */
+int dhm_read_public( dhm_context *ctx,
+                     const unsigned char *input, size_t ilen );
+
+/**
+ * \brief          Create own private value X and export G^X
+ *
+ * \param ctx      DHM context
+ * \param x_size   private value size in bytes
+ * \param output   destination buffer
+ * \param olen     must be equal to ctx->P.len
+ * \param f_rng    RNG function
+ * \param p_rng    RNG parameter
+ *
+ * \return         0 if successful, or an POLARSSL_ERR_DHM_XXX error code
+ */
+int dhm_make_public( dhm_context *ctx, int x_size,
+                     unsigned char *output, size_t olen,
+                     int (*f_rng)(void *, unsigned char *, size_t),
+                     void *p_rng );
+
+/**
+ * \brief          Derive and export the shared secret (G^Y)^X mod P
+ *
+ * \param ctx      DHM context
+ * \param output   destination buffer
+ * \param olen     number of chars written
+ *
+ * \return         0 if successful, or an POLARSSL_ERR_DHM_XXX error code
+ */
+int dhm_calc_secret( dhm_context *ctx,
+                     unsigned char *output, size_t *olen );
+
+/*
+ * \brief          Free the components of a DHM key
+ */
+void dhm_free( dhm_context *ctx );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int dhm_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/linux/rsa/pem.h b/include/linux/rsa/pem.h
new file mode 100755
index 0000000..fbae8c5
--- /dev/null
+++ b/include/linux/rsa/pem.h
@@ -0,0 +1,100 @@
+/**
+ * \file pem.h
+ *
+ * \brief Privacy Enhanced Mail (PEM) decoding
+ *
+ *  Copyright (C) 2006-2010, Brainspark B.V.
+ *
+ *  This file is part of PolarSSL (http://www.polarssl.org)
+ *  Lead Maintainer: Paul Bakker <polarssl_maintainer at polarssl.org>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef POLARSSL_PEM_H
+#define POLARSSL_PEM_H
+
+//#include <string.h>
+
+/**
+ * \name PEM Error codes
+ * These error codes are returned in case of errors reading the
+ * PEM data.
+ * \{
+ */
+#define POLARSSL_ERR_PEM_NO_HEADER_PRESENT                 -0x1080  /**< No PEM header found. */
+#define POLARSSL_ERR_PEM_INVALID_DATA                      -0x1100  /**< PEM string is not as expected. */
+#define POLARSSL_ERR_PEM_MALLOC_FAILED                     -0x1180  /**< Failed to allocate memory. */
+#define POLARSSL_ERR_PEM_INVALID_ENC_IV                    -0x1200  /**< RSA IV is not in hex-format. */
+#define POLARSSL_ERR_PEM_UNKNOWN_ENC_ALG                   -0x1280  /**< Unsupported key encryption algorithm. */
+#define POLARSSL_ERR_PEM_PASSWORD_REQUIRED                 -0x1300  /**< Private key password can't be empty. */
+#define POLARSSL_ERR_PEM_PASSWORD_MISMATCH                 -0x1380  /**< Given private key password does not allow for correct decryption. */
+#define POLARSSL_ERR_PEM_FEATURE_UNAVAILABLE               -0x1400  /**< Unavailable feature, e.g. hashing/encryption combination. */
+/* \} name */
+
+/**
+ * \brief       PEM context structure
+ */
+typedef struct
+{
+    unsigned char *buf;     /*!< buffer for decoded data             */
+    size_t buflen;          /*!< length of the buffer                */
+    unsigned char *info;    /*!< buffer for extra header information */
+}
+pem_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief       PEM context setup
+ *
+ * \param ctx   context to be initialized
+ */
+void pem_init( pem_context *ctx );
+
+/**
+ * \brief       Read a buffer for PEM information and store the resulting
+ *              data into the specified context buffers.
+ *
+ * \param ctx       context to use
+ * \param header    header string to seek and expect
+ * \param footer    footer string to seek and expect
+ * \param data      source data to look in
+ * \param pwd       password for decryption (can be NULL)
+ * \param pwdlen    length of password
+ * \param use_len   destination for total length used
+ *
+ * \return          0 on success, ior a specific PEM error code
+ */
+int pem_read_buffer( pem_context *ctx,
+                     const unsigned char *data,
+                     const unsigned char *pwd,
+                     size_t pwdlen, size_t *use_len );
+
+/**
+ * \brief       PEM context memory freeing
+ *
+ * \param ctx   context to be freed
+ */
+void pem_free( pem_context *ctx );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* pem.h */
diff --git a/include/linux/rsa/rsa.h b/include/linux/rsa/rsa.h
new file mode 100755
index 0000000..d19e419
--- /dev/null
+++ b/include/linux/rsa/rsa.h
@@ -0,0 +1,374 @@
+/**
+ * \file rsa.h
+ *
+ * \brief The RSA public-key cryptosystem
+ *
+ *  Copyright (C) 2006-2010, Brainspark B.V.
+ *
+ *  This file is part of PolarSSL (http://www.polarssl.org)
+ *  Lead Maintainer: Paul Bakker <polarssl_maintainer at polarssl.org>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef POLARSSL_RSA_H
+#define POLARSSL_RSA_H
+
+//#include "bignum.h"
+#include <linux/rsa/bignum.h>
+#include <stddef.h>
+/*
+ * RSA Error codes
+ */
+#define POLARSSL_ERR_RSA_BAD_INPUT_DATA                    -0x4080  /**< Bad input parameters to function. */
+#define POLARSSL_ERR_RSA_INVALID_PADDING                   -0x4100  /**< Input data contains invalid padding and is rejected. */
+#define POLARSSL_ERR_RSA_KEY_GEN_FAILED                    -0x4180  /**< Something failed during generation of a key. */
+#define POLARSSL_ERR_RSA_KEY_CHECK_FAILED                  -0x4200  /**< Key failed to pass the libraries validity check. */
+#define POLARSSL_ERR_RSA_PUBLIC_FAILED                     -0x4280  /**< The public key operation failed. */
+#define POLARSSL_ERR_RSA_PRIVATE_FAILED                    -0x4300  /**< The private key operation failed. */
+#define POLARSSL_ERR_RSA_VERIFY_FAILED                     -0x4380  /**< The PKCS#1 verification failed. */
+#define POLARSSL_ERR_RSA_OUTPUT_TOO_LARGE                  -0x4400  /**< The output buffer for decryption is not large enough. */
+#define POLARSSL_ERR_RSA_RNG_FAILED                        -0x4480  /**< The random generator failed to generate non-zeros. */
+
+/*
+ * PKCS#1 constants
+ */
+#define SIG_RSA_RAW     0
+#define SIG_RSA_MD2     2
+#define SIG_RSA_MD4     3
+#define SIG_RSA_MD5     4
+#define SIG_RSA_SHA1    5
+#define SIG_RSA_SHA224 14
+#define SIG_RSA_SHA256 11
+#define SIG_RSA_SHA384 12
+#define SIG_RSA_SHA512 13
+
+#define RSA_PUBLIC      0
+#define RSA_PRIVATE     1
+
+#define RSA_PKCS_V15    0
+#define RSA_PKCS_V21    1
+
+#define RSA_SIGN        1
+#define RSA_CRYPT       2
+
+#define ASN1_STR_CONSTRUCTED_SEQUENCE   "\x30"
+#define ASN1_STR_NULL                   "\x05"
+#define ASN1_STR_OID                    "\x06"
+#define ASN1_STR_OCTET_STRING           "\x04"
+
+#define OID_DIGEST_ALG_MDX              "\x2A\x86\x48\x86\xF7\x0D\x02\x00"
+#define OID_HASH_ALG_SHA1               "\x2b\x0e\x03\x02\x1a"
+#define OID_HASH_ALG_SHA2X              "\x60\x86\x48\x01\x65\x03\x04\x02\x00"
+
+#define OID_ISO_MEMBER_BODIES           "\x2a"
+#define OID_ISO_IDENTIFIED_ORG          "\x2b"
+
+/*
+ * ISO Member bodies OID parts
+ */
+#define OID_COUNTRY_US                  "\x86\x48"
+#define OID_RSA_DATA_SECURITY           "\x86\xf7\x0d"
+
+/*
+ * ISO Identified organization OID parts
+ */
+#define OID_OIW_SECSIG_SHA1             "\x0e\x03\x02\x1a"
+
+/*
+ * DigestInfo ::= SEQUENCE {
+ *   digestAlgorithm DigestAlgorithmIdentifier,
+ *   digest Digest }
+ *
+ * DigestAlgorithmIdentifier ::= AlgorithmIdentifier
+ *
+ * Digest ::= OCTET STRING
+ */
+#define ASN1_HASH_MDX                           \
+(                                               \
+    ASN1_STR_CONSTRUCTED_SEQUENCE "\x20"        \
+      ASN1_STR_CONSTRUCTED_SEQUENCE "\x0C"      \
+        ASN1_STR_OID "\x08"                     \
+      OID_DIGEST_ALG_MDX                        \
+    ASN1_STR_NULL "\x00"                        \
+      ASN1_STR_OCTET_STRING "\x10"              \
+)
+
+#define ASN1_HASH_SHA1                          \
+    ASN1_STR_CONSTRUCTED_SEQUENCE "\x21"        \
+      ASN1_STR_CONSTRUCTED_SEQUENCE "\x09"      \
+        ASN1_STR_OID "\x05"                     \
+      OID_HASH_ALG_SHA1                         \
+        ASN1_STR_NULL "\x00"                    \
+      ASN1_STR_OCTET_STRING "\x14"
+
+#define ASN1_HASH_SHA2X                         \
+    ASN1_STR_CONSTRUCTED_SEQUENCE "\x11"        \
+      ASN1_STR_CONSTRUCTED_SEQUENCE "\x0d"      \
+        ASN1_STR_OID "\x09"                     \
+      OID_HASH_ALG_SHA2X                        \
+        ASN1_STR_NULL "\x00"                    \
+      ASN1_STR_OCTET_STRING "\x00"
+
+
+/**
+ * \brief          RSA context structure
+ */
+typedef struct
+{
+    int ver;                    /*!<  always 0          */
+    size_t len;                 /*!<  size(N) in chars  */
+
+    mpi N;                      /*!<  public modulus    */
+    mpi E;                      /*!<  public exponent   */
+
+    mpi D;                      /*!<  private exponent  */
+    mpi P;                      /*!<  1st prime factor  */
+    mpi Q;                      /*!<  2nd prime factor  */
+    mpi DP;                     /*!<  D % (P - 1)       */
+    mpi DQ;                     /*!<  D % (Q - 1)       */
+    mpi QP;                     /*!<  1 / (Q % P)       */
+
+    mpi RN;                     /*!<  cached R^2 mod N  */
+    mpi RP;                     /*!<  cached R^2 mod P  */
+    mpi RQ;                     /*!<  cached R^2 mod Q  */
+
+    int padding;                /*!<  RSA_PKCS_V15 for 1.5 padding and
+                                      RSA_PKCS_v21 for OAEP/PSS         */
+    int hash_id;                /*!<  Hash identifier of md_type_t as
+                                      specified in the md.h header file
+                                      for the EME-OAEP and EMSA-PSS
+                                      encoding                          */
+}
+rsa_context;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief          Initialize an RSA context
+ *
+ * \param ctx      RSA context to be initialized
+ * \param padding  RSA_PKCS_V15 or RSA_PKCS_V21
+ * \param hash_id  RSA_PKCS_V21 hash identifier
+ *
+ * \note           The hash_id parameter is actually ignored
+ *                 when using RSA_PKCS_V15 padding.
+ */
+void rsa_init( rsa_context *ctx,
+               int padding,
+               int hash_id);
+
+/**
+ * \brief          Generate an RSA keypair
+ *
+ * \param ctx      RSA context that will hold the key
+ * \param f_rng    RNG function
+ * \param p_rng    RNG parameter
+ * \param nbits    size of the public key in bits
+ * \param exponent public exponent (e.g., 65537)
+ *
+ * \note           rsa_init() must be called beforehand to setup
+ *                 the RSA context.
+ *
+ * \return         0 if successful, or an POLARSSL_ERR_RSA_XXX error code
+ */
+int rsa_gen_key( rsa_context *ctx,
+                 int (*f_rng)(void *, unsigned char *, size_t),
+                 void *p_rng,
+                 unsigned int nbits, int exponent );
+
+/**
+ * \brief          Check a public RSA key
+ *
+ * \param ctx      RSA context to be checked
+ *
+ * \return         0 if successful, or an POLARSSL_ERR_RSA_XXX error code
+ */
+int rsa_check_pubkey( const rsa_context *ctx );
+
+/**
+ * \brief          Check a private RSA key
+ *
+ * \param ctx      RSA context to be checked
+ *
+ * \return         0 if successful, or an POLARSSL_ERR_RSA_XXX error code
+ */
+int rsa_check_privkey( const rsa_context *ctx );
+
+/**
+ * \brief          Do an RSA public key operation
+ *
+ * \param ctx      RSA context
+ * \param input    input buffer
+ * \param output   output buffer
+ *
+ * \return         0 if successful, or an POLARSSL_ERR_RSA_XXX error code
+ *
+ * \note           This function does NOT take care of message
+ *                 padding. Also, be sure to set input[0] = 0 or assure that
+ *                 input is smaller than N.
+ *
+ * \note           The input and output buffers must be large
+ *                 enough (eg. 128 bytes if RSA-1024 is used).
+ */
+int rsa_public( rsa_context *ctx,
+                const unsigned char *input,
+                unsigned char *output );
+
+/**
+ * \brief          Do an RSA private key operation
+ *
+ * \param ctx      RSA context
+ * \param input    input buffer
+ * \param output   output buffer
+ *
+ * \return         0 if successful, or an POLARSSL_ERR_RSA_XXX error code
+ *
+ * \note           The input and output buffers must be large
+ *                 enough (eg. 128 bytes if RSA-1024 is used).
+ */
+int rsa_private( rsa_context *ctx,
+                 const unsigned char *input,
+                 unsigned char *output );
+
+/**
+ * \brief          Add the message padding, then do an RSA operation
+ *
+ * \param ctx      RSA context
+ * \param f_rng    RNG function (Needed for padding and PKCS#1 v2.1 encoding)
+ * \param p_rng    RNG parameter
+ * \param mode     RSA_PUBLIC or RSA_PRIVATE
+ * \param ilen     contains the plaintext length
+ * \param input    buffer holding the data to be encrypted
+ * \param output   buffer that will hold the ciphertext
+ *
+ * \return         0 if successful, or an POLARSSL_ERR_RSA_XXX error code
+ *
+ * \note           The output buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
+ */
+int rsa_pkcs1_encrypt( rsa_context *ctx,
+                       int (*f_rng)(void *, unsigned char *, size_t),
+                       void *p_rng,
+                       int mode, size_t ilen,
+                       const unsigned char *input,
+                       unsigned char *output );
+
+/**
+ * \brief          Do an RSA operation, then remove the message padding
+ *
+ * \param ctx      RSA context
+ * \param mode     RSA_PUBLIC or RSA_PRIVATE
+ * \param olen     will contain the plaintext length
+ * \param input    buffer holding the encrypted data
+ * \param output   buffer that will hold the plaintext
+ * \param output_max_len    maximum length of the output buffer
+ *
+ * \return         0 if successful, or an POLARSSL_ERR_RSA_XXX error code
+ *
+ * \note           The output buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used) otherwise
+ *                 an error is thrown.
+ */
+int rsa_pkcs1_decrypt( rsa_context *ctx,
+                       int mode, size_t *olen,
+                       const unsigned char *input,
+                       unsigned char *output,
+                       size_t output_max_len );
+
+/**
+ * \brief          Do a private RSA to sign a message digest
+ *
+ * \param ctx      RSA context
+ * \param f_rng    RNG function (Needed for PKCS#1 v2.1 encoding)
+ * \param p_rng    RNG parameter
+ * \param mode     RSA_PUBLIC or RSA_PRIVATE
+ * \param hash_id  SIG_RSA_RAW, SIG_RSA_MD{2,4,5} or SIG_RSA_SHA{1,224,256,384,512}
+ * \param hashlen  message digest length (for SIG_RSA_RAW only)
+ * \param hash     buffer holding the message digest
+ * \param sig      buffer that will hold the ciphertext
+ *
+ * \return         0 if the signing operation was successful,
+ *                 or an POLARSSL_ERR_RSA_XXX error code
+ *
+ * \note           The "sig" buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
+ *
+ * \note           In case of PKCS#1 v2.1 encoding keep in mind that
+ *                 the hash_id in the RSA context is the one used for the
+ *                 encoding. hash_id in the function call is the type of hash
+ *                 that is encoded. According to RFC 3447 it is advised to
+ *                 keep both hashes the same.
+ */
+int rsa_pkcs1_sign( rsa_context *ctx,
+                    int (*f_rng)(void *, unsigned char *, size_t),
+                    void *p_rng,
+                    int mode,
+                    int hash_id,
+                    unsigned int hashlen,
+                    const unsigned char *hash,
+                    unsigned char *sig );
+
+/**
+ * \brief          Do a public RSA and check the message digest
+ *
+ * \param ctx      points to an RSA public key
+ * \param mode     RSA_PUBLIC or RSA_PRIVATE
+ * \param hash_id  SIG_RSA_RAW, SIG_RSA_MD{2,4,5} or SIG_RSA_SHA{1,224,256,384,512}
+ * \param hashlen  message digest length (for SIG_RSA_RAW only)
+ * \param hash     buffer holding the message digest
+ * \param sig      buffer holding the ciphertext
+ *
+ * \return         0 if the verify operation was successful,
+ *                 or an POLARSSL_ERR_RSA_XXX error code
+ *
+ * \note           The "sig" buffer must be as large as the size
+ *                 of ctx->N (eg. 128 bytes if RSA-1024 is used).
+ *
+ * \note           In case of PKCS#1 v2.1 encoding keep in mind that
+ *                 the hash_id in the RSA context is the one used for the
+ *                 verification. hash_id in the function call is the type of hash
+ *                 that is verified. According to RFC 3447 it is advised to
+ *                 keep both hashes the same.
+ */
+int rsa_pkcs1_verify( rsa_context *ctx,
+                      int mode,
+                      int hash_id,
+                      unsigned int hashlen,
+                      const unsigned char *hash,
+                      unsigned char *sig );
+
+/**
+ * \brief          Free the components of an RSA key
+ *
+ * \param ctx      RSA Context to free
+ */
+void rsa_free( rsa_context *ctx );
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int rsa_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* rsa.h */
diff --git a/include/linux/rsa/x509.h b/include/linux/rsa/x509.h
new file mode 100755
index 0000000..cd0dc84
--- /dev/null
+++ b/include/linux/rsa/x509.h
@@ -0,0 +1,726 @@
+/**
+ * \file x509.h
+ *
+ * \brief X.509 certificate and private key decoding
+ *
+ *  Copyright (C) 2006-2011, Brainspark B.V.
+ *
+ *  This file is part of PolarSSL (http://www.polarssl.org)
+ *  Lead Maintainer: Paul Bakker <polarssl_maintainer at polarssl.org>
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef POLARSSL_X509_H
+#define POLARSSL_X509_H
+
+#include "asn1.h"
+#include "rsa.h"
+#include "dhm.h"
+
+/** 
+ * \addtogroup x509_module
+ * \{ 
+ */
+ 
+/** 
+ * \name X509 Error codes
+ * \{
+ */
+#define POLARSSL_ERR_X509_FEATURE_UNAVAILABLE              -0x2080  /**< Unavailable feature, e.g. RSA hashing/encryption combination. */
+#define POLARSSL_ERR_X509_CERT_INVALID_PEM                 -0x2100  /**< The PEM-encoded certificate contains invalid elements, e.g. invalid character. */ 
+#define POLARSSL_ERR_X509_CERT_INVALID_FORMAT              -0x2180  /**< The certificate format is invalid, e.g. different type expected. */
+#define POLARSSL_ERR_X509_CERT_INVALID_VERSION             -0x2200  /**< The certificate version element is invalid. */
+#define POLARSSL_ERR_X509_CERT_INVALID_SERIAL              -0x2280  /**< The serial tag or value is invalid. */
+#define POLARSSL_ERR_X509_CERT_INVALID_ALG                 -0x2300  /**< The algorithm tag or value is invalid. */
+#define POLARSSL_ERR_X509_CERT_INVALID_NAME                -0x2380  /**< The name tag or value is invalid. */
+#define POLARSSL_ERR_X509_CERT_INVALID_DATE                -0x2400  /**< The date tag or value is invalid. */
+#define POLARSSL_ERR_X509_CERT_INVALID_PUBKEY              -0x2480  /**< The pubkey tag or value is invalid (only RSA is supported). */
+#define POLARSSL_ERR_X509_CERT_INVALID_SIGNATURE           -0x2500  /**< The signature tag or value invalid. */
+#define POLARSSL_ERR_X509_CERT_INVALID_EXTENSIONS          -0x2580  /**< The extension tag or value is invalid. */
+#define POLARSSL_ERR_X509_CERT_UNKNOWN_VERSION             -0x2600  /**< Certificate or CRL has an unsupported version number. */
+#define POLARSSL_ERR_X509_CERT_UNKNOWN_SIG_ALG             -0x2680  /**< Signature algorithm (oid) is unsupported. */
+#define POLARSSL_ERR_X509_UNKNOWN_PK_ALG                   -0x2700  /**< Key algorithm is unsupported (only RSA is supported). */
+#define POLARSSL_ERR_X509_CERT_SIG_MISMATCH                -0x2780  /**< Certificate signature algorithms do not match. (see \c ::x509_cert sig_oid) */
+#define POLARSSL_ERR_X509_CERT_VERIFY_FAILED               -0x2800  /**< Certificate verification failed, e.g. CRL, CA or signature check failed. */
+#define POLARSSL_ERR_X509_KEY_INVALID_VERSION              -0x2880  /**< Unsupported RSA key version */
+#define POLARSSL_ERR_X509_KEY_INVALID_FORMAT               -0x2900  /**< Invalid RSA key tag or value. */
+#define POLARSSL_ERR_X509_CERT_UNKNOWN_FORMAT              -0x2980  /**< Format not recognized as DER or PEM. */
+#define POLARSSL_ERR_X509_INVALID_INPUT                    -0x2A00  /**< Input invalid. */
+#define POLARSSL_ERR_X509_MALLOC_FAILED                    -0x2A80  /**< Allocation of memory failed. */
+#define POLARSSL_ERR_X509_FILE_IO_ERROR                    -0x2B00  /**< Read/write of file failed. */
+/* \} name */
+
+
+/**
+ * \name X509 Verify codes
+ * \{
+ */
+#define BADCERT_EXPIRED             0x01  /**< The certificate validity has expired. */
+#define BADCERT_REVOKED             0x02  /**< The certificate has been revoked (is on a CRL). */
+#define BADCERT_CN_MISMATCH         0x04  /**< The certificate Common Name (CN) does not match with the expected CN. */
+#define BADCERT_NOT_TRUSTED         0x08  /**< The certificate is not correctly signed by the trusted CA. */
+#define BADCRL_NOT_TRUSTED          0x10  /**< CRL is not correctly signed by the trusted CA. */
+#define BADCRL_EXPIRED              0x20  /**< CRL is expired. */
+#define BADCERT_MISSING             0x40  /**< Certificate was missing. */
+#define BADCERT_SKIP_VERIFY         0x80  /**< Certificate verification was skipped. */
+/* \} name */
+/* \} addtogroup x509_module */
+
+/*
+ * various object identifiers
+ */
+#define X520_COMMON_NAME                3
+#define X520_COUNTRY                    6
+#define X520_LOCALITY                   7
+#define X520_STATE                      8
+#define X520_ORGANIZATION              10
+#define X520_ORG_UNIT                  11
+#define PKCS9_EMAIL                     1
+
+#define X509_OUTPUT_DER              0x01
+#define X509_OUTPUT_PEM              0x02
+#define PEM_LINE_LENGTH                72
+#define X509_ISSUER                  0x01
+#define X509_SUBJECT                 0x02
+
+#define OID_X520                "\x55\x04"
+#define OID_CN                  OID_X520 "\x03"
+
+#define OID_PKCS1               "\x2A\x86\x48\x86\xF7\x0D\x01\x01"
+#define OID_PKCS1_RSA           OID_PKCS1 "\x01"
+
+#define OID_RSA_SHA_OBS         "\x2B\x0E\x03\x02\x1D"
+
+#define OID_PKCS9               "\x2A\x86\x48\x86\xF7\x0D\x01\x09"
+#define OID_PKCS9_EMAIL         OID_PKCS9 "\x01"
+
+/** ISO arc for standard certificate and CRL extensions */
+#define OID_ID_CE               "\x55\x1D" /**< id-ce OBJECT IDENTIFIER  ::=  {joint-iso-ccitt(2) ds(5) 29} */
+
+/**
+ * Private Internet Extensions
+ * { iso(1) identified-organization(3) dod(6) internet(1)
+ *                      security(5) mechanisms(5) pkix(7) }
+ */
+#define OID_PKIX                "\x2B\x06\x01\x05\x05\x07"
+
+/*
+ * OIDs for standard certificate extensions
+ */
+#define OID_AUTHORITY_KEY_IDENTIFIER    OID_ID_CE "\x23" /**< id-ce-authorityKeyIdentifier OBJECT IDENTIFIER ::=  { id-ce 35 } */
+#define OID_SUBJECT_KEY_IDENTIFIER      OID_ID_CE "\x0E" /**< id-ce-subjectKeyIdentifier OBJECT IDENTIFIER ::=  { id-ce 14 } */
+#define OID_KEY_USAGE                   OID_ID_CE "\x0F" /**< id-ce-keyUsage OBJECT IDENTIFIER ::=  { id-ce 15 } */
+#define OID_CERTIFICATE_POLICIES        OID_ID_CE "\x20" /**< id-ce-certificatePolicies OBJECT IDENTIFIER ::=  { id-ce 32 } */
+#define OID_POLICY_MAPPINGS             OID_ID_CE "\x21" /**< id-ce-policyMappings OBJECT IDENTIFIER ::=  { id-ce 33 } */
+#define OID_SUBJECT_ALT_NAME            OID_ID_CE "\x11" /**< id-ce-subjectAltName OBJECT IDENTIFIER ::=  { id-ce 17 } */
+#define OID_ISSUER_ALT_NAME             OID_ID_CE "\x12" /**< id-ce-issuerAltName OBJECT IDENTIFIER ::=  { id-ce 18 } */
+#define OID_SUBJECT_DIRECTORY_ATTRS     OID_ID_CE "\x09" /**< id-ce-subjectDirectoryAttributes OBJECT IDENTIFIER ::=  { id-ce 9 } */
+#define OID_BASIC_CONSTRAINTS           OID_ID_CE "\x13" /**< id-ce-basicConstraints OBJECT IDENTIFIER ::=  { id-ce 19 } */
+#define OID_NAME_CONSTRAINTS            OID_ID_CE "\x1E" /**< id-ce-nameConstraints OBJECT IDENTIFIER ::=  { id-ce 30 } */
+#define OID_POLICY_CONSTRAINTS          OID_ID_CE "\x24" /**< id-ce-policyConstraints OBJECT IDENTIFIER ::=  { id-ce 36 } */
+#define OID_EXTENDED_KEY_USAGE          OID_ID_CE "\x25" /**< id-ce-extKeyUsage OBJECT IDENTIFIER ::= { id-ce 37 } */
+#define OID_CRL_DISTRIBUTION_POINTS     OID_ID_CE "\x1F" /**< id-ce-cRLDistributionPoints OBJECT IDENTIFIER ::=  { id-ce 31 } */
+#define OID_INIHIBIT_ANYPOLICY          OID_ID_CE "\x36" /**< id-ce-inhibitAnyPolicy OBJECT IDENTIFIER ::=  { id-ce 54 } */
+#define OID_FRESHEST_CRL                OID_ID_CE "\x2E" /**< id-ce-freshestCRL OBJECT IDENTIFIER ::=  { id-ce 46 } */
+
+/*
+ * X.509 v3 Key Usage Extension flags
+ */
+#define KU_DIGITAL_SIGNATURE            (0x80)  /* bit 0 */
+#define KU_NON_REPUDIATION              (0x40)  /* bit 1 */
+#define KU_KEY_ENCIPHERMENT             (0x20)  /* bit 2 */
+#define KU_DATA_ENCIPHERMENT            (0x10)  /* bit 3 */
+#define KU_KEY_AGREEMENT                (0x08)  /* bit 4 */
+#define KU_KEY_CERT_SIGN                (0x04)  /* bit 5 */
+#define KU_CRL_SIGN                     (0x02)  /* bit 6 */
+
+/*
+ * X.509 v3 Extended key usage OIDs
+ */
+#define OID_ANY_EXTENDED_KEY_USAGE      OID_EXTENDED_KEY_USAGE "\x00" /**< anyExtendedKeyUsage OBJECT IDENTIFIER ::= { id-ce-extKeyUsage 0 } */
+
+#define OID_KP                          OID_PKIX "\x03" /**< id-kp OBJECT IDENTIFIER ::= { id-pkix 3 } */
+#define OID_SERVER_AUTH                 OID_KP "\x01" /**< id-kp-serverAuth OBJECT IDENTIFIER ::= { id-kp 1 } */
+#define OID_CLIENT_AUTH                 OID_KP "\x02" /**< id-kp-clientAuth OBJECT IDENTIFIER ::= { id-kp 2 } */
+#define OID_CODE_SIGNING                OID_KP "\x03" /**< id-kp-codeSigning OBJECT IDENTIFIER ::= { id-kp 3 } */
+#define OID_EMAIL_PROTECTION            OID_KP "\x04" /**< id-kp-emailProtection OBJECT IDENTIFIER ::= { id-kp 4 } */
+#define OID_TIME_STAMPING               OID_KP "\x08" /**< id-kp-timeStamping OBJECT IDENTIFIER ::= { id-kp 8 } */
+#define OID_OCSP_SIGNING                OID_KP "\x09" /**< id-kp-OCSPSigning OBJECT IDENTIFIER ::= { id-kp 9 } */
+
+#define STRING_SERVER_AUTH              "TLS Web Server Authentication"
+#define STRING_CLIENT_AUTH              "TLS Web Client Authentication"
+#define STRING_CODE_SIGNING             "Code Signing"
+#define STRING_EMAIL_PROTECTION         "E-mail Protection"
+#define STRING_TIME_STAMPING            "Time Stamping"
+#define STRING_OCSP_SIGNING             "OCSP Signing"
+
+/*
+ * OIDs for CRL extensions
+ */
+#define OID_PRIVATE_KEY_USAGE_PERIOD    OID_ID_CE "\x10"
+#define OID_CRL_NUMBER                  OID_ID_CE "\x14" /**< id-ce-cRLNumber OBJECT IDENTIFIER ::= { id-ce 20 } */
+
+/*
+ * Netscape certificate extensions
+ */
+#define OID_NETSCAPE                "\x60\x86\x48\x01\x86\xF8\x42" /**< Netscape OID */
+#define OID_NS_CERT                 OID_NETSCAPE "\x01"
+#define OID_NS_CERT_TYPE            OID_NS_CERT  "\x01"
+#define OID_NS_BASE_URL             OID_NS_CERT  "\x02"
+#define OID_NS_REVOCATION_URL       OID_NS_CERT  "\x03"
+#define OID_NS_CA_REVOCATION_URL    OID_NS_CERT  "\x04"
+#define OID_NS_RENEWAL_URL          OID_NS_CERT  "\x07"
+#define OID_NS_CA_POLICY_URL        OID_NS_CERT  "\x08"
+#define OID_NS_SSL_SERVER_NAME      OID_NS_CERT  "\x0C"
+#define OID_NS_COMMENT              OID_NS_CERT  "\x0D"
+#define OID_NS_DATA_TYPE            OID_NETSCAPE "\x02"
+#define OID_NS_CERT_SEQUENCE        OID_NS_DATA_TYPE "\x05"
+
+/*
+ * Netscape certificate types
+ * (http://www.mozilla.org/projects/security/pki/nss/tech-notes/tn3.html)
+ */
+
+#define NS_CERT_TYPE_SSL_CLIENT         (0x80)  /* bit 0 */
+#define NS_CERT_TYPE_SSL_SERVER         (0x40)  /* bit 1 */
+#define NS_CERT_TYPE_EMAIL              (0x20)  /* bit 2 */
+#define NS_CERT_TYPE_OBJECT_SIGNING     (0x10)  /* bit 3 */
+#define NS_CERT_TYPE_RESERVED           (0x08)  /* bit 4 */
+#define NS_CERT_TYPE_SSL_CA             (0x04)  /* bit 5 */
+#define NS_CERT_TYPE_EMAIL_CA           (0x02)  /* bit 6 */
+#define NS_CERT_TYPE_OBJECT_SIGNING_CA  (0x01)  /* bit 7 */
+
+#define EXT_AUTHORITY_KEY_IDENTIFIER    (1 << 0)
+#define EXT_SUBJECT_KEY_IDENTIFIER      (1 << 1)
+#define EXT_KEY_USAGE                   (1 << 2)
+#define EXT_CERTIFICATE_POLICIES        (1 << 3)
+#define EXT_POLICY_MAPPINGS             (1 << 4)
+#define EXT_SUBJECT_ALT_NAME            (1 << 5)
+#define EXT_ISSUER_ALT_NAME             (1 << 6)
+#define EXT_SUBJECT_DIRECTORY_ATTRS     (1 << 7)
+#define EXT_BASIC_CONSTRAINTS           (1 << 8)
+#define EXT_NAME_CONSTRAINTS            (1 << 9)
+#define EXT_POLICY_CONSTRAINTS          (1 << 10)
+#define EXT_EXTENDED_KEY_USAGE          (1 << 11)
+#define EXT_CRL_DISTRIBUTION_POINTS     (1 << 12)
+#define EXT_INIHIBIT_ANYPOLICY          (1 << 13)
+#define EXT_FRESHEST_CRL                (1 << 14)
+
+#define EXT_NS_CERT_TYPE                (1 << 16)
+
+/*
+ * Storage format identifiers
+ * Recognized formats: PEM and DER
+ */
+#define X509_FORMAT_DER                 1
+#define X509_FORMAT_PEM                 2
+
+/** 
+ * \addtogroup x509_module
+ * \{ */
+
+/**
+ * \name Structures for parsing X.509 certificates and CRLs
+ * \{
+ */
+ 
+/** 
+ * Type-length-value structure that allows for ASN1 using DER.
+ */
+typedef asn1_buf x509_buf;
+
+/**
+ * Container for ASN1 bit strings.
+ */
+typedef asn1_bitstring x509_bitstring;
+
+/**
+ * Container for ASN1 named information objects. 
+ * It allows for Relative Distinguished Names (e.g. cn=polarssl,ou=code,etc.).
+ */
+typedef struct _x509_name
+{
+    x509_buf oid;               /**< The object identifier. */
+    x509_buf val;               /**< The named value. */
+    struct _x509_name *next;    /**< The next named information object. */
+}
+x509_name;
+
+/**
+ * Container for a sequence of ASN.1 items
+ */
+typedef asn1_sequence x509_sequence;
+
+/** Container for date and time (precision in seconds). */
+typedef struct _x509_time
+{
+    int year, mon, day;         /**< Date. */
+    int hour, min, sec;         /**< Time. */
+}
+x509_time;
+
+/** 
+ * Container for an X.509 certificate. The certificate may be chained.
+ */
+typedef struct _x509_cert
+{
+    x509_buf raw;               /**< The raw certificate data (DER). */
+    x509_buf tbs;               /**< The raw certificate body (DER). The part that is To Be Signed. */
+
+    int version;                /**< The X.509 version. (0=v1, 1=v2, 2=v3) */
+    x509_buf serial;            /**< Unique id for certificate issued by a specific CA. */
+    x509_buf sig_oid1;          /**< Signature algorithm, e.g. sha1RSA */
+
+    x509_buf issuer_raw;        /**< The raw issuer data (DER). Used for quick comparison. */
+    x509_buf subject_raw;       /**< The raw subject data (DER). Used for quick comparison. */
+
+    x509_name issuer;           /**< The parsed issuer data (named information object). */
+    x509_name subject;          /**< The parsed subject data (named information object). */
+
+    x509_time valid_from;       /**< Start time of certificate validity. */
+    x509_time valid_to;         /**< End time of certificate validity. */
+
+    x509_buf pk_oid;            /**< Subject public key info. Includes the public key algorithm and the key itself. */
+    rsa_context rsa;            /**< Container for the RSA context. Only RSA is supported for public keys at this time. */
+
+    x509_buf issuer_id;         /**< Optional X.509 v2/v3 issuer unique identifier. */
+    x509_buf subject_id;        /**< Optional X.509 v2/v3 subject unique identifier. */
+    x509_buf v3_ext;            /**< Optional X.509 v3 extensions. Only Basic Contraints are supported at this time. */
+
+    int ext_types;              /**< Bit string containing detected and parsed extensions */
+    int ca_istrue;              /**< Optional Basic Constraint extension value: 1 if this certificate belongs to a CA, 0 otherwise. */
+    int max_pathlen;            /**< Optional Basic Constraint extension value: The maximum path length to the root certificate. */
+
+    unsigned char key_usage;    /**< Optional key usage extension value: See the values below */
+
+    x509_sequence ext_key_usage; /**< Optional list of extended key usage OIDs. */
+
+    unsigned char ns_cert_type; /**< Optional Netscape certificate type extension value: See the values below */
+
+    x509_buf sig_oid2;          /**< Signature algorithm. Must match sig_oid1. */
+    x509_buf sig;               /**< Signature: hash of the tbs part signed with the private key. */
+    int sig_alg;                /**< Internal representation of the signature algorithm, e.g. SIG_RSA_MD2 */
+
+    struct _x509_cert *next;    /**< Next certificate in the CA-chain. */ 
+}
+x509_cert;
+
+/** 
+ * Certificate revocation list entry. 
+ * Contains the CA-specific serial numbers and revocation dates.
+ */
+typedef struct _x509_crl_entry
+{
+    x509_buf raw;
+
+    x509_buf serial;
+
+    x509_time revocation_date;
+
+    x509_buf entry_ext;
+
+    struct _x509_crl_entry *next;
+}
+x509_crl_entry;
+
+/** 
+ * Certificate revocation list structure. 
+ * Every CRL may have multiple entries.
+ */
+typedef struct _x509_crl
+{
+    x509_buf raw;           /**< The raw certificate data (DER). */
+    x509_buf tbs;           /**< The raw certificate body (DER). The part that is To Be Signed. */
+
+    int version;
+    x509_buf sig_oid1;
+
+    x509_buf issuer_raw;    /**< The raw issuer data (DER). */
+
+    x509_name issuer;       /**< The parsed issuer data (named information object). */
+
+    x509_time this_update;  
+    x509_time next_update;
+
+    x509_crl_entry entry;   /**< The CRL entries containing the certificate revocation times for this CA. */
+
+    x509_buf crl_ext;
+
+    x509_buf sig_oid2;
+    x509_buf sig;
+    int sig_alg;
+
+    struct _x509_crl *next; 
+}
+x509_crl;
+/** \} name Structures for parsing X.509 certificates and CRLs */
+/** \} addtogroup x509_module */
+
+/**
+ * \name Structures for writing X.509 certificates.
+ * XvP: commented out as they are not used.
+ * - <tt>typedef struct _x509_node x509_node;</tt>
+ * - <tt>typedef struct _x509_raw x509_raw;</tt>
+ */
+/*
+typedef struct _x509_node
+{
+    unsigned char *data;
+    unsigned char *p;
+    unsigned char *end;
+
+    size_t len;
+}
+x509_node;
+
+typedef struct _x509_raw
+{
+    x509_node raw;
+    x509_node tbs;
+
+    x509_node version;
+    x509_node serial;
+    x509_node tbs_signalg;
+    x509_node issuer;
+    x509_node validity;
+    x509_node subject;
+    x509_node subpubkey;
+
+    x509_node signalg;
+    x509_node sign;
+}
+x509_raw;
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \name Functions to read in DHM parameters, a certificate, CRL or private RSA key
+ * \{
+ */
+
+/** \ingroup x509_module */
+/**
+ * \brief          Parse one or more certificates and add them
+ *                 to the chained list. Parses permissively. If some
+ *                 certificates can be parsed, the result is the number
+ *                 of failed certificates it encountered. If none complete
+ *                 correctly, the first error is returned.
+ *
+ * \param chain    points to the start of the chain
+ * \param buf      buffer holding the certificate data
+ * \param buflen   size of the buffer
+ *
+ * \return         0 if all certificates parsed successfully, a positive number
+ *                 if partly successful or a specific X509 or PEM error code
+ */
+int x509parse_crt( x509_cert *chain, const unsigned char *buf, size_t buflen );
+
+/** \ingroup x509_module */
+/**
+ * \brief          Load one or more certificates and add them
+ *                 to the chained list. Parses permissively. If some
+ *                 certificates can be parsed, the result is the number
+ *                 of failed certificates it encountered. If none complete
+ *                 correctly, the first error is returned.
+ *
+ * \param chain    points to the start of the chain
+ * \param path     filename to read the certificates from
+ *
+ * \return         0 if all certificates parsed successfully, a positive number
+ *                 if partly successful or a specific X509 or PEM error code
+ */
+int x509parse_crtfile( x509_cert *chain, const char *path );
+
+/** \ingroup x509_module */
+/**
+ * \brief          Parse one or more CRLs and add them
+ *                 to the chained list
+ *
+ * \param chain    points to the start of the chain
+ * \param buf      buffer holding the CRL data
+ * \param buflen   size of the buffer
+ *
+ * \return         0 if successful, or a specific X509 or PEM error code
+ */
+int x509parse_crl( x509_crl *chain, const unsigned char *buf, size_t buflen );
+
+/** \ingroup x509_module */
+/**
+ * \brief          Load one or more CRLs and add them
+ *                 to the chained list
+ *
+ * \param chain    points to the start of the chain
+ * \param path     filename to read the CRLs from
+ *
+ * \return         0 if successful, or a specific X509 or PEM error code
+ */
+int x509parse_crlfile( x509_crl *chain, const char *path );
+
+/** \ingroup x509_module */
+/**
+ * \brief          Parse a private RSA key
+ *
+ * \param rsa      RSA context to be initialized
+ * \param key      input buffer
+ * \param keylen   size of the buffer
+ * \param pwd      password for decryption (optional)
+ * \param pwdlen   size of the password
+ *
+ * \return         0 if successful, or a specific X509 or PEM error code
+ */
+int x509parse_key( rsa_context *rsa,
+                   const unsigned char *key, size_t keylen,
+                   const unsigned char *pwd, size_t pwdlen );
+
+/** \ingroup x509_module */
+/**
+ * \brief          Load and parse a private RSA key
+ *
+ * \param rsa      RSA context to be initialized
+ * \param path     filename to read the private key from
+ * \param password password to decrypt the file (can be NULL)
+ *
+ * \return         0 if successful, or a specific X509 or PEM error code
+ */
+int x509parse_keyfile( rsa_context *rsa, const char *path,
+                       const char *password );
+
+/** \ingroup x509_module */
+/**
+ * \brief          Parse a public RSA key
+ *
+ * \param rsa      RSA context to be initialized
+ * \param key      input buffer
+ * \param keylen   size of the buffer
+ *
+ * \return         0 if successful, or a specific X509 or PEM error code
+ */
+int x509parse_public_key( rsa_context *rsa,
+                   const unsigned char *key, size_t keylen );
+
+/** \ingroup x509_module */
+/**
+ * \brief          Load and parse a public RSA key
+ *
+ * \param rsa      RSA context to be initialized
+ * \param path     filename to read the private key from
+ *
+ * \return         0 if successful, or a specific X509 or PEM error code
+ */
+int x509parse_public_keyfile( rsa_context *rsa, const char *path );
+
+/** \ingroup x509_module */
+/**
+ * \brief          Parse DHM parameters
+ *
+ * \param dhm      DHM context to be initialized
+ * \param dhmin    input buffer
+ * \param dhminlen size of the buffer
+ *
+ * \return         0 if successful, or a specific X509 or PEM error code
+ */
+int x509parse_dhm( dhm_context *dhm, const unsigned char *dhmin, size_t dhminlen );
+
+/** \ingroup x509_module */
+/**
+ * \brief          Load and parse DHM parameters
+ *
+ * \param dhm      DHM context to be initialized
+ * \param path     filename to read the DHM Parameters from
+ *
+ * \return         0 if successful, or a specific X509 or PEM error code
+ */
+int x509parse_dhmfile( dhm_context *dhm, const char *path );
+
+/** \} name Functions to read in DHM parameters, a certificate, CRL or private RSA key */
+
+/**
+ * \brief          Store the certificate DN in printable form into buf;
+ *                 no more than size characters will be written.
+ *
+ * \param buf      Buffer to write to
+ * \param size     Maximum size of buffer
+ * \param dn       The X509 name to represent
+ *
+ * \return         The amount of data written to the buffer, or -1 in
+ *                 case of an error.
+ */
+int x509parse_dn_gets( char *buf, size_t size, const x509_name *dn );
+
+/**
+ * \brief          Store the certificate serial in printable form into buf;
+ *                 no more than size characters will be written.
+ *
+ * \param buf      Buffer to write to
+ * \param size     Maximum size of buffer
+ * \param serial   The X509 serial to represent
+ *
+ * \return         The amount of data written to the buffer, or -1 in
+ *                 case of an error.
+ */
+int x509parse_serial_gets( char *buf, size_t size, const x509_buf *serial );
+
+/**
+ * \brief          Returns an informational string about the
+ *                 certificate.
+ *
+ * \param buf      Buffer to write to
+ * \param size     Maximum size of buffer
+ * \param prefix   A line prefix
+ * \param crt      The X509 certificate to represent
+ *
+ * \return         The amount of data written to the buffer, or -1 in
+ *                 case of an error.
+ */
+int x509parse_cert_info( char *buf, size_t size, const char *prefix,
+                         const x509_cert *crt );
+
+/**
+ * \brief          Returns an informational string about the
+ *                 CRL.
+ *
+ * \param buf      Buffer to write to
+ * \param size     Maximum size of buffer
+ * \param prefix   A line prefix
+ * \param crl      The X509 CRL to represent
+ *
+ * \return         The amount of data written to the buffer, or -1 in
+ *                 case of an error.
+ */
+int x509parse_crl_info( char *buf, size_t size, const char *prefix,
+                        const x509_crl *crl );
+
+/**
+ * \brief          Give an known OID, return its descriptive string.
+ *
+ * \param oid      buffer containing the oid
+ *
+ * \return         Return a string if the OID is known,
+ *                 or NULL otherwise.
+ */
+const char *x509_oid_get_description( x509_buf *oid );
+
+/*
+ * \brief          Give an OID, return a string version of its OID number.
+ *
+ * \param buf      Buffer to write to
+ * \param size     Maximum size of buffer
+ * \param oid      Buffer containing the OID
+ *
+ * \return         The amount of data written to the buffer, or -1 in
+ *                 case of an error.
+ */
+int x509_oid_get_numeric_string( char *buf, size_t size, x509_buf *oid );
+
+/**
+ * \brief          Check a given x509_time against the system time and check
+ *                 if it is valid.
+ *
+ * \param time     x509_time to check
+ *
+ * \return         Return 0 if the x509_time is still valid,
+ *                 or 1 otherwise.
+ */
+int x509parse_time_expired( const x509_time *time );
+
+/**
+ * \name Functions to verify a certificate
+ * \{
+ */
+/** \ingroup x509_module */
+/**
+ * \brief          Verify the certificate signature
+ *
+ * \param crt      a certificate to be verified
+ * \param trust_ca the trusted CA chain
+ * \param ca_crl   the CRL chain for trusted CA's
+ * \param cn       expected Common Name (can be set to
+ *                 NULL if the CN must not be verified)
+ * \param flags    result of the verification
+ * \param f_vrfy   verification function
+ * \param p_vrfy   verification parameter
+ *
+ * \return         0 if successful or POLARSSL_ERR_X509_SIG_VERIFY_FAILED,
+ *                 in which case *flags will have one or more of
+ *                 the following values set:
+ *                      BADCERT_EXPIRED --
+ *                      BADCERT_REVOKED --
+ *                      BADCERT_CN_MISMATCH --
+ *                      BADCERT_NOT_TRUSTED
+ *
+ * \note           TODO: add two arguments, depth and crl
+ */
+int x509parse_verify( x509_cert *crt,
+                      x509_cert *trust_ca,
+                      x509_crl *ca_crl,
+                      const char *cn, int *flags,
+                      int (*f_vrfy)(void *, x509_cert *, int, int),
+                      void *p_vrfy );
+
+/**
+ * \brief          Verify the certificate signature
+ *
+ * \param crt      a certificate to be verified
+ * \param crl      the CRL to verify against
+ *
+ * \return         1 if the certificate is revoked, 0 otherwise
+ *
+ */
+int x509parse_revoked( const x509_cert *crt, const x509_crl *crl );
+
+/** \} name Functions to verify a certificate */
+
+
+
+/**
+ * \name Functions to clear a certificate, CRL or private RSA key 
+ * \{
+ */
+/** \ingroup x509_module */
+/**
+ * \brief          Unallocate all certificate data
+ *
+ * \param crt      Certificate chain to free
+ */
+void x509_free( x509_cert *crt );
+
+/** \ingroup x509_module */
+/**
+ * \brief          Unallocate all CRL data
+ *
+ * \param crl      CRL chain to free
+ */
+void x509_crl_free( x509_crl *crl );
+
+/** \} name Functions to clear a certificate, CRL or private RSA key */
+
+
+/**
+ * \brief          Checkup routine
+ *
+ * \return         0 if successful, or 1 if the test failed
+ */
+int x509_self_test( int verbose );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* x509.h */
diff --git a/include/linux/stat.h b/include/linux/stat.h
new file mode 100755
index 0000000..2f7a3b3
--- /dev/null
+++ b/include/linux/stat.h
@@ -0,0 +1,132 @@
+#ifndef _LINUX_STAT_H
+#define _LINUX_STAT_H
+
+#include <linux/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define S_IFMT  00170000	/* type of file */
+#define S_IFSOCK 0140000	/* named socket */
+#define S_IFLNK	 0120000	/* symbolic link */
+#define S_IFREG  0100000	/* regular */
+#define S_IFBLK  0060000	/* block special */
+#define S_IFDIR  0040000	/* directory */
+#define S_IFCHR  0020000	/* character special */
+#define S_IFIFO  0010000	/* fifo */
+#define S_ISUID  0004000	/* set user id on execution */
+#define S_ISGID  0002000	/* set group id on execution */
+#define S_ISVTX  0001000	/* save swapped text even after use */
+
+#define S_ISLNK(m)	(((m) & S_IFMT) == S_IFLNK)
+#define S_ISREG(m)	(((m) & S_IFMT) == S_IFREG)
+#define S_ISDIR(m)	(((m) & S_IFMT) == S_IFDIR)
+#define S_ISCHR(m)	(((m) & S_IFMT) == S_IFCHR)
+#define S_ISBLK(m)	(((m) & S_IFMT) == S_IFBLK)
+#define S_ISFIFO(m)	(((m) & S_IFMT) == S_IFIFO)
+#define S_ISSOCK(m)	(((m) & S_IFMT) == S_IFSOCK)
+
+#define S_IRWXU 00700		/* rwx for owner */
+#define S_IRUSR 00400		/* read permission for owner */
+#define S_IWUSR 00200		/* write permission for owner */
+#define S_IXUSR 00100		/* execute/search permission for owner */
+
+#define S_IRWXG 00070		/* rwx for group */
+#define S_IRGRP 00040		/* read permission for group */
+#define S_IWGRP 00020		/* write permission for group */
+#define S_IXGRP 00010		/* execute/search permission for group */
+
+#define S_IRWXO 00007		/* rwx for other */
+#define S_IROTH 00004		/* read permission for other */
+#define S_IWOTH 00002		/* read permission for other */
+#define S_IXOTH 00001		/* execute/search permission for other */
+
+#ifdef	__PPC__
+
+struct stat {
+	dev_t		st_dev;		/* file system id */
+	ino_t		st_ino;		/* file id */
+	mode_t		st_mode;	/* ownership/protection */
+	nlink_t		st_nlink;	/* number of links */
+	uid_t 		st_uid;		/* user id */
+	gid_t 		st_gid;		/* group id */
+	dev_t		st_rdev;
+	off_t		st_size;	/* file size in # of bytes */
+	unsigned long  	st_blksize;	/* block size */
+	unsigned long  	st_blocks;	/* file size in # of blocks */
+	unsigned long  	st_atime;	/* time file was last accessed */
+	unsigned long  	__unused1;
+	unsigned long  	st_mtime;	/* time file was last modified */
+	unsigned long  	__unused2;
+	unsigned long  	st_ctime;	/* time file status was last changed */
+	unsigned long  	__unused3;
+	unsigned long  	__unused4;
+	unsigned long  	__unused5;
+};
+
+#endif	/* __PPC__ */
+
+#if defined (__ARM__) || defined (__I386__) || defined (__M68K__)
+
+struct stat {
+	unsigned short st_dev;
+	unsigned short __pad1;
+	unsigned long st_ino;
+	unsigned short st_mode;
+	unsigned short st_nlink;
+	unsigned short st_uid;
+	unsigned short st_gid;
+	unsigned short st_rdev;
+	unsigned short __pad2;
+	unsigned long  st_size;
+	unsigned long  st_blksize;
+	unsigned long  st_blocks;
+	unsigned long  st_atime;
+	unsigned long  __unused1;
+	unsigned long  st_mtime;
+	unsigned long  __unused2;
+	unsigned long  st_ctime;
+	unsigned long  __unused3;
+	unsigned long  __unused4;
+	unsigned long  __unused5;
+};
+
+#endif	/* __ARM__ */
+
+#if defined (__MIPS__)
+
+struct stat {
+	dev_t           st_dev;
+	long            st_pad1[3];
+	ino_t           st_ino;
+	mode_t          st_mode;
+	nlink_t         st_nlink;
+	uid_t           st_uid;
+	gid_t           st_gid;
+	dev_t           st_rdev;
+	long            st_pad2[2];
+	off_t           st_size;
+	long            st_pad3;
+	/*
+	 * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+	 * but we don't have it under Linux.
+	 */
+	time_t          st_atime;
+	long            reserved0;
+	time_t          st_mtime;
+	long            reserved1;
+	time_t          st_ctime;
+	long            reserved2;
+	long            st_blksize;
+	long            st_blocks;
+	long            st_pad4[14];
+};
+
+#endif	/* __MIPS__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/linux/stddef.h b/include/linux/stddef.h
new file mode 100755
index 0000000..81e34c2
--- /dev/null
+++ b/include/linux/stddef.h
@@ -0,0 +1,18 @@
+#ifndef _LINUX_STDDEF_H
+#define _LINUX_STDDEF_H
+
+#undef NULL
+#if defined(__cplusplus)
+#define NULL 0
+#else
+#define NULL ((void *)0)
+#endif
+
+#ifndef _SIZE_T
+#include <linux/types.h>
+#endif
+
+#undef offsetof
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+
+#endif
diff --git a/include/linux/string.h b/include/linux/string.h
new file mode 100755
index 0000000..1a45fd3
--- /dev/null
+++ b/include/linux/string.h
@@ -0,0 +1,89 @@
+#ifndef _LINUX_STRING_H_
+#define _LINUX_STRING_H_
+
+#include <linux/types.h>	/* for size_t */
+#include <linux/stddef.h>	/* for NULL */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern char * ___strtok;
+extern char * strpbrk(const char *,const char *);
+extern char * strtok(char *,const char *);
+extern char * strsep(char **,const char *);
+extern __kernel_size_t strspn(const char *,const char *);
+
+
+/*
+ * Include machine specific inline routines
+ */
+#include <asm/string.h>
+
+#ifndef __HAVE_ARCH_STRCPY
+extern char * strcpy(char *,const char *);
+#endif
+#ifndef __HAVE_ARCH_STRNCPY
+extern char * strncpy(char *,const char *, __kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_STRCAT
+extern char * strcat(char *, const char *);
+#endif
+#ifndef __HAVE_ARCH_STRNCAT
+extern char * strncat(char *, const char *, __kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_STRCMP
+extern int strcmp(const char *,const char *);
+#endif
+#ifndef __HAVE_ARCH_STRNCMP
+extern int strncmp(const char *,const char *,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_STRNICMP
+extern int strnicmp(const char *, const char *, __kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_STRCHR
+extern char * strchr(const char *,int);
+#endif
+#ifndef __HAVE_ARCH_STRRCHR
+extern char * strrchr(const char *,int);
+#endif
+#ifndef __HAVE_ARCH_STRSTR
+extern char * strstr(const char *,const char *);
+#endif
+#ifndef __HAVE_ARCH_STRLEN
+extern __kernel_size_t strlen(const char *);
+#endif
+#ifndef __HAVE_ARCH_STRNLEN
+extern __kernel_size_t strnlen(const char *,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_STRDUP
+extern char * strdup(const char *);
+#endif
+#ifndef __HAVE_ARCH_STRSWAB
+extern char * strswab(const char *);
+#endif
+
+#ifndef __HAVE_ARCH_MEMSET
+extern void * memset(void *,int,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *,const void *,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMMOVE
+extern void * memmove(void *,const void *,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMSCAN
+extern void * memscan(void *,int,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMCMP
+extern int memcmp(const void *,const void *,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMCHR
+extern void * memchr(const void *,int,__kernel_size_t);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _LINUX_STRING_H_ */
diff --git a/include/linux/time.h b/include/linux/time.h
new file mode 100755
index 0000000..bf12b99
--- /dev/null
+++ b/include/linux/time.h
@@ -0,0 +1,158 @@
+#ifndef _LINUX_TIME_H
+#define _LINUX_TIME_H
+
+#include <linux/types.h>
+
+#define _DEFUN(a,b,c) a(c)
+#define _CONST const
+#define _AND ,
+
+#define _REENT_ONLY
+
+#define SECSPERMIN	60L
+#define MINSPERHOUR	60L
+#define HOURSPERDAY	24L
+#define SECSPERHOUR	(SECSPERMIN * MINSPERHOUR)
+#define SECSPERDAY	(SECSPERHOUR * HOURSPERDAY)
+#define DAYSPERWEEK	7
+#define MONSPERYEAR	12
+
+#define YEAR_BASE	1900
+#define EPOCH_YEAR      1970
+#define EPOCH_WDAY      4
+
+#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0)
+
+
+/* Used by other time functions.  */
+struct tm {
+    int tm_sec;                   /* Seconds.     [0-60] (1 leap second) */
+    int tm_min;                   /* Minutes.     [0-59] */
+    int tm_hour;                  /* Hours.       [0-23] */
+    int tm_mday;                  /* Day.         [1-31] */
+    int tm_mon;                   /* Month.       [0-11] */
+    int tm_year;                  /* Year - 1900.  */
+    int tm_wday;                  /* Day of week. [0-6] */
+    int tm_yday;                  /* Days in year.[0-365] */
+    int tm_isdst;                 /* DST.         [-1/0/1]*/
+
+# ifdef __USE_BSD
+    long int tm_gmtoff;           /* Seconds east of UTC.  */
+    __const char *tm_zone;        /* Timezone abbreviation.  */
+# else
+    long int __tm_gmtoff;         /* Seconds east of UTC.  */
+    __const char *__tm_zone;      /* Timezone abbreviation.  */
+# endif
+};
+
+static inline char *
+_DEFUN (asctime_r, (tim_p, result),
+	_CONST struct tm *tim_p _AND
+	char *result)
+{
+    static _CONST char day_name[7][3] = {
+	"Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat"
+    };
+    static _CONST char mon_name[12][3] = {
+	"Jan", "Feb", "Mar", "Apr", "May", "Jun",
+	"Jul", "Aug", "Sep", "Oct", "Nov", "Dec"
+    };
+
+    sprintf (result, "%.3s %.3s %.2d %.2d:%.2d:%.2d %d\n",
+	    day_name[tim_p->tm_wday],
+	    mon_name[tim_p->tm_mon],
+	    tim_p->tm_mday, tim_p->tm_hour, tim_p->tm_min,
+	    tim_p->tm_sec, 1900 + tim_p->tm_year);
+    return result;
+}
+
+static inline struct tm *
+_DEFUN (localtime_r, (tim_p, res),
+	_CONST time_t * tim_p _AND
+	struct tm *res)
+{
+    static _CONST int mon_lengths[2][MONSPERYEAR] = {
+      {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31},
+      {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}
+    } ;
+
+    static _CONST int year_lengths[2] = {
+      365,
+      366
+    } ;
+
+    long days, rem;
+    int y;
+    int yleap;
+    _CONST int *ip;
+
+    days = ((long) *tim_p) / SECSPERDAY;
+    rem = ((long) *tim_p) % SECSPERDAY;
+    while (rem < 0)
+    {
+	rem += SECSPERDAY;
+	--days;
+    }
+    while (rem >= SECSPERDAY)
+    {
+	rem -= SECSPERDAY;
+	++days;
+    }
+
+    /* compute hour, min, and sec */
+    res->tm_hour = (int) (rem / SECSPERHOUR);
+    rem %= SECSPERHOUR;
+    res->tm_min = (int) (rem / SECSPERMIN);
+    res->tm_sec = (int) (rem % SECSPERMIN);
+
+    /* compute day of week */
+    if ((res->tm_wday = ((EPOCH_WDAY + days) % DAYSPERWEEK)) < 0)
+	res->tm_wday += DAYSPERWEEK;
+
+    /* compute year & day of year */
+    y = EPOCH_YEAR;
+    if (days >= 0)
+    {
+	for (;;)
+	{
+	    yleap = isleap(y);
+	    if (days < year_lengths[yleap])
+		break;
+	    y++;
+	    days -= year_lengths[yleap];
+	}
+    }
+    else
+    {
+	do
+	{
+	    --y;
+	    yleap = isleap(y);
+	    days += year_lengths[yleap];
+	} while (days < 0);
+    }
+
+    res->tm_year = y - YEAR_BASE;
+    res->tm_yday = days;
+    ip = mon_lengths[yleap];
+    for (res->tm_mon = 0; days >= ip[res->tm_mon]; ++res->tm_mon)
+	days -= ip[res->tm_mon];
+    res->tm_mday = days + 1;
+
+    /* set daylight saving time flag */
+    res->tm_isdst = -1;
+
+    return (res);
+}
+
+static inline char *
+_DEFUN (ctime_r, (tim_p, result),
+	_CONST time_t * tim_p _AND
+	char * result)
+
+{
+    struct tm tm;
+    return asctime_r (localtime_r (tim_p, &tm), result);
+}
+
+#endif
diff --git a/include/linux/types.h b/include/linux/types.h
new file mode 100755
index 0000000..1b0b4a4
--- /dev/null
+++ b/include/linux/types.h
@@ -0,0 +1,154 @@
+#ifndef _LINUX_TYPES_H
+#define _LINUX_TYPES_H
+
+#ifdef	__KERNEL__
+#include <linux/config.h>
+#endif
+
+#include <linux/posix_types.h>
+#include <asm/types.h>
+
+#ifndef __KERNEL_STRICT_NAMES
+
+typedef __kernel_fd_set		fd_set;
+typedef __kernel_dev_t		dev_t;
+typedef __kernel_ino_t		ino_t;
+typedef __kernel_mode_t		mode_t;
+typedef __kernel_nlink_t	nlink_t;
+typedef __kernel_off_t		off_t;
+typedef __kernel_pid_t		pid_t;
+typedef __kernel_daddr_t	daddr_t;
+typedef __kernel_key_t		key_t;
+typedef __kernel_suseconds_t	suseconds_t;
+
+#ifdef __KERNEL__
+typedef __kernel_uid32_t	uid_t;
+typedef __kernel_gid32_t	gid_t;
+typedef __kernel_uid16_t        uid16_t;
+typedef __kernel_gid16_t        gid16_t;
+
+#ifdef CONFIG_UID16
+/* This is defined by include/asm-{arch}/posix_types.h */
+typedef __kernel_old_uid_t	old_uid_t;
+typedef __kernel_old_gid_t	old_gid_t;
+#endif /* CONFIG_UID16 */
+
+/* libc5 includes this file to define uid_t, thus uid_t can never change
+ * when it is included by non-kernel code
+ */
+#else
+typedef __kernel_uid_t		uid_t;
+typedef __kernel_gid_t		gid_t;
+#endif /* __KERNEL__ */
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __kernel_loff_t		loff_t;
+#endif
+
+/*
+ * The following typedefs are also protected by individual ifdefs for
+ * historical reasons:
+ */
+#ifndef _SIZE_T
+#define _SIZE_T
+typedef __kernel_size_t		size_t;
+#endif
+
+#ifndef _SSIZE_T
+#define _SSIZE_T
+typedef __kernel_ssize_t	ssize_t;
+#endif
+
+#ifndef _PTRDIFF_T
+#define _PTRDIFF_T
+typedef __kernel_ptrdiff_t	ptrdiff_t;
+#endif
+
+#ifndef _TIME_T
+#define _TIME_T
+typedef __kernel_time_t		time_t;
+#endif
+
+#ifndef _CLOCK_T
+#define _CLOCK_T
+typedef __kernel_clock_t	clock_t;
+#endif
+
+#ifndef _CADDR_T
+#define _CADDR_T
+typedef __kernel_caddr_t	caddr_t;
+#endif
+
+/* bsd */
+typedef unsigned char		u_char;
+typedef unsigned short		u_short;
+typedef unsigned int		u_int;
+typedef unsigned long		u_long;
+
+/* sysv */
+typedef unsigned char		unchar;
+typedef unsigned short		ushort;
+typedef unsigned int		uint;
+typedef unsigned long		ulong;
+
+#ifndef __BIT_TYPES_DEFINED__
+#define __BIT_TYPES_DEFINED__
+
+typedef		__u8		u_int8_t;
+typedef		__s8		int8_t;
+typedef		__u16		u_int16_t;
+typedef		__s16		int16_t;
+typedef		__u32		u_int32_t;
+typedef		__s32		int32_t;
+
+#endif /* !(__BIT_TYPES_DEFINED__) */
+
+typedef		__u8		uint8_t;
+typedef		__u16		uint16_t;
+typedef		__u32		uint32_t;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef		__u64		uint64_t;
+typedef		__u64		u_int64_t;
+typedef		__s64		int64_t;
+#endif
+
+#endif /* __KERNEL_STRICT_NAMES */
+
+/*
+ * Below are truly Linux-specific types that should never collide with
+ * any application/library that wants linux/types.h.
+ */
+#ifdef __CHECKER__
+#define __bitwise__ __attribute__((bitwise))
+#else
+#define __bitwise__
+#endif
+#ifdef __CHECK_ENDIAN__
+#define __bitwise __bitwise__
+#else
+#define __bitwise
+#endif
+
+typedef __u16 __bitwise __le16;
+typedef __u16 __bitwise __be16;
+typedef __u32 __bitwise __le32;
+typedef __u32 __bitwise __be32;
+#if defined(__GNUC__)
+typedef __u64 __bitwise __le64;
+typedef __u64 __bitwise __be64;
+#endif
+typedef __u16 __bitwise __sum16;
+typedef __u32 __bitwise __wsum;
+
+
+typedef unsigned __bitwise__	gfp_t;
+
+struct ustat {
+	__kernel_daddr_t	f_tfree;
+	__kernel_ino_t		f_tinode;
+	char			f_fname[6];
+	char			f_fpack[6];
+};
+
+#endif /* _LINUX_TYPES_H */
diff --git a/include/linux/unaligned/access_ok.h b/include/linux/unaligned/access_ok.h
new file mode 100755
index 0000000..5f46eee
--- /dev/null
+++ b/include/linux/unaligned/access_ok.h
@@ -0,0 +1,66 @@
+#ifndef _LINUX_UNALIGNED_ACCESS_OK_H
+#define _LINUX_UNALIGNED_ACCESS_OK_H
+
+#include <asm/byteorder.h>
+
+static inline u16 get_unaligned_le16(const void *p)
+{
+	return le16_to_cpup((__le16 *)p);
+}
+
+static inline u32 get_unaligned_le32(const void *p)
+{
+	return le32_to_cpup((__le32 *)p);
+}
+
+static inline u64 get_unaligned_le64(const void *p)
+{
+	return le64_to_cpup((__le64 *)p);
+}
+
+static inline u16 get_unaligned_be16(const void *p)
+{
+	return be16_to_cpup((__be16 *)p);
+}
+
+static inline u32 get_unaligned_be32(const void *p)
+{
+	return be32_to_cpup((__be32 *)p);
+}
+
+static inline u64 get_unaligned_be64(const void *p)
+{
+	return be64_to_cpup((__be64 *)p);
+}
+
+static inline void put_unaligned_le16(u16 val, void *p)
+{
+	*((__le16 *)p) = cpu_to_le16(val);
+}
+
+static inline void put_unaligned_le32(u32 val, void *p)
+{
+	*((__le32 *)p) = cpu_to_le32(val);
+}
+
+static inline void put_unaligned_le64(u64 val, void *p)
+{
+	*((__le64 *)p) = cpu_to_le64(val);
+}
+
+static inline void put_unaligned_be16(u16 val, void *p)
+{
+	*((__be16 *)p) = cpu_to_be16(val);
+}
+
+static inline void put_unaligned_be32(u32 val, void *p)
+{
+	*((__be32 *)p) = cpu_to_be32(val);
+}
+
+static inline void put_unaligned_be64(u64 val, void *p)
+{
+	*((__be64 *)p) = cpu_to_be64(val);
+}
+
+#endif /* _LINUX_UNALIGNED_ACCESS_OK_H */
diff --git a/include/linux/unaligned/be_byteshift.h b/include/linux/unaligned/be_byteshift.h
new file mode 100755
index 0000000..9356b24
--- /dev/null
+++ b/include/linux/unaligned/be_byteshift.h
@@ -0,0 +1,70 @@
+#ifndef _LINUX_UNALIGNED_BE_BYTESHIFT_H
+#define _LINUX_UNALIGNED_BE_BYTESHIFT_H
+
+#include <linux/types.h>
+
+static inline u16 __get_unaligned_be16(const u8 *p)
+{
+	return p[0] << 8 | p[1];
+}
+
+static inline u32 __get_unaligned_be32(const u8 *p)
+{
+	return p[0] << 24 | p[1] << 16 | p[2] << 8 | p[3];
+}
+
+static inline u64 __get_unaligned_be64(const u8 *p)
+{
+	return (u64)__get_unaligned_be32(p) << 32 |
+	       __get_unaligned_be32(p + 4);
+}
+
+static inline void __put_unaligned_be16(u16 val, u8 *p)
+{
+	*p++ = val >> 8;
+	*p++ = val;
+}
+
+static inline void __put_unaligned_be32(u32 val, u8 *p)
+{
+	__put_unaligned_be16(val >> 16, p);
+	__put_unaligned_be16(val, p + 2);
+}
+
+static inline void __put_unaligned_be64(u64 val, u8 *p)
+{
+	__put_unaligned_be32(val >> 32, p);
+	__put_unaligned_be32(val, p + 4);
+}
+
+static inline u16 get_unaligned_be16(const void *p)
+{
+	return __get_unaligned_be16((const u8 *)p);
+}
+
+static inline u32 get_unaligned_be32(const void *p)
+{
+	return __get_unaligned_be32((const u8 *)p);
+}
+
+static inline u64 get_unaligned_be64(const void *p)
+{
+	return __get_unaligned_be64((const u8 *)p);
+}
+
+static inline void put_unaligned_be16(u16 val, void *p)
+{
+	__put_unaligned_be16(val, p);
+}
+
+static inline void put_unaligned_be32(u32 val, void *p)
+{
+	__put_unaligned_be32(val, p);
+}
+
+static inline void put_unaligned_be64(u64 val, void *p)
+{
+	__put_unaligned_be64(val, p);
+}
+
+#endif /* _LINUX_UNALIGNED_BE_BYTESHIFT_H */
diff --git a/include/linux/unaligned/generic.h b/include/linux/unaligned/generic.h
new file mode 100755
index 0000000..cc688e1
--- /dev/null
+++ b/include/linux/unaligned/generic.h
@@ -0,0 +1,71 @@
+#ifndef _LINUX_UNALIGNED_GENERIC_H
+#define _LINUX_UNALIGNED_GENERIC_H
+
+/* define __force to nothing in U-Boot */
+#define __force
+
+/*
+ * Cause a link-time error if we try an unaligned access other than
+ * 1,2,4 or 8 bytes long
+ */
+extern void __bad_unaligned_access_size(void);
+
+#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr),			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)),	\
+	__bad_unaligned_access_size()))));					\
+	}))
+
+#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr),			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)),	\
+	__bad_unaligned_access_size()))));					\
+	}))
+
+#define __put_unaligned_le(val, ptr) ({					\
+	void *__gu_p = (ptr);						\
+	switch (sizeof(*(ptr))) {					\
+	case 1:								\
+		*(u8 *)__gu_p = (__force u8)(val);			\
+		break;							\
+	case 2:								\
+		put_unaligned_le16((__force u16)(val), __gu_p);		\
+		break;							\
+	case 4:								\
+		put_unaligned_le32((__force u32)(val), __gu_p);		\
+		break;							\
+	case 8:								\
+		put_unaligned_le64((__force u64)(val), __gu_p);		\
+		break;							\
+	default:							\
+		__bad_unaligned_access_size();				\
+		break;							\
+	}								\
+	(void)0; })
+
+#define __put_unaligned_be(val, ptr) ({					\
+	void *__gu_p = (ptr);						\
+	switch (sizeof(*(ptr))) {					\
+	case 1:								\
+		*(u8 *)__gu_p = (__force u8)(val);			\
+		break;							\
+	case 2:								\
+		put_unaligned_be16((__force u16)(val), __gu_p);		\
+		break;							\
+	case 4:								\
+		put_unaligned_be32((__force u32)(val), __gu_p);		\
+		break;							\
+	case 8:								\
+		put_unaligned_be64((__force u64)(val), __gu_p);		\
+		break;							\
+	default:							\
+		__bad_unaligned_access_size();				\
+		break;							\
+	}								\
+	(void)0; })
+
+#endif /* _LINUX_UNALIGNED_GENERIC_H */
diff --git a/include/linux/unaligned/le_byteshift.h b/include/linux/unaligned/le_byteshift.h
new file mode 100755
index 0000000..be376fb
--- /dev/null
+++ b/include/linux/unaligned/le_byteshift.h
@@ -0,0 +1,70 @@
+#ifndef _LINUX_UNALIGNED_LE_BYTESHIFT_H
+#define _LINUX_UNALIGNED_LE_BYTESHIFT_H
+
+#include <linux/types.h>
+
+static inline u16 __get_unaligned_le16(const u8 *p)
+{
+	return p[0] | p[1] << 8;
+}
+
+static inline u32 __get_unaligned_le32(const u8 *p)
+{
+	return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24;
+}
+
+static inline u64 __get_unaligned_le64(const u8 *p)
+{
+	return (u64)__get_unaligned_le32(p + 4) << 32 |
+	       __get_unaligned_le32(p);
+}
+
+static inline void __put_unaligned_le16(u16 val, u8 *p)
+{
+	*p++ = val;
+	*p++ = val >> 8;
+}
+
+static inline void __put_unaligned_le32(u32 val, u8 *p)
+{
+	__put_unaligned_le16(val >> 16, p + 2);
+	__put_unaligned_le16(val, p);
+}
+
+static inline void __put_unaligned_le64(u64 val, u8 *p)
+{
+	__put_unaligned_le32(val >> 32, p + 4);
+	__put_unaligned_le32(val, p);
+}
+
+static inline u16 get_unaligned_le16(const void *p)
+{
+	return __get_unaligned_le16((const u8 *)p);
+}
+
+static inline u32 get_unaligned_le32(const void *p)
+{
+	return __get_unaligned_le32((const u8 *)p);
+}
+
+static inline u64 get_unaligned_le64(const void *p)
+{
+	return __get_unaligned_le64((const u8 *)p);
+}
+
+static inline void put_unaligned_le16(u16 val, void *p)
+{
+	__put_unaligned_le16(val, p);
+}
+
+static inline void put_unaligned_le32(u32 val, void *p)
+{
+	__put_unaligned_le32(val, p);
+}
+
+static inline void put_unaligned_le64(u64 val, void *p)
+{
+	__put_unaligned_le64(val, p);
+}
+
+#endif /* _LINUX_UNALIGNED_LE_BYTESHIFT_H */
diff --git a/include/linux_logo.h b/include/linux_logo.h
new file mode 100755
index 0000000..9aa712e
--- /dev/null
+++ b/include/linux_logo.h
@@ -0,0 +1,1445 @@
+/* $Id: linux_logo.h,v 1.5 1998/07/30 16:30:58 jj Exp $
+ * include/linux/linux_logo.h: This is a linux logo
+ *                             to be displayed on boot.
+ *
+ * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu)
+ * Copyright (C) 1996,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ *
+ * You can put anything here, but:
+ * LINUX_LOGO_COLORS has to be less than 224
+ * image size has to be 80x80
+ * values have to start from 0x20
+ * (i.e. RGB(linux_logo_red[0],
+ *           linux_logo_green[0],
+ *           linux_logo_blue[0]) is color 0x20)
+ * BW image has to be 80x80 as well, with MS bit
+ * on the left
+ * Serial_console ascii image can be any size,
+ * but should contain %s to display the version
+ */
+
+#if LINUX_LOGO_COLORS == 214
+
+unsigned char linux_logo_red[] __initdata = {
+  0x02, 0x9E, 0xE9, 0xC4, 0x50, 0xC9, 0xC4, 0xE9,
+  0x65, 0xE3, 0xC2, 0x25, 0xA4, 0xEC, 0x90, 0xA6,
+  0xC4, 0x6A, 0xD1, 0xF3, 0x12, 0xED, 0xA0, 0xC2,
+  0xB8, 0xD5, 0xDB, 0xD2, 0x3E, 0x16, 0xEB, 0x54,
+  0xA9, 0xCD, 0xF5, 0x0A, 0xBA, 0xB3, 0xDC, 0x74,
+  0xCE, 0xF6, 0xD3, 0xC5, 0xEA, 0xB8, 0xED, 0x5E,
+  0xE5, 0x26, 0xF4, 0xA9, 0x82, 0x94, 0xE6, 0x38,
+  0xF2, 0x0F, 0x7F, 0x49, 0xE5, 0xF4, 0xD3, 0xC3,
+  0xC2, 0x1E, 0xD5, 0xC6, 0xA4, 0xFA, 0x0A, 0xBA,
+  0xD4, 0xEB, 0xEA, 0xEC, 0xA8, 0xBC, 0xB4, 0xDC,
+  0x84, 0xE4, 0xCE, 0xEC, 0x92, 0xCD, 0xDC, 0x8B,
+  0xCC, 0x1E, 0xF6, 0xB2, 0x60, 0x2A, 0x96, 0x52,
+  0x0F, 0xBD, 0xFA, 0xCC, 0xB8, 0x7A, 0x4C, 0xD2,
+  0x06, 0xEF, 0x44, 0x64, 0xF4, 0xBA, 0xCE, 0xE6,
+  0x8A, 0x6F, 0x3C, 0x70, 0x7C, 0x9C, 0xBA, 0xDF,
+  0x2C, 0x4D, 0x3B, 0xCA, 0xDE, 0xCE, 0xEE, 0x46,
+  0x6A, 0xAC, 0x96, 0xE5, 0x96, 0x7A, 0xBA, 0xB6,
+  0xE2, 0x7E, 0xAA, 0xC5, 0x96, 0x9E, 0xC2, 0xAA,
+  0xDA, 0x35, 0xB6, 0x82, 0x88, 0xBE, 0xC2, 0x9E,
+  0xB4, 0xD5, 0xDA, 0x9C, 0xA0, 0xD0, 0xA8, 0xC7,
+  0x72, 0xF2, 0xDB, 0x76, 0xDC, 0xBE, 0xAA, 0xF4,
+  0x87, 0x2F, 0x53, 0x8E, 0x36, 0xCE, 0xE6, 0xCA,
+  0xCB, 0xE4, 0xD6, 0xAA, 0x42, 0x5D, 0xB4, 0x59,
+  0x1C, 0xC8, 0x96, 0x6C, 0xDA, 0xCE, 0xE6, 0xCB,
+  0x96, 0x16, 0xFA, 0xBE, 0xAE, 0xFE, 0x6E, 0xD6,
+  0xCE, 0xB6, 0xE5, 0xED, 0xDB, 0xDC, 0xF4, 0x72,
+  0x1F, 0xAE, 0xE6, 0xC2, 0xCA, 0xC4
+};
+
+unsigned char linux_logo_green[] __initdata = {
+  0x02, 0x88, 0xC4, 0x85, 0x44, 0xA2, 0xA8, 0xE5,
+  0x65, 0xA6, 0xC2, 0x24, 0xA4, 0xB4, 0x62, 0x86,
+  0x94, 0x44, 0xD2, 0xB6, 0x12, 0xD4, 0x73, 0x96,
+  0x92, 0x95, 0xB2, 0xC2, 0x36, 0x0E, 0xBC, 0x54,
+  0x75, 0xA5, 0xF5, 0x0A, 0xB2, 0x83, 0xC2, 0x74,
+  0x9B, 0xBD, 0xA2, 0xCA, 0xDA, 0x8C, 0xCB, 0x42,
+  0xAC, 0x12, 0xDA, 0x7B, 0x54, 0x94, 0xD2, 0x24,
+  0xBE, 0x06, 0x65, 0x33, 0xBB, 0xBC, 0xAB, 0x8C,
+  0x92, 0x1E, 0x9B, 0xB6, 0x6E, 0xFB, 0x04, 0xA2,
+  0xC8, 0xBD, 0xAD, 0xEC, 0x92, 0xBC, 0x7B, 0x9D,
+  0x84, 0xC4, 0xC4, 0xB4, 0x6C, 0x93, 0xA3, 0x5E,
+  0x8D, 0x13, 0xD6, 0x82, 0x4C, 0x2A, 0x7A, 0x5A,
+  0x0D, 0x82, 0xBB, 0xCC, 0x8B, 0x6A, 0x3C, 0xBE,
+  0x06, 0xC4, 0x44, 0x45, 0xDB, 0x96, 0xB6, 0xDE,
+  0x8A, 0x4D, 0x3C, 0x5A, 0x7C, 0x9C, 0xAA, 0xCB,
+  0x1C, 0x4D, 0x2E, 0xB2, 0xBE, 0xAA, 0xDE, 0x3E,
+  0x6A, 0xAC, 0x82, 0xE5, 0x72, 0x62, 0x92, 0x9E,
+  0xCA, 0x4A, 0x8E, 0xBE, 0x86, 0x6B, 0xAA, 0x9A,
+  0xBE, 0x34, 0xAB, 0x76, 0x6E, 0x9A, 0x9E, 0x62,
+  0x76, 0xCE, 0xD3, 0x92, 0x7C, 0xB8, 0x7E, 0xC6,
+  0x5E, 0xE2, 0xC3, 0x54, 0xAA, 0x9E, 0x8A, 0xCA,
+  0x63, 0x2D, 0x3B, 0x8E, 0x1A, 0x9E, 0xC2, 0xA6,
+  0xCB, 0xDC, 0xD6, 0x8E, 0x26, 0x5C, 0xB4, 0x45,
+  0x1C, 0xB8, 0x6E, 0x4C, 0xBC, 0xAE, 0xD6, 0x92,
+  0x63, 0x16, 0xF6, 0x8C, 0x7A, 0xFE, 0x6E, 0xBA,
+  0xC6, 0x86, 0xAA, 0xAE, 0xDB, 0xA4, 0xD4, 0x56,
+  0x0E, 0x6E, 0xB6, 0xB2, 0xBE, 0xBE
+};
+
+unsigned char linux_logo_blue[] __initdata = {
+  0x04, 0x28, 0x10, 0x0B, 0x14, 0x14, 0x74, 0xC7,
+  0x64, 0x0E, 0xC3, 0x24, 0xA4, 0x0C, 0x10, 0x20,
+  0x0D, 0x04, 0xD1, 0x0D, 0x13, 0x22, 0x0A, 0x40,
+  0x14, 0x0C, 0x11, 0x94, 0x0C, 0x08, 0x0B, 0x56,
+  0x09, 0x47, 0xF4, 0x0B, 0x9C, 0x07, 0x54, 0x74,
+  0x0F, 0x0C, 0x0F, 0xC7, 0x6C, 0x14, 0x14, 0x11,
+  0x0B, 0x04, 0x12, 0x0C, 0x05, 0x94, 0x94, 0x0A,
+  0x34, 0x09, 0x14, 0x08, 0x2F, 0x15, 0x19, 0x11,
+  0x28, 0x0C, 0x0B, 0x94, 0x08, 0xFA, 0x08, 0x7C,
+  0xBC, 0x15, 0x0A, 0xEC, 0x64, 0xBB, 0x0A, 0x0C,
+  0x84, 0x2C, 0xA0, 0x15, 0x10, 0x0D, 0x0B, 0x0E,
+  0x0A, 0x07, 0x10, 0x3C, 0x24, 0x2C, 0x28, 0x5C,
+  0x0A, 0x0D, 0x0A, 0xC1, 0x22, 0x4C, 0x10, 0x94,
+  0x04, 0x0F, 0x45, 0x08, 0x31, 0x54, 0x3C, 0xBC,
+  0x8C, 0x09, 0x3C, 0x18, 0x7C, 0x9C, 0x7C, 0x91,
+  0x0C, 0x4D, 0x17, 0x74, 0x0C, 0x48, 0x9C, 0x3C,
+  0x6A, 0xAC, 0x5C, 0xE3, 0x29, 0x3C, 0x2C, 0x7C,
+  0x6C, 0x04, 0x14, 0xA9, 0x74, 0x07, 0x2C, 0x74,
+  0x4C, 0x34, 0x97, 0x5C, 0x38, 0x0C, 0x5C, 0x04,
+  0x0C, 0xBA, 0xBC, 0x78, 0x18, 0x88, 0x24, 0xC2,
+  0x3C, 0xB4, 0x87, 0x0C, 0x14, 0x4C, 0x3C, 0x10,
+  0x17, 0x2C, 0x0A, 0x8C, 0x04, 0x1C, 0x44, 0x2C,
+  0xCD, 0xD8, 0xD4, 0x34, 0x0C, 0x5B, 0xB4, 0x1E,
+  0x1D, 0xAC, 0x24, 0x18, 0x20, 0x5C, 0xB4, 0x1C,
+  0x09, 0x14, 0xFC, 0x0C, 0x10, 0xFC, 0x6C, 0x7C,
+  0xB4, 0x1C, 0x15, 0x17, 0xDB, 0x18, 0x21, 0x24,
+  0x04, 0x04, 0x44, 0x8C, 0x8C, 0xB7
+};
+
+unsigned char linux_logo[] __initdata = {
+  0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, 0x2C, 0x2C,
+  0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, 0x2C, 0x95,
+  0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, 0xD6, 0x2C,
+  0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, 0x6D, 0xD6,
+  0xA1, 0x2C, 0x55, 0x95, 0x2C, 0x2C, 0x55, 0x55,
+  0x95, 0xA1, 0xA1, 0xA1, 0x6D, 0xBF, 0x2A, 0x2A,
+  0xBF, 0x83, 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1,
+  0x2C, 0x2C, 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95,
+  0x2C, 0x95, 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6,
+  0xD6, 0x2C, 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A,
+  0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C, 0x2C, 0x95,
+  0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0xCB,
+  0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6, 0xA1, 0x2C,
+  0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6, 0xA1, 0x2C,
+  0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x2C, 0x2C,
+  0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xD6, 0xD6, 0xD6,
+  0xD6, 0xD6, 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C,
+  0x2C, 0x95, 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55,
+  0x55, 0xCB, 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6,
+  0xA1, 0x2C, 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6,
+  0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1, 0x2C, 0x95,
+  0x55, 0x55, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x70,
+  0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C,
+  0x95, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C,
+  0x95, 0x55, 0xCB, 0x95, 0xD6, 0xA1, 0x2C, 0x95,
+  0xA1, 0xD6, 0xD6, 0xA1, 0xA1, 0xD6, 0xA1, 0xA1,
+  0xA1, 0x2C, 0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1,
+  0x2C, 0x95, 0x55, 0x55, 0x90, 0xCB, 0x55, 0x55,
+  0x55, 0x70, 0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6,
+  0xA1, 0x2C, 0x95, 0x95, 0x2C, 0xD6, 0xD6, 0xA1,
+  0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
+  0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0xCB,
+  0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C,
+  0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x95,
+  0x55, 0x55, 0x2C, 0x3F, 0x80, 0x20, 0x88, 0x88,
+  0x88, 0x20, 0x88, 0xB1, 0x2C, 0xA1, 0x2C, 0x2C,
+  0x95, 0xCB, 0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6,
+  0xA1, 0x95, 0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55,
+  0xCB, 0xCB, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6,
+  0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C,
+  0x55, 0x55, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55,
+  0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x95,
+  0x55, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
+  0x2C, 0x94, 0x80, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x88, 0x92, 0xA1, 0x95,
+  0x55, 0x90, 0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6,
+  0xA1, 0x2C, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x55,
+  0x55, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1,
+  0x2C, 0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95,
+  0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0x95,
+  0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55, 0x2C, 0x2C,
+  0xA1, 0xD6, 0xA1, 0xA1, 0x2C, 0x2C, 0x95, 0x55,
+  0x55, 0x55, 0x95, 0x95, 0x2C, 0x95, 0x95, 0xD6,
+  0xB1, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x80, 0x34, 0x88, 0x43, 0x47,
+  0x95, 0xCB, 0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6,
+  0xA1, 0x95, 0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55,
+  0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0x2C,
+  0x55, 0x55, 0x55, 0x55, 0x2C, 0x95, 0x2C, 0x2C,
+  0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x55,
+  0x90, 0x70, 0x90, 0x55, 0x95, 0x95, 0xA1, 0xA1,
+  0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x95,
+  0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD5,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x88, 0x7D, 0x3F, 0xB1, 0x80, 0x20,
+  0x99, 0x2C, 0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1,
+  0x2C, 0x55, 0x90, 0x70, 0x90, 0x55, 0x95, 0x95,
+  0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C,
+  0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1, 0x95, 0xCB,
+  0x70, 0x94, 0x90, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
+  0x2C, 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95,
+  0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0xA1, 0x88,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0xB1, 0x47, 0xD5, 0x7D, 0x43,
+  0x20, 0x70, 0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
+  0x95, 0xCB, 0x70, 0x94, 0x90, 0x55, 0x95, 0xA1,
+  0xA1, 0xA1, 0x2C, 0x95, 0x2C, 0x2C, 0x95, 0x95,
+  0x95, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95,
+  0x95, 0x90, 0x55, 0x2C, 0xD6, 0xD6, 0x2C, 0x90,
+  0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xA1,
+  0x95, 0x95, 0x95, 0x2C, 0x2C, 0x95, 0x55, 0x55,
+  0xCB, 0xCB, 0xCB, 0x55, 0xCB, 0x55, 0x47, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x88, 0xB1, 0x3F, 0x92, 0x2B, 0x80,
+  0x20, 0x80, 0xD6, 0x70, 0x55, 0x2C, 0xD6, 0xD6,
+  0x2C, 0x90, 0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6,
+  0xD6, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x95,
+  0x95, 0x55, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x55,
+  0xD6, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x55, 0x70,
+  0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x95,
+  0x55, 0x55, 0x55, 0x95, 0x55, 0x55, 0xCB, 0x90,
+  0x70, 0x90, 0xCB, 0x55, 0x55, 0xA1, 0xD8, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x88, 0xD8, 0xE1, 0x88, 0x20, 0x20,
+  0x88, 0x88, 0xE6, 0x55, 0x2C, 0xA1, 0xD6, 0xA1,
+  0x55, 0x70, 0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
+  0xA1, 0x95, 0x55, 0x55, 0x95, 0x95, 0x55, 0x55,
+  0x90, 0x90, 0x90, 0x90, 0xCB, 0x55, 0x55, 0x55,
+  0xD6, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0xCB, 0x70,
+  0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x55,
+  0xCB, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
+  0x55, 0x95, 0x2C, 0x95, 0x2C, 0xD6, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x80, 0xD6, 0xA1, 0xD6, 0xD6, 0xA1,
+  0xCB, 0x70, 0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C,
+  0x2C, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0x55, 0x55,
+  0x55, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xD6, 0xA1, 0xA1, 0xA1, 0xA1, 0x55, 0x70, 0x94,
+  0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95, 0xCB, 0x55,
+  0x90, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x95, 0xA1,
+  0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x95, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x88, 0x95, 0xA1, 0xA1, 0xA1, 0x55,
+  0x70, 0x94, 0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95,
+  0xCB, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x55,
+  0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
+  0x2C, 0x2C, 0x2C, 0x95, 0x95, 0xCB, 0x70, 0x70,
+  0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x70, 0x90, 0xCB,
+  0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x2C, 0xD6,
+  0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x70, 0x20, 0x20,
+  0x88, 0x43, 0xD8, 0x43, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x88, 0x88, 0x43, 0x2B, 0xD8, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x3F, 0x2C, 0x95, 0x95, 0xCB,
+  0x70, 0x70, 0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x90,
+  0x90, 0xCB, 0x55, 0xCB, 0x55, 0xCB, 0x55, 0x95,
+  0x2C, 0xD6, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C,
+  0xA1, 0x95, 0x95, 0x55, 0xCB, 0x70, 0x90, 0x55,
+  0x2C, 0x2C, 0x2C, 0x55, 0x70, 0x70, 0x55, 0x95,
+  0x95, 0xCB, 0x90, 0x90, 0x90, 0x95, 0x2C, 0xA1,
+  0xD6, 0xD6, 0x2C, 0x2C, 0x95, 0x70, 0x20, 0x20,
+  0x80, 0x2B, 0x34, 0x2B, 0x88, 0x20, 0x20, 0x20,
+  0x88, 0xB1, 0x28, 0x28, 0x2B, 0x7D, 0x80, 0x20,
+  0x20, 0x20, 0x20, 0x92, 0x95, 0x55, 0xCB, 0x70,
+  0x90, 0x55, 0x2C, 0x2C, 0x2C, 0x55, 0x70, 0x70,
+  0x55, 0x95, 0x55, 0x55, 0x90, 0x90, 0x90, 0x55,
+  0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x95,
+  0xA1, 0x95, 0x55, 0xCB, 0x90, 0x70, 0xCB, 0x95,
+  0xA1, 0x95, 0x95, 0xCB, 0x90, 0xCB, 0x95, 0x2C,
+  0x95, 0x70, 0x70, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
+  0x2C, 0x2C, 0x55, 0xCB, 0x55, 0x90, 0x20, 0x34,
+  0x90, 0x6D, 0x70, 0xD8, 0x43, 0x20, 0x20, 0x88,
+  0x3F, 0x55, 0xA1, 0x2A, 0xD6, 0x7D, 0x43, 0x20,
+  0x20, 0x20, 0x88, 0x7D, 0x55, 0xCB, 0x90, 0x70,
+  0xCB, 0x95, 0xA1, 0x95, 0x95, 0xCB, 0x70, 0xCB,
+  0x95, 0xA1, 0x95, 0x70, 0x70, 0xCB, 0x55, 0x2C,
+  0xA1, 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x55, 0x95,
+  0x2C, 0x55, 0x90, 0x70, 0x94, 0x90, 0x95, 0x2C,
+  0x2C, 0x95, 0xCB, 0x90, 0x55, 0x95, 0xA1, 0xA1,
+  0x95, 0x90, 0x90, 0x95, 0xA1, 0xD6, 0xD6, 0x6D,
+  0xA1, 0x95, 0x55, 0xCB, 0x55, 0xCB, 0x20, 0x99,
+  0xBF, 0xA3, 0xA3, 0x90, 0x20, 0x20, 0x20, 0x92,
+  0x83, 0x6B, 0x6B, 0x6B, 0xA3, 0x70, 0x88, 0x20,
+  0x20, 0x20, 0x20, 0x2B, 0x90, 0x70, 0x94, 0x90,
+  0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x90, 0x55, 0x95,
+  0xA1, 0x2C, 0x55, 0x90, 0x90, 0x95, 0xA1, 0xD6,
+  0xD6, 0x6D, 0xA1, 0x95, 0x55, 0xCB, 0x55, 0x55,
+  0x2C, 0x55, 0x70, 0x70, 0x94, 0x90, 0x95, 0x2C,
+  0x2C, 0x55, 0xCB, 0xCB, 0x95, 0x2C, 0x2C, 0x2C,
+  0x55, 0x55, 0x95, 0xA1, 0x6D, 0xBF, 0x6D, 0xD6,
+  0x95, 0x55, 0x90, 0xCB, 0x55, 0x95, 0x88, 0x95,
+  0x2C, 0x3F, 0x6D, 0x6B, 0x34, 0x20, 0x20, 0x47,
+  0x65, 0xD6, 0xE1, 0x3F, 0x2A, 0x6B, 0x2B, 0x20,
+  0x20, 0x20, 0x20, 0x43, 0x70, 0x70, 0x94, 0x90,
+  0x95, 0x2C, 0x2C, 0x55, 0x55, 0x55, 0x95, 0x2C,
+  0xA1, 0x2C, 0x55, 0xCB, 0x95, 0xA1, 0x6D, 0xBF,
+  0x6D, 0xD6, 0x2C, 0x55, 0x90, 0xCB, 0x95, 0x95,
+  0x95, 0x55, 0x70, 0x94, 0x70, 0x55, 0x2C, 0xA1,
+  0x2C, 0x55, 0xCB, 0x55, 0x2C, 0x95, 0x2C, 0x95,
+  0x95, 0x95, 0xA1, 0x6D, 0xBF, 0x2A, 0xD6, 0x95,
+  0x70, 0x94, 0x94, 0x70, 0x55, 0x55, 0x20, 0xBF,
+  0xC9, 0xB1, 0x99, 0x42, 0xB1, 0x61, 0x7D, 0x94,
+  0x65, 0xB1, 0x88, 0x99, 0xD5, 0xE5, 0x7F, 0x20,
+  0x20, 0x20, 0x20, 0x43, 0x70, 0x94, 0x70, 0x55,
+  0x2C, 0xA1, 0x2C, 0x55, 0x90, 0x55, 0x2C, 0x95,
+  0x2C, 0x95, 0x95, 0x2C, 0xA1, 0x6D, 0xBF, 0xBF,
+  0xD6, 0x55, 0x70, 0x94, 0x94, 0x70, 0xCB, 0x55,
+  0x55, 0xCB, 0x70, 0x94, 0x70, 0x95, 0xA1, 0xA1,
+  0x95, 0x55, 0x55, 0x95, 0x2C, 0x95, 0x95, 0x95,
+  0x95, 0xA1, 0x6D, 0x2A, 0x2A, 0xD6, 0x55, 0x94,
+  0xE6, 0xE6, 0x47, 0x70, 0x55, 0x95, 0x20, 0x2A,
+  0xD8, 0x43, 0xC9, 0x83, 0x98, 0x79, 0x34, 0x9F,
+  0x6B, 0x43, 0x20, 0x88, 0x2B, 0x65, 0xA0, 0x20,
+  0x20, 0x20, 0x20, 0xE1, 0x70, 0x94, 0x70, 0x95,
+  0xA1, 0xA1, 0x95, 0x55, 0x55, 0x95, 0x2C, 0x95,
+  0x95, 0x95, 0x95, 0xA1, 0x6D, 0xBF, 0x2A, 0xD6,
+  0x55, 0x94, 0xE6, 0xE6, 0x47, 0x70, 0x55, 0x55,
+  0x94, 0x70, 0x94, 0x47, 0x70, 0x95, 0x2C, 0x2C,
+  0x95, 0xCB, 0x95, 0x2C, 0x2C, 0xA1, 0x2C, 0x2C,
+  0xA1, 0xD6, 0x6D, 0x6D, 0xA1, 0xCB, 0x47, 0x28,
+  0xE6, 0x47, 0x70, 0x55, 0x95, 0xA1, 0x20, 0x2C,
+  0x7F, 0x88, 0xF0, 0xC6, 0x25, 0x5E, 0xCF, 0x2F,
+  0xE7, 0x9A, 0x20, 0x88, 0x99, 0x65, 0x3F, 0x20,
+  0x20, 0x20, 0x20, 0x34, 0x94, 0x47, 0x70, 0x95,
+  0xA1, 0x2C, 0x55, 0xCB, 0x95, 0x2C, 0x2C, 0xA1,
+  0x2C, 0x2C, 0xA1, 0xD6, 0x6D, 0x6D, 0xA1, 0xCB,
+  0x94, 0x28, 0xA0, 0x47, 0x70, 0x55, 0x95, 0x95,
+  0x47, 0x70, 0x90, 0x94, 0x70, 0x95, 0xA1, 0x2C,
+  0x55, 0x55, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C,
+  0xA1, 0x6D, 0x2A, 0xD6, 0x55, 0x47, 0x28, 0x28,
+  0x47, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0x20, 0x28,
+  0xEC, 0x86, 0xBE, 0x48, 0x3E, 0x3E, 0x3A, 0x25,
+  0x4E, 0xAE, 0x93, 0xD7, 0xEC, 0xD1, 0x34, 0x20,
+  0x20, 0x20, 0x20, 0x43, 0x55, 0x94, 0x70, 0x95,
+  0xA1, 0xA1, 0x55, 0xCB, 0x2C, 0xA1, 0xA1, 0xA1,
+  0xA1, 0x2C, 0xA1, 0x6D, 0x6D, 0xD6, 0x55, 0x47,
+  0x28, 0x28, 0x47, 0x70, 0x55, 0x95, 0x2C, 0x2C,
+  0x95, 0x95, 0x55, 0x90, 0xCB, 0x2C, 0xA1, 0xA1,
+  0x55, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0xA1, 0x2C,
+  0xD6, 0x6D, 0x6D, 0xA1, 0x70, 0x28, 0xD5, 0xE6,
+  0x70, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0x20, 0xE1,
+  0x26, 0x84, 0x76, 0x73, 0x9C, 0x22, 0x4E, 0x35,
+  0x8C, 0x7A, 0x4E, 0xDC, 0x8E, 0x7E, 0x3D, 0x88,
+  0x20, 0x20, 0x20, 0x88, 0x2C, 0x90, 0x90, 0x95,
+  0xA1, 0x2C, 0x55, 0x55, 0x2C, 0xD6, 0xD6, 0xD6,
+  0x2C, 0x2C, 0xD6, 0x2A, 0x6D, 0x2C, 0x70, 0x28,
+  0xD5, 0xE6, 0x70, 0x55, 0x95, 0xA1, 0x2C, 0xA1,
+  0xBF, 0xA1, 0x95, 0xCB, 0xCB, 0x2C, 0xA1, 0xA1,
+  0x95, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C, 0x95,
+  0xD6, 0x6D, 0xD6, 0x95, 0x94, 0x28, 0xE6, 0x70,
+  0x55, 0x95, 0xA1, 0xA1, 0xA1, 0xD6, 0x20, 0x57,
+  0xE4, 0xDF, 0x50, 0x3E, 0x22, 0x4E, 0x35, 0x8C,
+  0x8C, 0x52, 0x52, 0x7A, 0x4E, 0x58, 0xD7, 0x20,
+  0x20, 0x20, 0x20, 0x88, 0x2C, 0xCB, 0x55, 0x2C,
+  0xA1, 0xA1, 0x95, 0x95, 0xA1, 0xD6, 0xD6, 0xA1,
+  0x2C, 0x95, 0xA1, 0x6D, 0x6D, 0x95, 0x47, 0xA0,
+  0xE6, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0xA1,
+  0xD2, 0x95, 0x55, 0x90, 0x55, 0x2C, 0xD6, 0xA1,
+  0x95, 0x95, 0xA1, 0xD6, 0xD6, 0x2C, 0x95, 0x2C,
+  0xA1, 0x6D, 0xA1, 0x55, 0x94, 0x47, 0x94, 0xCB,
+  0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6, 0x59, 0xC8,
+  0xE3, 0x76, 0x2D, 0x3E, 0x22, 0x4E, 0x8C, 0x35,
+  0x52, 0x52, 0xEE, 0x3A, 0x4D, 0xED, 0x24, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x28, 0xCB, 0x55, 0x2C,
+  0xD6, 0xA1, 0x95, 0x95, 0xA1, 0xD6, 0xA1, 0x2C,
+  0x95, 0x2C, 0xD6, 0x6D, 0xA1, 0x55, 0x94, 0xE6,
+  0x70, 0xCB, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xA1,
+  0xD0, 0x94, 0x94, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
+  0x55, 0x95, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x2C,
+  0xA1, 0xD6, 0x2C, 0x70, 0x94, 0x94, 0x94, 0x94,
+  0x70, 0x55, 0xA1, 0xD6, 0xA1, 0xD6, 0x88, 0x77,
+  0x38, 0xC4, 0x3E, 0x69, 0x4E, 0x35, 0x8C, 0xEE,
+  0x35, 0x89, 0x30, 0x30, 0x4A, 0x48, 0x3C, 0x20,
+  0x20, 0x88, 0x20, 0x20, 0xD8, 0x2C, 0x55, 0x2C,
+  0xD6, 0xA1, 0x95, 0x95, 0x2C, 0xD6, 0xA1, 0x2C,
+  0x95, 0x2C, 0xA1, 0xD6, 0x2C, 0x90, 0x94, 0x47,
+  0x94, 0x94, 0x70, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
+  0x95, 0x28, 0x47, 0x90, 0x95, 0x2C, 0xA1, 0x2C,
+  0x95, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C,
+  0xA1, 0xA1, 0x55, 0x70, 0x94, 0x47, 0x94, 0x94,
+  0x70, 0x2C, 0xD6, 0xD6, 0x2C, 0xA1, 0x43, 0x98,
+  0x54, 0x48, 0x3E, 0x22, 0x35, 0xEE, 0xEE, 0x9C,
+  0x4D, 0x45, 0x75, 0x4A, 0xDF, 0x7B, 0x3D, 0x20,
+  0xD8, 0x28, 0x2B, 0x88, 0x20, 0x95, 0x95, 0x2C,
+  0xA1, 0x2C, 0x55, 0x55, 0x2C, 0xA1, 0xD6, 0xA1,
+  0x2C, 0x95, 0xA1, 0x2C, 0x55, 0x70, 0x94, 0x94,
+  0x94, 0x94, 0x70, 0x95, 0xD6, 0xD6, 0x2C, 0x95,
+  0x70, 0x28, 0x47, 0x55, 0x95, 0x2C, 0x2C, 0x2C,
+  0x95, 0x95, 0x95, 0xA1, 0xA1, 0xA1, 0x95, 0x55,
+  0x95, 0x95, 0x55, 0x70, 0x70, 0x70, 0x94, 0x70,
+  0x55, 0xD6, 0x6D, 0xD6, 0x95, 0x2C, 0x20, 0x43,
+  0xBB, 0xC8, 0x36, 0x30, 0x30, 0x38, 0x45, 0x6E,
+  0xE3, 0x75, 0x78, 0x37, 0xBD, 0xD9, 0x3F, 0x20,
+  0x88, 0xD5, 0x70, 0xB1, 0x88, 0xA0, 0x95, 0x2C,
+  0x2C, 0xA1, 0x95, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
+  0x2C, 0x55, 0x95, 0x2C, 0x55, 0x70, 0x70, 0x70,
+  0x94, 0x70, 0x55, 0xD6, 0x6D, 0x6D, 0x95, 0x55,
+  0x94, 0x47, 0x70, 0x95, 0x2C, 0x2C, 0x2C, 0xA1,
+  0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x55,
+  0x55, 0x95, 0x95, 0x55, 0x55, 0x55, 0x55, 0x95,
+  0xA1, 0x6D, 0x4B, 0xD6, 0x55, 0xD6, 0x20, 0xD8,
+  0xD6, 0x67, 0xDA, 0x4D, 0xED, 0x62, 0x78, 0x78,
+  0x23, 0x84, 0x67, 0xF5, 0x4B, 0xBF, 0x90, 0x88,
+  0x88, 0x2B, 0x47, 0x99, 0x20, 0x43, 0xD6, 0x2C,
+  0x2C, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1,
+  0x95, 0x95, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55,
+  0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB,
+  0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
+  0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x95,
+  0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
+  0x6D, 0x2A, 0x2A, 0xA1, 0x55, 0x55, 0x20, 0xD8,
+  0x6D, 0xAB, 0x96, 0x7E, 0x64, 0x53, 0x36, 0x36,
+  0xC6, 0x63, 0x6D, 0xD0, 0x6B, 0xE5, 0xA3, 0x7D,
+  0x20, 0x88, 0x80, 0x88, 0x20, 0x20, 0xC9, 0xA1,
+  0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1,
+  0x95, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
+  0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55,
+  0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0xA1,
+  0xA1, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x95,
+  0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6,
+  0x6D, 0x6D, 0xA1, 0x55, 0x2C, 0xD8, 0x20, 0xB1,
+  0xA3, 0x4B, 0x6D, 0xD9, 0xA7, 0x6C, 0xAF, 0xB2,
+  0x6D, 0x2A, 0x83, 0x42, 0xE5, 0xE5, 0x65, 0x2C,
+  0x20, 0x20, 0x88, 0x20, 0x20, 0x20, 0x88, 0x95,
+  0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
+  0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1,
+  0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55,
+  0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x95, 0x2C,
+  0x2C, 0x95, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x95,
+  0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xA1,
+  0xA1, 0x2C, 0x55, 0x55, 0x28, 0x88, 0x43, 0x2A,
+  0xE5, 0xA3, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D,
+  0xBF, 0xA3, 0x42, 0xE5, 0xE5, 0xE5, 0xE5, 0x65,
+  0xB1, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0xD8,
+  0xD6, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x2C,
+  0x95, 0x95, 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1,
+  0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x90, 0x90, 0x55,
+  0x90, 0xCB, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95,
+  0x2C, 0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x55,
+  0x55, 0xCB, 0x55, 0x2C, 0x95, 0x95, 0x95, 0x95,
+  0x55, 0x90, 0x90, 0x90, 0xE1, 0x43, 0x28, 0xE5,
+  0xE5, 0x65, 0xD0, 0x6D, 0x6D, 0x6D, 0x2A, 0xD2,
+  0x42, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xD6, 0x20, 0x20, 0x20, 0x20, 0x20, 0x88, 0x88,
+  0xD5, 0x2C, 0x2C, 0x2C, 0x95, 0x55, 0x95, 0x95,
+  0x95, 0x55, 0x55, 0xCB, 0x55, 0x95, 0x2C, 0x95,
+  0x95, 0x95, 0x55, 0x90, 0x70, 0x70, 0x70, 0x90,
+  0x70, 0x70, 0xCB, 0x55, 0x55, 0x95, 0x95, 0x95,
+  0x2C, 0x95, 0x95, 0x55, 0x55, 0x55, 0x55, 0xCB,
+  0x70, 0x70, 0x70, 0xCB, 0x90, 0x90, 0x70, 0x94,
+  0x94, 0x94, 0x2C, 0x80, 0x20, 0xE1, 0xA3, 0xE5,
+  0xE5, 0xE5, 0x42, 0xEC, 0xD0, 0x83, 0xA3, 0x65,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0x65, 0x7D, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x88, 0x2C, 0x95, 0x95, 0x95, 0x55, 0x55, 0x55,
+  0x55, 0xCB, 0x70, 0x70, 0x90, 0x90, 0x90, 0x90,
+  0x70, 0x94, 0x94, 0x94, 0x70, 0x70, 0x70, 0x70,
+  0x70, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95, 0x95,
+  0x2C, 0x2C, 0x95, 0x55, 0x55, 0x55, 0x55, 0x55,
+  0x90, 0x70, 0x90, 0x55, 0x55, 0xCB, 0x70, 0x94,
+  0x94, 0x95, 0xD8, 0x20, 0x88, 0x70, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0x47, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0xE1, 0x6D, 0x2C, 0x95, 0x55, 0x55, 0x55,
+  0x55, 0x55, 0x90, 0x70, 0x70, 0x55, 0x55, 0xCB,
+  0x70, 0x94, 0x94, 0x94, 0x70, 0x90, 0x70, 0x94,
+  0x55, 0x2C, 0x2C, 0x2C, 0x95, 0x2C, 0x95, 0x95,
+  0x2C, 0x2C, 0x2C, 0x55, 0x55, 0x55, 0x55, 0x55,
+  0xCB, 0xCB, 0x95, 0x2C, 0x2C, 0x95, 0x55, 0x90,
+  0x55, 0x99, 0x20, 0x20, 0xE1, 0xA3, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xD6, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x2B, 0x6D, 0x95, 0x95, 0x55, 0x55,
+  0x55, 0x55, 0xCB, 0x55, 0x95, 0x2C, 0x2C, 0x95,
+  0x55, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x90, 0x70,
+  0x2C, 0xD6, 0xD6, 0x2C, 0x2C, 0x95, 0x95, 0x95,
+  0x95, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95,
+  0x95, 0x95, 0x2C, 0xA1, 0x2C, 0x95, 0x55, 0x95,
+  0xE6, 0x88, 0x20, 0x20, 0x3F, 0xA3, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0x42, 0xA3, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x88, 0x2B, 0xD6, 0x95, 0x95, 0x95,
+  0x95, 0x95, 0x95, 0x95, 0x2C, 0xA1, 0x2C, 0x95,
+  0x55, 0x55, 0x95, 0x95, 0x95, 0x55, 0x55, 0x55,
+  0xA1, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x2C,
+  0x2C, 0x2C, 0x95, 0x2C, 0x95, 0x95, 0x55, 0x95,
+  0x95, 0x2C, 0x2C, 0x2C, 0x95, 0xCB, 0xCB, 0x94,
+  0x20, 0x20, 0x20, 0x20, 0xE6, 0x83, 0x65, 0xE5,
+  0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0x6B, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0x6B, 0xA3, 0xD2,
+  0xD2, 0x6B, 0xC9, 0x20, 0x20, 0x88, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x88, 0x8A, 0xA1, 0x95, 0x95,
+  0x95, 0x55, 0x95, 0x2C, 0xA1, 0x2C, 0x95, 0xCB,
+  0xCB, 0x55, 0x95, 0x95, 0x95, 0x55, 0x55, 0x95,
+  0x6D, 0x6D, 0x6D, 0xD6, 0xA1, 0x2C, 0x2C, 0x95,
+  0x2C, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x95,
+  0x95, 0x95, 0x95, 0x55, 0x70, 0x70, 0x2C, 0x80,
+  0x88, 0x20, 0x20, 0x80, 0x94, 0xD6, 0x32, 0x6B,
+  0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xA3, 0xD2, 0xD0, 0xBF, 0x2A,
+  0x2A, 0xD0, 0x6D, 0x34, 0x20, 0xE1, 0x88, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x88, 0xA1, 0x95, 0x95,
+  0x95, 0x95, 0x95, 0x95, 0x95, 0x55, 0x70, 0x70,
+  0x70, 0x90, 0xCB, 0xCB, 0xCB, 0x95, 0x95, 0x2C,
+  0xD0, 0x6D, 0xD6, 0xD6, 0xA1, 0xA1, 0xA1, 0x2C,
+  0x2C, 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x55, 0x95,
+  0x95, 0x2C, 0x95, 0x55, 0xCB, 0xCB, 0x95, 0x88,
+  0x20, 0x20, 0x88, 0xD8, 0x2C, 0xD1, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0x65, 0x65, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0xEC,
+  0xBF, 0x2A, 0xEC, 0x95, 0x20, 0x34, 0x2B, 0xE1,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x99, 0x95, 0x55,
+  0x55, 0x55, 0x95, 0x95, 0x95, 0x55, 0xCB, 0xCB,
+  0x55, 0x55, 0xCB, 0xCB, 0xCB, 0x55, 0x95, 0x95,
+  0x32, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C,
+  0xA1, 0x95, 0x95, 0x95, 0x55, 0xCB, 0xCB, 0x55,
+  0x95, 0x95, 0x95, 0x95, 0x95, 0x55, 0x99, 0x20,
+  0xE1, 0xE1, 0x43, 0x47, 0x6B, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0x42, 0xEC, 0xBF, 0xA3, 0x8A, 0x20, 0x88, 0xD8,
+  0x2B, 0x20, 0x20, 0x20, 0x88, 0x88, 0x2C, 0xCB,
+  0xCB, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x55, 0x95,
+  0x55, 0x55, 0x55, 0x55, 0x55, 0x95, 0x55, 0x95,
+  0x6D, 0x55, 0x55, 0x55, 0x95, 0x95, 0x2C, 0x95,
+  0x2C, 0x95, 0x95, 0x55, 0x55, 0x55, 0x55, 0x95,
+  0x95, 0x95, 0x95, 0x95, 0x95, 0xA1, 0x34, 0x20,
+  0xC9, 0x20, 0xE1, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xA3, 0x83, 0x6D, 0x20, 0x88, 0x88,
+  0x2B, 0x34, 0x20, 0x20, 0x20, 0x88, 0xD5, 0x55,
+  0x55, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
+  0x95, 0x95, 0x95, 0x95, 0x55, 0x55, 0x95, 0x95,
+  0x2C, 0x55, 0xCB, 0x55, 0xCB, 0x55, 0x55, 0x95,
+  0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x2C, 0x95, 0x95, 0x55, 0x95, 0x2C, 0x20, 0xD8,
+  0xE1, 0x20, 0x70, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0x65, 0xA3, 0x92, 0x43, 0x7D,
+  0xD8, 0xC9, 0x88, 0x20, 0x20, 0x20, 0x43, 0xD6,
+  0x2C, 0x2C, 0x95, 0x95, 0x95, 0x55, 0x95, 0x2C,
+  0x95, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x95, 0x2C,
+  0xA1, 0x55, 0x55, 0x55, 0x55, 0x95, 0x95, 0x55,
+  0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0xA1, 0x2C,
+  0xA1, 0x2C, 0x2C, 0x95, 0x2C, 0x99, 0x88, 0xB1,
+  0x20, 0xD8, 0x42, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xCB, 0x34, 0x8A,
+  0xC9, 0x34, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x90,
+  0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x95, 0x95, 0x2C,
+  0x2C, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
+  0xD6, 0x2C, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C,
+  0x55, 0xCB, 0x55, 0x2C, 0x2C, 0xA1, 0x2C, 0xA1,
+  0xA1, 0xA1, 0x2C, 0x2C, 0x6D, 0x43, 0xD8, 0x80,
+  0x88, 0xCB, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x32, 0x80, 0xE1,
+  0x80, 0x20, 0xB1, 0x20, 0x20, 0x20, 0x20, 0xC9,
+  0xD6, 0xA1, 0xA1, 0xA1, 0x2C, 0xA1, 0x2C, 0x2C,
+  0x2C, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95, 0x55,
+  0xD6, 0x95, 0x95, 0x95, 0x2C, 0xA1, 0x2C, 0x2C,
+  0x95, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x95, 0x2C,
+  0x2C, 0x2C, 0x2C, 0x95, 0xCB, 0x20, 0xC9, 0x20,
+  0xE1, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0x42, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xD8, 0x20,
+  0x20, 0x20, 0x2B, 0x43, 0x20, 0x20, 0x20, 0x88,
+  0xD6, 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x55,
+  0x95, 0x55, 0x55, 0xCB, 0x55, 0xCB, 0xCB, 0x55,
+  0x2C, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0x95,
+  0x55, 0x95, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95,
+  0x55, 0xCB, 0x70, 0xCB, 0xC9, 0x80, 0x2B, 0x20,
+  0xA0, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0x42, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x92, 0x20,
+  0x20, 0x20, 0xE1, 0xD8, 0x20, 0x20, 0x20, 0x20,
+  0x95, 0x95, 0x55, 0xCB, 0x90, 0x90, 0x70, 0x90,
+  0x90, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x55, 0x95,
+  0x95, 0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
+  0x95, 0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x55,
+  0x90, 0x47, 0xA0, 0x55, 0x20, 0x2B, 0x43, 0x88,
+  0x6D, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x28, 0x20,
+  0x20, 0x20, 0xE1, 0xE1, 0x20, 0x20, 0x20, 0x20,
+  0x28, 0x55, 0x90, 0x47, 0xA0, 0x47, 0x94, 0x70,
+  0x55, 0x95, 0x95, 0x55, 0xCB, 0x55, 0x55, 0x2C,
+  0x2C, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
+  0x95, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x95, 0x55,
+  0x94, 0xE6, 0x70, 0x2B, 0x88, 0x2B, 0x88, 0xE1,
+  0x65, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x47, 0x20,
+  0x20, 0x20, 0xE1, 0x34, 0x20, 0x20, 0x20, 0x20,
+  0xB1, 0x95, 0x94, 0xE6, 0xA0, 0x47, 0x70, 0x55,
+  0x2C, 0xA1, 0x2C, 0x55, 0x90, 0xCB, 0x2C, 0xD6,
+  0x6D, 0xA1, 0x2C, 0x95, 0x95, 0xA1, 0x2C, 0xA1,
+  0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x95, 0x55,
+  0x70, 0xE6, 0x70, 0x20, 0x20, 0x7D, 0x20, 0x8A,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0x65, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x94, 0x20,
+  0x20, 0x20, 0xD8, 0x88, 0x20, 0x20, 0x20, 0x20,
+  0xD8, 0x2C, 0x94, 0x47, 0x47, 0x90, 0x95, 0x95,
+  0xA1, 0x6D, 0xA1, 0x90, 0x94, 0x55, 0x2C, 0xD6,
+  0xD0, 0xA1, 0x95, 0x95, 0x2C, 0x2C, 0xA1, 0x2C,
+  0x95, 0x95, 0x55, 0x55, 0x55, 0x95, 0x2C, 0x2C,
+  0xCB, 0x95, 0xD8, 0x20, 0x20, 0xB1, 0x88, 0x28,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE2, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xCB, 0x20,
+  0x20, 0x20, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x88, 0xD6, 0x55, 0x47, 0x94, 0x55, 0x2C, 0xA1,
+  0xA1, 0xD6, 0x95, 0x94, 0x94, 0x55, 0xD6, 0x6D,
+  0xBF, 0x95, 0x90, 0xCB, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x55, 0x95, 0xCB, 0x90, 0x90, 0x95, 0x2C, 0x95,
+  0x90, 0x70, 0x20, 0x20, 0x34, 0x8A, 0x20, 0x94,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0x65, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xCB, 0x20,
+  0x20, 0x88, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x88, 0xD6, 0xCB, 0x47, 0x94, 0x55, 0xA1, 0xD6,
+  0xD6, 0x2C, 0xCB, 0x47, 0x70, 0xA1, 0x6D, 0x2A,
+  0x95, 0x47, 0x47, 0x70, 0x95, 0xA1, 0x2C, 0x95,
+  0x55, 0x55, 0x90, 0x90, 0x55, 0x55, 0x55, 0x90,
+  0x47, 0xD5, 0x20, 0x20, 0x80, 0xD5, 0x43, 0xCB,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0x42, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xCB, 0x20,
+  0x20, 0x80, 0x34, 0x20, 0x20, 0x20, 0x88, 0x20,
+  0x20, 0x2C, 0x47, 0xE6, 0x70, 0x2C, 0xD6, 0xD6,
+  0xA1, 0x2C, 0x55, 0xCB, 0x95, 0xA1, 0x6D, 0xD6,
+  0x90, 0x47, 0x47, 0x90, 0x2C, 0xA1, 0x2C, 0x95,
+  0x55, 0x55, 0x90, 0x90, 0x55, 0x55, 0x55, 0x70,
+  0x94, 0x8A, 0x20, 0x88, 0x88, 0xE1, 0xD8, 0x95,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE2, 0x42, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x47, 0x20,
+  0x43, 0x7D, 0x43, 0x80, 0x88, 0x20, 0x20, 0x20,
+  0x88, 0xCB, 0x94, 0x70, 0x55, 0xA1, 0xD6, 0xD6,
+  0xA1, 0x2C, 0x2C, 0x95, 0xA1, 0xA1, 0xD6, 0xA1,
+  0x94, 0xE6, 0x47, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
+  0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0xCB,
+  0x55, 0xA0, 0x43, 0x86, 0x86, 0x43, 0xD8, 0xCB,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0x65, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x3F, 0x80,
+  0xD8, 0x80, 0x88, 0x34, 0xD8, 0x2B, 0xD8, 0x20,
+  0x99, 0x90, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6,
+  0xA1, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C,
+  0x55, 0x55, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55,
+  0x95, 0x44, 0xBC, 0x3E, 0x5D, 0xD3, 0x79, 0x92,
+  0xA3, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0x65, 0x42, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0x9A, 0x34,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x43, 0x99, 0xE1,
+  0x70, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xD6, 0xA1,
+  0x2C, 0x95, 0x55, 0x55, 0x95, 0x95, 0x95, 0x95,
+  0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0x95,
+  0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55, 0x2C, 0x2C,
+  0x32, 0x9D, 0xEB, 0x5D, 0x69, 0x49, 0x84, 0xF0,
+  0xB1, 0xEC, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0x42, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xC1, 0x4E, 0x21, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x34, 0xC9, 0xD8,
+  0xBB, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C,
+  0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C,
+  0x55, 0xCB, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x55,
+  0x90, 0x70, 0x90, 0x55, 0x95, 0x95, 0x6D, 0xD0,
+  0xC2, 0x48, 0x6A, 0x49, 0x69, 0x82, 0x5D, 0x2F,
+  0x59, 0x7D, 0xBF, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0x65, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xEA, 0xC7, 0x7E, 0x66,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x34, 0x43, 0x5A,
+  0x46, 0x27, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x95,
+  0x95, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1, 0x95, 0x55,
+  0x94, 0x94, 0x2C, 0x2A, 0x72, 0x3B, 0x56, 0xDD,
+  0xDF, 0x29, 0x5D, 0x49, 0x89, 0x5D, 0x3E, 0x69,
+  0x93, 0x66, 0x34, 0xA1, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0x65, 0x42, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xEA, 0x3E, 0x5A, 0x66,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x66, 0x5B, 0x73,
+  0x89, 0x4C, 0xBF, 0x2C, 0x95, 0x2C, 0x2C, 0x95,
+  0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
+  0x2C, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0x2C, 0xCB,
+  0x70, 0x55, 0xE7, 0x60, 0x4A, 0x48, 0xCD, 0x4A,
+  0x29, 0x73, 0x5D, 0x82, 0x49, 0x49, 0x49, 0x49,
+  0x3A, 0x57, 0x88, 0x88, 0x70, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0x42, 0x73, 0x50, 0xBE, 0x79,
+  0x20, 0x20, 0x20, 0x20, 0x66, 0xCC, 0x37, 0x9C,
+  0x3E, 0xCE, 0xBF, 0x95, 0x95, 0x95, 0x2C, 0x95,
+  0x95, 0x55, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0x55,
+  0xA1, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x55, 0x94,
+  0x94, 0xE8, 0x60, 0xC4, 0x3E, 0x2D, 0x2D, 0x2D,
+  0x33, 0x5D, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x89, 0xAA, 0x59, 0x20, 0x20, 0x28, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xEC, 0x4A, 0x2D, 0x50, 0x78, 0x2E,
+  0x57, 0x51, 0xF0, 0x57, 0x31, 0x4D, 0x50, 0x2D,
+  0x5D, 0xF2, 0xA1, 0x2C, 0x95, 0x95, 0x55, 0x55,
+  0x90, 0x90, 0x70, 0x90, 0xCB, 0x55, 0x55, 0x55,
+  0x6D, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0x55, 0x94,
+  0x70, 0xB9, 0x75, 0x50, 0x3E, 0x49, 0x49, 0x49,
+  0x5D, 0x82, 0x49, 0x49, 0x82, 0x49, 0x49, 0x49,
+  0x89, 0x69, 0x4F, 0x20, 0x20, 0x20, 0x8A, 0x42,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0x83, 0x4A, 0x3A, 0x50, 0x62, 0x23,
+  0x81, 0xB8, 0xB8, 0xE9, 0x5F, 0x29, 0x33, 0x5D,
+  0x5D, 0x73, 0xE8, 0xCB, 0x55, 0x55, 0x55, 0x55,
+  0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xD6, 0xA1, 0xA1, 0xA1, 0xA1, 0x55, 0x70, 0x70,
+  0xCB, 0x68, 0x75, 0x50, 0x82, 0x49, 0x49, 0x49,
+  0x5D, 0x49, 0x49, 0x5D, 0x49, 0x49, 0x5D, 0x82,
+  0x69, 0x5D, 0x25, 0xF0, 0x20, 0x20, 0x20, 0xE1,
+  0x2A, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0x4B, 0xF4, 0xDF, 0x50, 0x73, 0x76, 0x48,
+  0x75, 0xDF, 0x75, 0x62, 0xC4, 0x33, 0x82, 0x49,
+  0x5D, 0x5D, 0xA8, 0xF5, 0x55, 0x55, 0x55, 0x55,
+  0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
+  0x2C, 0x2C, 0x2C, 0x95, 0x95, 0xCB, 0x70, 0x70,
+  0x95, 0x83, 0x5F, 0xEA, 0x2D, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x5D, 0x49, 0x22, 0x5A, 0x79, 0x20, 0x20, 0x20,
+  0x80, 0xD2, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0x65, 0xD0, 0x63, 0x5F, 0x29, 0x2D, 0x2D, 0xEA,
+  0x29, 0x29, 0x76, 0x50, 0x2D, 0x82, 0x49, 0x49,
+  0x3E, 0x49, 0x5C, 0xB0, 0xBA, 0x95, 0x55, 0x55,
+  0x2C, 0xA1, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C,
+  0xA1, 0x95, 0x95, 0x55, 0xCB, 0x70, 0x70, 0x55,
+  0x2C, 0x83, 0x60, 0x76, 0x5D, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x5D, 0x89, 0xDC, 0x8B, 0x20, 0x20, 0x20,
+  0x20, 0x95, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE2, 0x32, 0x85, 0xE3, 0x29, 0x2D, 0x33, 0x2D,
+  0x2D, 0x2D, 0x6A, 0x2D, 0x33, 0x5D, 0x49, 0x82,
+  0x49, 0x49, 0x82, 0x73, 0x5C, 0x9E, 0x2C, 0x55,
+  0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x95,
+  0x2C, 0x95, 0x55, 0xCB, 0x90, 0x90, 0xCB, 0x95,
+  0x2C, 0x6D, 0x41, 0x6F, 0x3E, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x82, 0x3E, 0x4E, 0x38, 0xCA, 0x20, 0x20,
+  0x20, 0x55, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x65,
+  0x42, 0xA0, 0xD4, 0xE3, 0x29, 0x2D, 0x82, 0x5D,
+  0x5D, 0x82, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x3E, 0x49, 0x49, 0x49, 0x5C, 0x56, 0xD6,
+  0xA1, 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x55, 0x95,
+  0xA1, 0x55, 0x90, 0x70, 0x94, 0x70, 0x95, 0x2C,
+  0x2C, 0xD6, 0xDD, 0x6F, 0x33, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x5D, 0x5D, 0x82, 0x69, 0x22, 0x62, 0x80, 0x34,
+  0x94, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0xE5, 0x65, 0x6B,
+  0xD5, 0x88, 0x5B, 0xE3, 0x29, 0x5D, 0x5D, 0x5D,
+  0x5D, 0x5D, 0x5D, 0x5D, 0x49, 0x49, 0x49, 0x82,
+  0x49, 0x49, 0x89, 0x49, 0x82, 0x49, 0x71, 0xBA,
+  0x6D, 0x6D, 0xA1, 0x95, 0x55, 0xCB, 0x55, 0x55,
+  0x2C, 0x55, 0x70, 0x70, 0x70, 0x90, 0x95, 0xA1,
+  0x2C, 0xA1, 0x41, 0x76, 0x5D, 0x5D, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x5D, 0x82, 0x5D, 0x89, 0x5E, 0x96, 0x65,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0x65, 0xEC, 0xB1,
+  0x20, 0x20, 0xCA, 0x23, 0x29, 0x33, 0x49, 0x5D,
+  0x49, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49, 0x82,
+  0x49, 0x82, 0x5D, 0x5D, 0x5D, 0x2D, 0x5C, 0x8F,
+  0x6D, 0xD6, 0x2C, 0x55, 0x90, 0xCB, 0x95, 0x95,
+  0x95, 0x55, 0x70, 0x94, 0x70, 0x55, 0x2C, 0xA1,
+  0x95, 0xE8, 0x5F, 0x76, 0x33, 0x5D, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x3E, 0x9C, 0x2F, 0x68,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0x65, 0xE5, 0x65, 0xE5, 0x6B, 0x90, 0x80, 0x20,
+  0x20, 0x20, 0x4F, 0x81, 0x50, 0x3E, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x69, 0x69, 0x49, 0x5D, 0x2D, 0xC4, 0x46, 0xA3,
+  0xD6, 0x55, 0x70, 0x94, 0x94, 0x70, 0xCB, 0x55,
+  0x55, 0xCB, 0x70, 0x47, 0x70, 0x95, 0xA1, 0xA1,
+  0x95, 0xBD, 0x75, 0x2D, 0x33, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x5D, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x5D, 0x2D, 0xB5, 0xDB,
+  0xD6, 0x65, 0xE5, 0x65, 0xE5, 0xE5, 0x65, 0xE5,
+  0x65, 0x65, 0x6B, 0x95, 0x2B, 0x88, 0x20, 0x20,
+  0x20, 0x20, 0x8B, 0x81, 0x29, 0x33, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x3E, 0x3E, 0x5E, 0x41, 0x97, 0x27, 0xD6,
+  0x55, 0x94, 0xE6, 0xE6, 0x47, 0x70, 0x55, 0x55,
+  0x94, 0x70, 0x94, 0x94, 0x70, 0x55, 0xA1, 0x2C,
+  0x6D, 0xC5, 0x39, 0x6A, 0x5D, 0x5D, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x3E, 0xEA, 0x30, 0x77,
+  0xE1, 0xC9, 0x94, 0x2C, 0xD6, 0xD6, 0xA1, 0x55,
+  0x47, 0x9F, 0x43, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x80, 0x91, 0x81, 0x6A, 0x2D, 0x49, 0x49,
+  0x49, 0x5D, 0x5D, 0x49, 0x49, 0x5D, 0x5D, 0x82,
+  0xEB, 0x4A, 0x41, 0xC2, 0x8F, 0xF5, 0xA1, 0x55,
+  0x94, 0x28, 0xA0, 0x47, 0x70, 0x55, 0x95, 0x95,
+  0x47, 0x70, 0x70, 0x94, 0x90, 0x95, 0xA1, 0x2C,
+  0xE8, 0xA6, 0x39, 0x76, 0x50, 0x50, 0x2D, 0x2D,
+  0x3E, 0x3E, 0x5D, 0x3E, 0x5D, 0x5D, 0x49, 0x82,
+  0x49, 0x49, 0x49, 0x82, 0x82, 0x50, 0x75, 0xE0,
+  0x57, 0x20, 0x88, 0x88, 0x20, 0x20, 0x88, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x79, 0x91, 0x81, 0x76, 0x33, 0x49, 0x49,
+  0x5D, 0x82, 0x49, 0x49, 0x3E, 0x6A, 0xEA, 0x29,
+  0xDF, 0x97, 0xBF, 0x6D, 0x6D, 0xD6, 0x55, 0x47,
+  0x28, 0x28, 0x47, 0x70, 0x55, 0x95, 0x2C, 0x2C,
+  0x95, 0x95, 0x55, 0x90, 0x90, 0x95, 0xA1, 0xA1,
+  0xD6, 0x26, 0x45, 0x81, 0x5F, 0x30, 0x48, 0x6F,
+  0x6F, 0x29, 0x29, 0x6A, 0x2D, 0x2D, 0x5D, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x2D, 0x76, 0x6E, 0x77,
+  0x5B, 0x66, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x79, 0xA9, 0xB8, 0x39, 0x50, 0x5D, 0x5D,
+  0x5D, 0x5D, 0x3E, 0x2D, 0x29, 0x76, 0xCD, 0x37,
+  0xB9, 0xA1, 0xA1, 0x6D, 0x6D, 0x2C, 0x94, 0x28,
+  0xD5, 0xE6, 0x70, 0x55, 0x95, 0xA1, 0x2C, 0xA1,
+  0xBF, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0xA1, 0x2C,
+  0x95, 0x83, 0xDE, 0x87, 0xB6, 0xBE, 0x40, 0x6E,
+  0x81, 0x81, 0x78, 0x78, 0x39, 0x6F, 0xEA, 0x2D,
+  0x2D, 0x33, 0x33, 0x33, 0x76, 0x30, 0x64, 0x54,
+  0x5B, 0x66, 0x20, 0x20, 0x66, 0x20, 0x88, 0x20,
+  0x20, 0x20, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x88, 0x34, 0x8B, 0xF1, 0x23, 0x6F, 0x50, 0x2D,
+  0x2D, 0x6A, 0x29, 0x6F, 0x78, 0x84, 0x9B, 0xD2,
+  0x2C, 0x2C, 0xD6, 0x6D, 0x6D, 0x2C, 0x47, 0xA0,
+  0xE6, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0xA1,
+  0xD2, 0x95, 0x55, 0xCB, 0x55, 0x2C, 0xD6, 0xA1,
+  0x95, 0x95, 0xA1, 0xD6, 0x6D, 0x6D, 0xBA, 0xF3,
+  0x8D, 0x36, 0x74, 0x36, 0xF1, 0xB8, 0x23, 0x78,
+  0x62, 0x4A, 0x29, 0x62, 0x23, 0xF1, 0x54, 0x31,
+  0x57, 0x2B, 0x90, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C, 0xCB,
+  0xE6, 0x7D, 0xCA, 0xB7, 0xB8, 0x75, 0x6F, 0x6F,
+  0x76, 0x6F, 0x78, 0x81, 0x53, 0xBD, 0x6D, 0x2C,
+  0x95, 0x95, 0xA1, 0x6D, 0xA1, 0x55, 0x94, 0xE6,
+  0x70, 0xCB, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xA1,
+  0xD0, 0x94, 0x94, 0x90, 0x95, 0x2C, 0xD6, 0xA1,
+  0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x2C,
+  0xD6, 0x68, 0xAB, 0x6C, 0xA4, 0x77, 0x77, 0xAD,
+  0x40, 0x53, 0x6E, 0x40, 0xB7, 0x54, 0x31, 0xD7,
+  0xAC, 0xD6, 0x55, 0x55, 0x95, 0x95, 0x95, 0x55,
+  0x95, 0x2C, 0x2C, 0xA1, 0x95, 0x95, 0x2C, 0xA1,
+  0x6D, 0xD2, 0x7C, 0x54, 0xAD, 0x40, 0x6E, 0x81,
+  0x81, 0x6E, 0x36, 0xDA, 0xE8, 0xD6, 0xD6, 0x2C,
+  0x2C, 0x2C, 0xA1, 0xD6, 0x95, 0x90, 0x94, 0x47,
+  0x94, 0x94, 0x70, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
+  0x95, 0x28, 0x47, 0x90, 0x95, 0x2C, 0xA1, 0x2C,
+  0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C,
+  0x2C, 0xA1, 0x55, 0x70, 0x95, 0x2C, 0xB2, 0xB4,
+  0xC3, 0xC3, 0x54, 0x54, 0xA9, 0x31, 0xCA, 0x2A,
+  0x95, 0x90, 0x55, 0x95, 0x2C, 0xA1, 0x2C, 0x95,
+  0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD6,
+  0x6D, 0x2A, 0xB2, 0x4F, 0x31, 0x2E, 0xE0, 0xAD,
+  0xB7, 0xC8, 0xB4, 0xF5, 0x2C, 0xA1, 0xA1, 0xA1,
+  0x95, 0x2C, 0xA1, 0x2C, 0x95, 0x70, 0x94, 0x94,
+  0x94, 0x94, 0x70, 0x95, 0xD6, 0xD6, 0x2C, 0x95,
+  0x94, 0x28, 0x47, 0xCB, 0x95, 0x2C, 0xA1, 0xA1,
+  0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x95,
+  0x95, 0x2C, 0x55, 0x70, 0x70, 0x70, 0x94, 0x2C,
+  0x63, 0xBB, 0xA5, 0xD7, 0xCA, 0xB3, 0x6D, 0x2C,
+  0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x95, 0x95,
+  0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
+  0xD6, 0x2C, 0x70, 0x95, 0xAC, 0xC0, 0xDB, 0xEF,
+  0xEF, 0xA2, 0xE8, 0x95, 0x95, 0xA1, 0xD6, 0xA1,
+  0x95, 0x55, 0x2C, 0x95, 0x55, 0x70, 0x70, 0x70,
+  0x94, 0x70, 0x55, 0xD6, 0x6D, 0x6D, 0x95, 0x55,
+  0x70, 0x47, 0x70, 0x95, 0x2C, 0x2C, 0x2C, 0xA1,
+  0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x55,
+  0x55, 0x95, 0x55, 0x55, 0x55, 0x55, 0x55, 0x95,
+  0xA1, 0xF5, 0xBF, 0xBF, 0xA1, 0x95, 0x95, 0x95,
+  0x95, 0x55, 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x95,
+  0x95, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0xA1,
+  0x2C, 0x55, 0x70, 0x94, 0x90, 0x2C, 0x6D, 0x6D,
+  0x6D, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1,
+  0x2C, 0x55, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55,
+  0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB,
+  0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
+  0xA1, 0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x95,
+  0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
+  0x6D, 0xBF, 0x6D, 0x2C, 0x55, 0x55, 0x95, 0x95,
+  0xCB, 0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x95,
+  0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C,
+  0xA1, 0x95, 0xCB, 0xCB, 0x95, 0x95, 0x2C, 0x2C,
+  0x2C, 0xA1, 0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C,
+  0x2C, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
+  0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55,
+  0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x95,
+  0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6,
+  0x6D, 0x6D, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0x55,
+  0x90, 0x70, 0xCB, 0xCB, 0x90, 0xCB, 0x95, 0x95,
+  0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0xA1,
+  0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
+  0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C,
+  0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1,
+  0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55
+};
+
+#endif
+
+#ifdef INCLUDE_LINUX_LOGOBW
+
+unsigned char linux_logo_bw[] __initdata = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x3F,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F,
+  0xFE, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFE, 0x3F, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFE, 0x7F, 0xFF, 0xC7, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xC3,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF,
+  0xFB, 0xE3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFD, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF,
+  0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xF9, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0xCF, 0xC3, 0xF8, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x87, 0x81, 0xF9,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xA7,
+  0x99, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xF9, 0xF3, 0xBC, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0xE3, 0xBC, 0xF9, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0, 0x3C, 0xF9,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0,
+  0x19, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xF9, 0xC0, 0x03, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80,
+  0x01, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xF9, 0xC0, 0x21, 0xD8, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0xB1, 0x80, 0xEC, 0xC0, 0x1F,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x90, 0x00, 0xE4,
+  0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x8C,
+  0xC0, 0x7C, 0x04, 0x81, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xE3, 0x80, 0x00, 0x7C, 0x40, 0x11, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xE3, 0x80, 0x00, 0x7F, 0xD2, 0x29,
+  0xFF, 0xFF, 0xFF, 0xFF, 0x87, 0x00, 0x00, 0x3F,
+  0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, 0x0E, 0x00,
+  0x00, 0x3F, 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF,
+  0x1E, 0x00, 0x00, 0x1F, 0x80, 0x19, 0xFF, 0xFF,
+  0xFF, 0xFE, 0x1C, 0x00, 0x00, 0x1E, 0x80, 0x19,
+  0xFF, 0xFF, 0xFF, 0xFE, 0x3C, 0x00, 0x00, 0x1E,
+  0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC, 0x7C, 0x00,
+  0x00, 0x0F, 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC,
+  0xF8, 0x00, 0x00, 0x0E, 0x80, 0x11, 0xFF, 0xFF,
+  0xFF, 0xFC, 0xF8, 0x00, 0x00, 0x06, 0x00, 0x11,
+  0xFF, 0xFF, 0xFF, 0xF8, 0xF8, 0x00, 0x00, 0x06,
+  0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xF9, 0xF0, 0x00,
+  0x00, 0x02, 0x00, 0x09, 0xFF, 0xFF, 0xFF, 0xF1,
+  0xF0, 0x00, 0x00, 0x02, 0x80, 0x10, 0xFF, 0xFF,
+  0xFF, 0xF1, 0xE0, 0x00, 0x00, 0x00, 0x97, 0x10,
+  0xFF, 0xFF, 0xFF, 0xE3, 0xE0, 0x00, 0x00, 0x00,
+  0xDF, 0xF0, 0xFF, 0xFF, 0xFF, 0xE3, 0xC0, 0x00,
+  0x00, 0x00, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xC7,
+  0xC0, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF,
+  0xFF, 0xC7, 0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8,
+  0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00, 0x00, 0x01,
+  0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00,
+  0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x9F,
+  0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF,
+  0xFF, 0x9F, 0x80, 0x00, 0x00, 0x01, 0x80, 0x18,
+  0xFF, 0xFF, 0xFF, 0x9E, 0x80, 0x00, 0x00, 0x03,
+  0xA8, 0x11, 0xFF, 0xFF, 0xFF, 0x9F, 0x80, 0x00,
+  0x00, 0x02, 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0x99,
+  0x80, 0x00, 0x00, 0x00, 0x00, 0x09, 0xFF, 0xFF,
+  0xFF, 0x00, 0x80, 0x00, 0x00, 0x01, 0xC0, 0x01,
+  0xFF, 0xFF, 0xFE, 0x20, 0x60, 0x00, 0x00, 0x00,
+  0xFF, 0xC3, 0xFF, 0xFF, 0xF8, 0x00, 0x30, 0x00,
+  0x00, 0x00, 0xFF, 0x0F, 0xFF, 0xFF, 0xC0, 0x40,
+  0x38, 0x00, 0x00, 0x00, 0xFE, 0x47, 0xFF, 0xFF,
+  0x81, 0x00, 0x1C, 0x00, 0x00, 0x00, 0xFC, 0x23,
+  0xFF, 0xFF, 0x90, 0x00, 0x1E, 0x00, 0x00, 0x00,
+  0x78, 0x11, 0xFF, 0xFF, 0x80, 0x00, 0x0F, 0x80,
+  0x00, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0x80, 0x00,
+  0x07, 0xC0, 0x00, 0x00, 0x00, 0x08, 0xFF, 0xFF,
+  0xC0, 0x00, 0x07, 0xC0, 0x00, 0x00, 0x00, 0x04,
+  0x7F, 0xFF, 0x80, 0x00, 0x03, 0xC0, 0x00, 0x10,
+  0x00, 0x00, 0x1F, 0xFF, 0x80, 0x00, 0x01, 0x80,
+  0x00, 0x30, 0x00, 0x00, 0x0F, 0xFF, 0x80, 0x00,
+  0x00, 0x00, 0x00, 0x70, 0x00, 0x01, 0x4F, 0xFF,
+  0x80, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00,
+  0x0F, 0xFF, 0xC0, 0x00, 0x00, 0x80, 0x03, 0xF0,
+  0x00, 0x00, 0x8F, 0xFF, 0x80, 0x00, 0x00, 0x40,
+  0x0F, 0xF0, 0x00, 0x04, 0x1F, 0xFF, 0x80, 0x00,
+  0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x10, 0x1F, 0xFF,
+  0xC0, 0x00, 0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x40,
+  0xFF, 0xFF, 0x98, 0x00, 0x00, 0xFF, 0xFF, 0xF0,
+  0x00, 0x83, 0xFF, 0xFF, 0x81, 0xE0, 0x01, 0xFF,
+  0xFF, 0xF8, 0x02, 0x07, 0xFF, 0xFF, 0x80, 0x3F,
+  0x07, 0xE0, 0x00, 0x1C, 0x0C, 0x1F, 0xFF, 0xFF,
+  0xF8, 0x03, 0xFF, 0x80, 0x00, 0x1F, 0x78, 0x1F,
+  0xFF, 0xFF, 0xFF, 0x80, 0x7F, 0x00, 0x07, 0x0F,
+  0xF0, 0x7F, 0xFF, 0xFF, 0xFF, 0xFE, 0x0C, 0x07,
+  0xFF, 0x83, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0x00, 0x1F, 0xFF, 0xC0, 0x03, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0x07, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+};
+
+#endif
+
+#ifdef INCLUDE_LINUX_LOGO16
+
+unsigned char linux_logo16_red[] __initdata = {
+    0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x35, 0x83, 0xa5,
+    0x65, 0x8f, 0x98, 0xc9, 0xdb, 0xe1, 0xe7, 0xf8
+};
+
+unsigned char linux_logo16_green[] __initdata = {
+    0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x2e, 0x83, 0xa5,
+    0x65, 0x6e, 0x98, 0x89, 0xbf, 0xac, 0xda, 0xf8
+};
+
+unsigned char linux_logo16_blue[] __initdata = {
+    0x00, 0x90, 0xaf, 0x9c, 0xf7, 0x2b, 0x82, 0xa5,
+    0x65, 0x41, 0x97, 0x1e, 0x60, 0x29, 0xa5, 0xf8
+};
+
+unsigned char linux_logo16[] __initdata = {
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa1, 0x11, 0x11,
+    0x61, 0x16, 0x66, 0x66, 0x11, 0x11, 0x11, 0x11,
+    0x11, 0x11, 0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0xa8, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x87, 0x77, 0x77, 0x77, 0x77,
+    0x77, 0x77, 0x73, 0x33, 0x33, 0x3a, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x77, 0x77, 0x77, 0x77,
+    0x77, 0x27, 0x77, 0x77, 0x77, 0x33, 0x3a, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xa3, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x55, 0x50, 0x08, 0x33, 0x77, 0x77,
+    0x77, 0x72, 0x72, 0x27, 0x77, 0x77, 0x33, 0x33,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xa3, 0x33, 0x33, 0x77, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x58, 0x85, 0x00, 0x11, 0x11, 0xaa,
+    0xa3, 0x37, 0x77, 0x72, 0x22, 0x22, 0x77, 0x73,
+    0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3,
+    0x33, 0x37, 0x77, 0x33, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x56, 0x85, 0x00, 0x06, 0x66, 0x11,
+    0x11, 0x1a, 0xa3, 0x37, 0x77, 0x72, 0x22, 0x77,
+    0x73, 0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33,
+    0x33, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x55, 0x00, 0x00, 0x06, 0x66, 0x66,
+    0x66, 0x66, 0x11, 0x1a, 0xa3, 0x77, 0x72, 0x22,
+    0x77, 0x73, 0x3a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33,
+    0x33, 0x33, 0x33, 0xa0, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x11,
+    0x66, 0x66, 0x66, 0x66, 0x11, 0xa3, 0x77, 0x22,
+    0x22, 0x77, 0x33, 0x33, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33,
+    0x33, 0x3a, 0xa1, 0x10, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x33,
+    0xaa, 0x11, 0x16, 0x66, 0x66, 0x61, 0x1a, 0x37,
+    0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x33,
+    0x3a, 0xa1, 0x11, 0x10, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x22,
+    0x22, 0x77, 0x3a, 0x11, 0x66, 0x66, 0x66, 0x1a,
+    0x37, 0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33, 0x3a,
+    0xa1, 0x11, 0x11, 0x10, 0x00, 0x00, 0x50, 0x00,
+    0x00, 0x05, 0x80, 0x50, 0x00, 0x00, 0x07, 0x72,
+    0x22, 0x22, 0x22, 0x73, 0xa1, 0x66, 0x66, 0x61,
+    0x1a, 0x77, 0x22, 0x27, 0x73, 0x33, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x3a, 0xaa,
+    0x11, 0x11, 0x1a, 0xa0, 0x08, 0x71, 0x05, 0x00,
+    0x00, 0x12, 0x22, 0x50, 0x00, 0x00, 0x07, 0x77,
+    0x77, 0x72, 0x22, 0x22, 0x27, 0x31, 0x16, 0x66,
+    0x61, 0x13, 0x77, 0x22, 0x77, 0x33, 0x3a, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xa1,
+    0x11, 0x1a, 0x33, 0x70, 0x07, 0x2e, 0x70, 0x00,
+    0x01, 0x44, 0x42, 0x60, 0x00, 0x00, 0x02, 0x22,
+    0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x31, 0x66,
+    0x66, 0x61, 0xa3, 0x72, 0x22, 0x77, 0x33, 0xaa,
+    0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xaa, 0x11,
+    0x1a, 0x33, 0x77, 0x30, 0x04, 0x82, 0x40, 0x00,
+    0x54, 0x48, 0x54, 0x40, 0x00, 0x00, 0x01, 0xaa,
+    0x32, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x31,
+    0x66, 0x66, 0x11, 0x37, 0x22, 0x27, 0x73, 0x3a,
+    0xaa, 0xaa, 0xa3, 0x33, 0x3a, 0xaa, 0xaa, 0xaa,
+    0xa3, 0x77, 0xaa, 0x10, 0x50, 0x08, 0x46, 0x05,
+    0x54, 0x80, 0x50, 0x42, 0x00, 0x00, 0x08, 0x66,
+    0x66, 0x1a, 0x32, 0x22, 0x22, 0x22, 0x22, 0x27,
+    0x31, 0x66, 0x66, 0x13, 0x72, 0x22, 0x77, 0x33,
+    0xaa, 0xaa, 0xaa, 0x33, 0xaa, 0xa1, 0xaa, 0xa3,
+    0x37, 0xa1, 0x1a, 0x30, 0x50, 0x06, 0x26, 0x00,
+    0x54, 0x00, 0x00, 0x44, 0x00, 0x00, 0x08, 0xe2,
+    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22, 0x22,
+    0x27, 0xa6, 0x66, 0x61, 0xa7, 0x72, 0x27, 0x73,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33,
+    0x31, 0x11, 0x37, 0x70, 0x02, 0x00, 0xab, 0xbb,
+    0xb6, 0x00, 0x00, 0xf4, 0x00, 0x00, 0xee, 0xee,
+    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22,
+    0x22, 0x23, 0x16, 0x66, 0x1a, 0x37, 0x22, 0x77,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x3a,
+    0x11, 0xa7, 0x33, 0x10, 0x04, 0x09, 0xbd, 0xdd,
+    0xbd, 0xd0, 0x04, 0x45, 0x00, 0x0e, 0xee, 0xee,
+    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22,
+    0x22, 0x22, 0x71, 0x66, 0x66, 0x13, 0x72, 0x27,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x11,
+    0xa3, 0x73, 0xa1, 0x60, 0x08, 0xbd, 0xdd, 0xdd,
+    0xdd, 0xdd, 0xdb, 0x90, 0x00, 0x02, 0xec, 0xee,
+    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xce, 0x22,
+    0x22, 0x22, 0x27, 0xa6, 0x66, 0x61, 0x37, 0x27,
+    0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0xa1, 0x1a,
+    0x33, 0xa1, 0x16, 0x60, 0x0b, 0xbd, 0xdd, 0xdd,
+    0xcd, 0xdd, 0xdd, 0xd9, 0x00, 0x00, 0xec, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xce, 0xa2,
+    0x22, 0x22, 0x22, 0x7a, 0x66, 0x66, 0x13, 0x77,
+    0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0x3a, 0x11, 0x33,
+    0xaa, 0x11, 0x66, 0x60, 0x9b, 0xdd, 0xdd, 0xdd,
+    0xcd, 0xdd, 0xdb, 0xb9, 0x00, 0x00, 0xec, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xee, 0x61,
+    0x72, 0x22, 0x22, 0x22, 0xa1, 0x66, 0x61, 0x37,
+    0x1a, 0xaa, 0xaa, 0xaa, 0xa3, 0xa1, 0x13, 0x3a,
+    0x11, 0x11, 0x11, 0x10, 0x5b, 0xdd, 0xdd, 0xdc,
+    0xdd, 0xdd, 0xbd, 0xd9, 0x00, 0x00, 0xec, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xee, 0x86,
+    0x17, 0x22, 0x22, 0x22, 0x23, 0x16, 0x66, 0xaa,
+    0xaa, 0xa3, 0x3a, 0xaa, 0xaa, 0x1a, 0x3a, 0xa1,
+    0x11, 0x11, 0x1a, 0x70, 0x05, 0xbd, 0xdd, 0xdd,
+    0xdb, 0x5b, 0xdd, 0xb0, 0x00, 0x60, 0x2e, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xe6, 0x88,
+    0x66, 0x32, 0x22, 0x22, 0x22, 0x36, 0x66, 0x11,
+    0x33, 0x33, 0x3a, 0xaa, 0x11, 0xaa, 0xaa, 0xa1,
+    0x11, 0x1a, 0x3a, 0x60, 0x02, 0x99, 0xbb, 0xb9,
+    0x9b, 0xbb, 0xbc, 0x22, 0x00, 0x86, 0x5e, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xe1, 0x68,
+    0x86, 0x63, 0x22, 0x22, 0x22, 0x2a, 0x66, 0x66,
+    0x33, 0x33, 0xaa, 0xaa, 0x1a, 0xaa, 0xaa, 0x11,
+    0x1a, 0xa7, 0x68, 0x80, 0x02, 0x2b, 0xbd, 0xbb,
+    0xbb, 0xb9, 0x22, 0x22, 0x00, 0x06, 0x6e, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xc7, 0xa6,
+    0x88, 0x86, 0x32, 0x22, 0x22, 0x27, 0xa6, 0x66,
+    0x33, 0x3a, 0xaa, 0xa1, 0xaa, 0xaa, 0xa1, 0x11,
+    0xa3, 0xa6, 0x88, 0x80, 0x02, 0x22, 0x9b, 0xbb,
+    0xbb, 0x22, 0x24, 0xf4, 0x60, 0x00, 0x0c, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xc2, 0x21,
+    0x68, 0x88, 0x63, 0x22, 0x22, 0x22, 0x71, 0x66,
+    0x33, 0x3a, 0x11, 0x11, 0xaa, 0xaa, 0x11, 0xaa,
+    0x71, 0x88, 0x88, 0x00, 0x02, 0xe2, 0x26, 0x99,
+    0x22, 0x22, 0x4f, 0xf4, 0x40, 0x00, 0x0c, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x22, 0x22,
+    0x16, 0x88, 0x86, 0xa2, 0x22, 0x22, 0x27, 0x11,
+    0x33, 0xa1, 0x11, 0x11, 0xaa, 0x31, 0x1a, 0xa3,
+    0x68, 0x88, 0x81, 0x00, 0x54, 0x42, 0x22, 0x22,
+    0x22, 0x44, 0xff, 0xff, 0x48, 0x00, 0x00, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x22, 0x22,
+    0x21, 0x88, 0x88, 0x6a, 0x22, 0x22, 0x22, 0x31,
+    0x3a, 0xa1, 0x11, 0x1a, 0xa3, 0x11, 0x33, 0x36,
+    0x88, 0x86, 0x30, 0x00, 0x4f, 0x44, 0x22, 0x22,
+    0x24, 0xff, 0xff, 0xff, 0x44, 0x00, 0x00, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x95, 0x22, 0x72,
+    0x22, 0x18, 0x88, 0x86, 0x32, 0x22, 0x22, 0x27,
+    0xaa, 0x11, 0x11, 0x1a, 0x31, 0x13, 0x33, 0x68,
+    0x88, 0x6a, 0x00, 0x02, 0x4f, 0x4f, 0x42, 0x24,
+    0x4f, 0xff, 0xff, 0xff, 0xf4, 0x50, 0x00, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x22, 0x73,
+    0x72, 0x26, 0x88, 0x88, 0x63, 0x22, 0x22, 0x22,
+    0x11, 0x11, 0x11, 0xa3, 0xa1, 0x73, 0xa6, 0x88,
+    0x81, 0xa5, 0x00, 0x04, 0x4f, 0x4f, 0x44, 0x4f,
+    0xff, 0xff, 0xff, 0xff, 0xf4, 0x40, 0x00, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x12, 0x27,
+    0xaa, 0x22, 0x68, 0x55, 0x86, 0x72, 0x22, 0x22,
+    0x11, 0x11, 0x1a, 0x33, 0x13, 0x3a, 0x18, 0x88,
+    0x1a, 0x10, 0x00, 0x44, 0x4f, 0x4f, 0xff, 0x4f,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x61, 0x22,
+    0x3a, 0xa2, 0x26, 0x85, 0x58, 0x67, 0x22, 0x22,
+    0x61, 0x61, 0x1a, 0x7a, 0x37, 0x31, 0x88, 0x81,
+    0x11, 0x00, 0x05, 0xe4, 0x44, 0xff, 0xff, 0xff,
+    0x4f, 0xf4, 0x44, 0xff, 0xff, 0xf5, 0x00, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x88, 0x12,
+    0x2a, 0xaa, 0x72, 0x68, 0x55, 0x81, 0x22, 0x22,
+    0x66, 0x61, 0xa3, 0x33, 0x73, 0x16, 0x88, 0x11,
+    0x10, 0x00, 0x08, 0x74, 0x44, 0x4f, 0x44, 0x44,
+    0xf4, 0xf4, 0x44, 0x44, 0xe2, 0x44, 0x00, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x88, 0x81,
+    0x22, 0xaa, 0xa7, 0x26, 0x85, 0x88, 0x12, 0x22,
+    0x66, 0x61, 0x37, 0xa7, 0x3a, 0x66, 0x66, 0x11,
+    0x80, 0x00, 0x0a, 0x72, 0x44, 0x4f, 0x44, 0x4f,
+    0xff, 0x44, 0x44, 0x22, 0x22, 0x24, 0x00, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x85, 0x88,
+    0x12, 0x2a, 0xaa, 0x22, 0x68, 0x58, 0x63, 0x22,
+    0x66, 0x1a, 0x73, 0x77, 0x31, 0x66, 0x61, 0x11,
+    0x00, 0x00, 0x07, 0x44, 0xff, 0x4f, 0xf4, 0x4f,
+    0xff, 0x4f, 0x44, 0xf4, 0x42, 0x22, 0x40, 0x9b,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb9, 0x85, 0x55,
+    0x81, 0x27, 0xaa, 0xa2, 0x78, 0x88, 0x86, 0x72,
+    0x66, 0x13, 0x77, 0x73, 0x11, 0x66, 0x61, 0x76,
+    0x00, 0x50, 0x84, 0xf4, 0xff, 0x4f, 0xf4, 0xff,
+    0xff, 0x4f, 0x44, 0xff, 0x4f, 0x42, 0x40, 0x9b,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb9, 0x68, 0x55,
+    0x58, 0x12, 0x3a, 0xaa, 0x23, 0x88, 0x88, 0xa7,
+    0x66, 0xa7, 0x77, 0x7a, 0x16, 0x66, 0x1a, 0x15,
+    0x05, 0x00, 0x4f, 0xf4, 0xff, 0x4f, 0xf4, 0xff,
+    0xff, 0x4f, 0x44, 0xff, 0x4f, 0x44, 0x24, 0x9b,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb9, 0x26, 0x55,
+    0x55, 0x81, 0x23, 0xaa, 0x32, 0x18, 0x88, 0x6a,
+    0x61, 0x37, 0x77, 0x31, 0x66, 0x66, 0x17, 0x60,
+    0x05, 0x08, 0x4f, 0xf4, 0xff, 0x4f, 0xf4, 0xff,
+    0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x4e, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0xa2, 0x65,
+    0x55, 0x58, 0xa2, 0x7a, 0xa2, 0x26, 0x88, 0x61,
+    0x61, 0x32, 0x27, 0xa1, 0x66, 0x61, 0x31, 0x60,
+    0x00, 0x04, 0x4f, 0xf4, 0xff, 0x44, 0x44, 0xff,
+    0xff, 0x4f, 0x44, 0xff, 0x4f, 0x44, 0xf4, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x9b, 0xaa, 0x26,
+    0x55, 0x55, 0x87, 0x27, 0x33, 0x27, 0x68, 0x61,
+    0x1a, 0x72, 0x27, 0xa6, 0x66, 0x6a, 0x71, 0x00,
+    0x80, 0x84, 0xff, 0xf4, 0xff, 0x44, 0x44, 0xff,
+    0xff, 0x4f, 0x44, 0xff, 0x4f, 0x44, 0xf4, 0x99,
+    0x9b, 0x9b, 0x99, 0xb9, 0xb9, 0x99, 0xaa, 0xa2,
+    0x85, 0x55, 0x56, 0x22, 0x27, 0x22, 0x36, 0x66,
+    0x13, 0x22, 0x23, 0x16, 0x86, 0x63, 0x73, 0x00,
+    0x00, 0x44, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0xff,
+    0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x4f, 0x99,
+    0x9b, 0x99, 0x99, 0x99, 0xb9, 0x99, 0xaa, 0xaa,
+    0x28, 0x55, 0x58, 0x12, 0x22, 0x22, 0x21, 0x11,
+    0xa3, 0x27, 0x7a, 0x66, 0x86, 0x17, 0x75, 0x05,
+    0x05, 0xff, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0xff,
+    0xff, 0x4f, 0x44, 0x4f, 0x4f, 0x44, 0x4f, 0x99,
+    0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x3a, 0xaa,
+    0xa2, 0x85, 0x58, 0x67, 0x72, 0x22, 0x27, 0xa1,
+    0x37, 0x27, 0x7a, 0x68, 0x86, 0xa2, 0x70, 0x00,
+    0x02, 0xff, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0x4f,
+    0xff, 0x4f, 0x44, 0xf4, 0xf4, 0xf4, 0xf4, 0x99,
+    0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x23, 0xaa,
+    0xa7, 0x78, 0x88, 0x81, 0x77, 0x22, 0x27, 0x3a,
+    0x72, 0x73, 0x71, 0x68, 0x66, 0x32, 0x50, 0x00,
+    0x04, 0x4f, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0x4f,
+    0xff, 0x4f, 0x44, 0xf4, 0xf4, 0xf4, 0x44, 0x95,
+    0x99, 0x99, 0x99, 0x99, 0x99, 0x55, 0x12, 0x3a,
+    0xaa, 0x21, 0x88, 0x81, 0x77, 0x27, 0x73, 0x73,
+    0x72, 0x33, 0x36, 0x86, 0x61, 0x72, 0x00, 0x00,
+    0x04, 0x44, 0xf4, 0xf4, 0xf4, 0x44, 0x44, 0x4f,
+    0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x44, 0x55,
+    0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x8a, 0x27,
+    0xaa, 0x77, 0x68, 0x61, 0x23, 0x71, 0x11, 0x3a,
+    0x27, 0xa3, 0x36, 0x86, 0x61, 0x20, 0x00, 0x00,
+    0x04, 0xf4, 0xf4, 0xf4, 0xf4, 0x44, 0x44, 0x4f,
+    0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x41, 0x59,
+    0x99, 0x99, 0x99, 0x99, 0x99, 0x95, 0x58, 0x77,
+    0x27, 0x32, 0x36, 0x63, 0x23, 0x71, 0x66, 0x11,
+    0x27, 0x13, 0xa6, 0x86, 0x6a, 0x20, 0x00, 0x50,
+    0x04, 0x4f, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f,
+    0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x41, 0x99,
+    0x9b, 0xbb, 0xbb, 0xbb, 0xb9, 0x99, 0x68, 0x13,
+    0x32, 0x22, 0x73, 0xa7, 0x2a, 0x31, 0x88, 0x66,
+    0x7a, 0x13, 0x18, 0x66, 0x63, 0x20, 0x00, 0x06,
+    0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f,
+    0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x49, 0x95,
+    0xa9, 0xa9, 0x99, 0x97, 0x92, 0x99, 0x65, 0x6a,
+    0x17, 0x22, 0x23, 0x72, 0x27, 0xaa, 0x88, 0x88,
+    0xa1, 0x17, 0x68, 0x66, 0x67, 0x70, 0x00, 0x05,
+    0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f,
+    0xff, 0x4f, 0x44, 0xff, 0xf4, 0xf4, 0x49, 0x9c,
+    0x2e, 0xee, 0xee, 0xee, 0xee, 0xa9, 0x65, 0x8a,
+    0x1a, 0xaa, 0x37, 0x72, 0x27, 0x37, 0x88, 0x88,
+    0x11, 0x17, 0x68, 0x66, 0x67, 0x10, 0x9d, 0xd0,
+    0x84, 0x44, 0xff, 0x4f, 0x4f, 0x44, 0xf4, 0x4f,
+    0xff, 0x4f, 0x44, 0xff, 0xf4, 0xf4, 0x4f, 0x69,
+    0xcc, 0xee, 0xee, 0xee, 0xec, 0x99, 0x88, 0x63,
+    0x61, 0x68, 0x61, 0x72, 0x22, 0x7a, 0x68, 0x88,
+    0x11, 0x17, 0x88, 0x66, 0x12, 0x1b, 0xdd, 0xdd,
+    0x02, 0x44, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f,
+    0xff, 0x4f, 0x44, 0xff, 0xff, 0x4f, 0x4c, 0xc5,
+    0x0c, 0xc1, 0x11, 0x1c, 0xc0, 0x26, 0x66, 0x17,
+    0x66, 0x88, 0x88, 0x12, 0x22, 0x23, 0xa8, 0x88,
+    0x11, 0x13, 0x88, 0x66, 0x17, 0xbb, 0xdd, 0xdd,
+    0xd0, 0x8f, 0xff, 0xf4, 0xf4, 0x44, 0xf4, 0x4f,
+    0xff, 0x4f, 0x44, 0xf4, 0x4f, 0x44, 0xdd, 0xdd,
+    0x00, 0x00, 0x00, 0x05, 0x9d, 0x21, 0x66, 0x27,
+    0xa6, 0x65, 0x58, 0x67, 0x22, 0x27, 0x28, 0x88,
+    0x11, 0xaa, 0x86, 0x68, 0x1a, 0xbb, 0xdd, 0xdd,
+    0xdb, 0x05, 0xf4, 0xf4, 0xf4, 0xf4, 0x44, 0x4f,
+    0xff, 0x4f, 0x44, 0xf4, 0xf4, 0xf4, 0xdd, 0xdb,
+    0x00, 0x00, 0x00, 0x00, 0xdd, 0xda, 0x66, 0x22,
+    0x71, 0x15, 0x55, 0x81, 0x22, 0x22, 0x76, 0x88,
+    0x11, 0x31, 0x88, 0x88, 0xab, 0xbd, 0xdd, 0xdd,
+    0xdd, 0x00, 0x04, 0x44, 0xff, 0xff, 0x4f, 0x4f,
+    0xff, 0x4f, 0x44, 0xf4, 0xf4, 0x44, 0xdd, 0xdb,
+    0x00, 0x00, 0x00, 0x0b, 0xdd, 0xda, 0x11, 0x22,
+    0x23, 0x68, 0x55, 0x86, 0x22, 0x22, 0x7a, 0x88,
+    0x1a, 0x71, 0x88, 0x89, 0xbb, 0xdd, 0xdd, 0xdd,
+    0xdd, 0xd0, 0x00, 0x4f, 0x44, 0xff, 0x4f, 0x4f,
+    0xff, 0x4f, 0x44, 0xf4, 0xff, 0xe2, 0xdd, 0xdb,
+    0x90, 0x00, 0x05, 0xbd, 0xdd, 0xb8, 0x63, 0x22,
+    0x27, 0xa6, 0x55, 0x88, 0x77, 0x22, 0x22, 0x88,
+    0x1a, 0x28, 0xbd, 0xdb, 0xdd, 0xdd, 0xdd, 0xdd,
+    0xdd, 0xdb, 0x00, 0x07, 0x44, 0x4f, 0x4f, 0x4f,
+    0xff, 0x4f, 0x44, 0x4f, 0x4f, 0x22, 0xdd, 0xdb,
+    0xbb, 0x9b, 0xbb, 0xbd, 0xdd, 0xd5, 0x86, 0x22,
+    0x22, 0x77, 0x85, 0x88, 0x17, 0x22, 0x22, 0x88,
+    0xaa, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
+    0xdd, 0xdd, 0x00, 0x00, 0x54, 0x4f, 0x4f, 0x4f,
+    0xff, 0x4f, 0x44, 0xf4, 0x44, 0x22, 0xbd, 0xdd,
+    0xbb, 0xbb, 0xbb, 0xdd, 0xdd, 0xdd, 0x88, 0x72,
+    0x27, 0x22, 0x88, 0x88, 0x67, 0x72, 0x22, 0x18,
+    0x33, 0x2d, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
+    0xdd, 0xdd, 0xd0, 0x00, 0x05, 0x4f, 0x4f, 0x4f,
+    0xff, 0x4f, 0x44, 0x44, 0x4f, 0x22, 0xbd, 0xdd,
+    0xdb, 0xbb, 0xdd, 0xdd, 0xdd, 0xdd, 0x88, 0x17,
+    0x27, 0x72, 0x68, 0x88, 0x87, 0x32, 0x22, 0x36,
+    0x37, 0x2d, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
+    0xdd, 0xdd, 0xd5, 0x00, 0x00, 0x4f, 0x4f, 0x4f,
+    0xff, 0xf4, 0xf4, 0xf4, 0xf4, 0x22, 0xbb, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, 0x67,
+    0x72, 0x77, 0x38, 0x88, 0x83, 0x37, 0x22, 0x26,
+    0x72, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
+    0xdd, 0xdd, 0xdd, 0x00, 0x00, 0x4f, 0x4f, 0x4f,
+    0xff, 0xf4, 0xf4, 0xf4, 0x44, 0x25, 0xbb, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd3,
+    0x32, 0x73, 0x76, 0x88, 0x81, 0x33, 0x22, 0x2a,
+    0x22, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xb0, 0x54, 0x4f, 0x4f, 0x4f,
+    0xff, 0xf4, 0xf4, 0xff, 0x44, 0x00, 0xbb, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
+    0xa7, 0x73, 0x26, 0x88, 0x86, 0x7a, 0x72, 0x27,
+    0x22, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdb, 0x44, 0xff, 0x4f, 0x4f,
+    0xff, 0xf4, 0xf4, 0x44, 0x40, 0x05, 0xbb, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
+    0x13, 0x23, 0x21, 0x68, 0x86, 0x17, 0x72, 0x22,
+    0x22, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdb, 0x44, 0x4f, 0x4f, 0x4f,
+    0xff, 0xff, 0x44, 0x42, 0x00, 0x05, 0xbd, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
+    0x87, 0x27, 0x27, 0x16, 0x66, 0x67, 0x22, 0x22,
+    0x72, 0x7b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdd, 0x94, 0x44, 0x44, 0x44,
+    0x44, 0x44, 0x44, 0x00, 0x00, 0x05, 0xbb, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xb8,
+    0x86, 0x22, 0x22, 0x7a, 0x68, 0x81, 0x22, 0x22,
+    0x37, 0x7b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdb, 0xb5, 0x44, 0x44, 0x44,
+    0x44, 0x47, 0x00, 0x00, 0x00, 0x05, 0xbd, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, 0x68,
+    0x58, 0x72, 0x22, 0x27, 0x18, 0x86, 0x72, 0x22,
+    0x1a, 0xbb, 0xbd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdb, 0xb5, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xbb, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xb9, 0x18, 0x85,
+    0x58, 0x12, 0x22, 0x36, 0x18, 0x88, 0x32, 0x22,
+    0x61, 0x3b, 0xbb, 0xbb, 0xbd, 0xdd, 0xdd, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdb, 0xb9, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xbb, 0xdd,
+    0xdd, 0xdd, 0xdd, 0xdd, 0xb9, 0x7a, 0x68, 0x85,
+    0x88, 0x62, 0x27, 0x16, 0x18, 0x88, 0x12, 0x27,
+    0x86, 0x18, 0x9b, 0xbb, 0xbb, 0xbb, 0xbb, 0xbd,
+    0xdd, 0xdd, 0xdd, 0xbb, 0xb5, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0xbb, 0xbd,
+    0xdd, 0xdd, 0xdb, 0xbb, 0x87, 0x31, 0x68, 0x65,
+    0x88, 0x82, 0x23, 0x16, 0x18, 0x88, 0x12, 0x23,
+    0x88, 0x67, 0x27, 0xa8, 0x9b, 0xbb, 0xbb, 0xbb,
+    0xbd, 0xdd, 0xbb, 0xbb, 0x95, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x9b, 0xbb,
+    0xbb, 0xbb, 0xbb, 0x96, 0x87, 0x16, 0x68, 0x18,
+    0x88, 0x62, 0x31, 0x66, 0x18, 0x88, 0x62, 0x73,
+    0x88, 0x63, 0x27, 0x33, 0x65, 0x55, 0x99, 0x9b,
+    0xbb, 0xbb, 0xbb, 0x99, 0x55, 0x0a, 0xa1, 0x86,
+    0x81, 0x68, 0x88, 0x55, 0x58, 0x85, 0x9b, 0xbb,
+    0xbb, 0xbb, 0x95, 0x88, 0x83, 0x66, 0x66, 0x18,
+    0x66, 0x82, 0xa1, 0x66, 0x18, 0x88, 0x62, 0x33,
+    0x88, 0x81, 0x27, 0x7a, 0x18, 0x58, 0x86, 0x85,
+    0x99, 0x99, 0x99, 0x95, 0x53, 0x2a, 0xaa, 0x88,
+    0x67, 0x31, 0x68, 0x55, 0x58, 0x85, 0x59, 0xbb,
+    0xbb, 0xb9, 0x58, 0x68, 0x83, 0x66, 0x61, 0x16,
+    0x66, 0x62, 0x16, 0x66, 0x68, 0x88, 0x62, 0xaa,
+    0x88, 0x86, 0x27, 0x77, 0x78, 0x55, 0x88, 0x22,
+    0x25, 0x55, 0x95, 0x55, 0x6a, 0xa2, 0x2a, 0x88,
+    0x62, 0x27, 0x37, 0x38, 0x88, 0x87, 0x55, 0x59,
+    0x95, 0x58, 0x16, 0x88, 0x8a, 0x66, 0x63, 0x68,
+    0x86, 0x67, 0x66, 0x66, 0x68, 0x88, 0x12, 0x11,
+    0x88, 0x88, 0x72, 0x77, 0x78, 0x85, 0x58, 0x17,
+    0x23, 0x32, 0x55, 0x55, 0x81, 0x13, 0x73, 0x66,
+    0x62, 0x7a, 0xaa, 0x38, 0x88, 0x58, 0x27, 0x55,
+    0x58, 0x32, 0x38, 0x88, 0x81, 0x66, 0xa2, 0x88,
+    0x86, 0x61, 0x66, 0x61, 0x66, 0x68, 0x13, 0x11,
+    0x88, 0x88, 0x12, 0x22, 0x71, 0x85, 0x58, 0x62,
+    0x23, 0xa2, 0x68, 0x88, 0x81, 0x66, 0x88, 0x88,
+    0x63, 0x2a, 0xaa, 0x28, 0x88, 0x55, 0x86, 0x61,
+    0x66, 0x66, 0x68, 0x88, 0x66, 0x66, 0x77, 0x88,
+    0x68, 0x16, 0x66, 0x62, 0x66, 0x68, 0xa1, 0x61,
+    0x88, 0x88, 0x62, 0x22, 0x22, 0x85, 0x55, 0x83,
+    0x72, 0x37, 0xa8, 0x88, 0x61, 0x66, 0x85, 0x55,
+    0x86, 0x23, 0xaa, 0x71, 0x88, 0x85, 0x88, 0x66,
+    0x88, 0x86, 0x88, 0x88, 0x16, 0x61, 0x21, 0x88,
+    0x66, 0xa6, 0x86, 0x17, 0x66, 0x66, 0x31, 0x61,
+    0x88, 0x88, 0x87, 0x72, 0x22, 0x68, 0x55, 0x86,
+    0x77, 0x77, 0x36, 0x88, 0x13, 0x68, 0x85, 0x55,
+    0x58, 0x12, 0x73, 0x72, 0x76, 0x88, 0x88, 0x68,
+    0x88, 0x88, 0x88, 0x66, 0x36, 0x63, 0x26, 0x86,
+    0x86, 0x36, 0x86, 0x11, 0x66, 0x66, 0x76, 0x61,
+    0x88, 0x88, 0x81, 0x22, 0x22, 0x38, 0x85, 0x58,
+    0x37, 0x22, 0x21, 0x68, 0xa2, 0x31, 0x68, 0x55,
+    0x55, 0x81, 0x22, 0x22, 0xa8, 0x88, 0x88, 0x68,
+    0x86, 0x88, 0x68, 0x81, 0x36, 0x17, 0x21, 0x68,
+    0x86, 0x16, 0x66, 0x26, 0x66, 0x61, 0x36, 0x66,
+    0x68, 0x88, 0x86, 0x27, 0x22, 0x28, 0x88, 0x88,
+    0x17, 0x72, 0x2a, 0x66, 0xa2, 0x22, 0x36, 0x55,
+    0x55, 0x58, 0x37, 0x3a, 0x16, 0x66, 0x66, 0x66,
+    0x66, 0x18, 0x88, 0x67, 0x16, 0x12, 0x71, 0x68,
+    0x81, 0x68, 0x61, 0x76, 0x66, 0x6a, 0x16, 0x66,
+    0x88, 0x88, 0x86, 0x77, 0x22, 0x26, 0x88, 0x88,
+    0x13, 0x37, 0x71, 0x66, 0xa2, 0x33, 0x2a, 0x85,
+    0x55, 0x55, 0x17, 0x73, 0x16, 0x66, 0x66, 0x68,
+    0x63, 0x88, 0x88, 0xa2, 0x66, 0xa2, 0xa6, 0x88,
+    0x61, 0x68, 0x6a, 0x76, 0x66, 0x6a, 0x66, 0x6a
+};
+
+#endif
diff --git a/include/lists.h b/include/lists.h
new file mode 100755
index 0000000..804b5cd
--- /dev/null
+++ b/include/lists.h
@@ -0,0 +1,77 @@
+#ifndef _LISTS_H_
+#define _LISTS_H_
+
+#define LIST_START    	-1      /* Handy Constants that substitute for item positions */
+#define LIST_END      	0       /* END_OF_LIST means one past current length of list when */
+				/* inserting. Otherwise it refers the last item in the list. */
+
+typedef struct
+    {
+    void            *ptr;
+    unsigned int    size;
+    } HandleRecord;
+
+typedef void **Handle;
+
+typedef int (*CompareFunction)(void *data1, void *data2) ;
+
+typedef struct ListStructTag
+    {
+    int signature;              /* debugging aid */
+    int percentIncrease;        /* %of current size to increase by when list is out of space */
+    int minNumItemsIncrease;    /* fixed number of items to increase by when list is out of space */
+    int listSize;               /* number of items than can fit in the currently allocated memory */
+    int itemSize;               /* the size of each item in the list (same for every item) */
+    int numItems;               /* number of items currently in the list */
+    unsigned char itemList[1];  /* resizable array of list elements */
+    } ListStruct;
+
+typedef struct ListStructTag **list_t;        /* The list abstract data type */
+typedef int ( * ListApplicationFunc)(int index, void *ptrToItem, void *callbackData);
+
+/* Basic List Operations */
+list_t	ListCreate(int elementSize);
+int     ListNumItems(list_t list);
+int     ListInsertItem(list_t list, void *ptrToItem, int itemPosition);
+int     ListInsertItems(list_t list, void *ptrToItems, int firstItemPosition, int numItemsToInsert);
+void    ListDispose(list_t list);
+void    *ListGetPtrToItem(list_t list, int itemPosition);
+void    ListRemoveItem(list_t list, void *itemDestination, int itemPosition);
+void    ListRemoveItems(list_t list, void *itemsDestination, int firstItemPosition, int numItemsToRemove);
+
+#if 0	/* rarely ever used; kept here for reference just in case ... */
+void    ListDisposePtrList(list_t list);
+void    ListGetItem(list_t list, void *itemDestination, int itemPosition);
+void    ListReplaceItem(list_t list, void *ptrToItem, int itemPosition);
+void    ListRemoveItem(list_t list, void *itemDestination, int itemPosition);
+void    ListGetItems(list_t list, void *itemsDestination, int firstItemPosition, int numItemsToGet);
+void    ListReplaceItems(list_t list, void *ptrToItems, int firstItemPosition, int numItemsToReplace);
+void    ListRemoveItems(list_t list, void *itemsDestination, int firstItemPosition, int numItemsToRemove);
+list_t  ListCopy(list_t originalList);
+int     ListAppend(list_t list1, list_t list2);
+void    ListClear(list_t list);
+int     ListEqual(list_t list1, list_t list2);
+int     ListInsertInOrder(list_t list, void *ptrToItem, CompareFunction compareFunction);
+void    *ListGetDataPtr(list_t list);
+int     ListApplyToEach(list_t list, int ascending, ListApplicationFunc funcToApply, void *callbackData);
+
+/* List Searching and Sorting */
+int     ListFindItem(list_t list, void *ptrToItem, int startingPosition, CompareFunction compareFunction);
+void    ListRemoveDuplicates(list_t list, CompareFunction compareFunction);
+int     ListBinSearch(list_t list, void *itemPtr, CompareFunction compareFunction);
+void    ListQuickSort(list_t list, CompareFunction compareFunction);
+void    ListHeapSort(list_t list, CompareFunction compareFunction);
+void    ListInsertionSort(list_t list, CompareFunction compareFunction);
+int     ListIsSorted(list_t list, CompareFunction compareFunction);
+
+/*  Advanced List Functions */
+void	ListSetAllocationPolicy(list_t list, int minItemsPerAlloc, int percentIncreasePerAlloc);
+void    ListCompact(list_t list);
+int     ListPreAllocate(list_t list, int numItems);
+int     ListGetItemSize(list_t list);
+int     GetIntListFromParmInfo(va_list parmInfo, int numIntegers, list_t *integerList);
+int     ListInsertAfterItem(list_t list, void *ptrToItem, void *ptrToItemToInsertAfter, CompareFunction compareFunction);
+int     ListInsertBeforeItem(list_t list, void *ptrToItem, void *ptrToItemToInsertBefore, CompareFunction compareFunction);
+#endif /* 0 */
+
+#endif	/* _LISTS_H_ */
diff --git a/include/logbuff.h b/include/logbuff.h
new file mode 100755
index 0000000..3acfc18
--- /dev/null
+++ b/include/logbuff.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2002
+ * Detlev Zundel, dzu@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _LOGBUFF_H
+#define _LOGBUFF_H
+
+#ifdef CONFIG_LOGBUFFER
+
+#define LOGBUFF_LEN	(16384)	/* Must be 16k right now */
+#define LOGBUFF_MASK	(LOGBUFF_LEN-1)
+#define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */
+#define LOGBUFF_RESERVE (LOGBUFF_LEN+LOGBUFF_OVERHEAD)
+
+#define LOGBUFF_INITIALIZED	(1<<31)
+
+int drv_logbuff_init (void);
+void logbuff_init_ptrs (void);
+void logbuff_log(char *msg);
+void logbuff_reset (void);
+
+#endif /* CONFIG_LOGBUFFER */
+
+#endif /* _LOGBUFF_H */
diff --git a/include/lpd7a400_cpld.h b/include/lpd7a400_cpld.h
new file mode 100755
index 0000000..c70af09
--- /dev/null
+++ b/include/lpd7a400_cpld.h
@@ -0,0 +1,195 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Logic lh7a400-10 Card Engine CPLD interface
+ */
+
+#ifndef __LPD7A400_CPLD_H_
+#define __LPD7A400_CPLD_H_
+
+
+/*
+ * IO Controller Address and Register Definitions
+ *   - using LH7A400-10 Card Engine IO Controller Specification
+ *     (logic PN: 70000079)
+ */
+
+/*------------------------------------------------------------------
+ * Slow Peripherals (nCS6)
+ */
+#define LPD7A400_CPLD_CF		(0x60200000)
+#define LPD7A400_CPLD_ISA		(0x60400000)
+
+/*------------------------------------------------------------------
+ * Fast Peripherals (nCS7)
+ *
+ * The CPLD directs access to 0x70000000-0x701fffff to the onboard
+ * ethernet controller
+ */
+#define LPD7A400_CPLD_WLAN_BASE		(0x70000000)
+
+/* All registers are 8 bit */
+#define LPD7A400_CPLD_CECTL_REG		(0x70200000)
+#define LPD7A400_CPLD_SPIDATA_REG	(0x70600000)
+#define LPD7A400_CPLD_SPICTL_REG	(0x70800000)
+#define LPD7A400_CPLD_EEPSPI_REG	(0x70a00000)
+#define LPD7A400_CPLD_INTMASK_REG	(0x70c00000)
+#define LPD7A400_CPLD_MODE_REG		(0x70e00000)
+#define LPD7A400_CPLD_FLASH_REG		(0x71000000)
+#define LPD7A400_CPLD_PWRMG_REG		(0x71200000)
+#define LPD7A400_CPLD_REV_REG		(0x71400000)
+#define LPD7A400_CPLD_EXTGPIO_REG	(0x71600000)
+#define LPD7A400_CPLD_GPIODATA_REG	(0x71800000)
+#define LPD7A400_CPLD_GPIODIR_REG	(0x71a00000)
+
+#define LPD7A400_CPLD_REGPTR		(volatile u8*)
+
+/* Card Engine Control Register (section 3.1.2) */
+#define CECTL_SWINT	(0x80)	/* Software settable interrupt source
+				   (routed to uP PF3)
+				   0 = generate interrupt, 1 = do not */
+#define CECTL_OCMSK	(0x40)	/* USB1 connection interrupt mask
+				   0 = not masked, 1 = masked */
+#define CECTL_PDRV	(0x20)	/* PCC_nDRV output
+				   0 = active, 1 = inactive */
+#define CECTL_USB1C	(0x10)	/* USB1 connection interrupt
+				   0 = active, 1 = inactive */
+#define CECTL_USB1P	(0x08)  /* USB1 Power enable
+				   0 = enabled, 1 = disabled */
+#define CECTL_AWKP	(0x04)  /* Auto-Wakeup enable
+				   0 = enabled, 1 = disabled */
+#define CECTL_LCDV	(0x02)  /* LCD VEE enable
+				   0 = disabled, 1 = enabled */
+#define CECTL_WLPE	(0x01)  /* Wired LAN power enable
+				   0 = enabled, 1 = disabled */
+
+/* SPI Control Register (section 3.1.5) */
+#define SPICTL_SPLD	(0x20)	/* SPI load (R)
+				   0 = data reg. has not been loaded, shift
+				       count has not been reset
+				   1 = data reg. loaded, shift count reset */
+#define SPICTL_SPST	(0x10)  /* SPI start (RW)
+				   0 = don't load data reg. and reset shift count
+				   1 = ready to load data reg and reset shift count */
+#define SPICTL_SPDN	(0x08)  /* SPI done (R)
+				   0 = not done
+				   1 = access done */
+#define SPICTL_SPRW	(0x04)  /* SPI read/write (RW)
+				   0 = SPI write access
+				   1 = SPI read access */
+#define SPICTL_STCS	(0x02)  /* SPI touch chip select (RW)
+				   0 = not selected
+				   1 = selected */
+#define SPICTL_SCCS	(0x01)  /* SPI CODEC chip select (RW) {not used}
+				   0 = not selected
+				   1 = selected */
+
+/* EEPROM SPI Interface Register (section 3.1.6) */
+#define EEPSPI_EECS	(0x08)	/* EEPROM chip select (RW)
+				   0 = not selected
+				   1 = selected */
+#define EEPSPI_EECK	(0x04)	/* EEPROM SPI clock (RW) */
+#define EEPSPI_EETX	(0x02)  /* EEPROM SPI tx data (RW) */
+#define EEPSPI_EERX	(0x01)  /* EEPROM SPI rx data (R) */
+
+/* Interrupt/Mask Register (section 3.1.7) */
+#define INTMASK_CMSK	(0x80)  /* CPLD_nIRQD interrupt mask (RW)
+				   0 = not masked
+				   1 = masked */
+#define INTMASK_CIRQ	(0x40)	/* interrupt signal to CPLD (R)
+				   0 = interrupt active
+				   1 = no interrupt */
+#define INTMASK_PIRQ	(0x10)	/* legacy, no effect */
+#define INTMASK_TMSK	(0x08)	/* Touch chip interrupt mask (RW)
+				   0 = not masked
+				   1 = masked */
+#define INTMASK_WMSK	(0x04)  /* Wired LAN interrupt mask (RW)
+				   0 = not masked
+				   1 = masked */
+#define INTMASK_TIRQ	(0x02)  /* Touch chip interrupt request (R)
+				   0 = interrupt active
+				   1 = no interrupt */
+#define INTMASK_WIRQ	(0x01)  /* Wired LAN interrupt request (R)
+				   0 = interrupt active
+				   1 = no interrupt */
+
+/* Mode Register (section 3.1.8) */
+#define MODE_VS1	(0x80)  /* PCMCIA Voltage Sense 1 input (PCC_VS1) (R)
+				   0 = active slot VS1 pin is low
+				   1 = active slot VS1 pin is high */
+#define MODE_CD2	(0x40)  /* PCMCIA Card Detect 2 input (PCC_nCD2) (R)
+				   0 = active slot CD2 is low
+				   1 = active slot CD2 is high */
+#define MODE_IOIS16	(0x20)  /* PCMCIA IOIS16 input (PCC_nIOIS16) (R)
+				   0 = 16 bit access area
+				   1 = 8 bit access area */
+#define MODE_CD1	(0x10)  /* PCMCIA Card Detect 1 input (PCC_nCD1) (R)
+				   0 = active slot CD1 is low
+				   1 = active slot CD1 is high */
+#define MODE_upMODE3	(0x08)  /* Mode Pin 3 (R)
+				   0 = off-board boot device
+				   1 = on-board boot device (flash) */
+#define MODE_upMODE2	(0x04)  /* Mode Pin 2 (R) (LH7A400 Little Endian only)
+				   0 = big endian
+				   1 = little endian */
+#define MODE_upMODE1	(0x02)  /* Mode Pin 1 and Mode Pin 2 (R) */
+#define MODE_upMODE0	(0x01)  /*   - bus width at boot */
+
+
+/* Flash Register (section 3.1.9) */
+#define FLASH_FPOP	(0x08)	/* Flash populated (RW)
+				   0 = populated, 1 = not */
+#define FLASH_FST2	(0x04)  /* Flash status (R) (RY/BY# pin for upper 16 bit chip
+				   0 = busy, 1 = ready */
+#define FLASH_FST1	(0x02)  /* Flash status (R) (RY/BY# pin for lower 16 bit chip
+				   0 = busy, 1 = ready */
+#define FLASH_FPEN	(0x01)  /* Flash program enable (RW)
+				   0 = flash write protected
+				   1 = programming enabled */
+
+/* Power Management Register (section 3.1.10)
+ *    - when either of these is low an unmaskable interrupt to cpu
+ *      is generated
+ */
+#define PWRMG_STBY	(0x10)  /* state of nSTANDBY signal to CPLD (R)
+				   0 = low, 1 = high */
+#define PWRMG_SPND	(0x04)  /* state of nSUSPEND signal to CPLD (R)
+				   0 = low, 1 = high */
+
+
+/* Extended GPIO Register (section 3.1.12) */
+#define EXTGPIO_STATUS1	(0x04)  /* Status 1 output (RW) (uP_STATUS_1)
+				   0 = set pin low, 1 = set pin high */
+#define EXTGPIO_STATUS2 (0x02)  /* Status 2 output (RW) (uP_STATUS_2)
+				   0 = set pin low, 1 = set pin high */
+#define EXTGPIO_GPIO1	(0x01)  /* General purpose output (RW) (CPLD_GPIO_1)
+				   0 = set pin low, 1 = set pin high */
+
+/* GPIO Data Register (section 3.1.13) */
+#define GPIODATA_GPIO2	(0x01)  /* General purpose input/output (RW) (CPLD_GPIO_2)
+				   0 = set low (output) / read low (input)
+				   1 = set high (output) / read high (input) */
+
+/* GPIO Direction Register (section 3.1.14) */
+#define GPIODIR_GPDR0	(0x01)  /* GPIO2 direction (RW)
+				   0 = output, 1 = input */
+
+#endif  /* __LH7A400_H__ */
diff --git a/include/lxt971a.h b/include/lxt971a.h
new file mode 100755
index 0000000..2b5b6d4
--- /dev/null
+++ b/include/lxt971a.h
@@ -0,0 +1,246 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @References: [1] NS9750 Hardware Reference, December 2003
+ *              [2] Intel LXT971 Datasheet #249414 Rev. 02
+ *              [3] NS7520 Linux Ethernet Driver
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ***********************************************************************/
+
+#ifndef __LXT971A_H__
+#define __LXT971A_H__
+
+/* PHY definitions (LXT971A) [2] */
+#define PHY_COMMON_CTRL    	 	(0x00)
+#define PHY_COMMON_STAT    	 	(0x01)
+#define PHY_COMMON_ID1    	 	(0x02)
+#define PHY_COMMON_ID2           	(0x03)
+#define PHY_COMMON_AUTO_ADV      	(0x04)
+#define PHY_COMMON_AUTO_LNKB     	(0x05)
+#define PHY_COMMON_AUTO_EXP      	(0x06)
+#define PHY_COMMON_AUTO_NEXT     	(0x07)
+#define PHY_COMMON_AUTO_LNKN     	(0x08)
+#define PHY_LXT971_PORT_CFG      	(0x10)
+#define PHY_LXT971_STAT2         	(0x11)
+#define PHY_LXT971_INT_ENABLE    	(0x12)
+#define PHY_LXT971_INT_STATUS    	(0x13)
+#define PHY_LXT971_LED_CFG       	(0x14)
+#define PHY_LXT971_DIG_CFG       	(0x1A)
+#define PHY_LXT971_TX_CTRL       	(0x1E)
+
+/* CTRL PHY Control Register Bit Fields */
+#define PHY_COMMON_CTRL_RESET  	 	(0x8000)
+#define PHY_COMMON_CTRL_LOOPBACK 	(0x4000)
+#define PHY_COMMON_CTRL_SPD_MA   	(0x2040)
+#define PHY_COMMON_CTRL_SPD_10   	(0x0000)
+#define PHY_COMMON_CTRL_SPD_100  	(0x2000)
+#define PHY_COMMON_CTRL_SPD_1000 	(0x0040)
+#define PHY_COMMON_CTRL_SPD_RES  	(0x2040)
+#define PHY_COMMON_CTRL_AUTO_NEG 	(0x1000)
+#define PHY_COMMON_CTRL_POWER_DN 	(0x0800)
+#define PHY_COMMON_CTRL_ISOLATE	 	(0x0400)
+#define PHY_COMMON_CTRL_RES_AUTO 	(0x0200)
+#define PHY_COMMON_CTRL_DUPLEX	 	(0x0100)
+#define PHY_COMMON_CTRL_COL_TEST 	(0x0080)
+#define PHY_COMMON_CTRL_RES1     	(0x003F)
+
+/* STAT Status Register Bit Fields */
+#define PHY_COMMON_STAT_100BT4	 	(0x8000)
+#define PHY_COMMON_STAT_100BXFD	 	(0x4000)
+#define PHY_COMMON_STAT_100BXHD	 	(0x2000)
+#define PHY_COMMON_STAT_10BTFD	 	(0x1000)
+#define PHY_COMMON_STAT_10BTHD	 	(0x0800)
+#define PHY_COMMON_STAT_100BT2FD 	(0x0400)
+#define PHY_COMMON_STAT_100BT2HD 	(0x0200)
+#define PHY_COMMON_STAT_EXT_STAT 	(0x0100)
+#define PHY_COMMON_STAT_RES1	 	(0x0080)
+#define PHY_COMMON_STAT_MF_PSUP	 	(0x0040)
+#define PHY_COMMON_STAT_AN_COMP  	(0x0020)
+#define PHY_COMMON_STAT_RMT_FLT	 	(0x0010)
+#define PHY_COMMON_STAT_AN_CAP	 	(0x0008)
+#define PHY_COMMON_STAT_LNK_STAT 	(0x0004)
+#define PHY_COMMON_STAT_JAB_DTCT 	(0x0002)
+#define PHY_COMMON_STAT_EXT_CAP	 	(0x0001)
+
+/* AUTO_ADV Auto-neg Advert Register Bit Fields */
+#define PHY_COMMON_AUTO_ADV_NP       	(0x8000)
+#define PHY_COMMON_AUTO_ADV_RES1        (0x4000)
+#define PHY_COMMON_AUTO_ADV_RMT_FLT     (0x2000)
+#define PHY_COMMON_AUTO_ADV_RES2        (0x1000)
+#define PHY_COMMON_AUTO_ADV_AS_PAUSE    (0x0800)
+#define PHY_COMMON_AUTO_ADV_PAUSE       (0x0400)
+#define PHY_COMMON_AUTO_ADV_100BT4      (0x0200)
+#define PHY_COMMON_AUTO_ADV_100BTXFD   	(0x0100)
+#define PHY_COMMON_AUTO_ADV_100BTX      (0x0080)
+#define PHY_COMMON_AUTO_ADV_10BTFD   	(0x0040)
+#define PHY_COMMON_AUTO_ADV_10BT     	(0x0020)
+#define PHY_COMMON_AUTO_ADV_SEL_FLD_MA  (0x001F)
+#define PHY_COMMON_AUTO_ADV_802_9       (0x0002)
+#define PHY_COMMON_AUTO_ADV_802_3       (0x0001)
+
+/* AUTO_LNKB Auto-neg Link Ability Register Bit Fields */
+#define PHY_COMMON_AUTO_LNKB_NP       	(0x8000)
+#define PHY_COMMON_AUTO_LNKB_ACK        (0x4000)
+#define PHY_COMMON_AUTO_LNKB_RMT_FLT    (0x2000)
+#define PHY_COMMON_AUTO_LNKB_RES2       (0x1000)
+#define PHY_COMMON_AUTO_LNKB_AS_PAUSE   (0x0800)
+#define PHY_COMMON_AUTO_LNKB_PAUSE      (0x0400)
+#define PHY_COMMON_AUTO_LNKB_100BT4     (0x0200)
+#define PHY_COMMON_AUTO_LNKB_100BTXFD   (0x0100)
+#define PHY_COMMON_AUTO_LNKB_100BTX     (0x0080)
+#define PHY_COMMON_AUTO_LNKB_10BTFD   	(0x0040)
+#define PHY_COMMON_AUTO_LNKB_10BT     	(0x0020)
+#define PHY_COMMON_AUTO_LNKB_SEL_FLD_MA (0x001F)
+#define PHY_COMMON_AUTO_LNKB_802_9      (0x0002)
+#define PHY_COMMON_AUTO_LNKB_802_3      (0x0001)
+
+/* AUTO_EXP Auto-neg Expansion Register Bit Fields */
+#define PHY_COMMON_AUTO_EXP_RES1        (0xFFC0)
+#define PHY_COMMON_AUTO_EXP_BASE_PAGE   (0x0020)
+#define PHY_COMMON_AUTO_EXP_PAR_DT_FLT  (0x0010)
+#define PHY_COMMON_AUTO_EXP_LNK_NP_CAP  (0x0008)
+#define PHY_COMMON_AUTO_EXP_NP_CAP      (0x0004)
+#define PHY_COMMON_AUTO_EXP_PAGE_REC    (0x0002)
+#define PHY_COMMON_AUTO_EXP_LNK_AN_CAP  (0x0001)
+
+/* AUTO_NEXT Aut-neg Next Page Tx Register Bit Fields */
+#define PHY_COMMON_AUTO_NEXT_NP         (0x8000)
+#define PHY_COMMON_AUTO_NEXT_RES1       (0x4000)
+#define PHY_COMMON_AUTO_NEXT_MSG_PAGE   (0x2000)
+#define PHY_COMMON_AUTO_NEXT_ACK_2      (0x1000)
+#define PHY_COMMON_AUTO_NEXT_TOGGLE     (0x0800)
+#define PHY_COMMON_AUTO_NEXT_MSG        (0x07FF)
+
+/* AUTO_LNKN Auto-neg Link Partner Rx Reg Bit Fields */
+#define PHY_COMMON_AUTO_LNKN_NP         (0x8000)
+#define PHY_COMMON_AUTO_LNKN_ACK        (0x4000)
+#define PHY_COMMON_AUTO_LNKN_MSG_PAGE   (0x2000)
+#define PHY_COMMON_AUTO_LNKN_ACK_2      (0x1000)
+#define PHY_COMMON_AUTO_LNKN_TOGGLE     (0x0800)
+#define PHY_COMMON_AUTO_LNKN_MSG        (0x07FF)
+
+/* PORT_CFG Port Configuration Register Bit Fields */
+#define PHY_LXT971_PORT_CFG_RES1        (0x8000)
+#define PHY_LXT971_PORT_CFG_FORCE_LNK   (0x4000)
+#define PHY_LXT971_PORT_CFG_TX_DISABLE  (0x2000)
+#define PHY_LXT971_PORT_CFG_BYPASS_SCR  (0x1000)
+#define PHY_LXT971_PORT_CFG_RES2        (0x0800)
+#define PHY_LXT971_PORT_CFG_JABBER      (0x0400)
+#define PHY_LXT971_PORT_CFG_SQE	        (0x0200)
+#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
+#define PHY_LXT971_PORT_CFG_CRS_SEL     (0x0080)
+#define PHY_LXT971_PORT_CFG_SLEEP_MODE  (0x0040)
+#define PHY_LXT971_PORT_CFG_PRE_EN      (0x0020)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_MA  (0x0018)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
+#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
+#define PHY_LXT971_PORT_CFG_ALT_NP      (0x0002)
+#define PHY_LXT971_PORT_CFG_FIBER_SEL   (0x0001)
+
+/* STAT2 Status Register #2 Bit Fields */
+#define PHY_LXT971_STAT2_RES1   	(0x8000)
+#define PHY_LXT971_STAT2_100BTX 	(0x4000)
+#define PHY_LXT971_STAT2_TX_STATUS	(0x2000)
+#define PHY_LXT971_STAT2_RX_STATUS	(0x1000)
+#define PHY_LXT971_STAT2_COL_STATUS	(0x0800)
+#define PHY_LXT971_STAT2_LINK   	(0x0400)
+#define PHY_LXT971_STAT2_DUPLEX_MODE	(0x0200)
+#define PHY_LXT971_STAT2_AUTO_NEG	(0x0100)
+#define PHY_LXT971_STAT2_AUTO_NEG_COMP 	(0x0080)
+#define PHY_LXT971_STAT2_RES2   	(0x0040)
+#define PHY_LXT971_STAT2_POLARITY	(0x0020)
+#define PHY_LXT971_STAT2_PAUSE  	(0x0010)
+#define PHY_LXT971_STAT2_ERROR  	(0x0008)
+#define PHY_LXT971_STAT2_RES3   	(0x0007)
+
+/* INT_ENABLE Interrupt Enable Register Bit Fields */
+#define PHY_LXT971_INT_ENABLE_RES1      (0xFF00)
+#define PHY_LXT971_INT_ENABLE_ANMSK     (0x0080)
+#define PHY_LXT971_INT_ENABLE_SPEEDMSK  (0x0040)
+#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
+#define PHY_LXT971_INT_ENABLE_LINKMSK   (0x0010)
+#define PHY_LXT971_INT_ENABLE_RES2      (0x000C)
+#define PHY_LXT971_INT_ENABLE_INTEN     (0x0002)
+#define PHY_LXT971_INT_ENABLE_TINT      (0x0001)
+
+/* INT_STATUS Interrupt Status Register Bit Fields */
+#define PHY_LXT971_INT_STATUS_RES1      (0xFF00)
+#define PHY_LXT971_INT_STATUS_ANDONE    (0x0080)
+#define PHY_LXT971_INT_STATUS_SPEEDCHG  (0x0040)
+#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
+#define PHY_LXT971_INT_STATUS_LINKCHG   (0x0010)
+#define PHY_LXT971_INT_STATUS_RES2      (0x0008)
+#define PHY_LXT971_INT_STATUS_MDINT     (0x0004)
+#define PHY_LXT971_INT_STATUS_RES3      (0x0003)
+
+/* LED_CFG Interrupt LED Configuration Register Bit Fields */
+#define PHY_LXT971_LED_CFG_SHIFT_LED1   (0x000C)
+#define PHY_LXT971_LED_CFG_SHIFT_LED2   (0x0008)
+#define PHY_LXT971_LED_CFG_SHIFT_LED3   (0x0004)
+#define PHY_LXT971_LED_CFG_LEDFREQ_MA	(0x000C)
+#define PHY_LXT971_LED_CFG_LEDFREQ_RES	(0x000C)
+#define PHY_LXT971_LED_CFG_LEDFREQ_100	(0x0008)
+#define PHY_LXT971_LED_CFG_LEDFREQ_60	(0x0004)
+#define PHY_LXT971_LED_CFG_LEDFREQ_30	(0x0000)
+#define PHY_LXT971_LED_CFG_PULSE_STR    (0x0002)
+#define PHY_LXT971_LED_CFG_RES1         (0x0001)
+
+/* only one of these values must be shifted for each SHIFT_LED?  */
+#define PHY_LXT971_LED_CFG_UNUSED1      (0x000F)
+#define PHY_LXT971_LED_CFG_DUPLEX_COL   (0x000E)
+#define PHY_LXT971_LED_CFG_LINK_ACT     (0x000D)
+#define PHY_LXT971_LED_CFG_LINK_RX      (0x000C)
+#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
+#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
+#define PHY_LXT971_LED_CFG_TEST_OFF     (0x0009)
+#define PHY_LXT971_LED_CFG_TEST_ON      (0x0008)
+#define PHY_LXT971_LED_CFG_RX_OR_TX     (0x0007)
+#define PHY_LXT971_LED_CFG_UNUSED2      (0x0006)
+#define PHY_LXT971_LED_CFG_DUPLEX       (0x0005)
+#define PHY_LXT971_LED_CFG_LINK	        (0x0004)
+#define PHY_LXT971_LED_CFG_COLLISION    (0x0003)
+#define PHY_LXT971_LED_CFG_RECEIVE      (0x0002)
+#define PHY_LXT971_LED_CFG_TRANSMIT     (0x0001)
+#define PHY_LXT971_LED_CFG_SPEED        (0x0000)
+
+/* DIG_CFG Digitial Configuration Register Bit Fields */
+#define PHY_LXT971_DIG_CFG_RES1 	(0xF000)
+#define PHY_LXT971_DIG_CFG_MII_DRIVE	(0x0800)
+#define PHY_LXT971_DIG_CFG_RES2 	(0x0400)
+#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL	(0x0200)
+#define PHY_LXT971_DIG_CFG_RES3 	(0x01FF)
+
+#define PHY_LXT971_MDIO_MAX_CLK		(8000000)
+#define PHY_MDIO_MAX_CLK		(2500000)
+
+/* TX_CTRL Transmit Control Register Bit Fields
+   documentation is buggy for this register, therefore setting not included */
+
+typedef enum
+{
+	PHY_NONE    = 0x0000, /* no PHY detected yet */
+	PHY_LXT971A = 0x0013
+} PhyType;
+
+#endif /* __LXT971A_H__ */
diff --git a/include/lynxkdi.h b/include/lynxkdi.h
new file mode 100755
index 0000000..fbf7617
--- /dev/null
+++ b/include/lynxkdi.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2003
+ * Orbacom Systems, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __LYNXKDI_H__
+#define __LYNXKDI_H__
+
+
+/* Boot parameter struct passed to kernel
+ */
+typedef struct lynxos_bootparms_t {
+	uint8_t		rsvd1[2];	/* Reserved			*/
+	uint8_t		ethaddr[6];	/* Ethernet address		*/
+	uint16_t	flags;		/* Boot flags			*/
+	uint32_t	rate;		/* System frequency		*/
+	uint32_t	clock_ref;	/* Time reference		*/
+	uint32_t	dramsz;		/* DRAM size			*/
+	uint32_t	rsvd2;		/* Reserved			*/
+} lynxos_bootparms_t;
+
+
+#endif	/* __LYNXKDI_H__ */
diff --git a/include/malloc.h b/include/malloc.h
new file mode 100755
index 0000000..9d285ee
--- /dev/null
+++ b/include/malloc.h
@@ -0,0 +1,944 @@
+/*
+  A version of malloc/free/realloc written by Doug Lea and released to the
+  public domain.  Send questions/comments/complaints/performance data
+  to dl@cs.oswego.edu
+
+* VERSION 2.6.6  Sun Mar  5 19:10:03 2000  Doug Lea  (dl at gee)
+
+   Note: There may be an updated version of this malloc obtainable at
+	   ftp://g.oswego.edu/pub/misc/malloc.c
+	 Check before installing!
+
+* Why use this malloc?
+
+  This is not the fastest, most space-conserving, most portable, or
+  most tunable malloc ever written. However it is among the fastest
+  while also being among the most space-conserving, portable and tunable.
+  Consistent balance across these factors results in a good general-purpose
+  allocator. For a high-level description, see
+     http://g.oswego.edu/dl/html/malloc.html
+
+* Synopsis of public routines
+
+  (Much fuller descriptions are contained in the program documentation below.)
+
+  malloc(size_t n);
+     Return a pointer to a newly allocated chunk of at least n bytes, or null
+     if no space is available.
+  free(Void_t* p);
+     Release the chunk of memory pointed to by p, or no effect if p is null.
+  realloc(Void_t* p, size_t n);
+     Return a pointer to a chunk of size n that contains the same data
+     as does chunk p up to the minimum of (n, p's size) bytes, or null
+     if no space is available. The returned pointer may or may not be
+     the same as p. If p is null, equivalent to malloc.  Unless the
+     #define REALLOC_ZERO_BYTES_FREES below is set, realloc with a
+     size argument of zero (re)allocates a minimum-sized chunk.
+  memalign(size_t alignment, size_t n);
+     Return a pointer to a newly allocated chunk of n bytes, aligned
+     in accord with the alignment argument, which must be a power of
+     two.
+  valloc(size_t n);
+     Equivalent to memalign(pagesize, n), where pagesize is the page
+     size of the system (or as near to this as can be figured out from
+     all the includes/defines below.)
+  pvalloc(size_t n);
+     Equivalent to valloc(minimum-page-that-holds(n)), that is,
+     round up n to nearest pagesize.
+  calloc(size_t unit, size_t quantity);
+     Returns a pointer to quantity * unit bytes, with all locations
+     set to zero.
+  cfree(Void_t* p);
+     Equivalent to free(p).
+  malloc_trim(size_t pad);
+     Release all but pad bytes of freed top-most memory back
+     to the system. Return 1 if successful, else 0.
+  malloc_usable_size(Void_t* p);
+     Report the number usable allocated bytes associated with allocated
+     chunk p. This may or may not report more bytes than were requested,
+     due to alignment and minimum size constraints.
+  malloc_stats();
+     Prints brief summary statistics on stderr.
+  mallinfo()
+     Returns (by copy) a struct containing various summary statistics.
+  mallopt(int parameter_number, int parameter_value)
+     Changes one of the tunable parameters described below. Returns
+     1 if successful in changing the parameter, else 0.
+
+* Vital statistics:
+
+  Alignment:                            8-byte
+       8 byte alignment is currently hardwired into the design.  This
+       seems to suffice for all current machines and C compilers.
+
+  Assumed pointer representation:       4 or 8 bytes
+       Code for 8-byte pointers is untested by me but has worked
+       reliably by Wolfram Gloger, who contributed most of the
+       changes supporting this.
+
+  Assumed size_t  representation:       4 or 8 bytes
+       Note that size_t is allowed to be 4 bytes even if pointers are 8.
+
+  Minimum overhead per allocated chunk: 4 or 8 bytes
+       Each malloced chunk has a hidden overhead of 4 bytes holding size
+       and status information.
+
+  Minimum allocated size: 4-byte ptrs:  16 bytes    (including 4 overhead)
+			  8-byte ptrs:  24/32 bytes (including, 4/8 overhead)
+
+       When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte
+       ptrs but 4 byte size) or 24 (for 8/8) additional bytes are
+       needed; 4 (8) for a trailing size field
+       and 8 (16) bytes for free list pointers. Thus, the minimum
+       allocatable size is 16/24/32 bytes.
+
+       Even a request for zero bytes (i.e., malloc(0)) returns a
+       pointer to something of the minimum allocatable size.
+
+  Maximum allocated size: 4-byte size_t: 2^31 -  8 bytes
+			  8-byte size_t: 2^63 - 16 bytes
+
+       It is assumed that (possibly signed) size_t bit values suffice to
+       represent chunk sizes. `Possibly signed' is due to the fact
+       that `size_t' may be defined on a system as either a signed or
+       an unsigned type. To be conservative, values that would appear
+       as negative numbers are avoided.
+       Requests for sizes with a negative sign bit when the request
+       size is treaded as a long will return null.
+
+  Maximum overhead wastage per allocated chunk: normally 15 bytes
+
+       Alignnment demands, plus the minimum allocatable size restriction
+       make the normal worst-case wastage 15 bytes (i.e., up to 15
+       more bytes will be allocated than were requested in malloc), with
+       two exceptions:
+	 1. Because requests for zero bytes allocate non-zero space,
+	    the worst case wastage for a request of zero bytes is 24 bytes.
+	 2. For requests >= mmap_threshold that are serviced via
+	    mmap(), the worst case wastage is 8 bytes plus the remainder
+	    from a system page (the minimal mmap unit); typically 4096 bytes.
+
+* Limitations
+
+    Here are some features that are NOT currently supported
+
+    * No user-definable hooks for callbacks and the like.
+    * No automated mechanism for fully checking that all accesses
+      to malloced memory stay within their bounds.
+    * No support for compaction.
+
+* Synopsis of compile-time options:
+
+    People have reported using previous versions of this malloc on all
+    versions of Unix, sometimes by tweaking some of the defines
+    below. It has been tested most extensively on Solaris and
+    Linux. It is also reported to work on WIN32 platforms.
+    People have also reported adapting this malloc for use in
+    stand-alone embedded systems.
+
+    The implementation is in straight, hand-tuned ANSI C.  Among other
+    consequences, it uses a lot of macros.  Because of this, to be at
+    all usable, this code should be compiled using an optimizing compiler
+    (for example gcc -O2) that can simplify expressions and control
+    paths.
+
+  __STD_C                  (default: derived from C compiler defines)
+     Nonzero if using ANSI-standard C compiler, a C++ compiler, or
+     a C compiler sufficiently close to ANSI to get away with it.
+  DEBUG                    (default: NOT defined)
+     Define to enable debugging. Adds fairly extensive assertion-based
+     checking to help track down memory errors, but noticeably slows down
+     execution.
+  REALLOC_ZERO_BYTES_FREES (default: NOT defined)
+     Define this if you think that realloc(p, 0) should be equivalent
+     to free(p). Otherwise, since malloc returns a unique pointer for
+     malloc(0), so does realloc(p, 0).
+  HAVE_MEMCPY               (default: defined)
+     Define if you are not otherwise using ANSI STD C, but still
+     have memcpy and memset in your C library and want to use them.
+     Otherwise, simple internal versions are supplied.
+  USE_MEMCPY               (default: 1 if HAVE_MEMCPY is defined, 0 otherwise)
+     Define as 1 if you want the C library versions of memset and
+     memcpy called in realloc and calloc (otherwise macro versions are used).
+     At least on some platforms, the simple macro versions usually
+     outperform libc versions.
+  HAVE_MMAP                 (default: defined as 1)
+     Define to non-zero to optionally make malloc() use mmap() to
+     allocate very large blocks.
+  HAVE_MREMAP                 (default: defined as 0 unless Linux libc set)
+     Define to non-zero to optionally make realloc() use mremap() to
+     reallocate very large blocks.
+  malloc_getpagesize        (default: derived from system #includes)
+     Either a constant or routine call returning the system page size.
+  HAVE_USR_INCLUDE_MALLOC_H (default: NOT defined)
+     Optionally define if you are on a system with a /usr/include/malloc.h
+     that declares struct mallinfo. It is not at all necessary to
+     define this even if you do, but will ensure consistency.
+  INTERNAL_SIZE_T           (default: size_t)
+     Define to a 32-bit type (probably `unsigned int') if you are on a
+     64-bit machine, yet do not want or need to allow malloc requests of
+     greater than 2^31 to be handled. This saves space, especially for
+     very small chunks.
+  INTERNAL_LINUX_C_LIB      (default: NOT defined)
+     Defined only when compiled as part of Linux libc.
+     Also note that there is some odd internal name-mangling via defines
+     (for example, internally, `malloc' is named `mALLOc') needed
+     when compiling in this case. These look funny but don't otherwise
+     affect anything.
+  WIN32                     (default: undefined)
+     Define this on MS win (95, nt) platforms to compile in sbrk emulation.
+  LACKS_UNISTD_H            (default: undefined if not WIN32)
+     Define this if your system does not have a <unistd.h>.
+  LACKS_SYS_PARAM_H         (default: undefined if not WIN32)
+     Define this if your system does not have a <sys/param.h>.
+  MORECORE                  (default: sbrk)
+     The name of the routine to call to obtain more memory from the system.
+  MORECORE_FAILURE          (default: -1)
+     The value returned upon failure of MORECORE.
+  MORECORE_CLEARS           (default 1)
+     True (1) if the routine mapped to MORECORE zeroes out memory (which
+     holds for sbrk).
+  DEFAULT_TRIM_THRESHOLD
+  DEFAULT_TOP_PAD
+  DEFAULT_MMAP_THRESHOLD
+  DEFAULT_MMAP_MAX
+     Default values of tunable parameters (described in detail below)
+     controlling interaction with host system routines (sbrk, mmap, etc).
+     These values may also be changed dynamically via mallopt(). The
+     preset defaults are those that give best performance for typical
+     programs/systems.
+  USE_DL_PREFIX             (default: undefined)
+     Prefix all public routines with the string 'dl'.  Useful to
+     quickly avoid procedure declaration conflicts and linker symbol
+     conflicts with existing memory allocation routines.
+
+
+*/
+
+
+#ifndef __MALLOC_H__
+#define __MALLOC_H__
+
+/* Preliminaries */
+
+#ifndef __STD_C
+#ifdef __STDC__
+#define __STD_C     1
+#else
+#if __cplusplus
+#define __STD_C     1
+#else
+#define __STD_C     0
+#endif /*__cplusplus*/
+#endif /*__STDC__*/
+#endif /*__STD_C*/
+
+#ifndef Void_t
+#if (__STD_C || defined(WIN32))
+#define Void_t      void
+#else
+#define Void_t      char
+#endif
+#endif /*Void_t*/
+
+#if __STD_C
+#include <linux/stddef.h>	/* for size_t */
+#else
+#include <sys/types.h>
+#endif	/* __STD_C */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if 0	/* not for U-Boot */
+#include <stdio.h>	/* needed for malloc_stats */
+#endif
+
+
+/*
+  Compile-time options
+*/
+
+
+/*
+    Debugging:
+
+    Because freed chunks may be overwritten with link fields, this
+    malloc will often die when freed memory is overwritten by user
+    programs.  This can be very effective (albeit in an annoying way)
+    in helping track down dangling pointers.
+
+    If you compile with -DDEBUG, a number of assertion checks are
+    enabled that will catch more memory errors. You probably won't be
+    able to make much sense of the actual assertion errors, but they
+    should help you locate incorrectly overwritten memory.  The
+    checking is fairly extensive, and will slow down execution
+    noticeably. Calling malloc_stats or mallinfo with DEBUG set will
+    attempt to check every non-mmapped allocated and free chunk in the
+    course of computing the summmaries. (By nature, mmapped regions
+    cannot be checked very much automatically.)
+
+    Setting DEBUG may also be helpful if you are trying to modify
+    this code. The assertions in the check routines spell out in more
+    detail the assumptions and invariants underlying the algorithms.
+
+*/
+#if 0
+#ifdef DEBUG
+/* #include <assert.h> */
+#define assert(x) ((void)0)
+#else
+#define assert(x) ((void)0)
+#endif
+#endif
+
+/*
+  INTERNAL_SIZE_T is the word-size used for internal bookkeeping
+  of chunk sizes. On a 64-bit machine, you can reduce malloc
+  overhead by defining INTERNAL_SIZE_T to be a 32 bit `unsigned int'
+  at the expense of not being able to handle requests greater than
+  2^31. This limitation is hardly ever a concern; you are encouraged
+  to set this. However, the default version is the same as size_t.
+*/
+
+#ifndef INTERNAL_SIZE_T
+#define INTERNAL_SIZE_T size_t
+#endif
+
+/*
+  REALLOC_ZERO_BYTES_FREES should be set if a call to
+  realloc with zero bytes should be the same as a call to free.
+  Some people think it should. Otherwise, since this malloc
+  returns a unique pointer for malloc(0), so does realloc(p, 0).
+*/
+
+
+/*   #define REALLOC_ZERO_BYTES_FREES */
+
+
+/*
+  WIN32 causes an emulation of sbrk to be compiled in
+  mmap-based options are not currently supported in WIN32.
+*/
+
+/* #define WIN32 */
+#ifdef WIN32
+#define MORECORE wsbrk
+#define HAVE_MMAP 0
+
+#define LACKS_UNISTD_H
+#define LACKS_SYS_PARAM_H
+
+/*
+  Include 'windows.h' to get the necessary declarations for the
+  Microsoft Visual C++ data structures and routines used in the 'sbrk'
+  emulation.
+
+  Define WIN32_LEAN_AND_MEAN so that only the essential Microsoft
+  Visual C++ header files are included.
+*/
+#define WIN32_LEAN_AND_MEAN
+#include <windows.h>
+#endif
+
+
+/*
+  HAVE_MEMCPY should be defined if you are not otherwise using
+  ANSI STD C, but still have memcpy and memset in your C library
+  and want to use them in calloc and realloc. Otherwise simple
+  macro versions are defined here.
+
+  USE_MEMCPY should be defined as 1 if you actually want to
+  have memset and memcpy called. People report that the macro
+  versions are often enough faster than libc versions on many
+  systems that it is better to use them.
+
+*/
+
+#define HAVE_MEMCPY
+
+#ifndef USE_MEMCPY
+#ifdef HAVE_MEMCPY
+#define USE_MEMCPY 1
+#else
+#define USE_MEMCPY 0
+#endif
+#endif
+
+#if (__STD_C || defined(HAVE_MEMCPY))
+
+#if __STD_C
+void* memset(void*, int, size_t);
+void* memcpy(void*, const void*, size_t);
+#else
+#ifdef WIN32
+/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */
+/* 'windows.h' */
+#else
+Void_t* memset();
+Void_t* memcpy();
+#endif
+#endif
+#endif
+
+#if USE_MEMCPY
+
+/* The following macros are only invoked with (2n+1)-multiples of
+   INTERNAL_SIZE_T units, with a positive integer n. This is exploited
+   for fast inline execution when n is small. */
+
+#define MALLOC_ZERO(charp, nbytes)                                            \
+do {                                                                          \
+  INTERNAL_SIZE_T mzsz = (nbytes);                                            \
+  if(mzsz <= 9*sizeof(mzsz)) {                                                \
+    INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp);                         \
+    if(mzsz >= 5*sizeof(mzsz)) {     *mz++ = 0;                               \
+				     *mz++ = 0;                               \
+      if(mzsz >= 7*sizeof(mzsz)) {   *mz++ = 0;                               \
+				     *mz++ = 0;                               \
+	if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0;                               \
+				     *mz++ = 0; }}}                           \
+				     *mz++ = 0;                               \
+				     *mz++ = 0;                               \
+				     *mz   = 0;                               \
+  } else memset((charp), 0, mzsz);                                            \
+} while(0)
+
+#define MALLOC_COPY(dest,src,nbytes)                                          \
+do {                                                                          \
+  INTERNAL_SIZE_T mcsz = (nbytes);                                            \
+  if(mcsz <= 9*sizeof(mcsz)) {                                                \
+    INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src);                        \
+    INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest);                       \
+    if(mcsz >= 5*sizeof(mcsz)) {     *mcdst++ = *mcsrc++;                     \
+				     *mcdst++ = *mcsrc++;                     \
+      if(mcsz >= 7*sizeof(mcsz)) {   *mcdst++ = *mcsrc++;                     \
+				     *mcdst++ = *mcsrc++;                     \
+	if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++;                     \
+				     *mcdst++ = *mcsrc++; }}}                 \
+				     *mcdst++ = *mcsrc++;                     \
+				     *mcdst++ = *mcsrc++;                     \
+				     *mcdst   = *mcsrc  ;                     \
+  } else memcpy(dest, src, mcsz);                                             \
+} while(0)
+
+#else /* !USE_MEMCPY */
+
+/* Use Duff's device for good zeroing/copying performance. */
+
+#define MALLOC_ZERO(charp, nbytes)                                            \
+do {                                                                          \
+  INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp);                           \
+  long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn;                         \
+  if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; }             \
+  switch (mctmp) {                                                            \
+    case 0: for(;;) { *mzp++ = 0;                                             \
+    case 7:           *mzp++ = 0;                                             \
+    case 6:           *mzp++ = 0;                                             \
+    case 5:           *mzp++ = 0;                                             \
+    case 4:           *mzp++ = 0;                                             \
+    case 3:           *mzp++ = 0;                                             \
+    case 2:           *mzp++ = 0;                                             \
+    case 1:           *mzp++ = 0; if(mcn <= 0) break; mcn--; }                \
+  }                                                                           \
+} while(0)
+
+#define MALLOC_COPY(dest,src,nbytes)                                          \
+do {                                                                          \
+  INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src;                            \
+  INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest;                           \
+  long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn;                         \
+  if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; }             \
+  switch (mctmp) {                                                            \
+    case 0: for(;;) { *mcdst++ = *mcsrc++;                                    \
+    case 7:           *mcdst++ = *mcsrc++;                                    \
+    case 6:           *mcdst++ = *mcsrc++;                                    \
+    case 5:           *mcdst++ = *mcsrc++;                                    \
+    case 4:           *mcdst++ = *mcsrc++;                                    \
+    case 3:           *mcdst++ = *mcsrc++;                                    \
+    case 2:           *mcdst++ = *mcsrc++;                                    \
+    case 1:           *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; }       \
+  }                                                                           \
+} while(0)
+
+#endif
+
+
+/*
+  Define HAVE_MMAP to optionally make malloc() use mmap() to
+  allocate very large blocks.  These will be returned to the
+  operating system immediately after a free().
+*/
+
+/***
+#ifndef HAVE_MMAP
+#define HAVE_MMAP 1
+#endif
+***/
+#undef	HAVE_MMAP	/* Not available for U-Boot */
+
+/*
+  Define HAVE_MREMAP to make realloc() use mremap() to re-allocate
+  large blocks.  This is currently only possible on Linux with
+  kernel versions newer than 1.3.77.
+*/
+
+/***
+#ifndef HAVE_MREMAP
+#ifdef INTERNAL_LINUX_C_LIB
+#define HAVE_MREMAP 1
+#else
+#define HAVE_MREMAP 0
+#endif
+#endif
+***/
+#undef	HAVE_MREMAP	/* Not available for U-Boot */
+
+#if HAVE_MMAP
+
+#include <unistd.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+
+#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON)
+#define MAP_ANONYMOUS MAP_ANON
+#endif
+
+#endif /* HAVE_MMAP */
+
+/*
+  Access to system page size. To the extent possible, this malloc
+  manages memory from the system in page-size units.
+
+  The following mechanics for getpagesize were adapted from
+  bsd/gnu getpagesize.h
+*/
+
+#define	LACKS_UNISTD_H	/* Shortcut for U-Boot */
+#define	malloc_getpagesize	4096
+
+#ifndef LACKS_UNISTD_H
+#  include <unistd.h>
+#endif
+
+#ifndef malloc_getpagesize
+#  ifdef _SC_PAGESIZE         /* some SVR4 systems omit an underscore */
+#    ifndef _SC_PAGE_SIZE
+#      define _SC_PAGE_SIZE _SC_PAGESIZE
+#    endif
+#  endif
+#  ifdef _SC_PAGE_SIZE
+#    define malloc_getpagesize sysconf(_SC_PAGE_SIZE)
+#  else
+#    if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE)
+       extern size_t getpagesize();
+#      define malloc_getpagesize getpagesize()
+#    else
+#      ifdef WIN32
+#        define malloc_getpagesize (4096) /* TBD: Use 'GetSystemInfo' instead */
+#      else
+#        ifndef LACKS_SYS_PARAM_H
+#          include <sys/param.h>
+#        endif
+#        ifdef EXEC_PAGESIZE
+#          define malloc_getpagesize EXEC_PAGESIZE
+#        else
+#          ifdef NBPG
+#            ifndef CLSIZE
+#              define malloc_getpagesize NBPG
+#            else
+#              define malloc_getpagesize (NBPG * CLSIZE)
+#            endif
+#          else
+#            ifdef NBPC
+#              define malloc_getpagesize NBPC
+#            else
+#              ifdef PAGESIZE
+#                define malloc_getpagesize PAGESIZE
+#              else
+#                define malloc_getpagesize (4096) /* just guess */
+#              endif
+#            endif
+#          endif
+#        endif
+#      endif
+#    endif
+#  endif
+#endif
+
+
+/*
+
+  This version of malloc supports the standard SVID/XPG mallinfo
+  routine that returns a struct containing the same kind of
+  information you can get from malloc_stats. It should work on
+  any SVID/XPG compliant system that has a /usr/include/malloc.h
+  defining struct mallinfo. (If you'd like to install such a thing
+  yourself, cut out the preliminary declarations as described above
+  and below and save them in a malloc.h file. But there's no
+  compelling reason to bother to do this.)
+
+  The main declaration needed is the mallinfo struct that is returned
+  (by-copy) by mallinfo().  The SVID/XPG malloinfo struct contains a
+  bunch of fields, most of which are not even meaningful in this
+  version of malloc. Some of these fields are are instead filled by
+  mallinfo() with other numbers that might possibly be of interest.
+
+  HAVE_USR_INCLUDE_MALLOC_H should be set if you have a
+  /usr/include/malloc.h file that includes a declaration of struct
+  mallinfo.  If so, it is included; else an SVID2/XPG2 compliant
+  version is declared below.  These must be precisely the same for
+  mallinfo() to work.
+
+*/
+
+/* #define HAVE_USR_INCLUDE_MALLOC_H */
+
+#if HAVE_USR_INCLUDE_MALLOC_H
+#include "/usr/include/malloc.h"
+#else
+
+/* SVID2/XPG mallinfo structure */
+
+struct mallinfo {
+  int arena;    /* total space allocated from system */
+  int ordblks;  /* number of non-inuse chunks */
+  int smblks;   /* unused -- always zero */
+  int hblks;    /* number of mmapped regions */
+  int hblkhd;   /* total space in mmapped regions */
+  int usmblks;  /* unused -- always zero */
+  int fsmblks;  /* unused -- always zero */
+  int uordblks; /* total allocated space */
+  int fordblks; /* total non-inuse space */
+  int keepcost; /* top-most, releasable (via malloc_trim) space */
+};
+
+/* SVID2/XPG mallopt options */
+
+#define M_MXFAST  1    /* UNUSED in this malloc */
+#define M_NLBLKS  2    /* UNUSED in this malloc */
+#define M_GRAIN   3    /* UNUSED in this malloc */
+#define M_KEEP    4    /* UNUSED in this malloc */
+
+#endif
+
+/* mallopt options that actually do something */
+
+#define M_TRIM_THRESHOLD    -1
+#define M_TOP_PAD           -2
+#define M_MMAP_THRESHOLD    -3
+#define M_MMAP_MAX          -4
+
+
+#ifndef DEFAULT_TRIM_THRESHOLD
+#define DEFAULT_TRIM_THRESHOLD (128 * 1024)
+#endif
+
+/*
+    M_TRIM_THRESHOLD is the maximum amount of unused top-most memory
+      to keep before releasing via malloc_trim in free().
+
+      Automatic trimming is mainly useful in long-lived programs.
+      Because trimming via sbrk can be slow on some systems, and can
+      sometimes be wasteful (in cases where programs immediately
+      afterward allocate more large chunks) the value should be high
+      enough so that your overall system performance would improve by
+      releasing.
+
+      The trim threshold and the mmap control parameters (see below)
+      can be traded off with one another. Trimming and mmapping are
+      two different ways of releasing unused memory back to the
+      system. Between these two, it is often possible to keep
+      system-level demands of a long-lived program down to a bare
+      minimum. For example, in one test suite of sessions measuring
+      the XF86 X server on Linux, using a trim threshold of 128K and a
+      mmap threshold of 192K led to near-minimal long term resource
+      consumption.
+
+      If you are using this malloc in a long-lived program, it should
+      pay to experiment with these values.  As a rough guide, you
+      might set to a value close to the average size of a process
+      (program) running on your system.  Releasing this much memory
+      would allow such a process to run in memory.  Generally, it's
+      worth it to tune for trimming rather tham memory mapping when a
+      program undergoes phases where several large chunks are
+      allocated and released in ways that can reuse each other's
+      storage, perhaps mixed with phases where there are no such
+      chunks at all.  And in well-behaved long-lived programs,
+      controlling release of large blocks via trimming versus mapping
+      is usually faster.
+
+      However, in most programs, these parameters serve mainly as
+      protection against the system-level effects of carrying around
+      massive amounts of unneeded memory. Since frequent calls to
+      sbrk, mmap, and munmap otherwise degrade performance, the default
+      parameters are set to relatively high values that serve only as
+      safeguards.
+
+      The default trim value is high enough to cause trimming only in
+      fairly extreme (by current memory consumption standards) cases.
+      It must be greater than page size to have any useful effect.  To
+      disable trimming completely, you can set to (unsigned long)(-1);
+
+
+*/
+
+
+#ifndef DEFAULT_TOP_PAD
+#define DEFAULT_TOP_PAD        (0)
+#endif
+
+/*
+    M_TOP_PAD is the amount of extra `padding' space to allocate or
+      retain whenever sbrk is called. It is used in two ways internally:
+
+      * When sbrk is called to extend the top of the arena to satisfy
+	a new malloc request, this much padding is added to the sbrk
+	request.
+
+      * When malloc_trim is called automatically from free(),
+	it is used as the `pad' argument.
+
+      In both cases, the actual amount of padding is rounded
+      so that the end of the arena is always a system page boundary.
+
+      The main reason for using padding is to avoid calling sbrk so
+      often. Having even a small pad greatly reduces the likelihood
+      that nearly every malloc request during program start-up (or
+      after trimming) will invoke sbrk, which needlessly wastes
+      time.
+
+      Automatic rounding-up to page-size units is normally sufficient
+      to avoid measurable overhead, so the default is 0.  However, in
+      systems where sbrk is relatively slow, it can pay to increase
+      this value, at the expense of carrying around more memory than
+      the program needs.
+
+*/
+
+
+#ifndef DEFAULT_MMAP_THRESHOLD
+#define DEFAULT_MMAP_THRESHOLD (128 * 1024)
+#endif
+
+/*
+
+    M_MMAP_THRESHOLD is the request size threshold for using mmap()
+      to service a request. Requests of at least this size that cannot
+      be allocated using already-existing space will be serviced via mmap.
+      (If enough normal freed space already exists it is used instead.)
+
+      Using mmap segregates relatively large chunks of memory so that
+      they can be individually obtained and released from the host
+      system. A request serviced through mmap is never reused by any
+      other request (at least not directly; the system may just so
+      happen to remap successive requests to the same locations).
+
+      Segregating space in this way has the benefit that mmapped space
+      can ALWAYS be individually released back to the system, which
+      helps keep the system level memory demands of a long-lived
+      program low. Mapped memory can never become `locked' between
+      other chunks, as can happen with normally allocated chunks, which
+      menas that even trimming via malloc_trim would not release them.
+
+      However, it has the disadvantages that:
+
+	 1. The space cannot be reclaimed, consolidated, and then
+	    used to service later requests, as happens with normal chunks.
+	 2. It can lead to more wastage because of mmap page alignment
+	    requirements
+	 3. It causes malloc performance to be more dependent on host
+	    system memory management support routines which may vary in
+	    implementation quality and may impose arbitrary
+	    limitations. Generally, servicing a request via normal
+	    malloc steps is faster than going through a system's mmap.
+
+      All together, these considerations should lead you to use mmap
+      only for relatively large requests.
+
+
+*/
+
+
+#ifndef DEFAULT_MMAP_MAX
+#if HAVE_MMAP
+#define DEFAULT_MMAP_MAX       (64)
+#else
+#define DEFAULT_MMAP_MAX       (0)
+#endif
+#endif
+
+/*
+    M_MMAP_MAX is the maximum number of requests to simultaneously
+      service using mmap. This parameter exists because:
+
+	 1. Some systems have a limited number of internal tables for
+	    use by mmap.
+	 2. In most systems, overreliance on mmap can degrade overall
+	    performance.
+	 3. If a program allocates many large regions, it is probably
+	    better off using normal sbrk-based allocation routines that
+	    can reclaim and reallocate normal heap memory. Using a
+	    small value allows transition into this mode after the
+	    first few allocations.
+
+      Setting to 0 disables all use of mmap.  If HAVE_MMAP is not set,
+      the default value is 0, and attempts to set it to non-zero values
+      in mallopt will fail.
+*/
+
+
+/*
+    USE_DL_PREFIX will prefix all public routines with the string 'dl'.
+      Useful to quickly avoid procedure declaration conflicts and linker
+      symbol conflicts with existing memory allocation routines.
+
+*/
+
+/* #define USE_DL_PREFIX */
+
+
+/*
+
+  Special defines for linux libc
+
+  Except when compiled using these special defines for Linux libc
+  using weak aliases, this malloc is NOT designed to work in
+  multithreaded applications.  No semaphores or other concurrency
+  control are provided to ensure that multiple malloc or free calls
+  don't run at the same time, which could be disasterous. A single
+  semaphore could be used across malloc, realloc, and free (which is
+  essentially the effect of the linux weak alias approach). It would
+  be hard to obtain finer granularity.
+
+*/
+
+
+#ifdef INTERNAL_LINUX_C_LIB
+
+#if __STD_C
+
+Void_t * __default_morecore_init (ptrdiff_t);
+Void_t *(*__morecore)(ptrdiff_t) = __default_morecore_init;
+
+#else
+
+Void_t * __default_morecore_init ();
+Void_t *(*__morecore)() = __default_morecore_init;
+
+#endif
+
+#define MORECORE (*__morecore)
+#define MORECORE_FAILURE 0
+#define MORECORE_CLEARS 1
+
+#else /* INTERNAL_LINUX_C_LIB */
+
+#if __STD_C
+extern Void_t*     sbrk(ptrdiff_t);
+#else
+extern Void_t*     sbrk();
+#endif
+
+#ifndef MORECORE
+#define MORECORE sbrk
+#endif
+
+#ifndef MORECORE_FAILURE
+#define MORECORE_FAILURE -1
+#endif
+
+#ifndef MORECORE_CLEARS
+#define MORECORE_CLEARS 1
+#endif
+
+#endif /* INTERNAL_LINUX_C_LIB */
+
+#if defined(INTERNAL_LINUX_C_LIB) && defined(__ELF__)
+
+#define cALLOc		__libc_calloc
+#define fREe		__libc_free
+#define mALLOc		__libc_malloc
+#define mEMALIGn	__libc_memalign
+#define rEALLOc		__libc_realloc
+#define vALLOc		__libc_valloc
+#define pvALLOc		__libc_pvalloc
+#define mALLINFo	__libc_mallinfo
+#define mALLOPt		__libc_mallopt
+
+#pragma weak calloc = __libc_calloc
+#pragma weak free = __libc_free
+#pragma weak cfree = __libc_free
+#pragma weak malloc = __libc_malloc
+#pragma weak memalign = __libc_memalign
+#pragma weak realloc = __libc_realloc
+#pragma weak valloc = __libc_valloc
+#pragma weak pvalloc = __libc_pvalloc
+#pragma weak mallinfo = __libc_mallinfo
+#pragma weak mallopt = __libc_mallopt
+
+#else
+
+#ifdef USE_DL_PREFIX
+#define cALLOc		dlcalloc
+#define fREe		dlfree
+#define mALLOc		dlmalloc
+#define mEMALIGn	dlmemalign
+#define rEALLOc		dlrealloc
+#define vALLOc		dlvalloc
+#define pvALLOc		dlpvalloc
+#define mALLINFo	dlmallinfo
+#define mALLOPt		dlmallopt
+#else /* USE_DL_PREFIX */
+#define cALLOc		calloc
+#define fREe		free
+#define mALLOc		malloc
+#define mEMALIGn	memalign
+#define rEALLOc		realloc
+#define vALLOc		valloc
+#define pvALLOc		pvalloc
+#define mALLINFo	mallinfo
+#define mALLOPt		mallopt
+#endif /* USE_DL_PREFIX */
+
+#endif
+
+/* Public routines */
+
+#if __STD_C
+
+Void_t* mALLOc(size_t);
+void    fREe(Void_t*);
+Void_t* rEALLOc(Void_t*, size_t);
+Void_t* mEMALIGn(size_t, size_t);
+Void_t* vALLOc(size_t);
+Void_t* pvALLOc(size_t);
+Void_t* cALLOc(size_t, size_t);
+void    cfree(Void_t*);
+int     malloc_trim(size_t);
+size_t  malloc_usable_size(Void_t*);
+void    malloc_stats(void);
+int     mALLOPt(int, int);
+struct mallinfo mALLINFo(void);
+#else
+Void_t* mALLOc();
+void    fREe();
+Void_t* rEALLOc();
+Void_t* mEMALIGn();
+Void_t* vALLOc();
+Void_t* pvALLOc();
+Void_t* cALLOc();
+void    cfree();
+int     malloc_trim();
+size_t  malloc_usable_size();
+void    malloc_stats();
+int     mALLOPt();
+struct mallinfo mALLINFo();
+#endif
+
+
+#ifdef __cplusplus
+};  /* end of extern "C" */
+#endif
+#endif /* __MALLOC_H__ */
diff --git a/include/mii_phy.h b/include/mii_phy.h
new file mode 100755
index 0000000..f0d3e62
--- /dev/null
+++ b/include/mii_phy.h
@@ -0,0 +1,8 @@
+#ifndef _MII_PHY_H_
+#define _MII_PHY_H_
+
+void mii_discover_phy(void);
+unsigned short mii_phy_read(unsigned short reg);
+void mii_phy_write(unsigned short reg, unsigned short val);
+
+#endif
diff --git a/include/miiphy.h b/include/miiphy.h
new file mode 100755
index 0000000..71716b0
--- /dev/null
+++ b/include/miiphy.h
@@ -0,0 +1,160 @@
+/*----------------------------------------------------------------------------+
+|
+|	This source code has been made available to you by IBM on an AS-IS
+|	basis.	Anyone receiving this source is licensed under IBM
+|	copyrights to use it in any way he or she deems fit, including
+|	copying it, modifying it, compiling it, and redistributing it either
+|	with or without modifications.	No license under IBM patents or
+|	patent applications is to be implied by the copyright license.
+|
+|	Any user of this software should understand that IBM cannot provide
+|	technical support for this software and will not be responsible for
+|	any consequences resulting from the use of this software.
+|
+|	Any person who transfers this source code or any derivative work
+|	must include the IBM copyright notice, this paragraph, and the
+|	preceding two paragraphs in the transferred software.
+|
+|	COPYRIGHT   I B M   CORPORATION 1999
+|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+|
+|  File Name:	miiphy.h
+|
+|  Function:	Include file defining PHY registers.
+|
+|  Author:	Mark Wisner
+|
+|  Change Activity-
+|
+|  Date	       Description of Change					BY
+|  ---------   ---------------------					---
+|  04-May-99   Created							MKW
+|  07-Jul-99   Added full duplex support				MKW
+|  08-Sep-01   Tweaks							gvb
+|
++----------------------------------------------------------------------------*/
+#ifndef _miiphy_h_
+#define _miiphy_h_
+
+#include <net.h>
+
+int  miiphy_read(char *devname, unsigned char addr, unsigned char reg,
+		unsigned short *value);
+int  miiphy_write(char *devname, unsigned char addr, unsigned char reg,
+		unsigned short value);
+int  miiphy_info(char *devname, unsigned char addr, unsigned int  *oui,
+		unsigned char *model, unsigned char *rev);
+int  miiphy_reset(char *devname, unsigned char addr);
+int  miiphy_speed(char *devname, unsigned char addr);
+int  miiphy_duplex(char *devname, unsigned char addr);
+#ifdef CFG_FAULT_ECHO_LINK_DOWN
+int  miiphy_link(char *devname, unsigned char addr);
+#endif
+
+void miiphy_init(void);
+
+void miiphy_register(char *devname,
+	int (* read)(char *devname, unsigned char addr,
+		unsigned char reg, unsigned short *value),
+	int (* write)(char *devname, unsigned char addr,
+		unsigned char reg, unsigned short value));
+
+int miiphy_set_current_dev(char *devname);
+char *miiphy_get_current_dev(void);
+
+void miiphy_listdev(void);
+
+#define BB_MII_DEVNAME	"bbmii"
+
+int bb_miiphy_read (char *devname, unsigned char addr,
+		unsigned char reg, unsigned short *value);
+int bb_miiphy_write (char *devname, unsigned char addr,
+		unsigned char reg, unsigned short value);
+
+/* phy seed setup */
+#define AUTO			99
+#define _1000BASET              1000
+#define _100BASET		100
+#define _10BASET		10
+#define HALF			22
+#define FULL			44
+
+/* phy register offsets */
+#define PHY_BMCR		0x00
+#define PHY_BMSR		0x01
+#define PHY_PHYIDR1		0x02
+#define PHY_PHYIDR2		0x03
+#define PHY_ANAR		0x04
+#define PHY_ANLPAR		0x05
+#define PHY_ANER		0x06
+#define PHY_ANNPTR		0x07
+#define PHY_ANLPNP              0x08
+#define PHY_1000BTCR            0x09
+#define PHY_1000BTSR            0x0A
+#define PHY_PHYSTS		0x10
+#define PHY_MIPSCR		0x11
+#define PHY_MIPGSR		0x12
+#define PHY_DCR			0x13
+#define PHY_FCSCR		0x14
+#define PHY_RECR		0x15
+#define PHY_PCSR		0x16
+#define PHY_LBR			0x17
+#define PHY_10BTSCR		0x18
+#define PHY_PHYCTRL		0x19
+
+/* PHY BMCR */
+#define PHY_BMCR_RESET		0x8000
+#define PHY_BMCR_LOOP		0x4000
+#define PHY_BMCR_100MB		0x2000
+#define PHY_BMCR_AUTON		0x1000
+#define PHY_BMCR_POWD		0x0800
+#define PHY_BMCR_ISO		0x0400
+#define PHY_BMCR_RST_NEG	0x0200
+#define PHY_BMCR_DPLX		0x0100
+#define PHY_BMCR_COL_TST	0x0080
+
+#define PHY_BMCR_SPEED_MASK     0x2040
+#define PHY_BMCR_1000_MBPS      0x0040
+#define PHY_BMCR_100_MBPS       0x2000
+#define PHY_BMCR_10_MBPS        0x0000
+
+/* phy BMSR */
+#define PHY_BMSR_100T4		0x8000
+#define PHY_BMSR_100TXF		0x4000
+#define PHY_BMSR_100TXH		0x2000
+#define PHY_BMSR_10TF		0x1000
+#define PHY_BMSR_10TH		0x0800
+#define PHY_BMSR_PRE_SUP	0x0040
+#define PHY_BMSR_AUTN_COMP	0x0020
+#define PHY_BMSR_RF		0x0010
+#define PHY_BMSR_AUTN_ABLE	0x0008
+#define PHY_BMSR_LS		0x0004
+#define PHY_BMSR_JD		0x0002
+#define PHY_BMSR_EXT		0x0001
+
+/*phy ANLPAR */
+#define PHY_ANLPAR_NP		0x8000
+#define PHY_ANLPAR_ACK		0x4000
+#define PHY_ANLPAR_RF		0x2000
+#define PHY_ANLPAR_T4		0x0200
+#define PHY_ANLPAR_TXFD		0x0100
+#define PHY_ANLPAR_TX		0x0080
+#define PHY_ANLPAR_10FD		0x0040
+#define PHY_ANLPAR_10		0x0020
+#define PHY_ANLPAR_100		0x0380	    /* we can run at 100 */
+
+#define PHY_ANLPAR_PSB_MASK     0x001f
+#define PHY_ANLPAR_PSB_802_3    0x0001
+#define PHY_ANLPAR_PSB_802_9    0x0002
+
+/* PHY_1000BTSR */
+#define PHY_1000BTSR_MSCF       0x8000
+#define PHY_1000BTSR_MSCR       0x4000
+#define PHY_1000BTSR_LRS        0x2000
+#define PHY_1000BTSR_RRS        0x1000
+#define PHY_1000BTSR_1000FD     0x0800
+#define PHY_1000BTSR_1000HD     0x0400
+
+#endif
diff --git a/include/mk48t59.h b/include/mk48t59.h
new file mode 100755
index 0000000..03c992e
--- /dev/null
+++ b/include/mk48t59.h
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support for the MK48T59 RTC
+ */
+
+
+#if defined(CONFIG_RTC_MK48T59) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+
+#define RTC_PORT_ADDR0		CFG_ISA_IO +  0x70
+#define RTC_PORT_ADDR1		RTC_PORT_ADDR0 +  0x1
+#define RTC_PORT_DATA		CFG_ISA_IO +  0x76
+
+/* RTC Offsets */
+#define RTC_SECONDS             0x1FF9
+#define RTC_MINUTES             0x1FFA
+#define RTC_HOURS               0x1FFB
+#define RTC_DAY_OF_WEEK         0x1FFC
+#define RTC_DAY_OF_MONTH        0x1FFD
+#define RTC_MONTH               0x1FFE
+#define RTC_YEAR                0x1FFF
+
+#define RTC_CONTROLA            0x1FF8
+#define RTC_CA_WRITE            0x80
+#define RTC_CA_READ             0x40
+#define RTC_CA_CALIB_SIGN       0x20
+#define RTC_CA_CALIB_MASK       0x1f
+
+#define RTC_CONTROLB            0x1FF9
+#define RTC_CB_STOP             0x80
+
+#define RTC_WATCHDOG			0x1FF7
+#define RTC_WDS					0x80
+#define RTC_WD_RB_16TH			0x0
+#define RTC_WD_RB_4TH			0x1
+#define RTC_WD_RB_1				0x2
+#define RTC_WD_RB_4				0x3
+
+void rtc_set_watchdog(short multi, short res);
+void *nvram_read(void *dest, const short src, size_t count);
+void nvram_write(short dest, const void *src, size_t count);
+
+#endif
diff --git a/include/mmc.h b/include/mmc.h
new file mode 100755
index 0000000..13fe9a8
--- /dev/null
+++ b/include/mmc.h
@@ -0,0 +1,57 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MMC_H_
+#define _MMC_H_
+//#include <asm/arch/mmc.h>
+
+int mmc_init(int verbose, int device_num);
+int mmc_read(ulong src, uchar *dst, int size);
+int mmc_write(uchar *src, ulong dst, int size);
+ulong mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst);
+ulong mmc_bwrite(int dev_num, ulong blknr, ulong blkcnt, ulong *src);
+int mmc_fb_write(unsigned dev_num, ulong blknr, ulong blkcnt, uchar *src);  //Charles,tmp
+int mmc2info(ulong addr);
+int SD_card_inserted(void);
+void SD_Controller_Powerup(void);
+int mmc_wfs_read(unsigned long dev, unsigned long addr, char *filename, unsigned long bytes);
+int mmc_wfs_write(unsigned long dev, unsigned long addr, char *filename, unsigned long bytes);
+
+
+#endif /* _MMC_H_ */
diff --git a/include/mpc106.h b/include/mpc106.h
new file mode 100755
index 0000000..ab6d57e
--- /dev/null
+++ b/include/mpc106.h
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MPC106_PCI_H
+#define _MPC106_PCI_H
+
+/*
+ * Defines for the MPC106 PCI Config address and data registers followed by
+ * defines for the standard PCI device configuration header.
+ */
+#define PCIDEVID_MPC106 		0x0
+
+/*
+ * MPC106 Registers
+ */
+#define	MPC106_REG			0x80000000
+
+#ifdef CFG_ADDRESS_MAP_A
+#define MPC106_REG_ADDR 		0x80000cf8
+#define	MPC106_REG_DATA			0x80000cfc
+#define MPC106_ISA_IO_PHYS		0x80000000
+#define MPC106_ISA_IO_BUS		0x00000000
+#define MPC106_ISA_IO_SIZE		0x00800000
+#define MPC106_PCI_IO_PHYS		0x81000000
+#define MPC106_PCI_IO_BUS		0x01000000
+#define MPC106_PCI_IO_SIZE		0x3e800000
+#define MPC106_PCI_MEM_PHYS		0xc0000000
+#define MPC106_PCI_MEM_BUS		0x00000000
+#define MPC106_PCI_MEM_SIZE		0x3f000000
+#define	MPC106_PCI_MEMORY_PHYS		0x00000000
+#define	MPC106_PCI_MEMORY_BUS		0x80000000
+#define	MPC106_PCI_MEMORY_SIZE		0x80000000
+#else
+#define MPC106_REG_ADDR 		0xfec00cf8
+#define	MPC106_REG_DATA			0xfee00cfc
+#define MPC106_ISA_MEM_PHYS		0xfd000000
+#define MPC106_ISA_MEM_BUS		0x00000000
+#define MPC106_ISA_MEM_SIZE		0x01000000
+#define MPC106_ISA_IO_PHYS		0xfe000000
+#define MPC106_ISA_IO_BUS		0x00000000
+#define MPC106_ISA_IO_SIZE		0x00800000
+#define MPC106_PCI_IO_PHYS		0xfe800000
+#define MPC106_PCI_IO_BUS		0x00800000
+#define MPC106_PCI_IO_SIZE		0x00400000
+#define MPC106_PCI_MEM_PHYS		0x80000000
+#define MPC106_PCI_MEM_BUS		0x80000000
+#define MPC106_PCI_MEM_SIZE		0x7d000000
+#define	MPC106_PCI_MEMORY_PHYS		0x00000000
+#define	MPC106_PCI_MEMORY_BUS		0x00000000
+#define MPC106_PCI_MEMORY_SIZE		0x40000000
+#endif
+
+#define CMD_SERR			0x0100
+#define PCI_CMD_MASTER			0x0004
+#define PCI_CMD_MEMEN			0x0002
+#define PCI_CMD_IOEN			0x0001
+
+#define PCI_STAT_NO_RSV_BITS		0xffff
+
+#define PCI_BUSNUM       		0x40
+#define PCI_SUBBUSNUM    		0x41
+#define PCI_DISCOUNT     		0x42
+
+#define PCI_PICR1			0xA8
+#define PICR1_CF_CBA(value)		((value & 0xff) << 24)
+#define PICR1_CF_BREAD_WS(value)	((value & 0x3) << 22)
+#define PICR1_PROC_TYPE_603		0x40000
+#define PICR1_PROC_TYPE_604		0x60000
+#define PICR1_MCP_EN			0x800
+#define PICR1_CF_DPARK			0x200
+#define PICR1_CF_LOOP_SNOOP		0x10
+#define PICR1_CF_L2_COPY_BACK		0x2
+#define PICR1_CF_L2_CACHE_MASK		0x3
+#define PICR1_CF_APARK			0x8
+#define PICR1_ADDRESS_MAP		0x10000
+#define PICR1_XIO_MODE			0x80000
+#define PICR1_CF_CACHE_1G		0x200000
+
+#define PCI_PICR2			0xAC
+#define PICR2_CF_SNOOP_WS(value)	((value & 0x3) << 18)
+#define PICR2_CF_FLUSH_L2		0x10000000
+#define PICR2_CF_L2_HIT_DELAY(value)	((value & 0x3) << 9)
+#define PICR2_CF_APHASE_WS(value)	((value & 0x3) << 2)
+#define PICR2_CF_INV_MODE		0x00001000
+#define PICR2_CF_MOD_HIGH		0x00020000
+#define PICR2_CF_HIT_HIGH		0x00010000
+#define PICR2_L2_SIZE_256K		0x00000000
+#define PICR2_L2_SIZE_512K		0x00000010
+#define PICR2_L2_SIZE_1MB		0x00000020
+#define PICR2_L2_EN			0x40000000
+#define PICR2_L2_UPDATE_EN		0x80000000
+#define PICR2_CF_ADDR_ONLY_DISABLE	0x00004000
+#define PICR2_CF_FAST_CASTOUT		0x00000080
+#define PICR2_CF_WDATA			0x00000001
+#define PICR2_CF_DATA_RAM_PBURST	0x00400000
+
+/*
+ * Memory controller
+ */
+#define MPC106_MCCR1			0xF0
+#define MCCR1_TYPE_EDO			0x00020000
+#define MCCR1_BK0_9BITS			0x0
+#define MCCR1_BK0_10BITS		0x1
+#define MCCR1_BK0_11BITS		0x2
+#define MCCR1_BK0_12BITS		0x3
+#define MCCR1_BK1_9BITS			0x0
+#define MCCR1_BK1_10BITS		0x4
+#define MCCR1_BK1_11BITS		0x8
+#define MCCR1_BK1_12BITS		0xC
+#define MCCR1_BK2_9BITS			0x00
+#define MCCR1_BK2_10BITS		0x10
+#define MCCR1_BK2_11BITS		0x20
+#define MCCR1_BK2_12BITS		0x30
+#define MCCR1_BK3_9BITS			0x00
+#define MCCR1_BK3_10BITS		0x40
+#define MCCR1_BK3_11BITS		0x80
+#define MCCR1_BK3_12BITS		0xC0
+#define MCCR1_MEMGO			0x00080000
+
+#define MPC106_MCCR2			0xF4
+#define MPC106_MCCR3			0xF8
+#define MPC106_MCCR4			0xFC
+
+#define MPC106_MSAR1			0x80
+#define MPC106_EMSAR1			0x88
+#define MPC106_EMSAR2			0x8C
+#define MPC106_MEAR1			0x90
+#define MPC106_EMEAR1			0x98
+#define MPC106_EMEAR2			0x9C
+
+#define MPC106_MBER			0xA0
+#define MBER_BANK0			0x1
+#define MBER_BANK1			0x2
+#define MBER_BANK2			0x4
+#define MBER_BANK3			0x8
+
+#endif
diff --git a/include/mpc5xx.h b/include/mpc5xx.h
new file mode 100755
index 0000000..7508f6d
--- /dev/null
+++ b/include/mpc5xx.h
@@ -0,0 +1,188 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * File:		mpc5xx.h
+ *
+ * Discription:		mpc5xx specific definitions
+ *
+ */
+
+#ifndef __MPC5XX_H__
+#define __MPC5XX_H__
+
+
+/*-----------------------------------------------------------------------
+ * Exception offsets (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
+
+/*-----------------------------------------------------------------------
+ * ISB bit in IMMR to set internal memory map
+ */
+
+#define CFG_ISB			((CFG_IMMR / 0x00400000) << 1)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control Register
+ */
+#define SYPCR_SWTC	0xffff0000	/* Software Watchdog Timer Count	*/
+#define SYPCR_BMT	0x0000ff00	/* Bus Monitor Timing			*/
+#define SYPCR_BME	0x00000080	/* Bus Monitor Enable			*/
+#define SYPCR_SWF	0x00000008	/* Software Watchdog Freeze		*/
+#define SYPCR_SWE	0x00000004	/* Software Watchdog Enable		*/
+#define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Select	*/
+#define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale		*/
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register
+ */
+#define SIUMCR_EARB	0x80000000	/* External Arbitration			*/
+#define SIUMCR_EARP0	0x00000000	/* External Arbi. Request priority 0	*/
+#define SIUMCR_EARP1	0x10000000	/* External Arbi. Request priority 1	*/
+#define SIUMCR_EARP2	0x20000000	/* External Arbi. Request priority 2	*/
+#define SIUMCR_EARP3	0x30000000	/* External Arbi. Request priority 3	*/
+#define SIUMCR_EARP4	0x40000000	/* External Arbi. Request priority 4	*/
+#define SIUMCR_EARP5	0x50000000	/* External Arbi. Request priority 5	*/
+#define SIUMCR_EARP6	0x60000000	/* External Arbi. Request priority 6	*/
+#define SIUMCR_EARP7	0x70000000	/* External Arbi. Request priority 7	*/
+#define SIUMCR_DSHW	0x00800000	/* Data Showcycles			*/
+#define SIUMCR_DBGC00	0x00000000	/* Debug pins configuration		*/
+#define SIUMCR_DBGC01	0x00200000	/* - " -				*/
+#define SIUMCR_DBGC10	0x00400000	/* - " -				*/
+#define SIUMCR_DBGC11	0x00600000	/* - " -				*/
+#define SIUMCR_DBPC00	0x00000000	/* Debug Port pins Config.		*/
+#define SIUMCR_DBPC01	0x00080000	/* - " -				*/
+#define SIUMCR_DBPC10	0x00100000	/* - " -				*/
+#define SIUMCR_DBPC11	0x00180000	/* - " -				*/
+#define SIUMCR_GPC00	0x00000000	/* General Pins Config 			*/
+#define SIUMCR_GPC01	0x00020000	/* General Pins Config 			*/
+#define SIUMCR_GPC10	0x00040000	/* General Pins Config 			*/
+#define SIUMCR_GPC11	0x00060000	/* General Pins Config 			*/
+#define SIUMCR_DLK	0x00010000	/* Debug Register Lock			*/
+#define SIUMCR_SC00	0x00000000	/* Multi Chip 32 bit			*/
+#define SIUMCR_SC01	0x00004000	/* Muilt Chip 16 bit			*/
+#define SIUMCR_SC10	0x00004000	/* Single adress show			*/
+#define SIUMCR_SC11	0x00006000	/* Single adress			*/
+#define SIUMCR_RCTX	0x00001000	/* Data Parity pins Config.		*/
+#define SIUMCR_MLRC00	0x00000000	/* Multi Level Reserva. Ctrl		*/
+#define SIUMCR_MLRC01	0x00000400	/* - " -				*/
+#define SIUMCR_MLRC10	0x00000800	/* - " -				*/
+#define SIUMCR_MLRC11	0x00000c00	/* - " -				*/
+#define SIUMCR_MTSC	0x00000100	/* Memory transfer      		*/
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control Register
+ */
+#define TBSCR_REFA	((ushort)0x0080)	/* Reference Interrupt Status A	*/
+#define TBSCR_REFB	((ushort)0x0040)	/* Reference Interrupt Status B */
+#define TBSCR_TBF	((ushort)0x0002)	/* Time Base stops while FREEZE */
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control Register
+ */
+#define PISCR_PITF	((ushort)0x0002)	/* PIT stops when FREEZE	*/
+#define PISCR_PS	0x0080			/* Periodic Interrupt Status	*/
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register
+ */
+#define PLPRCR_MF_MSK	0xfff00000	/* MF mask				*/
+#define PLPRCR_DIVF_MSK	0x0000001f	/* DIVF mask				*/
+#define PLPRCR_CSRC_MSK 0x00000400	/* CSRC mask				*/
+#define PLPRCR_MF_SHIFT 0x00000014	/* Multiplication factor shift value	*/
+#define PLPRCR_DIVF_0   0x00000000	/* Division factor 0			*/
+#define PLPRCR_MF_9     0x00900000	/* Mulitipliaction factor 9		*/
+#define PLPRCR_TEXPS	0x00004000	/* TEXP Status				*/
+#define PLPRCR_TMIST	0x00001000	/* Timers Interrupt Status		*/
+#define PLPRCR_CSR	0x00000080	/* CheskStop Reset value		*/
+#define PLPRCR_SPLSS	0x00008000	/* SPLL Lock Status Sticky bit		*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register
+ */
+#define SCCR_DFNL_MSK	0x00000070	/* DFNL mask				*/
+#define SCCR_DFNH_MSK	0x00000007  	/* DFNH mask				*/
+#define SCCR_DFNL_SHIFT 0x0000004	/* DFNL shift value			*/
+#define SCCR_RTSEL	0x00100000	/* RTC circuit input source select	*/
+#define SCCR_EBDF00	0x00000000	/* Division factor 1. CLKOUT is GCLK2   */
+#define SCCR_EBDF11	0x00060000	/* reserved				*/
+#define SCCR_TBS	0x02000000	/* Time Base Source			*/
+#define SCCR_RTDIV	0x01000000	/* RTC Clock Divide 			*/
+#define SCCR_COM00	0x00000000	/* full strength CLKOUT output buffer	*/
+#define SCCR_COM01	0x20000000	/* half strength CLKOUT output buffer	*/
+#define SCCR_DFNL000	0x00000000	/* Division by 2 (default = minimum)	*/
+#define SCCR_DFNH000	0x00000000	/* Division by 1 (default = minimum)	*/
+
+/*-----------------------------------------------------------------------
+ * MC - Memory Controller
+ */
+#define BR_V		0x00000001	/* Bank valid 				*/
+#define BR_BI		0x00000002	/* Burst inhibit 			*/
+#define BR_PS_8		0x00000400	/* 8 bit port size 			*/
+#define BR_PS_16	0x00000800	/* 16 bit port size 			*/
+#define BR_PS_32	0x00000000	/* 32 bit port size 			*/
+#define BR_LBDIR	0x00000008	/* Late burst data in progess		*/
+#define BR_SETA		0x00000004	/* External Data Acknowledge		*/
+#define OR_SCY_3	0x00000030	/* 3 clock cycles wait states		*/
+#define OR_SCY_1	0x00000000	/* 1 clock cycle wait state		*/
+#define OR_SCY_8	0x00000080	/* 8 clock cycles wait states		*/
+#define OR_TRLX		0x00000001	/* Timing relaxed			*/
+#define OR_BSCY		0x00000060	/* Burst beats length in clocks		*/
+#define OR_ACS_10	0x00000600	/* Adress to chip-select setup		*/
+#define OR_CSNT		0x00000800	/* Chip-select negotation time		*/
+#define OR_ETHR		0x00000100	/* Extended hold time on read		*/
+#define OR_ADDR_MK_FF	0xFF000000
+#define OR_ADDR_MK_FFFF	0xFFFF0000
+
+/*-----------------------------------------------------------------------
+ * UMCR - UIMB Module Configuration Register
+ */
+#define UMCR_FSPEED 	0x00000000	/* Full speed. Opposit of UMCR_HSPEED	*/
+#define UMCR_HSPEED 	0x10000000	/* Half speed				*/
+
+/*-----------------------------------------------------------------------
+ * ICTRL - I-Bus Support Control Register
+ */
+#define ICTRL_ISCT_SER_7 0x00000007	/* All indirect change of flow		*/
+
+
+#define NR_IRQS		0		/* Place this later in a separate file */
+
+/*-----------------------------------------------------------------------
+ * SCI - Serial communication interface
+ */
+
+#define SCI_TDRE	0x0100		/* Transmit data register empty 	*/
+#define SCI_TE		0x0008		/* Transmitter enabled 			*/
+#define SCI_RE		0x0004		/* Receiver enabled			*/
+#define SCI_RDRF	0x0040		/* Receive data register full 		*/
+#define SCI_PE		0x0400		/* Parity enable 			*/
+#define SCI_SCXBR_MK	0x1fff		/* Baudrate mask 			*/
+#define SCI_SCXDR_MK	0x00ff		/* Data register mask 			*/
+#define SCI_M_11	0x0200		/* Frame size is 11 bit			*/
+#define SCI_M_10	0x0000		/* Frame size is 10 bit			*/
+#define SCI_PORT_1	((int)1)	/* Place this later somewhere better 	*/
+#define SCI_PORT_2	((int)2)
+
+#endif	/* __MPC5XX_H__ */
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
new file mode 100755
index 0000000..f33d858
--- /dev/null
+++ b/include/mpc5xxx.h
@@ -0,0 +1,704 @@
+/*
+ * include/asm-ppc/mpc5xxx.h
+ *
+ * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
+ * embedded cpu chips
+ *
+ * 2003 (c) MontaVista, Software, Inc.
+ * Author: Dale Farnsworth <dfarnsworth@mvista.com>
+ *
+ * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASMPPC_MPC5XXX_H
+#define __ASMPPC_MPC5XXX_H
+
+/* Processor name */
+#if defined(CONFIG_MPC5200)
+#define CPU_ID_STR	"MPC5200"
+#elif defined(CONFIG_MGT5100)
+#define CPU_ID_STR	"MGT5100"
+#endif
+
+/* Exception offsets (PowerPC standard) */
+#define EXC_OFF_SYS_RESET	0x0100
+
+/* useful macros for manipulating CSx_START/STOP */
+#if defined(CONFIG_MGT5100)
+#define START_REG(start)	((start) >> 15)
+#define STOP_REG(start, size)	(((start) + (size) - 1) >> 15)
+#elif defined(CONFIG_MPC5200)
+#define START_REG(start)	((start) >> 16)
+#define STOP_REG(start, size)	(((start) + (size) - 1) >> 16)
+#endif
+
+/* Internal memory map */
+
+#define MPC5XXX_CS0_START	(CFG_MBAR + 0x0004)
+#define MPC5XXX_CS0_STOP	(CFG_MBAR + 0x0008)
+#define MPC5XXX_CS1_START	(CFG_MBAR + 0x000c)
+#define MPC5XXX_CS1_STOP	(CFG_MBAR + 0x0010)
+#define MPC5XXX_CS2_START	(CFG_MBAR + 0x0014)
+#define MPC5XXX_CS2_STOP	(CFG_MBAR + 0x0018)
+#define MPC5XXX_CS3_START	(CFG_MBAR + 0x001c)
+#define MPC5XXX_CS3_STOP	(CFG_MBAR + 0x0020)
+#define MPC5XXX_CS4_START	(CFG_MBAR + 0x0024)
+#define MPC5XXX_CS4_STOP	(CFG_MBAR + 0x0028)
+#define MPC5XXX_CS5_START	(CFG_MBAR + 0x002c)
+#define MPC5XXX_CS5_STOP	(CFG_MBAR + 0x0030)
+#define MPC5XXX_BOOTCS_START	(CFG_MBAR + 0x004c)
+#define MPC5XXX_BOOTCS_STOP	(CFG_MBAR + 0x0050)
+#define MPC5XXX_ADDECR		(CFG_MBAR + 0x0054)
+
+#if defined(CONFIG_MGT5100)
+#define MPC5XXX_SDRAM_START	(CFG_MBAR + 0x0034)
+#define MPC5XXX_SDRAM_STOP	(CFG_MBAR + 0x0038)
+#define MPC5XXX_PCI1_START	(CFG_MBAR + 0x003c)
+#define MPC5XXX_PCI1_STOP	(CFG_MBAR + 0x0040)
+#define MPC5XXX_PCI2_START	(CFG_MBAR + 0x0044)
+#define MPC5XXX_PCI2_STOP	(CFG_MBAR + 0x0048)
+#elif defined(CONFIG_MPC5200)
+#define MPC5XXX_CS6_START	(CFG_MBAR + 0x0058)
+#define MPC5XXX_CS6_STOP	(CFG_MBAR + 0x005c)
+#define MPC5XXX_CS7_START	(CFG_MBAR + 0x0060)
+#define MPC5XXX_CS7_STOP	(CFG_MBAR + 0x0064)
+#define MPC5XXX_SDRAM_CS0CFG	(CFG_MBAR + 0x0034)
+#define MPC5XXX_SDRAM_CS1CFG	(CFG_MBAR + 0x0038)
+#endif
+
+#define MPC5XXX_SDRAM		(CFG_MBAR + 0x0100)
+#define MPC5XXX_CDM		(CFG_MBAR + 0x0200)
+#define MPC5XXX_LPB		(CFG_MBAR + 0x0300)
+#define MPC5XXX_ICTL		(CFG_MBAR + 0x0500)
+#define MPC5XXX_GPT		(CFG_MBAR + 0x0600)
+#define MPC5XXX_GPIO		(CFG_MBAR + 0x0b00)
+#define MPC5XXX_WU_GPIO         (CFG_MBAR + 0x0c00)
+#define MPC5XXX_PCI		(CFG_MBAR + 0x0d00)
+#define MPC5XXX_SPI		(CFG_MBAR + 0x0f00)
+#define MPC5XXX_USB		(CFG_MBAR + 0x1000)
+#define MPC5XXX_SDMA		(CFG_MBAR + 0x1200)
+#define MPC5XXX_XLBARB		(CFG_MBAR + 0x1f00)
+
+#if defined(CONFIG_MGT5100)
+#define	MPC5XXX_PSC1		(CFG_MBAR + 0x2000)
+#define	MPC5XXX_PSC2		(CFG_MBAR + 0x2400)
+#define	MPC5XXX_PSC3		(CFG_MBAR + 0x2800)
+#elif defined(CONFIG_MPC5200)
+#define	MPC5XXX_PSC1		(CFG_MBAR + 0x2000)
+#define	MPC5XXX_PSC2		(CFG_MBAR + 0x2200)
+#define	MPC5XXX_PSC3		(CFG_MBAR + 0x2400)
+#define	MPC5XXX_PSC4		(CFG_MBAR + 0x2600)
+#define	MPC5XXX_PSC5		(CFG_MBAR + 0x2800)
+#define	MPC5XXX_PSC6		(CFG_MBAR + 0x2c00)
+#endif
+
+#define	MPC5XXX_FEC		(CFG_MBAR + 0x3000)
+#define MPC5XXX_ATA             (CFG_MBAR + 0x3A00)
+
+#define MPC5XXX_I2C1		(CFG_MBAR + 0x3D00)
+#define MPC5XXX_I2C2		(CFG_MBAR + 0x3D40)
+
+#if defined(CONFIG_MGT5100)
+#define MPC5XXX_SRAM		(CFG_MBAR + 0x4000)
+#define MPC5XXX_SRAM_SIZE	(8*1024)
+#elif defined(CONFIG_MPC5200)
+#define MPC5XXX_SRAM		(CFG_MBAR + 0x8000)
+#define MPC5XXX_SRAM_SIZE	(16*1024)
+#endif
+
+/* SDRAM Controller */
+#define MPC5XXX_SDRAM_MODE	(MPC5XXX_SDRAM + 0x0000)
+#define MPC5XXX_SDRAM_CTRL	(MPC5XXX_SDRAM + 0x0004)
+#define MPC5XXX_SDRAM_CONFIG1	(MPC5XXX_SDRAM + 0x0008)
+#define MPC5XXX_SDRAM_CONFIG2	(MPC5XXX_SDRAM + 0x000c)
+#if defined(CONFIG_MGT5100)
+#define MPC5XXX_SDRAM_XLBSEL	(MPC5XXX_SDRAM + 0x0010)
+#endif
+
+/* Clock Distribution Module */
+#define MPC5XXX_CDM_JTAGID	(MPC5XXX_CDM + 0x0000)
+#define MPC5XXX_CDM_PORCFG	(MPC5XXX_CDM + 0x0004)
+#define MPC5XXX_CDM_CFG		(MPC5XXX_CDM + 0x000c)
+#define MPC5XXX_CDM_48_FDC	(MPC5XXX_CDM + 0x0010)
+#define MPC5XXX_CDM_SRESET	(MPC5XXX_CDM + 0x0020)
+
+/* Local Plus Bus interface */
+#define MPC5XXX_CS0_CFG		(MPC5XXX_LPB + 0x0000)
+#define MPC5XXX_CS1_CFG		(MPC5XXX_LPB + 0x0004)
+#define MPC5XXX_CS2_CFG		(MPC5XXX_LPB + 0x0008)
+#define MPC5XXX_CS3_CFG		(MPC5XXX_LPB + 0x000c)
+#define MPC5XXX_CS4_CFG		(MPC5XXX_LPB + 0x0010)
+#define MPC5XXX_CS5_CFG		(MPC5XXX_LPB + 0x0014)
+#define MPC5XXX_BOOTCS_CFG	MPC5XXX_CS0_CFG
+#define MPC5XXX_CS_CTRL		(MPC5XXX_LPB + 0x0018)
+#define MPC5XXX_CS_STATUS	(MPC5XXX_LPB + 0x001c)
+#if defined(CONFIG_MPC5200)
+#define MPC5XXX_CS6_CFG		(MPC5XXX_LPB + 0x0020)
+#define MPC5XXX_CS7_CFG		(MPC5XXX_LPB + 0x0024)
+#define MPC5XXX_CS_BURST	(MPC5XXX_LPB + 0x0028)
+#define MPC5XXX_CS_DEADCYCLE	(MPC5XXX_LPB + 0x002c)
+#endif
+
+#if defined(CONFIG_MPC5200)
+/* XLB Arbiter registers */
+#define MPC5XXX_XLBARB_CFG		(MPC5XXX_XLBARB + 0x40)
+#define MPC5XXX_XLBARB_MPRIEN	(MPC5XXX_XLBARB + 0x64)
+#define MPC5XXX_XLBARB_MPRIVAL	(MPC5XXX_XLBARB + 0x68)
+#endif
+
+/* GPIO registers */
+#define MPC5XXX_GPS_PORT_CONFIG	(MPC5XXX_GPIO + 0x0000)
+
+/* Standard GPIO registers (simple, output only and simple interrupt */
+#define MPC5XXX_GPIO_ENABLE     (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_GPIO_ODE        (MPC5XXX_GPIO + 0x0008)
+#define MPC5XXX_GPIO_DIR        (MPC5XXX_GPIO + 0x000c)
+#define MPC5XXX_GPIO_DATA_O     (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_GPIO_DATA_I     (MPC5XXX_GPIO + 0x0014)
+#define MPC5XXX_GPIO_OO_ENABLE  (MPC5XXX_GPIO + 0x0018)
+#define MPC5XXX_GPIO_OO_DATA    (MPC5XXX_GPIO + 0x001C)
+#define MPC5XXX_GPIO_SI_ENABLE  (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_GPIO_SI_ODE     (MPC5XXX_GPIO + 0x0024)
+#define MPC5XXX_GPIO_SI_DIR     (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_GPIO_SI_DATA    (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_GPIO_SI_IEN     (MPC5XXX_GPIO + 0x0030)
+#define MPC5XXX_GPIO_SI_ITYPE   (MPC5XXX_GPIO + 0x0034)
+#define MPC5XXX_GPIO_SI_MEN     (MPC5XXX_GPIO + 0x0038)
+#define MPC5XXX_GPIO_SI_STATUS  (MPC5XXX_GPIO + 0x003C)
+
+/* WakeUp GPIO registers */
+#define MPC5XXX_WU_GPIO_ENABLE  (MPC5XXX_WU_GPIO + 0x0000)
+#define MPC5XXX_WU_GPIO_ODE     (MPC5XXX_WU_GPIO + 0x0004)
+#define MPC5XXX_WU_GPIO_DIR     (MPC5XXX_WU_GPIO + 0x0008)
+#define MPC5XXX_WU_GPIO_DATA    (MPC5XXX_WU_GPIO + 0x000c)
+
+/* PCI registers */
+#define MPC5XXX_PCI_CMD		(MPC5XXX_PCI + 0x04)
+#define MPC5XXX_PCI_CFG		(MPC5XXX_PCI + 0x0c)
+#define MPC5XXX_PCI_BAR0	(MPC5XXX_PCI + 0x10)
+#define MPC5XXX_PCI_BAR1	(MPC5XXX_PCI + 0x14)
+#if defined(CONFIG_MGT5100)
+#define MPC5XXX_PCI_CTRL	(MPC5XXX_PCI + 0x68)
+#define MPC5XXX_PCI_VALMSKR	(MPC5XXX_PCI + 0x6c)
+#define MPC5XXX_PCI_VALMSKW	(MPC5XXX_PCI + 0x70)
+#define MPC5XXX_PCI_SUBW1	(MPC5XXX_PCI + 0x74)
+#define MPC5XXX_PCI_SUBW2	(MPC5XXX_PCI + 0x78)
+#define MPC5XXX_PCI_WINCOMMAND	(MPC5XXX_PCI + 0x7c)
+#elif defined(CONFIG_MPC5200)
+#define MPC5XXX_PCI_GSCR	(MPC5XXX_PCI + 0x60)
+#define MPC5XXX_PCI_TBATR0	(MPC5XXX_PCI + 0x64)
+#define MPC5XXX_PCI_TBATR1	(MPC5XXX_PCI + 0x68)
+#define MPC5XXX_PCI_TCR		(MPC5XXX_PCI + 0x6c)
+#define MPC5XXX_PCI_IW0BTAR	(MPC5XXX_PCI + 0x70)
+#define MPC5XXX_PCI_IW1BTAR	(MPC5XXX_PCI + 0x74)
+#define MPC5XXX_PCI_IW2BTAR	(MPC5XXX_PCI + 0x78)
+#define MPC5XXX_PCI_IWCR	(MPC5XXX_PCI + 0x80)
+#define MPC5XXX_PCI_ICR		(MPC5XXX_PCI + 0x84)
+#define MPC5XXX_PCI_ISR		(MPC5XXX_PCI + 0x88)
+#define MPC5XXX_PCI_ARB		(MPC5XXX_PCI + 0x8c)
+#define MPC5XXX_PCI_CAR		(MPC5XXX_PCI + 0xf8)
+#endif
+
+/* Interrupt Controller registers */
+#define MPC5XXX_ICTL_PER_MASK	(MPC5XXX_ICTL + 0x0000)
+#define MPC5XXX_ICTL_PER_PRIO1	(MPC5XXX_ICTL + 0x0004)
+#define MPC5XXX_ICTL_PER_PRIO2	(MPC5XXX_ICTL + 0x0008)
+#define MPC5XXX_ICTL_PER_PRIO3	(MPC5XXX_ICTL + 0x000c)
+#define MPC5XXX_ICTL_EXT	(MPC5XXX_ICTL + 0x0010)
+#define MPC5XXX_ICTL_CRIT	(MPC5XXX_ICTL + 0x0014)
+#define MPC5XXX_ICTL_MAIN_PRIO1	(MPC5XXX_ICTL + 0x0018)
+#define MPC5XXX_ICTL_MAIN_PRIO2	(MPC5XXX_ICTL + 0x001c)
+#define MPC5XXX_ICTL_STS	(MPC5XXX_ICTL + 0x0024)
+#define MPC5XXX_ICTL_CRIT_STS	(MPC5XXX_ICTL + 0x0028)
+#define MPC5XXX_ICTL_MAIN_STS	(MPC5XXX_ICTL + 0x002c)
+#define MPC5XXX_ICTL_PER_STS	(MPC5XXX_ICTL + 0x0030)
+#define MPC5XXX_ICTL_BUS_STS	(MPC5XXX_ICTL + 0x0038)
+
+/* General Purpose Timers registers */
+#define MPC5XXX_GPT0_ENABLE		(MPC5XXX_GPT + 0x0)
+#define MPC5XXX_GPT0_COUNTER		(MPC5XXX_GPT + 0x4)
+#define MPC5XXX_GPT1_ENABLE		(MPC5XXX_GPT + 0x10)
+#define MPC5XXX_GPT1_COUNTER		(MPC5XXX_GPT + 0x14)
+#define MPC5XXX_GPT2_ENABLE		(MPC5XXX_GPT + 0x20)
+#define MPC5XXX_GPT2_COUNTER		(MPC5XXX_GPT + 0x24)
+#define MPC5XXX_GPT3_ENABLE		(MPC5XXX_GPT + 0x30)
+#define MPC5XXX_GPT3_COUNTER		(MPC5XXX_GPT + 0x34)
+#define MPC5XXX_GPT4_ENABLE		(MPC5XXX_GPT + 0x40)
+#define MPC5XXX_GPT4_COUNTER		(MPC5XXX_GPT + 0x44)
+#define MPC5XXX_GPT5_ENABLE		(MPC5XXX_GPT + 0x50)
+#define MPC5XXX_GPT5_COUNTER		(MPC5XXX_GPT + 0x54)
+#define MPC5XXX_GPT6_ENABLE		(MPC5XXX_GPT + 0x60)
+#define MPC5XXX_GPT6_COUNTER		(MPC5XXX_GPT + 0x64)
+#define MPC5XXX_GPT7_ENABLE		(MPC5XXX_GPT + 0x70)
+#define MPC5XXX_GPT7_COUNTER		(MPC5XXX_GPT + 0x74)
+
+#define MPC5XXX_GPT7_PWMCFG		(MPC5XXX_GPT + 0x78)
+
+/* ATA registers */
+#define MPC5XXX_ATA_HOST_CONFIG         (MPC5XXX_ATA + 0x0000)
+#define MPC5XXX_ATA_PIO1                (MPC5XXX_ATA + 0x0008)
+#define MPC5XXX_ATA_PIO2                (MPC5XXX_ATA + 0x000C)
+#define MPC5XXX_ATA_SHARE_COUNT         (MPC5XXX_ATA + 0x002C)
+
+/* I2Cn control register bits */
+#define I2C_EN		0x80
+#define I2C_IEN		0x40
+#define I2C_STA		0x20
+#define I2C_TX		0x10
+#define I2C_TXAK	0x08
+#define I2C_RSTA	0x04
+#define I2C_INIT_MASK	(I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
+
+/* I2Cn status register bits */
+#define I2C_CF		0x80
+#define I2C_AAS		0x40
+#define I2C_BB		0x20
+#define I2C_AL		0x10
+#define I2C_SRW		0x04
+#define I2C_IF		0x02
+#define I2C_RXAK	0x01
+
+/* Programmable Serial Controller (PSC) status register bits */
+#define PSC_SR_CDE		0x0080
+#define PSC_SR_RXRDY		0x0100
+#define PSC_SR_RXFULL		0x0200
+#define PSC_SR_TXRDY		0x0400
+#define PSC_SR_TXEMP		0x0800
+#define PSC_SR_OE		0x1000
+#define PSC_SR_PE		0x2000
+#define PSC_SR_FE		0x4000
+#define PSC_SR_RB		0x8000
+
+/* PSC Command values */
+#define PSC_RX_ENABLE		0x0001
+#define PSC_RX_DISABLE		0x0002
+#define PSC_TX_ENABLE		0x0004
+#define PSC_TX_DISABLE		0x0008
+#define PSC_SEL_MODE_REG_1	0x0010
+#define PSC_RST_RX		0x0020
+#define PSC_RST_TX		0x0030
+#define PSC_RST_ERR_STAT	0x0040
+#define PSC_RST_BRK_CHG_INT	0x0050
+#define PSC_START_BRK		0x0060
+#define PSC_STOP_BRK		0x0070
+
+/* PSC Rx FIFO status bits */
+#define PSC_RX_FIFO_ERR		0x0040
+#define PSC_RX_FIFO_UF		0x0020
+#define PSC_RX_FIFO_OF		0x0010
+#define PSC_RX_FIFO_FR		0x0008
+#define PSC_RX_FIFO_FULL	0x0004
+#define PSC_RX_FIFO_ALARM	0x0002
+#define PSC_RX_FIFO_EMPTY	0x0001
+
+/* PSC interrupt mask bits */
+#define PSC_IMR_TXRDY		0x0100
+#define PSC_IMR_RXRDY		0x0200
+#define PSC_IMR_DB		0x0400
+#define PSC_IMR_IPC		0x8000
+
+/* PSC input port change bits */
+#define PSC_IPCR_CTS		0x01
+#define PSC_IPCR_DCD		0x02
+
+/* PSC mode fields */
+#define PSC_MODE_5_BITS		0x00
+#define PSC_MODE_6_BITS		0x01
+#define PSC_MODE_7_BITS		0x02
+#define PSC_MODE_8_BITS		0x03
+#define PSC_MODE_PAREVEN	0x00
+#define PSC_MODE_PARODD		0x04
+#define PSC_MODE_PARFORCE	0x08
+#define PSC_MODE_PARNONE	0x10
+#define PSC_MODE_ERR		0x20
+#define PSC_MODE_FFULL		0x40
+#define PSC_MODE_RXRTS		0x80
+
+#define PSC_MODE_ONE_STOP_5_BITS	0x00
+#define PSC_MODE_ONE_STOP		0x07
+#define PSC_MODE_TWO_STOP		0x0f
+
+/* ATA config fields */
+#define MPC5xxx_ATA_HOSTCONF_SMR	0x80000000UL	/* State machine
+							   reset */
+#define MPC5xxx_ATA_HOSTCONF_FR		0x40000000UL	/* FIFO Reset */
+#define MPC5xxx_ATA_HOSTCONF_IE		0x02000000UL	/* Enable interrupt
+							   in PIO */
+#define MPC5xxx_ATA_HOSTCONF_IORDY	0x01000000UL	/* Drive supports
+							   IORDY protocol */
+
+#ifndef __ASSEMBLY__
+struct mpc5xxx_psc {
+	volatile u8	mode;		/* PSC + 0x00 */
+	volatile u8	reserved0[3];
+	union {				/* PSC + 0x04 */
+		volatile u16	status;
+		volatile u16	clock_select;
+	} sr_csr;
+#define psc_status	sr_csr.status
+#define psc_clock_select sr_csr.clock_select
+	volatile u16	reserved1;
+	volatile u8	command;	/* PSC + 0x08 */
+	volatile u8	reserved2[3];
+	union {				/* PSC + 0x0c */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} buffer;
+#define psc_buffer_8	buffer.buffer_8
+#define psc_buffer_16	buffer.buffer_16
+#define psc_buffer_32	buffer.buffer_32
+	union {				/* PSC + 0x10 */
+		volatile u8	ipcr;
+		volatile u8	acr;
+	} ipcr_acr;
+#define psc_ipcr	ipcr_acr.ipcr
+#define psc_acr		ipcr_acr.acr
+	volatile u8	reserved3[3];
+	union {				/* PSC + 0x14 */
+		volatile u16	isr;
+		volatile u16	imr;
+	} isr_imr;
+#define psc_isr		isr_imr.isr
+#define psc_imr		isr_imr.imr
+	volatile u16	reserved4;
+	volatile u8	ctur;		/* PSC + 0x18 */
+	volatile u8	reserved5[3];
+	volatile u8	ctlr;		/* PSC + 0x1c */
+	volatile u8	reserved6[3];
+	volatile u16	ccr;		/* PSC + 0x20 */
+	volatile u8	reserved7[14];
+	volatile u8	ivr;		/* PSC + 0x30 */
+	volatile u8	reserved8[3];
+	volatile u8	ip;		/* PSC + 0x34 */
+	volatile u8	reserved9[3];
+	volatile u8	op1;		/* PSC + 0x38 */
+	volatile u8	reserved10[3];
+	volatile u8	op0;		/* PSC + 0x3c */
+	volatile u8	reserved11[3];
+	volatile u32	sicr;		/* PSC + 0x40 */
+	volatile u8	ircr1;		/* PSC + 0x44 */
+	volatile u8	reserved12[3];
+	volatile u8	ircr2;		/* PSC + 0x44 */
+	volatile u8	reserved13[3];
+	volatile u8	irsdr;		/* PSC + 0x4c */
+	volatile u8	reserved14[3];
+	volatile u8	irmdr;		/* PSC + 0x50 */
+	volatile u8	reserved15[3];
+	volatile u8	irfdr;		/* PSC + 0x54 */
+	volatile u8	reserved16[3];
+	volatile u16	rfnum;		/* PSC + 0x58 */
+	volatile u16	reserved17;
+	volatile u16	tfnum;		/* PSC + 0x5c */
+	volatile u16	reserved18;
+	volatile u32	rfdata;		/* PSC + 0x60 */
+	volatile u16	rfstat;		/* PSC + 0x64 */
+	volatile u16	reserved20;
+	volatile u8	rfcntl;		/* PSC + 0x68 */
+	volatile u8	reserved21[5];
+	volatile u16	rfalarm;	/* PSC + 0x6e */
+	volatile u16	reserved22;
+	volatile u16	rfrptr;		/* PSC + 0x72 */
+	volatile u16	reserved23;
+	volatile u16	rfwptr;		/* PSC + 0x76 */
+	volatile u16	reserved24;
+	volatile u16	rflrfptr;	/* PSC + 0x7a */
+	volatile u16	reserved25;
+	volatile u16	rflwfptr;	/* PSC + 0x7e */
+	volatile u32	tfdata;		/* PSC + 0x80 */
+	volatile u16	tfstat;		/* PSC + 0x84 */
+	volatile u16	reserved26;
+	volatile u8	tfcntl;		/* PSC + 0x88 */
+	volatile u8	reserved27[5];
+	volatile u16	tfalarm;	/* PSC + 0x8e */
+	volatile u16	reserved28;
+	volatile u16	tfrptr;		/* PSC + 0x92 */
+	volatile u16	reserved29;
+	volatile u16	tfwptr;		/* PSC + 0x96 */
+	volatile u16	reserved30;
+	volatile u16	tflrfptr;	/* PSC + 0x9a */
+	volatile u16	reserved31;
+	volatile u16	tflwfptr;	/* PSC + 0x9e */
+};
+
+struct mpc5xxx_intr {
+	volatile u32	per_mask;	/* INTR + 0x00 */
+	volatile u32	per_pri1;	/* INTR + 0x04 */
+	volatile u32	per_pri2;	/* INTR + 0x08 */
+	volatile u32	per_pri3;	/* INTR + 0x0c */
+	volatile u32	ctrl;		/* INTR + 0x10 */
+	volatile u32	main_mask;	/* INTR + 0x14 */
+	volatile u32	main_pri1;	/* INTR + 0x18 */
+	volatile u32	main_pri2;	/* INTR + 0x1c */
+	volatile u32	reserved1;	/* INTR + 0x20 */
+	volatile u32	enc_status;	/* INTR + 0x24 */
+	volatile u32	crit_status;	/* INTR + 0x28 */
+	volatile u32	main_status;	/* INTR + 0x2c */
+	volatile u32	per_status;	/* INTR + 0x30 */
+	volatile u32	reserved2;	/* INTR + 0x34 */
+	volatile u32	per_error;	/* INTR + 0x38 */
+};
+
+struct mpc5xxx_gpio {
+	volatile u32 port_config;	/* GPIO + 0x00 */
+	volatile u32 simple_gpioe;	/* GPIO + 0x04 */
+	volatile u32 simple_ode;	/* GPIO + 0x08 */
+	volatile u32 simple_ddr;	/* GPIO + 0x0c */
+	volatile u32 simple_dvo;	/* GPIO + 0x10 */
+	volatile u32 simple_ival;	/* GPIO + 0x14 */
+	volatile u8 outo_gpioe;		/* GPIO + 0x18 */
+	volatile u8 reserved1[3];	/* GPIO + 0x19 */
+	volatile u8 outo_dvo;		/* GPIO + 0x1c */
+	volatile u8 reserved2[3];	/* GPIO + 0x1d */
+	volatile u8 sint_gpioe;		/* GPIO + 0x20 */
+	volatile u8 reserved3[3];	/* GPIO + 0x21 */
+	volatile u8 sint_ode;		/* GPIO + 0x24 */
+	volatile u8 reserved4[3];	/* GPIO + 0x25 */
+	volatile u8 sint_ddr;		/* GPIO + 0x28 */
+	volatile u8 reserved5[3];	/* GPIO + 0x29 */
+	volatile u8 sint_dvo;		/* GPIO + 0x2c */
+	volatile u8 reserved6[3];	/* GPIO + 0x2d */
+	volatile u8 sint_inten;		/* GPIO + 0x30 */
+	volatile u8 reserved7[3];	/* GPIO + 0x31 */
+	volatile u16 sint_itype;	/* GPIO + 0x34 */
+	volatile u16 reserved8;		/* GPIO + 0x36 */
+	volatile u8 gpio_control;	/* GPIO + 0x38 */
+	volatile u8 reserved9[3];	/* GPIO + 0x39 */
+	volatile u8 sint_istat;		/* GPIO + 0x3c */
+	volatile u8 sint_ival;		/* GPIO + 0x3d */
+	volatile u8 bus_errs;		/* GPIO + 0x3e */
+	volatile u8 reserved10;		/* GPIO + 0x3f */
+};
+
+struct mpc5xxx_sdma {
+	volatile u32 taskBar;		/* SDMA + 0x00 */
+	volatile u32 currentPointer;	/* SDMA + 0x04 */
+	volatile u32 endPointer;	/* SDMA + 0x08 */
+	volatile u32 variablePointer;	/* SDMA + 0x0c */
+
+	volatile u8 IntVect1;		/* SDMA + 0x10 */
+	volatile u8 IntVect2;		/* SDMA + 0x11 */
+	volatile u16 PtdCntrl;		/* SDMA + 0x12 */
+
+	volatile u32 IntPend;		/* SDMA + 0x14 */
+	volatile u32 IntMask;		/* SDMA + 0x18 */
+
+	volatile u16 tcr_0;		/* SDMA + 0x1c */
+	volatile u16 tcr_1;		/* SDMA + 0x1e */
+	volatile u16 tcr_2;		/* SDMA + 0x20 */
+	volatile u16 tcr_3;		/* SDMA + 0x22 */
+	volatile u16 tcr_4;		/* SDMA + 0x24 */
+	volatile u16 tcr_5;		/* SDMA + 0x26 */
+	volatile u16 tcr_6;		/* SDMA + 0x28 */
+	volatile u16 tcr_7;		/* SDMA + 0x2a */
+	volatile u16 tcr_8;		/* SDMA + 0x2c */
+	volatile u16 tcr_9;		/* SDMA + 0x2e */
+	volatile u16 tcr_a;		/* SDMA + 0x30 */
+	volatile u16 tcr_b;		/* SDMA + 0x32 */
+	volatile u16 tcr_c;		/* SDMA + 0x34 */
+	volatile u16 tcr_d;		/* SDMA + 0x36 */
+	volatile u16 tcr_e;		/* SDMA + 0x38 */
+	volatile u16 tcr_f;		/* SDMA + 0x3a */
+
+	volatile u8 IPR0;		/* SDMA + 0x3c */
+	volatile u8 IPR1;		/* SDMA + 0x3d */
+	volatile u8 IPR2;		/* SDMA + 0x3e */
+	volatile u8 IPR3;		/* SDMA + 0x3f */
+	volatile u8 IPR4;		/* SDMA + 0x40 */
+	volatile u8 IPR5;		/* SDMA + 0x41 */
+	volatile u8 IPR6;		/* SDMA + 0x42 */
+	volatile u8 IPR7;		/* SDMA + 0x43 */
+	volatile u8 IPR8;		/* SDMA + 0x44 */
+	volatile u8 IPR9;		/* SDMA + 0x45 */
+	volatile u8 IPR10;		/* SDMA + 0x46 */
+	volatile u8 IPR11;		/* SDMA + 0x47 */
+	volatile u8 IPR12;		/* SDMA + 0x48 */
+	volatile u8 IPR13;		/* SDMA + 0x49 */
+	volatile u8 IPR14;		/* SDMA + 0x4a */
+	volatile u8 IPR15;		/* SDMA + 0x4b */
+	volatile u8 IPR16;		/* SDMA + 0x4c */
+	volatile u8 IPR17;		/* SDMA + 0x4d */
+	volatile u8 IPR18;		/* SDMA + 0x4e */
+	volatile u8 IPR19;		/* SDMA + 0x4f */
+	volatile u8 IPR20;		/* SDMA + 0x50 */
+	volatile u8 IPR21;		/* SDMA + 0x51 */
+	volatile u8 IPR22;		/* SDMA + 0x52 */
+	volatile u8 IPR23;		/* SDMA + 0x53 */
+	volatile u8 IPR24;		/* SDMA + 0x54 */
+	volatile u8 IPR25;		/* SDMA + 0x55 */
+	volatile u8 IPR26;		/* SDMA + 0x56 */
+	volatile u8 IPR27;		/* SDMA + 0x57 */
+	volatile u8 IPR28;		/* SDMA + 0x58 */
+	volatile u8 IPR29;		/* SDMA + 0x59 */
+	volatile u8 IPR30;		/* SDMA + 0x5a */
+	volatile u8 IPR31;		/* SDMA + 0x5b */
+
+	volatile u32 res1;		/* SDMA + 0x5c */
+	volatile u32 res2;		/* SDMA + 0x60 */
+	volatile u32 res3;		/* SDMA + 0x64 */
+	volatile u32 MDEDebug;		/* SDMA + 0x68 */
+	volatile u32 ADSDebug;		/* SDMA + 0x6c */
+	volatile u32 Value1;		/* SDMA + 0x70 */
+	volatile u32 Value2;		/* SDMA + 0x74 */
+	volatile u32 Control;		/* SDMA + 0x78 */
+	volatile u32 Status;		/* SDMA + 0x7c */
+	volatile u32 EU00;		/* SDMA + 0x80 */
+	volatile u32 EU01;		/* SDMA + 0x84 */
+	volatile u32 EU02;		/* SDMA + 0x88 */
+	volatile u32 EU03;		/* SDMA + 0x8c */
+	volatile u32 EU04;		/* SDMA + 0x90 */
+	volatile u32 EU05;		/* SDMA + 0x94 */
+	volatile u32 EU06;		/* SDMA + 0x98 */
+	volatile u32 EU07;		/* SDMA + 0x9c */
+	volatile u32 EU10;		/* SDMA + 0xa0 */
+	volatile u32 EU11;		/* SDMA + 0xa4 */
+	volatile u32 EU12;		/* SDMA + 0xa8 */
+	volatile u32 EU13;		/* SDMA + 0xac */
+	volatile u32 EU14;		/* SDMA + 0xb0 */
+	volatile u32 EU15;		/* SDMA + 0xb4 */
+	volatile u32 EU16;		/* SDMA + 0xb8 */
+	volatile u32 EU17;		/* SDMA + 0xbc */
+	volatile u32 EU20;		/* SDMA + 0xc0 */
+	volatile u32 EU21;		/* SDMA + 0xc4 */
+	volatile u32 EU22;		/* SDMA + 0xc8 */
+	volatile u32 EU23;		/* SDMA + 0xcc */
+	volatile u32 EU24;		/* SDMA + 0xd0 */
+	volatile u32 EU25;		/* SDMA + 0xd4 */
+	volatile u32 EU26;		/* SDMA + 0xd8 */
+	volatile u32 EU27;		/* SDMA + 0xdc */
+	volatile u32 EU30;		/* SDMA + 0xe0 */
+	volatile u32 EU31;		/* SDMA + 0xe4 */
+	volatile u32 EU32;		/* SDMA + 0xe8 */
+	volatile u32 EU33;		/* SDMA + 0xec */
+	volatile u32 EU34;		/* SDMA + 0xf0 */
+	volatile u32 EU35;		/* SDMA + 0xf4 */
+	volatile u32 EU36;		/* SDMA + 0xf8 */
+	volatile u32 EU37;		/* SDMA + 0xfc */
+};
+
+struct mpc5xxx_i2c {
+	volatile u32 madr;		/* I2Cn + 0x00 */
+	volatile u32 mfdr;		/* I2Cn + 0x04 */
+	volatile u32 mcr;		/* I2Cn + 0x08 */
+	volatile u32 msr;		/* I2Cn + 0x0C */
+	volatile u32 mdr;		/* I2Cn + 0x10 */
+};
+
+struct mpc5xxx_spi {
+	volatile u8 cr1;		/* SPI + 0x0F00 */
+	volatile u8 cr2;		/* SPI + 0x0F01 */
+	volatile u8 reserved1[2];
+	volatile u8 brr;		/* SPI + 0x0F04 */
+	volatile u8 sr;			/* SPI + 0x0F05 */
+	volatile u8 reserved2[3];
+	volatile u8 dr;			/* SPI + 0x0F09 */
+	volatile u8 reserved3[3];
+	volatile u8 pdr;		/* SPI + 0x0F0D */
+	volatile u8 reserved4[2];
+	volatile u8 ddr;		/* SPI + 0x0F10 */
+};
+
+
+struct mpc5xxx_gpt {
+	volatile u32 emsr;		/* GPT + Timer# * 0x10 + 0x00 */
+	volatile u32 cir;		/* GPT + Timer# * 0x10 + 0x04 */
+	volatile u32 pwmcr;		/* GPT + Timer# * 0x10 + 0x08 */
+	volatile u32 sr;		/* GPT + Timer# * 0x10 + 0x0c */
+};
+
+struct mpc5xxx_gpt_0_7 {
+	struct mpc5xxx_gpt gpt0;
+	struct mpc5xxx_gpt gpt1;
+	struct mpc5xxx_gpt gpt2;
+	struct mpc5xxx_gpt gpt3;
+	struct mpc5xxx_gpt gpt4;
+	struct mpc5xxx_gpt gpt5;
+	struct mpc5xxx_gpt gpt6;
+	struct mpc5xxx_gpt gpt7;
+};
+
+struct mscan_buffer {
+	volatile u8  idr[0x8];          /* 0x00 */
+	volatile u8  dsr[0x10];         /* 0x08 */
+	volatile u8  dlr;               /* 0x18 */
+	volatile u8  tbpr;              /* 0x19 */      /* This register is not applicable for receive buffers */
+	volatile u16 rsrv1;             /* 0x1A */
+	volatile u8  tsrh;              /* 0x1C */
+	volatile u8  tsrl;              /* 0x1D */
+	volatile u16 rsrv2;             /* 0x1E */
+};
+
+struct mpc5xxx_mscan {
+	volatile u8  canctl0;           /* MSCAN + 0x00 */
+	volatile u8  canctl1;           /* MSCAN + 0x01 */
+	volatile u16 rsrv1;             /* MSCAN + 0x02 */
+	volatile u8  canbtr0;           /* MSCAN + 0x04 */
+	volatile u8  canbtr1;           /* MSCAN + 0x05 */
+	volatile u16 rsrv2;             /* MSCAN + 0x06 */
+	volatile u8  canrflg;           /* MSCAN + 0x08 */
+	volatile u8  canrier;           /* MSCAN + 0x09 */
+	volatile u16 rsrv3;             /* MSCAN + 0x0A */
+	volatile u8  cantflg;           /* MSCAN + 0x0C */
+	volatile u8  cantier;           /* MSCAN + 0x0D */
+	volatile u16 rsrv4;             /* MSCAN + 0x0E */
+	volatile u8  cantarq;           /* MSCAN + 0x10 */
+	volatile u8  cantaak;           /* MSCAN + 0x11 */
+	volatile u16 rsrv5;             /* MSCAN + 0x12 */
+	volatile u8  cantbsel;          /* MSCAN + 0x14 */
+	volatile u8  canidac;           /* MSCAN + 0x15 */
+	volatile u16 rsrv6[3];          /* MSCAN + 0x16 */
+	volatile u8  canrxerr;          /* MSCAN + 0x1C */
+	volatile u8  cantxerr;          /* MSCAN + 0x1D */
+	volatile u16 rsrv7;             /* MSCAN + 0x1E */
+	volatile u8  canidar0;          /* MSCAN + 0x20 */
+	volatile u8  canidar1;          /* MSCAN + 0x21 */
+	volatile u16 rsrv8;             /* MSCAN + 0x22 */
+	volatile u8  canidar2;          /* MSCAN + 0x24 */
+	volatile u8  canidar3;          /* MSCAN + 0x25 */
+	volatile u16 rsrv9;             /* MSCAN + 0x26 */
+	volatile u8  canidmr0;          /* MSCAN + 0x28 */
+	volatile u8  canidmr1;          /* MSCAN + 0x29 */
+	volatile u16 rsrv10;            /* MSCAN + 0x2A */
+	volatile u8  canidmr2;          /* MSCAN + 0x2C */
+	volatile u8  canidmr3;          /* MSCAN + 0x2D */
+	volatile u16 rsrv11;            /* MSCAN + 0x2E */
+	volatile u8  canidar4;          /* MSCAN + 0x30 */
+	volatile u8  canidar5;          /* MSCAN + 0x31 */
+	volatile u16 rsrv12;            /* MSCAN + 0x32 */
+	volatile u8  canidar6;          /* MSCAN + 0x34 */
+	volatile u8  canidar7;          /* MSCAN + 0x35 */
+	volatile u16 rsrv13;            /* MSCAN + 0x36 */
+	volatile u8  canidmr4;          /* MSCAN + 0x38 */
+	volatile u8  canidmr5;          /* MSCAN + 0x39 */
+	volatile u16 rsrv14;            /* MSCAN + 0x3A */
+	volatile u8  canidmr6;          /* MSCAN + 0x3C */
+	volatile u8  canidmr7;          /* MSCAN + 0x3D */
+	volatile u16 rsrv15;            /* MSCAN + 0x3E */
+
+	struct mscan_buffer canrxfg;    /* MSCAN + 0x40 */    /* Foreground receive buffer */
+	struct mscan_buffer cantxfg;    /* MSCAN + 0x60 */    /* Foreground transmit buffer */
+	};
+
+/* function prototypes */
+void loadtask(int basetask, int tasks);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASMPPC_MPC5XXX_H */
diff --git a/include/mpc8220.h b/include/mpc8220.h
new file mode 100755
index 0000000..ff7acc6
--- /dev/null
+++ b/include/mpc8220.h
@@ -0,0 +1,716 @@
+/*
+ * include/mpc8220.h
+ *
+ * Prototypes, etc. for the Motorola MPC8220
+ * embedded cpu chips
+ *
+ * 2004 (c) Freescale, Inc.
+ * Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __MPC8220_H__
+#define __MPC8220_H__
+
+/* Processor name */
+#if defined(CONFIG_MPC8220)
+#define CPU_ID_STR	    "MPC8220"
+#endif
+
+/* Exception offsets (PowerPC standard) */
+#define EXC_OFF_SYS_RESET   0x0100
+
+/* Internal memory map */
+/* MPC8220 Internal Register MMAP */
+#define MMAP_MBAR	(CFG_MBAR + 0x00000000) /* chip selects		     */
+#define MMAP_MEMCTL	(CFG_MBAR + 0x00000100) /* sdram controller	     */
+#define MMAP_XLBARB	(CFG_MBAR + 0x00000200) /* xlb arbitration control   */
+#define MMAP_CDM	(CFG_MBAR + 0x00000300) /* clock distribution module */
+#define MMAP_VDOPLL	(CFG_MBAR + 0x00000400) /* video PLL		     */
+#define MMAP_FB		(CFG_MBAR + 0x00000500) /* flex bus controller	     */
+#define MMAP_PCFG	(CFG_MBAR + 0x00000600) /* port config		     */
+#define MMAP_ICTL	(CFG_MBAR + 0x00000700) /* interrupt controller	     */
+#define MMAP_GPTMR	(CFG_MBAR + 0x00000800) /* general purpose timers    */
+#define MMAP_SLTMR	(CFG_MBAR + 0x00000900) /* slice timers		     */
+#define MMAP_GPIO	(CFG_MBAR + 0x00000A00) /* gpio module		     */
+#define MMAP_XCPCI	(CFG_MBAR + 0x00000B00) /* pci controller	     */
+#define MMAP_PCIARB	(CFG_MBAR + 0x00000C00) /* pci arbiter		     */
+#define MMAP_EXTDMA1	(CFG_MBAR + 0x00000D00) /* external dma1	     */
+#define MMAP_EXTDMA2	(CFG_MBAR + 0x00000E00) /* external dma1	     */
+#define MMAP_USBH	(CFG_MBAR + 0x00001000) /* usb host		     */
+#define MMAP_CMTMR	(CFG_MBAR + 0x00007f00) /* comm timers		     */
+#define MMAP_DMA	(CFG_MBAR + 0x00008000) /* dma			     */
+#define MMAP_USBD	(CFG_MBAR + 0x00008200) /* usb device		     */
+#define MMAP_COMMPCI	(CFG_MBAR + 0x00008400) /* pci comm Bus regs	     */
+#define MMAP_1284	(CFG_MBAR + 0x00008500) /* 1284			     */
+#define MMAP_PEV	(CFG_MBAR + 0x00008600) /* print engine video	     */
+#define MMAP_PSC1	(CFG_MBAR + 0x00008800) /* psc1 block		     */
+#define MMAP_I2C	(CFG_MBAR + 0x00008f00) /* i2c controller	     */
+#define MMAP_FEC1	(CFG_MBAR + 0x00009000) /* fast ethernet 1	     */
+#define MMAP_FEC2	(CFG_MBAR + 0x00009800) /* fast ethernet 2	     */
+#define MMAP_JBIGRAM	(CFG_MBAR + 0x0000a000) /* jbig RAM		     */
+#define MMAP_JBIG	(CFG_MBAR + 0x0000c000) /* jbig			     */
+#define MMAP_PDLA	(CFG_MBAR + 0x00010000) /*			     */
+#define MMAP_SRAMCFG	(CFG_MBAR + 0x0001ff00) /* SRAM config		     */
+#define MMAP_SRAM	(CFG_MBAR + 0x00020000) /* SRAM			     */
+
+#define SRAM_SIZE	0x8000			/* 32 KB */
+
+/* ------------------------------------------------------------------------ */
+/*
+ * Macro for Programmable Serial Channel
+ */
+/* equates for mode reg. 1 for channel	A or B */
+#define PSC_MR1_RX_RTS		0x80000000    /* receiver RTS enabled */
+#define PSC_MR1_RX_INT		0x40000000    /* receiver intrupt enabled */
+#define PSC_MR1_ERR_MODE	0x20000000    /* block error mode */
+#define PSC_MR1_PAR_MODE_MULTI	0x18000000    /* multi_drop mode */
+#define PSC_MR1_NO_PARITY	0x10000000    /* no parity mode */
+#define PSC_MR1_ALWAYS_0	0x08000000    /* force parity mode */
+#define PSC_MR1_ALWAYS_1	0x0c000000    /* force parity mode */
+#define PSC_MR1_EVEN_PARITY	0x00000000    /* parity mode */
+#define PSC_MR1_ODD_PARITY	0x04000000    /* 0 = even, 1 = odd */
+#define PSC_MR1_BITS_CHAR_8	0x03000000    /* 8 bits */
+#define PSC_MR1_BITS_CHAR_7	0x02000000    /* 7 bits */
+#define PSC_MR1_BITS_CHAR_6	0x01000000    /* 6 bits */
+#define PSC_MR1_BITS_CHAR_5	0x00000000    /* 5 bits */
+
+/* equates for mode reg. 2 for channel	A or B */
+#define PSC_MR2_NORMAL_MODE	0x00000000    /* normal channel mode */
+#define PSC_MR2_AUTO_MODE	0x40000000    /* automatic channel mode */
+#define PSC_MR2_LOOPBACK_LOCL	0x80000000    /* local loopback channel mode */
+#define PSC_MR2_LOOPBACK_REMT	0xc0000000    /* remote loopback channel mode */
+#define PSC_MR2_TX_RTS		0x20000000    /* transmitter RTS enabled */
+#define PSC_MR2_TX_CTS		0x10000000    /* transmitter CTS enabled */
+#define PSC_MR2_STOP_BITS_2	0x0f000000    /* 2 stop bits */
+#define PSC_MR2_STOP_BITS_1	0x07000000    /* 1 stop bit */
+
+/* equates for status reg. A or B */
+#define PSC_SR_BREAK		0x80000000    /* received break */
+#define PSC_SR_NEOF		PSC_SR_BREAK  /* Next byte is EOF - MIR/FIR */
+#define PSC_SR_FRAMING		0x40000000    /* framing error */
+#define PSC_SR_PHYERR		PSC_SR_FRAMING/* Physical Layer error - MIR/FIR */
+#define PSC_SR_PARITY		0x20000000    /* parity error */
+#define PSC_SR_CRCERR		PSC_SR_PARITY /* CRC error */
+#define PSC_SR_OVERRUN		0x10000000    /* overrun error */
+#define PSC_SR_TXEMT		0x08000000    /* transmitter empty */
+#define PSC_SR_TXRDY		0x04000000    /* transmitter ready*/
+#define PSC_SR_FFULL		0x02000000    /* fifo full */
+#define PSC_SR_RXRDY		0x01000000    /* receiver ready */
+#define PSC_SR_DEOF		0x00800000    /* Detect EOF or RX-FIFO contain EOF */
+#define PSC_SR_ERR		0x00400000    /* Error Status including FIFO */
+
+/* equates for clock select reg. */
+#define PSC_CSRX16EXT_CLK	0x1110	/* x 16 ext_clock */
+#define PSC_CSRX1EXT_CLK	0x1111	/* x 1 ext_clock  */
+
+/* equates for command reg. A or B */
+#define PSC_CR_NO_COMMAND	0x00000000    /* no command */
+#define PSC_CR_RST_MR_PTR_CMD	0x10000000    /* reset mr pointer command */
+#define PSC_CR_RST_RX_CMD	0x20000000    /* reset receiver command */
+#define PSC_CR_RST_TX_CMD	0x30000000    /* reset transmitter command */
+#define PSC_CR_RST_ERR_STS_CMD	0x40000000    /* reset error status cmnd */
+#define PSC_CR_RST_BRK_INT_CMD	0x50000000    /* reset break int. command */
+#define PSC_CR_STR_BREAK_CMD	0x60000000    /* start break command */
+#define PSC_CR_STP_BREAK_CMD	0x70000000    /* stop break command */
+#define PSC_CR_RX_ENABLE	0x01000000    /* receiver enabled */
+#define PSC_CR_RX_DISABLE	0x02000000    /* receiver disabled */
+#define PSC_CR_TX_ENABLE	0x04000000    /* transmitter enabled */
+#define PSC_CR_TX_DISABLE	0x08000000    /* transmitter disabled */
+
+/* equates for input port change reg. */
+#define PSC_IPCR_SYNC		0x80000000    /* Sync Detect */
+#define PSC_IPCR_D_CTS		0x10000000    /* Delta CTS */
+#define PSC_IPCR_CTS		0x01000000    /* CTS - current state of PSC_CTS */
+
+/* equates for auxiliary control reg. (timer and counter clock selects) */
+#define PSC_ACR_BRG		0x80000000    /* for 68681 compatibility
+						 baud rate gen select
+						 0 = set 1; 1 = set 2
+						 equates are set 2 ONLY */
+#define PSC_ACR_TMR_EXT_CLK_16	0x70000000    /* xtnl clock divided by 16 */
+#define PSC_ACR_TMR_EXT_CLK	0x60000000    /* external clock */
+#define PSC_ACR_TMR_IP2_16	0x50000000    /* ip2 divided by 16 */
+#define PSC_ACR_TMR_IP2		0x40000000    /* ip2 */
+#define PSC_ACR_CTR_EXT_CLK_16	0x30000000    /* xtnl clock divided by 16 */
+#define PSC_ACR_CTR_TXCB	0x20000000    /* channel B xmitr clock */
+#define PSC_ACR_CTR_TXCA	0x10000000    /* channel A xmitr clock */
+#define PSC_ACR_CTR_IP2		0x00000000    /* ip2 */
+#define PSC_ACR_IEC0		0x01000000    /* interrupt enable ctrl for D_CTS */
+
+/* equates for int. status reg. */
+#define PSC_ISR_IPC		0x80000000    /* input port change*/
+#define PSC_ISR_BREAK		0x04000000    /* delta break */
+#define PSC_ISR_RX_RDY		0x02000000    /* receiver rdy /fifo full */
+#define PSC_ISR_TX_RDY		0x01000000    /* transmitter ready */
+#define PSC_ISR_DEOF		0x00800000    /* Detect EOF / RX-FIFO contains EOF */
+#define PSC_ISR_ERR		0x00400000    /* Error Status including FIFO */
+
+/* equates for int. mask reg. */
+#define PSC_IMR_CLEAR		0xff000000    /* Clear the imr */
+#define PSC_IMR_IPC		0x80000000    /* input port change*/
+#define PSC_IMR_BREAK		0x04000000    /* delta break */
+#define PSC_IMR_RX_RDY		0x02000000    /* rcvr ready / fifo full */
+#define PSC_IMR_TX_RDY		0x01000000    /* transmitter ready */
+#define PSC_IMR_DEOF		0x00800000    /* Detect EOF / RX-FIFO contains EOF */
+#define PSC_IMR_ERR		0x00400000    /* Error Status including FIFO */
+
+/* equates for input port reg. */
+#define PSC_IP_LPWRB		0x80000000    /* Low power mode in Ac97 */
+#define PSC_IP_TGL		0x40000000    /* test usage */
+#define PSC_IP_CTS		0x01000000    /* CTS */
+
+/* equates for output port bit set reg. */
+#define PSC_OPSET_RTS		0x01000000    /* Assert PSC_RTS output */
+
+/* equates for output port bit reset reg. */
+#define PSC_OPRESET_RTS		0x01000000    /* Assert PSC_RTS output */
+
+/* equates for rx FIFO number of data reg. */
+#define PSC_RFNUM(x)		((x&0xff)<<24)/* receive count */
+
+/* equates for tx FIFO number of data reg. */
+#define PSC_TFNUM(x)		((x&0xff)<<24)/* receive count */
+
+/* equates for rx FIFO status reg */
+#define PSC_RFSTAT_TAG(x)	((x&3)<<28)   /* tag */
+#define PSC_RFSTAT_FRAME0	0x08	      /* Frame Indicator 0 */
+#define PSC_RFSTAT_FRAME1	0x04	      /* Frame Indicator 1 */
+#define PSC_RFSTAT_FRAME2	0x02	      /* Frame Indicator 2 */
+#define PSC_RFSTAT_FRAME3	0x01	      /* Frame Indicator 3 */
+#define PSC_RFSTAT_FRAME(x)	((x&0x0f)<<24)/* Frame indicator */
+#define PSC_RFSTAT_ERR		0x00400000    /* Fifo err */
+#define PSC_RFSTAT_UF		0x00200000    /* Underflow */
+#define PSC_RFSTAT_OF		0x00100000    /* overflow */
+#define PSC_RFSTAT_FR		0x00080000    /* frame ready */
+#define PSC_RFSTAT_FULL		0x00040000    /* full */
+#define PSC_RFSTAT_ALARM	0x00020000    /* alarm */
+#define PSC_RFSTAT_EMPTY	0x00010000    /* empty */
+
+/* equates for tx FIFO status reg */
+#define PSC_TFSTAT_TAG(x)	((x&3)<<28)   /* tag */
+#define PSC_TFSTAT_FRAME0	0x08	      /* Frame Indicator 0 */
+#define PSC_TFSTAT_FRAME1	0x04	      /* Frame Indicator 1 */
+#define PSC_TFSTAT_FRAME2	0x02	      /* Frame Indicator 2 */
+#define PSC_TFSTAT_FRAME3	0x01	      /* Frame Indicator 3 */
+#define PSC_TFSTAT_FRAME(x)	((x&0x0f)<<24)/* Frame indicator */
+#define PSC_TFSTAT_ERR		0x00400000    /* Fifo err */
+#define PSC_TFSTAT_UF		0x00200000    /* Underflow */
+#define PSC_TFSTAT_OF		0x00100000    /* overflow */
+#define PSC_TFSTAT_FR		0x00080000    /* frame ready */
+#define PSC_TFSTAT_FULL		0x00040000    /* full */
+#define PSC_TFSTAT_ALARM	0x00020000    /* alarm */
+#define PSC_TFSTAT_EMPTY	0x00010000    /* empty */
+
+/* equates for rx FIFO control reg. */
+#define PSC_RFCNTL_WTAG(x)	((x&3)<<29)   /* Write tag */
+#define PSC_RFCNTL_FRAME	0x08000000    /* Frame mode enable */
+#define PSC_RFCNTL_GR(x)	((x&7)<<24)   /* Granularity */
+
+/* equates for tx FIFO control reg. */
+#define PSC_TFCNTL_WTAG(x)	((x&3)<<29)   /* Write tag */
+#define PSC_TFCNTL_FRAME	0x08000000    /* Frame mode enable */
+#define PSC_TFCNTL_GR(x)	((x&7)<<24)   /* Granularity */
+
+/* equates for rx FIFO alarm reg */
+#define PSC_RFALARM(x)		(x&0x1ff)     /* Alarm */
+
+/* equates for tx FIFO alarm reg */
+#define PSC_TFALARM(x)		(x&0x1ff)     /* Alarm */
+
+/* equates for rx FIFO read pointer */
+#define PSC_RFRPTR(x)		(x&0x1ff)     /* read pointer */
+
+/* equates for tx FIFO read pointer */
+#define PSC_TFRPTR(x)		(x&0x1ff)     /* read pointer */
+
+/* equates for rx FIFO write pointer */
+#define PSC_RFWPTR(x)		(x&0x1ff)     /* write pointer */
+
+/* equates for rx FIFO write pointer */
+#define PSC_TFWPTR(x)		(x&0x1ff)     /* write pointer */
+
+/* equates for rx FIFO last read frame pointer reg */
+#define PSC_RFLRFPTR(x)		(x&0x1ff)     /* last read frame pointer */
+
+/* equates for tx FIFO last read frame pointer reg */
+#define PSC_TFLRFPTR(x)		(x&0x1ff)     /* last read frame pointer */
+
+/* equates for rx FIFO last write frame pointer reg */
+#define PSC_RFLWFPTR(x)		(x&0x1ff)     /* last write frame pointer */
+
+/* equates for tx FIFO last write frame pointer reg */
+#define PSC_TFLWFPTR(x)		(x&0x1ff)     /* last write frame pointer */
+
+/* PCI configuration (only for PLL determination)*/
+#define PCI_REG_PCIGSCR		(MMAP_XCPCI + 0x60) /* Global status/control register */
+#define PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK	0x07000000
+#define PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT		24
+
+#define PCI_REG_PCICAR		(MMAP_XCPCI + 0xF8) /* Configuration Address Register */
+
+/* ------------------------------------------------------------------------ */
+/*
+ * Macro for General Purpose Timer
+ */
+/* Enable and Mode Select */
+#define GPT_OCT(x)	    (x & 0x3)<<4/* Output Compare Type */
+#define GPT_ICT(x)	    (x & 0x3)	/* Input Capture Type */
+#define GPT_CTRL_WDEN	    0x80	/* Watchdog Enable */
+#define GPT_CTRL_CE	    0x10	/* Counter Enable */
+#define GPT_CTRL_STPCNT	    0x04	/* Stop continous */
+#define GPT_CTRL_ODRAIN	    0x02	/* Open Drain */
+#define GPT_CTRL_INTEN	    0x01	/* Interrupt Enable */
+#define GPT_MODE_GPIO(x)    (x & 0x3)<<4/* Gpio Mode Type */
+#define GPT_TMS_ICT	    0x01	/* Input Capture Enable */
+#define GPT_TMS_OCT	    0x02	/* Output Capture Enable */
+#define GPT_TMS_PWM	    0x03	/* PWM Capture Enable */
+#define GPT_TMS_SGPIO	    0x04	/* PWM Capture Enable */
+
+#define GPT_PWM_WIDTH(x)    (x & 0xffff)
+
+/* Status */
+#define GPT_STA_CAPTURE(x)  (x & 0xffff)/* Read of internal counter */
+
+#define GPT_OVFPIN_OVF(x)   (x & 0x70)	/* Internal counter roll over */
+#define GPT_OVFPIN_PIN	    0x01	/* Input pin - Timer 0 and 1 */
+
+#define GPT_INT_TEXP	    0x08	/* Timer Expired in Internal Timer mode */
+#define GPT_INT_PWMP	    0x04	/* PWM end of period occurred */
+#define GPT_INT_COMP	    0x02	/* OC reference event occurred */
+#define GPT_INT_CAPT	    0x01	/* IC reference event occurred */
+
+/* ------------------------------------------------------------------------ */
+/*
+ * Port configuration
+ */
+#define CFG_FEC1_PORT0_CONFIG	0x00000000
+#define CFG_FEC1_PORT1_CONFIG	0x00000000
+#define CFG_1284_PORT0_CONFIG  0x00000000
+#define CFG_1284_PORT1_CONFIG  0x00000000
+#define CFG_FEC2_PORT2_CONFIG	0x00000000
+#define CFG_PEV_PORT2_CONFIG   0x00000000
+#define CFG_GP0_PORT0_CONFIG   0x00000000
+#define CFG_GP1_PORT2_CONFIG   0xaaaaaac0
+#define CFG_PSC_PORT3_CONFIG   0x00020000
+#define CFG_CS1_PORT3_CONFIG   0x00000000
+#define CFG_CS2_PORT3_CONFIG	0x10000000
+#define CFG_CS3_PORT3_CONFIG	0x40000000
+#define CFG_CS4_PORT3_CONFIG	0x00000400
+#define CFG_CS5_PORT3_CONFIG	0x00000200
+#define CFG_PCI_PORT3_CONFIG   0x01400180
+#define CFG_I2C_PORT3_CONFIG   0x00000000
+#define CFG_GP2_PORT3_CONFIG   0x000200a0
+
+/* ------------------------------------------------------------------------ */
+/*
+ * DRAM configuration
+ */
+
+/* Field definitions for the control register */
+#define CTL_MODE_ENABLE_SHIFT	    31
+#define CTL_CKE_SHIFT		    30
+#define CTL_DDR_SHIFT		    29
+#define CTL_REFRESH_SHIFT	    28
+#define CTL_ADDRMUX_SHIFT	    24
+#define CTL_PRECHARGE_SHIFT	    23
+#define CTL_DRIVE_RULE_SHIFT	    22
+#define CTL_REFRESH_INTERVAL_SHIFT  16
+#define CTL_DQSOEN_SHIFT	    8
+#define CTL_BUFFERED_SHIFT	    4
+#define CTL_REFRESH_CMD_SHIFT	    2
+#define CTL_PRECHARGE_CMD_SHIFT	    1
+
+#define CTL_MODE_ENABLE		    (1<<CTL_MODE_ENABLE_SHIFT)
+#define CTL_CKE_HIGH		    (1<<CTL_CKE_SHIFT)
+#define CTL_DDR_MODE		    (1<<CTL_DDR_SHIFT)
+#define CTL_REFRESH_ENABLE	    (1<<CTL_REFRESH_SHIFT)
+#define CTL_ADDRMUX(value)	    ((value)<<CTL_ADDRMUX_SHIFT)
+#define CTL_A8PRECHARGE		    (1<<CTL_PRECHARGE_SHIFT)
+#define CTL_REFRESH_INTERVAL(value) ((value)<<CTL_REFRESH_INTERVAL_SHIFT)
+#define CTL_DQSOEN(value)	    ((value)<<CTL_DQSOEN_SHIFT)
+#define CTL_BUFFERED		    (1<<CTL_BUFFERED_SHIFT)
+#define CTL_REFRESH_CMD		    (1<<CTL_REFRESH_CMD_SHIFT)
+#define CTL_PRECHARGE_CMD	    (1<<CTL_PRECHARGE_CMD_SHIFT)
+
+/* Field definitions for config register 1 */
+
+#define CFG1_SRD2RWP_SHIFT	    28
+#define CFG1_SWT2RWP_SHIFT	    24
+#define CFG1_RLATENCY_SHIFT	    20
+#define CFG1_ACT2WR_SHIFT	    16
+#define CFG1_PRE2ACT_SHIFT	    12
+#define CFG1_REF2ACT_SHIFT	    8
+#define CFG1_WLATENCY_SHIFT	    4
+
+#define CFG1_SRD2RWP(value)	    ((value)<<CFG1_SRD2RWP_SHIFT)
+#define CFG1_SWT2RWP(value)	    ((value)<<CFG1_SWT2RWP_SHIFT)
+#define CFG1_RLATENCY(value)	    ((value)<<CFG1_RLATENCY_SHIFT)
+#define CFG1_ACT2WR(value)	    ((value)<<CFG1_ACT2WR_SHIFT)
+#define CFG1_PRE2ACT(value)	    ((value)<<CFG1_PRE2ACT_SHIFT)
+#define CFG1_REF2ACT(value)	    ((value)<<CFG1_REF2ACT_SHIFT)
+#define CFG1_WLATENCY(value)	    ((value)<<CFG1_WLATENCY_SHIFT)
+
+/* Field definitions for config register 2 */
+#define CFG2_BRD2RP_SHIFT	    28
+#define CFG2_BWT2RWP_SHIFT	    24
+#define CFG2_BRD2WT_SHIFT	    20
+#define CFG2_BURSTLEN_SHIFT	    16
+
+#define CFG2_BRD2RP(value)	    ((value)<<CFG2_BRD2RP_SHIFT)
+#define CFG2_BWT2RWP(value)	    ((value)<<CFG2_BWT2RWP_SHIFT)
+#define CFG2_BRD2WT(value)	    ((value)<<CFG2_BRD2WT_SHIFT)
+#define CFG2_BURSTLEN(value)	    ((value)<<CFG2_BURSTLEN_SHIFT)
+
+/* Field definitions for the mode/extended mode register - mode
+ * register access
+ */
+#define MODE_REG_SHIFT		    30
+#define MODE_OPMODE_SHIFT	    25
+#define MODE_CL_SHIFT		    22
+#define MODE_BT_SHIFT		    21
+#define MODE_BURSTLEN_SHIFT	    18
+#define MODE_CMD_SHIFT		    16
+
+#define MODE_MODE		    0
+#define MODE_OPMODE(value)	    ((value)<<MODE_OPMODE_SHIFT)
+#define MODE_CL(value)		    ((value)<<MODE_CL_SHIFT)
+#define MODE_BT_INTERLEAVED	    (1<<MODE_BT_SHIFT)
+#define MODE_BT_SEQUENTIAL	    (0<<MODE_BT_SHIFT)
+#define MODE_BURSTLEN(value)	    ((value)<<MODE_BURSTLEN_SHIFT)
+#define MODE_CMD		    (1<<MODE_CMD_SHIFT)
+
+#define MODE_BURSTLEN_8		    3
+#define MODE_BURSTLEN_4		    2
+#define MODE_BURSTLEN_2		    1
+
+#define MODE_CL_2		    2
+#define MODE_CL_2p5		    6
+#define MODE_OPMODE_NORMAL	    0
+#define MODE_OPMODE_RESETDLL	    2
+
+
+/* Field definitions for the mode/extended mode register - extended
+ * mode register access
+ */
+#define MODE_X_DLL_SHIFT	    18 /* DLL enable/disable */
+#define MODE_X_DS_SHIFT		    19 /* Drive strength normal/reduced */
+#define MODE_X_QFC_SHIFT	    20 /* QFC function (whatever that is) */
+#define MODE_X_OPMODE_SHIFT	    21
+
+#define MODE_EXTENDED		    (1<<MODE_REG_SHIFT)
+#define MODE_X_DLL_ENABLE	    0
+#define MODE_X_DLL_DISABLE	    (1<<MODE_X_DLL_SHIFT)
+#define MODE_X_DS_NORMAL	    0
+#define MODE_X_DS_REDUCED	    (1<<MODE_X_DS_SHIFT)
+#define MODE_X_QFC_DISABLED	    0
+#define MODE_X_OPMODE(value)	    ((value)<<MODE_X_OPMODE_SHIFT)
+
+#ifndef __ASSEMBLY__
+/*
+ * DMA control/status registers.
+ */
+struct mpc8220_dma {
+    u32 taskBar;	/* DMA + 0x00 */
+    u32 currentPointer; /* DMA + 0x04 */
+    u32 endPointer;	/* DMA + 0x08 */
+    u32 variablePointer;/* DMA + 0x0c */
+
+    u8 IntVect1;	/* DMA + 0x10 */
+    u8 IntVect2;	/* DMA + 0x11 */
+    u16 PtdCntrl;	/* DMA + 0x12 */
+
+    u32 IntPend;	/* DMA + 0x14 */
+    u32 IntMask;	/* DMA + 0x18 */
+
+    u16 tcr_0;		/* DMA + 0x1c */
+    u16 tcr_1;		/* DMA + 0x1e */
+    u16 tcr_2;		/* DMA + 0x20 */
+    u16 tcr_3;		/* DMA + 0x22 */
+    u16 tcr_4;		/* DMA + 0x24 */
+    u16 tcr_5;		/* DMA + 0x26 */
+    u16 tcr_6;		/* DMA + 0x28 */
+    u16 tcr_7;		/* DMA + 0x2a */
+    u16 tcr_8;		/* DMA + 0x2c */
+    u16 tcr_9;		/* DMA + 0x2e */
+    u16 tcr_a;		/* DMA + 0x30 */
+    u16 tcr_b;		/* DMA + 0x32 */
+    u16 tcr_c;		/* DMA + 0x34 */
+    u16 tcr_d;		/* DMA + 0x36 */
+    u16 tcr_e;		/* DMA + 0x38 */
+    u16 tcr_f;		/* DMA + 0x3a */
+
+    u8 IPR0;		/* DMA + 0x3c */
+    u8 IPR1;		/* DMA + 0x3d */
+    u8 IPR2;		/* DMA + 0x3e */
+    u8 IPR3;		/* DMA + 0x3f */
+    u8 IPR4;		/* DMA + 0x40 */
+    u8 IPR5;		/* DMA + 0x41 */
+    u8 IPR6;		/* DMA + 0x42 */
+    u8 IPR7;		/* DMA + 0x43 */
+    u8 IPR8;		/* DMA + 0x44 */
+    u8 IPR9;		/* DMA + 0x45 */
+    u8 IPR10;		/* DMA + 0x46 */
+    u8 IPR11;		/* DMA + 0x47 */
+    u8 IPR12;		/* DMA + 0x48 */
+    u8 IPR13;		/* DMA + 0x49 */
+    u8 IPR14;		/* DMA + 0x4a */
+    u8 IPR15;		/* DMA + 0x4b */
+    u8 IPR16;		/* DMA + 0x4c */
+    u8 IPR17;		/* DMA + 0x4d */
+    u8 IPR18;		/* DMA + 0x4e */
+    u8 IPR19;		/* DMA + 0x4f */
+    u8 IPR20;		/* DMA + 0x50 */
+    u8 IPR21;		/* DMA + 0x51 */
+    u8 IPR22;		/* DMA + 0x52 */
+    u8 IPR23;		/* DMA + 0x53 */
+    u8 IPR24;		/* DMA + 0x54 */
+    u8 IPR25;		/* DMA + 0x55 */
+    u8 IPR26;		/* DMA + 0x56 */
+    u8 IPR27;		/* DMA + 0x57 */
+    u8 IPR28;		/* DMA + 0x58 */
+    u8 IPR29;		/* DMA + 0x59 */
+    u8 IPR30;		/* DMA + 0x5a */
+    u8 IPR31;		/* DMA + 0x5b */
+
+    u32 res1;		/* DMA + 0x5c */
+    u32 res2;		/* DMA + 0x60 */
+    u32 res3;		/* DMA + 0x64 */
+    u32 MDEDebug;	/* DMA + 0x68 */
+    u32 ADSDebug;	/* DMA + 0x6c */
+    u32 Value1;		/* DMA + 0x70 */
+    u32 Value2;		/* DMA + 0x74 */
+    u32 Control;	/* DMA + 0x78 */
+    u32 Status;		/* DMA + 0x7c */
+    u32 EU00;		/* DMA + 0x80 */
+    u32 EU01;		/* DMA + 0x84 */
+    u32 EU02;		/* DMA + 0x88 */
+    u32 EU03;		/* DMA + 0x8c */
+    u32 EU04;		/* DMA + 0x90 */
+    u32 EU05;		/* DMA + 0x94 */
+    u32 EU06;		/* DMA + 0x98 */
+    u32 EU07;		/* DMA + 0x9c */
+    u32 EU10;		/* DMA + 0xa0 */
+    u32 EU11;		/* DMA + 0xa4 */
+    u32 EU12;		/* DMA + 0xa8 */
+    u32 EU13;		/* DMA + 0xac */
+    u32 EU14;		/* DMA + 0xb0 */
+    u32 EU15;		/* DMA + 0xb4 */
+    u32 EU16;		/* DMA + 0xb8 */
+    u32 EU17;		/* DMA + 0xbc */
+    u32 EU20;		/* DMA + 0xc0 */
+    u32 EU21;		/* DMA + 0xc4 */
+    u32 EU22;		/* DMA + 0xc8 */
+    u32 EU23;		/* DMA + 0xcc */
+    u32 EU24;		/* DMA + 0xd0 */
+    u32 EU25;		/* DMA + 0xd4 */
+    u32 EU26;		/* DMA + 0xd8 */
+    u32 EU27;		/* DMA + 0xdc */
+    u32 EU30;		/* DMA + 0xe0 */
+    u32 EU31;		/* DMA + 0xe4 */
+    u32 EU32;		/* DMA + 0xe8 */
+    u32 EU33;		/* DMA + 0xec */
+    u32 EU34;		/* DMA + 0xf0 */
+    u32 EU35;		/* DMA + 0xf4 */
+    u32 EU36;		/* DMA + 0xf8 */
+    u32 EU37;		/* DMA + 0xfc */
+};
+
+/*
+ * PCI Header Registers
+ */
+typedef struct mpc8220_xcpci {
+	u32	dev_ven_id;		/* 0xb00 - device/vendor ID */
+	u32	stat_cmd_reg;		/* 0xb04 - status command register */
+	u32	class_code_rev_id;	/* 0xb08 - class code / revision ID */
+	u32	bist_htyp_lat_cshl;	/* 0xb0c - BIST/HeaderType/Latency/cache line */
+	u32	base0;			/* 0xb10 - base address 0 */
+	u32	base1;			/* 0xb14 - base address 1 */
+	u32	reserved1[4];		/* 0xb18->0xd27 - base address 2 - 5 */
+	u32	cis;			/* 0xb28 - cardBus CIS pointer */
+	u32	sub_sys_ven_id;		/* 0xb2c - sub system ID/ subsystem vendor ID */
+	u32	reserved2;		/* 0xb30 - expansion ROM base address */
+	u32	reserved3;		/* 0xb00 - reserved */
+	u32	reserved4;		/* 0xb00 - reserved */
+	u32	mlat_mgnt_ipl;		/* 0xb3c - MaxLat/MinGnt/ int pin/int line */
+	u32	reserved5[8];
+	/* MPC8220 specific - not accessible in PCI header space externally */
+	u32	glb_stat_ctl;		/* 0xb60 - Global Status Control */
+	u32	target_bar0;		/* 0xb64 - Target Base Address 0 */
+	u32	target_bar1;		/* 0xb68 - Target Base Address 1 */
+	u32	target_ctrl;		/* 0xb6c - Target Control */
+	u32	init_win0;		/* 0xb70 - Initiator Window 0 Base/Translation */
+	u32	init_win1;		/* 0xb74 - Initiator Window 1 Base/Translation */
+	u32	init_win2;		/* 0xb78 - Initiator Window 2 Base/Translation */
+	u32	reserved6;		/* 0xb7c - reserved  */
+	u32	init_win_cfg;		/* 0xb80 */
+	u32	init_ctrl;		/* 0xb84 */
+	u32	init_stat;		/* 0xb88 */
+	u32	reserved7[27];
+	u32	cfg_adr;		/* 0xbf8 */
+	u32	reserved8;
+} mpc8220_xcpci_t;
+
+/* PCI->XLB space translation (MPC8220 target), reg0 can address max 256MB,
+   reg1 - 1GB */
+#define PCI_BASE_ADDR_REG0			0x40000000
+#define PCI_BASE_ADDR_REG1			(CFG_SDRAM_BASE)
+#define PCI_TARGET_BASE_ADDR_REG0		(CFG_MBAR)
+#define PCI_TARGET_BASE_ADDR_REG1		(CFG_SDRAM_BASE)
+#define PCI_TARGET_BASE_ADDR_EN			1<<0
+
+
+/* PCI Global Status/Control Register (PCIGSCR) */
+#define PCI_GLB_STAT_CTRL_PE_SHIFT		29
+#define PCI_GLB_STAT_CTRL_SE_SHIFT		28
+#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_SHIFT	24
+#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_MASK	0x7
+#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_SHIFT	16
+#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_MASK	0x7
+#define PCI_GLB_STAT_CTRL_PEE_SHIFT		13
+#define PCI_GLB_STAT_CTRL_SEE_SHIFT		12
+#define PCI_GLB_STAT_CTRL_PR_SHIFT		0
+
+#define PCI_GLB_STAT_CTRL_PE			(1<<PCI_GLB_STAT_CTRL_PE_SHIFT)
+#define PCI_GLB_STAT_CTRL_SE			(1<<PCI_GLB_STAT_CTRL_SE_SHIFT)
+#define PCI_GLB_STAT_CTRL_PEE			(1<<PCI_GLB_STAT_CTRL_PEE_SHIFT)
+#define PCI_GLB_STAT_CTRL_SEE			(1<<PCI_GLB_STAT_CTRL_SEE_SHIFT)
+#define PCI_GLB_STAT_CTRL_PR			(1<<PCI_GLB_STAT_CTRL_PR_SHIFT)
+
+/* PCI Target Control Register (PCITCR) */
+#define PCI_TARGET_CTRL_LD_SHIFT		24
+#define PCI_TARGET_CTRL_P_SHIFT			16
+
+#define PCI_TARGET_CTRL_LD			(1<<PCI_TARGET_CTRL_LD_SHIFT)
+#define PCI_TARGET_CTRL_P			(1<<PCI_TARGET_CTRL_P_SHIFT)
+
+/* PCI Initiator Window Configuration Register (PCIIWCR) */
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT	27
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_SHIFT	25
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_MASK	0x3
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT	24
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT	19
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_SHIFT	17
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_MASK	0x3
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT	16
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT	11
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_SHIFT	9
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_MASK	0x3
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT	8
+
+#define PCI_INIT_WIN_CFG_WIN_MEM_READ		0x0
+#define PCI_INIT_WIN_CFG_WIN_MEM_READ_LINE	0x1
+#define PCI_INIT_WIN_CFG_WIN_MEM_READ_MULTIPLE	0x2
+
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO		(1<<PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT)
+#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN		(1<<PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT)
+
+/* PCI Initiator Control Register (PCIICR) */
+#define PCI_INIT_CTRL_REE_SHIFT			26
+#define PCI_INIT_CTRL_IAE_SHIFT			25
+#define PCI_INIT_CTRL_TAE_SHIFT			24
+#define PCI_INIT_CTRL_MAX_RETRIES_SHIFT		0
+#define PCI_INIT_CTRL_MAX_RETRIES_MASK		0xff
+
+#define PCI_INIT_CTRL_REE			(1<<PCI_INIT_CTRL_REE_SHIFT)
+#define PCI_INIT_CTRL_IAE			(1<<PCI_INIT_CTRL_IAE_SHIFT)
+#define PCI_INIT_CTRL_TAE			(1<<PCI_INIT_CTRL_TAE_SHIFT)
+
+/* PCI Status/Command Register (PCISCR) - PCI Dword 1 */
+#define PCI_STAT_CMD_PE_SHIFT			31
+#define PCI_STAT_CMD_SE_SHIFT			30
+#define PCI_STAT_CMD_MA_SHIFT			29
+#define PCI_STAT_CMD_TR_SHIFT			28
+#define PCI_STAT_CMD_TS_SHIFT			27
+#define PCI_STAT_CMD_DT_SHIFT			25
+#define PCI_STAT_CMD_DT_MASK			0x3
+#define PCI_STAT_CMD_DP_SHIFT			24
+#define PCI_STAT_CMD_FC_SHIFT			23
+#define PCI_STAT_CMD_R_SHIFT			22
+#define PCI_STAT_CMD_66M_SHIFT			21
+#define PCI_STAT_CMD_C_SHIFT			20
+#define PCI_STAT_CMD_F_SHIFT			9
+#define PCI_STAT_CMD_S_SHIFT			8
+#define PCI_STAT_CMD_ST_SHIFT			7
+#define PCI_STAT_CMD_PER_SHIFT			6
+#define PCI_STAT_CMD_V_SHIFT			5
+#define PCI_STAT_CMD_MW_SHIFT			4
+#define PCI_STAT_CMD_SP_SHIFT			3
+#define PCI_STAT_CMD_B_SHIFT			2
+#define PCI_STAT_CMD_M_SHIFT			1
+#define PCI_STAT_CMD_IO_SHIFT			0
+
+#define PCI_STAT_CMD_PE			(1<<PCI_STAT_CMD_PE_SHIFT)
+#define PCI_STAT_CMD_SE			(1<<PCI_STAT_CMD_SE_SHIFT)
+#define PCI_STAT_CMD_MA			(1<<PCI_STAT_CMD_MA_SHIFT)
+#define PCI_STAT_CMD_TR			(1<<PCI_STAT_CMD_TR_SHIFT)
+#define PCI_STAT_CMD_TS			(1<<PCI_STAT_CMD_TS_SHIFT)
+#define PCI_STAT_CMD_DP			(1<<PCI_STAT_CMD_DP_SHIFT)
+#define PCI_STAT_CMD_FC			(1<<PCI_STAT_CMD_FC_SHIFT)
+#define PCI_STAT_CMD_R				(1<<PCI_STAT_CMD_R_SHIFT)
+#define PCI_STAT_CMD_66M			(1<<PCI_STAT_CMD_66M_SHIFT)
+#define PCI_STAT_CMD_C				(1<<PCI_STAT_CMD_C_SHIFT)
+#define PCI_STAT_CMD_F				(1<<PCI_STAT_CMD_F_SHIFT)
+#define PCI_STAT_CMD_S				(1<<PCI_STAT_CMD_S_SHIFT)
+#define PCI_STAT_CMD_ST			(1<<PCI_STAT_CMD_ST_SHIFT)
+#define PCI_STAT_CMD_PER			(1<<PCI_STAT_CMD_PER_SHIFT)
+#define PCI_STAT_CMD_V				(1<<PCI_STAT_CMD_V_SHIFT)
+#define PCI_STAT_CMD_MW			(1<<PCI_STAT_CMD_MW_SHIFT)
+#define PCI_STAT_CMD_SP			(1<<PCI_STAT_CMD_SP_SHIFT)
+#define PCI_STAT_CMD_B				(1<<PCI_STAT_CMD_B_SHIFT)
+#define PCI_STAT_CMD_M				(1<<PCI_STAT_CMD_M_SHIFT)
+#define PCI_STAT_CMD_IO			(1<<PCI_STAT_CMD_IO_SHIFT)
+
+/* PCI Configuration 1 Register (PCICR1) - PCI Dword 3 */
+#define PCI_CFG1_HT_SHIFT			16
+#define PCI_CFG1_HT_MASK			0xff
+#define PCI_CFG1_LT_SHIFT			8
+#define PCI_CFG1_LT_MASK			0xff
+#define PCI_CFG1_CLS_SHIFT			0
+#define PCI_CFG1_CLS_MASK			0xf
+
+/* function prototypes */
+void loadtask(int basetask, int tasks);
+u32 dramSetup(void);
+
+#if defined(CONFIG_PSC_CONSOLE)
+int psc_serial_init (void);
+void psc_serial_putc(const char c);
+void psc_serial_puts (const char *s);
+int psc_serial_getc(void);
+int psc_serial_tstc(void);
+void psc_serial_setbrg(void);
+#endif
+
+#if defined (CONFIG_EXTUART_CONSOLE)
+int ext_serial_init (void);
+void ext_serial_putc(const char c);
+void ext_serial_puts (const char *s);
+int ext_serial_getc(void);
+int ext_serial_tstc(void);
+void ext_serial_setbrg(void);
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __MPC8220_H__ */
diff --git a/include/mpc824x.h b/include/mpc824x.h
new file mode 100755
index 0000000..30fc795
--- /dev/null
+++ b/include/mpc824x.h
@@ -0,0 +1,576 @@
+/*
+ * Copyright Rob Taylor, Flying Pig Systems Ltd. 2000.
+ * Copyright (C) 2001, James Dougherty, jfd@cs.stanford.edu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MPC824X_H__
+#define __MPC824X_H__
+
+#include <config.h>
+
+/* CPU Types */
+#define CPU_TYPE_601		0x01		/* PPC 601	 CPU */
+#define CPU_TYPE_602		0x02		/* PPC 602	 CPU */
+#define CPU_TYPE_603		0x03		/* PPC 603	 CPU */
+#define CPU_TYPE_603E		0x06		/* PPC 603e	 CPU */
+#define CPU_TYPE_603P		0x07		/* PPC 603p	 CPU */
+#define CPU_TYPE_604		0x04		/* PPC 604	 CPU */
+#define CPU_TYPE_604E		0x09		/* PPC 604e	 CPU */
+#define CPU_TYPE_604R		0x0a		/* PPC 604r	 CPU */
+#define CPU_TYPE_750		0x08		/* PPC 750	 CPU */
+#define CPU_TYPE_8240		0x81		/* PPC 8240	 CPU */
+#define CPU_TYPE_8245		0x8081		/* PPC 8245/8241 CPU */
+#define _CACHE_ALIGN_SIZE	32		/* cache line size */
+
+/* spr976 - DMISS data tlb miss address register
+ * spr977 - DCMP data tlb miss compare register
+ * spr978 - HASH1 PTEG1 address register
+ * spr980 - HASH2 PTEG2 address register
+ * IMISS  - instruction tlb miss address register
+ * ICMP	  - instruction TLB mis compare register
+ * RPA	  - real page address register
+ * HID0	  - hardware implemntation register
+ * HID2	  - instruction address breakpoint register
+ */
+
+/* Kahlua/MPC8240 defines */
+#define VEN_DEV_ID		0x00021057	/* Vendor and Dev. ID for MPC106 */
+#define KAHLUA_ID		0x00031057	/* Vendor & Dev Id for Kahlua's PCI */
+#define KAHLUA2_ID	        0x00061057      /* 8245 is aka Kahlua-2 */
+#define BMC_BASE		0x80000000	/* Kahlua ID in PCI Memory space */
+#define CHRP_REG_ADDR		0xfec00000	/* MPC107 Config, Map B */
+#define CHRP_REG_DATA		0xfee00000	/* MPC107 Config, Map B */
+#define CHRP_ISA_MEM_PHYS	0xfd000000
+#define CHRP_ISA_MEM_BUS	0x00000000
+#define CHRP_ISA_MEM_SIZE	0x01000000
+#define CHRP_ISA_IO_PHYS	0xfe000000
+#define CHRP_ISA_IO_BUS		0x00000000
+#define CHRP_ISA_IO_SIZE	0x00800000
+#define CHRP_PCI_IO_PHYS	0xfe800000
+#define CHRP_PCI_IO_BUS		0x00800000
+#define CHRP_PCI_IO_SIZE	0x00400000
+#define CHRP_PCI_MEM_PHYS	0x80000000
+#define CHRP_PCI_MEM_BUS	0x80000000
+#define CHRP_PCI_MEM_SIZE	0x7d000000
+#define	CHRP_PCI_MEMORY_PHYS	0x00000000
+#define	CHRP_PCI_MEMORY_BUS	0x00000000
+#define CHRP_PCI_MEMORY_SIZE	0x40000000
+#define PREP_REG_ADDR		0x80000cf8	/* MPC107 Config, Map A */
+#define PREP_REG_DATA		0x80000cfc	/* MPC107 Config, Map A */
+#define PREP_ISA_IO_PHYS	0x80000000
+#define PREP_ISA_IO_BUS		0x00000000
+#define PREP_ISA_IO_SIZE	0x00800000
+#define PREP_PCI_IO_PHYS	0x81000000
+#define PREP_PCI_IO_BUS		0x01000000
+#define PREP_PCI_IO_SIZE	0x3e800000
+#define PREP_PCI_MEM_PHYS	0xc0000000
+#define PREP_PCI_MEM_BUS	0x00000000
+#define PREP_PCI_MEM_SIZE	0x3f000000
+#define	PREP_PCI_MEMORY_PHYS	0x00000000
+#define	PREP_PCI_MEMORY_BUS	0x80000000
+#define	PREP_PCI_MEMORY_SIZE	0x80000000
+#define MPC107_PCI_CMD		0x80000004	/* MPC107 PCI cmd reg */
+#define MPC107_PCI_STAT 	0x80000006	/* MPC107 PCI status reg */
+#define PROC_INT1_ADR		0x800000a8	/* MPC107 Processor i/f cfg1 */
+#define PROC_INT2_ADR		0x800000ac	/* MPC107 Processor i/f cfg2 */
+#define MEM_CONT1_ADR		0x800000f0	/* MPC107 Memory control config. 1 */
+#define MEM_CONT2_ADR		0x800000f4	/* MPC107 Memory control config. 2 */
+#define MEM_CONT3_ADR		0x800000f8	/* MPC107 Memory control config. 3 */
+#define MEM_CONT4_ADR		0x800000fc	/* MPC107 Memory control config. 4 */
+#define MEM_ERREN1_ADR		0x800000c0	/* MPC107 Memory error enable 1 */
+#define MEM_START1_ADR		0x80000080	/* MPC107 Memory starting addr */
+#define MEM_START2_ADR		0x80000084	/* MPC107 Memory starting addr-lo */
+#define XMEM_START1_ADR 	0x80000088	/* MPC107 Extended mem. start addr-hi*/
+#define XMEM_START2_ADR 	0x8000008c	/* MPC107 Extended mem. start addr-lo*/
+#define MEM_END1_ADR		0x80000090	/* MPC107 Memory ending address */
+#define MEM_END2_ADR		0x80000094	/* MPC107 Memory ending addr-lo */
+#define XMEM_END1_ADR		0x80000098	/* MPC107 Extended mem. end addrs-hi */
+#define XMEM_END2_ADR		0x8000009c	/* MPC107 Extended mem. end addrs-lo*/
+#define OUT_DRV_CONT		0x80000073	/* MPC107 Output Driver Control reg */
+#define MEM_EN_ADR		0x800000a0	/* Memory bank enable */
+#define PAGE_MODE		0x800000a3	/* MPC107 Page Mode Counter/Timer */
+
+/*-----------------------------------------------------------------------
+ * Exception offsets (PowerPC standard)
+ */
+#define EXC_OFF_RESERVED0	0x0000	/* Reserved */
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset */
+#define EXC_OFF_MACH_CHCK	0x0200	/* Machine Check */
+#define EXC_OFF_DATA_STOR	0x0300	/* Data Storage */
+#define EXC_OFF_INS_STOR	0x0400	/* Instruction Storage */
+#define EXC_OFF_EXTERNAL	0x0500	/* External */
+#define EXC_OFF_ALIGN		0x0600	/* Alignment */
+#define EXC_OFF_PROGRAM		0x0700	/* Program */
+#define EXC_OFF_FPUNAVAIL	0x0800	/* Floating-point Unavailable */
+#define EXC_OFF_DECR		0x0900	/* Decrementer */
+#define EXC_OFF_RESERVED1	0x0A00	/* Reserved */
+#define EXC_OFF_RESERVED2	0x0B00	/* Reserved */
+#define EXC_OFF_SYS_CALL	0x0C00	/* System Call */
+#define EXC_OFF_TRACE		0x0D00	/* Trace */
+#define EXC_OFF_FPUNASSIST	0x0E00	/* Floating-point Assist */
+
+	/* 0x0E10 - 0x0FFF are marked reserved in The PowerPC Architecture book */
+	/* these found in DINK code  - may not apply to 8240*/
+#define EXC_OFF_PMI		0x0F00	/* Performance Monitoring Interrupt */
+#define EXC_OFF_VMXUI		0x0F20	/* VMX (AltiVec) Unavailable Interrupt */
+
+	/* 0x1000 - 0x2FFF are implementation specific */
+	/* these found in DINK code  - may not apply to 8240 */
+#define EXC_OFF_ITME		0x1000	/* Instruction Translation Miss Exception */
+#define EXC_OFF_DLTME		0x1100	/* Data Load Translation Miss Exception */
+#define EXC_OFF_DSTME		0x1200	/* Data Store Translation Miss Exception */
+#define EXC_OFF_IABE		0x1300	/* Instruction Addr Breakpoint Exception */
+#define EXC_OFF_SMIE		0x1400	/* System Management Interrupt Exception */
+#define EXC_OFF_JMDDI		0x1600	/* Java Mode denorm detect Interr -- WTF??*/
+#define EXC_OFF_RMTE		0x2000	/* Run Mode or Trace Exception */
+
+#define MAP_A_CONFIG_ADDR_HIGH	0x8000	/* Upper half of CONFIG_ADDR for Map A */
+#define MAP_A_CONFIG_ADDR_LOW	0x0CF8	/* Lower half of CONFIG_ADDR for Map A */
+#define MAP_A_CONFIG_DATA_HIGH	0x8000	/* Upper half of CONFIG_DAT for Map A */
+#define MAP_A_CONFIG_DATA_LOW	0x0CFC	/* Lower half of CONFIG_DAT for Map A */
+#define MAP_B_CONFIG_ADDR_HIGH	0xfec0	/* Upper half of CONFIG_ADDR for Map B */
+#define MAP_B_CONFIG_ADDR_LOW	0x0000	/* Lower half of CONFIG_ADDR for Map B */
+#define MAP_B_CONFIG_DATA_HIGH	0xfee0	/* Upper half of CONFIG_DAT for Map B */
+#define MAP_B_CONFIG_DATA_LOW	0x0000	/* Lower half of CONFIG_DAT for Map B */
+
+
+#if defined(CFG_ADDR_MAP_A)
+#define CONFIG_ADDR_HIGH    MAP_A_CONFIG_ADDR_HIGH  /* Upper half of CONFIG_ADDR */
+#define CONFIG_ADDR_LOW	    MAP_A_CONFIG_ADDR_LOW   /* Lower half of CONFIG_ADDR */
+#define CONFIG_DATA_HIGH    MAP_A_CONFIG_DATA_HIGH  /* Upper half of CONFIG_DAT */
+#define CONFIG_DATA_LOW	    MAP_A_CONFIG_DATA_LOW   /* Lower half of CONFIG_DAT */
+#else /* Assume Map B, default */
+#define CONFIG_ADDR_HIGH    MAP_B_CONFIG_ADDR_HIGH  /* Upper half of CONFIG_ADDR */
+#define CONFIG_ADDR_LOW	    MAP_B_CONFIG_ADDR_LOW   /* Lower half of CONFIG_ADDR */
+#define CONFIG_DATA_HIGH    MAP_B_CONFIG_DATA_HIGH  /* Upper half of CONFIG_DAT */
+#define CONFIG_DATA_LOW	    MAP_B_CONFIG_DATA_LOW   /* Lower half of CONFIG_DAT */
+#endif
+
+#define CONFIG_ADDR	(CONFIG_ADDR_HIGH << 16 | CONFIG_ADDR_LOW)
+
+#define CONFIG_DATA	(CONFIG_DATA_HIGH << 16 | CONFIG_DATA_LOW)
+
+/* Macros to write to config registers. addr should be a constant in all cases */
+
+#define CONFIG_WRITE_BYTE( addr, data ) \
+  __asm__ __volatile__( \
+  " stwbrx %1, 0, %0\n \
+    sync\n \
+    stb %3, %4(%2)\n \
+    sync " \
+  : /* no output */ \
+  : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
+    "b" (CONFIG_DATA), "r" (data), \
+    "n" ((addr) & 3));
+
+#define CONFIG_WRITE_HALFWORD( addr, data ) \
+  __asm__ __volatile__( \
+  " stwbrx %1, 0, %0\n \
+    sync\n \
+    sthbrx %3, %4, %2\n \
+    sync " \
+  : /* no output */ \
+  : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
+    "r" (CONFIG_DATA), "r" (data), \
+    "b" ((addr) & 3));
+
+/* this assumes it's writeing on word boundaries*/
+#define CONFIG_WRITE_WORD( addr, data ) \
+  __asm__ __volatile__( \
+  " stwbrx %1, 0, %0\n \
+    sync\n \
+    stwbrx %3, 0, %2\n \
+    sync " \
+  : /* no output */ \
+  : "r" (CONFIG_ADDR), "r" (addr), \
+    "r" (CONFIG_DATA), "r" (data));
+
+/* Configuration register reads*/
+
+#define CONFIG_READ_BYTE( addr, reg ) \
+  __asm__ ( \
+  " stwbrx %1, 0, %2\n \
+    sync\n \
+    lbz	  %0, %4(%3)\n \
+    sync " \
+  : "=r" (reg) \
+  : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
+    "b" (CONFIG_DATA), "n" ((addr) & 3));
+
+
+#define CONFIG_READ_HALFWORD( addr, reg ) \
+  __asm__ ( \
+  " stwbrx %1, 0, %2\n \
+    sync\n \
+    lhbrx %0, %4, %3\n \
+    sync " \
+  : "=r" (reg) \
+  : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
+    "r" (CONFIG_DATA), \
+    "b" ((addr) & 3));
+
+/* this assumes it's reading on word boundaries*/
+#define CONFIG_READ_WORD( addr, reg ) \
+  __asm__ ( \
+  " stwbrx %1, 0, %2\n \
+    sync\n \
+    lwbrx %0, 0, %3\n \
+    sync " \
+  : "=r" (reg) \
+  : "r" (addr), "r" (CONFIG_ADDR),\
+    "r" (CONFIG_DATA));
+
+/*
+ *  configuration register 'addresses'.
+ *  These are described in chaper 5 of the 8240 users manual.
+ *  Where the register has an abreviation in the manual, this has
+ *  been usaed here, otherwise a name in keeping with the norm has
+ *  been invented.
+ *  Note that some of these registers aren't documented in the manual.
+ */
+
+#define PCICR		0x80000004  /* PCI Command Register */
+#define PCISR		0x80000006  /* PCI Status Register */
+#define REVID		0x80000008  /* CPU revision id */
+#define PIR		0x80000009  /* PCI Programming Interface Register */
+#define PBCCR		0x8000000b  /* PCI Base Class Code Register */
+#define PCLSR		0x8000000c  /* Processor Cache Line Size Register */
+#define PLTR		0x8000000d  /* PCI Latancy Timer Register */
+#define PHTR		0x8000000e  /* PCI Header Type Register */
+#define BISTCTRL	0x8000000f  /* BIST Control */
+#define LMBAR		0x80000010  /* Local Base Addres Register */
+#define PCSRBAR		0x80000014  /* PCSR Base Address Register */
+#define ILR		0x8000003c  /* PCI Interrupt Line Register */
+#define IPR		0x8000003d  /* Interrupt Pin Register */
+#define MINGNT		0x8000003e  /* MIN GNI */
+#define MAXLAT		0x8000003f  /* MAX LAT */
+#define PCIACR		0x80000046  /* PCI Arbiter Control Register */
+#define PMCR1		0x80000070  /* Power management config. 1 */
+#define PMCR2		0x80000072  /* Power management config. 2 */
+#define ODCR		0x80000073  /* Output Driver Control Register */
+#define CLKDCR		0x80000074  /* CLK Driver Control Register */
+#if defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
+#define MIOCR1		0x80000076  /* Miscellaneous I/O Control Register 1 */
+#define MIOCR2		0x80000077  /* Miscellaneous I/O Control Register 2 */
+#endif
+#define EUMBBAR		0x80000078  /* Embedded Utilities Memory Block Base Address Register */
+#define EUMBBAR_VAL	0x80500000  /* PCI Relocation offset for EUMB region */
+#define EUMBSIZE	0x00100000  /* Size of EUMB region */
+
+#define MSAR1		0x80000080  /* Memory Starting Address Register 1 */
+#define MSAR2		0x80000084  /* Memory Starting Address Register 2 */
+#define EMSAR1		0x80000088  /* Extended Memory Starting Address Register 1*/
+#define EMSAR2		0x8000008c  /* Extended Memory Starting Address Register 2*/
+#define MEAR1		0x80000090  /* Memory Ending Address Register 1 */
+#define MEAR2		0x80000094  /* Memory Ending Address Register 2 */
+#define EMEAR1		0x80000098  /* Extended Memory Ending Address Register 1 */
+#define EMEAR2		0x8000009c  /* Extended Memory Ending Address Register 2 */
+#define MBER		0x800000a0  /* Memory bank Enable Register*/
+#define MPMR		0x800000a3  /* Memory Page Mode Register (stores PGMAX) */
+#define PICR1		0x800000a8  /* Processor Interface Configuration Register 1 */
+#define PICR2		0x800000ac  /* Processor Interface Configuration Register 2 */
+#define ECCSBECR	0x800000b8  /* ECC Single-Bit Error Counter Register */
+#define ECCSBETR	0x800000b8  /* ECC Single-Bit Error Trigger Register */
+#define ERRENR1		0x800000c0  /* Error Enableing Register 1 */
+#define ERRENR2		0x800000c4  /* Error Enableing Register 2 */
+#define ERRDR1		0x800000c1  /* Error Detection Register 1 */
+#define IPBESR		0x800000c3  /* Internal Processor Error Status Register */
+#define ERRDR2		0x800000c5  /* Error Detection Register 2 */
+#define PBESR		0x800000c7  /* PCI Bus Error Status Register */
+#define PBEAR		0x800000c8  /* Processor/PCI Bus Error Status Register */
+#define AMBOR		0x800000e0  /* Address Map B Options Register */
+#define PCMBCR		0x800000e1  /* PCI/Memory Buffer Configuration */
+#define MCCR1		0x800000f0  /* Memory Control Configuration Register 1 */
+#define MCCR2		0x800000f4  /* Memory Control Configuration Register 2 */
+#define MCCR3		0x800000f8  /* Memory Control Configuration Register 3 */
+#define MCCR4		0x800000fc  /* Memory Control Configuration Register 4 */
+
+/* some values for some of the above */
+
+#define PICR1_CF_APARK		0x00000008
+#define PICR1_LE_MODE		0x00000020
+#define PICR1_ST_GATH_EN	0x00000040
+#if defined(CONFIG_MPC8240)
+#define PICR1_EN_PCS		0x00000080 /* according to dink code, sets the 8240 to handle pci config space */
+#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
+#define PICR1_NO_BUSW_CK	0x00000080 /* no bus width check for flash writes */
+#define PICR1_DEC		0x00000100 /* Time Base enable on 8245/8241 */
+#define ERCR1		        0x800000d0  /* Extended ROM Configuration Register 1 */
+#define ERCR2		        0x800000d4  /* Extended ROM Configuration Register 2 */
+#define ERCR3		        0x800000d8  /* Extended ROM Configuration Register 3 */
+#define ERCR4		        0x800000dc  /* Extended ROM Configuration Register 4 */
+#define MIOCR1		        0x80000076  /* Miscellaneous I/O Control Register 1 */
+#define MIOCR1_ADR_X	        0x80000074  /* Miscellaneous I/O Control Register 1 */
+#define MIOCR1_SHIFT	        2
+#define MIOCR2		        0x80000077  /* Miscellaneous I/O Control Register 2 */
+#define MIOCR2_ADR_X	        0x80000074  /* Miscellaneous I/O Control Register 1 */
+#define MIOCR2_SHIFT	        3
+#define ODCR_ADR_X	        0x80000070	/* Output Driver Control register */
+#define ODCR_SHIFT              3
+#define PMCR2_ADR	        0x80000072	/* Power Mgmnt Cfg 2 register */
+#define PMCR2_ADR_X	        0x80000070
+#define PMCR2_SHIFT             3
+#define PMCR1_ADR	        0x80000070	/* Power Mgmnt Cfg 1 reister */
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+#define PICR1_CF_DPARK		0x00000200
+#define PICR1_MCP_EN		0x00000800
+#define PICR1_FLASH_WR_EN	0x00001000
+#ifdef CONFIG_MPC8240
+#define PICR1_ADDRESS_MAP	0x00010000
+#define PIRC1_MSK		0xff000000
+#endif
+#define PICR1_PROC_TYPE_MSK	0x00060000
+#define PICR1_PROC_TYPE_603E	0x00040000
+#define PICR1_RCS0		0x00100000
+
+#define PICR2_CF_SNOOP_WS_MASK	0x000c0000
+#define PICR2_CF_SNOOP_WS_0WS	0x00000000
+#define PICR2_CF_SNOOP_WS_1WS	0x00040000
+#define PICR2_CF_SNOOP_WS_2WS	0x00080000
+#define PICR2_CF_SNOOP_WS_3WS	0x000c0000
+#define PICR2_CF_APHASE_WS_MASK 0x0000000c
+#define PICR2_CF_APHASE_WS_0WS	0x00000000
+#define PICR2_CF_APHASE_WS_1WS	0x00000004
+#define PICR2_CF_APHASE_WS_2WS	0x00000008
+#define PICR2_CF_APHASE_WS_3WS	0x0000000c
+
+#define MCCR1_ROMNAL_SHIFT	28
+#define MCCR1_ROMNAL_MSK	0xf0000000
+#define MCCR1_ROMFAL_SHIFT	23
+#define MCCR1_ROMFAL_MSK	0x0f800000
+#define MCCR1_DBUS_SIZE0        0x00400000
+#define MCCR1_BURST		0x00100000
+#define MCCR1_MEMGO		0x00080000
+#define MCCR1_SREN		0x00040000
+#if defined(CONFIG_MPC8240)
+#define MCCR1_RAM_TYPE		0x00020000
+#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
+#define MCCR1_SDRAM_EN		0x00020000
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+#define MCCR1_PCKEN		0x00010000
+#define MCCR1_BANK1ROW_SHIFT	2
+#define MCCR1_BANK2ROW_SHIFT	4
+#define MCCR1_BANK3ROW_SHIFT	6
+#define MCCR1_BANK4ROW_SHIFT	8
+#define MCCR1_BANK5ROW_SHIFT	10
+#define MCCR1_BANK6ROW_SHIFT	12
+#define MCCR1_BANK7ROW_SHIFT	14
+
+#define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000
+#define MCCR2_TS_WAIT_TIMER_SHIFT 29
+#define MCCR2_ASRISE_MSK	0x1e000000
+#define MCCR2_ASRISE_SHIFT	25
+#define MCCR2_ASFALL_MSK	0x01e00000
+#define MCCR2_ASFALL_SHIFT	21
+
+#define MCCR2_INLINE_PAR_NOT_ECC    0x00100000
+#define MCCR2_WRITE_PARITY_CHK	0x00080000
+#define MCCR2_INLFRD_PARECC_CHK_EN  0x00040000
+#ifdef CONFIG_MPC8240
+#define MCCR2_ECC_EN		0x00020000
+#define MCCR2_EDO		0x00010000
+#endif
+#define MCCR2_REFINT_MSK	0x0000fffc
+#define MCCR2_REFINT_SHIFT	2
+#define MCCR2_RSV_PG		0x00000002
+#define MCCR2_PMW_PAR		0x00000001
+
+#define MCCR3_BSTOPRE2TO5_MSK	0xf0000000 /*BSTOPRE[2-5]*/
+#define MCCR3_BSTOPRE2TO5_SHIFT 28
+#define MCCR3_REFREC_MSK	0x0f000000
+#define MCCR3_REFREC_SHIFT	24
+#ifdef CONFIG_MPC8240
+#define MCCR3_RDLAT_MSK		0x00f00000
+#define MCCR3_RDLAT_SHIFT	20
+#define MCCR3_CPX		0x00010000
+#define MCCR3_RAS6P_MSK		0x00078000
+#define MCCR3_RAS6P_SHIFT	15
+#define MCCR3_CAS5_MSK		0x00007000
+#define MCCR3_CAS5_SHIFT	12
+#define MCCR3_CP4_MSK		0x00000e00
+#define MCCR3_CP4_SHIFT		9
+#define MCCR3_CAS3_MSK		0x000001c0
+#define MCCR3_CAS3_SHIFT	6
+#define MCCR3_RCD2_MSK		0x00000038
+#define MCCR3_RCD2_SHIFT	3
+#define MCCR3_RP1_MSK		0x00000007
+#define MCCR3_RP1_SHIFT		0
+#endif
+
+#define MCCR4_PRETOACT_MSK	0xf0000000
+#define MCCR4_PRETOACT_SHIFT	28
+#define MCCR4_ACTTOPRE_MSK	0x0f000000
+#define MCCR4_ACTTOPRE_SHIFT	24
+#define MCCR4_WMODE		0x00800000
+#define MCCR4_INLINE		0x00400000
+#if defined(CONFIG_MPC8240)
+#define MCCR4_BIT21		0x00200000 /* this include cos DINK code sets it- unknown function*/
+#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
+#define MCCR4_EXTROM		0x00200000 /* enables Extended ROM space */
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+#define MCCR4_REGISTERED	0x00100000
+#define MCCR4_BSTOPRE0TO1_MSK	0x000c0000 /*BSTOPRE[0-1]*/
+#define MCCR4_BSTOPRE0TO1_SHIFT 18
+#define MCCR4_REGDIMM		0x00008000
+#define MCCR4_SDMODE_MSK	0x00007f00
+#define MCCR4_SDMODE_SHIFT	8
+#define MCCR4_ACTTORW_MSK	0x000000f0
+#define MCCR4_ACTTORW_SHIFT	4
+#define MCCR4_BSTOPRE6TO9_MSK	0x0000000f /*BSTOPRE[6-9]*/
+#define MCCR4_BSTOPRE6TO9_SHIFT 0
+#define MCCR4_DBUS_SIZE2_SHIFT	17
+
+#define MICR_ADDR_MASK		0x0ff00000
+#define MICR_ADDR_SHIFT		20
+#define MICR_EADDR_MASK		0x30000000
+#define MICR_EADDR_SHIFT	28
+
+#define BATU_BEPI_MSK		0xfffe0000
+#define BATU_BL_MSK		0x00001ffc
+
+#define BATU_BL_128K		0x00000000
+#define BATU_BL_256K		0x00000004
+#define BATU_BL_512K		0x0000000c
+#define BATU_BL_1M		0x0000001c
+#define BATU_BL_2M		0x0000003c
+#define BATU_BL_4M		0x0000007c
+#define BATU_BL_8M		0x000000fc
+#define BATU_BL_16M		0x000001fc
+#define BATU_BL_32M		0x000003fc
+#define BATU_BL_64M		0x000007fc
+#define BATU_BL_128M		0x00000ffc
+#define BATU_BL_256M		0x00001ffc
+
+#define BATU_VS			0x00000002
+#define BATU_VP			0x00000001
+
+#define BATL_BRPN_MSK		0xfffe0000
+#define BATL_WIMG_MSK		0x00000078
+
+#define BATL_WRITETHROUGH	0x00000040
+#define BATL_CACHEINHIBIT	0x00000020
+#define BATL_MEMCOHERENCE	0x00000010
+#define BATL_GUARDEDSTORAGE	0x00000008
+
+#define BATL_PP_MSK		0x00000003
+#define BATL_PP_00		0x00000000 /* No access */
+#define BATL_PP_01		0x00000001 /* Read-only */
+#define BATL_PP_10		0x00000002 /* Read-write */
+#define BATL_PP_11		0x00000003
+
+/*
+ * I'd attempt to do defines for the PP bits, but it's use is a bit
+ * too complex, see the PowerPC Operating Environment Architecture
+ * section in the PowerPc arch book, chapter 4.
+ */
+
+/*eumb and epic config*/
+
+#define EPIC_FPR		0x00041000
+#define EPIC_GCR		0x00041020
+#define EPIC_EICR		0x00041030
+#define EPIC_EVI		0x00041080
+#define EPIC_PI			0x00041090
+#define EPIC_SVR		0x000410E0
+#define EPIC_TFRR		0x000410F0
+
+/*
+ * Note the information for these is rather mangled in the 8240 manual.
+ * These are guesses.
+ */
+
+#define EPIC_GTCCR0		0x00041100
+#define EPIC_GTCCR1		0x00041140
+#define EPIC_GTCCR2		0x00041180
+#define EPIC_GTCCR3		0x000411C0
+#define EPIC_GTBCR0		0x00041110
+#define EPIC_GTBCR1		0x00041150
+#define EPIC_GTBCR2		0x00041190
+#define EPIC_GTBCR3		0x000411D0
+#define EPIC_GTVPR0		0x00041120
+#define EPIC_GTVPR1		0x00041160
+#define EPIC_GTVPR2		0x000411a0
+#define EPIC_GTVPR3		0x000411e0
+#define EPIC_GTDR0		0x00041130
+#define EPIC_GTDR1		0x00041170
+#define EPIC_GTDR2		0x000411b0
+#define EPIC_GTDR3		0x000411f0
+
+#define EPIC_IVPR0		0x00050200
+#define EPIC_IVPR1		0x00050220
+#define EPIC_IVPR2		0x00050240
+#define EPIC_IVPR3		0x00050260
+#define EPIC_IVPR4		0x00050280
+
+#define EPIC_SVPR0		0x00050200
+#define EPIC_SVPR1		0x00050220
+#define EPIC_SVPR2		0x00050240
+#define EPIC_SVPR3		0x00050260
+#define EPIC_SVPR4		0x00050280
+#define EPIC_SVPR5		0x000502A0
+#define EPIC_SVPR6		0x000502C0
+#define EPIC_SVPR7		0x000502E0
+#define EPIC_SVPR8		0x00050300
+#define EPIC_SVPR9		0x00050320
+#define EPIC_SVPRa		0x00050340
+#define EPIC_SVPRb		0x00050360
+#define EPIC_SVPRc		0x00050380
+#define EPIC_SVPRd		0x000503A0
+#define EPIC_SVPRe		0x000503C0
+#define EPIC_SVPRf		0x000503E0
+
+/* MPC8240 Byte Swap/PCI Support Macros */
+#define BYTE_SWAP_16_BIT(x)    ( (((x) & 0x00ff) << 8) | ( (x) >> 8) )
+#define LONGSWAP(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
+		     (((x) & 0x00ff0000) >>  8) | (((x) & 0xff000000) >> 24) )
+#define PCISWAP(x)   LONGSWAP(x)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * MPC107 Support
+ *
+ */
+unsigned int mpc824x_mpc107_getreg(unsigned int regNum);
+void mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal);
+void mpc824x_mpc107_write8(unsigned int address, unsigned char data);
+void mpc824x_mpc107_write16(unsigned int address, unsigned short data);
+void mpc824x_mpc107_write32(unsigned int address, unsigned int data);
+unsigned char mpc824x_mpc107_read8(unsigned int address);
+unsigned short mpc824x_mpc107_read16(unsigned int address);
+unsigned int mpc824x_mpc107_read32(unsigned int address);
+unsigned int mpc824x_eummbar_read(unsigned int regNum);
+void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal);
+
+#ifdef CONFIG_PCI
+struct pci_controller;
+void pci_cpm824x_init(struct pci_controller* hose);
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __MPC824X_H__ */
diff --git a/include/mpc8260.h b/include/mpc8260.h
new file mode 100755
index 0000000..ff52a7b
--- /dev/null
+++ b/include/mpc8260.h
@@ -0,0 +1,913 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8260.h
+ *
+ * MPC8255 / MPC8260 specific definitions
+ */
+
+#ifndef __MPC8260_H__
+#define __MPC8260_H__
+
+#ifdef CONFIG_MPC8255
+#define CPU_ID_STR	"MPC8255"
+#endif
+#ifndef CPU_ID_STR
+#if defined(CONFIG_MPC8272_FAMILY)
+#define CPU_ID_STR	"MPC8272"
+#else
+#define CPU_ID_STR	"MPC8260"
+#endif
+#endif /* !CPU_ID_STR */
+
+/*-----------------------------------------------------------------------
+ * Exception offsets (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset			*/
+
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration Register					 4-25
+ */
+#define BCR_EBM		0x80000000	/* External Bus Mode		*/
+#define BCR_APD_MSK	0x70000000	/* Address Phase Delay Mask	*/
+#define BCR_L2C		0x08000000	/* Secondary Cache Controller	*/
+#define BCR_L2D_MSK	0x07000000	/* L2 Cache Hit Delay Mask	*/
+#define BCR_PLDP	0x00800000	/* Pipeline Maximum Depth	*/
+#define BCR_EAV		0x00400000	/* Enable Address Visibility	*/
+#define BCR_ETM		0x00080000	/* Compatibility Mode Enable	*/
+#define BCR_LETM	0x00040000	/* LocalBus Compatibility Mode Enable*/
+#define BCR_EPAR	0x00020000	/* Even Parity			*/
+#define BCR_LEPAR	0x00010000	/* Local Bus Even Parity	*/
+#define BCR_NPQM0	0x00008000	/* Non PowerQUICC-II Master 0	*/
+#define BCR_NPQM1	0x00004000	/* Non PowerQUICC-II Master 1	*/
+#define BCR_NPQM2	0x00002000	/* Non PowerQUICC-II Master 2	*/
+#define BCR_EXDD	0x00000400	/* External Master Delay Disable*/
+#define BCR_ISPS	0x00000010	/* Internal Space Port Size	*/
+
+/*-----------------------------------------------------------------------
+ * PPC_ACR - 60x Bus Arbiter Configuration Register			 4-28
+ */
+#define PPC_ACR_DBGD	0x20		/* Data Bus Grant Delay		*/
+#define PPC_ACR_EARB	0x10		/* External Arbitration		*/
+#define PPC_ACR_PRKM_MSK 0x0f		/* Parking Master		*/
+
+#define PPC_ACR_PRKM_CPMH 0x00		/* CPM high request level	*/
+#define PPC_ACR_PRKM_CPMM 0x01		/* CPM middle request level	*/
+#define PPC_ACR_PRKM_CPML 0x02		/* CPM low request level	*/
+#define PPC_ACR_PRKM_CORE 0x06		/* Internal Core		*/
+#define PPC_ACR_PRKM_EXT1 0x07		/* External Master 1		*/
+#define PPC_ACR_PRKM_EXT2 0x08		/* External Master 2		*/
+#define PPC_ACR_PRKM_EXT3 0x09		/* External Master 3		*/
+
+/*-----------------------------------------------------------------------
+ * PPC_ALRH/PPC_ALRL - 60x Bus Arbitration-Level Registers		 4-28
+ */
+#define PPC_ALRH_PF0_MSK  0xf0000000	/* Priority Field  0 Mask	*/
+#define PPC_ALRH_PF1_MSK  0x0f000000	/* Priority Field  1 Mask	*/
+#define PPC_ALRH_PF2_MSK  0x00f00000	/* Priority Field  2 Mask	*/
+#define PPC_ALRH_PF3_MSK  0x000f0000	/* Priority Field  3 Mask	*/
+#define PPC_ALRH_PF4_MSK  0x0000f000	/* Priority Field  4 Mask	*/
+#define PPC_ALRH_PF5_MSK  0x00000f00	/* Priority Field  5 Mask	*/
+#define PPC_ALRH_PF6_MSK  0x000000f0	/* Priority Field  6 Mask	*/
+#define PPC_ALRH_PF7_MSK  0x0000000f	/* Priority Field  7 Mask	*/
+#define PPC_ALRL_PF8_MSK  0xf0000000	/* Priority Field  8 Mask	*/
+#define PPC_ALRL_PF9_MSK  0x0f000000	/* Priority Field  9 Mask	*/
+#define PPC_ALRL_PF10_MSK 0x00f00000	/* Priority Field 10 Mask	*/
+#define PPC_ALRL_PF11_MSK 0x000f0000	/* Priority Field 11 Mask	*/
+#define PPC_ALRL_PF12_MSK 0x0000f000	/* Priority Field 12 Mask	*/
+#define PPC_ALRL_PF13_MSK 0x00000f00	/* Priority Field 13 Mask	*/
+#define PPC_ALRL_PF14_MSK 0x000000f0	/* Priority Field 14 Mask	*/
+#define PPC_ALRL_PF15_MSK 0x0000000f	/* Priority Field 15 Mask	*/
+
+/*-----------------------------------------------------------------------
+ * LCL_ACR - Local Bus Arbiter Configuration Register			 4-29
+ */
+#define LCL_ACR_DBGD	0x20		/* Data Bus Grant Delay		*/
+#define LCL_ACR_PRKM_MSK 0x0f		/* Parking Master		*/
+
+#define LCL_ACR_PRKM_CPMH 0x00		/* CPM high request level	*/
+#define LCL_ACR_PRKM_CPMM 0x01		/* CPM middle request level	*/
+#define LCL_ACR_PRKM_CPML 0x02		/* CPM low request level	*/
+#define LCL_ACR_PRKM_HOST 0x03		/* Host Bridge			*/
+
+/*-----------------------------------------------------------------------
+ * LCL_ALRH/LCL_ALRL - Local Bus Arbitration Level Registers		 4-30
+ */
+#define LCL_ALRH_PF0_MSK  0xf0000000	/* Priority Field  0 Mask	*/
+#define LCL_ALRH_PF1_MSK  0x0f000000	/* Priority Field  1 Mask	*/
+#define LCL_ALRH_PF2_MSK  0x00f00000	/* Priority Field  2 Mask	*/
+#define LCL_ALRH_PF3_MSK  0x000f0000	/* Priority Field  3 Mask	*/
+#define LCL_ALRH_PF4_MSK  0x0000f000	/* Priority Field  4 Mask	*/
+#define LCL_ALRH_PF5_MSK  0x00000f00	/* Priority Field  5 Mask	*/
+#define LCL_ALRH_PF6_MSK  0x000000f0	/* Priority Field  6 Mask	*/
+#define LCL_ALRH_PF7_MSK  0x0000000f	/* Priority Field  7 Mask	*/
+#define LCL_ALRL_PF8_MSK  0xf0000000	/* Priority Field  8 Mask	*/
+#define LCL_ALRL_PF9_MSK  0x0f000000	/* Priority Field  9 Mask	*/
+#define LCL_ALRL_PF10_MSK 0x00f00000	/* Priority Field 10 Mask	*/
+#define LCL_ALRL_PF11_MSK 0x000f0000	/* Priority Field 11 Mask	*/
+#define LCL_ALRL_PF12_MSK 0x0000f000	/* Priority Field 12 Mask	*/
+#define LCL_ALRL_PF13_MSK 0x00000f00	/* Priority Field 13 Mask	*/
+#define LCL_ALRL_PF14_MSK 0x000000f0	/* Priority Field 14 Mask	*/
+#define LCL_ALRL_PF15_MSK 0x0000000f	/* Priority Field 15 Mask	*/
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register				 4-31
+ */
+#define SIUMCR_BBD	0x80000000	/* Bus Busy Disable		*/
+#define SIUMCR_ESE	0x40000000	/* External Snoop Enable	*/
+#define SIUMCR_PBSE	0x20000000	/* Parity Byte Select Enable	*/
+#define SIUMCR_CDIS	0x10000000	/* Core Disable			*/
+#define SIUMCR_DPPC00	0x00000000	/* Data Parity Pins Configuration*/
+#define SIUMCR_DPPC01	0x04000000	/* - " -			*/
+#define SIUMCR_DPPC10	0x08000000	/* - " -			*/
+#define SIUMCR_DPPC11	0x0c000000	/* - " -			*/
+#define SIUMCR_L2CPC00	0x00000000	/* L2 Cache Pins Configuration	*/
+#define SIUMCR_L2CPC01	0x01000000	/* - " -			*/
+#define SIUMCR_L2CPC10	0x02000000	/* - " -			*/
+#define SIUMCR_L2CPC11	0x03000000	/* - " -			*/
+#define SIUMCR_LBPC00	0x00000000	/* Local Bus Pins Configuration	*/
+#define SIUMCR_LBPC01	0x00400000	/* - " -			*/
+#define SIUMCR_LBPC10	0x00800000	/* - " -			*/
+#define SIUMCR_LBPC11	0x00c00000	/* - " -			*/
+#define SIUMCR_APPC00	0x00000000	/* Address Parity Pins Configuration*/
+#define SIUMCR_APPC01	0x00100000	/* - " -			*/
+#define SIUMCR_APPC10	0x00200000	/* - " -			*/
+#define SIUMCR_APPC11	0x00300000	/* - " -			*/
+#define SIUMCR_CS10PC00	0x00000000	/* CS10 Pin Configuration	*/
+#define SIUMCR_CS10PC01	0x00040000	/* - " -			*/
+#define SIUMCR_CS10PC10	0x00080000	/* - " -			*/
+#define SIUMCR_CS10PC11	0x000c0000	/* - " -			*/
+#define SIUMCR_BCTLC00	0x00000000	/* Buffer Control Configuration	*/
+#define SIUMCR_BCTLC01	0x00010000	/* - " -			*/
+#define SIUMCR_BCTLC10	0x00020000	/* - " -			*/
+#define SIUMCR_BCTLC11	0x00030000	/* - " -			*/
+#define SIUMCR_MMR00	0x00000000	/* Mask Masters Requests	*/
+#define SIUMCR_MMR01	0x00004000	/* - " -			*/
+#define SIUMCR_MMR10	0x00008000	/* - " -			*/
+#define SIUMCR_MMR11	0x0000c000	/* - " -			*/
+#define SIUMCR_LPBSE	0x00002000	/* LocalBus Parity Byte Select Enable*/
+
+/*-----------------------------------------------------------------------
+ * IMMR - Internal Memory Map Register					 4-34
+ */
+#define IMMR_ISB_MSK	 0xfffe0000	/* Internal Space base		*/
+#define IMMR_PARTNUM_MSK 0x0000ff00	/* Part number			*/
+#define IMMR_MASKNUM_MSK 0x000000ff	/* Mask number			*/
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control Register				 4-35
+ */
+#define SYPCR_SWTC	0xffff0000	/* Software Watchdog Timer Count*/
+#define SYPCR_BMT	0x0000ff00	/* Bus Monitor Timing		*/
+#define SYPCR_PBME	0x00000080	/* 60x Bus Monitor Enable	*/
+#define SYPCR_LBME	0x00000040	/* Local Bus Monitor Enable	*/
+#define SYPCR_SWE	0x00000004	/* Software Watchdog Enable	*/
+#define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Select*/
+#define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale	*/
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control Register			 4-40
+ */
+#define TMCNTSC_SEC	0x0080		/* Once Per Second Interrupt	*/
+#define TMCNTSC_ALR	0x0040		/* Alarm Interrupt		*/
+#define TMCNTSC_SIE	0x0008		/* Second Interrupt Enable	*/
+#define TMCNTSC_ALE	0x0004		/* Alarm Interrupt Enable	*/
+#define TMCNTSC_TCF	0x0002		/* Time Counter Frequency	*/
+#define TMCNTSC_TCE	0x0001		/* Time Counter Enable		*/
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control Register		 4-42
+ */
+#if 0	/* already defined in asm/immap_8260.h */
+#define PISCR_PS	0x0080		/* Periodic Interrupt Status	*/
+#define PISCR_PIE	0x0004		/* Periodic Interrupt Enable	*/
+#define PISCR_PTF	0x0002		/* Periodic Timer Frequency	*/
+#define PISCR_PTE	0x0001		/* Periodic Timer Enable	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * RSR - Reset Status Register						 5-4
+ */
+#define RSR_JTRS	0x00000020	/* JTAG Reset Status		*/
+#define RSR_CSRS	0x00000010	/* Check Stop Reset Status	*/
+#define RSR_SWRS	0x00000008	/* Software Watchdog Reset Status*/
+#define RSR_BMRS	0x00000004	/* Bus Monitor Reset Status	*/
+#define RSR_ESRS	0x00000002	/* External Soft Reset Status	*/
+#define RSR_EHRS	0x00000001	/* External Hard Reset Status	*/
+
+#define RSR_ALLBITS	(RSR_JTRS|RSR_CSRS|RSR_SWRS|RSR_BMRS|RSR_ESRS|RSR_EHRS)
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register						 5-5
+ */
+#define RMR_CSRE	0x00000001	/* Checkstop Reset Enable	*/
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Word					 5-8
+ */
+#define HRCW_EARB	0x80000000	/* External Arbitration		*/
+#define HRCW_EXMC	0x40000000	/* External Memory Controller	*/
+#define HRCW_CDIS	0x20000000	/* Core Disable			*/
+#define HRCW_EBM	0x10000000	/* External Bus Mode		*/
+#define HRCW_BPS00	0x00000000	/* Boot Port Size		*/
+#define HRCW_BPS01	0x04000000	/* - " -			*/
+#define HRCW_BPS10	0x08000000	/* - " -			*/
+#define HRCW_BPS11	0x0c000000	/* - " -			*/
+#define HRCW_CIP	0x02000000	/* Core Initial Prefix		*/
+#define HRCW_ISPS	0x01000000	/* Internal Space Port Size	*/
+#define HRCW_L2CPC00	0x00000000	/* L2 Cache Pins Configuration	*/
+#define HRCW_L2CPC01	0x00400000	/* - " -			*/
+#define HRCW_L2CPC10	0x00800000	/* - " -			*/
+#define HRCW_L2CPC11	0x00c00000	/* - " -			*/
+#define HRCW_DPPC00	0x00000000	/* Data Parity Pin Configuration*/
+#define HRCW_DPPC01	0x00100000	/* - " -			*/
+#define HRCW_DPPC10	0x00200000	/* - " -			*/
+#define HRCW_DPPC11	0x00300000	/* - " -			*/
+#define HRCW_reserved1	0x00080000	/* reserved			*/
+#define HRCW_ISB000	0x00000000	/* Initial Internal Space Base	*/
+#define HRCW_ISB001	0x00010000	/* - " -			*/
+#define HRCW_ISB010	0x00020000	/* - " -			*/
+#define HRCW_ISB011	0x00030000	/* - " -			*/
+#define HRCW_ISB100	0x00040000	/* - " -			*/
+#define HRCW_ISB101	0x00050000	/* - " -			*/
+#define HRCW_ISB110	0x00060000	/* - " -			*/
+#define HRCW_ISB111	0x00070000	/* - " -			*/
+#define HRCW_BMS	0x00008000	/* Boot Memory Space		*/
+#define HRCW_BBD	0x00004000	/* Bus Busy Disable		*/
+#define HRCW_MMR00	0x00000000	/* Mask Masters Requests	*/
+#define HRCW_MMR01	0x00001000	/* - " -			*/
+#define HRCW_MMR10	0x00002000	/* - " -			*/
+#define HRCW_MMR11	0x00003000	/* - " -			*/
+#define HRCW_LBPC00	0x00000000	/* Local Bus Pin Configuration	*/
+#define HRCW_LBPC01	0x00000400	/* - " -			*/
+#define HRCW_LBPC10	0x00000800	/* - " -			*/
+#define HRCW_LBPC11	0x00000c00	/* - " -			*/
+#define HRCW_APPC00	0x00000000	/* Address Parity Pin Configuration*/
+#define HRCW_APPC01	0x00000100	/* - " -			*/
+#define HRCW_APPC10	0x00000200	/* - " -			*/
+#define HRCW_APPC11	0x00000300	/* - " -			*/
+#define HRCW_CS10PC00	0x00000000	/* CS10 Pin Configuration	*/
+#define HRCW_CS10PC01	0x00000040	/* - " -			*/
+#define HRCW_CS10PC10	0x00000080	/* - " -			*/
+#define HRCW_CS10PC11	0x000000c0	/* - " -			*/
+#define HRCW_MODCK_H0000 0x00000000	/* High-order bits of MODCK Bus	*/
+#define HRCW_MODCK_H0001 0x00000001	/* - " -			*/
+#define HRCW_MODCK_H0010 0x00000002	/* - " -			*/
+#define HRCW_MODCK_H0011 0x00000003	/* - " -			*/
+#define HRCW_MODCK_H0100 0x00000004	/* - " -			*/
+#define HRCW_MODCK_H0101 0x00000005	/* - " -			*/
+#define HRCW_MODCK_H0110 0x00000006	/* - " -			*/
+#define HRCW_MODCK_H0111 0x00000007	/* - " -			*/
+#define HRCW_MODCK_H1000 0x00000008	/* - " -			*/
+#define HRCW_MODCK_H1001 0x00000009	/* - " -			*/
+#define HRCW_MODCK_H1010 0x0000000a	/* - " -			*/
+#define HRCW_MODCK_H1011 0x0000000b	/* - " -			*/
+#define HRCW_MODCK_H1100 0x0000000c	/* - " -			*/
+#define HRCW_MODCK_H1101 0x0000000d	/* - " -			*/
+#define HRCW_MODCK_H1110 0x0000000e	/* - " -			*/
+#define HRCW_MODCK_H1111 0x0000000f	/* - " -			*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control Register					 9-8
+ */
+#define SCCR_PCI_MODE	0x00000100	/* PCI Mode	*/
+#define SCCR_PCI_MODCK	0x00000080	/* Value of PCI_MODCK pin	*/
+#define SCCR_PCIDF_MSK	0x00000078	/* PCI division factor	*/
+#define SCCR_PCIDF_SHIFT 3
+#define SCCR_CLPD	0x00000004	/* CPM Low Power Disable	*/
+#define SCCR_DFBRG_MSK	0x00000003	/* Division factor of BRGCLK Mask */
+#define SCCR_DFBRG_SHIFT 0
+
+#define SCCR_DFBRG00	0x00000000	/* BRGCLK division by 4		*/
+#define SCCR_DFBRG01	0x00000001	/* BRGCLK division by 16 (normal op.)*/
+#define SCCR_DFBRG10	0x00000002	/* BRGCLK division by 64	*/
+#define SCCR_DFBRG11	0x00000003	/* BRGCLK division by 128	*/
+
+/*-----------------------------------------------------------------------
+ * SCMR - System Clock Mode Register					 9-9
+ */
+#define SCMR_CORECNF_MSK   0x1f000000	/* Core Configuration Mask	*/
+#define SCMR_CORECNF_SHIFT 24
+#define SCMR_BUSDF_MSK	   0x00f00000	/* 60x Bus Division Factor Mask	*/
+#define SCMR_BUSDF_SHIFT   20
+#define SCMR_CPMDF_MSK	   0x000f0000	/* CPM Division Factor Mask	*/
+#define SCMR_CPMDF_SHIFT   16
+#define SCMR_PLLDF	   0x00001000	/* PLL Pre-divider Value	*/
+#define SCMR_PLLMF_MSK	   0x00000fff	/* PLL Multiplication Factor Mask*/
+#define SCMR_PLLMF_MSKH7   0x0000000f	/* for HiP7 processors */
+#define SCMR_PLLMF_SHIFT 0
+
+
+/*-----------------------------------------------------------------------
+ * MxMR - Machine A/B/C Mode Registers					10-13
+ */
+#define MxMR_BSEL	0x80000000	/* Bus Select			*/
+#define MxMR_RFEN	0x40000000	/* Refresh Enable		*/
+#define MxMR_OP_MSK	0x30000000	/* Command Opcode Mask		*/
+#define MxMR_AMx_MSK	0x07000000	/* Addess Multiplex Size Mask	*/
+#define MxMR_DSx_MSK	0x00c00000	/* Disable Timer Period Mask	*/
+#define MxMR_G0CLx_MSK	0x00380000	/* General Line 0 Control Mask	*/
+#define MxMR_GPL_x4DIS	0x00040000	/* GPL_A4 Ouput Line Disable	*/
+#define MxMR_RLFx_MSK	0x0003c000	/* Read Loop Field Mask		*/
+#define MxMR_WLFx_MSK	0x00003c00	/* Write Loop Field Mask	*/
+#define MxMR_TLFx_MSK	0x000003c0	/* Refresh Loop Field Mask	*/
+#define MxMR_MAD_MSK	0x0000003f	/* Machine Address Mask		*/
+
+#define MxMR_OP_NORM	0x00000000	/* Normal Operation		*/
+#define MxMR_OP_WARR	0x10000000	/* Write to Array		*/
+#define MxMR_OP_RARR	0x20000000	/* Read from Array		*/
+#define MxMR_OP_RUNP	0x30000000	/* Run Pattern			*/
+
+#define MxMR_AMx_TYPE_0 0x00000000	/* Addess Multiplexing Type 0	*/
+#define MxMR_AMx_TYPE_1 0x01000000	/* Addess Multiplexing Type 1	*/
+#define MxMR_AMx_TYPE_2 0x02000000	/* Addess Multiplexing Type 2	*/
+#define MxMR_AMx_TYPE_3 0x03000000	/* Addess Multiplexing Type 3	*/
+#define MxMR_AMx_TYPE_4 0x04000000	/* Addess Multiplexing Type 4	*/
+#define MxMR_AMx_TYPE_5 0x05000000	/* Addess Multiplexing Type 5	*/
+
+#define MxMR_DSx_1_CYCL 0x00000000	/* 1 cycle Disable Period	*/
+#define MxMR_DSx_2_CYCL 0x00400000	/* 2 cycle Disable Period	*/
+#define MxMR_DSx_3_CYCL 0x00800000	/* 3 cycle Disable Period	*/
+#define MxMR_DSx_4_CYCL 0x00c00000	/* 4 cycle Disable Period	*/
+
+#define MxMR_G0CLx_A12	0x00000000	/* General Line 0 : A12		*/
+#define MxMR_G0CLx_A11	0x00080000	/* General Line 0 : A11		*/
+#define MxMR_G0CLx_A10	0x00100000	/* General Line 0 : A10		*/
+#define MxMR_G0CLx_A9	0x00180000	/* General Line 0 : A9		*/
+#define MxMR_G0CLx_A8	0x00200000	/* General Line 0 : A8		*/
+#define MxMR_G0CLx_A7	0x00280000	/* General Line 0 : A7		*/
+#define MxMR_G0CLx_A6	0x00300000	/* General Line 0 : A6		*/
+#define MxMR_G0CLx_A5	0x00380000	/* General Line 0 : A5		*/
+
+#define MxMR_RLFx_1X	0x00004000	/* Read Loop is executed 1 time	*/
+#define MxMR_RLFx_2X	0x00008000	/* Read Loop is executed 2 times*/
+#define MxMR_RLFx_3X	0x0000c000	/* Read Loop is executed 3 times*/
+#define MxMR_RLFx_4X	0x00010000	/* Read Loop is executed 4 times*/
+#define MxMR_RLFx_5X	0x00014000	/* Read Loop is executed 5 times*/
+#define MxMR_RLFx_6X	0x00018000	/* Read Loop is executed 6 times*/
+#define MxMR_RLFx_7X	0x0001c000	/* Read Loop is executed 7 times*/
+#define MxMR_RLFx_8X	0x00020000	/* Read Loop is executed 8 times*/
+#define MxMR_RLFx_9X	0x00024000	/* Read Loop is executed 9 times*/
+#define MxMR_RLFx_10X	0x00028000	/* Read Loop is executed 10 times*/
+#define MxMR_RLFx_11X	0x0002c000	/* Read Loop is executed 11 times*/
+#define MxMR_RLFx_12X	0x00030000	/* Read Loop is executed 12 times*/
+#define MxMR_RLFx_13X	0x00034000	/* Read Loop is executed 13 times*/
+#define MxMR_RLFx_14X	0x00038000	/* Read Loop is executed 14 times*/
+#define MxMR_RLFx_15X	0x0003c000	/* Read Loop is executed 15 times*/
+#define MxMR_RLFx_16X	0x00000000	/* Read Loop is executed 16 times*/
+
+#define MxMR_WLFx_1X	0x00000400	/* Write Loop is executed 1 time*/
+#define MxMR_WLFx_2X	0x00000800	/* Write Loop is executed 2 times*/
+#define MxMR_WLFx_3X	0x00000c00	/* Write Loop is executed 3 times*/
+#define MxMR_WLFx_4X	0x00001000	/* Write Loop is executed 4 times*/
+#define MxMR_WLFx_5X	0x00001400	/* Write Loop is executed 5 times*/
+#define MxMR_WLFx_6X	0x00001800	/* Write Loop is executed 6 times*/
+#define MxMR_WLFx_7X	0x00001c00	/* Write Loop is executed 7 times*/
+#define MxMR_WLFx_8X	0x00002000	/* Write Loop is executed 8 times*/
+#define MxMR_WLFx_9X	0x00002400	/* Write Loop is executed 9 times*/
+#define MxMR_WLFx_10X	0x00002800	/* Write Loop is executed 10 times*/
+#define MxMR_WLFx_11X	0x00002c00	/* Write Loop is executed 11 times*/
+#define MxMR_WLFx_12X	0x00003000	/* Write Loop is executed 12 times*/
+#define MxMR_WLFx_13X	0x00003400	/* Write Loop is executed 13 times*/
+#define MxMR_WLFx_14X	0x00003800	/* Write Loop is executed 14 times*/
+#define MxMR_WLFx_15X	0x00003c00	/* Write Loop is executed 15 times*/
+#define MxMR_WLFx_16X	0x00000000	/* Write Loop is executed 16 times*/
+
+#define MxMR_TLFx_1X	0x00000040	/* Timer Loop is executed 1 time*/
+#define MxMR_TLFx_2X	0x00000080	/* Timer Loop is executed 2 times*/
+#define MxMR_TLFx_3X	0x000000c0	/* Timer Loop is executed 3 times*/
+#define MxMR_TLFx_4X	0x00000100	/* Timer Loop is executed 4 times*/
+#define MxMR_TLFx_5X	0x00000140	/* Timer Loop is executed 5 times*/
+#define MxMR_TLFx_6X	0x00000180	/* Timer Loop is executed 6 times*/
+#define MxMR_TLFx_7X	0x000001c0	/* Timer Loop is executed 7 times*/
+#define MxMR_TLFx_8X	0x00000200	/* Timer Loop is executed 8 times*/
+#define MxMR_TLFx_9X	0x00000240	/* Timer Loop is executed 9 times*/
+#define MxMR_TLFx_10X	0x00000280	/* Timer Loop is executed 10 times*/
+#define MxMR_TLFx_11X	0x000002c0	/* Timer Loop is executed 11 times*/
+#define MxMR_TLFx_12X	0x00000300	/* Timer Loop is executed 12 times*/
+#define MxMR_TLFx_13X	0x00000340	/* Timer Loop is executed 13 times*/
+#define MxMR_TLFx_14X	0x00000380	/* Timer Loop is executed 14 times*/
+#define MxMR_TLFx_15X	0x000003c0	/* Timer Loop is executed 15 times*/
+#define MxMR_TLFx_16X	0x00000000	/* Timer Loop is executed 16 times*/
+
+
+/*-----------------------------------------------------------------------
+ * BRx - Memory Controller: Base Register				10-14
+ */
+#define BRx_BA_MSK	0xffff8000	/* Base Address Mask		*/
+#define BRx_PS_MSK	0x00001800	/* Port Size Mask		*/
+#define BRx_DECC_MSK	0x00000600	/* Data Error Correct+Check Mask*/
+#define BRx_WP		0x00000100	/* Write Protect		*/
+#define BRx_MS_MSK	0x000000e0	/* Machine Select Mask		*/
+#define BRx_EMEMC	0x00000010	/* External MEMC Enable		*/
+#define BRx_ATOM_MSK	0x0000000c	/* Atomic Operation Mask	*/
+#define BRx_DR		0x00000002	/* Data Pipelining		*/
+#define BRx_V		0x00000001	/* Bank Valid			*/
+
+#define BRx_PS_64	0x00000000	/* 64 bit port size (60x bus only)*/
+#define BRx_PS_8	0x00000800	/*  8 bit port size		*/
+#define BRx_PS_16	0x00001000	/* 16 bit port size		*/
+#define BRx_PS_32	0x00001800	/* 32 bit port size		*/
+
+#define BRx_DECC_NONE	0x00000000	/* Data Errors Checking Disabled*/
+#define BRx_DECC_NORMAL	0x00000200	/* Normal Parity Checking	*/
+#define BRx_DECC_RMWPC	0x00000400	/* Read-Modify-Write Parity Checking*/
+#define BRx_DECC_ECC	0x00000600	/* ECC Correction and Checking	*/
+
+#define BRx_MS_GPCM_P	0x00000000	/* G.P.C.M. 60x Bus Machine Select*/
+#define BRx_MS_GPCM_L	0x00000020	/* G.P.C.M. Local Bus Machine Select*/
+#define BRx_MS_SDRAM_P	0x00000040	/* SDRAM 60x Bus Machine Select	*/
+#define BRx_MS_SDRAM_L	0x00000060	/* SDRAM Local Bus Machine Select*/
+#define BRx_MS_UPMA	0x00000080	/* U.P.M.A Machine Select	*/
+#define BRx_MS_UPMB	0x000000a0	/* U.P.M.B Machine Select	*/
+#define BRx_MS_UPMC	0x000000c0	/* U.P.M.C Machine Select	*/
+
+#define BRx_ATOM_RAWA	0x00000004	/* Read-After-Write-Atomic	*/
+#define BRx_ATOM_WARA	0x00000008	/* Write-After-Read-Atomic	*/
+
+/*-----------------------------------------------------------------------
+ * ORx - Memory Controller: Option Register - SDRAM Mode		10-16
+ */
+#define ORxS_SDAM_MSK	0xfff00000	/* SDRAM Address Mask Mask	*/
+#define ORxS_LSDAM_MSK	0x000f8000	/* Lower SDRAM Address Mask Mask*/
+#define ORxS_BPD_MSK	0x00006000	/* Banks Per Device Mask	*/
+#define ORxS_ROWST_MSK	0x00001e00	/* Row Start Address Bit Mask	*/
+#define ORxS_NUMR_MSK	0x000001c0	/* Number of Row Addr Lines Mask*/
+#define ORxS_PMSEL	0x00000020	/* Page Mode Select		*/
+#define ORxS_IBID	0x00000010	/* Internal Bank Interleaving Disable*/
+
+#define ORxS_BPD_2	0x00000000	/* 2 Banks Per Device		*/
+#define ORxS_BPD_4	0x00002000	/* 4 Banks Per Device		*/
+#define ORxS_BPD_8	0x00004000	/* 8 Banks Per Device		*/
+
+/* ROWST values for xSDMR[PBI] = 0 */
+#define ORxS_ROWST_PBI0_A7  0x00000400	/* Row Start Address Bit is A7	*/
+#define ORxS_ROWST_PBI0_A8  0x00000800	/* Row Start Address Bit is A8	*/
+#define ORxS_ROWST_PBI0_A9  0x00000c00	/* Row Start Address Bit is A9	*/
+#define ORxS_ROWST_PBI0_A10 0x00001000	/* Row Start Address Bit is A10	*/
+#define ORxS_ROWST_PBI0_A11 0x00001400	/* Row Start Address Bit is A11	*/
+#define ORxS_ROWST_PBI0_A12 0x00001800	/* Row Start Address Bit is A12	*/
+#define ORxS_ROWST_PBI0_A13 0x00001c00	/* Row Start Address Bit is A13	*/
+
+/* ROWST values for xSDMR[PBI] = 1 */
+#define ORxS_ROWST_PBI1_A0  0x00000000	/* Row Start Address Bit is A0	*/
+#define ORxS_ROWST_PBI1_A1  0x00000200	/* Row Start Address Bit is A1	*/
+#define ORxS_ROWST_PBI1_A2  0x00000400	/* Row Start Address Bit is A2	*/
+#define ORxS_ROWST_PBI1_A3  0x00000600	/* Row Start Address Bit is A3	*/
+#define ORxS_ROWST_PBI1_A4  0x00000800	/* Row Start Address Bit is A4	*/
+#define ORxS_ROWST_PBI1_A5  0x00000a00	/* Row Start Address Bit is A5	*/
+#define ORxS_ROWST_PBI1_A6  0x00000c00	/* Row Start Address Bit is A6	*/
+#define ORxS_ROWST_PBI1_A7  0x00000e00	/* Row Start Address Bit is A7	*/
+#define ORxS_ROWST_PBI1_A8  0x00001000	/* Row Start Address Bit is A8	*/
+#define ORxS_ROWST_PBI1_A9  0x00001200	/* Row Start Address Bit is A9	*/
+#define ORxS_ROWST_PBI1_A10 0x00001400	/* Row Start Address Bit is A10	*/
+#define ORxS_ROWST_PBI1_A11 0x00001600	/* Row Start Address Bit is A11	*/
+#define ORxS_ROWST_PBI1_A12 0x00001800	/* Row Start Address Bit is A12	*/
+
+#define ORxS_NUMR_9	0x00000000	/*  9 Row Address Lines		*/
+#define ORxS_NUMR_10	0x00000040	/* 10 Row Address Lines		*/
+#define ORxS_NUMR_11	0x00000080	/* 11 Row Address Lines		*/
+#define ORxS_NUMR_12	0x000000c0	/* 12 Row Address Lines		*/
+#define ORxS_NUMR_13	0x00000100	/* 13 Row Address Lines		*/
+#define ORxS_NUMR_14	0x00000140	/* 14 Row Address Lines		*/
+#define ORxS_NUMR_15	0x00000180	/* 15 Row Address Lines		*/
+#define ORxS_NUMR_16	0x000001c0	/* 16 Row Address Lines		*/
+
+/* helper to determine the AM for a given size (SDRAM mode) */
+#define ORxS_SIZE_TO_AM(s) ((~((s) - 1)) & 0xffff8000)	/* must be pow of 2 */
+
+/*-----------------------------------------------------------------------
+ * ORx - Memory Controller: Option Register - GPCM Mode			10-18
+ */
+#define ORxG_AM_MSK	0xffff8000	/* Address Mask Mask		*/
+#define ORxG_BCTLD	0x00001000	/* Data Buffer Control Disable	*/
+#define ORxG_CSNT	0x00000800	/* Chip Select Negation Time	*/
+#define ORxG_ACS_MSK	0x00000600	/* Address to Chip Select Setup mask*/
+#define ORxG_SCY_MSK	0x000000f0	/* Cycle Lenght in Clocks	*/
+#define ORxG_SETA	0x00000008	/* External Access Termination	*/
+#define ORxG_TRLX	0x00000004	/* Timing Relaxed		*/
+#define ORxG_EHTR	0x00000002	/* Extended Hold Time on Read	*/
+
+#define ORxG_ACS_DIV1	0x00000000	/* CS is output at the same time*/
+#define ORxG_ACS_DIV4	0x00000400	/* CS is output 1/4 a clock later*/
+#define ORxG_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later*/
+
+#define ORxG_SCY_0_CLK	0x00000000	/*  0 clock cycles wait states	*/
+#define ORxG_SCY_1_CLK	0x00000010	/*  1 clock cycles wait states	*/
+#define ORxG_SCY_2_CLK	0x00000020	/*  2 clock cycles wait states	*/
+#define ORxG_SCY_3_CLK	0x00000030	/*  3 clock cycles wait states	*/
+#define ORxG_SCY_4_CLK	0x00000040	/*  4 clock cycles wait states	*/
+#define ORxG_SCY_5_CLK	0x00000050	/*  5 clock cycles wait states	*/
+#define ORxG_SCY_6_CLK	0x00000060	/*  6 clock cycles wait states	*/
+#define ORxG_SCY_7_CLK	0x00000070	/*  7 clock cycles wait states	*/
+#define ORxG_SCY_8_CLK	0x00000080	/*  8 clock cycles wait states	*/
+#define ORxG_SCY_9_CLK	0x00000090	/*  9 clock cycles wait states	*/
+#define ORxG_SCY_10_CLK	0x000000a0	/* 10 clock cycles wait states	*/
+#define ORxG_SCY_11_CLK	0x000000b0	/* 11 clock cycles wait states	*/
+#define ORxG_SCY_12_CLK	0x000000c0	/* 12 clock cycles wait states	*/
+#define ORxG_SCY_13_CLK	0x000000d0	/* 13 clock cycles wait states	*/
+#define ORxG_SCY_14_CLK	0x000000e0	/* 14 clock cycles wait states	*/
+#define ORxG_SCY_15_CLK	0x000000f0	/* 15 clock cycles wait states	*/
+
+/*-----------------------------------------------------------------------
+ * ORx - Memory Controller: Option Register - UPM Mode			10-20
+ */
+#define ORxU_AM_MSK	0xffff8000	/* Address Mask Mask		*/
+#define ORxU_BCTLD	0x00001000	/* Data Buffer Control Disable	*/
+#define ORxU_BI		0x00000100	/* Burst Inhibit		*/
+#define ORxU_EHTR_MSK	0x00000006	/* Extended Hold Time on Read Mask*/
+
+#define ORxU_EHTR_NORM	0x00000000	/* Normal Timing		*/
+#define ORxU_EHTR_1IDLE	0x00000002	/* One Idle Clock Cycle Inserted*/
+#define ORxU_EHTR_4IDLE	0x00000004	/* Four Idle Clock Cycles Inserted*/
+#define ORxU_EHTR_8IDLE	0x00000006	/* Eight Idle Clock Cycles Inserted*/
+
+
+/* helpers to convert values into an OR address mask (GPCM mode) */
+#define P2SZ_TO_AM(s)	((~((s) - 1)) & 0xffff8000)	/* must be pow of 2 */
+#define MEG_TO_AM(m)	P2SZ_TO_AM((m) << 20)
+
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x SDRAM Mode Register					10-21
+ */
+#define PSDMR_PBI	     0x80000000	/* Page-based Interleaving	*/
+#define PSDMR_RFEN	     0x40000000	/* Refresh Enable		*/
+#define PSDMR_OP_MSK	     0x38000000	/* SDRAM Operation Mask		*/
+#define PSDMR_SDAM_MSK	     0x07000000	/* SDRAM Address Multiplex Mask	*/
+#define PSDMR_BSMA_MSK	     0x00e00000	/* Bank Select Muxd Addr Line Mask*/
+#define PSDMR_SDA10_MSK	     0x001c0000	/* A10 Control Mask		*/
+#define PSDMR_RFRC_MSK	     0x00038000	/* Refresh Recovery Mask	*/
+#define PSDMR_PRETOACT_MSK   0x00007000	/* Precharge to Activate Intvl Mask*/
+#define PSDMR_ACTTORW_MSK    0x00000e00	/* Activate to Read/Write Intvl Mask*/
+#define PSDMR_BL	     0x00000100	/* Burst Length			*/
+#define PSDMR_LDOTOPRE_MSK   0x000000c0	/* Last Data Out to Precharge Mask*/
+#define PSDMR_WRC_MSK	     0x00000030	/* Write Recovery Time Mask	*/
+#define PSDMR_EAMUX	     0x00000008	/* External Address Multiplexing*/
+#define PSDMR_BUFCMD	     0x00000004	/* SDRAM ctl lines asrtd for 2 cycles*/
+#define PSDMR_CL_MSK	     0x00000003	/* CAS Latency Mask		*/
+
+#define PSDMR_OP_NORM	     0x00000000	/* Normal Operation		*/
+#define PSDMR_OP_CBRR	     0x08000000	/* CBR Refresh			*/
+#define PSDMR_OP_SELFR	     0x10000000	/* Self Refresh			*/
+#define PSDMR_OP_MRW	     0x18000000	/* Mode Register Write		*/
+#define PSDMR_OP_PREB	     0x20000000	/* Precharge Bank		*/
+#define PSDMR_OP_PREA	     0x28000000	/* Precharge All Banks		*/
+#define PSDMR_OP_ACTB	     0x30000000	/* Activate Bank		*/
+#define PSDMR_OP_RW	     0x38000000	/* Read/Write			*/
+
+#define PSDMR_SDAM_A13_IS_A5 0x00000000	/* SDRAM Address Multiplex A13 is A5 */
+#define PSDMR_SDAM_A14_IS_A5 0x01000000	/* SDRAM Address Multiplex A14 is A5 */
+#define PSDMR_SDAM_A15_IS_A5 0x02000000	/* SDRAM Address Multiplex A15 is A5 */
+#define PSDMR_SDAM_A16_IS_A5 0x03000000	/* SDRAM Address Multiplex A16 is A5 */
+#define PSDMR_SDAM_A17_IS_A5 0x04000000	/* SDRAM Address Multiplex A17 is A5 */
+#define PSDMR_SDAM_A18_IS_A5 0x05000000	/* SDRAM Address Multiplex A18 is A5 */
+
+#define PSDMR_BSMA_A12_A14   0x00000000	/* A12 - A14			*/
+#define PSDMR_BSMA_A13_A15   0x00200000	/* A13 - A15			*/
+#define PSDMR_BSMA_A14_A16   0x00400000	/* A14 - A16			*/
+#define PSDMR_BSMA_A15_A17   0x00600000	/* A15 - A17			*/
+#define PSDMR_BSMA_A16_A18   0x00800000	/* A16 - A18			*/
+#define PSDMR_BSMA_A17_A19   0x00a00000	/* A17 - A19			*/
+#define PSDMR_BSMA_A18_A20   0x00c00000	/* A18 - A20			*/
+#define PSDMR_BSMA_A19_A21   0x00e00000	/* A19 - A21			*/
+
+/* SDA10 values for xSDMR[PBI] = 0 */
+#define PSDMR_SDA10_PBI0_A12 0x00000000	/* "A10" Control is A12		*/
+#define PSDMR_SDA10_PBI0_A11 0x00040000	/* "A10" Control is A11		*/
+#define PSDMR_SDA10_PBI0_A10 0x00080000	/* "A10" Control is A10		*/
+#define PSDMR_SDA10_PBI0_A9  0x000c0000	/* "A10" Control is A9		*/
+#define PSDMR_SDA10_PBI0_A8  0x00100000	/* "A10" Control is A8		*/
+#define PSDMR_SDA10_PBI0_A7  0x00140000	/* "A10" Control is A7		*/
+#define PSDMR_SDA10_PBI0_A6  0x00180000	/* "A10" Control is A6		*/
+#define PSDMR_SDA10_PBI0_A5  0x001c0000	/* "A10" Control is A5		*/
+
+/* SDA10 values for xSDMR[PBI] = 1 */
+#define PSDMR_SDA10_PBI1_A10 0x00000000	/* "A10" Control is A10		*/
+#define PSDMR_SDA10_PBI1_A9  0x00040000	/* "A10" Control is A9		*/
+#define PSDMR_SDA10_PBI1_A8  0x00080000	/* "A10" Control is A8		*/
+#define PSDMR_SDA10_PBI1_A7  0x000c0000	/* "A10" Control is A7		*/
+#define PSDMR_SDA10_PBI1_A6  0x00100000	/* "A10" Control is A6		*/
+#define PSDMR_SDA10_PBI1_A5  0x00140000	/* "A10" Control is A5		*/
+#define PSDMR_SDA10_PBI1_A4  0x00180000	/* "A10" Control is A4		*/
+#define PSDMR_SDA10_PBI1_A3  0x001c0000	/* "A10" Control is A3		*/
+
+#define PSDMR_RFRC_3_CLK     0x00008000	/*  3 Clocks			*/
+#define PSDMR_RFRC_4_CLK     0x00010000	/*  4 Clocks			*/
+#define PSDMR_RFRC_5_CLK     0x00018000	/*  5 Clocks			*/
+#define PSDMR_RFRC_6_CLK     0x00020000	/*  6 Clocks			*/
+#define PSDMR_RFRC_7_CLK     0x00028000	/*  7 Clocks			*/
+#define PSDMR_RFRC_8_CLK     0x00030000	/*  8 Clocks			*/
+#define PSDMR_RFRC_16_CLK    0x00038000	/* 16 Clocks			*/
+
+#define PSDMR_PRETOACT_8W    0x00000000	/* 8 Clock-cycle Wait States	*/
+#define PSDMR_PRETOACT_1W    0x00001000	/* 1 Clock-cycle Wait States	*/
+#define PSDMR_PRETOACT_2W    0x00002000	/* 2 Clock-cycle Wait States	*/
+#define PSDMR_PRETOACT_3W    0x00003000	/* 3 Clock-cycle Wait States	*/
+#define PSDMR_PRETOACT_4W    0x00004000	/* 4 Clock-cycle Wait States	*/
+#define PSDMR_PRETOACT_5W    0x00005000	/* 5 Clock-cycle Wait States	*/
+#define PSDMR_PRETOACT_6W    0x00006000	/* 6 Clock-cycle Wait States	*/
+#define PSDMR_PRETOACT_7W    0x00007000	/* 7 Clock-cycle Wait States	*/
+
+#define PSDMR_ACTTORW_8W     0x00000000	/* 8 Clock-cycle Wait States	*/
+#define PSDMR_ACTTORW_1W     0x00000200	/* 1 Clock-cycle Wait States	*/
+#define PSDMR_ACTTORW_2W     0x00000400	/* 2 Clock-cycle Wait States	*/
+#define PSDMR_ACTTORW_3W     0x00000600	/* 3 Clock-cycle Wait States	*/
+#define PSDMR_ACTTORW_4W     0x00000800	/* 4 Clock-cycle Wait States	*/
+#define PSDMR_ACTTORW_5W     0x00000a00	/* 5 Clock-cycle Wait States	*/
+#define PSDMR_ACTTORW_6W     0x00000c00	/* 6 Clock-cycle Wait States	*/
+#define PSDMR_ACTTORW_7W     0x00000e00	/* 7 Clock-cycle Wait States	*/
+
+#define PSDMR_LDOTOPRE_0C    0x00000000	/* 0 Clock Cycles		*/
+#define PSDMR_LDOTOPRE_1C    0x00000040	/* 1 Clock Cycles		*/
+#define PSDMR_LDOTOPRE_2C    0x00000080	/* 2 Clock Cycles		*/
+
+#define PSDMR_WRC_4C	     0x00000000	/* 4 Clock Cycles		*/
+#define PSDMR_WRC_1C	     0x00000010	/* 1 Clock Cycles		*/
+#define PSDMR_WRC_2C	     0x00000020	/* 2 Clock Cycles		*/
+#define PSDMR_WRC_3C	     0x00000030	/* 3 Clock Cycles		*/
+
+#define PSDMR_CL_1	     0x00000001	/* CAS Latency = 1		*/
+#define PSDMR_CL_2	     0x00000002	/* CAS Latency = 2		*/
+#define PSDMR_CL_3	     0x00000003	/* CAS Latency = 3		*/
+
+/*-----------------------------------------------------------------------
+ * LSDMR - Local Bus SDRAM Mode Register			 	10-24
+ */
+
+/*
+ * No definitions here - the LSDMR has the same fields as the PSDMR.
+ */
+
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Refresh Timer Prescaler Register			10-32
+ * See User's Manual Errata for the changed definition (matches the
+ * 8xx now).  The wrong prescaler definition causes excessive refreshes
+ * (typically "divide by 2" when "divide by 32" is intended) which will
+ * cause unnecessary memory subsystem slowdown.
+ */
+#define MPTPR_PTP_MSK	0xff00		/* Periodic Timers Prescaler Mask */
+#define MPTPR_PTP_DIV2	0x2000		/* BRGCLK divided by 2		*/
+#define MPTPR_PTP_DIV4	0x1000		/* BRGCLK divided by 4		*/
+#define MPTPR_PTP_DIV8	0x0800		/* BRGCLK divided by 8		*/
+#define MPTPR_PTP_DIV16	0x0400		/* BRGCLK divided by 16		*/
+#define MPTPR_PTP_DIV32	0x0200		/* BRGCLK divided by 32		*/
+#define MPTPR_PTP_DIV64	0x0100		/* BRGCLK divided by 64		*/
+
+
+/*-----------------------------------------------------------------------
+ * TGCR1/TGCR2 - Timer Global Configuration Registers			17-4
+ */
+#define TGCR1_CAS2	0x80		/* Cascade Timer 1 and 2	*/
+#define TGCR1_STP2	0x20		/* Stop timer   2		*/
+#define TGCR1_RST2	0x10		/* Reset timer  2		*/
+#define TGCR1_GM1	0x08		/* Gate Mode for Pin 1		*/
+#define TGCR1_STP1	0x02		/* Stop timer   1		*/
+#define TGCR1_RST1	0x01		/* Reset timer  1		*/
+#define TGCR2_CAS4	0x80		/* Cascade Timer 3 and 4	*/
+#define TGCR2_STP4	0x20		/* Stop timer   4		*/
+#define TGCR2_RST4	0x10		/* Reset timer  4		*/
+#define TGCR2_GM2	0x08		/* Gate Mode for Pin 2		*/
+#define TGCR2_STP3	0x02		/* Stop timer   3		*/
+#define TGCR2_RST3	0x01		/* Reset timer  3		*/
+
+
+/*-----------------------------------------------------------------------
+ * TMR1-TMR4 - Timer Mode Registers					17-6
+ */
+#define TMRx_PS_MSK		0xff00	/* Prescaler Value 		*/
+#define TMRx_CE_MSK		0x00c0	/* Capture Edge and Enable Interrupt*/
+#define TMRx_OM			0x0020	/* Output Mode 			*/
+#define TMRx_ORI		0x0010	/* Output Reference Interrupt Enable*/
+#define TMRx_FRR		0x0008	/* Free Run/Restart 		*/
+#define TMRx_ICLK_MSK		0x0006	/* Timer Input Clock Source mask */
+#define TMRx_GE			0x0001	/* Gate Enable  		*/
+
+#define TMRx_CE_INTR_DIS	0x0000	/* Disable Interrupt on capture event*/
+#define TMRx_CE_RISING		0x0040	/* Capture on Rising TINx edge only */
+#define TMRx_CE_FALLING		0x0080	/* Capture on Falling TINx edge only */
+#define TMRx_CE_ANY		0x00c0	/* Capture on any TINx edge 	*/
+
+#define TMRx_ICLK_IN_CAS	0x0000	/* Internally cascaded input 	*/
+#define TMRx_ICLK_IN_GEN	0x0002	/* Internal General system clock*/
+#define TMRx_ICLK_IN_GEN_DIV16	0x0004	/* Internal General system clk div 16*/
+#define TMRx_ICLK_TIN_PIN	0x0006	/* TINx pin 			*/
+
+
+/*-----------------------------------------------------------------------
+ * CMXFCR - CMX FCC Clock Route Register				15-12
+ */
+#define CMXFCR_FC1	   0x40000000	/* FCC1 connection		*/
+#define CMXFCR_RF1CS_MSK   0x38000000	/* Receive FCC1 Clock Source Mask */
+#define CMXFCR_TF1CS_MSK   0x07000000	/* Transmit FCC1 Clock Source Mask */
+#define CMXFCR_FC2	   0x00400000	/* FCC2 connection		*/
+#define CMXFCR_RF2CS_MSK   0x00380000	/* Receive FCC2 Clock Source Mask */
+#define CMXFCR_TF2CS_MSK   0x00070000	/* Transmit FCC2 Clock Source Mask */
+#define CMXFCR_FC3	   0x00004000	/* FCC3 connection		*/
+#define CMXFCR_RF3CS_MSK   0x00003800	/* Receive FCC3 Clock Source Mask */
+#define CMXFCR_TF3CS_MSK   0x00000700	/* Transmit FCC3 Clock Source Mask */
+
+#define CMXFCR_RF1CS_BRG5  0x00000000	/* Receive FCC1 Clock Source is BRG5 */
+#define CMXFCR_RF1CS_BRG6  0x08000000	/* Receive FCC1 Clock Source is BRG6 */
+#define CMXFCR_RF1CS_BRG7  0x10000000	/* Receive FCC1 Clock Source is BRG7 */
+#define CMXFCR_RF1CS_BRG8  0x18000000	/* Receive FCC1 Clock Source is BRG8 */
+#define CMXFCR_RF1CS_CLK9  0x20000000	/* Receive FCC1 Clock Source is CLK9 */
+#define CMXFCR_RF1CS_CLK10 0x28000000	/* Receive FCC1 Clock Source is CLK10 */
+#define CMXFCR_RF1CS_CLK11 0x30000000	/* Receive FCC1 Clock Source is CLK11 */
+#define CMXFCR_RF1CS_CLK12 0x38000000	/* Receive FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_TF1CS_BRG5  0x00000000	/* Transmit FCC1 Clock Source is BRG5 */
+#define CMXFCR_TF1CS_BRG6  0x01000000	/* Transmit FCC1 Clock Source is BRG6 */
+#define CMXFCR_TF1CS_BRG7  0x02000000	/* Transmit FCC1 Clock Source is BRG7 */
+#define CMXFCR_TF1CS_BRG8  0x03000000	/* Transmit FCC1 Clock Source is BRG8 */
+#define CMXFCR_TF1CS_CLK9  0x04000000	/* Transmit FCC1 Clock Source is CLK9 */
+#define CMXFCR_TF1CS_CLK10 0x05000000	/* Transmit FCC1 Clock Source is CLK10 */
+#define CMXFCR_TF1CS_CLK11 0x06000000	/* Transmit FCC1 Clock Source is CLK11 */
+#define CMXFCR_TF1CS_CLK12 0x07000000	/* Transmit FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_RF2CS_BRG5  0x00000000	/* Receive FCC2 Clock Source is BRG5 */
+#define CMXFCR_RF2CS_BRG6  0x00080000	/* Receive FCC2 Clock Source is BRG6 */
+#define CMXFCR_RF2CS_BRG7  0x00100000	/* Receive FCC2 Clock Source is BRG7 */
+#define CMXFCR_RF2CS_BRG8  0x00180000	/* Receive FCC2 Clock Source is BRG8 */
+#define CMXFCR_RF2CS_CLK13 0x00200000	/* Receive FCC2 Clock Source is CLK13 */
+#define CMXFCR_RF2CS_CLK14 0x00280000	/* Receive FCC2 Clock Source is CLK14 */
+#define CMXFCR_RF2CS_CLK15 0x00300000	/* Receive FCC2 Clock Source is CLK15 */
+#define CMXFCR_RF2CS_CLK16 0x00380000	/* Receive FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_TF2CS_BRG5  0x00000000	/* Transmit FCC2 Clock Source is BRG5 */
+#define CMXFCR_TF2CS_BRG6  0x00010000	/* Transmit FCC2 Clock Source is BRG6 */
+#define CMXFCR_TF2CS_BRG7  0x00020000	/* Transmit FCC2 Clock Source is BRG7 */
+#define CMXFCR_TF2CS_BRG8  0x00030000	/* Transmit FCC2 Clock Source is BRG8 */
+#define CMXFCR_TF2CS_CLK13 0x00040000	/* Transmit FCC2 Clock Source is CLK13 */
+#define CMXFCR_TF2CS_CLK14 0x00050000	/* Transmit FCC2 Clock Source is CLK14 */
+#define CMXFCR_TF2CS_CLK15 0x00060000	/* Transmit FCC2 Clock Source is CLK15 */
+#define CMXFCR_TF2CS_CLK16 0x00070000	/* Transmit FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_RF3CS_BRG5  0x00000000	/* Receive FCC3 Clock Source is BRG5 */
+#define CMXFCR_RF3CS_BRG6  0x00000800	/* Receive FCC3 Clock Source is BRG6 */
+#define CMXFCR_RF3CS_BRG7  0x00001000	/* Receive FCC3 Clock Source is BRG7 */
+#define CMXFCR_RF3CS_BRG8  0x00001800	/* Receive FCC3 Clock Source is BRG8 */
+#define CMXFCR_RF3CS_CLK13 0x00002000	/* Receive FCC3 Clock Source is CLK13 */
+#define CMXFCR_RF3CS_CLK14 0x00002800	/* Receive FCC3 Clock Source is CLK14 */
+#define CMXFCR_RF3CS_CLK15 0x00003000	/* Receive FCC3 Clock Source is CLK15 */
+#define CMXFCR_RF3CS_CLK16 0x00003800	/* Receive FCC3 Clock Source is CLK16 */
+
+#define CMXFCR_TF3CS_BRG5  0x00000000	/* Transmit FCC3 Clock Source is BRG5 */
+#define CMXFCR_TF3CS_BRG6  0x00000100	/* Transmit FCC3 Clock Source is BRG6 */
+#define CMXFCR_TF3CS_BRG7  0x00000200	/* Transmit FCC3 Clock Source is BRG7 */
+#define CMXFCR_TF3CS_BRG8  0x00000300	/* Transmit FCC3 Clock Source is BRG8 */
+#define CMXFCR_TF3CS_CLK13 0x00000400	/* Transmit FCC3 Clock Source is CLK13 */
+#define CMXFCR_TF3CS_CLK14 0x00000500	/* Transmit FCC3 Clock Source is CLK14 */
+#define CMXFCR_TF3CS_CLK15 0x00000600	/* Transmit FCC3 Clock Source is CLK15 */
+#define CMXFCR_TF3CS_CLK16 0x00000700	/* Transmit FCC3 Clock Source is CLK16 */
+
+/*-----------------------------------------------------------------------
+ * CMXSCR - CMX SCC Clock Route Register				15-14
+ */
+#define CMXSCR_GR1	   0x80000000	/* Grant Support of SCC1	*/
+#define CMXSCR_SC1	   0x40000000	/* SCC1 connection		*/
+#define CMXSCR_RS1CS_MSK   0x38000000	/* Receive SCC1 Clock Source Mask */
+#define CMXSCR_TS1CS_MSK   0x07000000	/* Transmit SCC1 Clock Source Mask */
+#define CMXSCR_GR2	   0x00800000	/* Grant Support of SCC2	*/
+#define CMXSCR_SC2	   0x00400000	/* SCC2 connection		*/
+#define CMXSCR_RS2CS_MSK   0x00380000	/* Receive SCC2 Clock Source Mask */
+#define CMXSCR_TS2CS_MSK   0x00070000	/* Transmit SCC2 Clock Source Mask */
+#define CMXSCR_GR3	   0x00008000	/* Grant Support of SCC3	*/
+#define CMXSCR_SC3	   0x00004000	/* SCC3 connection		*/
+#define CMXSCR_RS3CS_MSK   0x00003800	/* Receive SCC3 Clock Source Mask */
+#define CMXSCR_TS3CS_MSK   0x00000700	/* Transmit SCC3 Clock Source Mask */
+#define CMXSCR_GR4	   0x00000080	/* Grant Support of SCC4	*/
+#define CMXSCR_SC4	   0x00000040	/* SCC4 connection		*/
+#define CMXSCR_RS4CS_MSK   0x00000038	/* Receive SCC4 Clock Source Mask */
+#define CMXSCR_TS4CS_MSK   0x00000007	/* Transmit SCC4 Clock Source Mask */
+
+#define CMXSCR_RS1CS_BRG1  0x00000000	/* SCC1 Rx Clock Source is BRG1 */
+#define CMXSCR_RS1CS_BRG2  0x08000000	/* SCC1 Rx Clock Source is BRG2 */
+#define CMXSCR_RS1CS_BRG3  0x10000000	/* SCC1 Rx Clock Source is BRG3 */
+#define CMXSCR_RS1CS_BRG4  0x18000000	/* SCC1 Rx Clock Source is BRG4 */
+#define CMXSCR_RS1CS_CLK11 0x20000000	/* SCC1 Rx Clock Source is CLK11 */
+#define CMXSCR_RS1CS_CLK12 0x28000000	/* SCC1 Rx Clock Source is CLK12 */
+#define CMXSCR_RS1CS_CLK3  0x30000000	/* SCC1 Rx Clock Source is CLK3 */
+#define CMXSCR_RS1CS_CLK4  0x38000000	/* SCC1 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS1CS_BRG1  0x00000000	/* SCC1 Tx Clock Source is BRG1 */
+#define CMXSCR_TS1CS_BRG2  0x01000000	/* SCC1 Tx Clock Source is BRG2 */
+#define CMXSCR_TS1CS_BRG3  0x02000000	/* SCC1 Tx Clock Source is BRG3 */
+#define CMXSCR_TS1CS_BRG4  0x03000000	/* SCC1 Tx Clock Source is BRG4 */
+#define CMXSCR_TS1CS_CLK11 0x04000000	/* SCC1 Tx Clock Source is CLK11 */
+#define CMXSCR_TS1CS_CLK12 0x05000000	/* SCC1 Tx Clock Source is CLK12 */
+#define CMXSCR_TS1CS_CLK3  0x06000000	/* SCC1 Tx Clock Source is CLK3 */
+#define CMXSCR_TS1CS_CLK4  0x07000000	/* SCC1 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS2CS_BRG1  0x00000000	/* SCC2 Rx Clock Source is BRG1 */
+#define CMXSCR_RS2CS_BRG2  0x00080000	/* SCC2 Rx Clock Source is BRG2 */
+#define CMXSCR_RS2CS_BRG3  0x00100000	/* SCC2 Rx Clock Source is BRG3 */
+#define CMXSCR_RS2CS_BRG4  0x00180000	/* SCC2 Rx Clock Source is BRG4 */
+#define CMXSCR_RS2CS_CLK11 0x00200000	/* SCC2 Rx Clock Source is CLK11 */
+#define CMXSCR_RS2CS_CLK12 0x00280000	/* SCC2 Rx Clock Source is CLK12 */
+#define CMXSCR_RS2CS_CLK3  0x00300000	/* SCC2 Rx Clock Source is CLK3 */
+#define CMXSCR_RS2CS_CLK4  0x00380000	/* SCC2 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS2CS_BRG1  0x00000000	/* SCC2 Tx Clock Source is BRG1 */
+#define CMXSCR_TS2CS_BRG2  0x00010000	/* SCC2 Tx Clock Source is BRG2 */
+#define CMXSCR_TS2CS_BRG3  0x00020000	/* SCC2 Tx Clock Source is BRG3 */
+#define CMXSCR_TS2CS_BRG4  0x00030000	/* SCC2 Tx Clock Source is BRG4 */
+#define CMXSCR_TS2CS_CLK11 0x00040000	/* SCC2 Tx Clock Source is CLK11 */
+#define CMXSCR_TS2CS_CLK12 0x00050000	/* SCC2 Tx Clock Source is CLK12 */
+#define CMXSCR_TS2CS_CLK3  0x00060000	/* SCC2 Tx Clock Source is CLK3 */
+#define CMXSCR_TS2CS_CLK4  0x00070000	/* SCC2 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS3CS_BRG1  0x00000000	/* SCC3 Rx Clock Source is BRG1 */
+#define CMXSCR_RS3CS_BRG2  0x00000800	/* SCC3 Rx Clock Source is BRG2 */
+#define CMXSCR_RS3CS_BRG3  0x00001000	/* SCC3 Rx Clock Source is BRG3 */
+#define CMXSCR_RS3CS_BRG4  0x00001800	/* SCC3 Rx Clock Source is BRG4 */
+#define CMXSCR_RS3CS_CLK5  0x00002000	/* SCC3 Rx Clock Source is CLK5 */
+#define CMXSCR_RS3CS_CLK6  0x00002800	/* SCC3 Rx Clock Source is CLK6 */
+#define CMXSCR_RS3CS_CLK7  0x00003000	/* SCC3 Rx Clock Source is CLK7 */
+#define CMXSCR_RS3CS_CLK8  0x00003800	/* SCC3 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS3CS_BRG1  0x00000000	/* SCC3 Tx Clock Source is BRG1 */
+#define CMXSCR_TS3CS_BRG2  0x00000100	/* SCC3 Tx Clock Source is BRG2 */
+#define CMXSCR_TS3CS_BRG3  0x00000200	/* SCC3 Tx Clock Source is BRG3 */
+#define CMXSCR_TS3CS_BRG4  0x00000300	/* SCC3 Tx Clock Source is BRG4 */
+#define CMXSCR_TS3CS_CLK5  0x00000400	/* SCC3 Tx Clock Source is CLK5 */
+#define CMXSCR_TS3CS_CLK6  0x00000500	/* SCC3 Tx Clock Source is CLK6 */
+#define CMXSCR_TS3CS_CLK7  0x00000600	/* SCC3 Tx Clock Source is CLK7 */
+#define CMXSCR_TS3CS_CLK8  0x00000700	/* SCC3 Tx Clock Source is CLK8 */
+
+#define CMXSCR_RS4CS_BRG1  0x00000000	/* SCC4 Rx Clock Source is BRG1 */
+#define CMXSCR_RS4CS_BRG2  0x00000008	/* SCC4 Rx Clock Source is BRG2 */
+#define CMXSCR_RS4CS_BRG3  0x00000010	/* SCC4 Rx Clock Source is BRG3 */
+#define CMXSCR_RS4CS_BRG4  0x00000018	/* SCC4 Rx Clock Source is BRG4 */
+#define CMXSCR_RS4CS_CLK5  0x00000020	/* SCC4 Rx Clock Source is CLK5 */
+#define CMXSCR_RS4CS_CLK6  0x00000028	/* SCC4 Rx Clock Source is CLK6 */
+#define CMXSCR_RS4CS_CLK7  0x00000030	/* SCC4 Rx Clock Source is CLK7 */
+#define CMXSCR_RS4CS_CLK8  0x00000038	/* SCC4 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS4CS_BRG1  0x00000000	/* SCC4 Tx Clock Source is BRG1 */
+#define CMXSCR_TS4CS_BRG2  0x00000001	/* SCC4 Tx Clock Source is BRG2 */
+#define CMXSCR_TS4CS_BRG3  0x00000002	/* SCC4 Tx Clock Source is BRG3 */
+#define CMXSCR_TS4CS_BRG4  0x00000003	/* SCC4 Tx Clock Source is BRG4 */
+#define CMXSCR_TS4CS_CLK5  0x00000004	/* SCC4 Tx Clock Source is CLK5 */
+#define CMXSCR_TS4CS_CLK6  0x00000005	/* SCC4 Tx Clock Source is CLK6 */
+#define CMXSCR_TS4CS_CLK7  0x00000006	/* SCC4 Tx Clock Source is CLK7 */
+#define CMXSCR_TS4CS_CLK8  0x00000007	/* SCC4 Tx Clock Source is CLK8 */
+
+/*-----------------------------------------------------------------------
+ * CMXSMR - CMX SMC Clock Route Register				15-17
+ */
+#define CMXSMR_SMC1	    0x80	/* SMC1 Connection		*/
+#define CMXSMR_SMC1CS_MSK   0x30	/* SMC1 Clock Source		*/
+#define CMXSMR_SMC2	    0x08	/* SMC2 Connection		*/
+#define CMXSMR_SMC2CS_MSK   0x03	/* SMC2 Clock Source		*/
+
+#define CMXSMR_SMC1CS_BRG1  0x00	/* SMC1 Tx and Rx Clocks are BRG1 */
+#define CMXSMR_SMC1CS_BRG7  0x10	/* SMC1 Tx and Rx Clocks are BRG7 */
+#define CMXSMR_SMC1CS_CLK7  0x20	/* SMC1 Tx and Rx Clocks are CLK7 */
+#define CMXSMR_SMC1CS_CLK9  0x30	/* SMC1 Tx and Rx Clocks are CLK9 */
+
+#define CMXSMR_SMC2CS_BRG2  0x00	/* SMC2 Tx and Rx Clocks are BRG2 */
+#define CMXSMR_SMC2CS_BRG8  0x01	/* SMC2 Tx and Rx Clocks are BRG8 */
+#define CMXSMR_SMC2CS_CLK19 0x02	/* SMC2 Tx and Rx Clocks are CLK19 */
+#define CMXSMR_SMC2CS_CLK20 0x03	/* SMC2 Tx and Rx Clocks are CLK20 */
+
+/*-----------------------------------------------------------------------
+ * miscellaneous
+ */
+
+#define UPMA			1
+#define UPMB			2
+#define UPMC			3
+
+#if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG)
+extern __inline__ void
+reset_8260_watchdog(volatile immap_t *immr)
+{
+    immr->im_siu_conf.sc_swsr = 0x556c;
+    immr->im_siu_conf.sc_swsr = 0xaa39;
+}
+#endif /* !__ASSEMBLY && CONFIG_WATCHDOG */
+
+#endif	/* __MPC8260_H__ */
diff --git a/include/mpc8260_irq.h b/include/mpc8260_irq.h
new file mode 100755
index 0000000..9bee9a3
--- /dev/null
+++ b/include/mpc8260_irq.h
@@ -0,0 +1,48 @@
+#ifndef _MPC8260_IRQ_H
+#define _MPC8260_IRQ_H
+
+/****************************************************************************/
+/* most of this was ripped out of include/asm-ppc/irq.h from the Linux/PPC  */
+/* source. There was no copyright information in the file.		    */
+
+/*
+ * this is the # irq's for all ppc arch's (pmac/chrp/prep)
+ * so it is the max of them all
+ *
+ * [let's just worry about 8260 for now - mjj]
+ */
+#define NR_IRQS			64
+
+/* The 8260 has an internal interrupt controller with a maximum of
+ * 64 IRQs.  We will use NR_IRQs from above since it is large enough.
+ * Don't be confused by the 8260 documentation where they list an
+ * "interrupt number" and "interrupt vector".  We are only interested
+ * in the interrupt vector.  There are "reserved" holes where the
+ * vector number increases, but the interrupt number in the table does not.
+ * (Document errata updates have fixed this...make sure you have up to
+ * date processor documentation -- Dan).
+ */
+#define NR_SIU_INTS	64
+
+/* There are many more than these, we will add them as we need them.
+*/
+#define	SIU_INT_SMC1		((uint)0x04)
+#define	SIU_INT_SMC2		((uint)0x05)
+#define	SIU_INT_IRQ1		((uint)0x13)
+#define	SIU_INT_IRQ2		((uint)0x14)
+#define	SIU_INT_IRQ3		((uint)0x15)
+#define	SIU_INT_IRQ4		((uint)0x16)
+#define	SIU_INT_IRQ5		((uint)0x17)
+#define	SIU_INT_IRQ6		((uint)0x18)
+#define	SIU_INT_IRQ7		((uint)0x19)
+#define	SIU_INT_FCC1		((uint)0x20)
+#define	SIU_INT_FCC2		((uint)0x21)
+#define	SIU_INT_FCC3		((uint)0x22)
+#define	SIU_INT_SCC1		((uint)0x28)
+#define	SIU_INT_SCC2		((uint)0x29)
+#define	SIU_INT_SCC3		((uint)0x2a)
+#define	SIU_INT_SCC4		((uint)0x2b)
+
+#define NR_MASK_WORDS	((NR_IRQS + 31) / 32)
+
+#endif /* _MPC8260_IRQ_H */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
new file mode 100755
index 0000000..ea40bad
--- /dev/null
+++ b/include/mpc83xx.h
@@ -0,0 +1,313 @@
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc83xx.h
+ *
+ * MPC83xx specific definitions
+ */
+
+#ifndef __MPC83XX_H__
+#define __MPC83XX_H__
+
+#if defined(CONFIG_E300)
+#include <asm/e300.h>
+#endif
+
+/*
+ * MPC83xx cpu provide RCR register to do reset thing specially. easier
+ * to implement
+ */
+
+#define MPC83xx_RESET
+
+/*
+ * System reset offset (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET	0x0100
+
+/*
+ * Default Internal Memory Register Space (Freescale recomandation)
+ */
+#define CONFIG_DEFAULT_IMMR 0xFF400000
+
+/*
+ * Watchdog
+ */
+#define SWCRR      0x0204
+#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
+#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
+#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */
+#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
+#define SWCRR_RES  ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+
+#define SWCNR      0x0208
+#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
+#define SWCNR_RES  ~(SWCNR_SWCN)
+
+#define SWSRR      0x020E
+
+/*
+ * Default Internal Memory Register Space (Freescale recomandation)
+ */
+#define IMMRBAR 0x0000
+#define IMMRBAR_BASE_ADDR     0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */
+#define IMMRBAR_RES           ~(IMMRBAR_BASE_ADDR)
+
+/*
+ * Default Internal Memory Register Space (Freescale recomandation)
+ */
+#define LBLAWBAR0 0x0020
+#define LBLAWAR0  0x0024
+#define LBLAWBAR1 0x0028
+#define LBLAWAR1  0x002C
+#define LBLAWBAR2 0x0030
+#define LBLAWAR2  0x0034
+#define LBLAWBAR3 0x0038
+#define LBLAWAR3  0x003C
+
+
+/*
+ * Base Registers & Option Registers
+ */
+#define BR0 0x5000
+#define BR1 0x5008
+#define BR2 0x5010
+#define BR3 0x5018
+#define BR4 0x5020
+#define BR5 0x5028
+#define BR6 0x5030
+#define BR7 0x5038
+
+#define BR_BA		0xFFFF8000
+#define BR_BA_SHIFT		15
+#define BR_PS		0x00001800
+#define BR_PS_SHIFT		11
+#define BR_PS_8		0x00000800  /* Port Size 8 bit */
+#define BR_PS_16	0x00001000  /* Port Size 16 bit */
+#define BR_PS_32	0x00001800  /* Port Size 32 bit */
+#define BR_DECC		0x00000600
+#define BR_DECC_SHIFT		 9
+#define BR_WP		0x00000100
+#define BR_WP_SHIFT		 8
+#define BR_MSEL		0x000000E0
+#define BR_MSEL_SHIFT		 5
+#define BR_MS_GPCM	0x00000000  /* GPCM */
+#define BR_MS_SDRAM	0x00000060  /* SDRAM */
+#define BR_MS_UPMA	0x00000080  /* UPMA */
+#define BR_MS_UPMB	0x000000A0  /* UPMB */
+#define BR_MS_UPMC	0x000000C0  /* UPMC */
+#define BR_V		0x00000001
+#define BR_V_SHIFT		 0
+#define BR_RES		~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
+
+#define OR0 0x5004
+#define OR1 0x500C
+#define OR2 0x5014
+#define OR3 0x501C
+#define OR4 0x5024
+#define OR5 0x502C
+#define OR6 0x5034
+#define OR7 0x503C
+
+#define OR_GPCM_AM		0xFFFF8000
+#define OR_GPCM_AM_SHIFT		15
+#define OR_GPCM_BCTLD		0x00001000
+#define OR_GPCM_BCTLD_SHIFT		12
+#define OR_GPCM_CSNT		0x00000800
+#define OR_GPCM_CSNT_SHIFT		11
+#define OR_GPCM_ACS		0x00000600
+#define OR_GPCM_ACS_SHIFT		 9
+#define OR_GPCM_ACS_0b10	0x00000400
+#define OR_GPCM_ACS_0b11	0x00000600
+#define OR_GPCM_XACS		0x00000100
+#define OR_GPCM_XACS_SHIFT		 8
+#define OR_GPCM_SCY		0x000000F0
+#define OR_GPCM_SCY_SHIFT		 4
+#define OR_GPCM_SCY_1		0x00000010
+#define OR_GPCM_SCY_2		0x00000020
+#define OR_GPCM_SCY_3		0x00000030
+#define OR_GPCM_SCY_4		0x00000040
+#define OR_GPCM_SCY_5		0x00000050
+#define OR_GPCM_SCY_6		0x00000060
+#define OR_GPCM_SCY_7		0x00000070
+#define OR_GPCM_SCY_8		0x00000080
+#define OR_GPCM_SCY_9		0x00000090
+#define OR_GPCM_SCY_10		0x000000a0
+#define OR_GPCM_SCY_11		0x000000b0
+#define OR_GPCM_SCY_12		0x000000c0
+#define OR_GPCM_SCY_13		0x000000d0
+#define OR_GPCM_SCY_14		0x000000e0
+#define OR_GPCM_SCY_15		0x000000f0
+#define OR_GPCM_SETA		0x00000008
+#define OR_GPCM_SETA_SHIFT		 3
+#define OR_GPCM_TRLX		0x00000004
+#define OR_GPCM_TRLX_SHIFT		 2
+#define OR_GPCM_EHTR		0x00000002
+#define OR_GPCM_EHTR_SHIFT		 1
+#define OR_GPCM_EAD		0x00000001
+#define OR_GPCM_EAD_SHIFT		 0
+
+#define OR_UPM_AM    0xFFFF8000
+#define OR_UPM_AM_SHIFT      15
+#define OR_UPM_XAM   0x00006000
+#define OR_UPM_XAM_SHIFT     13
+#define OR_UPM_BCTLD 0x00001000
+#define OR_UPM_BCTLD_SHIFT   12
+#define OR_UPM_BI    0x00000100
+#define OR_UPM_BI_SHIFT       8
+#define OR_UPM_TRLX  0x00000004
+#define OR_UPM_TRLX_SHIFT     2
+#define OR_UPM_EHTR  0x00000002
+#define OR_UPM_EHTR_SHIFT     1
+#define OR_UPM_EAD   0x00000001
+#define OR_UPM_EAD_SHIFT      0
+
+#define OR_SDRAM_AM    0xFFFF8000
+#define OR_SDRAM_AM_SHIFT      15
+#define OR_SDRAM_XAM   0x00006000
+#define OR_SDRAM_XAM_SHIFT     13
+#define OR_SDRAM_COLS  0x00001C00
+#define OR_SDRAM_COLS_SHIFT    10
+#define OR_SDRAM_ROWS  0x000001C0
+#define OR_SDRAM_ROWS_SHIFT     6
+#define OR_SDRAM_PMSEL 0x00000020
+#define OR_SDRAM_PMSEL_SHIFT    5
+#define OR_SDRAM_EAD   0x00000001
+#define OR_SDRAM_EAD_SHIFT      0
+
+/*
+ * Hard Reset Configration Word - High
+ */
+#define HRCWH_PCI_AGENT              0x00000000
+#define HRCWH_PCI_HOST               0x80000000
+
+#define HRCWH_32_BIT_PCI             0x00000000
+#define HRCWH_64_BIT_PCI             0x40000000
+
+#define HRCWH_PCI1_ARBITER_DISABLE   0x00000000
+#define HRCWH_PCI1_ARBITER_ENABLE    0x20000000
+
+#define HRCWH_PCI2_ARBITER_DISABLE   0x00000000
+#define HRCWH_PCI2_ARBITER_ENABLE    0x10000000
+
+#define HRCWH_CORE_DISABLE           0x08000000
+#define HRCWH_CORE_ENABLE            0x00000000
+
+#define HRCWH_FROM_0X00000100        0x00000000
+#define HRCWH_FROM_0XFFF00100        0x04000000
+
+#define HRCWH_BOOTSEQ_DISABLE        0x00000000
+#define HRCWH_BOOTSEQ_NORMAL         0x01000000
+#define HRCWH_BOOTSEQ_EXTENDED       0x02000000
+
+#define HRCWH_SW_WATCHDOG_DISABLE    0x00000000
+#define HRCWH_SW_WATCHDOG_ENABLE     0x00800000
+
+#define HRCWH_ROM_LOC_DDR_SDRAM      0x00000000
+#define HRCWH_ROM_LOC_PCI1           0x00100000
+#define HRCWH_ROM_LOC_PCI2           0x00200000
+#define HRCWH_ROM_LOC_LOCAL_8BIT     0x00500000
+#define HRCWH_ROM_LOC_LOCAL_16BIT    0x00600000
+#define HRCWH_ROM_LOC_LOCAL_32BIT    0x00700000
+
+#define HRCWH_TSEC1M_IN_RGMII        0x00000000
+#define HRCWH_TSEC1M_IN_RTBI         0x00004000
+#define HRCWH_TSEC1M_IN_GMII         0x00008000
+#define HRCWH_TSEC1M_IN_TBI          0x0000C000
+
+#define HRCWH_TSEC2M_IN_RGMII        0x00000000
+#define HRCWH_TSEC2M_IN_RTBI         0x00001000
+#define HRCWH_TSEC2M_IN_GMII         0x00002000
+#define HRCWH_TSEC2M_IN_TBI          0x00003000
+
+#define HRCWH_BIG_ENDIAN             0x00000000
+#define HRCWH_LITTLE_ENDIAN          0x00000008
+
+/*
+ * Hard Reset Configration Word - Low
+ */
+#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
+#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
+
+#define HRCWL_DDR_TO_SCB_CLK_1X1     0x00000000
+#define HRCWL_DDR_TO_SCB_CLK_2X1     0x40000000
+
+#define HRCWL_CSB_TO_CLKIN_16X1      0x00000000
+#define HRCWL_CSB_TO_CLKIN_1X1       0x01000000
+#define HRCWL_CSB_TO_CLKIN_2X1       0x02000000
+#define HRCWL_CSB_TO_CLKIN_3X1       0x03000000
+#define HRCWL_CSB_TO_CLKIN_4X1       0x04000000
+#define HRCWL_CSB_TO_CLKIN_5X1       0x05000000
+#define HRCWL_CSB_TO_CLKIN_6X1       0x06000000
+#define HRCWL_CSB_TO_CLKIN_7X1       0x07000000
+#define HRCWL_CSB_TO_CLKIN_8X1       0x08000000
+#define HRCWL_CSB_TO_CLKIN_9X1       0x09000000
+#define HRCWL_CSB_TO_CLKIN_10X1      0x0A000000
+#define HRCWL_CSB_TO_CLKIN_11X1      0x0B000000
+#define HRCWL_CSB_TO_CLKIN_12X1      0x0C000000
+#define HRCWL_CSB_TO_CLKIN_13X1      0x0D000000
+#define HRCWL_CSB_TO_CLKIN_14X1      0x0E000000
+#define HRCWL_CSB_TO_CLKIN_15X1      0x0F000000
+
+#define HRCWL_VCO_BYPASS             0x00000000
+#define HRCWL_VCO_1X2                0x00000000
+#define HRCWL_VCO_1X4                0x00200000
+#define HRCWL_VCO_1X8                0x00400000
+
+#define HRCWL_CORE_TO_CSB_BYPASS     0x00000000
+#define HRCWL_CORE_TO_CSB_1X1        0x00020000
+#define HRCWL_CORE_TO_CSB_1_5X1      0x00030000
+#define HRCWL_CORE_TO_CSB_2X1        0x00040000
+#define HRCWL_CORE_TO_CSB_2_5X1      0x00050000
+#define HRCWL_CORE_TO_CSB_3X1        0x00060000
+
+/*
+ * LCRR - Clock Ratio Register (10.3.1.16)
+ */
+#define LCRR_DBYP      0x80000000
+#define LCRR_DBYP_SHIFT        31
+#define LCRR_BUFCMDC   0x30000000
+#define LCRR_BUFCMDC_1 0x10000000
+#define LCRR_BUFCMDC_2 0x20000000
+#define LCRR_BUFCMDC_3 0x30000000
+#define LCRR_BUFCMDC_4 0x00000000
+#define LCRR_BUFCMDC_SHIFT     28
+#define LCRR_ECL       0x03000000
+#define LCRR_ECL_4     0x00000000
+#define LCRR_ECL_5     0x01000000
+#define LCRR_ECL_6     0x02000000
+#define LCRR_ECL_7     0x03000000
+#define LCRR_ECL_SHIFT         24
+#define LCRR_EADC      0x00030000
+#define LCRR_EADC_1    0x00010000
+#define LCRR_EADC_2    0x00020000
+#define LCRR_EADC_3    0x00030000
+#define LCRR_EADC_4    0x00000000
+#define LCRR_EADC_SHIFT        16
+#define LCRR_CLKDIV    0x0000000F
+#define LCRR_CLKDIV_2  0x00000002
+#define LCRR_CLKDIV_4  0x00000004
+#define LCRR_CLKDIV_8  0x00000008
+#define LCRR_CLKDIV_SHIFT       0
+
+#endif	/* __MPC83XX_H__ */
diff --git a/include/mpc85xx.h b/include/mpc85xx.h
new file mode 100755
index 0000000..60b6c61
--- /dev/null
+++ b/include/mpc85xx.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright(c) 2003 Motorola Inc.
+ * Xianghua Xiao (x.xiao@motorola.com)
+ */
+
+#ifndef	__MPC85xx_H__
+#define __MPC85xx_H__
+
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset	*/
+
+#if defined(CONFIG_E500)
+#include <e500.h>
+#endif
+
+/*
+ * SCCR - System Clock Control Register, 9-8
+ */
+#define SCCR_CLPD       0x00000004      /* CPM Low Power Disable */
+#define SCCR_DFBRG_MSK  0x00000003      /* Division by BRGCLK Mask */
+#define SCCR_DFBRG_SHIFT 0
+
+#define SCCR_DFBRG00    0x00000000      /* BRGCLK division by 4 */
+#define SCCR_DFBRG01    0x00000001      /* BRGCLK div by 16 (normal) */
+#define SCCR_DFBRG10    0x00000002      /* BRGCLK division by 64 */
+#define SCCR_DFBRG11    0x00000003      /* BRGCLK division by 256 */
+
+#endif	/* __MPC85xx_H__ */
diff --git a/include/mpc8xx.h b/include/mpc8xx.h
new file mode 100755
index 0000000..2911758
--- /dev/null
+++ b/include/mpc8xx.h
@@ -0,0 +1,634 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mpc8xx.h
+ *
+ * MPC8xx specific definitions
+ */
+
+#ifndef __MPCXX_H__
+#define __MPCXX_H__
+
+
+/*-----------------------------------------------------------------------
+ * Exception offsets (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control Register				11-9
+ */
+#define SYPCR_SWTC	0xFFFF0000	/* Software Watchdog Timer Count	*/
+#define SYPCR_BMT	0x0000FF00	/* Bus Monitor Timing			*/
+#define SYPCR_BME	0x00000080	/* Bus Monitor Enable			*/
+#define SYPCR_SWF	0x00000008	/* Software Watchdog Freeze		*/
+#define SYPCR_SWE	0x00000004	/* Software Watchdog Enable		*/
+#define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Select	*/
+#define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale		*/
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register				11-6
+ */
+#define SIUMCR_EARB	0x80000000	/* External Arbitration			*/
+#define SIUMCR_EARP0	0x00000000	/* External Arbi. Request priority 0	*/
+#define SIUMCR_EARP1	0x10000000	/* External Arbi. Request priority 1	*/
+#define SIUMCR_EARP2	0x20000000	/* External Arbi. Request priority 2	*/
+#define SIUMCR_EARP3	0x30000000	/* External Arbi. Request priority 3	*/
+#define SIUMCR_EARP4	0x40000000	/* External Arbi. Request priority 4	*/
+#define SIUMCR_EARP5	0x50000000	/* External Arbi. Request priority 5	*/
+#define SIUMCR_EARP6	0x60000000	/* External Arbi. Request priority 6	*/
+#define SIUMCR_EARP7	0x70000000	/* External Arbi. Request priority 7	*/
+#define SIUMCR_DSHW	0x00800000	/* Data Showcycles			*/
+#define SIUMCR_DBGC00	0x00000000	/* Debug pins configuration		*/
+#define SIUMCR_DBGC01	0x00200000	/* - " -				*/
+#define SIUMCR_DBGC10	0x00400000	/* - " -				*/
+#define SIUMCR_DBGC11	0x00600000	/* - " -				*/
+#define SIUMCR_DBPC00	0x00000000	/* Debug Port pins Config.		*/
+#define SIUMCR_DBPC01	0x00080000	/* - " -				*/
+#define SIUMCR_DBPC10	0x00100000	/* - " -				*/
+#define SIUMCR_DBPC11	0x00180000	/* - " -				*/
+#define SIUMCR_FRC	0x00020000	/* FRZ pin Configuration		*/
+#define SIUMCR_DLK	0x00010000	/* Debug Register Lock			*/
+#define SIUMCR_PNCS	0x00008000	/* Parity Non-mem Crtl reg		*/
+#define SIUMCR_OPAR	0x00004000	/* Odd Parity				*/
+#define SIUMCR_DPC	0x00002000	/* Data Parity pins Config.		*/
+#define SIUMCR_MPRE	0x00001000	/* Multi CPU Reserva. Enable		*/
+#define SIUMCR_MLRC00	0x00000000	/* Multi Level Reserva. Ctrl		*/
+#define SIUMCR_MLRC01	0x00000400	/* - " -				*/
+#define SIUMCR_MLRC10	0x00000800	/* - " -				*/
+#define SIUMCR_MLRC11	0x00000C00	/* - " -				*/
+#define SIUMCR_AEME	0x00000200	/* Asynchro External Master		*/
+#define SIUMCR_SEME	0x00000100	/* Synchro External Master		*/
+#define SIUMCR_BSC	0x00000080	/* Byte Select Configuration		*/
+#define SIUMCR_GB5E	0x00000040	/* GPL_B(5) Enable			*/
+#define SIUMCR_B2DD	0x00000020	/* Bank 2 Double Drive			*/
+#define SIUMCR_B3DD	0x00000010	/* Bank 3 Double Drive			*/
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control Register			11-26
+ */
+#define TBSCR_TBIRQ7	0x8000		/* Time Base Interrupt Request 7	*/
+#define TBSCR_TBIRQ6	0x4000		/* Time Base Interrupt Request 6	*/
+#define TBSCR_TBIRQ5	0x2000		/* Time Base Interrupt Request 5	*/
+#define TBSCR_TBIRQ4	0x1000		/* Time Base Interrupt Request 4	*/
+#define TBSCR_TBIRQ3	0x0800		/* Time Base Interrupt Request 3	*/
+#define TBSCR_TBIRQ2	0x0400		/* Time Base Interrupt Request 2	*/
+#define TBSCR_TBIRQ1	0x0200		/* Time Base Interrupt Request 1	*/
+#define TBSCR_TBIRQ0	0x0100		/* Time Base Interrupt Request 0	*/
+#if 0	/* already in asm/8xx_immap.h */
+#define TBSCR_REFA	0x0080		/* Reference Interrupt Status A		*/
+#define TBSCR_REFB	0x0040		/* Reference Interrupt Status B		*/
+#define TBSCR_REFAE	0x0008		/* Second Interrupt Enable A		*/
+#define TBSCR_REFBE	0x0004		/* Second Interrupt Enable B		*/
+#define TBSCR_TBF	0x0002		/* Time Base Freeze			*/
+#define TBSCR_TBE	0x0001		/* Time Base Enable			*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control Register		11-31
+ */
+#undef	PISCR_PIRQ			/* TBD					*/
+#define PISCR_PITF	0x0002		/* Periodic Interrupt Timer Freeze	*/
+#if 0	/* already in asm/8xx_immap.h */
+#define PISCR_PS	0x0080		/* Periodic interrupt Status		*/
+#define PISCR_PIE	0x0004		/* Periodic Interrupt Enable		*/
+#define PISCR_PTE	0x0001		/* Periodic Timer Enable		*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * RSR - Reset Status Register						 5-4
+ */
+#define RSR_JTRS	0x01000000	/* JTAG Reset Status		*/
+#define RSR_DBSRS	0x02000000	/* Debug Port Soft Reset Status */
+#define RSR_DBHRS	0x04000000	/* Debug Port Hard Reset Status */
+#define RSR_CSRS	0x08000000	/* Check Stop Reset Status	*/
+#define RSR_SWRS	0x10000000	/* Software Watchdog Reset Status*/
+#define RSR_LLRS	0x20000000	/* Loss-of-Lock Reset Status	*/
+#define RSR_ESRS	0x40000000	/* External Soft Reset Status	*/
+#define RSR_EHRS	0x80000000	/* External Hard Reset Status	*/
+
+#define RSR_ALLBITS	(RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS)
+
+/*-----------------------------------------------------------------------
+ * Newer chips (MPC866 family and MPC87x/88x family) have different
+ * clock distribution system. Their IMMR lower half is >= 0x0800
+ */
+#define MPC8xx_NEW_CLK 0x0800
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register			15-30
+ */
+/* Newer chips (MPC866/87x/88x et al) defines */
+#define PLPRCR_MFN_MSK	0xF8000000	/* Multiplication factor numerator bits */
+#define PLPRCR_MFN_SHIFT	27	/* Multiplication factor numerator shift*/
+#define PLPRCR_MFD_MSK	0x07C00000	/* Multiplication factor denominator bits */
+#define PLPRCR_MFD_SHIFT	22	/* Multiplication factor denominator shift*/
+#define PLPRCR_S_MSK	0x00300000	/* Multiplication factor integer bits	*/
+#define PLPRCR_S_SHIFT		20	/* Multiplication factor integer shift	*/
+#define PLPRCR_MFI_MSK	0x000F0000	/* Multiplication factor integer bits	*/
+#define PLPRCR_MFI_SHIFT	16	/* Multiplication factor integer shift	*/
+
+#define PLPRCR_PDF_MSK	0x0000001E	/* Predivision Factor bits		*/
+#define PLPRCR_PDF_SHIFT	 1	/* Predivision Factor shift value	*/
+#define PLPRCR_DBRMO	0x00000001	/* DPLL BRM Order bit			*/
+
+/* Multiplication factor + PDF bits */
+#define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \
+			  PLPRCR_MFD_MSK | \
+			  PLPRCR_S_MSK	 | \
+			  PLPRCR_MFI_MSK | \
+			  PLPRCR_PDF_MSK)
+
+/* Older chips (MPC860/862 et al) defines */
+#define PLPRCR_MF_MSK	0xFFF00000	/* Multiplication factor bits		*/
+#define PLPRCR_MF_SHIFT		20	/* Multiplication factor shift value	*/
+
+#define PLPRCR_SPLSS	0x00008000	/* SPLL Lock Status Sticky bit		*/
+#define PLPRCR_TMIST	0x00001000	/* Timers Interrupt Status		*/
+
+#define PLPRCR_LPM_MSK	0x00000300	/* Low Power Mode mask			*/
+#define PLPRCR_LPM_NORMAL 0x00000000	/* normal power management mode		*/
+#define PLPRCR_LPM_DOZE	  0x00000100	/* doze power management mode		*/
+#define PLPRCR_LPM_SLEEP  0x00000200	/* sleep power management mode		*/
+#define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode		*/
+#define PLPRCR_LPM_DOWN	  0x00000300	/* down power management mode		*/
+
+/* Common defines */
+#define PLPRCR_TEXPS	0x00004000	/* TEXP Status				*/
+#define PLPRCR_CSRC	0x00000400	/* Clock Source				*/
+
+#define PLPRCR_CSR	0x00000080	/* CheskStop Reset value		*/
+#define PLPRCR_LOLRE	0x00000040	/* Loss Of Lock Reset Enable		*/
+#define PLPRCR_FIOPD	0x00000020	/* Force I/O Pull Down			*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register			15-27
+ */
+#define SCCR_COM00	0x00000000	/* full strength CLKOUT output buffer	*/
+#define SCCR_COM01	0x20000000	/* half strength CLKOUT output buffer	*/
+#define SCCR_COM10	0x40000000	/* reserved				*/
+#define SCCR_COM11	0x60000000	/* CLKOUT output buffer disabled	*/
+#define SCCR_TBS	0x02000000	/* Time Base Source			*/
+#define SCCR_RTDIV	0x01000000	/* RTC Clock Divide			*/
+#define SCCR_RTSEL	0x00800000	/* RTC circuit input source select	*/
+#define SCCR_CRQEN	0x00400000	/* CPM Request Enable			*/
+#define SCCR_PRQEN	0x00200000	/* Power Management Request Enable	*/
+#define SCCR_EBDF00	0x00000000	/* CLKOUT is GCLK2 / 1 (normal op.)	*/
+#define SCCR_EBDF01	0x00020000	/* CLKOUT is GCLK2 / 2			*/
+#define SCCR_EBDF10	0x00040000	/* reserved				*/
+#define SCCR_EBDF11	0x00060000	/* reserved				*/
+#define SCCR_DFSYNC00	0x00000000	/* SyncCLK division by 1 (normal op.)	*/
+#define SCCR_DFSYNC01	0x00002000	/* SyncCLK division by 4		*/
+#define SCCR_DFSYNC10	0x00004000	/* SyncCLK division by 16		*/
+#define SCCR_DFSYNC11	0x00006000	/* SyncCLK division by 64		*/
+#define SCCR_DFBRG00	0x00000000	/* BRGCLK division by 1 (normal op.)	*/
+#define SCCR_DFBRG01	0x00000800	/* BRGCLK division by 4			*/
+#define SCCR_DFBRG10	0x00001000	/* BRGCLK division by 16		*/
+#define SCCR_DFBRG11	0x00001800	/* BRGCLK division by 64		*/
+#define SCCR_DFNL000	0x00000000	/* Division by 2 (default = minimum)	*/
+#define SCCR_DFNL001	0x00000100	/* Division by 4 	                */
+#define SCCR_DFNL010	0x00000200	/* Division by 8 	                */
+#define SCCR_DFNL011	0x00000300	/* Division by 16 	                */
+#define SCCR_DFNL100	0x00000400	/* Division by 32 	                */
+#define SCCR_DFNL101	0x00000500	/* Division by 64 	                */
+#define SCCR_DFNL110	0x00000600	/* Division by 128 	                */
+#define SCCR_DFNL111	0x00000700	/* Division by 256 (maximum)		*/
+#define SCCR_DFNH000	0x00000000	/* Division by 1 (default = minimum)	*/
+#define SCCR_DFNH110	0x000000D0	/* Division by 64 (maximum)		*/
+#define SCCR_DFNH111	0x000000E0	/* reserved				*/
+#define SCCR_DFLCD000	0x00000000	/* Division by 1 (default = minimum)	*/
+#define SCCR_DFLCD001	0x00000004	/* Division by 2			*/
+#define SCCR_DFLCD010	0x00000008	/* Division by 4			*/
+#define SCCR_DFLCD011	0x0000000C	/* Division by 8			*/
+#define SCCR_DFLCD100	0x00000010	/* Division by 16			*/
+#define SCCR_DFLCD101	0x00000014	/* Division by 32			*/
+#define SCCR_DFLCD110	0x00000018	/* Division by 64 (maximum)		*/
+#define SCCR_DFLCD111	0x0000001C	/* reserved				*/
+#define SCCR_DFALCD00	0x00000000	/* Division by 1 (default = minimum)	*/
+#define SCCR_DFALCD01	0x00000001	/* Division by 3			*/
+#define SCCR_DFALCD10	0x00000002	/* Division by 5			*/
+#define SCCR_DFALCD11	0x00000003	/* Division by 7 (maximum)		*/
+
+
+/*-----------------------------------------------------------------------
+ * BR - Memory Controler: Base Register					16-9
+ */
+#define BR_BA_MSK	0xFFFF8000	/* Base Address Mask			*/
+#define BR_AT_MSK	0x00007000	/* Address Type Mask			*/
+#define BR_PS_MSK	0x00000C00	/* Port Size Mask			*/
+#define BR_PS_32	0x00000000	/* 32 bit port size			*/
+#define BR_PS_16	0x00000800	/* 16 bit port size			*/
+#define BR_PS_8		0x00000400	/*  8 bit port size			*/
+#define BR_PARE		0x00000200	/* Parity Enable			*/
+#define BR_WP		0x00000100	/* Write Protect			*/
+#define BR_MS_MSK	0x000000C0	/* Machine Select Mask			*/
+#define BR_MS_GPCM	0x00000000	/* G.P.C.M. Machine Select		*/
+#define BR_MS_UPMA	0x00000080	/* U.P.M.A Machine Select		*/
+#define BR_MS_UPMB	0x000000C0	/* U.P.M.B Machine Select		*/
+#define BR_V		0x00000001	/* Bank Valid				*/
+
+/*-----------------------------------------------------------------------
+ * OR - Memory Controler: Option Register				16-11
+ */
+#define OR_AM_MSK	0xFFFF8000	/* Address Mask Mask			*/
+#define OR_ATM_MSK	0x00007000	/* Address Type Mask Mask		*/
+#define OR_CSNT_SAM	0x00000800	/* Chip Select Negation Time/ Start	*/
+					/* Address Multiplex			*/
+#define OR_ACS_MSK	0x00000600	/* Address to Chip Select Setup mask	*/
+#define OR_ACS_DIV1	0x00000000	/* CS is output at the same time	*/
+#define OR_ACS_DIV4	0x00000400	/* CS is output 1/4 a clock later	*/
+#define OR_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later	*/
+#define OR_G5LA		0x00000400	/* Output #GPL5 on #GPL_A5		*/
+#define OR_G5LS		0x00000200	/* Drive #GPL high on falling edge of...*/
+#define OR_BI		0x00000100	/* Burst inhibit			*/
+#define OR_SCY_MSK	0x000000F0	/* Cycle Lenght in Clocks		*/
+#define OR_SCY_0_CLK	0x00000000	/* 0 clock cycles wait states		*/
+#define OR_SCY_1_CLK	0x00000010	/* 1 clock cycles wait states		*/
+#define OR_SCY_2_CLK	0x00000020	/* 2 clock cycles wait states		*/
+#define OR_SCY_3_CLK	0x00000030	/* 3 clock cycles wait states		*/
+#define OR_SCY_4_CLK	0x00000040	/* 4 clock cycles wait states		*/
+#define OR_SCY_5_CLK	0x00000050	/* 5 clock cycles wait states		*/
+#define OR_SCY_6_CLK	0x00000060	/* 6 clock cycles wait states		*/
+#define OR_SCY_7_CLK	0x00000070	/* 7 clock cycles wait states		*/
+#define OR_SCY_8_CLK	0x00000080	/* 8 clock cycles wait states		*/
+#define OR_SCY_9_CLK	0x00000090	/* 9 clock cycles wait states		*/
+#define OR_SCY_10_CLK	0x000000A0	/* 10 clock cycles wait states		*/
+#define OR_SCY_11_CLK	0x000000B0	/* 11 clock cycles wait states		*/
+#define OR_SCY_12_CLK	0x000000C0	/* 12 clock cycles wait states		*/
+#define OR_SCY_13_CLK	0x000000D0	/* 13 clock cycles wait states		*/
+#define OR_SCY_14_CLK	0x000000E0	/* 14 clock cycles wait states		*/
+#define OR_SCY_15_CLK	0x000000F0	/* 15 clock cycles wait states		*/
+#define OR_SETA		0x00000008	/* External Transfer Acknowledge	*/
+#define OR_TRLX		0x00000004	/* Timing Relaxed			*/
+#define OR_EHTR		0x00000002	/* Extended Hold Time on Read		*/
+
+
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Periodic Timer Prescaler Register			16-17
+ */
+#define MPTPR_PTP_MSK	0xFF00		/* Periodic Timers Prescaler Mask	*/
+#define MPTPR_PTP_DIV2	0x2000		/* BRGCLK divided by 2			*/
+#define MPTPR_PTP_DIV4	0x1000		/* BRGCLK divided by 4			*/
+#define MPTPR_PTP_DIV8	0x0800		/* BRGCLK divided by 8			*/
+#define MPTPR_PTP_DIV16 0x0400		/* BRGCLK divided by 16			*/
+#define MPTPR_PTP_DIV32 0x0200		/* BRGCLK divided by 32			*/
+#define MPTPR_PTP_DIV64 0x0100		/* BRGCLK divided by 64			*/
+
+/*-----------------------------------------------------------------------
+ * MCR - Memory Command Register
+ */
+#define MCR_OP_WRITE	0x00000000	/* WRITE command			*/
+#define MCR_OP_READ	0x40000000	/* READ	 command			*/
+#define MCR_OP_RUN	0x80000000	/* RUN	 command			*/
+#define MCR_UPM_A	0x00000000	/* Select UPM A				*/
+#define MCR_UPM_B	0x00800000	/* Select UPM B				*/
+#define MCR_MB_CS0	0x00000000	/* Use Chip Select /CS0			*/
+#define MCR_MB_CS1	0x00002000	/* Use Chip Select /CS1			*/
+#define MCR_MB_CS2	0x00004000	/* Use Chip Select /CS2			*/
+#define MCR_MB_CS3	0x00006000	/* Use Chip Select /CS3			*/
+#define MCR_MB_CS4	0x00008000	/* Use Chip Select /CS4			*/
+#define MCR_MB_CS5	0x0000A000	/* Use Chip Select /CS5			*/
+#define MCR_MB_CS6	0x0000C000	/* Use Chip Select /CS6			*/
+#define MCR_MB_CS7	0x0000E000	/* Use Chip Select /CS7			*/
+#define MCR_MLCF(n)	(((n)&0xF)<<8)	/* Memory Command Loop Count Field	*/
+#define MCR_MAD(addr)	((addr)&0x3F)	/* Memory Array Index			*/
+
+/*-----------------------------------------------------------------------
+ * Machine A Mode Register						16-13
+ */
+#define MAMR_PTA_MSK	0xFF000000	/* Periodic Timer A period mask		*/
+#define MAMR_PTA_SHIFT	0x00000018	/* Periodic Timer A period shift	*/
+#define MAMR_PTAE	0x00800000	/* Periodic Timer A Enable		*/
+#define MAMR_AMA_MSK	0x00700000	/* Addess Multiplexing size A		*/
+#define MAMR_AMA_TYPE_0 0x00000000	/* Addess Multiplexing Type 0		*/
+#define MAMR_AMA_TYPE_1 0x00100000	/* Addess Multiplexing Type 1		*/
+#define MAMR_AMA_TYPE_2 0x00200000	/* Addess Multiplexing Type 2		*/
+#define MAMR_AMA_TYPE_3 0x00300000	/* Addess Multiplexing Type 3		*/
+#define MAMR_AMA_TYPE_4 0x00400000	/* Addess Multiplexing Type 4		*/
+#define MAMR_AMA_TYPE_5 0x00500000	/* Addess Multiplexing Type 5		*/
+#define MAMR_DSA_MSK	0x00060000	/* Disable Timer period mask		*/
+#define MAMR_DSA_1_CYCL 0x00000000	/* 1 cycle Disable Period		*/
+#define MAMR_DSA_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
+#define MAMR_DSA_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
+#define MAMR_DSA_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
+#define MAMR_G0CLA_MSK	0x0000E000	/* General Line 0 Control A		*/
+#define MAMR_G0CLA_A12	0x00000000	/* General Line 0 : A12			*/
+#define MAMR_G0CLA_A11	0x00002000	/* General Line 0 : A11			*/
+#define MAMR_G0CLA_A10	0x00004000	/* General Line 0 : A10			*/
+#define MAMR_G0CLA_A9	0x00006000	/* General Line 0 : A9			*/
+#define MAMR_G0CLA_A8	0x00008000	/* General Line 0 : A8			*/
+#define MAMR_G0CLA_A7	0x0000A000	/* General Line 0 : A7			*/
+#define MAMR_G0CLA_A6	0x0000C000	/* General Line 0 : A6			*/
+#define MAMR_G0CLA_A5	0x0000E000	/* General Line 0 : A5			*/
+#define MAMR_GPL_A4DIS	0x00001000	/* GPL_A4 ouput line Disable		*/
+#define MAMR_RLFA_MSK	0x00000F00	/* Read Loop Field A mask		*/
+#define MAMR_RLFA_1X	0x00000100	/* The Read Loop is executed 1 time	*/
+#define MAMR_RLFA_2X	0x00000200	/* The Read Loop is executed 2 times	*/
+#define MAMR_RLFA_3X	0x00000300	/* The Read Loop is executed 3 times	*/
+#define MAMR_RLFA_4X	0x00000400	/* The Read Loop is executed 4 times	*/
+#define MAMR_RLFA_5X	0x00000500	/* The Read Loop is executed 5 times	*/
+#define MAMR_RLFA_6X	0x00000600	/* The Read Loop is executed 6 times	*/
+#define MAMR_RLFA_7X	0x00000700	/* The Read Loop is executed 7 times	*/
+#define MAMR_RLFA_8X	0x00000800	/* The Read Loop is executed 8 times	*/
+#define MAMR_RLFA_9X	0x00000900	/* The Read Loop is executed 9 times	*/
+#define MAMR_RLFA_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
+#define MAMR_RLFA_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
+#define MAMR_RLFA_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
+#define MAMR_RLFA_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
+#define MAMR_RLFA_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
+#define MAMR_RLFA_15X	0x00000F00	/* The Read Loop is executed 15 times	*/
+#define MAMR_RLFA_16X	0x00000000	/* The Read Loop is executed 16 times	*/
+#define MAMR_WLFA_MSK	0x000000F0	/* Write Loop Field A mask		*/
+#define MAMR_WLFA_1X	0x00000010	/* The Write Loop is executed 1 time	*/
+#define MAMR_WLFA_2X	0x00000020	/* The Write Loop is executed 2 times	*/
+#define MAMR_WLFA_3X	0x00000030	/* The Write Loop is executed 3 times	*/
+#define MAMR_WLFA_4X	0x00000040	/* The Write Loop is executed 4 times	*/
+#define MAMR_WLFA_5X	0x00000050	/* The Write Loop is executed 5 times	*/
+#define MAMR_WLFA_6X	0x00000060	/* The Write Loop is executed 6 times	*/
+#define MAMR_WLFA_7X	0x00000070	/* The Write Loop is executed 7 times	*/
+#define MAMR_WLFA_8X	0x00000080	/* The Write Loop is executed 8 times	*/
+#define MAMR_WLFA_9X	0x00000090	/* The Write Loop is executed 9 times	*/
+#define MAMR_WLFA_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
+#define MAMR_WLFA_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
+#define MAMR_WLFA_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
+#define MAMR_WLFA_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
+#define MAMR_WLFA_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
+#define MAMR_WLFA_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
+#define MAMR_WLFA_16X	0x00000000	/* The Write Loop is executed 16 times	*/
+#define MAMR_TLFA_MSK	0x0000000F	/* Timer Loop Field A mask		*/
+#define MAMR_TLFA_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
+#define MAMR_TLFA_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
+#define MAMR_TLFA_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
+#define MAMR_TLFA_4X	0x00000004	/* The Timer Loop is executed 4 times	*/
+#define MAMR_TLFA_5X	0x00000005	/* The Timer Loop is executed 5 times	*/
+#define MAMR_TLFA_6X	0x00000006	/* The Timer Loop is executed 6 times	*/
+#define MAMR_TLFA_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
+#define MAMR_TLFA_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
+#define MAMR_TLFA_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
+#define MAMR_TLFA_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
+#define MAMR_TLFA_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
+#define MAMR_TLFA_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
+#define MAMR_TLFA_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
+#define MAMR_TLFA_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
+#define MAMR_TLFA_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
+#define MAMR_TLFA_16X	0x00000000	/* The Timer Loop is executed 16 times	*/
+
+/*-----------------------------------------------------------------------
+ * Machine B Mode Register						16-13
+ */
+#define MBMR_PTB_MSK	0xFF000000	/* Periodic Timer B period mask		*/
+#define MBMR_PTB_SHIFT	0x00000018	/* Periodic Timer B period shift	*/
+#define MBMR_PTBE	0x00800000	/* Periodic Timer B Enable		*/
+#define MBMR_AMB_MSK	0x00700000	/* Addess Multiplex size B		*/
+#define MBMR_AMB_TYPE_0 0x00000000	/* Addess Multiplexing Type 0		*/
+#define MBMR_AMB_TYPE_1 0x00100000	/* Addess Multiplexing Type 1		*/
+#define MBMR_AMB_TYPE_2 0x00200000	/* Addess Multiplexing Type 2		*/
+#define MBMR_AMB_TYPE_3 0x00300000	/* Addess Multiplexing Type 3		*/
+#define MBMR_AMB_TYPE_4 0x00400000	/* Addess Multiplexing Type 4		*/
+#define MBMR_AMB_TYPE_5 0x00500000	/* Addess Multiplexing Type 5		*/
+#define MBMR_DSB_MSK	0x00060000	/* Disable Timer period mask		*/
+#define MBMR_DSB_1_CYCL 0x00000000	/* 1 cycle Disable Period		*/
+#define MBMR_DSB_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
+#define MBMR_DSB_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
+#define MBMR_DSB_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
+#define MBMR_G0CLB_MSK	0x0000E000	/* General Line 0 Control B		*/
+#define MBMR_G0CLB_A12	0x00000000	/* General Line 0 : A12			*/
+#define MBMR_G0CLB_A11	0x00002000	/* General Line 0 : A11			*/
+#define MBMR_G0CLB_A10	0x00004000	/* General Line 0 : A10			*/
+#define MBMR_G0CLB_A9	0x00006000	/* General Line 0 : A9			*/
+#define MBMR_G0CLB_A8	0x00008000	/* General Line 0 : A8			*/
+#define MBMR_G0CLB_A7	0x0000A000	/* General Line 0 : A7			*/
+#define MBMR_G0CLB_A6	0x0000C000	/* General Line 0 : A6			*/
+#define MBMR_G0CLB_A5	0x0000E000	/* General Line 0 : A5			*/
+#define MBMR_GPL_B4DIS	0x00001000	/* GPL_B4 ouput line Disable		*/
+#define MBMR_RLFB_MSK	0x00000F00	/* Read Loop Field B mask		*/
+#define MBMR_RLFB_1X	0x00000100	/* The Read Loop is executed 1 time	*/
+#define MBMR_RLFB_2X	0x00000200	/* The Read Loop is executed 2 times	*/
+#define MBMR_RLFB_3X	0x00000300	/* The Read Loop is executed 3 times	*/
+#define MBMR_RLFB_4X	0x00000400	/* The Read Loop is executed 4 times	*/
+#define MBMR_RLFB_5X	0x00000500	/* The Read Loop is executed 5 times	*/
+#define MBMR_RLFB_6X	0x00000600	/* The Read Loop is executed 6 times	*/
+#define MBMR_RLFB_7X	0x00000700	/* The Read Loop is executed 7 times	*/
+#define MBMR_RLFB_8X	0x00000800	/* The Read Loop is executed 8 times	*/
+#define MBMR_RLFB_9X	0x00000900	/* The Read Loop is executed 9 times	*/
+#define MBMR_RLFB_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
+#define MBMR_RLFB_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
+#define MBMR_RLFB_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
+#define MBMR_RLFB_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
+#define MBMR_RLFB_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
+#define MBMR_RLFB_15X	0x00000f00	/* The Read Loop is executed 15 times	*/
+#define MBMR_RLFB_16X	0x00000000	/* The Read Loop is executed 16 times	*/
+#define MBMR_WLFB_MSK	0x000000F0	/* Write Loop Field B mask		*/
+#define MBMR_WLFB_1X	0x00000010	/* The Write Loop is executed 1 time	*/
+#define MBMR_WLFB_2X	0x00000020	/* The Write Loop is executed 2 times	*/
+#define MBMR_WLFB_3X	0x00000030	/* The Write Loop is executed 3 times	*/
+#define MBMR_WLFB_4X	0x00000040	/* The Write Loop is executed 4 times	*/
+#define MBMR_WLFB_5X	0x00000050	/* The Write Loop is executed 5 times	*/
+#define MBMR_WLFB_6X	0x00000060	/* The Write Loop is executed 6 times	*/
+#define MBMR_WLFB_7X	0x00000070	/* The Write Loop is executed 7 times	*/
+#define MBMR_WLFB_8X	0x00000080	/* The Write Loop is executed 8 times	*/
+#define MBMR_WLFB_9X	0x00000090	/* The Write Loop is executed 9 times	*/
+#define MBMR_WLFB_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
+#define MBMR_WLFB_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
+#define MBMR_WLFB_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
+#define MBMR_WLFB_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
+#define MBMR_WLFB_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
+#define MBMR_WLFB_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
+#define MBMR_WLFB_16X	0x00000000	/* The Write Loop is executed 16 times	*/
+#define MBMR_TLFB_MSK	0x0000000F	/* Timer Loop Field B mask		*/
+#define MBMR_TLFB_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
+#define MBMR_TLFB_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
+#define MBMR_TLFB_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
+#define MBMR_TLFB_4X	0x00000004	/* The Timer Loop is executed 4 times	*/
+#define MBMR_TLFB_5X	0x00000005	/* The Timer Loop is executed 5 times	*/
+#define MBMR_TLFB_6X	0x00000006	/* The Timer Loop is executed 6 times	*/
+#define MBMR_TLFB_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
+#define MBMR_TLFB_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
+#define MBMR_TLFB_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
+#define MBMR_TLFB_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
+#define MBMR_TLFB_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
+#define MBMR_TLFB_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
+#define MBMR_TLFB_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
+#define MBMR_TLFB_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
+#define MBMR_TLFB_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
+#define MBMR_TLFB_16X	0x00000000	/* The Timer Loop is executed 16 times	*/
+
+/*-----------------------------------------------------------------------
+ * Timer Global Configuration Register					18-8
+ */
+#define TGCR_CAS4	0x8000		/* Cascade Timer 3 and 4	*/
+#define TGCR_FRZ4	0x4000		/* Freeze timer 4		*/
+#define TGCR_STP4	0x2000		/* Stop timer	4		*/
+#define TGCR_RST4	0x1000		/* Reset timer	4		*/
+#define TGCR_GM2	0x0800		/* Gate Mode for Pin 2		*/
+#define TGCR_FRZ3	0x0400		/* Freeze timer 3		*/
+#define TGCR_STP3	0x0200		/* Stop timer	3		*/
+#define TGCR_RST3	0x0100		/* Reset timer	3		*/
+#define TGCR_CAS2	0x0080		/* Cascade Timer 1 and 2	*/
+#define TGCR_FRZ2	0x0040		/* Freeze timer 2		*/
+#define TGCR_STP2	0x0020		/* Stop timer	2		*/
+#define TGCR_RST2	0x0010		/* Reset timer	2		*/
+#define TGCR_GM1	0x0008		/* Gate Mode for Pin 1		*/
+#define TGCR_FRZ1	0x0004		/* Freeze timer 1		*/
+#define TGCR_STP1	0x0002		/* Stop timer	1		*/
+#define TGCR_RST1	0x0001		/* Reset timer	1		*/
+
+
+/*-----------------------------------------------------------------------
+ * Timer Mode Register							18-9
+ */
+#define TMR_PS_MSK		0xFF00	/* Prescaler Value			*/
+#define TMR_PS_SHIFT		     8	/* Prescaler position			*/
+#define TMR_CE_MSK		0x00C0	/* Capture Edge and Enable Interrupt	*/
+#define TMR_CE_INTR_DIS		0x0000	/* Disable Interrupt on capture event	*/
+#define TMR_CE_RISING		0x0040	/* Capture on Rising TINx edge only	*/
+#define TMR_CE_FALLING		0x0080	/* Capture on Falling TINx edge only	*/
+#define TMR_CE_ANY		0x00C0	/* Capture on any TINx edge		*/
+#define TMR_OM			0x0020	/* Output Mode				*/
+#define TMR_ORI			0x0010	/* Output Reference Interrupt Enable	*/
+#define TMR_FRR			0x0008	/* Free Run/Restart			*/
+#define TMR_ICLK_MSK		0x0006	/* Timer Input Clock Source mask	*/
+#define TMR_ICLK_IN_CAS		0x0000	/* Internally cascaded input		*/
+#define TMR_ICLK_IN_GEN		0x0002	/* Internal General system clock	*/
+#define TMR_ICLK_IN_GEN_DIV16	0x0004	/* Internal General system clk div 16	*/
+#define TMR_ICLK_TIN_PIN	0x0006	/* TINx pin				*/
+#define TMR_GE			0x0001	/* Gate Enable				*/
+
+
+/*-----------------------------------------------------------------------
+ * I2C Controller Registers
+ */
+#define I2MOD_REVD		0x20	/* Reverese Data			*/
+#define I2MOD_GCD		0x10	/* General Call Disable			*/
+#define I2MOD_FLT		0x08	/* Clock Filter				*/
+#define I2MOD_PDIV32		0x00	/* Pre-Divider 32			*/
+#define I2MOD_PDIV16		0x02	/* Pre-Divider 16			*/
+#define I2MOD_PDIV8		0x04	/* Pre-Divider	8			*/
+#define I2MOD_PDIV4		0x06	/* Pre-Divider	4			*/
+#define I2MOD_EN		0x01	/* Enable				*/
+
+#define I2CER_TXE		0x10	/* Tx Error				*/
+#define I2CER_BSY		0x04	/* Busy Condition			*/
+#define I2CER_TXB		0x02	/* Tx Buffer Transmitted		*/
+#define I2CER_RXB		0x01	/* Rx Buffer Received			*/
+#define I2CER_ALL		(I2CER_TXE | I2CER_BSY | I2CER_TXB | I2CER_RXB)
+
+#define I2COM_STR		0x80	/* Start Transmit			*/
+#define I2COM_MASTER		0x01	/* Master mode				*/
+
+/*-----------------------------------------------------------------------
+ * SPI Controller Registers						31-10
+ */
+#define SPI_EMASK		0x37	/* Event Mask				*/
+#define SPI_MME			0x20	/* Multi-Master Error			*/
+#define SPI_TXE			0x10	/* Transmit Error			*/
+#define SPI_BSY			0x04	/* Busy					*/
+#define SPI_TXB			0x02	/* Tx Buffer Empty			*/
+#define SPI_RXB			0x01	/* RX Buffer full/closed		*/
+
+#define SPI_STR			0x80	/* SPCOM: Start transmit		*/
+
+/*-----------------------------------------------------------------------
+ * PCMCIA Interface General Control Register				17-12
+ */
+#define PCMCIA_GCRX_CXRESET	0x00000040
+#define PCMCIA_GCRX_CXOE	0x00000080
+
+#define PCMCIA_VS1(slot)	(0x80000000 >> (slot << 4))
+#define PCMCIA_VS2(slot)	(0x40000000 >> (slot << 4))
+#define PCMCIA_VS_MASK(slot)	(0xC0000000 >> (slot << 4))
+#define PCMCIA_VS_SHIFT(slot)	(30 - (slot << 4))
+
+#define PCMCIA_WP(slot)		(0x20000000 >> (slot << 4))
+#define PCMCIA_CD2(slot)	(0x10000000 >> (slot << 4))
+#define PCMCIA_CD1(slot)	(0x08000000 >> (slot << 4))
+#define PCMCIA_BVD2(slot)	(0x04000000 >> (slot << 4))
+#define PCMCIA_BVD1(slot)	(0x02000000 >> (slot << 4))
+#define PCMCIA_RDY(slot)	(0x01000000 >> (slot << 4))
+#define PCMCIA_RDY_L(slot)	(0x00800000 >> (slot << 4))
+#define PCMCIA_RDY_H(slot)	(0x00400000 >> (slot << 4))
+#define PCMCIA_RDY_R(slot)	(0x00200000 >> (slot << 4))
+#define PCMCIA_RDY_F(slot)	(0x00100000 >> (slot << 4))
+#define PCMCIA_MASK(slot)	(0xFFFF0000 >> (slot << 4))
+
+/*-----------------------------------------------------------------------
+ * PCMCIA Option Register Definitions
+ *
+ * Bank Sizes:
+ */
+#define PCMCIA_BSIZE_1		0x00000000	/* Bank size:	1 Bytes */
+#define PCMCIA_BSIZE_2		0x08000000	/* Bank size:	2 Bytes */
+#define PCMCIA_BSIZE_4		0x18000000	/* Bank size:	4 Bytes */
+#define PCMCIA_BSIZE_8		0x10000000	/* Bank size:	8 Bytes */
+#define PCMCIA_BSIZE_16		0x30000000	/* Bank size:  16 Bytes */
+#define PCMCIA_BSIZE_32		0x38000000	/* Bank size:  32 Bytes */
+#define PCMCIA_BSIZE_64		0x28000000	/* Bank size:  64 Bytes */
+#define PCMCIA_BSIZE_128	0x20000000	/* Bank size: 128 Bytes */
+#define PCMCIA_BSIZE_256	0x60000000	/* Bank size: 256 Bytes */
+#define PCMCIA_BSIZE_512	0x68000000	/* Bank size: 512 Bytes */
+#define PCMCIA_BSIZE_1K		0x78000000	/* Bank size:	1 kB	*/
+#define PCMCIA_BSIZE_2K		0x70000000	/* Bank size:	2 kB	*/
+#define PCMCIA_BSIZE_4K		0x50000000	/* Bank size:	4 kB	*/
+#define PCMCIA_BSIZE_8K		0x58000000	/* Bank size:	8 kB	*/
+#define PCMCIA_BSIZE_16K	0x48000000	/* Bank size:  16 kB	*/
+#define PCMCIA_BSIZE_32K	0x40000000	/* Bank size:  32 kB	*/
+#define PCMCIA_BSIZE_64K	0xC0000000	/* Bank size:  64 kB	*/
+#define PCMCIA_BSIZE_128K	0xC8000000	/* Bank size: 128 kB	*/
+#define PCMCIA_BSIZE_256K	0xD8000000	/* Bank size: 256 kB	*/
+#define PCMCIA_BSIZE_512K	0xD0000000	/* Bank size: 512 kB	*/
+#define PCMCIA_BSIZE_1M		0xF0000000	/* Bank size:	1 MB	*/
+#define PCMCIA_BSIZE_2M		0xF8000000	/* Bank size:	2 MB	*/
+#define PCMCIA_BSIZE_4M		0xE8000000	/* Bank size:	4 MB	*/
+#define PCMCIA_BSIZE_8M		0xE0000000	/* Bank size:	8 MB	*/
+#define PCMCIA_BSIZE_16M	0xA0000000	/* Bank size:  16 MB	*/
+#define PCMCIA_BSIZE_32M	0xA8000000	/* Bank size:  32 MB	*/
+#define PCMCIA_BSIZE_64M	0xB8000000	/* Bank size:  64 MB	*/
+
+/* PCMCIA Timing */
+#define PCMCIA_SHT(t)	((t & 0x0F)<<16)	/* Strobe Hold	Time	*/
+#define PCMCIA_SST(t)	((t & 0x0F)<<12)	/* Strobe Setup Time	*/
+#define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length	*/
+
+/* PCMCIA Port Sizes */
+#define PCMCIA_PPS_8		0x00000000	/*  8 bit port size	*/
+#define PCMCIA_PPS_16		0x00000040	/* 16 bit port size	*/
+
+/* PCMCIA Region Select */
+#define PCMCIA_PRS_MEM		0x00000000	/* Common Memory Space	*/
+#define PCMCIA_PRS_ATTR		0x00000010	/*     Attribute Space	*/
+#define PCMCIA_PRS_IO		0x00000018	/*	     I/O Space	*/
+#define PCMCIA_PRS_DMA		0x00000020	/* DMA, normal transfer */
+#define PCMCIA_PRS_DMA_LAST	0x00000028	/* DMA, last transactn	*/
+#define PCMCIA_PRS_CEx		0x00000030	/* A[22:23] ==> CE1,CE2 */
+
+#define PCMCIA_PSLOT_A		0x00000000	/* Slot A		*/
+#define PCMCIA_PSLOT_B		0x00000004	/* Slot B		*/
+#define PCMCIA_WPROT		0x00000002	/* Write Protect	*/
+#define PCMCIA_PV		0x00000001	/* Valid Bit		*/
+
+#define UPMA	0x00000000
+#define UPMB	0x00800000
+
+#endif	/* __MPCXX_H__ */
diff --git a/include/mpc8xx_irq.h b/include/mpc8xx_irq.h
new file mode 100755
index 0000000..d2a81c0
--- /dev/null
+++ b/include/mpc8xx_irq.h
@@ -0,0 +1,59 @@
+#ifndef _MPC8XX_IRQ_H
+#define _MPC8XX_IRQ_H
+
+/* The MPC8xx cores have 16 possible interrupts.  There are eight
+ * possible level sensitive interrupts assigned and generated internally
+ * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
+ * There are eight external interrupts (IRQs) that can be configured
+ * as either level or edge sensitive.
+ *
+ * On some implementations, there is also the possibility of an 8259
+ * through the PCI and PCI-ISA bridges.
+ *
+ * We don't support the 8259 (yet).
+ */
+#define NR_SIU_INTS	16
+#define	NR_8259_INTS	0
+
+#define NR_IRQS	(NR_SIU_INTS + NR_8259_INTS)
+
+/* These values must be zero-based and map 1:1 with the SIU configuration.
+ * They are used throughout the 8xx I/O subsystem to generate
+ * interrupt masks, flags, and other control patterns.  This is why the
+ * current kernel assumption of the 8259 as the base controller is such
+ * a pain in the butt.
+ */
+#define	SIU_IRQ0	(0)	/* Highest priority */
+#define	SIU_LEVEL0	(1)
+#define	SIU_IRQ1	(2)
+#define	SIU_LEVEL1	(3)
+#define	SIU_IRQ2	(4)
+#define	SIU_LEVEL2	(5)
+#define	SIU_IRQ3	(6)
+#define	SIU_LEVEL3	(7)
+#define	SIU_IRQ4	(8)
+#define	SIU_LEVEL4	(9)
+#define	SIU_IRQ5	(10)
+#define	SIU_LEVEL5	(11)
+#define	SIU_IRQ6	(12)
+#define	SIU_LEVEL6	(13)
+#define	SIU_IRQ7	(14)
+#define	SIU_LEVEL7	(15)
+
+/* The internal interrupts we can configure as we see fit.
+ * My personal preference is CPM at level 2, which puts it above the
+ * MBX PCI/ISA/IDE interrupts.
+ */
+
+#ifdef CFG_CPM_INTERRUPT
+# define CPM_INTERRUPT		CFG_CPM_INTERRUPT
+#else
+# define CPM_INTERRUPT		SIU_LEVEL2
+#endif
+
+/* Some internal interrupt registers use an 8-bit mask for the interrupt
+ * level instead of a number.
+ */
+#define	mk_int_int_mask(IL) (1 << (7 - (IL/2)))
+
+#endif /* _MPC8XX_IRQ_H */
diff --git a/include/mtd/ubi-user.h b/include/mtd/ubi-user.h
new file mode 100755
index 0000000..a7421f1
--- /dev/null
+++ b/include/mtd/ubi-user.h
@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) International Business Machines Corp., 2006
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ * the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Author: Artem Bityutskiy (Битюцкий �ртём)
+ */
+
+#ifndef __UBI_USER_H__
+#define __UBI_USER_H__
+
+/*
+ * UBI device creation (the same as MTD device attachment)
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * MTD devices may be attached using %UBI_IOCATT ioctl command of the UBI
+ * control device. The caller has to properly fill and pass
+ * &struct ubi_attach_req object - UBI will attach the MTD device specified in
+ * the request and return the newly created UBI device number as the ioctl
+ * return value.
+ *
+ * UBI device deletion (the same as MTD device detachment)
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * An UBI device maybe deleted with %UBI_IOCDET ioctl command of the UBI
+ * control device.
+ *
+ * UBI volume creation
+ * ~~~~~~~~~~~~~~~~~~~
+ *
+ * UBI volumes are created via the %UBI_IOCMKVOL IOCTL command of UBI character
+ * device. A &struct ubi_mkvol_req object has to be properly filled and a
+ * pointer to it has to be passed to the IOCTL.
+ *
+ * UBI volume deletion
+ * ~~~~~~~~~~~~~~~~~~~
+ *
+ * To delete a volume, the %UBI_IOCRMVOL IOCTL command of the UBI character
+ * device should be used. A pointer to the 32-bit volume ID hast to be passed
+ * to the IOCTL.
+ *
+ * UBI volume re-size
+ * ~~~~~~~~~~~~~~~~~~
+ *
+ * To re-size a volume, the %UBI_IOCRSVOL IOCTL command of the UBI character
+ * device should be used. A &struct ubi_rsvol_req object has to be properly
+ * filled and a pointer to it has to be passed to the IOCTL.
+ *
+ * UBI volume update
+ * ~~~~~~~~~~~~~~~~~
+ *
+ * Volume update should be done via the %UBI_IOCVOLUP IOCTL command of the
+ * corresponding UBI volume character device. A pointer to a 64-bit update
+ * size should be passed to the IOCTL. After this, UBI expects user to write
+ * this number of bytes to the volume character device. The update is finished
+ * when the claimed number of bytes is passed. So, the volume update sequence
+ * is something like:
+ *
+ * fd = open("/dev/my_volume");
+ * ioctl(fd, UBI_IOCVOLUP, &image_size);
+ * write(fd, buf, image_size);
+ * close(fd);
+ *
+ * Atomic eraseblock change
+ * ~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * Atomic eraseblock change operation is done via the %UBI_IOCEBCH IOCTL
+ * command of the corresponding UBI volume character device. A pointer to
+ * &struct ubi_leb_change_req has to be passed to the IOCTL. Then the user is
+ * expected to write the requested amount of bytes. This is similar to the
+ * "volume update" IOCTL.
+ */
+
+/*
+ * When a new UBI volume or UBI device is created, users may either specify the
+ * volume/device number they want to create or to let UBI automatically assign
+ * the number using these constants.
+ */
+#define UBI_VOL_NUM_AUTO (-1)
+#define UBI_DEV_NUM_AUTO (-1)
+
+/* Maximum volume name length */
+#define UBI_MAX_VOLUME_NAME 127
+
+/* IOCTL commands of UBI character devices */
+
+#define UBI_IOC_MAGIC 'o'
+
+/* Create an UBI volume */
+#define UBI_IOCMKVOL _IOW(UBI_IOC_MAGIC, 0, struct ubi_mkvol_req)
+/* Remove an UBI volume */
+#define UBI_IOCRMVOL _IOW(UBI_IOC_MAGIC, 1, int32_t)
+/* Re-size an UBI volume */
+#define UBI_IOCRSVOL _IOW(UBI_IOC_MAGIC, 2, struct ubi_rsvol_req)
+
+/* IOCTL commands of the UBI control character device */
+
+#define UBI_CTRL_IOC_MAGIC 'o'
+
+/* Attach an MTD device */
+#define UBI_IOCATT _IOW(UBI_CTRL_IOC_MAGIC, 64, struct ubi_attach_req)
+/* Detach an MTD device */
+#define UBI_IOCDET _IOW(UBI_CTRL_IOC_MAGIC, 65, int32_t)
+
+/* IOCTL commands of UBI volume character devices */
+
+#define UBI_VOL_IOC_MAGIC 'O'
+
+/* Start UBI volume update */
+#define UBI_IOCVOLUP _IOW(UBI_VOL_IOC_MAGIC, 0, int64_t)
+/* An eraseblock erasure command, used for debugging, disabled by default */
+#define UBI_IOCEBER _IOW(UBI_VOL_IOC_MAGIC, 1, int32_t)
+/* An atomic eraseblock change command */
+#define UBI_IOCEBCH _IOW(UBI_VOL_IOC_MAGIC, 2, int32_t)
+
+/* Maximum MTD device name length supported by UBI */
+#define MAX_UBI_MTD_NAME_LEN 127
+
+/*
+ * UBI data type hint constants.
+ *
+ * UBI_LONGTERM: long-term data
+ * UBI_SHORTTERM: short-term data
+ * UBI_UNKNOWN: data persistence is unknown
+ *
+ * These constants are used when data is written to UBI volumes in order to
+ * help the UBI wear-leveling unit to find more appropriate physical
+ * eraseblocks.
+ */
+enum {
+	UBI_LONGTERM  = 1,
+	UBI_SHORTTERM = 2,
+	UBI_UNKNOWN   = 3,
+};
+
+/*
+ * UBI volume type constants.
+ *
+ * @UBI_DYNAMIC_VOLUME: dynamic volume
+ * @UBI_STATIC_VOLUME:  static volume
+ */
+enum {
+	UBI_DYNAMIC_VOLUME = 3,
+	UBI_STATIC_VOLUME  = 4,
+};
+
+/**
+ * struct ubi_attach_req - attach MTD device request.
+ * @ubi_num: UBI device number to create
+ * @mtd_num: MTD device number to attach
+ * @vid_hdr_offset: VID header offset (use defaults if %0)
+ * @padding: reserved for future, not used, has to be zeroed
+ *
+ * This data structure is used to specify MTD device UBI has to attach and the
+ * parameters it has to use. The number which should be assigned to the new UBI
+ * device is passed in @ubi_num. UBI may automatically assign the number if
+ * @UBI_DEV_NUM_AUTO is passed. In this case, the device number is returned in
+ * @ubi_num.
+ *
+ * Most applications should pass %0 in @vid_hdr_offset to make UBI use default
+ * offset of the VID header within physical eraseblocks. The default offset is
+ * the next min. I/O unit after the EC header. For example, it will be offset
+ * 512 in case of a 512 bytes page NAND flash with no sub-page support. Or
+ * it will be 512 in case of a 2KiB page NAND flash with 4 512-byte sub-pages.
+ *
+ * But in rare cases, if this optimizes things, the VID header may be placed to
+ * a different offset. For example, the boot-loader might do things faster if the
+ * VID header sits at the end of the first 2KiB NAND page with 4 sub-pages. As
+ * the boot-loader would not normally need to read EC headers (unless it needs
+ * UBI in RW mode), it might be faster to calculate ECC. This is weird example,
+ * but it real-life example. So, in this example, @vid_hdr_offer would be
+ * 2KiB-64 bytes = 1984. Note, that this position is not even 512-bytes
+ * aligned, which is OK, as UBI is clever enough to realize this is 4th sub-page
+ * of the first page and add needed padding.
+ */
+struct ubi_attach_req {
+	int32_t ubi_num;
+	int32_t mtd_num;
+	int32_t vid_hdr_offset;
+	uint8_t padding[12];
+};
+
+/**
+ * struct ubi_mkvol_req - volume description data structure used in
+ *                        volume creation requests.
+ * @vol_id: volume number
+ * @alignment: volume alignment
+ * @bytes: volume size in bytes
+ * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME)
+ * @padding1: reserved for future, not used, has to be zeroed
+ * @name_len: volume name length
+ * @padding2: reserved for future, not used, has to be zeroed
+ * @name: volume name
+ *
+ * This structure is used by user-space programs when creating new volumes. The
+ * @used_bytes field is only necessary when creating static volumes.
+ *
+ * The @alignment field specifies the required alignment of the volume logical
+ * eraseblock. This means, that the size of logical eraseblocks will be aligned
+ * to this number, i.e.,
+ *	(UBI device logical eraseblock size) mod (@alignment) = 0.
+ *
+ * To put it differently, the logical eraseblock of this volume may be slightly
+ * shortened in order to make it properly aligned. The alignment has to be
+ * multiple of the flash minimal input/output unit, or %1 to utilize the entire
+ * available space of logical eraseblocks.
+ *
+ * The @alignment field may be useful, for example, when one wants to maintain
+ * a block device on top of an UBI volume. In this case, it is desirable to fit
+ * an integer number of blocks in logical eraseblocks of this UBI volume. With
+ * alignment it is possible to update this volume using plane UBI volume image
+ * BLOBs, without caring about how to properly align them.
+ */
+struct ubi_mkvol_req {
+	int32_t vol_id;
+	int32_t alignment;
+	int64_t bytes;
+	int8_t vol_type;
+	int8_t padding1;
+	int16_t name_len;
+	int8_t padding2[4];
+	char name[UBI_MAX_VOLUME_NAME + 1];
+} __attribute__ ((packed));
+
+/**
+ * struct ubi_rsvol_req - a data structure used in volume re-size requests.
+ * @vol_id: ID of the volume to re-size
+ * @bytes: new size of the volume in bytes
+ *
+ * Re-sizing is possible for both dynamic and static volumes. But while dynamic
+ * volumes may be re-sized arbitrarily, static volumes cannot be made to be
+ * smaller then the number of bytes they bear. To arbitrarily shrink a static
+ * volume, it must be wiped out first (by means of volume update operation with
+ * zero number of bytes).
+ */
+struct ubi_rsvol_req {
+	int64_t bytes;
+	int32_t vol_id;
+} __attribute__ ((packed));
+
+/**
+ * struct ubi_leb_change_req - a data structure used in atomic logical
+ *                             eraseblock change requests.
+ * @lnum: logical eraseblock number to change
+ * @bytes: how many bytes will be written to the logical eraseblock
+ * @dtype: data type (%UBI_LONGTERM, %UBI_SHORTTERM, %UBI_UNKNOWN)
+ * @padding: reserved for future, not used, has to be zeroed
+ */
+struct ubi_leb_change_req {
+	int32_t lnum;
+	int32_t bytes;
+	uint8_t dtype;
+	uint8_t padding[7];
+} __attribute__ ((packed));
+
+#endif /* __UBI_USER_H__ */
diff --git a/include/nand.h b/include/nand.h
new file mode 100755
index 0000000..bd5c948
--- /dev/null
+++ b/include/nand.h
@@ -0,0 +1,546 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+
+#ifndef __NAND_H__
+#define __NAND_H__
+
+#define __NFC_BASE 0xd8009000
+#define __SCC_BASE 0xd8120000
+
+typedef struct WMT_NFC_CFG_t{
+	volatile unsigned int NFCR0;           /* 0x00 */
+	volatile unsigned int	NFCR1;           /* 0x04 */
+	volatile unsigned int	NFCR2;           /* 0x08 */
+	volatile unsigned int	NFCR3;           /* 0x0c */
+	volatile unsigned int	NFCR4;           /* 0x10 */
+	volatile unsigned int NFCR5;           /* 0x14 */
+	volatile unsigned int	NFCR6;           /* 0x18 */
+	volatile unsigned int	NFCR7;           /* 0x1c */
+	volatile unsigned int	NFCR8;           /* 0x20 */
+	volatile unsigned int	NFCR9;           /* 0x24 */
+	volatile unsigned int NFCRa;           /* 0x28 */
+	volatile unsigned int	NFCRb;           /* 0x2c */
+	volatile unsigned int	NFCRc;           /* 0x30 */
+	volatile unsigned int	NFCRd;           /* 0x34 */
+	volatile unsigned int NFCRe;           /* 0x38 */
+	volatile unsigned int NFCRf;           /* 0x3c */
+	volatile unsigned int NFCR10;          /* 0x40 */
+	volatile unsigned int NFCR11;          /* 0x44 */
+	volatile unsigned int NFCR12;          /* 0x48 */
+	volatile unsigned int NFCR13;          /* 0x4c */
+	volatile unsigned int NFCR14;          /* 0x50 */
+	volatile unsigned int NFCR15;          /* 0x54 */
+	volatile unsigned int NFCR16;          /* 0x58 */
+	volatile unsigned int NFCR17;          /* 0x5c */
+	volatile unsigned int NFCR18;          /* 0x60 */
+	volatile unsigned int NFCR19;          /* 0x64 */
+	volatile unsigned int NFCR1a;          /* 0x68 */
+	volatile unsigned int NFCR1b;          /* 0x6c */
+	volatile unsigned int NFCR1c;          /* 0x70 */
+	volatile unsigned int NFCR1d;          /* 0x74 */
+	volatile unsigned int NFCR1e;          /* 0x78 */
+	volatile unsigned int NFCR1f;          /* 0x7c */
+	volatile unsigned int NFCR20;          /* 0x80 */
+	volatile unsigned int NFCR21;          /* 0x84 */
+	volatile unsigned int NFCR22;          /* 0x88 */
+	volatile unsigned int NFCR23;          /* 0x8c */
+	volatile unsigned int NFCR24;          /* 0x90 */
+	volatile unsigned int NFCR25;          /* 0x94 */
+	volatile unsigned int NFCR26;          /* 0x98 */
+	volatile unsigned int NFCR27;          /* 0x9c */
+	volatile unsigned int NFCR28;          /* 0xa0 */
+	volatile unsigned int NFCR29;          /* 0xa4 */
+	volatile unsigned int NFCR2a;          /* 0xa8 */
+	volatile unsigned int NFCR2b;          /* 0xac */
+	volatile unsigned int NFCR2c;          /* 0xb0 */
+	volatile unsigned int NFCR2d;          /* 0xb4 */
+	volatile unsigned int NFCR2e;          /* 0xb8 */
+	volatile unsigned int NFCR2f;          /* 0xbc */
+	volatile unsigned int NFCR30;					 /* 0xc0 */
+	volatile unsigned int NFCR31;					 /* 0xc4 */
+	volatile unsigned int NFCR32;					 /* 0xc8 */
+	volatile unsigned int NFCR33;					 /* 0xcc */
+	volatile unsigned int NFCR34;					 /* 0xd0 */
+	volatile unsigned int NFCR35;					 /* 0xd4 */
+	volatile unsigned int resv1[10]; /* 0xcc ~ 0xfc */
+	volatile unsigned int DMA_GCR;  /* 0x100 */
+	volatile unsigned int DMA_IER;  /* 0x104 */
+	volatile unsigned int DMA_ISR;  /* 0x108 */
+	volatile unsigned int DMA_DESPR;/* 0x10C */
+	volatile unsigned int DMA_RBR;  /* 0x110 */
+	volatile unsigned int DMA_DAR;  /* 0x114 */
+	volatile unsigned int DMA_BAR;  /* 0x118 */
+	volatile unsigned int DMA_CPR;  /* 0x11C */
+	volatile unsigned int DMA_CCR;  /* 0x120 */
+	volatile unsigned int resv2[39];	/* 0x124 ~ 0x1BC */
+	volatile unsigned char FIFO[64]; /* 0x1C0 ~ 0x1FC */
+} WMT_NFC_CFG, *WMT_PNFC_CFG;
+
+typedef struct WMTNF_INFO_s {
+	unsigned int 	id;
+	unsigned int 	oobblock;
+	unsigned int	oobsize;
+	unsigned int	page_shift;
+	unsigned int	totblk;
+	unsigned int	erasesize;
+	unsigned int  col; /* addr_cycle; */
+	unsigned int  row; /* page_cycle; */
+	unsigned int 	page[2];
+	unsigned int  bbpos;
+	//struct WMT_nand_flash_dev *nand_dev_info;
+	int (*nfc_read_page)(unsigned int start, unsigned int maddr, unsigned int len);
+	int (*update_table_inflash)(unsigned int last);
+	int (*update_table_inram)(unsigned int addr);
+	int (*isbadblock)(unsigned int addr);
+} WMTNF_INFO_t;
+
+typedef struct nand_oob_s {
+	unsigned int   dwReserved1;   /* Reserved - used by FAL */
+	unsigned char  bOEMReserved;  /* For use by OEM */
+	unsigned char  bBadBlock;     /* Indicates if block is BAD */
+	unsigned int   dwReserved2;   /* Reserved - used by FAL */
+} nand_oob_t;
+
+typedef struct WMTNAND_ID_s {
+	unsigned int 	manuf_code;
+	unsigned int 	dev_code;
+	unsigned int  width;
+	unsigned int 	oobblock;
+	unsigned int  oobsize;
+	unsigned int	totblk;
+	unsigned int	erasesize;
+	unsigned int  totcycles;
+	unsigned int  bbpos1;
+	unsigned int  bbpos2;
+} WMTNAND_ID_t;
+
+struct ECC_size_info{
+	int ecc_engine;
+	int banks;
+	int max_bit_error;
+	int oob_max_bit_error;
+	int ecc_bits_count;
+	int oob_ecc_bits_count;
+	int bank_offset; /* add data + data ecc ex: 512+8 4-bit engine */
+	int ECC_bytes;
+	int oob_ECC_bytes;
+	int unprotect;
+};
+
+struct NFC_RW_T{
+	unsigned int	T_R_setup;
+	unsigned int	T_R_hold;
+	unsigned int	T_W_setup;
+	unsigned int	T_W_hold;
+	unsigned int	divisor;
+	unsigned int	T_TADL;
+	unsigned int	T_TWHR;
+	unsigned int	T_TWB;
+	unsigned int	T_RHC_THC;
+};
+
+/*
+ *	NAND PDMA
+ */
+#define NAND_PDMA_BASE_ADDR 0xD8009100
+#define NAND_DESC_BASE_ADDR 0x00D00000
+typedef struct _NAND_PDMA_REG_ {
+	volatile unsigned long DMA_GCR;		/*	Rx00	*/
+	volatile unsigned long DMA_IER;		/*	Rx04	*/
+	volatile unsigned long DMA_ISR;		/*	Rx08	*/
+	volatile unsigned long DMA_DESPR;	/*	Rx0C	*/
+	volatile unsigned long DMA_RBR;		/*	Rx10	*/
+	volatile unsigned long DMA_DAR;		/*	Rx14	*/
+	volatile unsigned long DMA_BAR;		/*	Rx18	*/
+	volatile unsigned long DMA_CPR;		/*	Rx1C	*/
+	volatile unsigned long DMA_CCR;		/*	RX20	*/
+	volatile unsigned long resv[5];  	/*	RX2C-3C	*/
+} NAND_PDMA_REG;	
+//} NAND_PDMA_REG, *PNAND_PDMA_REG;
+
+/*
+ *	NAND PDMA - DMA_GCR : DMA Global Control Register
+ */
+#define NAND_PDMA_GCR_DMA_EN			0x00000001      /* [0] -- DMA controller enable */
+#define NAND_PDMA_GCR_SOFTRESET		0x00000100      /* [8] -- Software rest */
+
+/*
+ *	NAND PDMA - DMA_IER : DMA Interrupt Enable Register
+ */
+#define NAND_PDMA_IER_INT_EN			0x00000001      /* [0] -- DMA interrupt enable */
+/*
+ *	NAND PDMA - DMA_ISR : DMA Interrupt Status Register
+ */
+#define NAND_PDMA_IER_INT_STS			0x00000001      /* [0] -- DMA interrupt status */
+/*
+ *	NAND PDMA - DMA_DESPR : DMA Descriptor base address Pointer Register
+ */
+
+/*
+ *	NAND PDMA - DMA_RBR : DMA Residual Bytes Register
+ */
+#define NAND_PDMA_RBR_End				0x80000000      /* [31] -- DMA descriptor end flag */
+#define NAND_PDMA_RBR_Format			0x40000000      /* [30] -- DMA descriptor format */
+/*
+ *	NAND PDMA - DMA_DAR : DMA Data Address Register
+ */
+
+/*
+ *	NAND PDMA - DMA_BAR : DMA Rbanch Address Register
+ */
+
+/*
+ *	NAND PDMA - DMA_CPR : DMA Command Pointer Register
+ */
+
+/*
+ *	NAND PDMA - DMA_CCR : DMAContext Control Register for Channel 0
+ */
+#define NAND_PDMA_READ					0x00
+#define NAND_PDMA_WRITE					0x01
+#define NAND_PDMA_CCR_RUN					0x00000080
+#define NAND_PDMA_CCR_IF_to_peripheral	0x00000000
+#define NAND_PDMA_CCR_peripheral_to_IF	0x00400000
+#define NAND_PDMA_CCR_EvtCode				0x0000000f
+#define NAND_PDMA_CCR_Evt_no_status		0x00000000
+#define NAND_PDMA_CCR_Evt_ff_underrun		0x00000001
+#define NAND_PDMA_CCR_Evt_ff_overrun		0x00000002
+#define NAND_PDMA_CCR_Evt_desp_read		0x00000003
+#define NAND_PDMA_CCR_Evt_data_rw			0x00000004
+#define NAND_PDMA_CCR_Evt_early_end		0x00000005
+#define NAND_PDMA_CCR_Evt_success			0x0000000f
+
+/*
+ *	PDMA Descriptor short
+ */
+typedef struct _NAND_PDMA_DESC_S{
+	unsigned long volatile ReqCount:16;		/* bit 0 -15 -Request count             */
+	unsigned long volatile i:1;				/* bit 16    -interrupt                 */
+	unsigned long volatile reserve:13;		/* bit 17-29 -reserved                  */
+	unsigned long volatile format:1;		/* bit 30    -The descriptor format     */
+	unsigned long volatile end:1;			/* bit 31    -End flag of descriptor list*/
+	unsigned long volatile DataBufferAddr:32;/* bit 31    -Data Buffer address       */
+} NAND_PDMA_DESC_S;
+//} NAND_PDMA_DESC_S, *PNAND_PDMA_DESC_S;
+
+/*
+ *	PDMA Descriptor long
+ */
+typedef struct _NAND_PDMA_DESC_L{
+	unsigned long volatile ReqCount:16;		/* bit 0 -15 -Request count             */
+	unsigned long volatile i:1;				/* bit 16    -interrupt                 */
+	unsigned long volatile reserve:13;		/* bit 17-29 -reserved                  */
+	unsigned long volatile format:1;		/* bit 30    -The descriptor format     */
+	unsigned long volatile end:1;			/* bit 31    -End flag of descriptor list*/
+	unsigned long volatile DataBufferAddr:32;/* bit 31-0  -Data Buffer address       */
+	unsigned long volatile BranchAddr:32;	/* bit 31-2  -Descriptor Branch address	*/
+	unsigned long volatile reserve0:32;		/* bit 31-0  -reserved */
+} NAND_PDMA_DESC_L;
+//} NAND_PDMA_DESC_L, *PNAND_PDMA_DESC_L;
+
+#define SOURCE_CLOCK 24
+#define MAX_SPEED_MHZ 96
+#define MAX_READ_DELAY 15 /* 13.46 = tSKEW 7.07 + tDLY 5.99 + tSETUP 0.4 */
+#define MAX_WRITE_DELAY 1 /* -0.2 = tDLY 6.71 - tSKEW 6.91*/
+
+#define DMA_SINGNAL 0
+#define DMA_INC4 0x10
+#define DMA_INC8 0x20
+
+#define ECC1bit 0
+#define ECC4bit 1
+#define ECC8bit 2
+#define ECC12bit 3
+#define ECC16bit 4
+#define ECC24bitPer1K 5
+#define ECC40bitPer1K 6
+#define ECC60bitPer1K 7
+#define ECC44bitPer1K 7
+#define ECC44bit 8
+#define ECC1bit_bit_count 32
+#define ECC4bit_bit_count 52
+#define ECC8bit_bit_count 104
+#define ECC12bit_bit_count 156
+#define ECC16bit_bit_count 208
+#define ECC24bitPer1K_bit_count 336
+#define ECC40bitPer1K_bit_count 560
+#define ECC60bitPer1K_bit_count 830
+#define ECC44bitPer1K_bit_count 616
+#define ECC44bit_bit_count 576
+#define ECC1bit_byte_count 4
+#define ECC4bit_byte_count 8
+#define ECC8bit_byte_count 16
+#define ECC12bit_byte_count 20
+#define ECC16bit_byte_count 26
+#define ECC24bitPer1K_byte_count 42
+#define ECC40bitPer1K_byte_count 70
+#define ECC60bitPer1K_byte_count 106
+#define ECC44bitPer1K_byte_count 77
+#define ECC44bit_byte_count 72
+#define ECC1bit_unprotect 0
+#define ECC4bit_unprotect 0
+#define ECC8bit_unprotect 50
+#define ECC12bit_unprotect 14
+#define ECC16bit_unprotect 26
+#define ECC24bitPer1K_unprotect 34
+#define ECC40bitPer1K_unprotect 14
+#define ECC60bitPer1K_unprotect 46	//8k+960
+#define ECC44bitPer1K_unprotect 14
+#define ECC44bit_unprotect 72
+#define ECC_MOD_SEL 7
+#define MAX_ERR_BIT 60
+
+#define NAND_RESERVED 0xFE
+#define NAND_LARGE_RESERVED_OFS 8
+#define NAND_SMALL_RESERVED_OFS 7
+#define NAND_DWRESERVED1 0x54424C30
+#define NAND_LARGE_DWRESERVED1_OFS 4
+#define NAND_SMALL_DWRESERVED1_OFS 0
+#define NAND_DWRESERVED2 0x30
+#define NAND_LARGE_DWRESERVED2_OFS 0
+#define NAND_SMALL_DWRESERVED2_OFS 14
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+/* err define */
+#define ERR_NFC_CMD  1
+#define ERR_NAND_IDLE  2
+#define ERR_DMA_CFG 3
+#define ERR_NAND_READY  4
+#define ERR_NFC_READY  5
+#define ERR_NO_BBT	   6
+#define ERR_NAND_UNKNOW 7
+#define ERR_NOT_SUPPORT 8
+#define ERR_ECC_UNCORRECT 9
+#define ERR_ECC_BANK	10
+#define ERR_UNKNOW 11
+#define ERR_NAND_BOUND 12
+#define ERR_BBT_BAD 13
+
+#define ERR_IMAGE_FORMAT 13
+/* nand id */
+#define NAND_HYNIX 0xad
+//#define NAND_HYNIX_new 0x2c
+#define NAND_SAMSUNG 0xec
+#define NAND_TOSHIBA 0x98
+#define NAND_SANDISK 0x45
+#define NAND_MICRON 0x2c
+#define NAND_INTEL 0x89
+#define NAND_MXIC 0xC2
+#define NAND_MIRA 0x92
+#define NAND_UNKONW 0x00
+
+#define ECC_1bit_ERR 0x02
+
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_READ0		0
+#define NAND_READ1		1
+#define NAND_READ2		0x50
+#define NAND_PAGEPROG	0x10
+#define NAND_ERASE_SET	0x60
+#define NAND_STATUS		0x70
+#define NAND_MULTI_STATUS	0x71
+#define NAND_SEQIN		0x80
+#define NAND_READID		0x90
+#define NAND_ERASE_CONFIRM		0xd0
+#define NAND_RESET		0xff
+
+#define NAND_SET_PARAM 0x36
+#define NAND_GET_PARAM 0x37
+#define	NAND_READ_CONFIRM 0x30
+#define	NAND_DUMMY_READ 0x03
+#define NAND_DUMMY_PAGEPROG 0x11
+#define NAND_CMD_COPYBACK 0x8A
+
+/* Standard NAND Status bits */
+#define NAND_STATUS_FAIL	0x01
+#define PLANE0_FAIL				0x02
+#define PLANE1_FAIL				0x04
+#define PLANE2_FAIL				0x08
+#define PLANE3_FAIL				0x10
+#define NAND_STATUS_PER 	0x20
+#define NAND_STATUS_READY	0x40
+#define NAND_STATUS_NP		0x80
+
+/* cfg_1 */
+#define TWHR 0x800
+#define OLD_CMD 0x400
+#define DPAHSE_DISABLE 0x80 /*disable data phase */
+#define NAND2NFC  0x40  /* direction : nand to controller */
+#define SING_RW	0x20 /*	enable signal read/ write command */
+#define MUL_CMDS 0x10  /*  support cmd+addr+cmd */
+#define NFC_TRIGGER 0x01 /* start cmd&addr sequence */
+/*cfg_9 */
+#define READ_RESUME 0x100
+#define ECC_INT_EN 0x60
+#define BANK_DR     0x10
+#define DIS_BCH_ECC 0x8
+#define USE_SW_ECC 0x08
+#define USE_HW_ECC 0
+#define ECC_MOD_SEL 7
+/*cfg_a */
+#define NFC_CMD_RDY 0x04
+#define NFC_BUSY	0x02  /* command and data is being transfer in flash I/O */
+#define FLASH_RDY 0x01  /* flash is ready */
+/*cfg_b */
+#define B2R	0x08 /* status form busy to ready */
+#define ERR_CORRECT 0x2
+#define BCH_ERR     0x1
+/*cfg_d */
+#define RED_DIS	0x2
+#define OOB_READ	0x4 /* calculate the side info BCH decoder */
+#define HIGH64FIFO 8 /* read high 64 bytes fifo */
+/*cfg_f */
+#define RDMZ 0x10000 /* enable randomizer */
+#define RDMZH 1	/* enable randomizer */
+/*cfg_12 */
+#define PAGE_512 0
+#define PAGE_2K 1
+#define PAGE_4K 2
+#define PAGE_8K 3
+#define PAGE_16K 4
+#define PAGE_32K 5
+#define WD8 0
+#define WIDTH_16	(1<<3)
+#define WP_DISABLE (1<<4) /*disable write protection */
+#define DIRECT_MAP (1<<5)
+#define RD_DLY (1<<6)
+#define TOGGLE (1<<7)
+/*cfg_13*/				 /* Dannier Add */
+#define B2RMEN	0x08	 /* interrupt mask enable of nand flash form busy to ready */
+/*cfg_15 */
+#define NFC_IDLE	0x01
+/*cfg_17 status */
+#define BANK_NUM    0x1F00
+#define BCH_ERR_CNT 0x3F
+/*cfg_18 */
+#define BCH_ERRPOS0 0x3fff
+#define BCH_ERRPOS1 (BCH_ERRPOS0<<16)
+
+
+#define FLASH_UNKNOW 0xFFFF
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0		0
+#define NAND_CMD_READ1		1
+#define NAND_CMD_READ2		0x50
+#define NAND_CMD_PAGEPROG	0x10
+#define NAND_CMD_ERASE1		0x60
+#define NAND_CMD_STATUS		0x70
+#define NAND_CMD_MULTI_STATUS	0x71
+#define NAND_CMD_SEQIN		0x80
+#define NAND_CMD_READID		0x90
+#define NAND_CMD_ERASE2		0xd0
+#define NAND_CMD_RESET		0xff
+#define NAND_CMD_RANDOM_DATA_IN 0x85
+
+#define	NAND_DUMMY_READ 0x03
+#define NAND_DUMMY_PAGEPROG 0x11
+#define NAND_CMD_COPYBACK 0x8A
+#define NAND_LAG_READ		0x30
+
+/*
+ * Support Nand special commands
+ */
+#define CACHE_READ							(1<<0)
+#define CACHE_PROG							(1<<1)
+#define COPY_BACK								(1<<2)
+#define INTEL_COPY_BACK					(1<<3)
+#define RANDOM_INPUT						(1<<4)
+#define RANDOM_OUTPUT						(1<<5)
+#define PLANE2_READ							(1<<6)
+#define PLANE2_PROG							(1<<7)
+#define PLANE2_CACHE_READ				(1<<8)
+#define PLANE2_CACHE_PROG				(1<<9)
+#define PLANE2_COPY_BACK				(1<<10)
+#define PLANE2_INTEL_COPY_BACK	(1<<11)
+#define PLANE2_RANDOM_OUTPUT		(1<<12)
+#define PLANE2_ERASE						(1<<13)
+
+#define PLANE4_READ							(1<<16)
+#define PLANE4_PROG							(1<<17)
+#define PLANE4_CACHE_READ				(1<<18)
+#define PLANE4_CACHE_PROG				(1<<19)
+#define PLANE4_COPY_BACK				(1<<20)
+#define PLANE4_INTEL_COPY_BACK	(1<<21)
+#define PLANE4_RANDOM_OUTPUT		(1<<22)
+#define PLANE4_ERASE						(1<<23)
+
+/* Status bits */
+#define NAND_STATUS_ERR	0x01
+
+#define NAND_CMD_HYNIX_RETRY_END 0x38
+
+/* #define TEST_FUN */
+
+#ifdef TEST_FUN
+#define __OST_BASE  0xD8130100    /* OS Timers base address */
+
+typedef struct nand_ost_regs_s {
+	unsigned int volatile OSMR[4];  /* Match Register 0-3        */
+	unsigned int volatile OSCR;     /* Count Register            */
+	unsigned int volatile OSTS;     /* Status Register           */
+	unsigned int volatile OSTW;     /* Watchdog Enable Register  */
+	unsigned int volatile OSTI;     /* Interrupt Enable Register */
+	unsigned int volatile OSTC;     /* Control Register          */
+	unsigned int volatile OSTA;     /* Access Status Register    */
+} nand_ost_regs_t;
+
+/* for ecc test */
+/* we setup max 5 error to test */
+typedef struct ecc_test_info_s {
+	unsigned int err_cnt;
+	unsigned int pos[5];
+} ecc_test_info_t;
+
+int post_write_test(unsigned int size, unsigned int cnt);
+int post_read_test(unsigned int size, unsigned int cnt);
+void nand_read_counter(unsigned int *data);
+unsigned int hex2dec(unsigned int hex);
+int post_rw_one(unsigned int type);
+int post_rw_comp(unsigned int size, unsigned int cnt, unsigned int type, unsigned int type1);
+int post_table_test(unsigned int type);
+unsigned int creat_bch_pattern(unsigned char *fifo, ecc_test_info_t info,
+		unsigned int oob, unsigned char *buf);
+int post_bch_program(unsigned int *naddr, unsigned int first, unsigned int maddr);
+int post_test_bch(unsigned int count, unsigned int oob);
+int post_comp_bch(unsigned int src, unsigned int dest);
+int post_read_by_bank(unsigned int start, unsigned int maddr, unsigned int len, unsigned char *fifo);
+#endif
+
+/*
+ *	PDMA API
+ */
+int nand_init_pdma(void);
+int nand_free_pdma(void);
+int nand_alloc_desc_pool(unsigned long *DescAddr);
+int nand_init_short_desc(unsigned long *DescAddr, unsigned int ReqCount, unsigned long *BufferAddr, int End);
+int nand_init_long_desc(unsigned long *DescAddr, unsigned int ReqCount, unsigned long *BufferAddr,
+unsigned long *BranchAddr, int End);
+int nand_config_pdma(unsigned long *DescAddr, unsigned int dir);
+int nand_pdma_handler(void);
+#endif
diff --git a/include/net.h b/include/net.h
new file mode 100755
index 0000000..0efcb3f
--- /dev/null
+++ b/include/net.h
@@ -0,0 +1,521 @@
+/*
+ *	LiMon Monitor (LiMon) - Network.
+ *
+ *	Copyright 1994 - 2000 Neil Russell.
+ *	(See License)
+ *
+ *
+ * History
+ *	9/16/00	  bor  adapted to TQM823L/STK8xxL board, RARP/TFTP boot added
+ */
+
+#ifndef __NET_H__
+#define __NET_H__
+
+#if defined(CONFIG_8xx)
+#include <commproc.h>
+# if !defined(CONFIG_NET_MULTI)
+#  if defined(FEC_ENET) || defined(SCC_ENET)
+#   define CONFIG_NET_MULTI
+#  endif
+# endif
+#endif	/* CONFIG_8xx */
+
+#if defined(CONFIG_MPC5xxx)
+# if !defined(CONFIG_NET_MULTI)
+#  if defined(CONFIG_MPC5xxx_FEC)
+#   define CONFIG_NET_MULTI
+#  endif
+# endif
+#endif	/* CONFIG_MPC5xxx */
+
+#if !defined(CONFIG_NET_MULTI) && defined(CONFIG_CPM2)
+#include <config.h>
+#if defined(CONFIG_ETHER_ON_FCC)
+#if defined(CONFIG_ETHER_ON_SCC)
+#error "Ethernet not correctly defined"
+#endif /* CONFIG_ETHER_ON_SCC */
+#define CONFIG_NET_MULTI
+#if (CONFIG_ETHER_INDEX == 1)
+#define	CONFIG_ETHER_ON_FCC1
+# define CFG_CMXFCR_MASK1	CFG_CMXFCR_MASK
+# define CFG_CMXFCR_VALUE1	CFG_CMXFCR_VALUE
+#elif (CONFIG_ETHER_INDEX == 2)
+#define	CONFIG_ETHER_ON_FCC2
+# define CFG_CMXFCR_MASK2	CFG_CMXFCR_MASK
+# define CFG_CMXFCR_VALUE2	CFG_CMXFCR_VALUE
+#elif (CONFIG_ETHER_INDEX == 3)
+#define	CONFIG_ETHER_ON_FCC3
+# define CFG_CMXFCR_MASK3	CFG_CMXFCR_MASK
+# define CFG_CMXFCR_VALUE3	CFG_CMXFCR_VALUE
+#endif /* CONFIG_ETHER_INDEX */
+#endif /* CONFIG_ETHER_ON_FCC */
+#endif /* !CONFIG_NET_MULTI && CONFIG_8260 */
+
+#include <asm/byteorder.h>	/* for nton* / ntoh* stuff */
+
+
+/*
+ *	The number of receive packet buffers, and the required packet buffer
+ *	alignment in memory.
+ *
+ */
+
+#ifdef CFG_RX_ETH_BUFFER
+# define PKTBUFSRX	CFG_RX_ETH_BUFFER
+#else
+# define PKTBUFSRX	4
+#endif
+
+#define PKTALIGN	32
+
+typedef ulong		IPaddr_t;
+
+
+/*
+ * The current receive packet handler.  Called with a pointer to the
+ * application packet, and a protocol type (PORT_BOOTPC or PORT_TFTP).
+ * All other packets are dealt with without calling the handler.
+ */
+typedef void	rxhand_f(uchar *, unsigned, unsigned, unsigned);
+
+/*
+ *	A timeout handler.  Called after time interval has expired.
+ */
+typedef void	thand_f(void);
+
+#define NAMESIZE 16
+
+enum eth_state_t {
+	ETH_STATE_INIT,
+	ETH_STATE_PASSIVE,
+	ETH_STATE_ACTIVE
+};
+
+struct eth_device {
+	char name[NAMESIZE];
+	unsigned char enetaddr[6];
+	int iobase;
+	int state;
+
+	int  (*init) (struct eth_device*, bd_t*);
+	int  (*send) (struct eth_device*, volatile void* pachet, int length);
+	int  (*recv) (struct eth_device*);
+	void (*halt) (struct eth_device*);
+
+	int  (*write_hwaddr) (struct eth_device*);
+	struct eth_device *next;
+	void *priv;
+};
+
+extern int eth_initialize(bd_t *bis);		/* Initialize network subsystem */
+extern int eth_register(struct eth_device* dev);/* Register network device	*/
+extern void eth_try_another(int first_restart);	/* Change the device		*/
+#ifdef CONFIG_NET_MULTI
+extern void eth_set_current(void);		/* set nterface to ethcur var.  */
+#endif
+extern struct eth_device *eth_get_dev(void);	/* get the current device MAC	*/
+extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device	*/
+extern struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */
+extern int eth_get_dev_index (void);		/* get the device index         */
+extern void eth_parse_enetaddr(const char *addr, uchar *enetaddr);
+extern void eth_set_enetaddr(int num, char* a);	/* Set new MAC address		*/
+extern int eth_getenv_enetaddr(char *name, uchar *enetaddr);
+extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr);
+extern int eth_getenv_enetaddr_by_index(const char *base_name, int index,
+					uchar *enetaddr);
+
+extern int usb_eth_initialize(bd_t *bi);
+extern int eth_init(bd_t *bis);			/* Initialize the device	*/
+extern int eth_send(volatile void *packet, int length);	   /* Send a packet	*/
+extern int eth_rx(void);			/* Check for received packets	*/
+extern void eth_halt(void);			/* stop SCC			*/
+extern char *eth_get_name(void);		/* get name of current device	*/
+int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
+		     int eth_number);
+
+
+/**********************************************************************/
+/*
+ *	Protocol headers.
+ */
+
+/*
+ *	Ethernet header
+ */
+typedef struct {
+	uchar		et_dest[6];	/* Destination node		*/
+	uchar		et_src[6];	/* Source node			*/
+	ushort		et_protlen;	/* Protocol or length		*/
+	uchar		et_dsap;	/* 802 DSAP			*/
+	uchar		et_ssap;	/* 802 SSAP			*/
+	uchar		et_ctl;		/* 802 control			*/
+	uchar		et_snap1;	/* SNAP				*/
+	uchar		et_snap2;
+	uchar		et_snap3;
+	ushort		et_prot;	/* 802 protocol			*/
+} Ethernet_t;
+
+#define ETHER_HDR_SIZE	14		/* Ethernet header size		*/
+#define E802_HDR_SIZE	22		/* 802 ethernet header size	*/
+
+/*
+ *	Ethernet header
+ */
+typedef struct {
+	uchar		vet_dest[6];	/* Destination node		*/
+	uchar		vet_src[6];	/* Source node			*/
+	ushort		vet_vlan_type;	/* PROT_VLAN			*/
+	ushort		vet_tag;	/* TAG of VLAN			*/
+	ushort		vet_type;	/* protocol type		*/
+} VLAN_Ethernet_t;
+
+#define VLAN_ETHER_HDR_SIZE	18	/* VLAN Ethernet header size	*/
+
+#define PROT_IP		0x0800		/* IP protocol			*/
+#define PROT_ARP	0x0806		/* IP ARP protocol		*/
+#define PROT_RARP	0x8035		/* IP ARP protocol		*/
+#define PROT_VLAN	0x8100		/* IEEE 802.1q protocol		*/
+
+#define IPPROTO_ICMP	 1	/* Internet Control Message Protocol	*/
+#define IPPROTO_UDP	17	/* User Datagram Protocol		*/
+
+/*
+ *	Internet Protocol (IP) header.
+ */
+typedef struct {
+	uchar		ip_hl_v;	/* header length and version	*/
+	uchar		ip_tos;		/* type of service		*/
+	ushort		ip_len;		/* total length			*/
+	ushort		ip_id;		/* identification		*/
+	ushort		ip_off;		/* fragment offset field	*/
+	uchar		ip_ttl;		/* time to live			*/
+	uchar		ip_p;		/* protocol			*/
+	ushort		ip_sum;		/* checksum			*/
+	IPaddr_t	ip_src;		/* Source IP address		*/
+	IPaddr_t	ip_dst;		/* Destination IP address	*/
+	ushort		udp_src;	/* UDP source port		*/
+	ushort		udp_dst;	/* UDP destination port		*/
+	ushort		udp_len;	/* Length of UDP packet		*/
+	ushort		udp_xsum;	/* Checksum			*/
+} IP_t;
+
+#define IP_HDR_SIZE_NO_UDP	(sizeof (IP_t) - 8)
+#define IP_HDR_SIZE		(sizeof (IP_t))
+
+
+/*
+ *	Address Resolution Protocol (ARP) header.
+ */
+typedef struct
+{
+	ushort		ar_hrd;		/* Format of hardware address	*/
+#   define ARP_ETHER	    1		/* Ethernet  hardware address	*/
+	ushort		ar_pro;		/* Format of protocol address	*/
+	uchar		ar_hln;		/* Length of hardware address	*/
+	uchar		ar_pln;		/* Length of protocol address	*/
+	ushort		ar_op;		/* Operation			*/
+#   define ARPOP_REQUEST    1		/* Request  to resolve  address	*/
+#   define ARPOP_REPLY	    2		/* Response to previous request	*/
+
+#   define RARPOP_REQUEST   3		/* Request  to resolve  address	*/
+#   define RARPOP_REPLY	    4		/* Response to previous request */
+
+	/*
+	 * The remaining fields are variable in size, according to
+	 * the sizes above, and are defined as appropriate for
+	 * specific hardware/protocol combinations.
+	 */
+	uchar		ar_data[0];
+#if 0
+	uchar		ar_sha[];	/* Sender hardware address	*/
+	uchar		ar_spa[];	/* Sender protocol address	*/
+	uchar		ar_tha[];	/* Target hardware address	*/
+	uchar		ar_tpa[];	/* Target protocol address	*/
+#endif /* 0 */
+} ARP_t;
+
+#define ARP_HDR_SIZE	(8+20)		/* Size assuming ethernet	*/
+
+/*
+ * ICMP stuff (just enough to handle (host) redirect messages)
+ */
+#define ICMP_ECHO_REPLY		0	/* Echo reply 			*/
+#define ICMP_REDIRECT		5	/* Redirect (change route)	*/
+#define ICMP_ECHO_REQUEST	8	/* Echo request			*/
+
+/* Codes for REDIRECT. */
+#define ICMP_REDIR_NET		0	/* Redirect Net			*/
+#define ICMP_REDIR_HOST		1	/* Redirect Host		*/
+
+typedef struct icmphdr {
+	uchar		type;
+	uchar		code;
+	ushort		checksum;
+	union {
+		struct {
+			ushort	id;
+			ushort	sequence;
+		} echo;
+		ulong	gateway;
+		struct {
+			ushort	__unused;
+			ushort	mtu;
+		} frag;
+	} un;
+} ICMP_t;
+
+
+/*
+ * Maximum packet size; used to allocate packet storage.
+ * TFTP packets can be 524 bytes + IP header + ethernet header.
+ * Lets be conservative, and go for 38 * 16.  (Must also be
+ * a multiple of 32 bytes).
+ */
+/*
+ * AS.HARNOIS : Better to set PKTSIZE to maximum size because
+ * traffic type is not always controlled
+ * maximum packet size =  1518
+ * maximum packet size and multiple of 32 bytes =  1536
+ */
+#define PKTSIZE			1518
+#define PKTSIZE_ALIGN		1536
+/*#define PKTSIZE		608*/
+
+/*
+ * Maximum receive ring size; that is, the number of packets
+ * we can buffer before overflow happens. Basically, this just
+ * needs to be enough to prevent a packet being discarded while
+ * we are processing the previous one.
+ */
+#define RINGSZ		4
+#define RINGSZ_LOG2	2
+
+/**********************************************************************/
+/*
+ *	Globals.
+ *
+ * Note:
+ *
+ * All variables of type IPaddr_t are stored in NETWORK byte order
+ * (big endian).
+ */
+
+/* net.c */
+/** BOOTP EXTENTIONS **/
+extern IPaddr_t		NetOurGatewayIP;	/* Our gateway IP addresse	*/
+extern IPaddr_t		NetOurSubnetMask;	/* Our subnet mask (0 = unknown)*/
+extern IPaddr_t		NetOurDNSIP;	 /* Our Domain Name Server (0 = unknown)*/
+#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2)
+extern IPaddr_t		NetOurDNS2IP;	 /* Our 2nd Domain Name Server (0 = unknown)*/
+#endif
+extern char		NetOurNISDomain[32];	/* Our NIS domain		*/
+extern char		NetOurHostName[32];	/* Our hostname			*/
+extern char		NetOurRootPath[64];	/* Our root path		*/
+extern ushort		NetBootFileSize;	/* Our boot file size in blocks	*/
+/** END OF BOOTP EXTENTIONS **/
+extern ulong		NetBootFileXferSize;	/* size of bootfile in bytes	*/
+extern uchar		NetOurEther[6];		/* Our ethernet address		*/
+extern uchar		NetServerEther[6];	/* Boot server enet address	*/
+extern IPaddr_t		NetOurIP;		/* Our    IP addr (0 = unknown)	*/
+extern IPaddr_t		NetServerIP;		/* Server IP addr (0 = unknown)	*/
+extern volatile uchar * NetTxPacket;		/* THE transmit packet		*/
+extern volatile uchar * NetRxPackets[PKTBUFSRX];/* Receive packets		*/
+extern volatile uchar * NetRxPkt;		/* Current receive packet	*/
+extern int		NetRxPktLen;		/* Current rx packet length	*/
+extern unsigned		NetIPID;		/* IP ID (counting)		*/
+extern uchar		NetBcastAddr[6];	/* Ethernet boardcast address	*/
+extern uchar		NetEtherNullAddr[6];
+
+#define VLAN_NONE	4095			/* untagged 			*/
+#define VLAN_IDMASK	0x0fff			/* mask of valid vlan id 	*/
+extern ushort		NetOurVLAN;		/* Our VLAN 			*/
+extern ushort		NetOurNativeVLAN;	/* Our Native VLAN 		*/
+
+extern uchar		NetCDPAddr[6]; 		/* Ethernet CDP address		*/
+extern ushort		CDPNativeVLAN;		/* CDP returned native VLAN	*/
+extern ushort		CDPApplianceVLAN;	/* CDP returned appliance VLAN	*/
+
+extern int		NetState;		/* Network loop state		*/
+#define NETLOOP_CONTINUE	1
+#define NETLOOP_RESTART		2
+#define NETLOOP_SUCCESS		3
+#define NETLOOP_FAIL		4
+
+#ifdef CONFIG_NET_MULTI
+extern int		NetRestartWrap;		/* Tried all network devices	*/
+#endif
+
+typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP } proto_t;
+
+/* from net/net.c */
+extern char	BootFile[128];			/* Boot File name		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_PING)
+extern IPaddr_t	NetPingIP;			/* the ip address to ping 		*/
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_CDP)
+/* when CDP completes these hold the return values */
+extern ushort CDPNativeVLAN;
+extern ushort CDPApplianceVLAN;
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_SNTP)
+extern IPaddr_t	NetNtpServerIP;			/* the ip address to NTP 	*/
+extern int NetTimeOffset;			/* offset time from UTC		*/
+#endif
+
+/* Initialize the network adapter */
+extern int	NetLoop(proto_t);
+
+/* Shutdown adapters and cleanup */
+extern void	NetStop(void);
+
+/* Load failed.	 Start again. */
+extern void	NetStartAgain(void);
+
+/* Get size of the ethernet header when we send */
+extern int 	NetEthHdrSize(void);
+
+/* Set ethernet header; returns the size of the header */
+extern int	NetSetEther(volatile uchar *, uchar *, uint);
+
+/* Set IP header */
+extern void	NetSetIP(volatile uchar *, IPaddr_t, int, int, int);
+
+/* Checksum */
+extern int	NetCksumOk(uchar *, int);	/* Return true if cksum OK	*/
+extern uint	NetCksum(uchar *, int);		/* Calculate the checksum	*/
+
+/* Set callbacks */
+extern void	NetSetHandler(rxhand_f *);	/* Set RX packet handler	*/
+extern void	NetSetTimeout(ulong, thand_f *);/* Set timeout handler		*/
+
+/* Transmit "NetTxPacket" */
+extern void	NetSendPacket(volatile uchar *, int);
+
+/* Transmit UDP packet, performing ARP request if needed */
+extern int	NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport, int len);
+
+/* Processes a received packet */
+extern void	NetReceive(volatile uchar *, int);
+
+/* Print an IP address on the console */
+extern void	print_IPaddr (IPaddr_t);
+
+/*
+ * The following functions are a bit ugly, but necessary to deal with
+ * alignment restrictions on ARM.
+ *
+ * We're using inline functions, which had the smallest memory
+ * footprint in our tests.
+ */
+/* return IP *in network byteorder* */
+static inline IPaddr_t NetReadIP(void *from)
+{
+	IPaddr_t ip;
+	memcpy((void*)&ip, from, sizeof(ip));
+	return ip;
+}
+
+/* return ulong *in network byteorder* */
+static inline ulong NetReadLong(ulong *from)
+{
+	ulong l;
+	memcpy((void*)&l, (void*)from, sizeof(l));
+	return l;
+}
+
+/* write IP *in network byteorder* */
+static inline void NetWriteIP(void *to, IPaddr_t ip)
+{
+	memcpy(to, (void*)&ip, sizeof(ip));
+}
+
+/* copy IP */
+static inline void NetCopyIP(void *to, void *from)
+{
+	memcpy(to, from, sizeof(IPaddr_t));
+}
+
+/* copy ulong */
+static inline void NetCopyLong(ulong *to, ulong *from)
+{
+	memcpy((void*)to, (void*)from, sizeof(ulong));
+}
+
+/**
+ * is_zero_ether_addr - Determine if give Ethernet address is all zeros.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is all zeroes.
+ */
+static inline int is_zero_ether_addr(const u8 *addr)
+{
+	return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);
+}
+
+/**
+ * is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is a multicast address.
+ * By definition the broadcast address is also a multicast address.
+ */
+static inline int is_multicast_ether_addr(const u8 *addr)
+{
+	return (0x01 & addr[0]);
+}
+
+/*
+ * is_broadcast_ether_addr - Determine if the Ethernet address is broadcast
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is the broadcast address.
+ */
+static inline int is_broadcast_ether_addr(const u8 *addr)
+{
+	return (addr[0] & addr[1] & addr[2] & addr[3] & addr[4] & addr[5]) == 0xff;
+}
+
+/*
+ * is_valid_ether_addr - Determine if the given Ethernet address is valid
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not
+ * a multicast address, and is not FF:FF:FF:FF:FF:FF.
+ *
+ * Return true if the address is valid.
+ */
+static inline int is_valid_ether_addr(const u8 *addr)
+{
+	/* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to
+	 * explicitly check for it here. */
+	return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
+}
+
+/* Convert an IP address to a string */
+extern void	ip_to_string (IPaddr_t x, char *s);
+
+/* Convert a string to ip address */
+extern IPaddr_t string_to_ip(char *s);
+
+/* Convert a VLAN id to a string */
+extern void	VLAN_to_string (ushort x, char *s);
+
+/* Convert a string to a vlan id */
+extern ushort string_to_VLAN(char *s);
+
+/* read an IP address from a environment variable */
+extern IPaddr_t getenv_IPaddr (char *);
+
+/* read a VLAN id from an environment variable */
+extern ushort getenv_VLAN(char *);
+
+/* copy a filename (allow for "..." notation, limit length) */
+extern void	copy_filename (char *dst, char *src, int size);
+
+/**********************************************************************/
+
+#endif /* __NET_H__ */
diff --git a/include/nios-io.h b/include/nios-io.h
new file mode 100755
index 0000000..dc7e127
--- /dev/null
+++ b/include/nios-io.h
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * Altera Nios Standard Peripherals
+ ************************************************************************/
+
+#ifndef __NIOSIO_H__
+#define __NIOSIO_H__
+
+/*------------------------------------------------------------------------
+ * UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf)
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_uart_t {
+	unsigned	rxdata;		/* Rx data reg */
+	unsigned	txdata;		/* Tx data reg */
+	unsigned	status;		/* Status reg */
+	unsigned	control;	/* Control reg */
+	unsigned	divisor;	/* Baud rate divisor reg */
+	unsigned	endofpacket;	/* End-of-packet reg */
+}nios_uart_t;
+
+/* status register */
+#define NIOS_UART_PE		(1 << 0)	/* parity error */
+#define NIOS_UART_FE		(1 << 1)	/* frame error */
+#define NIOS_UART_BRK		(1 << 2)	/* break detect */
+#define NIOS_UART_ROE		(1 << 3)	/* rx overrun */
+#define NIOS_UART_TOE		(1 << 4)	/* tx overrun */
+#define NIOS_UART_TMT		(1 << 5)	/* tx empty */
+#define NIOS_UART_TRDY		(1 << 6)	/* tx ready */
+#define NIOS_UART_RRDY		(1 << 7)	/* rx ready */
+#define NIOS_UART_E		(1 << 8)	/* exception */
+#define NIOS_UART_DCTS		(1 << 10)	/* cts change */
+#define NIOS_UART_CTS		(1 << 11)	/* cts */
+#define NIOS_UART_EOP		(1 << 12)	/* eop detected */
+
+/* control register */
+#define NIOS_UART_IPE		(1 << 0)	/* parity error int ena*/
+#define NIOS_UART_IFE		(1 << 1)	/* frame error int ena */
+#define NIOS_UART_IBRK		(1 << 2)	/* break detect int ena */
+#define NIOS_UART_IROE		(1 << 3)	/* rx overrun int ena */
+#define NIOS_UART_ITOE		(1 << 4)	/* tx overrun int ena */
+#define NIOS_UART_ITMT		(1 << 5)	/* tx empty int ena */
+#define NIOS_UART_ITRDY		(1 << 6)	/* tx ready int ena */
+#define NIOS_UART_IRRDY		(1 << 7)	/* rx ready int ena */
+#define NIOS_UART_IE		(1 << 8)	/* exception int ena */
+#define NIOS_UART_TBRK		(1 << 9)	/* transmit break */
+#define NIOS_UART_IDCTS		(1 << 10)	/* cts change int ena */
+#define NIOS_UART_RTS		(1 << 11)	/* rts */
+#define NIOS_UART_IEOP		(1 << 12)	/* eop detected int ena */
+
+
+/*------------------------------------------------------------------------
+ * TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf)
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_timer_t {
+	unsigned	status;			/* Timer status reg */
+	unsigned	control;		/* Timer control reg */
+	unsigned	periodl;		/* Timeout period low */
+	unsigned	periodh;		/* Timeout period high */
+	unsigned	snapl;			/* Snapshot low */
+	unsigned	snaph;			/* Snapshot high */
+}nios_timer_t;
+
+/* status register */
+#define NIOS_TIMER_TO		(1 << 0)	/* Timeout */
+#define NIOS_TIMER_RUN		(1 << 1)	/* Timer running */
+
+/* control register */
+#define NIOS_TIMER_ITO		(1 << 0)	/* Timeout int ena */
+#define NIOS_TIMER_CONT		(1 << 1)	/* Continuous mode */
+#define NIOS_TIMER_START	(1 << 2)	/* Start timer */
+#define NIOS_TIMER_STOP		(1 << 3)	/* Stop timer */
+
+
+/*------------------------------------------------------------------------
+ * PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf)
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_pio_t {
+	unsigned int	data;		/* Data value at each PIO in/out */
+	unsigned int	direction;	/* Data direct. for each PIO bit */
+	unsigned int	interruptmask;	/* Per-bit IRQ enable/disable */
+	unsigned int	edgecapture;	/* Per-bit sync. edge detect & hold */
+}nios_pio_t;
+
+/* direction register */
+#define NIOS_PIO_OUT		(1)		/* PIO bit is output */
+#define NIOS_PIO_IN		(0)		/* PIO bit is input */
+
+
+/*------------------------------------------------------------------------
+ * SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf)
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_spi_t {
+	unsigned	rxdata;		/* Rx data reg */
+	unsigned	txdata;		/* Tx data reg */
+	unsigned	status;		/* Status reg */
+	unsigned	control;	/* Control reg */
+	unsigned	reserved;	/* (master only) */
+	unsigned	slaveselect;	/* SPI slave select mask (master only) */
+}nios_spi_t;
+
+/* status register */
+#define NIOS_SPI_ROE		(1 << 3)	/* rx overrun */
+#define NIOS_SPI_TOE		(1 << 4)	/* tx overrun */
+#define NIOS_SPI_TMT		(1 << 5)	/* tx empty */
+#define NIOS_SPI_TRDY		(1 << 6)	/* tx ready */
+#define NIOS_SPI_RRDY		(1 << 7)	/* rx ready */
+#define NIOS_SPI_E		(1 << 8)	/* exception */
+
+/* control register */
+#define NIOS_SPI_IROE		(1 << 3)	/* rx overrun int ena */
+#define NIOS_SPI_ITOE		(1 << 4)	/* tx overrun int ena */
+#define NIOS_SPI_ITRDY		(1 << 6)	/* tx ready int ena */
+#define NIOS_SPI_IRRDY		(1 << 7)	/* rx ready int ena */
+#define NIOS_SPI_IE		(1 << 8)	/* exception int ena */
+#define NIOS_SPI_SSO		(1 << 10)	/* override SS_n output */
+
+/*------------------------------------------------------------------------
+ * ASMI
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_asmi_t {
+	unsigned	rxdata;		/* Rx data reg */
+	unsigned	txdata;		/* Tx data reg */
+	unsigned	status;		/* Status reg */
+	unsigned	control;	/* Control reg */
+	unsigned	reserved;
+	unsigned	slavesel;	/* Slave select */
+	unsigned	endofpacket;	/* End-of-packet reg */
+}nios_asmi_t;
+
+/* status register */
+#define NIOS_ASMI_ROE		(1 << 3)	/* rx overrun */
+#define NIOS_ASMI_TOE		(1 << 4)	/* tx overrun */
+#define NIOS_ASMI_TMT		(1 << 5)	/* tx empty */
+#define NIOS_ASMI_TRDY		(1 << 6)	/* tx ready */
+#define NIOS_ASMI_RRDY		(1 << 7)	/* rx ready */
+#define NIOS_ASMI_E		(1 << 8)	/* exception */
+#define NIOS_ASMI_EOP		(1 << 9)	/* eop detected */
+
+/* control register */
+#define NIOS_ASMI_IROE		(1 << 3)	/* rx overrun int ena */
+#define NIOS_ASMI_ITOE		(1 << 4)	/* tx overrun int ena */
+#define NIOS_ASMI_ITRDY		(1 << 6)	/* tx ready int ena */
+#define NIOS_ASMI_IRRDY		(1 << 7)	/* rx ready int ena */
+#define NIOS_ASMI_IE		(1 << 8)	/* exception int ena */
+#define NIOS_ASMI_IEOP		(1 << 9)	/* rx eop int ena */
+#define NIOS_ASMI_SSO		(1 << 10)	/* slave select enable */
+
+/*------------------------------------------------------------------------
+ * JTAG UART
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_jtag_t {
+	unsigned short	rxcntl;			/* Rx data/cntl reg */
+	unsigned short	txcntl;			/* Tx data/cntl reg */
+	unsigned short	errcntl;		/* Err dta/cntl reg */
+}nios_jtag_t;
+
+/* status register */
+#define NIOS_JTAG_TRDY		(1 << 8)	/* tx ready bit */
+#define NIOS_JTAG_RRDY		(1 << 8)	/* rx ready bit */
+
+#endif /* __NIOSIO_H__ */
diff --git a/include/nios.h b/include/nios.h
new file mode 100755
index 0000000..46b685a
--- /dev/null
+++ b/include/nios.h
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __NIOS_H__
+#define __NIOS_H__
+
+/*------------------------------------------------------------------------
+ * Control registers -- use with wrctl() & rdctl()
+ *----------------------------------------------------------------------*/
+#define CTL_STATUS	0x00		/* Processor status		*/
+#define CTL_ISTATUS	0x01		/* Saved status (exception)	*/
+#define CTL_WVALID	0x02		/* Valid window limit		*/
+#define CTL_ICACHE	0x05		/* I-cache line-invalidate	*/
+#define CTL_CPU_ID	0x06		/* CPU version id		*/
+#define CTL_DCACHE	0x07		/* D-cache line-invalidate	*/
+#define CTL_CLR_IE	0x08		/* Interrupt clear (disable)	*/
+#define CTL_SET_IE	0x09		/* Interrupt set (enable)	*/
+
+/*------------------------------------------------------------------------
+ * Access to control regs
+ *----------------------------------------------------------------------*/
+#define _str_(s)	#s
+
+#define rdctl(reg)\
+	({unsigned int val;\
+	asm volatile( "pfx " _str_(reg) "\n\t rdctl %0"\
+		: "=r" (val) ); val;})
+
+#define wrctl(reg,val)\
+	asm volatile( "pfx " _str_(reg) "\n\t wrctl %0 \n\t nop"\
+		: : "r" (val))
+
+/*------------------------------------------------------------------------
+ * Control reg bit masks
+ *----------------------------------------------------------------------*/
+#define STATUS_DC	(1<<17)		/* Data cache enable		*/
+#define STATUS_IC	(1<<16)		/* Instruction cache enable	*/
+#define STATUS_IE	(1<<15)		/* Interrupt enable		*/
+#define STATUS_IPRI	(0x3f<<9)	/* Interrupt priority		*/
+#define STATUS_CWP	(0x1f<<4)	/* Current window pointer	*/
+#define STATUS_N	(1<<3)		/* Condition code: negative	*/
+#define STATUS_V	(1<<2)		/* Condition code: overflow	*/
+#define STATUS_Z	(1<<1)		/* Condition code: zero		*/
+#define STATUS_C	(1<<0)		/* Condition code: carry/borrow */
+
+static inline unsigned ipri( unsigned prio )
+{
+	unsigned tmp;
+	unsigned status = rdctl(CTL_STATUS);
+	prio = (prio << 9) & STATUS_IPRI;
+	tmp = (status & ~STATUS_IPRI) | prio;
+	wrctl(CTL_STATUS,tmp);
+	return( (status & STATUS_IPRI) >> 9);
+}
+
+
+#endif /* __NIOS_H__ */
diff --git a/include/nios2-epcs.h b/include/nios2-epcs.h
new file mode 100755
index 0000000..2c9522c
--- /dev/null
+++ b/include/nios2-epcs.h
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * Altera Nios-II EPCS Controller Core interfaces
+ ************************************************************************/
+
+#ifndef __NIOS2_EPCS_H__
+#define __NIOS2_EPCS_H__
+
+typedef struct epcs_devinfo_t {
+	const char 	*name;		/* Device name */
+	unsigned char	id;		/* Device silicon id */
+	unsigned char	size;		/* Total size log2(bytes)*/
+	unsigned char	num_sects;	/* Number of sectors */
+	unsigned char	sz_sect;	/* Sector size log2(bytes) */
+	unsigned char	sz_page;	/* Page size log2(bytes) */
+	unsigned char   prot_mask;	/* Protection mask */
+}epcs_devinfo_t;
+
+/* Returns the devinfo struct if EPCS device is found;
+ * NULL otherwise.
+ */
+extern epcs_devinfo_t *epcs_dev_find (void);
+
+/* Returns the number of bytes used by config data.
+ * Negative on error.
+ */
+extern int epcs_cfgsz (void);
+
+/* Erase sectors 'start' to 'end' - return zero on success
+ */
+extern int epcs_erase (unsigned start, unsigned end);
+
+/* Read 'cnt' bytes from device offset 'off' into buf at 'addr'
+ * Zero return on success
+ */
+extern int epcs_read (ulong addr, ulong off, ulong cnt);
+
+/* Write 'cnt' bytes to device offset 'off' from buf at 'addr'.
+ * Zero return on success
+ */
+extern int epcs_write (ulong addr, ulong off, ulong cnt);
+
+/* Verify 'cnt' bytes at device offset 'off' comparing with buf
+ * at 'addr'. On failure, write first invalid offset to *err.
+ * Zero return on success
+ */
+extern int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err);
+
+#endif /* __NIOS2_EPCS_H__ */
diff --git a/include/nios2-io.h b/include/nios2-io.h
new file mode 100755
index 0000000..d5c8652
--- /dev/null
+++ b/include/nios2-io.h
@@ -0,0 +1,169 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*************************************************************************
+ * Altera Nios2 Standard Peripherals
+ ************************************************************************/
+
+#ifndef __NIOS2IO_H__
+#define __NIOS2IO_H__
+
+/*------------------------------------------------------------------------
+ * UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf)
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_uart_t {
+	unsigned	rxdata;		/* Rx data reg */
+	unsigned	txdata;		/* Tx data reg */
+	unsigned	status;		/* Status reg */
+	unsigned	control;	/* Control reg */
+	unsigned	divisor;	/* Baud rate divisor reg */
+	unsigned	endofpacket;	/* End-of-packet reg */
+}nios_uart_t;
+
+/* status register */
+#define NIOS_UART_PE		(1 << 0)	/* parity error */
+#define NIOS_UART_FE		(1 << 1)	/* frame error */
+#define NIOS_UART_BRK		(1 << 2)	/* break detect */
+#define NIOS_UART_ROE		(1 << 3)	/* rx overrun */
+#define NIOS_UART_TOE		(1 << 4)	/* tx overrun */
+#define NIOS_UART_TMT		(1 << 5)	/* tx empty */
+#define NIOS_UART_TRDY		(1 << 6)	/* tx ready */
+#define NIOS_UART_RRDY		(1 << 7)	/* rx ready */
+#define NIOS_UART_E		(1 << 8)	/* exception */
+#define NIOS_UART_DCTS		(1 << 10)	/* cts change */
+#define NIOS_UART_CTS		(1 << 11)	/* cts */
+#define NIOS_UART_EOP		(1 << 12)	/* eop detected */
+
+/* control register */
+#define NIOS_UART_IPE		(1 << 0)	/* parity error int ena*/
+#define NIOS_UART_IFE		(1 << 1)	/* frame error int ena */
+#define NIOS_UART_IBRK		(1 << 2)	/* break detect int ena */
+#define NIOS_UART_IROE		(1 << 3)	/* rx overrun int ena */
+#define NIOS_UART_ITOE		(1 << 4)	/* tx overrun int ena */
+#define NIOS_UART_ITMT		(1 << 5)	/* tx empty int ena */
+#define NIOS_UART_ITRDY		(1 << 6)	/* tx ready int ena */
+#define NIOS_UART_IRRDY		(1 << 7)	/* rx ready int ena */
+#define NIOS_UART_IE		(1 << 8)	/* exception int ena */
+#define NIOS_UART_TBRK		(1 << 9)	/* transmit break */
+#define NIOS_UART_IDCTS		(1 << 10)	/* cts change int ena */
+#define NIOS_UART_RTS		(1 << 11)	/* rts */
+#define NIOS_UART_IEOP		(1 << 12)	/* eop detected int ena */
+
+
+/*------------------------------------------------------------------------
+ * TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf)
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_timer_t {
+	unsigned	status;			/* Timer status reg */
+	unsigned	control;		/* Timer control reg */
+	unsigned	periodl;		/* Timeout period low */
+	unsigned	periodh;		/* Timeout period high */
+	unsigned	snapl;			/* Snapshot low */
+	unsigned	snaph;			/* Snapshot high */
+}nios_timer_t;
+
+/* status register */
+#define NIOS_TIMER_TO		(1 << 0)	/* Timeout */
+#define NIOS_TIMER_RUN		(1 << 1)	/* Timer running */
+
+/* control register */
+#define NIOS_TIMER_ITO		(1 << 0)	/* Timeout int ena */
+#define NIOS_TIMER_CONT		(1 << 1)	/* Continuous mode */
+#define NIOS_TIMER_START	(1 << 2)	/* Start timer */
+#define NIOS_TIMER_STOP		(1 << 3)	/* Stop timer */
+
+
+/*------------------------------------------------------------------------
+ * PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf)
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_pio_t {
+	unsigned int	data;		/* Data value at each PIO in/out */
+	unsigned int	direction;	/* Data direct. for each PIO bit */
+	unsigned int	interruptmask;	/* Per-bit IRQ enable/disable */
+	unsigned int	edgecapture;	/* Per-bit sync. edge detect & hold */
+}nios_pio_t;
+
+/* direction register */
+#define NIOS_PIO_OUT		(1)		/* PIO bit is output */
+#define NIOS_PIO_IN		(0)		/* PIO bit is input */
+
+
+/*------------------------------------------------------------------------
+ * SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf)
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_spi_t {
+	unsigned	rxdata;		/* Rx data reg */
+	unsigned	txdata;		/* Tx data reg */
+	unsigned	status;		/* Status reg */
+	unsigned	control;	/* Control reg */
+	unsigned	reserved;	/* (master only) */
+	unsigned	slaveselect;	/* SPI slave select mask (master only) */
+}nios_spi_t;
+
+/* status register */
+#define NIOS_SPI_ROE		(1 << 3)	/* rx overrun */
+#define NIOS_SPI_TOE		(1 << 4)	/* tx overrun */
+#define NIOS_SPI_TMT		(1 << 5)	/* tx empty */
+#define NIOS_SPI_TRDY		(1 << 6)	/* tx ready */
+#define NIOS_SPI_RRDY		(1 << 7)	/* rx ready */
+#define NIOS_SPI_E		(1 << 8)	/* exception */
+
+/* control register */
+#define NIOS_SPI_IROE		(1 << 3)	/* rx overrun int ena */
+#define NIOS_SPI_ITOE		(1 << 4)	/* tx overrun int ena */
+#define NIOS_SPI_ITRDY		(1 << 6)	/* tx ready int ena */
+#define NIOS_SPI_IRRDY		(1 << 7)	/* rx ready int ena */
+#define NIOS_SPI_IE		(1 << 8)	/* exception int ena */
+#define NIOS_SPI_SSO		(1 << 10)	/* override SS_n output */
+
+/*------------------------------------------------------------------------
+ * JTAG UART
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_jtag_t {
+	unsigned	data;			/* Data register */
+	unsigned	control;		/* Control register */
+}nios_jtag_t;
+
+/* data register */
+#define NIOS_JTAG_RVALID	(1<<15)		/* Read valid */
+#define NIOS_JTAG_DATA(d)	((d)&0x0ff)	/* Read data */
+#define NIOS_JTAG_RAVAIL(d)	((d)>>16)	/* Read space avail */
+
+/* control register */
+#define NIOS_JTAG_RE		(1 << 0)	/* read intr enable */
+#define NIOS_JTAG_WE		(1 << 1)	/* write intr enable */
+#define NIOS_JTAG_RI		(1 << 8)	/* read intr pending */
+#define NIOS_JTAG_WI		(1 << 9)	/* write intr pending*/
+#define NIOS_JTAG_AC		(1 << 10)	/* activity indicator */
+#define NIOS_JTAG_RRDY		(1 << 12)	/* read available */
+#define NIOS_JTAG_WSPACE(d) 	((d)>>16)	/* Write space avail */
+
+/*------------------------------------------------------------------------
+ * SYSTEM ID
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_sysid_t {
+	unsigned 	id;			/* The system build id*/
+	unsigned 	timestamp;		/* Timestamp */
+}nios_sysid_t;
+
+#endif /* __NIOS2IO_H__ */
diff --git a/include/nios2.h b/include/nios2.h
new file mode 100755
index 0000000..54954e3
--- /dev/null
+++ b/include/nios2.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __NIOS2_H__
+#define __NIOS2_H__
+
+/*------------------------------------------------------------------------
+ * Control registers -- use with wrctl() & rdctl()
+ *----------------------------------------------------------------------*/
+#define CTL_STATUS	0		/* Processor status reg		*/
+#define CTL_ESTATUS	1		/* Exception status reg		*/
+#define CTL_BSTATUS	2		/* Break status reg		*/
+#define CTL_IENABLE	3		/* Interrut enable reg		*/
+#define CTL_IPENDING	4		/* Interrut pending reg		*/
+
+/*------------------------------------------------------------------------
+ * Access to control regs
+ *----------------------------------------------------------------------*/
+#define _str_(x) #x
+
+#define rdctl(reg)\
+	({unsigned int val;\
+	asm volatile( "rdctl %0, ctl" _str_(reg)\
+		: "=r" (val) ); val;})
+
+#define wrctl(reg,val)\
+	asm volatile( "wrctl ctl" _str_(reg) ",%0"\
+		: : "r" (val))
+
+/*------------------------------------------------------------------------
+ * Control reg bit masks
+ *----------------------------------------------------------------------*/
+#define STATUS_IE	(1<<0)		/* Interrupt enable		*/
+#define STATUS_U	(1<<1)		/* User-mode			*/
+
+/*------------------------------------------------------------------------
+ * Bit-31 Cache bypass -- only valid for data access. When data cache
+ * is not implemented, bit 31 is ignored for compatibility.
+ *----------------------------------------------------------------------*/
+#define CACHE_BYPASS(a) ((a) | 0x80000000)
+#define CACHE_NO_BYPASS(a) ((a) & ~0x80000000)
+
+#endif /* __NIOS2_H__ */
diff --git a/include/ns16550.h b/include/ns16550.h
new file mode 100755
index 0000000..e17a11e
--- /dev/null
+++ b/include/ns16550.h
@@ -0,0 +1,137 @@
+/*
+ * NS16550 Serial Port
+ * originally from linux source (arch/ppc/boot/ns16550.h)
+ * modified slightly to
+ * have addresses as offsets from CFG_ISA_BASE
+ * added a few more definitions
+ * added prototypes for ns16550.c
+ * reduced no of com ports to 2
+ * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
+ */
+
+#if (CFG_NS16550_REG_SIZE == 1)
+struct NS16550 {
+	unsigned char rbr;		/* 0 */
+	unsigned char ier;		/* 1 */
+	unsigned char fcr;		/* 2 */
+	unsigned char lcr;		/* 3 */
+	unsigned char mcr;		/* 4 */
+	unsigned char lsr;		/* 5 */
+	unsigned char msr;		/* 6 */
+	unsigned char scr;		/* 7 */
+#if defined(CONFIG_OMAP730)
+	unsigned char mdr1;		/* 8 */
+	unsigned char reg9;		/* 9 */
+	unsigned char regA;		/* A */
+	unsigned char regB;		/* B */
+	unsigned char regC;		/* C */
+	unsigned char regD;		/* D */
+	unsigned char regE;		/* E */
+	unsigned char regF;		/* F */
+	unsigned char reg10;		/* 10 */
+	unsigned char ssr;		/* 11*/
+#endif
+} __attribute__ ((packed));
+#elif (CFG_NS16550_REG_SIZE == 2)
+struct NS16550 {
+	unsigned short rbr;		/* 0 */
+	unsigned short ier;		/* 1 */
+	unsigned short fcr;		/* 2 */
+	unsigned short lcr;		/* 3 */
+	unsigned short mcr;		/* 4 */
+	unsigned short lsr;		/* 5 */
+	unsigned short msr;		/* 6 */
+	unsigned short scr;		/* 7 */
+} __attribute__ ((packed));
+#elif (CFG_NS16550_REG_SIZE == 4)
+struct NS16550 {
+	unsigned long rbr;		/* 0 */
+	unsigned long ier;		/* 1 */
+	unsigned long fcr;		/* 2 */
+	unsigned long lcr;		/* 3 */
+	unsigned long mcr;		/* 4 */
+	unsigned long lsr;		/* 5 */
+	unsigned long msr;		/* 6 */
+	unsigned long scr;		/* 7 */
+} __attribute__ ((packed));
+#elif (CFG_NS16550_REG_SIZE == -4)
+struct NS16550 {
+	unsigned char rbr;		/* 0 */
+	int pad1:24;
+	unsigned char ier;		/* 1 */
+	int pad2:24;
+	unsigned char fcr;		/* 2 */
+	int pad3:24;
+	unsigned char lcr;		/* 3 */
+	int pad4:24;
+	unsigned char mcr;		/* 4 */
+	int pad5:24;
+	unsigned char lsr;		/* 5 */
+	int pad6:24;
+	unsigned char msr;		/* 6 */
+	int pad7:24;
+	unsigned char scr;		/* 7 */
+	int pad8:24;
+#if defined(CONFIG_OMAP)
+	unsigned char mdr1;		/* mode select reset TL16C750*/
+#endif
+#ifdef CONFIG_OMAP1510
+	int pad9:24;
+	unsigned long pad[10];
+	unsigned char osc_12m_sel;
+	int pad10:24;
+#endif
+} __attribute__ ((packed));
+#else
+#error "Please define NS16550 registers size."
+#endif
+
+#define thr rbr
+#define iir fcr
+#define dll rbr
+#define dlm ier
+
+typedef volatile struct NS16550 *NS16550_t;
+
+#define FCR_FIFO_EN     0x01		/* Fifo enable */
+#define FCR_RXSR        0x02		/* Receiver soft reset */
+#define FCR_TXSR        0x04		/* Transmitter soft reset */
+
+#define MCR_DTR         0x01
+#define MCR_RTS         0x02
+#define MCR_DMA_EN      0x04
+#define MCR_TX_DFR      0x08
+
+#define LCR_WLS_MSK	0x03		/* character length slect mask */
+#define LCR_WLS_5	0x00		/* 5 bit character length */
+#define LCR_WLS_6	0x01		/* 6 bit character length */
+#define LCR_WLS_7	0x02		/* 7 bit character length */
+#define LCR_WLS_8	0x03		/* 8 bit character length */
+#define LCR_STB		0x04		/* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define LCR_PEN		0x08		/* Parity eneble */
+#define LCR_EPS		0x10		/* Even Parity Select */
+#define LCR_STKP	0x20		/* Stick Parity */
+#define LCR_SBRK	0x40		/* Set Break */
+#define LCR_BKSE	0x80		/* Bank select enable */
+
+#define LSR_DR		0x01		/* Data ready */
+#define LSR_OE		0x02		/* Overrun */
+#define LSR_PE		0x04		/* Parity error */
+#define LSR_FE		0x08		/* Framing error */
+#define LSR_BI		0x10		/* Break */
+#define LSR_THRE	0x20		/* Xmit holding register empty */
+#define LSR_TEMT	0x40		/* Xmitter empty */
+#define LSR_ERR		0x80		/* Error */
+
+#ifdef CONFIG_OMAP1510
+#define OSC_12M_SEL	0x01		/* selects 6.5 * current clk div */
+#endif
+
+/* useful defaults for LCR */
+#define LCR_8N1		0x03
+
+void	NS16550_init   (NS16550_t com_port, int baud_divisor);
+void	NS16550_putc   (NS16550_t com_port, char c);
+char	NS16550_getc   (NS16550_t com_port);
+int	NS16550_tstc   (NS16550_t com_port);
+void	NS16550_reinit (NS16550_t com_port, int baud_divisor);
diff --git a/include/ns7520_eth.h b/include/ns7520_eth.h
new file mode 100755
index 0000000..5019802
--- /dev/null
+++ b/include/ns7520_eth.h
@@ -0,0 +1,335 @@
+/***********************************************************************
+ *
+ *  Copyright 2003 by FS Forth-Systeme GmbH.
+ *  All rights reserved.
+ *
+ *  $Id$
+ *  @Author: Markus Pietrek
+ *  @Descr: Defines the NS7520 ethernet registers.
+ *          Stick with the old ETH prefix names instead going to the
+ *          new EFE names in the manual.
+ *          NS7520_ETH_* refer to NS7520 Hardware
+ *           Reference/January 2003 [1]
+ *          PHY_LXT971_* refer to Intel LXT971 Datasheet
+ *           #249414 Rev. 02 [2]
+ *          Partly derived from netarm_eth_module.h
+ *
+ * Modified by Arthur Shipkowski <art@videon-central.com> from the
+ * Linux version to be properly formatted for U-Boot (i.e. no C++ comments)
+ *
+ ***********************************************************************/
+
+#ifndef FS_NS7520_ETH_H
+#define FS_NS7520_ETH_H
+
+#ifdef CONFIG_DRIVER_NS7520_ETHERNET
+
+#include "lxt971a.h"
+
+/* The port addresses */
+
+#define	NS7520_ETH_MODULE_BASE	 	(0xFF800000)
+
+#define get_eth_reg_addr(c) \
+     ((volatile unsigned int*) ( NS7520_ETH_MODULE_BASE+(unsigned int) (c)))
+#define NS7520_ETH_EGCR		 (0x0000)	/* Ethernet Gen Control */
+#define NS7520_ETH_EGSR		 (0x0004)	/* Ethernet Gen Status */
+#define NS7520_ETH_FIFO		 (0x0008)	/* FIFO Data */
+#define NS7520_ETH_FIFOL	 (0x000C)	/* FIFO Data Last */
+#define NS7520_ETH_ETSR		 (0x0010)	/* Ethernet Transmit Status */
+#define NS7520_ETH_ERSR		 (0x0014)	/* Ethernet Receive Status */
+#define NS7520_ETH_MAC1		 (0x0400)	/* MAC Config 1 */
+#define NS7520_ETH_MAC2		 (0x0404)	/* MAC Config 2 */
+#define NS7520_ETH_IPGT		 (0x0408)	/* Back2Back InterPacket Gap */
+#define NS7520_ETH_IPGR		 (0x040C)	/* non back2back InterPacket Gap */
+#define NS7520_ETH_CLRT		 (0x0410)	/* Collision Window/Retry */
+#define NS7520_ETH_MAXF		 (0x0414)	/* Maximum Frame Register */
+#define NS7520_ETH_SUPP		 (0x0418)	/* PHY Support */
+#define NS7520_ETH_TEST		 (0x041C)	/* Test Register */
+#define NS7520_ETH_MCFG		 (0x0420)	/* MII Management Configuration */
+#define NS7520_ETH_MCMD		 (0x0424)	/* MII Management Command */
+#define NS7520_ETH_MADR		 (0x0428)	/* MII Management Address */
+#define NS7520_ETH_MWTD		 (0x042C)	/* MII Management Write Data */
+#define NS7520_ETH_MRDD		 (0x0430)	/* MII Management Read Data */
+#define NS7520_ETH_MIND		 (0x0434)	/* MII Management Indicators */
+#define NS7520_ETH_SMII		 (0x0438)	/* SMII Status Register */
+#define NS7520_ETH_SA1		 (0x0440)	/* Station Address 1 */
+#define NS7520_ETH_SA2		 (0x0444)	/* Station Address 2 */
+#define NS7520_ETH_SA3		 (0x0448)	/* Station Address 3 */
+#define NS7520_ETH_SAFR		 (0x05C0)	/* Station Address Filter */
+#define NS7520_ETH_HT1		 (0x05D0)	/* Hash Table 1 */
+#define NS7520_ETH_HT2		 (0x05D4)	/* Hash Table 2 */
+#define NS7520_ETH_HT3		 (0x05D8)	/* Hash Table 3 */
+#define NS7520_ETH_HT4		 (0x05DC)	/* Hash Table 4 */
+
+/* EGCR Ethernet General Control Register Bit Fields*/
+
+#define NS7520_ETH_EGCR_ERX	 (0x80000000)	/* Enable Receive FIFO */
+#define NS7520_ETH_EGCR_ERXDMA	 (0x40000000)	/* Enable Receive DMA */
+#define NS7520_ETH_EGCR_ERXLNG	 (0x20000000)	/* Accept Long packets */
+#define NS7520_ETH_EGCR_ERXSHT	 (0x10000000)	/* Accept Short packets */
+#define NS7520_ETH_EGCR_ERXREG	 (0x08000000)	/* Enable Receive Data Interrupt */
+#define NS7520_ETH_EGCR_ERFIFOH	 (0x04000000)	/* Enable Receive Half-Full Int */
+#define NS7520_ETH_EGCR_ERXBR	 (0x02000000)	/* Enable Receive buffer ready */
+#define NS7520_ETH_EGCR_ERXBAD	 (0x01000000)	/* Accept bad receive packets */
+#define NS7520_ETH_EGCR_ETX	 (0x00800000)	/* Enable Transmit FIFO */
+#define NS7520_ETH_EGCR_ETXDMA	 (0x00400000)	/* Enable Transmit DMA */
+#define NS7520_ETH_EGCR_ETXWM_R  (0x00300000)	/* Enable Transmit FIFO mark Reserv */
+#define NS7520_ETH_EGCR_ETXWM_75 (0x00200000)	/* Enable Transmit FIFO mark 75% */
+#define NS7520_ETH_EGCR_ETXWM_50 (0x00100000)	/* Enable Transmit FIFO mark 50% */
+#define NS7520_ETH_EGCR_ETXWM_25 (0x00000000)	/* Enable Transmit FIFO mark 25% */
+#define NS7520_ETH_EGCR_ETXREG	 (0x00080000)	/* Enable Transmit Data Read Int */
+#define NS7520_ETH_EGCR_ETFIFOH	 (0x00040000)	/* Enable Transmit Fifo Half Int */
+#define NS7520_ETH_EGCR_ETXBC	 (0x00020000)	/* Enable Transmit Buffer Compl Int */
+#define NS7520_ETH_EGCR_EFULLD	 (0x00010000)	/* Enable Full Duplex Operation */
+#define NS7520_ETH_EGCR_MODE_MA  (0x0000C000)	/* Mask */
+#define NS7520_ETH_EGCR_MODE_SEE (0x0000C000)	/* 10 Mbps SEEQ ENDEC PHY */
+#define NS7520_ETH_EGCR_MODE_LEV (0x00008000)	/* 10 Mbps Level1 ENDEC PHY */
+#define NS7520_ETH_EGCR_RES1     (0x00002000)	/* Reserved */
+#define NS7520_ETH_EGCR_RXCINV	 (0x00001000)	/* Invert the receive clock input */
+#define NS7520_ETH_EGCR_TXCINV	 (0x00000800)	/* Invert the transmit clock input */
+#define NS7520_ETH_EGCR_PNA	 (0x00000400)	/* pSOS pNA buffer */
+#define NS7520_ETH_EGCR_MAC_RES	 (0x00000200)	/* MAC Software reset */
+#define NS7520_ETH_EGCR_ITXA	 (0x00000100)	/* Insert Transmit Source Address */
+#define NS7520_ETH_EGCR_ENDEC_MA (0x000000FC)	/* ENDEC media control bits */
+#define NS7520_ETH_EGCR_EXINT_MA (0x00000003)	/* Mask */
+#define NS7520_ETH_EGCR_EXINT_RE (0x00000003)	/* Reserved */
+#define NS7520_ETH_EGCR_EXINT_TP (0x00000002)	/* TP-PMD Mode */
+#define NS7520_ETH_EGCR_EXINT_10 (0x00000001)	/* 10-MBit Mode */
+#define NS7520_ETH_EGCR_EXINT_NO (0x00000000)	/* MII normal operation */
+
+/* EGSR Ethernet General Status Register Bit Fields*/
+
+#define NS7520_ETH_EGSR_RES1	 (0xC0000000)	/* Reserved */
+#define NS7520_ETH_EGSR_RXFDB_MA (0x30000000)	/* Receive FIFO mask */
+#define NS7520_ETH_EGSR_RXFDB_3	 (0x30000000)	/* Receive FIFO 3 bytes available */
+#define NS7520_ETH_EGSR_RXFDB_2	 (0x20000000)	/* Receive FIFO 2 bytes available */
+#define NS7520_ETH_EGCR_RXFDB_1	 (0x10000000)	/* Receive FIFO 1 Bytes available */
+#define NS7520_ETH_EGCR_RXFDB_4	 (0x00000000)	/* Receive FIFO 4 Bytes available */
+#define NS7520_ETH_EGSR_RXREGR	 (0x08000000)	/* Receive Register Ready */
+#define NS7520_ETH_EGSR_RXFIFOH	 (0x04000000)	/* Receive FIFO Half Full */
+#define NS7520_ETH_EGSR_RXBR	 (0x02000000)	/* Receive Buffer Ready */
+#define NS7520_ETH_EGSR_RXSKIP	 (0x01000000)	/* Receive Buffer Skip */
+#define NS7520_ETH_EGSR_RES2	 (0x00F00000)	/* Reserved */
+#define NS7520_ETH_EGSR_TXREGE	 (0x00080000)	/* Transmit Register Empty */
+#define NS7520_ETH_EGSR_TXFIFOH	 (0x00040000)	/* Transmit FIFO half empty */
+#define NS7520_ETH_EGSR_TXBC	 (0x00020000)	/* Transmit buffer complete */
+#define NS7520_ETH_EGSR_TXFIFOE	 (0x00010000)	/* Transmit FIFO empty */
+#define NS7520_ETH_EGSR_RXPINS	 (0x0000FC00)	/* ENDEC Phy Status */
+#define NS7520_ETH_EGSR_RES3	 (0x000003FF)	/* Reserved */
+
+/* ETSR Ethernet Transmit Status Register Bit Fields*/
+
+#define NS7520_ETH_ETSR_RES1	 (0xFFFF0000)	/* Reserved */
+#define NS7520_ETH_ETSR_TXOK	 (0x00008000)	/* Packet transmitted OK */
+#define NS7520_ETH_ETSR_TXBR	 (0x00004000)	/* Broadcast packet transmitted */
+#define NS7520_ETH_ETSR_TXMC	 (0x00002000)	/* Multicast packet transmitted */
+#define NS7520_ETH_ETSR_TXAL	 (0x00001000)	/* Transmit abort - late collision */
+#define NS7520_ETH_ETSR_TXAED	 (0x00000800)	/* Transmit abort - deferral */
+#define NS7520_ETH_ETSR_TXAEC	 (0x00000400)	/* Transmit abort - exc collisions */
+#define NS7520_ETH_ETSR_TXAUR	 (0x00000200)	/* Transmit abort - underrun */
+#define NS7520_ETH_ETSR_TXAJ	 (0x00000100)	/* Transmit abort - jumbo */
+#define NS7520_ETH_ETSR_RES2	 (0x00000080)	/* Reserved */
+#define NS7520_ETH_ETSR_TXDEF	 (0x00000040)	/* Transmit Packet Deferred */
+#define NS7520_ETH_ETSR_TXCRC	 (0x00000020)	/* Transmit CRC error */
+#define NS7520_ETH_ETSR_RES3	 (0x00000010)	/* Reserved */
+#define NS7520_ETH_ETSR_TXCOLC   (0x0000000F)	/* Transmit Collision Count */
+
+/* ERSR Ethernet Receive Status Register Bit Fields*/
+
+#define NS7520_ETH_ERSR_RXSIZE	 (0xFFFF0000)	/* Receive Buffer Size */
+#define NS7520_ETH_ERSR_RXCE	 (0x00008000)	/* Receive Carrier Event */
+#define NS7520_ETH_ERSR_RXDV	 (0x00004000)	/* Receive Data Violation Event */
+#define NS7520_ETH_ERSR_RXOK	 (0x00002000)	/* Receive Packet OK */
+#define NS7520_ETH_ERSR_RXBR	 (0x00001000)	/* Receive Broadcast Packet */
+#define NS7520_ETH_ERSR_RXMC	 (0x00000800)	/* Receive Multicast Packet */
+#define NS7520_ETH_ERSR_RXCRC	 (0x00000400)	/* Receive Packet has CRC error */
+#define NS7520_ETH_ERSR_RXDR	 (0x00000200)	/* Receive Packet has dribble error */
+#define NS7520_ETH_ERSR_RXCV	 (0x00000100)	/* Receive Packet code violation */
+#define NS7520_ETH_ERSR_RXLNG	 (0x00000080)	/* Receive Packet too long */
+#define NS7520_ETH_ERSR_RXSHT	 (0x00000040)	/* Receive Packet too short */
+#define NS7520_ETH_ERSR_ROVER	 (0x00000020)	/* Recive overflow */
+#define NS7520_ETH_ERSR_RES	 (0x0000001F)	/* Reserved */
+
+/* MAC1 MAC Configuration Register 1 Bit Fields*/
+
+#define NS7520_ETH_MAC1_RES1 	 (0xFFFF0000)	/* Reserved */
+#define NS7520_ETH_MAC1_SRST	 (0x00008000)	/* Soft Reset */
+#define NS7520_ETH_MAC1_SIMMRST	 (0x00004000)	/* Simulation Reset */
+#define NS7520_ETH_MAC1_RES2	 (0x00003000)	/* Reserved */
+#define NS7520_ETH_MAC1_RPEMCSR	 (0x00000800)	/* Reset PEMCS/RX */
+#define NS7520_ETH_MAC1_RPERFUN	 (0x00000400)	/* Reset PERFUN */
+#define NS7520_ETH_MAC1_RPEMCST	 (0x00000200)	/* Reset PEMCS/TX */
+#define NS7520_ETH_MAC1_RPETFUN	 (0x00000100)	/* Reset PETFUN */
+#define NS7520_ETH_MAC1_RES3	 (0x000000E0)	/* Reserved */
+#define NS7520_ETH_MAC1_LOOPBK	 (0x00000010)	/* Internal Loopback */
+#define NS7520_ETH_MAC1_TXFLOW	 (0x00000008)	/* TX flow control */
+#define NS7520_ETH_MAC1_RXFLOW	 (0x00000004)	/* RX flow control */
+#define NS7520_ETH_MAC1_PALLRX	 (0x00000002)	/* Pass ALL receive frames */
+#define NS7520_ETH_MAC1_RXEN	 (0x00000001)	/* Receive enable */
+
+/* MAC Configuration Register 2 Bit Fields*/
+
+#define NS7520_ETH_MAC2_RES1 	 (0xFFFF8000)	/* Reserved */
+#define NS7520_ETH_MAC2_EDEFER	 (0x00004000)	/* Excess Deferral */
+#define NS7520_ETH_MAC2_BACKP	 (0x00002000)	/* Backpressure/NO back off */
+#define NS7520_ETH_MAC2_NOBO	 (0x00001000)	/* No back off */
+#define NS7520_ETH_MAC2_RES2	 (0x00000C00)	/* Reserved */
+#define NS7520_ETH_MAC2_LONGP	 (0x00000200)	/* Long Preable enforcement */
+#define NS7520_ETH_MAC2_PUREP	 (0x00000100)	/* Pure preamble enforcement */
+#define NS7520_ETH_MAC2_AUTOP	 (0x00000080)	/* Auto detect PAD enable */
+#define NS7520_ETH_MAC2_VLANP	 (0x00000040)	/* VLAN pad enable */
+#define NS7520_ETH_MAC2_PADEN  	 (0x00000020)	/* PAD/CRC enable */
+#define NS7520_ETH_MAC2_CRCEN	 (0x00000010)	/* CRC enable */
+#define NS7520_ETH_MAC2_DELCRC	 (0x00000008)	/* Delayed CRC */
+#define NS7520_ETH_MAC2_HUGE	 (0x00000004)	/* Huge frame enable */
+#define NS7520_ETH_MAC2_FLENC	 (0x00000002)	/* Frame length checking */
+#define NS7520_ETH_MAC2_FULLD	 (0x00000001)	/* Full duplex */
+
+/* IPGT Back-to-Back Inter-Packet-Gap Register Bit Fields*/
+
+#define NS7520_ETH_IPGT_RES	 (0xFFFFFF80)	/* Reserved */
+#define NS7520_ETH_IPGT_IPGT	 (0x0000007F)	/* Back-to-Back Interpacket Gap */
+
+/* IPGR Non Back-to-Back Inter-Packet-Gap Register Bit Fields*/
+
+#define NS7520_ETH_IPGR_RES1	 (0xFFFF8000)	/* Reserved */
+#define NS7520_ETH_IPGR_IPGR1	 (0x00007F00)	/* Non Back-to-back Interpacket Gap */
+#define NS7520_ETH_IPGR_RES2	 (0x00000080)	/* Reserved */
+#define NS7520_ETH_IPGR_IPGR2	 (0x0000007F)	/* Non back-to-back Interpacket Gap */
+
+/* CLRT Collision Windows/Collision Retry Register Bit Fields*/
+
+#define NS7520_ETH_CLRT_RES1	 (0xFFFFC000)	/* Reserved */
+#define NS7520_ETH_CLRT_CWIN	 (0x00003F00)	/* Collision Windows */
+#define NS7520_ETH_CLRT_RES2	 (0x000000F0)	/* Reserved */
+#define	NS7520_ETH_CLRT_RETX	 (0x0000000F)	/* Retransmission maximum */
+
+/* MAXF Maximum Frame Register Bit Fields*/
+
+#define NS7520_ETH_MAXF_RES1	 (0xFFFF0000)	/* Reserved */
+#define NS7520_ETH_MAXF_MAXF	 (0x0000FFFF)	/* Maximum frame length */
+
+/* SUPP PHY Support Register Bit Fields*/
+
+#define NS7520_ETH_SUPP_RES1	 (0xFFFFFF00)	/* Reserved */
+#define NS7520_ETH_SUPP_RPE100X	 (0x00000080)	/* Reset PE100X module */
+#define NS7520_ETH_SUPP_FORCEQ	 (0x00000040)	/* Force Quit */
+#define NS7520_ETH_SUPP_NOCIPH	 (0x00000020)	/* No Cipher */
+#define NS7520_ETH_SUPP_DLINKF	 (0x00000010)	/* Disable link fail */
+#define NS7520_ETH_SUPP_RPE10T	 (0x00000008)	/* Reset PE10T module */
+#define NS7520_ETH_SUPP_RES2	 (0x00000004)	/* Reserved */
+#define NS7520_ETH_SUPP_JABBER	 (0x00000002)	/* Enable Jabber protection */
+#define NS7520_ETH_SUPP_BITMODE	 (0x00000001)	/* Bit Mode */
+
+/* TEST Register Bit Fields*/
+
+#define NS7520_ETH_TEST_RES1	 (0xFFFFFFF8)	/* Reserved */
+#define NS7520_ETH_TEST_TBACK	 (0x00000004)	/* Test backpressure */
+#define NS7520_ETH_TEST_TPAUSE	 (0x00000002)	/* Test Pause */
+#define NS7520_ETH_TEST_SPQ	 (0x00000001)	/* Shortcut pause quanta */
+
+/* MCFG MII Management Configuration Register Bit Fields*/
+
+#define NS7520_ETH_MCFG_RES1	 (0xFFFF0000)	/* Reserved */
+#define NS7520_ETH_MCFG_RMIIM	 (0x00008000)	/* Reset MII management */
+#define NS7520_ETH_MCFG_RES2	 (0x00007FE0)	/* Reserved */
+#define NS7520_ETH_MCFG_CLKS_MA	 (0x0000001C)	/* Clock Select */
+#define NS7520_ETH_MCFG_CLKS_4	 (0x00000004)	/* Sysclk / 4 */
+#define NS7520_ETH_MCFG_CLKS_6	 (0x00000008)	/* Sysclk / 6 */
+#define NS7520_ETH_MCFG_CLKS_8	 (0x0000000C)	/* Sysclk / 8 */
+#define NS7520_ETH_MCFG_CLKS_10	 (0x00000010)	/* Sysclk / 10 */
+#define NS7520_ETH_MCFG_CLKS_14	 (0x00000014)	/* Sysclk / 14 */
+#define NS7520_ETH_MCFG_CLKS_20	 (0x00000018)	/* Sysclk / 20 */
+#define NS7520_ETH_MCFG_CLKS_28	 (0x0000001C)	/* Sysclk / 28 */
+#define NS7520_ETH_MCFG_SPRE	 (0x00000002)	/* Suppress preamble */
+#define NS7520_ETH_MCFG_SCANI	 (0x00000001)	/* Scan increment */
+
+/* MCMD MII Management Command Register Bit Fields*/
+
+#define NS7520_ETH_MCMD_RES1	 (0xFFFFFFFC)	/* Reserved */
+#define NS7520_ETH_MCMD_SCAN	 (0x00000002)	/* Automatically Scan for Read Data */
+#define NS7520_ETH_MCMD_READ	 (0x00000001)	/* Single scan for Read Data */
+
+/* MCMD MII Management Address Register Bit Fields*/
+
+#define NS7520_ETH_MADR_RES1	 (0xFFFFE000)	/* Reserved */
+#define NS7520_ETH_MADR_DADR	 (0x00001F00)	/* MII PHY device address */
+#define NS7520_ETH_MADR_RES2	 (0x000000E0)	/* Reserved */
+#define NS7520_ETH_MADR_RADR	 (0x0000001F)	/* MII PHY register address */
+
+/* MWTD MII Management Write Data Register Bit Fields*/
+
+#define NS7520_ETH_MWTD_RES1	 (0xFFFF0000)	/* Reserved */
+#define NS7520_ETH_MWTD_MWTD	 (0x0000FFFF)	/* MII Write Data */
+
+/* MRRD MII Management Read Data Register Bit Fields*/
+
+#define NS7520_ETH_MRRD_RES1	 (0xFFFF0000)	/* Reserved */
+#define NS7520_ETH_MRRD_MRDD	 (0x0000FFFF)	/* MII Read Data */
+
+/* MIND MII Management Indicators Register Bit Fields*/
+
+#define NS7520_ETH_MIND_RES1	 (0xFFFFFFF8)	/* Reserved */
+#define NS7520_ETH_MIND_NVALID	 (0x00000004)	/* Read Data not valid */
+#define NS7520_ETH_MIND_SCAN	 (0x00000002)	/* Automatically scan for read data */
+#define NS7520_ETH_MIND_BUSY	 (0x00000001)	/* MII interface busy */
+
+/* SMII Status Register Bit Fields*/
+
+#define NS7520_ETH_SMII_RES1	 (0xFFFFFFE0)	/* Reserved */
+#define NS7520_ETH_SMII_CLASH	 (0x00000010)	/* MAC-to-MAC with PHY */
+#define NS7520_ETH_SMII_JABBER	 (0x00000008)	/* Jabber condition present */
+#define NS7520_ETH_SMII_LINK	 (0x00000004)	/* Link OK */
+#define NS7520_ETH_SMII_DUPLEX	 (0x00000002)	/* Full-duplex operation */
+#define NS7520_ETH_SMII_SPEED	 (0x00000001)	/* 100 Mbps */
+
+/* SA1 Station Address 1 Register Bit Fields*/
+
+#define NS7520_ETH_SA1_RES1	 (0xFFFF0000)	/* Reserved */
+#define NS7520_ETH_SA1_OCTET1	 (0x0000FF00)	/* Station Address octet 1 */
+#define NS7520_ETH_SA1_OCTET2	 (0x000000FF)	/* Station Address octet 2 */
+
+/* SA2 Station Address 2 Register Bit Fields*/
+
+#define NS7520_ETH_SA2_RES1	 (0xFFFF0000)	/* Reserved */
+#define NS7520_ETH_SA2_OCTET3	 (0x0000FF00)	/* Station Address octet 3 */
+#define NS7520_ETH_SA2_OCTET4	 (0x000000FF)	/* Station Address octet 4 */
+
+/* SA3 Station Address 3 Register Bit Fields*/
+
+#define NS7520_ETH_SA3_RES1	 (0xFFFF0000)	/* Reserved */
+#define NS7520_ETH_SA3_OCTET5	 (0x0000FF00)	/* Station Address octet 5 */
+#define NS7520_ETH_SA3_OCTET6	 (0x000000FF)	/* Station Address octet 6 */
+
+/* SAFR Station Address Filter Register Bit Fields*/
+
+#define NS7520_ETH_SAFR_RES1	 (0xFFFFFFF0)	/* Reserved */
+#define NS7520_ETH_SAFR_PRO	 (0x00000008)	/* Enable Promiscuous mode */
+#define NS7520_ETH_SAFR_PRM	 (0x00000004)	/* Accept ALL multicast packets */
+#define NS7520_ETH_SAFR_PRA	 (0x00000002)	/* Accept multicast packets table */
+#define NS7520_ETH_SAFR_BROAD	 (0x00000001)	/* Accept ALL Broadcast packets */
+
+/* HT1 Hash Table 1 Register Bit Fields*/
+
+#define NS7520_ETH_HT1_RES1	 (0xFFFF0000)	/* Reserved */
+#define NS7520_ETH_HT1_HT1	 (0x0000FFFF)	/* CRC value 15-0 */
+
+/* HT2 Hash Table 2 Register Bit Fields*/
+
+#define NS7520_ETH_HT2_RES1	 (0xFFFF0000)	/* Reserved */
+#define NS7520_ETH_HT2_HT2	 (0x0000FFFF)	/* CRC value 31-16 */
+
+/* HT3 Hash Table 3 Register Bit Fields*/
+
+#define NS7520_ETH_HT3_RES1	 (0xFFFF0000)	/* Reserved */
+#define NS7520_ETH_HT3_HT3	 (0x0000FFFF)	/* CRC value 47-32 */
+
+/* HT4 Hash Table 4 Register Bit Fields*/
+
+#define NS7520_ETH_HT4_RES1	 (0xFFFF0000)	/* Reserved */
+#define NS7520_ETH_HT4_HT4	 (0x0000FFFF)	/* CRC value 63-48 */
+
+#endif				/* CONFIG_DRIVER_NS7520_ETHERNET */
+
+#endif				/* FS_NS7520_ETH_H */
diff --git a/include/ns87308.h b/include/ns87308.h
new file mode 100755
index 0000000..feeb940
--- /dev/null
+++ b/include/ns87308.h
@@ -0,0 +1,250 @@
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _NS87308_H_
+#define _NS87308_H_
+
+#include <asm/pci_io.h>
+
+/* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty
+   functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */
+
+void initialise_ns87308(void);
+
+/*
+ * The following struct represents the GPIO registers on the NS87308/NS97307
+ */
+struct GPIO
+{
+  unsigned char dta1;  /* 0 data port 1 */
+  unsigned char dir1;  /* 1 direction port 1 */
+  unsigned char out1;  /* 2 output type port 1 */
+  unsigned char puc1;  /* 3 pull-up control port 1 */
+  unsigned char dta2;  /* 4 data port 2 */
+  unsigned char dir2;  /* 5 direction port 2 */
+  unsigned char out2;  /* 6 output type port 2 */
+  unsigned char puc2;  /* 7 pull-up control port 2  */
+};
+
+/*
+ * The following represents the power management registers on the NS87308/NS97307
+ */
+#define PWM_FER1 0  /* 0 function enable reg. 1 */
+#define PWM_FER2 1  /* 1 function enable reg. 2 */
+#define PWM_PMC1 2  /* 2 power mgmt. control 1 */
+#define PWM_PMC2 3  /* 3 power mgmt. control 2 */
+#define PWM_PMC3 4  /* 4 power mgmt. control 3 */
+#define PWM_WDTO 5  /* 5 watchdog time-out */
+#define PWM_WDCF 6  /* 6 watchdog config. */
+#define PWM_WDST 7  /* 7 watchdog status  */
+
+/*PNP config registers:
+ * these depend on the stated of BADDR1 and BADDR0 on startup
+ * so there's three versions here with the last two digits indicating
+ * for which configuration their valid
+ * the 1st of the two digits indicates the state of BADDR1
+ * the 2st of the two digits indicates the state of BADDR0
+ */
+
+
+#define IO_INDEX_OFFSET_0x 0x0279  /* full PnP isa Mode */
+#define IO_INDEX_OFFSET_10 0x015C  /* PnP motherboard mode */
+#define IO_INDEX_OFFSET_11 0x002E  /* PnP motherboard mode */
+#define IO_DATA_OFFSET_0x  0x0A79  /* full PnP isa Mode */
+#define IO_DATA_OFFSET_10  0x015D  /* PnP motherboard mode */
+#define IO_DATA_OFFSET_11  0x002F  /* PnP motherboard mode */
+
+#if defined(CFG_NS87308_BADDR_0x)
+#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_0x)
+#define IO_DATA  (CFG_ISA_IO + IO_DATA_OFFSET_0x)
+#elif defined(CFG_NS87308_BADDR_10)
+#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_10)
+#define IO_DATA  (CFG_ISA_IO + IO_DATA_OFFSET_10)
+#elif defined(CFG_NS87308_BADDR_11)
+#define IO_INDEX (CFG_ISA_IO + IO_INDEX_OFFSET_11)
+#define IO_DATA  (CFG_ISA_IO + IO_DATA_OFFSET_11)
+#endif
+
+/* PnP register definitions */
+
+#define SET_RD_DATA_PORT    0x00
+#define SERIAL_ISOLATION    0x01
+#define CONFIG_CONTROL      0x02
+#define WAKE_CSN            0x03
+#define RES_DATA            0x04
+#define STATUS              0x05
+#define SET_CSN             0x06
+#define LOGICAL_DEVICE      0x07
+
+/*vendor defined values */
+#define SID_REG             0x20
+#define SUPOERIO_CONF1      0x21
+#define SUPOERIO_CONF2      0x22
+#define PGCS_INDEX          0x23
+#define PGCS_DATA           0x24
+
+/* values above 30 are different for each logical device
+   but I can't be arsed to enter them all. the ones here
+   are pretty consistent between all logical devices
+   feel free to correct the situation if you want.. ;)
+   */
+#define ACTIVATE            0x30
+#define ACTIVATE_OFF        0x00
+#define ACTIVATE_ON         0x01
+
+#define BASE_ADDR_HIGH      0x60
+#define BASE_ADDR_LOW       0x61
+#define LUN_CONFIG_REG		0xF0
+#define DBASE_HIGH			0x60	/* SIO KBC data base address, 15:8 */
+#define DBASE_LOW			0x61	/* SIO KBC data base address,  7:0 */
+#define CBASE_HIGH			0x62	/* SIO KBC command base addr, 15:8 */
+#define CBASE_LOW			0x63	/* SIO KBC command base addr,  7:0 */
+
+/* the logical devices*/
+#define LDEV_KBC1           0x00	/* 2 devices for keyboard and mouse controller*/
+#define LDEV_KBC2           0x01
+#define LDEV_MOUSE          0x01
+#define LDEV_RTC_APC        0x02	/*Real Time Clock and Advanced Power Control*/
+#define LDEV_FDC            0x03	/*floppy disk controller*/
+#define LDEV_PARP           0x04	/*Parallel port*/
+#define LDEV_UART2          0x05
+#define LDEV_UART1          0x06
+#define LDEV_GPIO           0x07    /*General Purpose IO and chip select output signals*/
+#define LDEV_POWRMAN        0x08    /*Power Managment*/
+
+#define CFG_NS87308_KBC1	(1 << LDEV_KBC1)
+#define CFG_NS87308_KBC2	(1 << LDEV_KBC2)
+#define CFG_NS87308_MOUSE	(1 << LDEV_MOUSE)
+#define CFG_NS87308_RTC_APC	(1 << LDEV_RTC_APC)
+#define CFG_NS87308_FDC		(1 << LDEV_FDC)
+#define CFG_NS87308_PARP	(1 << LDEV_PARP)
+#define CFG_NS87308_UART2	(1 << LDEV_UART2)
+#define CFG_NS87308_UART1	(1 << LDEV_UART1)
+#define CFG_NS87308_GPIO	(1 << LDEV_GPIO)
+#define CFG_NS87308_POWRMAN	(1 << LDEV_POWRMAN)
+
+/*some functions and macro's for doing configuration */
+
+static inline void read_pnp_config(unsigned char index, unsigned char *data)
+{
+    pci_writeb(index,IO_INDEX);
+    pci_readb(IO_DATA, *data);
+}
+
+static inline void write_pnp_config(unsigned char index, unsigned char data)
+{
+    pci_writeb(index,IO_INDEX);
+    pci_writeb(data, IO_DATA);
+}
+
+static inline void pnp_set_device(unsigned char dev)
+{
+    write_pnp_config(LOGICAL_DEVICE, dev);
+}
+
+static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
+{
+    pci_writeb(index, CFG_ISA_IO + base);
+    eieio();
+    pci_writeb(data, CFG_ISA_IO + base + 1);
+}
+
+/*void write_pnp_config(unsigned char index, unsigned char data);
+void pnp_set_device(unsigned char dev);
+*/
+
+#define PNP_SET_DEVICE_BASE(dev,base) \
+   pnp_set_device(dev); \
+   write_pnp_config(ACTIVATE, ACTIVATE_OFF); \
+   write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \
+   write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \
+   write_pnp_config(ACTIVATE, ACTIVATE_ON);
+
+#define PNP_ACTIVATE_DEVICE(dev) \
+   pnp_set_device(dev); \
+   write_pnp_config(ACTIVATE, ACTIVATE_ON);
+
+#define PNP_DEACTIVATE_DEVICE(dev) \
+   pnp_set_device(dev); \
+   write_pnp_config(ACTIVATE, ACTIVATE_OFF);
+
+
+static inline void write_pgcs_config(unsigned char index, unsigned char data)
+{
+    write_pnp_config(PGCS_INDEX, index);
+    write_pnp_config(PGCS_DATA, data);
+}
+
+/* these macrose configure the 3 CS lines
+   on the sandpoint board these controll NVRAM
+   CS0 is connected to NVRAMCS
+   CS1 is connected to NVRAMAS0
+   CS2 is connected to NVRAMAS1
+   */
+#define PGCS_CS_ASSERT_ON_WRITE 0x10
+#define PGCS_CS_ASSERT_ON_READ  0x20
+
+#define PNP_PGCS_CSLINE_BASE(cs, base) \
+  write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \
+  write_pgcs_config(((cs) << 2) + 1, (base) & 0xff );
+
+#define PNP_PGCS_CSLINE_CONF(cs, conf) \
+  write_pgcs_config(((cs) << 2) + 2, (conf) );
+
+
+/* The following sections are for 87308 extensions to the standard compoents it emulates */
+
+/* extensions to 16550*/
+
+#define MCR_MDSL_MSK    0xe0 /*mode select mask*/
+#define MCR_MDSL_UART   0x00 /*uart, default*/
+#define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/
+#define MCR_MDSL_SIR    0x03 /*SIR*/
+#define MCR_MDSL_CIR    0x06 /*Consumer IR*/
+
+#define FCR_TXFTH0      0x10    /* these bits control threshod of data level in fifo */
+#define FCR_TXFTH1      0x20    /* for interrupt trigger */
+
+/*
+ * Default NS87308 configuration
+ */
+#ifndef CFG_NS87308_KBC1_BASE
+#define CFG_NS87308_KBC1_BASE	0x0060
+#endif
+#ifndef CFG_NS87308_RTC_BASE
+#define CFG_NS87308_RTC_BASE	0x0070
+#endif
+#ifndef CFG_NS87308_FDC_BASE
+#define CFG_NS87308_FDC_BASE	0x03F0
+#endif
+#ifndef CFG_NS87308_LPT_BASE
+#define CFG_NS87308_LPT_BASE	0x0278
+#endif
+#ifndef CFG_NS87308_UART1_BASE
+#define CFG_NS87308_UART1_BASE	0x03F8
+#endif
+#ifndef CFG_NS87308_UART2_BASE
+#define CFG_NS87308_UART2_BASE	0x02F8
+#endif
+
+#endif /*_NS87308_H_*/
diff --git a/include/ns9750_bbus.h b/include/ns9750_bbus.h
new file mode 100755
index 0000000..0918931
--- /dev/null
+++ b/include/ns9750_bbus.h
@@ -0,0 +1,125 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: ns9750_bbus.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @Descr: Definitions for BBus usage
+ * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 10
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ ***********************************************************************/
+
+#ifndef FS_NS9750_BBUS_H
+#define FS_NS9750_BBUS_H
+
+#define NS9750_BBUS_MODULE_BASE		(0x90600000)
+
+#define get_bbus_reg_addr(c) \
+	((volatile unsigned int *)(NS9750_BBUS_MODULE_BASE+(unsigned int) (c)))
+
+/* We have support for 50 GPIO pins */
+
+#define get_gpio_cfg_reg_addr(pin) \
+	get_bbus_reg_addr( NS9750_BBUS_GPIO_CFG_BASE + (((pin) >> 3) * 4) )
+
+/* To Read/Modify/Write a pin configuration register, use it like
+   set_gpio_cfg_reg_val( 12, NS9750_GPIO_CFG_FUNC_GPIO|NS9750_GPIO_CFG_OUTPUT );
+   They should be wrapped by cli()/sti() */
+#define set_gpio_cfg_reg_val(pin,cfg) \
+	*get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \
+				 	~NS9750_GPIO_CFG_MASK((pin))) |\
+				NS9750_GPIO_CFG_VAL((pin),(cfg));
+
+#define NS9750_GPIO_CFG_MASK(pin)	(NS9750_GPIO_CFG_VAL(pin, \
+					 NS9750_GPIO_CFG_MA))
+#define NS9750_GPIO_CFG_VAL(pin,cfg)	((cfg) << (((pin) % 8) * 4))
+
+#define NS9750_GPIO_CFG_MA		(0x0F)
+#define NS9750_GPIO_CFG_INPUT		(0x00)
+#define NS9750_GPIO_CFG_OUTPUT		(0x08)
+#define NS9750_GPIO_CFG_FUNC_GPIO	(0x03)
+#define NS9750_GPIO_CFG_FUNC_2		(0x02)
+#define NS9750_GPIO_CFG_FUNC_1		(0x01)
+#define NS9750_GPIO_CFG_FUNC_0		(0x00)
+
+/* the register addresses */
+
+#define NS9750_BBUS_MASTER_RESET	(0x00)
+#define NS9750_BBUS_GPIO_CFG_BASE	(0x10)
+#define NS9750_BBUS_GPIO_CTRL_BASE	(0x30)
+#define NS9750_BBUS_GPIO_STAT_BASE	(0x40)
+#define NS9750_BBUS_MONITOR		(0x50)
+#define NS9750_BBUS_DMA_INT_STAT	(0x60)
+#define NS9750_BBUS_DMA_INT_ENABLE	(0x64)
+#define NS9750_BBUS_USB_CFG		(0x70)
+#define NS9750_BBUS_ENDIAN_CFG		(0x80)
+#define NS9750_BBUS_ARM_WAKE_UP		(0x90)
+
+/* register bit fields */
+
+#define NS9750_BBUS_MASTER_RESET_UTIL	(0x00000100)
+#define NS9750_BBUS_MASTER_RESET_I2C	(0x00000080)
+#define NS9750_BBUS_MASTER_RESET_1284	(0x00000040)
+#define NS9750_BBUS_MASTER_RESET_SER4	(0x00000020)
+#define NS9750_BBUS_MASTER_RESET_SER3	(0x00000010)
+#define NS9750_BBUS_MASTER_RESET_SER2	(0x00000008)
+#define NS9750_BBUS_MASTER_RESET_SER1	(0x00000004)
+#define NS9750_BBUS_MASTER_RESET_USB	(0x00000002)
+#define NS9750_BBUS_MASTER_RESET_DMA	(0x00000001)
+
+/* BS9750_BBUS_DMA_INT_BINT* are valid for *DMA_INT_STAT and *DMA_INT_ENABLE */
+
+#define NS9750_BBUS_DMA_INT_BINT16	(0x00010000)
+#define NS9750_BBUS_DMA_INT_BINT15	(0x00008000)
+#define NS9750_BBUS_DMA_INT_BINT14	(0x00004000)
+#define NS9750_BBUS_DMA_INT_BINT13	(0x00002000)
+#define NS9750_BBUS_DMA_INT_BINT12	(0x00001000)
+#define NS9750_BBUS_DMA_INT_BINT11	(0x00000800)
+#define NS9750_BBUS_DMA_INT_BINT10	(0x00000400)
+#define NS9750_BBUS_DMA_INT_BINT9 	(0x00000200)
+#define NS9750_BBUS_DMA_INT_BINT8 	(0x00000100)
+#define NS9750_BBUS_DMA_INT_BINT7 	(0x00000080)
+#define NS9750_BBUS_DMA_INT_BINT6 	(0x00000040)
+#define NS9750_BBUS_DMA_INT_BINT5 	(0x00000020)
+#define NS9750_BBUS_DMA_INT_BINT4 	(0x00000010)
+#define NS9750_BBUS_DMA_INT_BINT3 	(0x00000008)
+#define NS9750_BBUS_DMA_INT_BINT2 	(0x00000004)
+#define NS9750_BBUS_DMA_INT_BINT1 	(0x00000002)
+#define NS9750_BBUS_DMA_INT_BINT0 	(0x00000001)
+
+#define NS9750_BBUS_USB_CFG_OUTEN	(0x00000008)
+#define NS9750_BBUS_USB_CFG_SPEED	(0x00000004)
+#define NS9750_BBUS_USB_CFG_CFG_MA	(0x00000003)
+#define NS9750_BBUS_USB_CFG_CFG_HOST_SOFT (0x00000003)
+#define NS9750_BBUS_USB_CFG_CFG_DEVICE	(0x00000002)
+#define NS9750_BBUS_USB_CFG_CFG_HOST	(0x00000001)
+#define NS9750_BBUS_USB_CFG_CFG_DIS	(0x00000000)
+
+#define NS9750_BBUS_ENDIAN_CFG_AHBM	(0x00001000)
+#define NS9750_BBUS_ENDIAN_CFG_I2C	(0x00000080)
+#define NS9750_BBUS_ENDIAN_CFG_IEEE1284	(0x00000040)
+#define NS9750_BBUS_ENDIAN_CFG_SER4	(0x00000020)
+#define NS9750_BBUS_ENDIAN_CFG_SER3	(0x00000010)
+#define NS9750_BBUS_ENDIAN_CFG_SER2	(0x00000008)
+#define NS9750_BBUS_ENDIAN_CFG_SER1	(0x00000004)
+#define NS9750_BBUS_ENDIAN_CFG_USB	(0x00000002)
+#define NS9750_BBUS_ENDIAN_CFG_DMA	(0x00000001)
+
+#endif /* FS_NS9750_BBUS_H */
diff --git a/include/ns9750_eth.h b/include/ns9750_eth.h
new file mode 100755
index 0000000..978c0bb
--- /dev/null
+++ b/include/ns9750_eth.h
@@ -0,0 +1,297 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @References: [1] NS9750 Hardware Reference, December 2003
+ *              [2] Intel LXT971 Datasheet #249414 Rev. 02
+ *              [3] NS7520 Linux Ethernet Driver
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ***********************************************************************/
+
+#ifndef FS_NS9750_ETH_H
+#define FS_NS9750_ETH_H
+
+#ifdef CONFIG_DRIVER_NS9750_ETHERNET
+
+#include "lxt971a.h"
+
+#define	NS9750_ETH_MODULE_BASE	 	(0xA0600000)
+
+#define get_eth_reg_addr(c) \
+     ((volatile unsigned int*) ( NS9750_ETH_MODULE_BASE+(unsigned int) (c)))
+
+#define NS9750_ETH_EGCR1	 	(0x0000)
+#define NS9750_ETH_EGCR2	 	(0x0004)
+#define NS9750_ETH_EGSR		 	(0x0008)
+#define NS9750_ETH_FIFORX	 	(0x000C)
+#define NS9750_ETH_FIFOTX	 	(0x0010)
+#define NS9750_ETH_FIFOTXS	 	(0x0014)
+#define NS9750_ETH_ETSR		 	(0x0018)
+#define NS9750_ETH_ERSR		 	(0x001C)
+#define NS9750_ETH_MAC1			(0x0400)
+#define NS9750_ETH_MAC2			(0x0404)
+#define NS9750_ETH_IPGT			(0x0408)
+#define NS9750_ETH_IPGR			(0x040C)
+#define NS9750_ETH_CLRT			(0x0410)
+#define NS9750_ETH_MAXF			(0x0414)
+#define NS9750_ETH_SUPP			(0x0418)
+#define NS9750_ETH_TEST			(0x041C)
+#define NS9750_ETH_MCFG			(0x0420)
+#define NS9750_ETH_MCMD			(0x0424)
+#define NS9750_ETH_MADR			(0x0428)
+#define NS9750_ETH_MWTD			(0x042C)
+#define NS9750_ETH_MRDD			(0x0430)
+#define NS9750_ETH_MIND			(0x0434)
+#define NS9750_ETH_SA1			(0x0440)
+#define NS9750_ETH_SA2			(0x0444)
+#define NS9750_ETH_SA3			(0x0448)
+#define NS9750_ETH_SAFR			(0x0500)
+#define NS9750_ETH_HT1		 	(0x0504)
+#define NS9750_ETH_HT2		 	(0x0508)
+#define NS9750_ETH_STAT_BASE	 	(0x0680)
+#define NS9750_ETH_RXAPTR		(0x0A00)
+#define NS9750_ETH_RXBPTR		(0x0A04)
+#define NS9750_ETH_RXCPTR		(0x0A08)
+#define NS9750_ETH_RXDPTR		(0x0A0C)
+#define NS9750_ETH_EINTR		(0x0A10)
+#define NS9750_ETH_EINTREN		(0x0A14)
+#define NS9750_ETH_TXPTR		(0x0A18)
+#define NS9750_ETH_TXRPTR		(0x0A1C)
+#define NS9750_ETH_TXERBD		(0x0A20)
+#define NS9750_ETH_TXSPTR		(0x0A24)
+#define NS9750_ETH_RXAOFF		(0x0A28)
+#define NS9750_ETH_RXBOFF		(0x0A2C)
+#define NS9750_ETH_RXCOFF		(0x0A30)
+#define NS9750_ETH_RXDOFF		(0x0A34)
+#define NS9750_ETH_TXOFF		(0x0A38)
+#define NS9750_ETH_RXFREE		(0x0A3C)
+#define NS9750_ETH_TXBD			(0x1000)
+
+/* register bit fields */
+
+#define NS9750_ETH_EGCR1_ERX	 	(0x80000000)
+#define NS9750_ETH_EGCR1_ERXDMA	 	(0x40000000)
+#define NS9750_ETH_EGCR1_ERXSHT	 	(0x10000000)
+#define NS9750_ETH_EGCR1_ERXSIZ	 	(0x08000000)
+#define NS9750_ETH_EGCR1_ETXSIZ	 	(0x04000000)
+#define NS9750_ETH_EGCR1_ETXDIAG	(0x02000000)
+#define NS9750_ETH_EGCR1_ERXBAD	 	(0x01000000)
+#define NS9750_ETH_EGCR1_ETX	 	(0x00800000)
+#define NS9750_ETH_EGCR1_ETXDMA	 	(0x00400000)
+#define NS9750_ETH_EGCR1_ETXWM	  	(0x00200000)
+#define NS9750_ETH_EGCR1_ERXADV	 	(0x00100000)
+#define NS9750_ETH_EGCR1_ERXINIT	(0x00080000)
+#define NS9750_ETH_EGCR1_PHY_MODE_MA  	(0x0000C000)
+#define NS9750_ETH_EGCR1_PHY_MODE_MII 	(0x00008000)
+#define NS9750_ETH_EGCR1_PHY_MODE_RMII 	(0x00004000)
+#define NS9750_ETH_EGCR1_RXCINV	 	(0x00001000)
+#define NS9750_ETH_EGCR1_TXCINV	 	(0x00000800)
+#define NS9750_ETH_EGCR1_RXALIGN	(0x00000400)
+#define NS9750_ETH_EGCR1_MAC_HRST 	(0x00000200)
+#define NS9750_ETH_EGCR1_ITXA	 	(0x00000100)
+
+#define NS9750_ETH_EGCR2_TPTV_MA	(0xFFFF0000)
+#define NS9750_ETH_EGCR2_TPCF		(0x00000040)
+#define NS9750_ETH_EGCR2_THPDF		(0x00000020)
+#define NS9750_ETH_EGCR2_TCLER		(0x00000008)
+#define NS9750_ETH_EGCR2_AUTOZ		(0x00000004)
+#define NS9750_ETH_EGCR2_CLRCNT		(0x00000002)
+#define NS9750_ETH_EGCR2_STEN		(0x00000001)
+
+#define NS9750_ETH_EGSR_RXINIT	 	(0x00100000)
+#define NS9750_ETH_EGSR_TXFIFONF 	(0x00080000)
+#define NS9750_ETH_EGSR_TXFIFOH	 	(0x00040000)
+#define NS9750_ETH_EGSR_TXFIFOE	 	(0x00010000)
+
+#define NS9750_ETH_FIFOTXS_ALL		(0x00000055)
+#define NS9750_ETH_FIFOTXS_3		(0x000000d5)
+#define NS9750_ETH_FIFOTXS_2		(0x00000035)
+#define NS9750_ETH_FIFOTXS_1		(0x0000000D)
+#define NS9750_ETH_FIFOTXS_0		(0x00000003)
+
+#define NS9750_ETH_ETSR_TXOK	 	(0x00008000)
+#define NS9750_ETH_ETSR_TXBR	 	(0x00004000)
+#define NS9750_ETH_ETSR_TXMC	 	(0x00002000)
+#define NS9750_ETH_ETSR_TXAL	 	(0x00001000)
+#define NS9750_ETH_ETSR_TXAED	 	(0x00000800)
+#define NS9750_ETH_ETSR_TXAEC	 	(0x00000400)
+#define NS9750_ETH_ETSR_TXAUR	 	(0x00000200)
+#define NS9750_ETH_ETSR_TXAJ	 	(0x00000100)
+#define NS9750_ETH_ETSR_TXDEF	 	(0x00000040)
+#define NS9750_ETH_ETSR_TXCRC	 	(0x00000020)
+#define NS9750_ETH_ETSR_TXCOLC   	(0x0000000F)
+
+#define NS9750_ETH_ERSR_RXSIZE_MA	(0x0FFF0000)
+#define NS9750_ETH_ERSR_RXCE	 	(0x00008000)
+#define NS9750_ETH_ERSR_RXDV	 	(0x00004000)
+#define NS9750_ETH_ERSR_RXOK	 	(0x00002000)
+#define NS9750_ETH_ERSR_RXBR	 	(0x00001000)
+#define NS9750_ETH_ERSR_RXMC	 	(0x00000800)
+#define NS9750_ETH_ERSR_RXCRC	 	(0x00000400)
+#define NS9750_ETH_ERSR_RXDR	 	(0x00000200)
+#define NS9750_ETH_ERSR_RXCV	 	(0x00000100)
+#define NS9750_ETH_ERSR_RXSHT	 	(0x00000040)
+
+#define NS9750_ETH_MAC1_SRST	 	(0x00008000)
+#define NS9750_ETH_MAC1_SIMMRST	 	(0x00004000)
+#define NS9750_ETH_MAC1_RPEMCSR	 	(0x00000800)
+#define NS9750_ETH_MAC1_RPERFUN	 	(0x00000400)
+#define NS9750_ETH_MAC1_RPEMCST	 	(0x00000200)
+#define NS9750_ETH_MAC1_RPETFUN	 	(0x00000100)
+#define NS9750_ETH_MAC1_LOOPBK	 	(0x00000010)
+#define NS9750_ETH_MAC1_TXFLOW	 	(0x00000008)
+#define NS9750_ETH_MAC1_RXFLOW	 	(0x00000004)
+#define NS9750_ETH_MAC1_PALLRX	 	(0x00000002)
+#define NS9750_ETH_MAC1_RXEN	 	(0x00000001)
+
+#define NS9750_ETH_MAC2_EDEFER	 	(0x00004000)
+#define NS9750_ETH_MAC2_BACKP	 	(0x00002000)
+#define NS9750_ETH_MAC2_NOBO	 	(0x00001000)
+#define NS9750_ETH_MAC2_LONGP	 	(0x00000200)
+#define NS9750_ETH_MAC2_PUREP	 	(0x00000100)
+#define NS9750_ETH_MAC2_AUTOP	 	(0x00000080)
+#define NS9750_ETH_MAC2_VLANP	 	(0x00000040)
+#define NS9750_ETH_MAC2_PADEN  	 	(0x00000020)
+#define NS9750_ETH_MAC2_CRCEN	 	(0x00000010)
+#define NS9750_ETH_MAC2_DELCRC	 	(0x00000008)
+#define NS9750_ETH_MAC2_HUGE	 	(0x00000004)
+#define NS9750_ETH_MAC2_FLENC	 	(0x00000002)
+#define NS9750_ETH_MAC2_FULLD	 	(0x00000001)
+
+#define NS9750_ETH_IPGT_MA	 	(0x0000007F)
+
+#define NS9750_ETH_IPGR_IPGR1	 	(0x00007F00)
+#define NS9750_ETH_IPGR_IPGR2	 	(0x0000007F)
+
+#define NS9750_ETH_CLRT_CWIN	 	(0x00003F00)
+#define	NS9750_ETH_CLRT_RETX	 	(0x0000000F)
+
+#define NS9750_ETH_MAXF_MAXF	 	(0x0000FFFF)
+
+#define NS9750_ETH_SUPP_RPERMII	 	(0x00008000)
+#define NS9750_ETH_SUPP_SPEED  	 	(0x00000080)
+
+#define NS9750_ETH_TEST_TBACK	 	(0x00000004)
+#define NS9750_ETH_TEST_TPAUSE	 	(0x00000002)
+#define NS9750_ETH_TEST_SPQ	 	(0x00000001)
+
+#define NS9750_ETH_MCFG_RMIIM	 	(0x00008000)
+#define NS9750_ETH_MCFG_CLKS_MA	 	(0x0000001C)
+#define NS9750_ETH_MCFG_CLKS_4	 	(0x00000004)
+#define NS9750_ETH_MCFG_CLKS_6	 	(0x00000008)
+#define NS9750_ETH_MCFG_CLKS_8	 	(0x0000000C)
+#define NS9750_ETH_MCFG_CLKS_10	 	(0x00000010)
+#define NS9750_ETH_MCFG_CLKS_20	 	(0x00000014)
+#define NS9750_ETH_MCFG_CLKS_30	 	(0x00000018)
+#define NS9750_ETH_MCFG_CLKS_40	 	(0x0000001C)
+#define NS9750_ETH_MCFG_SPRE	 	(0x00000002)
+#define NS9750_ETH_MCFG_SCANI	 	(0x00000001)
+
+#define NS9750_ETH_MCMD_SCAN	 	(0x00000002)
+#define NS9750_ETH_MCMD_READ	 	(0x00000001)
+
+#define NS9750_ETH_MADR_DADR_MA	 	(0x00001F00)
+#define NS9750_ETH_MADR_RADR_MA	 	(0x0000001F)
+
+#define NS9750_ETH_MWTD_MA	 	(0x0000FFFF)
+
+#define NS9750_ETH_MRRD_MA	 	(0x0000FFFF)
+
+#define NS9750_ETH_MIND_MIILF		(0x00000008)
+#define NS9750_ETH_MIND_NVALID		(0x00000004)
+#define NS9750_ETH_MIND_SCAN	 	(0x00000002)
+#define NS9750_ETH_MIND_BUSY	 	(0x00000001)
+
+#define NS9750_ETH_SA1_OCTET1_MA 	(0x0000FF00)
+#define NS9750_ETH_SA1_OCTET2_MA 	(0x000000FF)
+
+#define NS9750_ETH_SA2_OCTET3_MA 	(0x0000FF00)
+#define NS9750_ETH_SA2_OCTET4_MA 	(0x000000FF)
+
+#define NS9750_ETH_SA3_OCTET5_MA 	(0x0000FF00)
+#define NS9750_ETH_SA3_OCTET6_MA 	(0x000000FF)
+
+#define NS9750_ETH_SAFR_PRO	 	(0x00000008)
+#define NS9750_ETH_SAFR_PRM	 	(0x00000004)
+#define NS9750_ETH_SAFR_PRA	 	(0x00000002)
+#define NS9750_ETH_SAFR_BROAD	 	(0x00000001)
+
+#define NS9750_ETH_HT1_MA	 	(0x0000FFFF)
+
+#define NS9750_ETH_HT2_MA	 	(0x0000FFFF)
+
+/* also valid for EINTREN */
+#define NS9750_ETH_EINTR_RXOVL_DATA	(0x02000000)
+#define NS9750_ETH_EINTR_RXOVL_STAT	(0x01000000)
+#define NS9750_ETH_EINTR_RXBUFC		(0x00800000)
+#define NS9750_ETH_EINTR_RXDONEA	(0x00400000)
+#define NS9750_ETH_EINTR_RXDONEB	(0x00200000)
+#define NS9750_ETH_EINTR_RXDONEC	(0x00100000)
+#define NS9750_ETH_EINTR_RXDONED	(0x00080000)
+#define NS9750_ETH_EINTR_RXNOBUF	(0x00040000)
+#define NS9750_ETH_EINTR_RXBUFFUL	(0x00020000)
+#define NS9750_ETH_EINTR_RXBR		(0x00010000)
+#define NS9750_ETH_EINTR_STOVFL		(0x00000040)
+#define NS9750_ETH_EINTR_TXPAUSE	(0x00000020)
+#define NS9750_ETH_EINTR_TXBUFC		(0x00000010)
+#define NS9750_ETH_EINTR_TXBUFNR	(0x00000008)
+#define NS9750_ETH_EINTR_TXDONE		(0x00000004)
+#define NS9750_ETH_EINTR_TXERR 		(0x00000002)
+#define NS9750_ETH_EINTR_TXIDLE		(0x00000001)
+#define NS9750_ETH_EINTR_RX_MA	\
+	(NS9750_ETH_EINTR_RXOVL_DATA | \
+	 NS9750_ETH_EINTR_RXOVL_STAT | \
+	 NS9750_ETH_EINTR_RXBUFC | \
+	 NS9750_ETH_EINTR_RXDONEA | \
+	 NS9750_ETH_EINTR_RXDONEB | \
+	 NS9750_ETH_EINTR_RXDONEC | \
+	 NS9750_ETH_EINTR_RXDONED | \
+	 NS9750_ETH_EINTR_RXNOBUF | \
+	 NS9750_ETH_EINTR_RXBUFFUL | \
+	 NS9750_ETH_EINTR_RXBR )
+#define NS9750_ETH_EINTR_TX_MA	\
+	(NS9750_ETH_EINTR_TXPAUSE | \
+	 NS9750_ETH_EINTR_TXBUFC | \
+	 NS9750_ETH_EINTR_TXBUFNR | \
+	 NS9750_ETH_EINTR_TXDONE | \
+	 NS9750_ETH_EINTR_TXERR | \
+	 NS9750_ETH_EINTR_TXIDLE)
+
+/* for TXPTR, TXRPTR, TXERBD and TXSPTR */
+#define NS9750_ETH_TXPTR_MA		(0x000000FF)
+
+/* for RXAOFF, RXBOFF, RXCOFF and RXDOFF */
+#define NS9750_ETH_RXOFF_MA		(0x000007FF)
+
+#define NS9750_ETH_TXOFF_MA		(0x000003FF)
+
+#define NS9750_ETH_RXFREE_D		(0x00000008)
+#define NS9750_ETH_RXFREE_C		(0x00000004)
+#define NS9750_ETH_RXFREE_B		(0x00000002)
+#define NS9750_ETH_RXFREE_A		(0x00000001)
+
+#ifndef NS9750_ETH_PHY_ADDRESS
+# define NS9750_ETH_PHY_ADDRESS	 	(0x0001) /* suitable for UNC20 */
+#endif /* NETARM_ETH_PHY_ADDRESS */
+
+#endif /* CONFIG_DRIVER_NS9750_ETHERNET */
+
+#endif /* FS_NS9750_ETH_H */
diff --git a/include/ns9750_mem.h b/include/ns9750_mem.h
new file mode 100755
index 0000000..44c8ddc
--- /dev/null
+++ b/include/ns9750_mem.h
@@ -0,0 +1,172 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: ns9750_mem.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @Descr: Definitions for Memory Control Module
+ * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 5
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ***********************************************************************/
+
+#ifndef FS_NS9750_MEM_H
+#define FS_NS9750_SYS_H
+
+#define NS9750_MEM_MODULE_BASE		(0xA0700000)
+
+#define get_mem_reg_addr(c) \
+	((volatile unsigned int *)(NS9750_MEM_MODULE_BASE+(unsigned int) (c)))
+
+/* the register addresses */
+
+#define NS9750_MEM_CTRL     		(0x0000)
+#define NS9750_MEM_STATUS     		(0x0004)
+#define NS9750_MEM_CFG     		(0x0008)
+#define NS9750_MEM_DYN_CTRL 		(0x0020)
+#define NS9750_MEM_DYN_REFRESH 		(0x0024)
+#define NS9750_MEM_DYN_READ_CFG		(0x0028)
+#define NS9750_MEM_DYN_TRP     		(0x0030)
+#define NS9750_MEM_DYN_TRAS    		(0x0034)
+#define NS9750_MEM_DYN_TSREX   		(0x0038)
+#define NS9750_MEM_DYN_TAPR   		(0x003C)
+#define NS9750_MEM_DYN_TDAL    		(0x0040)
+#define NS9750_MEM_DYN_TWR     		(0x0044)
+#define NS9750_MEM_DYN_TRC     		(0x0048)
+#define NS9750_MEM_DYN_TRFC    		(0x004C)
+#define NS9750_MEM_DYN_TXSR    		(0x0050)
+#define NS9750_MEM_DYN_TRRD    		(0x0054)
+#define NS9750_MEM_DYN_TMRD    		(0x0058)
+#define NS9750_MEM_STAT_EXT_WAIT	(0x0080)
+#define NS9750_MEM_DYN_CFG_BASE		(0x0100)
+#define NS9750_MEM_DYN_RAS_CAS_BASE	(0x0104)
+#define NS9750_MEM_STAT_CFG_BASE	(0x0200)
+#define NS9750_MEM_STAT_WAIT_WEN_BASE	(0x0204)
+#define NS9750_MEM_STAT_WAIT_OEN_BASE	(0x0208)
+#define NS9750_MEM_STAT_WAIT_RD_BASE	(0x020C)
+#define NS9750_MEM_STAT_WAIT_PAGE_BASE	(0x0210)
+#define NS9750_MEM_STAT_WAIR_WR_BASE	(0x0214)
+#define NS9750_MEM_STAT_WAIT_TURN_BASE	(0x0218)
+
+/* the vectored register addresses */
+
+#define NS9750_MEM_DYN_CFG(c)		(NS9750_MEM_DYN_CFG_BASE + (c)*0x20)
+#define NS9750_MEM_DYN_RAS_CAS(c)	(NS9750_MEM_DYN_RAS_CAS_BASE + (c)*0x20)
+#define NS9750_MEM_STAT_CFG(c)		(NS9750_MEM_STAT_CFG_BASE + (c)*0x20)
+#define NS9750_MEM_STAT_WAIT_WEN(c)	(NS9750_MEM_STAT_WAIT_WEN_BASE+(c)*0x20)
+#define NS9750_MEM_STAT_WAIT_OEN(c)	(NS9750_MEM_STAT_WAIT_OEN_BASE+(c)*0x20)
+#define NS9750_MEM_STAT_RD(c)		(NS9750_MEM_STAT_WAIT_RD_BASE+(c)*0x20)
+#define NS9750_MEM_STAT_PAGE(c)		(NS9750_MEM_STAT_WAIT_PAGE_BASE+(c)*0x20)
+#define NS9750_MEM_STAT_WR(c)		(NS9750_MEM_STAT_WAIT_WR_BASE+(c)*0x20)
+#define NS9750_MEM_STAT_TURN(c)		(NS9750_MEM_STAT_WAIT_TURN_BASE+(c)*0x20)
+
+/* register bit fields */
+
+#define NS9750_MEM_CTRL_L		(0x00000004)
+#define NS9750_MEM_CTRL_M		(0x00000002)
+#define NS9750_MEM_CTRL_E		(0x00000001)
+
+#define NS9750_MEM_STAT_SA		(0x00000004)
+#define NS9750_MEM_STAT_S		(0x00000002)
+#define NS9750_MEM_STAT_B		(0x00000001)
+
+#define NS9750_MEM_CFG_CLK		(0x00000010)
+#define NS9750_MEM_CFG_N		(0x00000001)
+
+#define NS9750_MEM_DYN_CTRL_NRP		(0x00004000)
+#define NS9750_MEM_DYN_CTRL_DP		(0x00002000)
+#define NS9750_MEM_DYN_CTRL_I_MA	(0x00000180)
+#define NS9750_MEM_DYN_CTRL_I_NORMAL	(0x00000000)
+#define NS9750_MEM_DYN_CTRL_I_MODE	(0x00000080)
+#define NS9750_MEM_DYN_CTRL_I_PALL	(0x00000100)
+#define NS9750_MEM_DYN_CTRL_I_NOP	(0x00000180)
+#define NS9750_MEM_DYN_CTRL_SR		(0x00000002)
+#define NS9750_MEM_DYN_CTRL_CE		(0x00000001)
+
+
+#define NS9750_MEM_DYN_REFRESH_MA	(0x000007FF)
+
+#define NS9750_MEM_DYN_READ_CFG_MA	(0x00000003)
+#define NS9750_MEM_DYN_READ_CFG_DELAY0 	(0x00000001)
+#define NS9750_MEM_DYN_READ_CFG_DELAY1  (0x00000002)
+#define NS9750_MEM_DYN_READ_CFG_DELAY2	(0x00000003)
+
+#define NS9750_MEM_DYN_TRP_MA		(0x0000000F)
+
+#define NS9750_MEM_DYN_TRAS_MA		(0x0000000F)
+
+#define NS9750_MEM_DYN_TSREX_MA		(0x0000000F)
+
+#define NS9750_MEM_DYN_TAPR_MA		(0x0000000F)
+
+#define NS9750_MEM_DYN_TDAL_MA		(0x0000000F)
+
+#define NS9750_MEM_DYN_TWR_MA		(0x0000000F)
+
+#define NS9750_MEM_DYN_TRC_MA		(0x0000001F)
+
+#define NS9750_MEM_DYN_TRFC_MA		(0x0000001F)
+
+#define NS9750_MEM_DYN_TXSR_MA		(0x0000001F)
+
+#define NS9750_MEM_DYN_TRRD_MA		(0x0000000F)
+
+#define NS9750_MEM_DYN_TMRD_MA		(0x0000000F)
+
+#define NS9750_MEM_STAT_EXTW_WAIT_MA	(0x0000003F)
+
+#define NS9750_MEM_DYN_CFG_P		(0x00100000)
+#define NS9750_MEM_DYN_CFG_BDMC		(0x00080000)
+#define NS9750_MEM_DYN_CFG_AM		(0x00004000)
+#define NS9750_MEM_DYN_CFG_AM_MA	(0x00001F80)
+#define NS9750_MEM_DYN_CFG_MD		(0x00000018)
+
+#define NS9750_MEM_DYN_RAS_CAS_CAS_MA	(0x00000300)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_1 	(0x00000100)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_2 	(0x00000200)
+#define NS9750_MEM_DYN_RAS_CAS_CAS_3 	(0x00000300)
+#define NS9750_MEM_DYN_RAS_CAS_RAS_MA	(0x00000003)
+#define NS9750_MEM_DYN_RAS_CAS_RAS_1	(0x00000001)
+#define NS9750_MEM_DYN_RAS_CAS_RAS_2 	(0x00000002)
+#define NS9750_MEM_DYN_RAS_CAS_RAS_3 	(0x00000003)
+
+#define NS9750_MEM_STAT_CFG_PSMC	(0x00100000)
+#define NS9750_MEM_STAT_CFG_BSMC	(0x00080000)
+#define NS9750_MEM_STAT_CFG_EW		(0x00000100)
+#define NS9750_MEM_STAT_CFG_PB		(0x00000080)
+#define NS9750_MEM_STAT_CFG_PC		(0x00000040)
+#define NS9750_MEM_STAT_CFG_PM		(0x00000008)
+#define NS9750_MEM_STAT_CFG_MW_MA	(0x00000003)
+#define NS9750_MEM_STAT_CFG_MW_8	(0x00000000)
+#define NS9750_MEM_STAT_CFG_MW_16      	(0x00000001)
+#define NS9750_MEM_STAT_CFG_MW_32	(0x00000002)
+
+#define NS9750_MEM_STAT_WAIT_WEN_MA	(0x0000000F)
+
+#define NS9750_MEM_STAT_WAIT_OEN_MA	(0x0000000F)
+
+#define NS9750_MEM_STAT_WAIT_RD_MA	(0x0000001F)
+
+#define NS9750_MEM_STAT_WAIT_PAGE_MA	(0x0000001F)
+
+#define NS9750_MEM_STAT_WAIT_WR_MA	(0x0000001F)
+
+#define NS9750_MEM_STAT_WAIT_TURN_MA	(0x0000000F)
+
+
+#endif /* FS_NS9750_MEM_H */
diff --git a/include/ns9750_ser.h b/include/ns9750_ser.h
new file mode 100755
index 0000000..e6ff3e1
--- /dev/null
+++ b/include/ns9750_ser.h
@@ -0,0 +1,202 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: ns9750_ser.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @References: [1] NS9750 Hardware Reference, December 2003
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ***********************************************************************/
+
+#ifndef FS_NS9750_SER_H
+#define FS_NS9750_SER_H
+
+#define NS9750_SER_MODULE_BASE		(0x90200000)
+
+#define get_ser_reg_addr(c) \
+	((volatile unsigned int *)(NS9750_SER_MODULE_BASE+(unsigned int) (c)))
+
+#define get_ser_reg_addr_channel(reg,chan) \
+	get_ser_reg_addr((reg)+(((chan)<2)?0:0x00100000)+(((chan)&1)?0x40:0))
+
+/* the register addresses */
+
+#define NS9750_SER_CTRL_A		(0x00)
+#define NS9750_SER_CTRL_B		(0x04)
+#define NS9750_SER_STAT_A		(0x08)
+#define NS9750_SER_BITRATE		(0x0C)
+#define NS9750_SER_FIFO			(0x10)
+#define NS9750_SER_RX_BUF_TIMER		(0x14)
+#define NS9750_SER_RX_CHAR_TIMER	(0x18)
+#define NS9750_SER_RX_MATCH		(0x1C)
+#define NS9750_SER_RX_MATCH_MASK	(0x20)
+#define NS9750_SER_FLOW_CTRL		(0x34)
+#define NS9750_SER_FLOW_CTRL_FORCE	(0x38)
+
+/* register bit fields */
+
+/* control A register */
+
+#define NS9750_SER_CTRL_A_CE		(0x80000000)
+#define NS9750_SER_CTRL_A_BRK		(0x40000000)
+#define NS9750_SER_CTRL_A_STICKP	(0x20000000)
+#define NS9750_SER_CTRL_A_EPS		(0x10000000)
+#define NS9750_SER_CTRL_A_PE		(0x08000000)
+#define NS9750_SER_CTRL_A_STOP		(0x04000000)
+#define NS9750_SER_CTRL_A_WLS_MA	(0x03000000)
+#define NS9750_SER_CTRL_A_WLS_5		(0x00000000)
+#define NS9750_SER_CTRL_A_WLS_6		(0x01000000)
+#define NS9750_SER_CTRL_A_WLS_7		(0x02000000)
+#define NS9750_SER_CTRL_A_WLS_8		(0x03000000)
+#define NS9750_SER_CTRL_A_CTSTX		(0x00800000)
+#define NS9750_SER_CTRL_A_RTSRX		(0x00400000)
+#define NS9750_SER_CTRL_A_RL		(0x00200000)
+#define NS9750_SER_CTRL_A_LL		(0x00100000)
+#define NS9750_SER_CTRL_A_RES		(0x000CF000)
+#define NS9750_SER_CTRL_A_DTR		(0x00020000)
+#define NS9750_SER_CTRL_A_RTS		(0x00010000)
+#define NS9750_SER_CTRL_A_RIE_MA	(0x00000E00)
+#define NS9750_SER_CTRL_A_ERXDMA	(0x00000100)
+#define NS9750_SER_CTRL_A_RIC_MA	(0x000000E0)
+#define NS9750_SER_CTRL_A_TIC_MA	(0x0000001E)
+#define NS9750_SER_CTRL_A_ETXDMA 	(0x00000001)
+
+/* control B register */
+
+#define NS9750_SER_CTRL_B_RDM1		(0x80000000)
+#define NS9750_SER_CTRL_B_RDM2		(0x40000000)
+#define NS9750_SER_CTRL_B_RDM3		(0x20000000)
+#define NS9750_SER_CTRL_B_RDM4		(0x10000000)
+#define NS9750_SER_CTRL_B_RBGT		(0x08000000)
+#define NS9750_SER_CTRL_B_RCGT		(0x04000000)
+#define NS9750_SER_CTRL_B_MODE_MA	(0x00300000)
+#define NS9750_SER_CTRL_B_MODE_UART	(0x00000000)
+#define NS9750_SER_CTRL_B_MODE_HDLC	(0x00100000)
+#define NS9750_SER_CTRL_B_MODE_SPI_M	(0x00200000)
+#define NS9750_SER_CTRL_B_MODE_SPI_S	(0x00300000)
+#define NS9750_SER_CTRL_B_BITORDR	(0x00080000)
+#define NS9750_SER_CTRL_B_RES		(0x0007703F)
+#define NS9750_SER_CTRL_B_RTSTX		(0x00008000)
+#define NS9750_SER_CTRL_B_ENDEC_MA	(0x00000FC0)
+
+/* status A register */
+
+#define NS9750_SER_STAT_A_MATCH1	(0x80000000)
+#define NS9750_SER_STAT_A_MATCH2	(0x40000000)
+#define NS9750_SER_STAT_A_MATCH3	(0x20000000)
+#define NS9750_SER_STAT_A_MATCH4	(0x10000000)
+#define NS9750_SER_STAT_A_BGAP		(0x08000000)
+#define NS9750_SER_STAT_A_CGAP		(0x04000000)
+#define NS9750_SER_STAT_A_RXFDB_MA	(0x00300000)
+#define NS9750_SER_STAT_A_RXFDB_FULL	(0x00000000)
+#define NS9750_SER_STAT_A_RXFDB_1	(0x00100000)
+#define NS9750_SER_STAT_A_RXFDB_2	(0x00200000)
+#define NS9750_SER_STAT_A_RXFDB_3	(0x00300000)
+#define NS9750_SER_STAT_A_DCD		(0x00080000)
+#define NS9750_SER_STAT_A_RI		(0x00040000)
+#define NS9750_SER_STAT_A_DSR		(0x00020000)
+#define NS9750_SER_STAT_A_CTS		(0x00010000)
+#define NS9750_SER_STAT_A_RBRK		(0x00008000)
+#define NS9750_SER_STAT_A_RFE		(0x00004000)
+#define NS9750_SER_STAT_A_RPE		(0x00002000)
+#define NS9750_SER_STAT_A_ROVER		(0x00001000)
+#define NS9750_SER_STAT_A_RRDY		(0x00000800)
+#define NS9750_SER_STAT_A_RHALF		(0x00000400)
+#define NS9750_SER_STAT_A_RBC		(0x00000200)
+#define NS9750_SER_STAT_A_RFULL		(0x00000100)
+#define NS9750_SER_STAT_A_DCDI		(0x00000080)
+#define NS9750_SER_STAT_A_RII		(0x00000040)
+#define NS9750_SER_STAT_A_DSRI		(0x00000020)
+#define NS9750_SER_STAT_A_CTSI		(0x00000010)
+#define NS9750_SER_STAT_A_TRDY		(0x00000008)
+#define NS9750_SER_STAT_A_THALF		(0x00000004)
+#define NS9750_SER_STAT_A_TBC		(0x00000002)
+#define NS9750_SER_STAT_A_TEMPTY	(0x00000001)
+
+#define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE | \
+		 		        NS9750_SER_STAT_A_ROVER | \
+				        NS9750_SER_STAT_A_RPE )
+#define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR | \
+				        NS9750_SER_STAT_A_RBRK | \
+				        NS9750_SER_STAT_A_RRDY | \
+				    	NS9750_SER_STAT_A_RHALF | \
+				    	NS9750_SER_STAT_A_RBC | \
+				    	NS9750_SER_STAT_A_DCDI | \
+				    	NS9750_SER_STAT_A_RII | \
+				    	NS9750_SER_STAT_A_DSRI | \
+				    	NS9750_SER_STAT_A_CTSI )
+#define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY | \
+				        NS9750_SER_STAT_A_THALF | \
+				        NS9750_SER_STAT_A_TBC | \
+				    	NS9750_SER_STAT_A_TEMPTY )
+/* bit rate register */
+
+#define NS9750_SER_BITRATE_EBIT		 (0x80000000)
+#define NS9750_SER_BITRATE_TMODE	 (0x40000000)
+#define NS9750_SER_BITRATE_RXSRC	 (0x20000000)
+#define NS9750_SER_BITRATE_TXSRC	 (0x10000000)
+#define NS9750_SER_BITRATE_RXEXT	 (0x08000000)
+#define NS9750_SER_BITRATE_TXEXT	 (0x04000000)
+#define NS9750_SER_BITRATE_CLKMUX_MA	 (0x03000000)
+#define NS9750_SER_BITRATE_CLKMUX_XTAL	 (0x00000000)
+#define NS9750_SER_BITRATE_CLKMUX_BCLK	 (0x01000000)
+#define NS9750_SER_BITRATE_CLKMUX_OUT1	 (0x02000000)
+#define NS9750_SER_BITRATE_CLKMUX_OUT2	 (0x03000000)
+#define NS9750_SER_BITRATE_TXCINV	 (0x00800000)
+#define NS9750_SER_BITRATE_RXCINV	 (0x00400000)
+#define NS9750_SER_BITRATE_TCDR_MA	 (0x00180000)
+#define NS9750_SER_BITRATE_TCDR_1 	 (0x00000000)
+#define NS9750_SER_BITRATE_TCDR_8 	 (0x00080000)
+#define NS9750_SER_BITRATE_TCDR_16	 (0x00100000)
+#define NS9750_SER_BITRATE_TCDR_32	 (0x00180000)
+#define NS9750_SER_BITRATE_RCDR_MA	 (0x00070000)
+#define NS9750_SER_BITRATE_RCDR_1 	 (0x00000000)
+#define NS9750_SER_BITRATE_RCDR_8 	 (0x00020000)
+#define NS9750_SER_BITRATE_RCDR_16	 (0x00040000)
+#define NS9750_SER_BITRATE_RCDR_32	 (0x00060000)
+#define NS9750_SER_BITRATE_TICS		 (0x00010000)
+#define NS9750_SER_BITRATE_RICS		 (0x00008000)
+#define NS9750_SER_BITRATE_N_MA		 (0x00007FFF)
+
+/* receive buffer gap timer */
+
+#define NS9750_SER_RX_BUF_TIMER_TRUN	 (0x80000000) /* UART and SPI */
+#define NS9750_SER_RX_BUF_TIMER_BT_MA	 (0x0000FFFF) /* UART and SPI */
+#define NS9750_SER_RX_BUF_TIMER_MAXLEN_MA (0x0000FFFF) /* HDLC only */
+
+/* receive character gap timer */
+
+#define NS9750_SER_RX_CHAR_TIMER_TRUN	 (0x80000000)
+#define NS9750_SER_RX_CHAR_TIMER_CT_MA	 (0x000FFFFF)
+
+/* receive match */
+
+#define NS9750_SER_RX_MATCH_RDMB1_MA	 (0xFF000000)
+#define NS9750_SER_RX_MATCH_RDMB2_MA	 (0x00FF0000)
+#define NS9750_SER_RX_MATCH_RDMB3_MA	 (0x0000FF00)
+#define NS9750_SER_RX_MATCH_RDMB4_MA	 (0x000000FF)
+
+/* receive match mask */
+
+#define NS9750_SER_RX_MATCH_MASK_RDMB1_MA (0xFF000000)
+#define NS9750_SER_RX_MATCH_MASK_RDMB2_MA (0x00FF0000)
+#define NS9750_SER_RX_MATCH_MASK_RDMB3_MA (0x0000FF00)
+#define NS9750_SER_RX_MATCH_MASK_RDMB4_MA (0x000000FF)
+
+#endif /* FS_NS9750_SER_H */
diff --git a/include/ns9750_sys.h b/include/ns9750_sys.h
new file mode 100755
index 0000000..c563cad
--- /dev/null
+++ b/include/ns9750_sys.h
@@ -0,0 +1,215 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: ns9750_sys.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @Descr: Definitions for SYS Control Module
+ * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 4
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ***********************************************************************/
+
+#ifndef FS_NS9750_SYS_H
+#define FS_NS9750_SYS_H
+
+#define NS9750_SYS_MODULE_BASE		(0xA0900000)
+
+#define get_sys_reg_addr(c) \
+	((volatile unsigned int *)(NS9750_SYS_MODULE_BASE+(unsigned int) (c)))
+
+/* the register addresses */
+
+#define NS9750_SYS_AHB_GEN		(0x0000)
+#define NS9750_SYS_BRC_BASE		(0x0004)
+#define NS9750_SYS_AHB_TIMEOUT		(0x0014)
+#define NS9750_SYS_AHB_ERROR1   	(0x0018)
+#define NS9750_SYS_AHB_ERROR2   	(0x001C)
+#define NS9750_SYS_AHB_MON    		(0x0020)
+#define NS9750_SYS_TIMER_COUNT_BASE	(0x0044)
+#define NS9750_SYS_TIMER_READ_BASE	(0x0084)
+#define NS9750_SYS_INT_VEC_ADR_BASE	(0x00C4)
+#define NS9750_SYS_INT_CFG_BASE		(0x0144)
+#define NS9750_SYS_ISRADDR		(0x0164)
+#define NS9750_SYS_INT_STAT_ACTIVE	(0x0168)
+#define NS9750_SYS_INT_STAT_RAW		(0x016C)
+#define NS9750_SYS_TIMER_INT_STAT	(0x0170)
+#define NS9750_SYS_SW_WDOG_CFG		(0x0174)
+#define NS9750_SYS_SW_WDOG_TIMER	(0x0178)
+#define NS9750_SYS_CLOCK		(0x017C)
+#define NS9750_SYS_RESET		(0x0180)
+#define NS9750_SYS_MISC			(0x0184)
+#define NS9750_SYS_PLL			(0x0188)
+#define NS9750_SYS_ACT_INT_STAT		(0x018C)
+#define NS9750_SYS_TIMER_CTRL_BASE	(0x0190)
+#define NS9750_SYS_CS_DYN_BASE_BASE	(0x01D0)
+#define NS9750_SYS_CS_DYN_MASK_BASE	(0x01D4)
+#define NS9750_SYS_CS_STATIC_BASE_BASE	(0x01F0)
+#define NS9750_SYS_CS_STATIC_MASK_BASE	(0x01F4)
+#define NS9750_SYS_GEN_ID		(0x0210)
+#define NS9750_SYS_EXT_INT_CTRL_BASE	(0x0214)
+
+/* the vectored register addresses */
+
+#define NS9750_SYS_TIMER_COUNT(c)	(NS9750_SYS_TIMER_COUNT_BASE + (c))
+#define NS9750_SYS_TIMER_READ(c)	(NS9750_SYS_TIMER_READ_BASE + (c))
+#define NS9750_SYS_INT_VEC_ADR(c)	(NS9750_SYS_INT_VEC_ADR_BASE + (c))
+#define NS9750_SYS_TIMER_CTRL(c)	(NS9750_SYS_TIMER_CTRL_BASE + (c))
+/* CS_DYN start with 4 */
+#define NS9750_SYS_CS_DYN_BASE(c)	(NS9750_SYS_CS_DYN_BASE_BASE + ((c)-4)*2)
+#define NS9750_SYS_CS_DYN_MASK(c)	(NS9750_SYS_CS_DYN_MASK_BASE + ((c)-4)*2)
+/* CS_STATIC start with 0 */
+#define NS9750_SYS_CS_STATIC_BASE(c)	(NS9750_SYS_CS_STATIC_BASE_BASE + (c)*2)
+#define NS9750_SYS_CS_STATIC_MASK(c)	(NS9750_SYS_CS_STATIC_MASK_BASE + (c)*2)
+#define NS9750_SYS_EXT_INT_CTRL(c)	(NS9750_SYS_EXT_INT_CTRL + (c))
+
+/* register bit fields */
+
+#define NS9750_SYS_AHB_GEN_EXMAM	(0x00000001)
+
+/* need to be n*8bit to BRC channel */
+#define NS9750_SYS_BRC_CEB		(0x00000080)
+#define NS9750_SYS_BRC_BRF_MA		(0x00000030)
+#define NS9750_SYS_BRC_BRF_100		(0x00000000)
+#define NS9750_SYS_BRC_BRF_75		(0x00000010)
+#define NS9750_SYS_BRC_BRF_50		(0x00000020)
+#define NS9750_SYS_BRC_BRF_25		(0x00000030)
+
+#define NS9750_SYS_AHB_TIMEOUT_BAT_MA	(0xFFFF0000)
+#define NS9750_SYS_AHB_TIMEOUT_BMT_MA	(0x0000FFFF)
+
+#define NS9750_SYS_AHB_ERROR2_ABL	(0x00040000)
+#define NS9750_SYS_AHB_ERROR2_AER	(0x00020000)
+#define NS9750_SYS_AHB_ERROR2_ABM	(0x00010000)
+#define NS9750_SYS_AHB_ERROR2_ABA	(0x00008000)
+#define NS9750_SYS_AHB_ERROR2_HWRT	(0x00004000)
+#define NS9750_SYS_AHB_ERROR2_HMID_MA	(0x00003C00)
+#define NS9750_SYS_AHB_ERROR2_HTPC_MA	(0x000003C0)
+#define NS9750_SYS_AHB_ERROR2_HSZ_MA	(0x00000038)
+#define NS9750_SYS_AHB_ERROR2_RR_MA	(0x00000007)
+
+#define NS9750_SYS_AHB_MON_EIC		(0x00800000)
+#define NS9750_SYS_AHB_MON_MBII		(0x00400000)
+#define NS9750_SYS_AHB_MON_MBL_MA	(0x003FFFC0)
+#define NS9750_SYS_AHB_MON_MBLDC	(0x00000020)
+#define NS9750_SYS_AHB_MON_SERDC	(0x00000010)
+#define NS9750_SYS_AHB_MON_BMTC_MA	(0x0000000C)
+#define NS9750_SYS_AHB_MON_BMTC_RECORD	(0x00000000)
+#define NS9750_SYS_AHB_MON_BMTC_GEN_IRQ	(0x00000004)
+#define NS9750_SYS_AHB_MON_BMTC_GEN_RES	(0x00000008)
+#define NS9750_SYS_AHB_MON_BATC_MA	(0x00000003)
+#define NS9750_SYS_AHB_MON_BATC_RECORD	(0x00000000)
+#define NS9750_SYS_AHB_MON_BATC_GEN_IRQ	(0x00000001)
+#define NS9750_SYS_AHB_MON_BATC_GEN_RES	(0x00000002)
+
+/* need to be n*8bit to Int Level */
+
+#define NS9750_SYS_INT_CFG_IE		(0x00000080)
+#define NS9750_SYS_INT_CFG_IT    	(0x00000020)
+#define NS9750_SYS_INT_CFG_IAD_MA	(0x0000001F)
+
+#define NS9750_SYS_TIMER_INT_STAT_MA 	(0x0000FFFF)
+
+#define NS9750_SYS_SW_WDOG_CFG_SWWE	(0x00000080)
+#define NS9750_SYS_SW_WDOG_CFG_SWWI	(0x00000020)
+#define NS9750_SYS_SW_WDOG_CFG_SWWIC	(0x00000010)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_MA	(0x00000007)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2 	(0x00000000)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4 	(0x00000001)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8 	(0x00000002)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_16	(0x00000003)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_32	(0x00000004)
+#define NS9750_SYS_SW_WDOG_CFG_SWTCS_64	(0x00000005)
+
+#define NS9750_SYS_CLOCK_LPCS_MA	(0x00000380)
+#define NS9750_SYS_CLOCK_LPCS_1 	(0x00000000)
+#define NS9750_SYS_CLOCK_LPCS_2 	(0x00000080)
+#define NS9750_SYS_CLOCK_LPCS_4 	(0x00000100)
+#define NS9750_SYS_CLOCK_LPCS_8 	(0x00000180)
+#define NS9750_SYS_CLOCK_LPCS_EXT	(0x00000200)
+#define NS9750_SYS_CLOCK_BBC		(0x00000040)
+#define NS9750_SYS_CLOCK_LCC		(0x00000020)
+#define NS9750_SYS_CLOCK_MCC		(0x00000010)
+#define NS9750_SYS_CLOCK_PARBC		(0x00000008)
+#define NS9750_SYS_CLOCK_PC		(0x00000004)
+#define NS9750_SYS_CLOCK_MACC		(0x00000001)
+
+#define NS9750_SYS_RESET_SR		(0x80000000)
+#define NS9750_SYS_RESET_I2CW		(0x00100000)
+#define NS9750_SYS_RESET_CSE		(0x00080000)
+#define NS9750_SYS_RESET_SMWE		(0x00040000)
+#define NS9750_SYS_RESET_EWE		(0x00020000)
+#define NS9750_SYS_RESET_PI3WE		(0x00010000)
+#define NS9750_SYS_RESET_BBT		(0x00000040)
+#define NS9750_SYS_RESET_LCDC		(0x00000020)
+#define NS9750_SYS_RESET_MEMC		(0x00000010)
+#define NS9750_SYS_RESET_PCIAR		(0x00000008)
+#define NS9750_SYS_RESET_PCIM		(0x00000004)
+#define NS9750_SYS_RESET_MACM		(0x00000001)
+
+#define NS9750_SYS_MISC_REV_MA		(0xFF000000)
+#define NS9750_SYS_MISC_PCIA		(0x00002000)
+#define NS9750_SYS_MISC_VDIS		(0x00001000)
+#define NS9750_SYS_MISC_BMM		(0x00000800)
+#define NS9750_SYS_MISC_CS1DB		(0x00000400)
+#define NS9750_SYS_MISC_CS1DW_MA	(0x00000300)
+#define NS9750_SYS_MISC_MCCM		(0x00000080)
+#define NS9750_SYS_MISC_PMSS		(0x00000040)
+#define NS9750_SYS_MISC_CS1P		(0x00000020)
+#define NS9750_SYS_MISC_ENDM		(0x00000008)
+#define NS9750_SYS_MISC_MBAR		(0x00000004)
+#define NS9750_SYS_MISC_IRAM0		(0x00000001)
+
+#define NS9750_SYS_PLL_PLLBS		(0x02000000)
+#define NS9750_SYS_PLL_PLLFS_MA		(0x01800000)
+#define NS9750_SYS_PLL_PLLIS_MA		(0x00600000)
+#define NS9750_SYS_PLL_PLLND_MA		(0x001F0000)
+#define NS9750_SYS_PLL_PLLSW		(0x00008000)
+#define NS9750_SYS_PLL_PLLBSSW		(0x00000200)
+#define NS9750_SYS_PLL_FSEL_MA		(0x00000180)
+#define NS9750_SYS_PLL_CPCC_MA		(0x00000060)
+#define NS9750_SYS_PLL_NDSW_MA		(0x0000001F)
+
+#define NS9750_SYS_ACT_INT_STAT_MA 	(0x0000FFFF)
+
+#define NS9750_SYS_TIMER_CTRL_TEN	(0x00008000)
+#define NS9750_SYS_TIMER_CTRL_INTC	(0x00000200)
+#define NS9750_SYS_TIMER_CTRL_TLCS_MA	(0x000001C0)
+#define NS9750_SYS_TIMER_CTRL_TLCS_1 	(0x00000000)
+#define NS9750_SYS_TIMER_CTRL_TLCS_2 	(0x00000040)
+#define NS9750_SYS_TIMER_CTRL_TLCS_4 	(0x00000080)
+#define NS9750_SYS_TIMER_CTRL_TLCS_8 	(0x000000C0)
+#define NS9750_SYS_TIMER_CTRL_TLCS_16	(0x00000100)
+#define NS9750_SYS_TIMER_CTRL_TLCS_32	(0x00000140)
+#define NS9750_SYS_TIMER_CTRL_TLCS_64	(0x00000180)
+#define NS9750_SYS_TIMER_CTRL_TLCS_EXT	(0x000001C0)
+#define NS9750_SYS_TIMER_CTRL_TM_MA	(0x00000030)
+#define NS9750_SYS_TIMER_CTRL_TM_INT  	(0x00000000)
+#define NS9750_SYS_TIMER_CTRL_TM_LOW 	(0x00000010)
+#define NS9750_SYS_TIMER_CTRL_TM_HIGH	(0x00000020)
+#define NS9750_SYS_TIMER_CTRL_INTS	(0x00000008)
+#define NS9750_SYS_TIMER_CTRL_UDS	(0x00000004)
+#define NS9750_SYS_TIMER_CTRL_TSZ	(0x00000002)
+#define NS9750_SYS_TIMER_CTRL_REN	(0x00000001)
+
+#define NS9750_SYS_EXT_INT_CTRL_STS	(0x00000008)
+#define NS9750_SYS_EXT_INT_CTRL_CLR	(0x00000004)
+#define NS9750_SYS_EXT_INT_CTRL_PLTY	(0x00000002)
+#define NS9750_SYS_EXT_INT_CTRL_LVEDG	(0x00000001)
+
+#endif /* FS_NS9750_SYS_H */
diff --git a/include/part.h b/include/part.h
new file mode 100755
index 0000000..dc71600
--- /dev/null
+++ b/include/part.h
@@ -0,0 +1,149 @@
+/*++ 
+Copyright (c) 2010 WonderMedia Technologies, Inc.
+
+This program is free software: you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free Software 
+Foundation, either version 2 of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU General Public License for more details. You
+should have received a copy of the GNU General Public License along with this
+program. If not, see http://www.gnu.org/licenses/>.
+
+WonderMedia Technologies, Inc.
+10F, 529, Chung-Cheng Road, Hsin-Tien, Taipei 231, R.O.C.
+--*/
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _PART_H
+#define _PART_H
+#include <ide.h>
+
+typedef struct block_dev_desc {
+	int		if_type;	/* type of the interface */
+	int	        dev;	  	/* device number */
+	unsigned char	part_type;  	/* partition type */
+	unsigned char	target;		/* target SCSI ID */
+	unsigned char	lun;		/* target LUN */
+	unsigned char	type;		/* device type */
+	unsigned char	removable;	/* removable device */
+#ifdef CONFIG_LBA48
+	unsigned char	lba48;		/* device can use 48bit addr (ATA/ATAPI v7) */
+#endif
+	lbaint_t		lba;	  	/* number of blocks */
+	unsigned long	blksz;		/* block size */
+	unsigned char	vendor [40+1]; 	/* IDE model, SCSI Vendor */
+	unsigned char	product[20+1];	/* IDE Serial no, SCSI product */
+	unsigned char	revision[8+1];	/* firmware revision */
+	unsigned long	(*block_read)(int dev,
+				      unsigned long start,
+				      lbaint_t blkcnt,
+				      unsigned long *buffer);
+	unsigned long	(*block_write)(int dev,

+				      unsigned long start,

+				      lbaint_t blkcnt,

+				      unsigned long *buffer);
+}block_dev_desc_t;
+
+/* Interface types: */
+#define IF_TYPE_UNKNOWN		0
+#define IF_TYPE_IDE		1
+#define IF_TYPE_SCSI		2
+#define IF_TYPE_ATAPI		3
+#define IF_TYPE_USB		4
+#define IF_TYPE_DOC		5
+#define IF_TYPE_MMC		6
+#define IF_TYPE_MEM		7
+#define IF_TYPE_SATA		8
+
+/* Part types */
+#define PART_TYPE_UNKNOWN	0x00
+#define PART_TYPE_MAC		0x01
+#define PART_TYPE_DOS		0x02
+#define PART_TYPE_ISO		0x03
+#define PART_TYPE_AMIGA		0x04
+
+/*
+ * Type string for U-Boot bootable partitions
+ */
+#define BOOT_PART_TYPE	"U-Boot"	/* primary boot partition type	*/
+#define BOOT_PART_COMP	"PPCBoot"	/* PPCBoot compatibility type	*/
+
+/* device types */
+#define DEV_TYPE_UNKNOWN	0xff	/* not connected */
+#define DEV_TYPE_HARDDISK	0x00	/* harddisk */
+#define DEV_TYPE_TAPE		0x01	/* Tape */
+#define DEV_TYPE_CDROM		0x05	/* CD-ROM */
+#define DEV_TYPE_OPDISK		0x07	/* optical disk */
+
+typedef struct disk_partition {
+	ulong   offset;
+	ulong	start;		/* # of first block in partition	*/
+	ulong	size;		/* number of blocks in partition	*/
+	ulong	blksz;		/* block size in bytes			*/
+	uchar	name[32];	/* partition name			*/
+	uchar	type[32];	/* string type description		*/
+} disk_partition_t;
+
+/* disk/part.c */
+int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+int del_partition(block_dev_desc_t * dev_desc, int part);
+int add_partition(block_dev_desc_t * dev_desc, int part, int ptype, int address, int length);
+void print_part (block_dev_desc_t *dev_desc);
+void  init_part (block_dev_desc_t *dev_desc);
+void dev_print(block_dev_desc_t *dev_desc);
+
+
+#ifdef CONFIG_MAC_PARTITION
+/* disk/part_mac.c */
+int get_partition_info_mac (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+void print_part_mac (block_dev_desc_t *dev_desc);
+int   test_part_mac (block_dev_desc_t *dev_desc);
+#endif
+
+#ifdef CONFIG_DOS_PARTITION
+/* disk/part_dos.c */
+int get_partition_info_dos (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+int del_partition_dos(block_dev_desc_t * dev_desc, int part);
+int add_partition_dos(block_dev_desc_t * dev_desc, int part, int ptype, int address, int length);
+void print_part_dos (block_dev_desc_t *dev_desc);
+int   test_part_dos (block_dev_desc_t *dev_desc);
+int getUserOrderParam(block_dev_desc_t * dev_desc, int *partlist, int *address, int *length, int partnum);
+#endif
+
+#ifdef CONFIG_ISO_PARTITION
+/* disk/part_iso.c */
+int get_partition_info_iso (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+void print_part_iso (block_dev_desc_t *dev_desc);
+int   test_part_iso (block_dev_desc_t *dev_desc);
+#endif
+
+#ifdef CONFIG_AMIGA_PARTITION
+/* disk/part_amiga.c */
+int get_partition_info_amiga (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+void print_part_amiga (block_dev_desc_t *dev_desc);
+int   test_part_amiga (block_dev_desc_t *dev_desc);
+#endif
+
+#endif /* _PART_H */
diff --git a/include/pc_keyb.h b/include/pc_keyb.h
new file mode 100755
index 0000000..ab51703
--- /dev/null
+++ b/include/pc_keyb.h
@@ -0,0 +1,121 @@
+/*
+ *	include/linux/pc_keyb.h
+ *
+ *	PC Keyboard And Keyboard Controller
+ *
+ *	(c) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
+ */
+
+/*
+ *	Configuration Switches
+ */
+#undef KBD_REPORT_ERR			/* Report keyboard errors */
+#define KBD_REPORT_UNKN			/* Report unknown scan codes */
+#define KBD_REPORT_TIMEOUTS		/* Report keyboard timeouts */
+#undef KBD_IS_FOCUS_9000		/* We have the brain-damaged FOCUS-9000 keyboard */
+#undef INITIALIZE_MOUSE			/* Define if your PS/2 mouse needs initialization. */
+
+#define KBD_INIT_TIMEOUT 1000		/* Timeout in ms for initializing the keyboard */
+#define KBC_TIMEOUT 250			/* Timeout in ms for sending to keyboard controller */
+#define KBD_TIMEOUT 1000		/* Timeout in ms for keyboard command acknowledge */
+
+/*
+ *	Internal variables of the driver
+ */
+extern unsigned char pckbd_read_mask;
+extern unsigned char aux_device_present;
+
+/*
+ *	Keyboard Controller Registers on normal PCs.
+ */
+#define KBD_STATUS_REG		0x64	/* Status register (R) */
+#define KBD_CNTL_REG		0x64	/* Controller command register (W) */
+#define KBD_DATA_REG		0x60	/* Keyboard data register (R/W) */
+
+/*
+ *	Keyboard Controller Commands
+ */
+#define KBD_CCMD_READ_MODE	0x20	/* Read mode bits */
+#define KBD_CCMD_WRITE_MODE	0x60	/* Write mode bits */
+#define KBD_CCMD_GET_VERSION	0xA1	/* Get controller version */
+#define KBD_CCMD_MOUSE_DISABLE	0xA7	/* Disable mouse interface */
+#define KBD_CCMD_MOUSE_ENABLE	0xA8	/* Enable mouse interface */
+#define KBD_CCMD_TEST_MOUSE	0xA9	/* Mouse interface test */
+#define KBD_CCMD_SELF_TEST	0xAA	/* Controller self test */
+#define KBD_CCMD_KBD_TEST	0xAB	/* Keyboard interface test */
+#define KBD_CCMD_KBD_DISABLE	0xAD	/* Keyboard interface disable */
+#define KBD_CCMD_KBD_ENABLE	0xAE	/* Keyboard interface enable */
+#define KBD_CCMD_WRITE_AUX_OBUF	0xD3    /* Write to output buffer as if
+					   initiated by the auxiliary device */
+#define KBD_CCMD_WRITE_MOUSE	0xD4	/* Write the following byte to the mouse */
+
+/*
+ *	Keyboard Commands
+ */
+#define KBD_CMD_SET_LEDS	0xED	/* Set keyboard leds */
+#define KBD_CMD_SET_RATE	0xF3	/* Set typematic rate */
+#define KBD_CMD_ENABLE		0xF4	/* Enable scanning */
+#define KBD_CMD_DISABLE		0xF5	/* Disable scanning */
+#define KBD_CMD_RESET		0xFF	/* Reset */
+
+/*
+ *	Keyboard Replies
+ */
+#define KBD_REPLY_POR		0xAA	/* Power on reset */
+#define KBD_REPLY_ACK		0xFA	/* Command ACK */
+#define KBD_REPLY_RESEND	0xFE	/* Command NACK, send the cmd again */
+
+/*
+ *	Status Register Bits
+ */
+#define KBD_STAT_OBF 		0x01	/* Keyboard output buffer full */
+#define KBD_STAT_IBF 		0x02	/* Keyboard input buffer full */
+#define KBD_STAT_SELFTEST	0x04	/* Self test successful */
+#define KBD_STAT_CMD		0x08	/* Last write was a command write (0=data) */
+#define KBD_STAT_UNLOCKED	0x10	/* Zero if keyboard locked */
+#define KBD_STAT_MOUSE_OBF	0x20	/* Mouse output buffer full */
+#define KBD_STAT_GTO 		0x40	/* General receive/xmit timeout */
+#define KBD_STAT_PERR 		0x80	/* Parity error */
+
+#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
+
+/*
+ *	Controller Mode Register Bits
+ */
+#define KBD_MODE_KBD_INT	0x01	/* Keyboard data generate IRQ1 */
+#define KBD_MODE_MOUSE_INT	0x02	/* Mouse data generate IRQ12 */
+#define KBD_MODE_SYS 		0x04	/* The system flag (?) */
+#define KBD_MODE_NO_KEYLOCK	0x08	/* The keylock doesn't affect the keyboard if set */
+#define KBD_MODE_DISABLE_KBD	0x10	/* Disable keyboard interface */
+#define KBD_MODE_DISABLE_MOUSE	0x20	/* Disable mouse interface */
+#define KBD_MODE_KCC 		0x40	/* Scan code conversion to PC format */
+#define KBD_MODE_RFU		0x80
+
+/*
+ *	Mouse Commands
+ */
+#define AUX_SET_RES		0xE8	/* Set resolution */
+#define AUX_SET_SCALE11		0xE6	/* Set 1:1 scaling */
+#define AUX_SET_SCALE21		0xE7	/* Set 2:1 scaling */
+#define AUX_GET_SCALE		0xE9	/* Get scaling factor */
+#define AUX_SET_STREAM		0xEA	/* Set stream mode */
+#define AUX_SET_SAMPLE		0xF3	/* Set sample rate */
+#define AUX_ENABLE_DEV		0xF4	/* Enable aux device */
+#define AUX_DISABLE_DEV		0xF5	/* Disable aux device */
+#define AUX_RESET		0xFF	/* Reset aux device */
+#define AUX_ACK			0xFA	/* Command byte ACK. */
+
+#define AUX_BUF_SIZE		2048	/* This might be better divisible by
+					   three to make overruns stay in sync
+					   but then the read function would need
+					   a lock etc - ick */
+
+#if 0
+struct aux_queue {
+	unsigned long head;
+	unsigned long tail;
+	wait_queue_head_t proc_list;
+	struct fasync_struct *fasync;
+	unsigned char buf[AUX_BUF_SIZE];
+};
+#endif
diff --git a/include/pci.h b/include/pci.h
new file mode 100755
index 0000000..8f19997
--- /dev/null
+++ b/include/pci.h
@@ -0,0 +1,493 @@
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * aloong with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PCI_H
+#define _PCI_H
+
+/*
+ * Under PCI, each device has 256 bytes of configuration address space,
+ * of which the first 64 bytes are standardized as follows:
+ */
+#define PCI_VENDOR_ID		0x00	/* 16 bits */
+#define PCI_DEVICE_ID		0x02	/* 16 bits */
+#define PCI_COMMAND		0x04	/* 16 bits */
+#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
+#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
+#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
+#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
+#define  PCI_COMMAND_INVALIDATE 0x10	/* Use memory write and invalidate */
+#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
+#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
+#define  PCI_COMMAND_WAIT	0x80	/* Enable address/data stepping */
+#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
+#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
+
+#define PCI_STATUS		0x06	/* 16 bits */
+#define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
+#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
+#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
+#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
+#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
+#define  PCI_STATUS_DEVSEL_MASK 0x600	/* DEVSEL timing */
+#define  PCI_STATUS_DEVSEL_FAST 0x000
+#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
+#define  PCI_STATUS_DEVSEL_SLOW 0x400
+#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
+#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
+#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
+#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
+#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
+
+#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8
+					   revision */
+#define PCI_REVISION_ID		0x08	/* Revision ID */
+#define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
+#define PCI_CLASS_DEVICE	0x0a	/* Device class */
+#define PCI_CLASS_CODE		0x0b	/* Device class code */
+#define PCI_CLASS_SUB_CODE	0x0a	/* Device sub-class code */
+
+#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
+#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
+#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
+#define  PCI_HEADER_TYPE_NORMAL 0
+#define  PCI_HEADER_TYPE_BRIDGE 1
+#define  PCI_HEADER_TYPE_CARDBUS 2
+
+#define PCI_BIST		0x0f	/* 8 bits */
+#define PCI_BIST_CODE_MASK	0x0f	/* Return result */
+#define PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
+#define PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
+
+/*
+ * Base addresses specify locations in memory or I/O space.
+ * Decoded size can be determined by writing a value of
+ * 0xffffffff to the register, and reading it back.  Only
+ * 1 bits are decoded.
+ */
+#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
+#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
+#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
+#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
+#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
+#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
+#define  PCI_BASE_ADDRESS_SPACE 0x01	/* 0 = memory, 1 = I/O */
+#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
+#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
+#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
+#define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
+#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
+#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
+#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
+#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fUL)
+#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03UL)
+/* bit 1 is reserved if address_space = 1 */
+
+/* Header type 0 (normal devices) */
+#define PCI_CARDBUS_CIS		0x28
+#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
+#define PCI_SUBSYSTEM_ID	0x2e
+#define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
+#define  PCI_ROM_ADDRESS_ENABLE 0x01
+#define PCI_ROM_ADDRESS_MASK	(~0x7ffUL)
+
+#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
+
+/* 0x35-0x3b are reserved */
+#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
+#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
+#define PCI_MIN_GNT		0x3e	/* 8 bits */
+#define PCI_MAX_LAT		0x3f	/* 8 bits */
+
+/* Header type 1 (PCI-to-PCI bridges) */
+#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
+#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
+#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
+#define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
+#define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
+#define PCI_IO_LIMIT		0x1d
+#define  PCI_IO_RANGE_TYPE_MASK 0x0f	/* I/O bridging type */
+#define  PCI_IO_RANGE_TYPE_16	0x00
+#define  PCI_IO_RANGE_TYPE_32	0x01
+#define  PCI_IO_RANGE_MASK	~0x0f
+#define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
+#define PCI_MEMORY_BASE		0x20	/* Memory range behind */
+#define PCI_MEMORY_LIMIT	0x22
+#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
+#define  PCI_MEMORY_RANGE_MASK	~0x0f
+#define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
+#define PCI_PREF_MEMORY_LIMIT	0x26
+#define  PCI_PREF_RANGE_TYPE_MASK 0x0f
+#define  PCI_PREF_RANGE_TYPE_32 0x00
+#define  PCI_PREF_RANGE_TYPE_64 0x01
+#define  PCI_PREF_RANGE_MASK	~0x0f
+#define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
+#define PCI_PREF_LIMIT_UPPER32	0x2c
+#define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
+#define PCI_IO_LIMIT_UPPER16	0x32
+/* 0x34 same as for htype 0 */
+/* 0x35-0x3b is reserved */
+#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
+/* 0x3c-0x3d are same as for htype 0 */
+#define PCI_BRIDGE_CONTROL	0x3e
+#define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
+#define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
+#define  PCI_BRIDGE_CTL_NO_ISA	0x04	/* Disable bridging of ISA ports */
+#define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
+#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
+#define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */
+#define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */
+
+/* From 440ep */
+#define PCI_ERREN       0x48     /* Error Enable */
+#define PCI_ERRSTS      0x49     /* Error Status */
+#define PCI_BRDGOPT1    0x4A     /* PCI Bridge Options 1 */
+#define PCI_PLBSESR0    0x4C     /* PCI PLB Slave Error Syndrome 0 */
+#define PCI_PLBSESR1    0x50     /* PCI PLB Slave Error Syndrome 1 */
+#define PCI_PLBSEAR     0x54     /* PCI PLB Slave Error Address */
+#define PCI_CAPID       0x58     /* Capability Identifier */
+#define PCI_NEXTITEMPTR 0x59     /* Next Item Pointer */
+#define PCI_PMC         0x5A     /* Power Management Capabilities */
+#define PCI_PMCSR       0x5C     /* Power Management Control Status */
+#define PCI_PMCSRBSE    0x5E     /* PMCSR PCI to PCI Bridge Support Extensions */
+#define PCI_BRDGOPT2    0x60     /* PCI Bridge Options 2 */
+#define PCI_PMSCRR      0x64     /* Power Management State Change Request Re. */
+
+/* Header type 2 (CardBus bridges) */
+#define PCI_CB_CAPABILITY_LIST	0x14
+/* 0x15 reserved */
+#define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
+#define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
+#define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
+#define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
+#define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
+#define PCI_CB_MEMORY_BASE_0	0x1c
+#define PCI_CB_MEMORY_LIMIT_0	0x20
+#define PCI_CB_MEMORY_BASE_1	0x24
+#define PCI_CB_MEMORY_LIMIT_1	0x28
+#define PCI_CB_IO_BASE_0	0x2c
+#define PCI_CB_IO_BASE_0_HI	0x2e
+#define PCI_CB_IO_LIMIT_0	0x30
+#define PCI_CB_IO_LIMIT_0_HI	0x32
+#define PCI_CB_IO_BASE_1	0x34
+#define PCI_CB_IO_BASE_1_HI	0x36
+#define PCI_CB_IO_LIMIT_1	0x38
+#define PCI_CB_IO_LIMIT_1_HI	0x3a
+#define  PCI_CB_IO_RANGE_MASK	~0x03
+/* 0x3c-0x3d are same as for htype 0 */
+#define PCI_CB_BRIDGE_CONTROL	0x3e
+#define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
+#define  PCI_CB_BRIDGE_CTL_SERR		0x02
+#define  PCI_CB_BRIDGE_CTL_ISA		0x04
+#define  PCI_CB_BRIDGE_CTL_VGA		0x08
+#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
+#define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
+#define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
+#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
+#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
+#define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
+#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
+#define PCI_CB_SUBSYSTEM_ID	0x42
+#define PCI_CB_LEGACY_MODE_BASE 0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
+/* 0x48-0x7f reserved */
+
+/* Capability lists */
+
+#define PCI_CAP_LIST_ID		0	/* Capability ID */
+#define  PCI_CAP_ID_PM		0x01	/* Power Management */
+#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
+#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
+#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
+#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
+#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
+#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
+#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
+#define PCI_CAP_SIZEOF		4
+
+/* Power Management Registers */
+
+#define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
+#define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
+#define  PCI_PM_CAP_AUX_POWER	0x0010	/* Auxilliary power support */
+#define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
+#define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
+#define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
+#define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
+#define PCI_PM_CTRL		4	/* PM control and status register */
+#define  PCI_PM_CTRL_STATE_MASK 0x0003	/* Current power state (D0 to D3) */
+#define  PCI_PM_CTRL_PME_ENABLE 0x0100	/* PME pin enable */
+#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
+#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
+#define  PCI_PM_CTRL_PME_STATUS 0x8000	/* PME pin status */
+#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
+#define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
+#define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
+#define PCI_PM_DATA_REGISTER	7	/* (??) */
+#define PCI_PM_SIZEOF		8
+
+/* AGP registers */
+
+#define PCI_AGP_VERSION		2	/* BCD version number */
+#define PCI_AGP_RFU		3	/* Rest of capability flags */
+#define PCI_AGP_STATUS		4	/* Status register */
+#define  PCI_AGP_STATUS_RQ_MASK 0xff000000	/* Maximum number of requests - 1 */
+#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
+#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
+#define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
+#define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
+#define PCI_AGP_COMMAND		8	/* Control register */
+#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
+#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
+#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
+#define  PCI_AGP_COMMAND_64BIT	0x0020	/* Allow processing of 64-bit addresses */
+#define  PCI_AGP_COMMAND_FW	0x0010	/* Force FW transfers */
+#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
+#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 4x rate */
+#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 4x rate */
+#define PCI_AGP_SIZEOF		12
+
+/* Slot Identification */
+
+#define PCI_SID_ESR		2	/* Expansion Slot Register */
+#define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
+#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
+#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
+
+/* Message Signalled Interrupts registers */
+
+#define PCI_MSI_FLAGS		2	/* Various flags */
+#define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
+#define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
+#define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
+#define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
+#define PCI_MSI_RFU		3	/* Rest of capability flags */
+#define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
+#define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
+#define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
+#define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
+
+#define PCI_MAX_PCI_DEVICES	32
+#define PCI_MAX_PCI_FUNCTIONS	8
+
+/* Include the ID list */
+
+#include <pci_ids.h>
+
+struct pci_region {
+	unsigned long bus_start;		/* Start on the bus */
+	unsigned long phys_start;		/* Start in physical address space */
+	unsigned long size;			/* Size */
+	unsigned long flags;			/* Resource flags */
+
+	unsigned long bus_lower;
+};
+
+#define PCI_REGION_MEM		0x00000000	/* PCI memory space */
+#define PCI_REGION_IO		0x00000001	/* PCI IO space */
+#define PCI_REGION_TYPE		0x00000001
+
+#define PCI_REGION_MEMORY	0x00000100	/* System memory */
+#define PCI_REGION_RO		0x00000200	/* Read-only memory */
+
+extern __inline__ void pci_set_region(struct pci_region *reg,
+				      unsigned long bus_start,
+				      unsigned long phys_start,
+				      unsigned long size,
+				      unsigned long flags) {
+	reg->bus_start	= bus_start;
+	reg->phys_start = phys_start;
+	reg->size	= size;
+	reg->flags	= flags;
+}
+
+typedef int pci_dev_t;
+
+#define PCI_BUS(d)	(((d) >> 16) & 0xff)
+#define PCI_DEV(d)	(((d) >> 11) & 0x1f)
+#define PCI_FUNC(d)	(((d) >> 8) & 0x7)
+#define PCI_BDF(b,d,f)	((b) << 16 | (d) << 11 | (f) << 8)
+
+#define PCI_ANY_ID (~0)
+
+struct pci_device_id {
+	unsigned int vendor, device;		/* Vendor and device ID or PCI_ANY_ID */
+};
+
+struct pci_controller;
+
+struct pci_config_table {
+	unsigned int vendor, device;		/* Vendor and device ID or PCI_ANY_ID */
+	unsigned int class;			/* Class ID, or  PCI_ANY_ID */
+	unsigned int bus;			/* Bus number, or PCI_ANY_ID */
+	unsigned int dev;			/* Device number, or PCI_ANY_ID */
+	unsigned int func;			/* Function number, or PCI_ANY_ID */
+
+	void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
+			      struct pci_config_table *);
+	unsigned long priv[3];
+};
+
+extern void pci_cfgfunc_nothing(struct pci_controller* hose, pci_dev_t dev,
+				struct pci_config_table *);
+extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
+				      struct pci_config_table *);
+
+#define MAX_PCI_REGIONS		7
+
+/*
+ * Structure of a PCI controller (host bridge)
+ */
+struct pci_controller {
+	struct pci_controller *next;
+
+	int first_busno;
+	int last_busno;
+
+	volatile unsigned int *cfg_addr;
+	volatile unsigned char *cfg_data;
+
+	struct pci_region regions[MAX_PCI_REGIONS];
+	int region_count;
+
+	struct pci_config_table *config_table;
+
+	void (*fixup_irq)(struct pci_controller *, pci_dev_t);
+
+	/* Low-level architecture-dependent routines */
+	int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
+	int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
+	int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
+	int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
+	int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
+	int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
+
+	/* Used by auto config */
+	struct pci_region *pci_mem, *pci_io;
+
+	/* Used by ppc405 autoconfig*/
+	struct pci_region *pci_fb;
+	int current_busno;
+};
+
+extern __inline__ void pci_set_ops(struct pci_controller *hose,
+				   int (*read_byte)(struct pci_controller*,
+						    pci_dev_t, int where, u8 *),
+				   int (*read_word)(struct pci_controller*,
+						    pci_dev_t, int where, u16 *),
+				   int (*read_dword)(struct pci_controller*,
+						     pci_dev_t, int where, u32 *),
+				   int (*write_byte)(struct pci_controller*,
+						     pci_dev_t, int where, u8),
+				   int (*write_word)(struct pci_controller*,
+						     pci_dev_t, int where, u16),
+				   int (*write_dword)(struct pci_controller*,
+						      pci_dev_t, int where, u32)) {
+	hose->read_byte   = read_byte;
+	hose->read_word   = read_word;
+	hose->read_dword  = read_dword;
+	hose->write_byte  = write_byte;
+	hose->write_word  = write_word;
+	hose->write_dword = write_dword;
+}
+
+extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
+
+extern unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
+					  unsigned long addr, unsigned long flags);
+extern unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
+					  unsigned long addr, unsigned long flags);
+
+#define pci_phys_to_bus(dev, addr, flags) \
+	pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
+#define pci_bus_to_phys(dev, addr, flags) \
+	pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
+
+#define pci_phys_to_mem(dev, addr)	pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
+#define pci_mem_to_phys(dev, addr)	pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
+#define pci_phys_to_io(dev, addr)	pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
+#define pci_io_to_phys(dev, addr)	pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
+
+extern int pci_hose_read_config_byte(struct pci_controller *hose,
+				     pci_dev_t dev, int where, u8 *val);
+extern int pci_hose_read_config_word(struct pci_controller *hose,
+				     pci_dev_t dev, int where, u16 *val);
+extern int pci_hose_read_config_dword(struct pci_controller *hose,
+				      pci_dev_t dev, int where, u32 *val);
+extern int pci_hose_write_config_byte(struct pci_controller *hose,
+				      pci_dev_t dev, int where, u8 val);
+extern int pci_hose_write_config_word(struct pci_controller *hose,
+				      pci_dev_t dev, int where, u16 val);
+extern int pci_hose_write_config_dword(struct pci_controller *hose,
+				       pci_dev_t dev, int where, u32 val);
+
+extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
+extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
+extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
+extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
+extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
+extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
+
+extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
+					       pci_dev_t dev, int where, u8 *val);
+extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
+					       pci_dev_t dev, int where, u16 *val);
+extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
+						pci_dev_t dev, int where, u8 val);
+extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
+						pci_dev_t dev, int where, u16 val);
+
+extern void pci_register_hose(struct pci_controller* hose);
+extern struct pci_controller* pci_bus_to_hose(int bus);
+
+extern int pci_hose_scan(struct pci_controller *hose);
+extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
+
+extern void pciauto_region_init(struct pci_region* res);
+extern void pciauto_region_align(struct pci_region *res, unsigned long size);
+extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
+extern void pciauto_setup_device(struct pci_controller *hose,
+				 pci_dev_t dev, int bars_num,
+				 struct pci_region *mem,
+				 struct pci_region *io);
+int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
+
+extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
+extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
+extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
+				int wanted_prog_if, int index);
+
+extern int pci_hose_config_device(struct pci_controller *hose,
+				  pci_dev_t dev,
+				  unsigned long io,
+				  unsigned long mem,
+				  unsigned long command);
+
+#ifdef CONFIG_MPC824X
+extern void pci_mpc824x_init (struct pci_controller *hose);
+#endif
+
+#endif	/* _PCI_H */
diff --git a/include/pci_ids.h b/include/pci_ids.h
new file mode 100755
index 0000000..7dec378
--- /dev/null
+++ b/include/pci_ids.h
@@ -0,0 +1,2048 @@
+/*
+ *	PCI Class, Vendor and Device IDs
+ *
+ *	Please keep sorted.
+ */
+
+/* Device classes and subclasses */
+
+#define PCI_CLASS_NOT_DEFINED		0x0000
+#define PCI_CLASS_NOT_DEFINED_VGA	0x0001
+
+#define PCI_BASE_CLASS_STORAGE		0x01
+#define PCI_CLASS_STORAGE_SCSI		0x0100
+#define PCI_CLASS_STORAGE_IDE		0x0101
+#define PCI_CLASS_STORAGE_FLOPPY	0x0102
+#define PCI_CLASS_STORAGE_IPI		0x0103
+#define PCI_CLASS_STORAGE_RAID		0x0104
+#define PCI_CLASS_STORAGE_OTHER		0x0180
+
+#define PCI_BASE_CLASS_NETWORK		0x02
+#define PCI_CLASS_NETWORK_ETHERNET	0x0200
+#define PCI_CLASS_NETWORK_TOKEN_RING	0x0201
+#define PCI_CLASS_NETWORK_FDDI		0x0202
+#define PCI_CLASS_NETWORK_ATM		0x0203
+#define PCI_CLASS_NETWORK_OTHER		0x0280
+
+#define PCI_BASE_CLASS_DISPLAY		0x03
+#define PCI_CLASS_DISPLAY_VGA		0x0300
+#define PCI_CLASS_DISPLAY_XGA		0x0301
+#define PCI_CLASS_DISPLAY_3D		0x0302
+#define PCI_CLASS_DISPLAY_OTHER		0x0380
+
+#define PCI_BASE_CLASS_MULTIMEDIA	0x04
+#define PCI_CLASS_MULTIMEDIA_VIDEO	0x0400
+#define PCI_CLASS_MULTIMEDIA_AUDIO	0x0401
+#define PCI_CLASS_MULTIMEDIA_PHONE	0x0402
+#define PCI_CLASS_MULTIMEDIA_OTHER	0x0480
+
+#define PCI_BASE_CLASS_MEMORY		0x05
+#define PCI_CLASS_MEMORY_RAM		0x0500
+#define PCI_CLASS_MEMORY_FLASH		0x0501
+#define PCI_CLASS_MEMORY_OTHER		0x0580
+
+#define PCI_BASE_CLASS_BRIDGE		0x06
+#define PCI_CLASS_BRIDGE_HOST		0x0600
+#define PCI_CLASS_BRIDGE_ISA		0x0601
+#define PCI_CLASS_BRIDGE_EISA		0x0602
+#define PCI_CLASS_BRIDGE_MC		0x0603
+#define PCI_CLASS_BRIDGE_PCI		0x0604
+#define PCI_CLASS_BRIDGE_PCMCIA		0x0605
+#define PCI_CLASS_BRIDGE_NUBUS		0x0606
+#define PCI_CLASS_BRIDGE_CARDBUS	0x0607
+#define PCI_CLASS_BRIDGE_RACEWAY	0x0608
+#define PCI_CLASS_BRIDGE_OTHER		0x0680
+
+#define PCI_BASE_CLASS_COMMUNICATION	0x07
+#define PCI_CLASS_COMMUNICATION_SERIAL	0x0700
+#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
+#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
+#define PCI_CLASS_COMMUNICATION_MODEM	0x0703
+#define PCI_CLASS_COMMUNICATION_OTHER	0x0780
+
+#define PCI_BASE_CLASS_SYSTEM		0x08
+#define PCI_CLASS_SYSTEM_PIC		0x0800
+#define PCI_CLASS_SYSTEM_DMA		0x0801
+#define PCI_CLASS_SYSTEM_TIMER		0x0802
+#define PCI_CLASS_SYSTEM_RTC		0x0803
+#define PCI_CLASS_SYSTEM_PCI_HOTPLUG	0x0804
+#define PCI_CLASS_SYSTEM_OTHER		0x0880
+
+#define PCI_BASE_CLASS_INPUT		0x09
+#define PCI_CLASS_INPUT_KEYBOARD	0x0900
+#define PCI_CLASS_INPUT_PEN		0x0901
+#define PCI_CLASS_INPUT_MOUSE		0x0902
+#define PCI_CLASS_INPUT_SCANNER		0x0903
+#define PCI_CLASS_INPUT_GAMEPORT	0x0904
+#define PCI_CLASS_INPUT_OTHER		0x0980
+
+#define PCI_BASE_CLASS_DOCKING		0x0a
+#define PCI_CLASS_DOCKING_GENERIC	0x0a00
+#define PCI_CLASS_DOCKING_OTHER		0x0a80
+
+#define PCI_BASE_CLASS_PROCESSOR	0x0b
+#define PCI_CLASS_PROCESSOR_386		0x0b00
+#define PCI_CLASS_PROCESSOR_486		0x0b01
+#define PCI_CLASS_PROCESSOR_PENTIUM	0x0b02
+#define PCI_CLASS_PROCESSOR_ALPHA	0x0b10
+#define PCI_CLASS_PROCESSOR_POWERPC	0x0b20
+#define PCI_CLASS_PROCESSOR_MIPS	0x0b30
+#define PCI_CLASS_PROCESSOR_CO		0x0b40
+
+#define PCI_BASE_CLASS_SERIAL		0x0c
+#define PCI_CLASS_SERIAL_FIREWIRE	0x0c00
+#define PCI_CLASS_SERIAL_ACCESS		0x0c01
+#define PCI_CLASS_SERIAL_SSA		0x0c02
+#define PCI_CLASS_SERIAL_USB		0x0c03
+#define PCI_CLASS_SERIAL_FIBER		0x0c04
+#define PCI_CLASS_SERIAL_SMBUS		0x0c05
+
+#define PCI_BASE_CLASS_INTELLIGENT	0x0e
+#define PCI_CLASS_INTELLIGENT_I2O	0x0e00
+
+#define PCI_BASE_CLASS_SATELLITE	0x0f
+#define PCI_CLASS_SATELLITE_TV		0x0f00
+#define PCI_CLASS_SATELLITE_AUDIO	0x0f01
+#define PCI_CLASS_SATELLITE_VOICE	0x0f03
+#define PCI_CLASS_SATELLITE_DATA	0x0f04
+
+#define PCI_BASE_CLASS_CRYPT		0x10
+#define PCI_CLASS_CRYPT_NETWORK		0x1000
+#define PCI_CLASS_CRYPT_ENTERTAINMENT	0x1001
+#define PCI_CLASS_CRYPT_OTHER		0x1080
+
+#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
+#define PCI_CLASS_SP_DPIO		0x1100
+#define PCI_CLASS_SP_OTHER		0x1180
+
+#define PCI_CLASS_OTHERS		0xff
+
+/* Vendors and devices.	 Sort key: vendor first, device next. */
+
+#define PCI_VENDOR_ID_DYNALINK		0x0675
+#define PCI_DEVICE_ID_DYNALINK_IS64PH	0x1702
+
+#define PCI_VENDOR_ID_BERKOM			0x0871
+#define PCI_DEVICE_ID_BERKOM_A1T		0xffa1
+#define PCI_DEVICE_ID_BERKOM_T_CONCEPT		0xffa2
+#define PCI_DEVICE_ID_BERKOM_A4T		0xffa4
+#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO	0xffa8
+
+#define PCI_VENDOR_ID_COMPAQ		0x0e11
+#define PCI_DEVICE_ID_COMPAQ_TOKENRING	0x0508
+#define PCI_DEVICE_ID_COMPAQ_1280	0x3033
+#define PCI_DEVICE_ID_COMPAQ_TRIFLEX	0x4000
+#define PCI_DEVICE_ID_COMPAQ_6010	0x6010
+#define PCI_DEVICE_ID_COMPAQ_TACHYON	0xa0fc
+#define PCI_DEVICE_ID_COMPAQ_SMART2P	0xae10
+#define PCI_DEVICE_ID_COMPAQ_NETEL100	0xae32
+#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33
+#define PCI_DEVICE_ID_COMPAQ_NETEL10	0xae34
+#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I	0xae35
+#define PCI_DEVICE_ID_COMPAQ_NETEL100D	0xae40
+#define PCI_DEVICE_ID_COMPAQ_NETEL100PI 0xae43
+#define PCI_DEVICE_ID_COMPAQ_NETEL100I	0xb011
+#define PCI_DEVICE_ID_COMPAQ_CISS	0xb060
+#define PCI_DEVICE_ID_COMPAQ_CISSB	0xb178
+#define PCI_DEVICE_ID_COMPAQ_CISSC	0x0046
+#define PCI_DEVICE_ID_COMPAQ_THUNDER	0xf130
+#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B	0xf150
+
+#define PCI_VENDOR_ID_NCR		0x1000
+#define PCI_VENDOR_ID_LSI_LOGIC		0x1000
+#define PCI_DEVICE_ID_NCR_53C810	0x0001
+#define PCI_DEVICE_ID_NCR_53C820	0x0002
+#define PCI_DEVICE_ID_NCR_53C825	0x0003
+#define PCI_DEVICE_ID_NCR_53C815	0x0004
+#define PCI_DEVICE_ID_LSI_53C810AP	0x0005
+#define PCI_DEVICE_ID_NCR_53C860	0x0006
+#define PCI_DEVICE_ID_LSI_53C1510	0x000a
+#define PCI_DEVICE_ID_NCR_53C896	0x000b
+#define PCI_DEVICE_ID_NCR_53C895	0x000c
+#define PCI_DEVICE_ID_NCR_53C885	0x000d
+#define PCI_DEVICE_ID_NCR_53C875	0x000f
+#define PCI_DEVICE_ID_NCR_53C1510	0x0010
+#define PCI_DEVICE_ID_LSI_53C895A	0x0012
+#define PCI_DEVICE_ID_LSI_53C875A	0x0013
+#define PCI_DEVICE_ID_LSI_53C1010_33	0x0020
+#define PCI_DEVICE_ID_LSI_53C1010_66	0x0021
+#define PCI_DEVICE_ID_LSI_53C1030	0x0030
+#define PCI_DEVICE_ID_LSI_53C1035	0x0040
+#define PCI_DEVICE_ID_NCR_53C875J	0x008f
+#define PCI_DEVICE_ID_LSI_FC909		0x0621
+#define PCI_DEVICE_ID_LSI_FC929		0x0622
+#define PCI_DEVICE_ID_LSI_FC929_LAN	0x0623
+#define PCI_DEVICE_ID_LSI_FC919		0x0624
+#define PCI_DEVICE_ID_LSI_FC919_LAN	0x0625
+#define PCI_DEVICE_ID_LSI_FC929X	0x0626
+#define PCI_DEVICE_ID_LSI_FC919X	0x0628
+#define PCI_DEVICE_ID_NCR_YELLOWFIN	0x0701
+#define PCI_DEVICE_ID_LSI_61C102	0x0901
+#define PCI_DEVICE_ID_LSI_63C815	0x1000
+
+#define PCI_VENDOR_ID_ATI		0x1002
+/* Mach64 */
+#define PCI_DEVICE_ID_ATI_68800		0x4158
+#define PCI_DEVICE_ID_ATI_215CT222	0x4354
+#define PCI_DEVICE_ID_ATI_210888CX	0x4358
+#define PCI_DEVICE_ID_ATI_215ET222	0x4554
+/* Mach64 / Rage */
+#define PCI_DEVICE_ID_ATI_215GB		0x4742
+#define PCI_DEVICE_ID_ATI_215GD		0x4744
+#define PCI_DEVICE_ID_ATI_215GI		0x4749
+#define PCI_DEVICE_ID_ATI_215GP		0x4750
+#define PCI_DEVICE_ID_ATI_215GQ		0x4751
+#define PCI_DEVICE_ID_ATI_215XL		0x4752
+#define PCI_DEVICE_ID_ATI_215GT		0x4754
+#define PCI_DEVICE_ID_ATI_215GTB	0x4755
+#define PCI_DEVICE_ID_ATI_215_IV	0x4756
+#define PCI_DEVICE_ID_ATI_215_IW	0x4757
+#define PCI_DEVICE_ID_ATI_215_IZ	0x475A
+#define PCI_DEVICE_ID_ATI_210888GX	0x4758
+#define PCI_DEVICE_ID_ATI_215_LB	0x4c42
+#define PCI_DEVICE_ID_ATI_215_LD	0x4c44
+#define PCI_DEVICE_ID_ATI_215_LG	0x4c47
+#define PCI_DEVICE_ID_ATI_215_LI	0x4c49
+#define PCI_DEVICE_ID_ATI_215_LM	0x4c4D
+#define PCI_DEVICE_ID_ATI_215_LN	0x4c4E
+#define PCI_DEVICE_ID_ATI_215_LR	0x4c52
+#define PCI_DEVICE_ID_ATI_215_LS	0x4c53
+#define PCI_DEVICE_ID_ATI_264_LT	0x4c54
+/* Mach64 VT */
+#define PCI_DEVICE_ID_ATI_264VT		0x5654
+#define PCI_DEVICE_ID_ATI_264VU		0x5655
+#define PCI_DEVICE_ID_ATI_264VV		0x5656
+/* Rage128 Pro GL */
+#define PCI_DEVICE_ID_ATI_Rage128_PA	0x5041
+#define PCI_DEVICE_ID_ATI_Rage128_PB	0x5042
+#define PCI_DEVICE_ID_ATI_Rage128_PC	0x5043
+#define PCI_DEVICE_ID_ATI_Rage128_PD	0x5044
+#define PCI_DEVICE_ID_ATI_Rage128_PE	0x5045
+#define PCI_DEVICE_ID_ATI_RAGE128_PF	0x5046
+/* Rage128 Pro VR */
+#define PCI_DEVICE_ID_ATI_RAGE128_PG	0x5047
+#define PCI_DEVICE_ID_ATI_RAGE128_PH	0x5048
+#define PCI_DEVICE_ID_ATI_RAGE128_PI	0x5049
+#define PCI_DEVICE_ID_ATI_RAGE128_PJ	0x504A
+#define PCI_DEVICE_ID_ATI_RAGE128_PK	0x504B
+#define PCI_DEVICE_ID_ATI_RAGE128_PL	0x504C
+#define PCI_DEVICE_ID_ATI_RAGE128_PM	0x504D
+#define PCI_DEVICE_ID_ATI_RAGE128_PN	0x504E
+#define PCI_DEVICE_ID_ATI_RAGE128_PO	0x504F
+#define PCI_DEVICE_ID_ATI_RAGE128_PP	0x5050
+#define PCI_DEVICE_ID_ATI_RAGE128_PQ	0x5051
+#define PCI_DEVICE_ID_ATI_RAGE128_PR	0x5052
+#define PCI_DEVICE_ID_ATI_RAGE128_TR	0x5452
+#define PCI_DEVICE_ID_ATI_RAGE128_PS	0x5053
+#define PCI_DEVICE_ID_ATI_RAGE128_PT	0x5054
+#define PCI_DEVICE_ID_ATI_RAGE128_PU	0x5055
+#define PCI_DEVICE_ID_ATI_RAGE128_PV	0x5056
+#define PCI_DEVICE_ID_ATI_RAGE128_PW	0x5057
+#define PCI_DEVICE_ID_ATI_RAGE128_PX	0x5058
+/* Rage128 GL */
+#define PCI_DEVICE_ID_ATI_RAGE128_RE	0x5245
+#define PCI_DEVICE_ID_ATI_RAGE128_RF	0x5246
+#define PCI_DEVICE_ID_ATI_RAGE128_RG	0x534b
+#define PCI_DEVICE_ID_ATI_RAGE128_RH	0x534c
+#define PCI_DEVICE_ID_ATI_RAGE128_RI	0x534d
+/* Rage128 VR */
+#define PCI_DEVICE_ID_ATI_RAGE128_RK	0x524b
+#define PCI_DEVICE_ID_ATI_RAGE128_RL	0x524c
+#define PCI_DEVICE_ID_ATI_RAGE128_RM	0x5345
+#define PCI_DEVICE_ID_ATI_RAGE128_RN	0x5346
+#define PCI_DEVICE_ID_ATI_RAGE128_RO	0x5347
+/* Rage128 M3 */
+#define PCI_DEVICE_ID_ATI_RAGE128_LE	0x4c45
+#define PCI_DEVICE_ID_ATI_RAGE128_LF	0x4c46
+/* Rage128 Pro Ultra */
+#define PCI_DEVICE_ID_ATI_RAGE128_U1	0x5446
+#define PCI_DEVICE_ID_ATI_RAGE128_U2	0x544C
+#define PCI_DEVICE_ID_ATI_RAGE128_U3	0x5452
+/* Rage M4 */
+#define PCI_DEVICE_ID_ATI_RADEON_LE	0x4d45
+#define PCI_DEVICE_ID_ATI_RADEON_LF	0x4d46
+/* Radeon R100 */
+#define PCI_DEVICE_ID_ATI_RADEON_QD	0x5144
+#define PCI_DEVICE_ID_ATI_RADEON_QE	0x5145
+#define PCI_DEVICE_ID_ATI_RADEON_QF	0x5146
+#define PCI_DEVICE_ID_ATI_RADEON_QG	0x5147
+/* Radeon RV100 (VE) */
+#define PCI_DEVICE_ID_ATI_RADEON_QY	0x5159
+#define PCI_DEVICE_ID_ATI_RADEON_QZ	0x515a
+/* Radeon R200 (8500) */
+#define PCI_DEVICE_ID_ATI_RADEON_QL	0x514c
+#define PCI_DEVICE_ID_ATI_RADEON_QN	0x514e
+#define PCI_DEVICE_ID_ATI_RADEON_QO	0x514f
+#define PCI_DEVICE_ID_ATI_RADEON_Ql	0x516c
+#define PCI_DEVICE_ID_ATI_RADEON_BB	0x4242
+/* Radeon R200 (9100) */
+#define PCI_DEVICE_ID_ATI_RADEON_QM	0x514d
+/* Radeon RV200 (7500) */
+#define PCI_DEVICE_ID_ATI_RADEON_QW	0x5157
+#define PCI_DEVICE_ID_ATI_RADEON_QX	0x5158
+/* Radeon RV250 (9000) */
+#define PCI_DEVICE_ID_ATI_RADEON_Id	0x4964
+#define PCI_DEVICE_ID_ATI_RADEON_Ie	0x4965
+#define PCI_DEVICE_ID_ATI_RADEON_If	0x4966
+#define PCI_DEVICE_ID_ATI_RADEON_Ig	0x4967
+/* Radeon RV280 (9200) */
+#define PCI_DEVICE_ID_ATI_RADEON_Y_	0x5960
+#define PCI_DEVICE_ID_ATI_RADEON_Ya	0x5961
+#define PCI_DEVICE_ID_ATI_RADEON_Yd	0x5964
+/* Radeon R300 (9700) */
+#define PCI_DEVICE_ID_ATI_RADEON_ND	0x4e44
+#define PCI_DEVICE_ID_ATI_RADEON_NE	0x4e45
+#define PCI_DEVICE_ID_ATI_RADEON_NF	0x4e46
+#define PCI_DEVICE_ID_ATI_RADEON_NG	0x4e47
+#define PCI_DEVICE_ID_ATI_RADEON_AE	0x4145
+#define PCI_DEVICE_ID_ATI_RADEON_AF	0x4146
+/* Radeon R300 (9500) */
+#define PCI_DEVICE_ID_ATI_RADEON_AD	0x4144
+/* Radeon R350 (9800) */
+#define PCI_DEVICE_ID_ATI_RADEON_NH	0x4e48
+#define PCI_DEVICE_ID_ATI_RADEON_NI	0x4e49
+/* Radeon RV350 (9600) */
+#define PCI_DEVICE_ID_ATI_RADEON_AP	0x4150
+#define PCI_DEVICE_ID_ATI_RADEON_AR	0x4152
+/* Radeon M6 */
+#define PCI_DEVICE_ID_ATI_RADEON_LY	0x4c59
+#define PCI_DEVICE_ID_ATI_RADEON_LZ	0x4c5a
+/* Radeon M7 */
+#define PCI_DEVICE_ID_ATI_RADEON_LW	0x4c57
+#define PCI_DEVICE_ID_ATI_RADEON_LX	0x4c58
+/* Radeon M9 */
+#define PCI_DEVICE_ID_ATI_RADEON_Ld	0x4c64
+#define PCI_DEVICE_ID_ATI_RADEON_Le	0x4c65
+#define PCI_DEVICE_ID_ATI_RADEON_Lf	0x4c66
+#define PCI_DEVICE_ID_ATI_RADEON_Lg	0x4c67
+/* RadeonIGP */
+#define PCI_DEVICE_ID_ATI_RADEON_IGP	0xCAB0
+/* ATI IXP Chipset */
+#define PCI_DEVICE_ID_ATI_IXP_IDE	0x4349
+
+#define PCI_VENDOR_ID_VLSI		0x1004
+#define PCI_DEVICE_ID_VLSI_82C592	0x0005
+#define PCI_DEVICE_ID_VLSI_82C593	0x0006
+#define PCI_DEVICE_ID_VLSI_82C594	0x0007
+#define PCI_DEVICE_ID_VLSI_82C597	0x0009
+#define PCI_DEVICE_ID_VLSI_82C541	0x000c
+#define PCI_DEVICE_ID_VLSI_82C543	0x000d
+#define PCI_DEVICE_ID_VLSI_82C532	0x0101
+#define PCI_DEVICE_ID_VLSI_82C534	0x0102
+#define PCI_DEVICE_ID_VLSI_82C535	0x0104
+#define PCI_DEVICE_ID_VLSI_82C147	0x0105
+#define PCI_DEVICE_ID_VLSI_VAS96011	0x0702
+
+#define PCI_VENDOR_ID_ADL		0x1005
+#define PCI_DEVICE_ID_ADL_2301		0x2301
+
+#define PCI_VENDOR_ID_NS		0x100b
+#define PCI_DEVICE_ID_NS_87415		0x0002
+#define PCI_DEVICE_ID_NS_87560_LIO	0x000e
+#define PCI_DEVICE_ID_NS_87560_USB	0x0012
+#define PCI_DEVICE_ID_NS_83815		0x0020
+#define PCI_DEVICE_ID_NS_83820		0x0022
+#define PCI_DEVICE_ID_NS_SCx200_BRIDGE	0x0500
+#define PCI_DEVICE_ID_NS_SCx200_SMI	0x0501
+#define PCI_DEVICE_ID_NS_SCx200_IDE	0x0502
+#define PCI_DEVICE_ID_NS_SCx200_AUDIO	0x0503
+#define PCI_DEVICE_ID_NS_SCx200_VIDEO	0x0504
+#define PCI_DEVICE_ID_NS_SCx200_XBUS	0x0505
+#define PCI_DEVICE_ID_NS_87410		0xd001
+
+#define PCI_VENDOR_ID_TSENG		0x100c
+#define PCI_DEVICE_ID_TSENG_W32P_2	0x3202
+#define PCI_DEVICE_ID_TSENG_W32P_b	0x3205
+#define PCI_DEVICE_ID_TSENG_W32P_c	0x3206
+#define PCI_DEVICE_ID_TSENG_W32P_d	0x3207
+#define PCI_DEVICE_ID_TSENG_ET6000	0x3208
+
+#define PCI_VENDOR_ID_WEITEK		0x100e
+#define PCI_DEVICE_ID_WEITEK_P9000	0x9001
+#define PCI_DEVICE_ID_WEITEK_P9100	0x9100
+
+#define PCI_VENDOR_ID_DEC		0x1011
+#define PCI_DEVICE_ID_DEC_BRD		0x0001
+#define PCI_DEVICE_ID_DEC_TULIP		0x0002
+#define PCI_DEVICE_ID_DEC_TGA		0x0004
+#define PCI_DEVICE_ID_DEC_TULIP_FAST	0x0009
+#define PCI_DEVICE_ID_DEC_TGA2		0x000D
+#define PCI_DEVICE_ID_DEC_FDDI		0x000F
+#define PCI_DEVICE_ID_DEC_TULIP_PLUS	0x0014
+#define PCI_DEVICE_ID_DEC_21142		0x0019
+#define PCI_DEVICE_ID_DEC_21052		0x0021
+#define PCI_DEVICE_ID_DEC_21150		0x0022
+#define PCI_DEVICE_ID_DEC_21152		0x0024
+#define PCI_DEVICE_ID_DEC_21153		0x0025
+#define PCI_DEVICE_ID_DEC_21154		0x0026
+#define PCI_DEVICE_ID_DEC_21285		0x1065
+#define PCI_DEVICE_ID_COMPAQ_42XX	0x0046
+
+#define PCI_VENDOR_ID_CIRRUS		0x1013
+#define PCI_DEVICE_ID_CIRRUS_7548	0x0038
+#define PCI_DEVICE_ID_CIRRUS_5430	0x00a0
+#define PCI_DEVICE_ID_CIRRUS_5434_4	0x00a4
+#define PCI_DEVICE_ID_CIRRUS_5434_8	0x00a8
+#define PCI_DEVICE_ID_CIRRUS_5436	0x00ac
+#define PCI_DEVICE_ID_CIRRUS_5446	0x00b8
+#define PCI_DEVICE_ID_CIRRUS_5480	0x00bc
+#define PCI_DEVICE_ID_CIRRUS_5462	0x00d0
+#define PCI_DEVICE_ID_CIRRUS_5464	0x00d4
+#define PCI_DEVICE_ID_CIRRUS_5465	0x00d6
+#define PCI_DEVICE_ID_CIRRUS_6729	0x1100
+#define PCI_DEVICE_ID_CIRRUS_6832	0x1110
+#define PCI_DEVICE_ID_CIRRUS_7542	0x1200
+#define PCI_DEVICE_ID_CIRRUS_7543	0x1202
+#define PCI_DEVICE_ID_CIRRUS_7541	0x1204
+
+#define PCI_VENDOR_ID_IBM		0x1014
+#define PCI_DEVICE_ID_IBM_FIRE_CORAL	0x000a
+#define PCI_DEVICE_ID_IBM_TR		0x0018
+#define PCI_DEVICE_ID_IBM_82G2675	0x001d
+#define PCI_DEVICE_ID_IBM_MCA		0x0020
+#define PCI_DEVICE_ID_IBM_82351		0x0022
+#define PCI_DEVICE_ID_IBM_PYTHON	0x002d
+#define PCI_DEVICE_ID_IBM_SERVERAID	0x002e
+#define PCI_DEVICE_ID_IBM_TR_WAKE	0x003e
+#define PCI_DEVICE_ID_IBM_MPIC		0x0046
+#define PCI_DEVICE_ID_IBM_3780IDSP	0x007d
+#define PCI_DEVICE_ID_IBM_CHUKAR	0x0096
+#define PCI_DEVICE_ID_IBM_CPC700	0x00f9
+#define PCI_DEVICE_ID_IBM_CPC710_PCI64	0x00fc
+#define PCI_DEVICE_ID_IBM_CPC710_PCI32	0x0105
+#define PCI_DEVICE_ID_IBM_405GP		0x0156
+#define PCI_DEVICE_ID_IBM_SERVERAIDI960 0x01bd
+#define PCI_DEVICE_ID_IBM_MPIC_2	0xffff
+
+#define PCI_VENDOR_ID_COMPEX2		0x101a /* pci.ids says "AT&T GIS (NCR)" */
+#define PCI_DEVICE_ID_COMPEX2_100VG	0x0005
+
+#define PCI_VENDOR_ID_WD		0x101c
+#define PCI_DEVICE_ID_WD_7197		0x3296
+#define PCI_DEVICE_ID_WD_90C		0xc24a
+
+#define PCI_VENDOR_ID_AMI		0x101e
+#define PCI_DEVICE_ID_AMI_MEGARAID3	0x1960
+#define PCI_DEVICE_ID_AMI_MEGARAID	0x9010
+#define PCI_DEVICE_ID_AMI_MEGARAID2	0x9060
+
+#define PCI_VENDOR_ID_AMD		0x1022
+#define PCI_DEVICE_ID_AMD_LANCE		0x2000
+#define PCI_DEVICE_ID_AMD_LANCE_HOME	0x2001
+#define PCI_DEVICE_ID_AMD_SCSI		0x2020
+#define PCI_DEVICE_ID_AMD_SERENADE	0x36c0
+#define PCI_DEVICE_ID_AMD_FE_GATE_7006	0x7006
+#define PCI_DEVICE_ID_AMD_FE_GATE_7007	0x7007
+#define PCI_DEVICE_ID_AMD_FE_GATE_700C	0x700C
+#define PCI_DEVICE_ID_AMD_FE_GATE_700D	0x700D
+#define PCI_DEVICE_ID_AMD_FE_GATE_700E	0x700E
+#define PCI_DEVICE_ID_AMD_FE_GATE_700F	0x700F
+#define PCI_DEVICE_ID_AMD_COBRA_7400	0x7400
+#define PCI_DEVICE_ID_AMD_COBRA_7401	0x7401
+#define PCI_DEVICE_ID_AMD_COBRA_7403	0x7403
+#define PCI_DEVICE_ID_AMD_COBRA_7404	0x7404
+#define PCI_DEVICE_ID_AMD_VIPER_7408	0x7408
+#define PCI_DEVICE_ID_AMD_VIPER_7409	0x7409
+#define PCI_DEVICE_ID_AMD_VIPER_740B	0x740B
+#define PCI_DEVICE_ID_AMD_VIPER_740C	0x740C
+#define PCI_DEVICE_ID_AMD_VIPER_7410	0x7410
+#define PCI_DEVICE_ID_AMD_VIPER_7411	0x7411
+#define PCI_DEVICE_ID_AMD_VIPER_7413	0x7413
+#define PCI_DEVICE_ID_AMD_VIPER_7414	0x7414
+#define PCI_DEVICE_ID_AMD_OPUS_7440	0x7440
+#	define PCI_DEVICE_ID_AMD_VIPER_7440	PCI_DEVICE_ID_AMD_OPUS_7440
+#define PCI_DEVICE_ID_AMD_OPUS_7441	0x7441
+#	define PCI_DEVICE_ID_AMD_VIPER_7441	PCI_DEVICE_ID_AMD_OPUS_7441
+#define PCI_DEVICE_ID_AMD_OPUS_7443	0x7443
+#	define PCI_DEVICE_ID_AMD_VIPER_7443	PCI_DEVICE_ID_AMD_OPUS_7443
+#define PCI_DEVICE_ID_AMD_OPUS_7448	0x7448
+# define	PCI_DEVICE_ID_AMD_VIPER_7448	PCI_DEVICE_ID_AMD_OPUS_7448
+#define PCI_DEVICE_ID_AMD_OPUS_7449	0x7449
+#	define PCI_DEVICE_ID_AMD_VIPER_7449	PCI_DEVICE_ID_AMD_OPUS_7449
+#define PCI_DEVICE_ID_AMD_8111_LAN	0x7462
+#define PCI_DEVICE_ID_AMD_8111_IDE	0x7469
+#define PCI_DEVICE_ID_AMD_8111_AC97	0x746d
+#define PCI_DEVICE_ID_AMD_8131_APIC	0x7450
+
+#define PCI_VENDOR_ID_TRIDENT		0x1023
+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
+#define PCI_DEVICE_ID_TRIDENT_9320	0x9320
+#define PCI_DEVICE_ID_TRIDENT_9388	0x9388
+#define PCI_DEVICE_ID_TRIDENT_9397	0x9397
+#define PCI_DEVICE_ID_TRIDENT_939A	0x939A
+#define PCI_DEVICE_ID_TRIDENT_9520	0x9520
+#define PCI_DEVICE_ID_TRIDENT_9525	0x9525
+#define PCI_DEVICE_ID_TRIDENT_9420	0x9420
+#define PCI_DEVICE_ID_TRIDENT_9440	0x9440
+#define PCI_DEVICE_ID_TRIDENT_9660	0x9660
+#define PCI_DEVICE_ID_TRIDENT_9750	0x9750
+#define PCI_DEVICE_ID_TRIDENT_9850	0x9850
+#define PCI_DEVICE_ID_TRIDENT_9880	0x9880
+#define PCI_DEVICE_ID_TRIDENT_8400	0x8400
+#define PCI_DEVICE_ID_TRIDENT_8420	0x8420
+#define PCI_DEVICE_ID_TRIDENT_8500	0x8500
+
+#define PCI_VENDOR_ID_AI		0x1025
+#define PCI_DEVICE_ID_AI_M1435		0x1435
+
+#define PCI_VENDOR_ID_DELL		0x1028
+
+#define PCI_VENDOR_ID_MATROX		0x102B
+#define PCI_DEVICE_ID_MATROX_MGA_2	0x0518
+#define PCI_DEVICE_ID_MATROX_MIL	0x0519
+#define PCI_DEVICE_ID_MATROX_MYS	0x051A
+#define PCI_DEVICE_ID_MATROX_MIL_2	0x051b
+#define PCI_DEVICE_ID_MATROX_MIL_2_AGP	0x051f
+#define PCI_DEVICE_ID_MATROX_MGA_IMP	0x0d10
+#define PCI_DEVICE_ID_MATROX_G100_MM	0x1000
+#define PCI_DEVICE_ID_MATROX_G100_AGP	0x1001
+#define PCI_DEVICE_ID_MATROX_G200_PCI	0x0520
+#define PCI_DEVICE_ID_MATROX_G200_AGP	0x0521
+#define PCI_DEVICE_ID_MATROX_G400	0x0525
+#define PCI_DEVICE_ID_MATROX_G550	0x2527
+#define PCI_DEVICE_ID_MATROX_VIA	0x4536
+
+#define PCI_VENDOR_ID_CT		0x102c
+#define PCI_DEVICE_ID_CT_65545		0x00d8
+#define PCI_DEVICE_ID_CT_65548		0x00dc
+#define PCI_DEVICE_ID_CT_65550		0x00e0
+#define PCI_DEVICE_ID_CT_65554		0x00e4
+#define PCI_DEVICE_ID_CT_65555		0x00e5
+#define PCI_DEVICE_ID_CT_69000		0x00c0
+
+#define PCI_VENDOR_ID_MIRO		0x1031
+#define PCI_DEVICE_ID_MIRO_36050	0x5601
+
+#define PCI_VENDOR_ID_NEC		0x1033
+#define PCI_DEVICE_ID_NEC_NAPCCARD	0x003e
+#define PCI_DEVICE_ID_NEC_PCX2		0x0046
+#define PCI_DEVICE_ID_NEC_NILE4		0x005a
+#define PCI_DEVICE_ID_NEC_VRC5476	0x009b
+#define PCI_DEVICE_ID_NEC_VRC4173	0x00a5
+#define PCI_DEVICE_ID_NEC_VRC5477_AC97	0x00a6
+
+#define PCI_VENDOR_ID_FD		0x1036
+#define PCI_DEVICE_ID_FD_36C70		0x0000
+
+#define PCI_VENDOR_ID_SI		0x1039
+#define PCI_DEVICE_ID_SI_5591_AGP	0x0001
+#define PCI_DEVICE_ID_SI_6202		0x0002
+#define PCI_DEVICE_ID_SI_503		0x0008
+#define PCI_DEVICE_ID_SI_ACPI		0x0009
+#define PCI_DEVICE_ID_SI_180		0x0180
+#define PCI_DEVICE_ID_SI_5597_VGA	0x0200
+#define PCI_DEVICE_ID_SI_6205		0x0205
+#define PCI_DEVICE_ID_SI_501		0x0406
+#define PCI_DEVICE_ID_SI_496		0x0496
+#define PCI_DEVICE_ID_SI_300		0x0300
+#define PCI_DEVICE_ID_SI_315H		0x0310
+#define PCI_DEVICE_ID_SI_315		0x0315
+#define PCI_DEVICE_ID_SI_315PRO		0x0325
+#define PCI_DEVICE_ID_SI_530		0x0530
+#define PCI_DEVICE_ID_SI_540		0x0540
+#define PCI_DEVICE_ID_SI_550		0x0550
+#define PCI_DEVICE_ID_SI_540_VGA	0x5300
+#define PCI_DEVICE_ID_SI_550_VGA	0x5315
+#define PCI_DEVICE_ID_SI_601		0x0601
+#define PCI_DEVICE_ID_SI_620		0x0620
+#define PCI_DEVICE_ID_SI_630		0x0630
+#define PCI_DEVICE_ID_SI_633		0x0633
+#define PCI_DEVICE_ID_SI_635		0x0635
+#define PCI_DEVICE_ID_SI_640		0x0640
+#define PCI_DEVICE_ID_SI_645		0x0645
+#define PCI_DEVICE_ID_SI_646		0x0646
+#define PCI_DEVICE_ID_SI_648		0x0648
+#define PCI_DEVICE_ID_SI_650		0x0650
+#define PCI_DEVICE_ID_SI_651		0x0651
+#define PCI_DEVICE_ID_SI_652		0x0652
+#define PCI_DEVICE_ID_SI_655		0x0655
+#define PCI_DEVICE_ID_SI_730		0x0730
+#define PCI_DEVICE_ID_SI_733		0x0733
+#define PCI_DEVICE_ID_SI_630_VGA	0x6300
+#define PCI_DEVICE_ID_SI_730_VGA	0x7300
+#define PCI_DEVICE_ID_SI_735		0x0735
+#define PCI_DEVICE_ID_SI_740		0x0740
+#define PCI_DEVICE_ID_SI_745		0x0745
+#define PCI_DEVICE_ID_SI_746		0x0746
+#define PCI_DEVICE_ID_SI_748		0x0748
+#define PCI_DEVICE_ID_SI_750		0x0750
+#define PCI_DEVICE_ID_SI_751		0x0751
+#define PCI_DEVICE_ID_SI_752		0x0752
+#define PCI_DEVICE_ID_SI_755		0x0755
+#define PCI_DEVICE_ID_SI_900		0x0900
+#define PCI_DEVICE_ID_SI_5107		0x5107
+#define PCI_DEVICE_ID_SI_5300		0x5300
+#define PCI_DEVICE_ID_SI_5511		0x5511
+#define PCI_DEVICE_ID_SI_5513		0x5513
+#define PCI_DEVICE_ID_SI_5518		0x5518
+#define PCI_DEVICE_ID_SI_5571		0x5571
+#define PCI_DEVICE_ID_SI_5581		0x5581
+#define PCI_DEVICE_ID_SI_5582		0x5582
+#define PCI_DEVICE_ID_SI_5591		0x5591
+#define PCI_DEVICE_ID_SI_5596		0x5596
+#define PCI_DEVICE_ID_SI_5597		0x5597
+#define PCI_DEVICE_ID_SI_5598		0x5598
+#define PCI_DEVICE_ID_SI_5600		0x5600
+#define PCI_DEVICE_ID_SI_6300		0x6300
+#define PCI_DEVICE_ID_SI_6306		0x6306
+#define PCI_DEVICE_ID_SI_6326		0x6326
+#define PCI_DEVICE_ID_SI_7001		0x7001
+#define PCI_DEVICE_ID_SI_7016		0x7016
+
+#define PCI_VENDOR_ID_HP		0x103c
+#define PCI_DEVICE_ID_HP_DONNER_GFX	0x1008
+#define PCI_DEVICE_ID_HP_TACHYON	0x1028
+#define PCI_DEVICE_ID_HP_TACHLITE	0x1029
+#define PCI_DEVICE_ID_HP_J2585A		0x1030
+#define PCI_DEVICE_ID_HP_J2585B		0x1031
+#define PCI_DEVICE_ID_HP_SAS		0x1048
+#define PCI_DEVICE_ID_HP_DIVA1		0x1049
+#define PCI_DEVICE_ID_HP_DIVA2		0x104A
+#define PCI_DEVICE_ID_HP_SP2_0		0x104B
+#define PCI_DEVICE_ID_HP_PCI_LBA	0x1054
+#define PCI_DEVICE_ID_HP_REO_SBA	0x10f0
+#define PCI_DEVICE_ID_HP_REO_IOC	0x10f1
+#define PCI_DEVICE_ID_HP_ZX1_SBA	0x1229
+#define PCI_DEVICE_ID_HP_ZX1_IOC	0x122a
+#define PCI_DEVICE_ID_HP_PCIX_LBA	0x122e
+#define PCI_DEVICE_ID_HP_SX1000_IOC	0x127c
+
+#define PCI_VENDOR_ID_PCTECH		0x1042
+#define PCI_DEVICE_ID_PCTECH_RZ1000	0x1000
+#define PCI_DEVICE_ID_PCTECH_RZ1001	0x1001
+#define PCI_DEVICE_ID_PCTECH_SAMURAI_0	0x3000
+#define PCI_DEVICE_ID_PCTECH_SAMURAI_1	0x3010
+#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020
+
+#define PCI_VENDOR_ID_ASUSTEK		0x1043
+#define PCI_DEVICE_ID_ASUSTEK_0675	0x0675
+
+#define PCI_VENDOR_ID_DPT		0x1044
+#define PCI_DEVICE_ID_DPT		0xa400
+
+#define PCI_VENDOR_ID_OPTI		0x1045
+#define PCI_DEVICE_ID_OPTI_92C178	0xc178
+#define PCI_DEVICE_ID_OPTI_82C557	0xc557
+#define PCI_DEVICE_ID_OPTI_82C558	0xc558
+#define PCI_DEVICE_ID_OPTI_82C621	0xc621
+#define PCI_DEVICE_ID_OPTI_82C700	0xc700
+#define PCI_DEVICE_ID_OPTI_82C701	0xc701
+#define PCI_DEVICE_ID_OPTI_82C814	0xc814
+#define PCI_DEVICE_ID_OPTI_82C822	0xc822
+#define PCI_DEVICE_ID_OPTI_82C861	0xc861
+#define PCI_DEVICE_ID_OPTI_82C825	0xd568
+
+#define PCI_VENDOR_ID_ELSA		0x1048
+#define PCI_DEVICE_ID_ELSA_MICROLINK	0x1000
+#define PCI_DEVICE_ID_ELSA_QS3000	0x3000
+
+#define PCI_VENDOR_ID_SGS		0x104a
+#define PCI_DEVICE_ID_SGS_2000		0x0008
+#define PCI_DEVICE_ID_SGS_1764		0x0009
+
+#define PCI_VENDOR_ID_BUSLOGIC			0x104B
+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC	0x0140
+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER	0x1040
+#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT	0x8130
+
+#define PCI_VENDOR_ID_TI		0x104c
+#define PCI_DEVICE_ID_TI_TVP4010	0x3d04
+#define PCI_DEVICE_ID_TI_TVP4020	0x3d07
+#define PCI_DEVICE_ID_TI_1130		0xac12
+#define PCI_DEVICE_ID_TI_1031		0xac13
+#define PCI_DEVICE_ID_TI_1131		0xac15
+#define PCI_DEVICE_ID_TI_1250		0xac16
+#define PCI_DEVICE_ID_TI_1220		0xac17
+#define PCI_DEVICE_ID_TI_1221		0xac19
+#define PCI_DEVICE_ID_TI_1210		0xac1a
+#define PCI_DEVICE_ID_TI_1410		0xac50
+#define PCI_DEVICE_ID_TI_1450		0xac1b
+#define PCI_DEVICE_ID_TI_1225		0xac1c
+#define PCI_DEVICE_ID_TI_1251A		0xac1d
+#define PCI_DEVICE_ID_TI_1211		0xac1e
+#define PCI_DEVICE_ID_TI_1251B		0xac1f
+#define PCI_DEVICE_ID_TI_4410		0xac41
+#define PCI_DEVICE_ID_TI_4451		0xac42
+#define PCI_DEVICE_ID_TI_1420		0xac51
+#define PCI_DEVICE_ID_TI_1520		0xac55
+#define PCI_DEVICE_ID_TI_1510		0xac56
+
+#define PCI_VENDOR_ID_SONY		0x104d
+#define PCI_DEVICE_ID_SONY_CXD3222	0x8039
+
+#define PCI_VENDOR_ID_OAK		0x104e
+#define PCI_DEVICE_ID_OAK_OTI107	0x0107
+
+/* Winbond have two vendor IDs! See 0x10ad as well */
+#define PCI_VENDOR_ID_WINBOND2		0x1050
+#define PCI_DEVICE_ID_WINBOND2_89C940	0x0940
+#define PCI_DEVICE_ID_WINBOND2_89C940F	0x5a5a
+#define PCI_DEVICE_ID_WINBOND2_6692	0x6692
+
+#define PCI_VENDOR_ID_ANIGMA		0x1051
+#define PCI_DEVICE_ID_ANIGMA_MC145575	0x0100
+
+#define PCI_VENDOR_ID_EFAR		0x1055
+#define PCI_DEVICE_ID_EFAR_SLC90E66_1	0x9130
+#define PCI_DEVICE_ID_EFAR_SLC90E66_0	0x9460
+#define PCI_DEVICE_ID_EFAR_SLC90E66_2	0x9462
+#define PCI_DEVICE_ID_EFAR_SLC90E66_3	0x9463
+
+#define PCI_VENDOR_ID_MOTOROLA		0x1057
+#define PCI_VENDOR_ID_MOTOROLA_OOPS	0x1507
+#define PCI_DEVICE_ID_MOTOROLA_MPC105	0x0001
+#define PCI_DEVICE_ID_MOTOROLA_MPC106	0x0002
+#define PCI_DEVICE_ID_MOTOROLA_MPC107	0x0004
+#define PCI_DEVICE_ID_MOTOROLA_MPC8540	0x0008
+#define PCI_DEVICE_ID_MOTOROLA_MPC8560	0x0009
+#define PCI_DEVICE_ID_MOTOROLA_MPC8265A 0x18c0
+#define PCI_DEVICE_ID_MOTOROLA_RAVEN	0x4801
+#define PCI_DEVICE_ID_MOTOROLA_FALCON	0x4802
+#define PCI_DEVICE_ID_MOTOROLA_HAWK	0x4803
+#define PCI_DEVICE_ID_MOTOROLA_CPX8216	0x4806
+#define PCI_DEVICE_ID_MOTOROLA_MPC190	0x6400
+
+#define PCI_VENDOR_ID_PROMISE		0x105a
+#define PCI_DEVICE_ID_PROMISE_20265	0x0d30
+#define PCI_DEVICE_ID_PROMISE_20267	0x4d30
+#define PCI_DEVICE_ID_PROMISE_20246	0x4d33
+#define PCI_DEVICE_ID_PROMISE_20262	0x4d38
+#define PCI_DEVICE_ID_PROMISE_20263	0x0D38
+#define PCI_DEVICE_ID_PROMISE_20268	0x4d68
+#define PCI_DEVICE_ID_PROMISE_20270	0x6268
+#define PCI_DEVICE_ID_PROMISE_20269	0x4d69
+#define PCI_DEVICE_ID_PROMISE_20271	0x6269
+#define PCI_DEVICE_ID_PROMISE_20275	0x1275
+#define PCI_DEVICE_ID_PROMISE_20276	0x5275
+#define PCI_DEVICE_ID_PROMISE_20277	0x7275
+#define PCI_DEVICE_ID_PROMISE_5300	0x5300
+
+#define PCI_VENDOR_ID_N9		0x105d
+#define PCI_DEVICE_ID_N9_I128		0x2309
+#define PCI_DEVICE_ID_N9_I128_2		0x2339
+#define PCI_DEVICE_ID_N9_I128_T2R	0x493d
+
+#define PCI_VENDOR_ID_UMC		0x1060
+#define PCI_DEVICE_ID_UMC_UM8673F	0x0101
+#define PCI_DEVICE_ID_UMC_UM8891A	0x0891
+#define PCI_DEVICE_ID_UMC_UM8886BF	0x673a
+#define PCI_DEVICE_ID_UMC_UM8886A	0x886a
+#define PCI_DEVICE_ID_UMC_UM8881F	0x8881
+#define PCI_DEVICE_ID_UMC_UM8886F	0x8886
+#define PCI_DEVICE_ID_UMC_UM9017F	0x9017
+#define PCI_DEVICE_ID_UMC_UM8886N	0xe886
+#define PCI_DEVICE_ID_UMC_UM8891N	0xe891
+
+#define PCI_VENDOR_ID_X			0x1061
+#define PCI_DEVICE_ID_X_AGX016		0x0001
+
+#define PCI_VENDOR_ID_MYLEX		0x1069
+#define PCI_DEVICE_ID_MYLEX_DAC960_P	0x0001
+#define PCI_DEVICE_ID_MYLEX_DAC960_PD	0x0002
+#define PCI_DEVICE_ID_MYLEX_DAC960_PG	0x0010
+#define PCI_DEVICE_ID_MYLEX_DAC960_LA	0x0020
+#define PCI_DEVICE_ID_MYLEX_DAC960_LP	0x0050
+#define PCI_DEVICE_ID_MYLEX_DAC960_BA	0xBA56
+
+#define PCI_VENDOR_ID_PICOP		0x1066
+#define PCI_DEVICE_ID_PICOP_PT86C52X	0x0001
+#define PCI_DEVICE_ID_PICOP_PT80C524	0x8002
+
+#define PCI_VENDOR_ID_APPLE		0x106b
+#define PCI_DEVICE_ID_APPLE_BANDIT	0x0001
+#define PCI_DEVICE_ID_APPLE_GC		0x0002
+#define PCI_DEVICE_ID_APPLE_HYDRA	0x000e
+#define PCI_DEVICE_ID_APPLE_UNI_N_FW	0x0018
+#define PCI_DEVICE_ID_APPLE_KL_USB	0x0019
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP	0x0020
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC	0x0021
+#define PCI_DEVICE_ID_APPLE_KEYLARGO	0x0022
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP 0x0024
+#define PCI_DEVICE_ID_APPLE_KEYLARGO_P	0x0025
+#define PCI_DEVICE_ID_APPLE_KL_USB_P	0x0026
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P 0x0027
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15 0x002d
+#define PCI_DEVICE_ID_APPLE_UNI_N_FW2	0x0030
+#define PCI_DEVICE_ID_APPLE_TIGON3	0x1645
+
+#define PCI_VENDOR_ID_YAMAHA		0x1073
+#define PCI_DEVICE_ID_YAMAHA_724	0x0004
+#define PCI_DEVICE_ID_YAMAHA_724F	0x000d
+#define PCI_DEVICE_ID_YAMAHA_740	0x000a
+#define PCI_DEVICE_ID_YAMAHA_740C	0x000c
+#define PCI_DEVICE_ID_YAMAHA_744	0x0010
+#define PCI_DEVICE_ID_YAMAHA_754	0x0012
+
+#define PCI_VENDOR_ID_NEXGEN		0x1074
+#define PCI_DEVICE_ID_NEXGEN_82C501	0x4e78
+
+#define PCI_VENDOR_ID_QLOGIC		0x1077
+#define PCI_DEVICE_ID_QLOGIC_ISP1020	0x1020
+#define PCI_DEVICE_ID_QLOGIC_ISP1022	0x1022
+#define PCI_DEVICE_ID_QLOGIC_ISP2100	0x2100
+#define PCI_DEVICE_ID_QLOGIC_ISP2200	0x2200
+
+#define PCI_VENDOR_ID_CYRIX		0x1078
+#define PCI_DEVICE_ID_CYRIX_5510	0x0000
+#define PCI_DEVICE_ID_CYRIX_PCI_MASTER	0x0001
+#define PCI_DEVICE_ID_CYRIX_5520	0x0002
+#define PCI_DEVICE_ID_CYRIX_5530_LEGACY 0x0100
+#define PCI_DEVICE_ID_CYRIX_5530_SMI	0x0101
+#define PCI_DEVICE_ID_CYRIX_5530_IDE	0x0102
+#define PCI_DEVICE_ID_CYRIX_5530_AUDIO	0x0103
+#define PCI_DEVICE_ID_CYRIX_5530_VIDEO	0x0104
+
+#define PCI_VENDOR_ID_LEADTEK		0x107d
+#define PCI_DEVICE_ID_LEADTEK_805	0x0000
+
+#define PCI_VENDOR_ID_INTERPHASE	0x107e
+#define PCI_DEVICE_ID_INTERPHASE_5526	0x0004
+#define PCI_DEVICE_ID_INTERPHASE_55x6	0x0005
+#define PCI_DEVICE_ID_INTERPHASE_5575	0x0008
+
+#define PCI_VENDOR_ID_CONTAQ		0x1080
+#define PCI_DEVICE_ID_CONTAQ_82C599	0x0600
+#define PCI_DEVICE_ID_CONTAQ_82C693	0xc693
+
+#define PCI_VENDOR_ID_FOREX		0x1083
+
+#define PCI_VENDOR_ID_OLICOM		0x108d
+#define PCI_DEVICE_ID_OLICOM_OC3136	0x0001
+#define PCI_DEVICE_ID_OLICOM_OC2315	0x0011
+#define PCI_DEVICE_ID_OLICOM_OC2325	0x0012
+#define PCI_DEVICE_ID_OLICOM_OC2183	0x0013
+#define PCI_DEVICE_ID_OLICOM_OC2326	0x0014
+#define PCI_DEVICE_ID_OLICOM_OC6151	0x0021
+
+#define PCI_VENDOR_ID_SUN		0x108e
+#define PCI_DEVICE_ID_SUN_EBUS		0x1000
+#define PCI_DEVICE_ID_SUN_HAPPYMEAL	0x1001
+#define PCI_DEVICE_ID_SUN_RIO_EBUS	0x1100
+#define PCI_DEVICE_ID_SUN_RIO_GEM	0x1101
+#define PCI_DEVICE_ID_SUN_RIO_1394	0x1102
+#define PCI_DEVICE_ID_SUN_RIO_USB	0x1103
+#define PCI_DEVICE_ID_SUN_GEM		0x2bad
+#define PCI_DEVICE_ID_SUN_SIMBA		0x5000
+#define PCI_DEVICE_ID_SUN_PBM		0x8000
+#define PCI_DEVICE_ID_SUN_SCHIZO	0x8001
+#define PCI_DEVICE_ID_SUN_SABRE		0xa000
+#define PCI_DEVICE_ID_SUN_HUMMINGBIRD	0xa001
+#define PCI_DEVICE_ID_SUN_TOMATILLO	0xa801
+
+#define PCI_VENDOR_ID_CMD		0x1095
+#define PCI_DEVICE_ID_SII_1210SA	0x0240
+
+#define PCI_DEVICE_ID_CMD_640		0x0640
+#define PCI_DEVICE_ID_CMD_643		0x0643
+#define PCI_DEVICE_ID_CMD_646		0x0646
+#define PCI_DEVICE_ID_CMD_647		0x0647
+#define PCI_DEVICE_ID_CMD_648		0x0648
+#define PCI_DEVICE_ID_CMD_649		0x0649
+#define PCI_DEVICE_ID_CMD_670		0x0670
+
+#define PCI_DEVICE_ID_SII_680		0x0680
+#define PCI_DEVICE_ID_SII_3112		0x3112
+
+#define PCI_VENDOR_ID_VISION		0x1098
+#define PCI_DEVICE_ID_VISION_QD8500	0x0001
+#define PCI_DEVICE_ID_VISION_QD8580	0x0002
+
+#define PCI_VENDOR_ID_BROOKTREE		0x109e
+#define PCI_DEVICE_ID_BROOKTREE_848	0x0350
+#define PCI_DEVICE_ID_BROOKTREE_849A	0x0351
+#define PCI_DEVICE_ID_BROOKTREE_878_1	0x036e
+#define PCI_DEVICE_ID_BROOKTREE_878	0x0878
+#define PCI_DEVICE_ID_BROOKTREE_8474	0x8474
+
+#define PCI_VENDOR_ID_SIERRA		0x10a8
+#define PCI_DEVICE_ID_SIERRA_STB	0x0000
+
+#define PCI_VENDOR_ID_SGI		0x10a9
+#define PCI_DEVICE_ID_SGI_IOC3		0x0003
+#define PCI_DEVICE_ID_SGI_IOC4		0x100a
+
+#define PCI_VENDOR_ID_ACC		0x10aa
+#define PCI_DEVICE_ID_ACC_2056		0x0000
+
+#define PCI_VENDOR_ID_WINBOND		0x10ad
+#define PCI_DEVICE_ID_WINBOND_83769	0x0001
+#define PCI_DEVICE_ID_WINBOND_82C105	0x0105
+#define PCI_DEVICE_ID_WINBOND_83C553	0x0565
+
+#define PCI_VENDOR_ID_DATABOOK		0x10b3
+#define PCI_DEVICE_ID_DATABOOK_87144	0xb106
+
+#define PCI_VENDOR_ID_PLX		0x10b5
+#define PCI_DEVICE_ID_PLX_R685		0x1030
+#define PCI_DEVICE_ID_PLX_ROMULUS	0x106a
+#define PCI_DEVICE_ID_PLX_SPCOM800	0x1076
+#define PCI_DEVICE_ID_PLX_1077		0x1077
+#define PCI_DEVICE_ID_PLX_SPCOM200	0x1103
+#define PCI_DEVICE_ID_PLX_DJINN_ITOO	0x1151
+#define PCI_DEVICE_ID_PLX_R753		0x1152
+#define PCI_DEVICE_ID_PLX_9050		0x9050
+#define PCI_DEVICE_ID_PLX_9060		0x9060
+#define PCI_DEVICE_ID_PLX_9060ES	0x906E
+#define PCI_DEVICE_ID_PLX_9060SD	0x906D
+#define PCI_DEVICE_ID_PLX_9080		0x9080
+#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2	0xa001
+
+#define PCI_VENDOR_ID_MADGE		0x10b6
+#define PCI_DEVICE_ID_MADGE_MK2		0x0002
+#define PCI_DEVICE_ID_MADGE_C155S	0x1001
+
+#define PCI_VENDOR_ID_3COM		0x10b7
+#define PCI_DEVICE_ID_3COM_3C985	0x0001
+#define PCI_DEVICE_ID_3COM_3C339	0x3390
+#define PCI_DEVICE_ID_3COM_3C590	0x5900
+#define PCI_DEVICE_ID_3COM_3C595TX	0x5950
+#define PCI_DEVICE_ID_3COM_3C595T4	0x5951
+#define PCI_DEVICE_ID_3COM_3C595MII	0x5952
+#define PCI_DEVICE_ID_3COM_3C900TPO	0x9000
+#define PCI_DEVICE_ID_3COM_3C900COMBO	0x9001
+#define PCI_DEVICE_ID_3COM_3C905TX	0x9050
+#define PCI_DEVICE_ID_3COM_3C905T4	0x9051
+#define PCI_DEVICE_ID_3COM_3C905B_TX	0x9055
+#define PCI_DEVICE_ID_3COM_3CR990	0x9900
+#define PCI_DEVICE_ID_3COM_3CR990_TX_95 0x9902
+#define PCI_DEVICE_ID_3COM_3CR990_TX_97 0x9903
+#define PCI_DEVICE_ID_3COM_3CR990B	0x9904
+#define PCI_DEVICE_ID_3COM_3CR990_FX	0x9905
+#define PCI_DEVICE_ID_3COM_3CR990SVR95	0x9908
+#define PCI_DEVICE_ID_3COM_3CR990SVR97	0x9909
+#define PCI_DEVICE_ID_3COM_3CR990SVR	0x990a
+
+#define PCI_VENDOR_ID_SMC		0x10b8
+#define PCI_DEVICE_ID_SMC_EPIC100	0x0005
+
+#define PCI_VENDOR_ID_AL		0x10b9
+#define PCI_DEVICE_ID_AL_M1445		0x1445
+#define PCI_DEVICE_ID_AL_M1449		0x1449
+#define PCI_DEVICE_ID_AL_M1451		0x1451
+#define PCI_DEVICE_ID_AL_M1461		0x1461
+#define PCI_DEVICE_ID_AL_M1489		0x1489
+#define PCI_DEVICE_ID_AL_M1511		0x1511
+#define PCI_DEVICE_ID_AL_M1513		0x1513
+#define PCI_DEVICE_ID_AL_M1521		0x1521
+#define PCI_DEVICE_ID_AL_M1523		0x1523
+#define PCI_DEVICE_ID_AL_M1531		0x1531
+#define PCI_DEVICE_ID_AL_M1533		0x1533
+#define PCI_DEVICE_ID_AL_M1535		0x1535
+#define PCI_DEVICE_ID_AL_M1541		0x1541
+#define PCI_DEVICE_ID_AL_M1621		0x1621
+#define PCI_DEVICE_ID_AL_M1631		0x1631
+#define PCI_DEVICE_ID_AL_M1641		0x1641
+#define PCI_DEVICE_ID_AL_M1644		0x1644
+#define PCI_DEVICE_ID_AL_M1647		0x1647
+#define PCI_DEVICE_ID_AL_M1651		0x1651
+#define PCI_DEVICE_ID_AL_M1543		0x1543
+#define PCI_DEVICE_ID_AL_M3307		0x3307
+#define PCI_DEVICE_ID_AL_M4803		0x5215
+#define PCI_DEVICE_ID_AL_M5219		0x5219
+#define PCI_DEVICE_ID_AL_M5229		0x5229
+#define PCI_DEVICE_ID_AL_M5237		0x5237
+#define PCI_DEVICE_ID_AL_M5243		0x5243
+#define PCI_DEVICE_ID_AL_M5451		0x5451
+#define PCI_DEVICE_ID_AL_M7101		0x7101
+
+#define PCI_VENDOR_ID_MITSUBISHI	0x10ba
+
+#define PCI_VENDOR_ID_SURECOM		0x10bd
+#define PCI_DEVICE_ID_SURECOM_NE34	0x0e34
+
+#define PCI_VENDOR_ID_NEOMAGIC		0x10c8
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070	0x0001
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V		0x0002
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV		0x0003
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160	0x0004
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV		0x0005
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS	0x0083
+
+#define PCI_VENDOR_ID_ASP		0x10cd
+#define PCI_DEVICE_ID_ASP_ABP940	0x1200
+#define PCI_DEVICE_ID_ASP_ABP940U	0x1300
+#define PCI_DEVICE_ID_ASP_ABP940UW	0x2300
+
+#define PCI_VENDOR_ID_MACRONIX		0x10d9
+#define PCI_DEVICE_ID_MACRONIX_MX98713	0x0512
+#define PCI_DEVICE_ID_MACRONIX_MX987x5	0x0531
+
+#define PCI_VENDOR_ID_TCONRAD		0x10da
+#define PCI_DEVICE_ID_TCONRAD_TOKENRING 0x0508
+
+#define PCI_VENDOR_ID_CERN		0x10dc
+#define PCI_DEVICE_ID_CERN_SPSB_PMC	0x0001
+#define PCI_DEVICE_ID_CERN_SPSB_PCI	0x0002
+#define PCI_DEVICE_ID_CERN_HIPPI_DST	0x0021
+#define PCI_DEVICE_ID_CERN_HIPPI_SRC	0x0022
+
+#define PCI_VENDOR_ID_NVIDIA			0x10de
+#define PCI_DEVICE_ID_NVIDIA_TNT		0x0020
+#define PCI_DEVICE_ID_NVIDIA_TNT2		0x0028
+#define PCI_DEVICE_ID_NVIDIA_UTNT2		0x0029
+#define PCI_DEVICE_ID_NVIDIA_VTNT2		0x002C
+#define PCI_DEVICE_ID_NVIDIA_UVTNT2		0x002D
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE	0x0065
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE	0x0085
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA	0x008e
+#define PCI_DEVICE_ID_NVIDIA_ITNT2		0x00A0
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3		0x00d1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE	0x00d5
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S		0x00e1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA	0x00e3
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE	0x00e5
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2	0x00ee
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR	0x0100
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR	0x0101
+#define PCI_DEVICE_ID_NVIDIA_QUADRO		0x0103
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX	0x0110
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2	0x0111
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO	0x0112
+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR	0x0113
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS	0x0150
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2	0x0151
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA	0x0152
+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO	0x0153
+#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2		0x01a0
+#define PCI_DEVICE_ID_NVIDIA_NFORCE		0x01a4
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE		0x01bc
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2		0x01e0
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3		0x0200
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1		0x0201
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2		0x0202
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC		0x0203
+
+#define PCI_VENDOR_ID_IMS		0x10e0
+#define PCI_DEVICE_ID_IMS_8849		0x8849
+#define PCI_DEVICE_ID_IMS_TT128		0x9128
+#define PCI_DEVICE_ID_IMS_TT3D		0x9135
+
+#define PCI_VENDOR_ID_TEKRAM2		0x10e1
+#define PCI_DEVICE_ID_TEKRAM2_690c	0x690c
+
+#define PCI_VENDOR_ID_TUNDRA		0x10e3
+#define PCI_DEVICE_ID_TUNDRA_CA91C042	0x0000
+
+#define PCI_VENDOR_ID_AMCC		0x10e8
+#define PCI_DEVICE_ID_AMCC_MYRINET	0x8043
+#define PCI_DEVICE_ID_AMCC_PARASTATION	0x8062
+#define PCI_DEVICE_ID_AMCC_S5933	0x807d
+#define PCI_DEVICE_ID_AMCC_S5933_HEPC3	0x809c
+
+#define PCI_VENDOR_ID_INTERG		0x10ea
+#define PCI_DEVICE_ID_INTERG_1680	0x1680
+#define PCI_DEVICE_ID_INTERG_1682	0x1682
+#define PCI_DEVICE_ID_INTERG_2000	0x2000
+#define PCI_DEVICE_ID_INTERG_2010	0x2010
+#define PCI_DEVICE_ID_INTERG_5000	0x5000
+#define PCI_DEVICE_ID_INTERG_5050	0x5050
+
+#define PCI_VENDOR_ID_REALTEK		0x10ec
+#define PCI_DEVICE_ID_REALTEK_8029	0x8029
+#define PCI_DEVICE_ID_REALTEK_8129	0x8129
+#define PCI_DEVICE_ID_REALTEK_8139	0x8139
+#define PCI_DEVICE_ID_REALTEK_8169	0x8169
+
+#define PCI_VENDOR_ID_XILINX		0x10ee
+#define PCI_DEVICE_ID_TURBOPAM		0x4020
+
+#define PCI_VENDOR_ID_TRUEVISION	0x10fa
+#define PCI_DEVICE_ID_TRUEVISION_T1000	0x000c
+
+#define PCI_VENDOR_ID_INIT		0x1101
+#define PCI_DEVICE_ID_INIT_320P		0x9100
+#define PCI_DEVICE_ID_INIT_360P		0x9500
+
+#define PCI_VENDOR_ID_CREATIVE		0x1102 /* duplicate: ECTIVA */
+#define PCI_DEVICE_ID_CREATIVE_EMU10K1	0x0002
+
+#define PCI_VENDOR_ID_ECTIVA		0x1102 /* duplicate: CREATIVE */
+#define PCI_DEVICE_ID_ECTIVA_EV1938	0x8938
+
+#define PCI_VENDOR_ID_TTI		0x1103
+#define PCI_DEVICE_ID_TTI_HPT343	0x0003
+#define PCI_DEVICE_ID_TTI_HPT366	0x0004
+#define PCI_DEVICE_ID_TTI_HPT372	0x0005
+#define PCI_DEVICE_ID_TTI_HPT302	0x0006
+#define PCI_DEVICE_ID_TTI_HPT371	0x0007
+#define PCI_DEVICE_ID_TTI_HPT374	0x0008
+#define PCI_DEVICE_ID_TTI_HPT372N	0x0009	/* appoarently a 372N variant? */
+
+#define PCI_VENDOR_ID_VIA		0x1106
+#define PCI_DEVICE_ID_VIA_8363_0	0x0305
+#define PCI_DEVICE_ID_VIA_8371_0	0x0391
+#define PCI_DEVICE_ID_VIA_8501_0	0x0501
+#define PCI_DEVICE_ID_VIA_82C505	0x0505
+#define PCI_DEVICE_ID_VIA_82C561	0x0561
+#define PCI_DEVICE_ID_VIA_82C586_1	0x0571
+#define PCI_DEVICE_ID_VIA_82C576	0x0576
+#define PCI_DEVICE_ID_VIA_82C585	0x0585
+#define PCI_DEVICE_ID_VIA_82C586_0	0x0586
+#define PCI_DEVICE_ID_VIA_82C595	0x0595
+#define PCI_DEVICE_ID_VIA_82C596	0x0596
+#define PCI_DEVICE_ID_VIA_82C597_0	0x0597
+#define PCI_DEVICE_ID_VIA_82C598_0	0x0598
+#define PCI_DEVICE_ID_VIA_8601_0	0x0601
+#define PCI_DEVICE_ID_VIA_8605_0	0x0605
+#define PCI_DEVICE_ID_VIA_82C680	0x0680
+#define PCI_DEVICE_ID_VIA_82C686	0x0686
+#define PCI_DEVICE_ID_VIA_82C691	0x0691
+#define PCI_DEVICE_ID_VIA_82C693	0x0693
+#define PCI_DEVICE_ID_VIA_82C693_1	0x0698
+#define PCI_DEVICE_ID_VIA_82C926	0x0926
+#define PCI_DEVICE_ID_VIA_82C576_1	0x1571
+#define PCI_DEVICE_ID_VIA_82C595_97	0x1595
+#define PCI_DEVICE_ID_VIA_82C586_2	0x3038
+#define PCI_DEVICE_ID_VIA_82C586_3	0x3040
+#define PCI_DEVICE_ID_VIA_6305		0x3044
+#define PCI_DEVICE_ID_VIA_82C596_3	0x3050
+#define PCI_DEVICE_ID_VIA_82C596B_3	0x3051
+#define PCI_DEVICE_ID_VIA_82C686_4	0x3057
+#define PCI_DEVICE_ID_VIA_82C686_5	0x3058
+#define PCI_DEVICE_ID_VIA_8233_5	0x3059
+#define PCI_DEVICE_ID_VIA_8233_7	0x3065
+#define PCI_DEVICE_ID_VIA_82C686_6	0x3068
+#define PCI_DEVICE_ID_VIA_8233_0	0x3074
+#define PCI_DEVICE_ID_VIA_8633_0	0x3091
+#define PCI_DEVICE_ID_VIA_8367_0	0x3099
+#define PCI_DEVICE_ID_VIA_8622		0x3102
+#define PCI_DEVICE_ID_VIA_8233C_0	0x3109
+#define PCI_DEVICE_ID_VIA_8361		0x3112
+#define PCI_DEVICE_ID_VIA_8375		0x3116
+#define PCI_DEVICE_ID_VIA_CLE266	0x3123
+#define PCI_DEVICE_ID_VIA_8233A		0x3147
+#define PCI_DEVICE_ID_VIA_P4M266	0x3148
+#define PCI_DEVICE_ID_VIA_8237_SATA	0x3149
+#define PCI_DEVICE_ID_VIA_P4X333	0x3168
+#define PCI_DEVICE_ID_VIA_8235		0x3177
+#define PCI_DEVICE_ID_VIA_8377_0	0x3189
+#define PCI_DEVICE_ID_VIA_K8T400M_0	0x3188
+#define PCI_DEVICE_ID_VIA_8237		0x3227
+#define PCI_DEVICE_ID_VIA_86C100A	0x6100
+#define PCI_DEVICE_ID_VIA_8231		0x8231
+#define PCI_DEVICE_ID_VIA_8231_4	0x8235
+#define PCI_DEVICE_ID_VIA_8365_1	0x8305
+#define PCI_DEVICE_ID_VIA_8371_1	0x8391
+#define PCI_DEVICE_ID_VIA_8501_1	0x8501
+#define PCI_DEVICE_ID_VIA_82C597_1	0x8597
+#define PCI_DEVICE_ID_VIA_82C598_1	0x8598
+#define PCI_DEVICE_ID_VIA_8601_1	0x8601
+#define PCI_DEVICE_ID_VIA_8505_1	0x8605
+#define PCI_DEVICE_ID_VIA_8633_1	0xB091
+#define PCI_DEVICE_ID_VIA_8367_1	0xB099
+
+#define PCI_VENDOR_ID_SIEMENS		0x110A
+#define PCI_DEVICE_ID_SIEMENS_DSCC4	0x2102
+
+#define PCI_VENDOR_ID_SMC2		0x1113
+#define PCI_DEVICE_ID_SMC2_1211TX	0x1211
+
+#define PCI_VENDOR_ID_VORTEX		0x1119
+#define PCI_DEVICE_ID_VORTEX_GDT60x0	0x0000
+#define PCI_DEVICE_ID_VORTEX_GDT6000B	0x0001
+#define PCI_DEVICE_ID_VORTEX_GDT6x10	0x0002
+#define PCI_DEVICE_ID_VORTEX_GDT6x20	0x0003
+#define PCI_DEVICE_ID_VORTEX_GDT6530	0x0004
+#define PCI_DEVICE_ID_VORTEX_GDT6550	0x0005
+#define PCI_DEVICE_ID_VORTEX_GDT6x17	0x0006
+#define PCI_DEVICE_ID_VORTEX_GDT6x27	0x0007
+#define PCI_DEVICE_ID_VORTEX_GDT6537	0x0008
+#define PCI_DEVICE_ID_VORTEX_GDT6557	0x0009
+#define PCI_DEVICE_ID_VORTEX_GDT6x15	0x000a
+#define PCI_DEVICE_ID_VORTEX_GDT6x25	0x000b
+#define PCI_DEVICE_ID_VORTEX_GDT6535	0x000c
+#define PCI_DEVICE_ID_VORTEX_GDT6555	0x000d
+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP	0x0100
+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP	0x0101
+#define PCI_DEVICE_ID_VORTEX_GDT6537RP	0x0102
+#define PCI_DEVICE_ID_VORTEX_GDT6557RP	0x0103
+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP	0x0104
+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP	0x0105
+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1 0x0110
+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1 0x0111
+#define PCI_DEVICE_ID_VORTEX_GDT6537RP1 0x0112
+#define PCI_DEVICE_ID_VORTEX_GDT6557RP1 0x0113
+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1 0x0114
+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1 0x0115
+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2 0x0120
+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2 0x0121
+#define PCI_DEVICE_ID_VORTEX_GDT6537RP2 0x0122
+#define PCI_DEVICE_ID_VORTEX_GDT6557RP2 0x0123
+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2 0x0124
+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2 0x0125
+
+#define PCI_VENDOR_ID_EF		0x111a
+#define PCI_DEVICE_ID_EF_ATM_FPGA	0x0000
+#define PCI_DEVICE_ID_EF_ATM_ASIC	0x0002
+
+#define PCI_VENDOR_ID_IDT		0x111d
+#define PCI_DEVICE_ID_IDT_IDT77201	0x0001
+
+#define PCI_VENDOR_ID_FORE		0x1127
+#define PCI_DEVICE_ID_FORE_PCA200PC	0x0210
+#define PCI_DEVICE_ID_FORE_PCA200E	0x0300
+
+#define PCI_VENDOR_ID_IMAGINGTECH	0x112f
+#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI 0x0000
+
+#define PCI_VENDOR_ID_PHILIPS		0x1131
+#define PCI_DEVICE_ID_PHILIPS_SAA7145	0x7145
+#define PCI_DEVICE_ID_PHILIPS_SAA7146	0x7146
+#define PCI_DEVICE_ID_PHILIPS_SAA9730	0x9730
+
+#define PCI_VENDOR_ID_EICON		0x1133
+#define PCI_DEVICE_ID_EICON_DIVA20PRO	0xe001
+#define PCI_DEVICE_ID_EICON_DIVA20	0xe002
+#define PCI_DEVICE_ID_EICON_DIVA20PRO_U 0xe003
+#define PCI_DEVICE_ID_EICON_DIVA20_U	0xe004
+#define PCI_DEVICE_ID_EICON_DIVA201	0xe005
+#define PCI_DEVICE_ID_EICON_DIVA202	0xe00b
+#define PCI_DEVICE_ID_EICON_MAESTRA	0xe010
+#define PCI_DEVICE_ID_EICON_MAESTRAQ	0xe012
+#define PCI_DEVICE_ID_EICON_MAESTRAQ_U	0xe013
+#define PCI_DEVICE_ID_EICON_MAESTRAP	0xe014
+
+#define PCI_VENDOR_ID_CYCLONE		0x113c
+#define PCI_DEVICE_ID_CYCLONE_SDK	0x0001
+
+#define PCI_VENDOR_ID_ALLIANCE		0x1142
+#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO 0x3210
+#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO 0x6422
+#define PCI_DEVICE_ID_ALLIANCE_AT24	0x6424
+#define PCI_DEVICE_ID_ALLIANCE_AT3D	0x643d
+
+#define PCI_VENDOR_ID_SYSKONNECT	0x1148
+#define PCI_DEVICE_ID_SYSKONNECT_FP	0x4000
+#define PCI_DEVICE_ID_SYSKONNECT_TR	0x4200
+#define PCI_DEVICE_ID_SYSKONNECT_GE	0x4300
+#define PCI_DEVICE_ID_SYSKONNECT_YU	0x4320
+#define PCI_DEVICE_ID_SYSKONNECT_9DXX	0x4400
+#define PCI_DEVICE_ID_SYSKONNECT_9MXX	0x4500
+
+#define PCI_VENDOR_ID_VMIC		0x114a
+#define PCI_DEVICE_ID_VMIC_VME		0x7587
+
+#define PCI_VENDOR_ID_DIGI		0x114f
+#define PCI_DEVICE_ID_DIGI_EPC		0x0002
+#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH	0x0003
+#define PCI_DEVICE_ID_DIGI_XEM		0x0004
+#define PCI_DEVICE_ID_DIGI_XR		0x0005
+#define PCI_DEVICE_ID_DIGI_CX		0x0006
+#define PCI_DEVICE_ID_DIGI_XRJ		0x0009
+#define PCI_DEVICE_ID_DIGI_EPCJ		0x000a
+#define PCI_DEVICE_ID_DIGI_XR_920	0x0027
+#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E	0x0070
+#define PCI_DEVICE_ID_DIGI_DF_M_E	0x0071
+#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A	0x0072
+#define PCI_DEVICE_ID_DIGI_DF_M_A	0x0073
+
+#define PCI_VENDOR_ID_MUTECH		0x1159
+#define PCI_DEVICE_ID_MUTECH_MV1000	0x0001
+
+#define PCI_VENDOR_ID_XIRCOM		0x115d
+#define PCI_DEVICE_ID_XIRCOM_X3201_ETH	0x0003
+#define PCI_DEVICE_ID_XIRCOM_X3201_MDM	0x0103
+
+#define PCI_VENDOR_ID_RENDITION		0x1163
+#define PCI_DEVICE_ID_RENDITION_VERITE	0x0001
+#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000
+
+#define PCI_VENDOR_ID_SERVERWORKS		0x1166
+#define PCI_DEVICE_ID_SERVERWORKS_HE		0x0008
+#define PCI_DEVICE_ID_SERVERWORKS_LE		0x0009
+#define PCI_DEVICE_ID_SERVERWORKS_CIOB30	0x0010
+#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE	0x0011
+#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE	0x0017
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4		0x0200
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5		0x0201
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6		0x0203
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE	0x0211
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE	0x0212
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE	0x0213
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2	0x0217
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB	0x0220
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5USB	PCI_DEVICE_ID_SERVERWORKS_OSB4USB
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6USB	0x0221
+#define PCI_DEVICE_ID_SERVERWORKS_GCLE		0x0225
+#define PCI_DEVICE_ID_SERVERWORKS_GCLE2		0x0227
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA	0x0230
+
+#define PCI_VENDOR_ID_SBE		0x1176
+#define PCI_DEVICE_ID_SBE_WANXL100	0x0301
+#define PCI_DEVICE_ID_SBE_WANXL200	0x0302
+#define PCI_DEVICE_ID_SBE_WANXL400	0x0104
+
+#define PCI_VENDOR_ID_TOSHIBA		0x1179
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO	0x0102
+#define PCI_DEVICE_ID_TOSHIBA_601	0x0601
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC95	0x060a
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC97	0x060f
+
+#define PCI_VENDOR_ID_TOSHIBA_2		0x102f
+#define PCI_DEVICE_ID_TOSHIBA_TX3927	0x000a
+#define PCI_DEVICE_ID_TOSHIBA_TC35815CF 0x0030
+#define PCI_DEVICE_ID_TOSHIBA_TX4927	0x0180
+
+#define PCI_VENDOR_ID_RICOH		0x1180
+#define PCI_DEVICE_ID_RICOH_RL5C465	0x0465
+#define PCI_DEVICE_ID_RICOH_RL5C466	0x0466
+#define PCI_DEVICE_ID_RICOH_RL5C475	0x0475
+#define PCI_DEVICE_ID_RICOH_RL5C476	0x0476
+#define PCI_DEVICE_ID_RICOH_RL5C478	0x0478
+
+#define PCI_VENDOR_ID_ARTOP		0x1191
+#define PCI_DEVICE_ID_ARTOP_ATP8400	0x0004
+#define PCI_DEVICE_ID_ARTOP_ATP850UF	0x0005
+#define PCI_DEVICE_ID_ARTOP_ATP860	0x0006
+#define PCI_DEVICE_ID_ARTOP_ATP860R	0x0007
+#define PCI_DEVICE_ID_ARTOP_ATP865	0x0008
+#define PCI_DEVICE_ID_ARTOP_ATP865R	0x0009
+#define PCI_DEVICE_ID_ARTOP_AEC7610	0x8002
+#define PCI_DEVICE_ID_ARTOP_AEC7612UW	0x8010
+#define PCI_DEVICE_ID_ARTOP_AEC7612U	0x8020
+#define PCI_DEVICE_ID_ARTOP_AEC7612S	0x8030
+#define PCI_DEVICE_ID_ARTOP_AEC7612D	0x8040
+#define PCI_DEVICE_ID_ARTOP_AEC7612SUW	0x8050
+#define PCI_DEVICE_ID_ARTOP_8060	0x8060
+
+#define PCI_VENDOR_ID_ZEITNET		0x1193
+#define PCI_DEVICE_ID_ZEITNET_1221	0x0001
+#define PCI_DEVICE_ID_ZEITNET_1225	0x0002
+
+#define PCI_VENDOR_ID_OMEGA		0x119b
+#define PCI_DEVICE_ID_OMEGA_82C092G	0x1221
+
+#define PCI_VENDOR_ID_FUJITSU_ME	0x119e
+#define PCI_DEVICE_ID_FUJITSU_FS155	0x0001
+#define PCI_DEVICE_ID_FUJITSU_FS50	0x0003
+
+#define PCI_SUBVENDOR_ID_KEYSPAN	0x11a9
+#define PCI_SUBDEVICE_ID_KEYSPAN_SX2	0x5334
+
+#define PCI_VENDOR_ID_GALILEO		0x11ab
+#define PCI_DEVICE_ID_GALILEO_GT64011	0x4146
+#define PCI_DEVICE_ID_GALILEO_GT64111	0x4146
+#define PCI_DEVICE_ID_GALILEO_GT96100	0x9652
+#define PCI_DEVICE_ID_GALILEO_GT96100A	0x9653
+
+#define PCI_VENDOR_ID_LITEON		0x11ad
+#define PCI_DEVICE_ID_LITEON_LNE100TX	0x0002
+
+#define PCI_VENDOR_ID_V3		0x11b0
+#define PCI_DEVICE_ID_V3_V960		0x0001
+#define PCI_DEVICE_ID_V3_V350		0x0001
+#define PCI_DEVICE_ID_V3_V961		0x0002
+#define PCI_DEVICE_ID_V3_V351		0x0002
+
+#define PCI_VENDOR_ID_NP		0x11bc
+#define PCI_DEVICE_ID_NP_PCI_FDDI	0x0001
+
+#define PCI_VENDOR_ID_ATT		0x11c1
+#define PCI_DEVICE_ID_ATT_L56XMF	0x0440
+#define PCI_DEVICE_ID_ATT_VENUS_MODEM	0x480
+
+#define PCI_VENDOR_ID_SPECIALIX		0x11cb
+#define PCI_DEVICE_ID_SPECIALIX_IO8	0x2000
+#define PCI_DEVICE_ID_SPECIALIX_XIO	0x4000
+#define PCI_DEVICE_ID_SPECIALIX_RIO	0x8000
+#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004
+
+#define PCI_VENDOR_ID_AURAVISION	0x11d1
+#define PCI_DEVICE_ID_AURAVISION_VXP524 0x01f7
+
+#define PCI_VENDOR_ID_ANALOG_DEVICES	0x11d4
+#define PCI_DEVICE_ID_AD1889JS		0x1889
+
+#define PCI_VENDOR_ID_IKON		0x11d5
+#define PCI_DEVICE_ID_IKON_10115	0x0115
+#define PCI_DEVICE_ID_IKON_10117	0x0117
+
+#define PCI_VENDOR_ID_ZORAN		0x11de
+#define PCI_DEVICE_ID_ZORAN_36057	0x6057
+#define PCI_DEVICE_ID_ZORAN_36120	0x6120
+
+#define PCI_VENDOR_ID_KINETIC		0x11f4
+#define PCI_DEVICE_ID_KINETIC_2915	0x2915
+
+#define PCI_VENDOR_ID_COMPEX		0x11f6
+#define PCI_DEVICE_ID_COMPEX_ENET100VG4 0x0112
+#define PCI_DEVICE_ID_COMPEX_RL2000	0x1401
+
+#define PCI_VENDOR_ID_RP		0x11fe
+#define PCI_DEVICE_ID_RP32INTF		0x0001
+#define PCI_DEVICE_ID_RP8INTF		0x0002
+#define PCI_DEVICE_ID_RP16INTF		0x0003
+#define PCI_DEVICE_ID_RP4QUAD		0x0004
+#define PCI_DEVICE_ID_RP8OCTA		0x0005
+#define PCI_DEVICE_ID_RP8J		0x0006
+#define PCI_DEVICE_ID_RPP4		0x000A
+#define PCI_DEVICE_ID_RPP8		0x000B
+#define PCI_DEVICE_ID_RP8M		0x000C
+
+#define PCI_VENDOR_ID_CYCLADES		0x120e
+#define PCI_DEVICE_ID_CYCLOM_Y_Lo	0x0100
+#define PCI_DEVICE_ID_CYCLOM_Y_Hi	0x0101
+#define PCI_DEVICE_ID_CYCLOM_4Y_Lo	0x0102
+#define PCI_DEVICE_ID_CYCLOM_4Y_Hi	0x0103
+#define PCI_DEVICE_ID_CYCLOM_8Y_Lo	0x0104
+#define PCI_DEVICE_ID_CYCLOM_8Y_Hi	0x0105
+#define PCI_DEVICE_ID_CYCLOM_Z_Lo	0x0200
+#define PCI_DEVICE_ID_CYCLOM_Z_Hi	0x0201
+#define PCI_DEVICE_ID_PC300_RX_2	0x0300
+#define PCI_DEVICE_ID_PC300_RX_1	0x0301
+#define PCI_DEVICE_ID_PC300_TE_2	0x0310
+#define PCI_DEVICE_ID_PC300_TE_1	0x0311
+
+#define PCI_VENDOR_ID_ESSENTIAL		0x120f
+#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER	0x0001
+
+#define PCI_VENDOR_ID_O2		0x1217
+#define PCI_DEVICE_ID_O2_6729		0x6729
+#define PCI_DEVICE_ID_O2_6730		0x673a
+#define PCI_DEVICE_ID_O2_6832		0x6832
+#define PCI_DEVICE_ID_O2_6836		0x6836
+
+#define PCI_VENDOR_ID_3DFX		0x121a
+#define PCI_DEVICE_ID_3DFX_VOODOO	0x0001
+#define PCI_DEVICE_ID_3DFX_VOODOO2	0x0002
+#define PCI_DEVICE_ID_3DFX_BANSHEE	0x0003
+#define PCI_DEVICE_ID_3DFX_VOODOO3	0x0005
+
+#define PCI_VENDOR_ID_SIGMADES		0x1236
+#define PCI_DEVICE_ID_SIGMADES_6425	0x6401
+
+#define PCI_VENDOR_ID_CCUBE		0x123f
+
+#define PCI_VENDOR_ID_AVM		0x1244
+#define PCI_DEVICE_ID_AVM_B1		0x0700
+#define PCI_DEVICE_ID_AVM_C4		0x0800
+#define PCI_DEVICE_ID_AVM_A1		0x0a00
+#define PCI_DEVICE_ID_AVM_A1_V2		0x0e00
+#define PCI_DEVICE_ID_AVM_C2		0x1100
+#define PCI_DEVICE_ID_AVM_T1		0x1200
+
+#define PCI_VENDOR_ID_DIPIX		0x1246
+
+#define PCI_VENDOR_ID_STALLION		0x124d
+#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000
+#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002
+#define PCI_DEVICE_ID_STALLION_EIOPCI	0x0003
+
+#define PCI_VENDOR_ID_OPTIBASE		0x1255
+#define PCI_DEVICE_ID_OPTIBASE_FORGE	0x1110
+#define PCI_DEVICE_ID_OPTIBASE_FUSION	0x1210
+#define PCI_DEVICE_ID_OPTIBASE_VPLEX	0x2110
+#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC	0x2120
+#define PCI_DEVICE_ID_OPTIBASE_VQUEST	0x2130
+
+#define PCI_VENDOR_ID_ESS		0x125d
+#define PCI_DEVICE_ID_ESS_ESS1968	0x1968
+#define PCI_DEVICE_ID_ESS_AUDIOPCI	0x1969
+#define PCI_DEVICE_ID_ESS_ESS1978	0x1978
+
+#define PCI_VENDOR_ID_SATSAGEM		0x1267
+#define PCI_DEVICE_ID_SATSAGEM_NICCY	0x1016
+#define PCI_DEVICE_ID_SATSAGEM_PCR2101	0x5352
+#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b
+
+#define PCI_VENDOR_ID_SMI		0x126f
+#define PCI_DEVICE_ID_SMI_710		0x0710
+#define PCI_DEVICE_ID_SMI_712		0x0712
+#define PCI_DEVICE_ID_SMI_810		0x0810
+
+#define PCI_VENDOR_ID_HUGHES		0x1273
+#define PCI_DEVICE_ID_HUGHES_DIRECPC	0x0002
+
+#define PCI_VENDOR_ID_ENSONIQ		0x1274
+#define PCI_DEVICE_ID_ENSONIQ_CT5880	0x5880
+#define PCI_DEVICE_ID_ENSONIQ_ES1370	0x5000
+#define PCI_DEVICE_ID_ENSONIQ_ES1371	0x1371
+
+#define PCI_VENDOR_ID_ROCKWELL		0x127A
+
+#define PCI_VENDOR_ID_DAVICOM		0x1282
+#define PCI_DEVICE_ID_DAVICOM_DM9102A	0x9102
+
+#define PCI_VENDOR_ID_ITE		0x1283
+#define PCI_DEVICE_ID_ITE_IT8172G	0x8172
+#define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801
+#define PCI_DEVICE_ID_ITE_IT8181	0x8181
+#define PCI_DEVICE_ID_ITE_8872		0x8872
+
+#define PCI_DEVICE_ID_ITE_IT8330G_0	0xe886
+
+/* formerly Platform Tech */
+#define PCI_VENDOR_ID_ESS_OLD		0x1285
+#define PCI_DEVICE_ID_ESS_ESS0100	0x0100
+
+#define PCI_VENDOR_ID_ALTEON		0x12ae
+#define PCI_DEVICE_ID_ALTEON_ACENIC	0x0001
+
+#define PCI_VENDOR_ID_USR		0x12B9
+
+#define PCI_SUBVENDOR_ID_CONNECT_TECH			0x12c4
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232		0x0001
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232		0x0002
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232		0x0003
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485		0x0004
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4	0x0005
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485		0x0006
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2	0x0007
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485		0x0008
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6	0x0009
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1	0x000A
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1	0x000B
+
+#define PCI_VENDOR_ID_PICTUREL		0x12c5
+#define PCI_DEVICE_ID_PICTUREL_PCIVST	0x0081
+
+#define PCI_VENDOR_ID_NVIDIA_SGS	0x12d2
+#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
+
+#define PCI_SUBVENDOR_ID_CHASE_PCIFAST		0x12E0
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4		0x0031
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8		0x0021
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16	0x0011
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC	0x0041
+#define PCI_SUBVENDOR_ID_CHASE_PCIRAS		0x124D
+#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4		0xF001
+#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8		0xF010
+
+#define PCI_VENDOR_ID_AUREAL		0x12eb
+#define PCI_DEVICE_ID_AUREAL_VORTEX_1	0x0001
+#define PCI_DEVICE_ID_AUREAL_VORTEX_2	0x0002
+
+#define PCI_VENDOR_ID_CBOARDS		0x1307
+#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001
+
+#define PCI_VENDOR_ID_SIIG		0x131f
+#define PCI_DEVICE_ID_SIIG_1S_10x_550	0x1000
+#define PCI_DEVICE_ID_SIIG_1S_10x_650	0x1001
+#define PCI_DEVICE_ID_SIIG_1S_10x_850	0x1002
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_550 0x1010
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_650 0x1011
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_850 0x1012
+#define PCI_DEVICE_ID_SIIG_1P_10x	0x1020
+#define PCI_DEVICE_ID_SIIG_2P_10x	0x1021
+#define PCI_DEVICE_ID_SIIG_2S_10x_550	0x1030
+#define PCI_DEVICE_ID_SIIG_2S_10x_650	0x1031
+#define PCI_DEVICE_ID_SIIG_2S_10x_850	0x1032
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_550 0x1034
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_650 0x1035
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_850 0x1036
+#define PCI_DEVICE_ID_SIIG_4S_10x_550	0x1050
+#define PCI_DEVICE_ID_SIIG_4S_10x_650	0x1051
+#define PCI_DEVICE_ID_SIIG_4S_10x_850	0x1052
+#define PCI_DEVICE_ID_SIIG_1S_20x_550	0x2000
+#define PCI_DEVICE_ID_SIIG_1S_20x_650	0x2001
+#define PCI_DEVICE_ID_SIIG_1S_20x_850	0x2002
+#define PCI_DEVICE_ID_SIIG_1P_20x	0x2020
+#define PCI_DEVICE_ID_SIIG_2P_20x	0x2021
+#define PCI_DEVICE_ID_SIIG_2S_20x_550	0x2030
+#define PCI_DEVICE_ID_SIIG_2S_20x_650	0x2031
+#define PCI_DEVICE_ID_SIIG_2S_20x_850	0x2032
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_550 0x2040
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_650 0x2041
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_850 0x2042
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_550 0x2010
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_650 0x2011
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_850 0x2012
+#define PCI_DEVICE_ID_SIIG_4S_20x_550	0x2050
+#define PCI_DEVICE_ID_SIIG_4S_20x_650	0x2051
+#define PCI_DEVICE_ID_SIIG_4S_20x_850	0x2052
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_550 0x2060
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_650 0x2061
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_850 0x2062
+
+#define PCI_VENDOR_ID_DOMEX		0x134a
+#define PCI_DEVICE_ID_DOMEX_DMX3191D	0x0001
+
+#define PCI_VENDOR_ID_QUATECH		0x135C
+#define PCI_DEVICE_ID_QUATECH_QSC100	0x0010
+#define PCI_DEVICE_ID_QUATECH_DSC100	0x0020
+#define PCI_DEVICE_ID_QUATECH_DSC200	0x0030
+#define PCI_DEVICE_ID_QUATECH_QSC200	0x0040
+#define PCI_DEVICE_ID_QUATECH_ESC100D	0x0050
+#define PCI_DEVICE_ID_QUATECH_ESC100M	0x0060
+
+#define PCI_VENDOR_ID_SEALEVEL		0x135e
+#define PCI_DEVICE_ID_SEALEVEL_U530	0x7101
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM2	0x7201
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM422 0x7402
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM232 0x7202
+#define PCI_DEVICE_ID_SEALEVEL_COMM4	0x7401
+#define PCI_DEVICE_ID_SEALEVEL_COMM8	0x7801
+
+#define PCI_VENDOR_ID_HYPERCOPE		0x1365
+#define PCI_DEVICE_ID_HYPERCOPE_PLX	0x9050
+#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO	0x0104
+#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO		0x0106
+#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO	0x0107
+#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2	0x0108
+#define PCI_SUBDEVICE_ID_HYPERCOPE_PLEXUS	0x0109
+
+#define PCI_VENDOR_ID_KAWASAKI		0x136b
+#define PCI_DEVICE_ID_MCHIP_KL5A72002	0xff01
+
+#define PCI_VENDOR_ID_LMC		0x1376
+#define PCI_DEVICE_ID_LMC_HSSI		0x0003
+#define PCI_DEVICE_ID_LMC_DS3		0x0004
+#define PCI_DEVICE_ID_LMC_SSI		0x0005
+#define PCI_DEVICE_ID_LMC_T1		0x0006
+
+#define PCI_VENDOR_ID_NETGEAR		0x1385
+#define PCI_DEVICE_ID_NETGEAR_GA620	0x620a
+#define PCI_DEVICE_ID_NETGEAR_GA622	0x622a
+
+#define PCI_VENDOR_ID_APPLICOM		0x1389
+#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001
+#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002
+#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003
+
+#define PCI_VENDOR_ID_MOXA		0x1393
+#define PCI_DEVICE_ID_MOXA_C104		0x1040
+#define PCI_DEVICE_ID_MOXA_C168		0x1680
+#define PCI_DEVICE_ID_MOXA_CP204J	0x2040
+#define PCI_DEVICE_ID_MOXA_C218		0x2180
+#define PCI_DEVICE_ID_MOXA_C320		0x3200
+
+#define PCI_VENDOR_ID_CCD		0x1397
+#define PCI_DEVICE_ID_CCD_2BD0		0x2bd0
+#define PCI_DEVICE_ID_CCD_B000		0xb000
+#define PCI_DEVICE_ID_CCD_B006		0xb006
+#define PCI_DEVICE_ID_CCD_B007		0xb007
+#define PCI_DEVICE_ID_CCD_B008		0xb008
+#define PCI_DEVICE_ID_CCD_B009		0xb009
+#define PCI_DEVICE_ID_CCD_B00A		0xb00a
+#define PCI_DEVICE_ID_CCD_B00B		0xb00b
+#define PCI_DEVICE_ID_CCD_B00C		0xb00c
+#define PCI_DEVICE_ID_CCD_B100		0xb100
+
+#define PCI_VENDOR_ID_3WARE		0x13C1
+#define PCI_DEVICE_ID_3WARE_1000	0x1000
+
+#define PCI_VENDOR_ID_ABOCOM		0x13D1
+#define PCI_DEVICE_ID_ABOCOM_2BD1	0x2BD1
+
+#define PCI_VENDOR_ID_CMEDIA		0x13f6
+#define PCI_DEVICE_ID_CMEDIA_CM8338A	0x0100
+#define PCI_DEVICE_ID_CMEDIA_CM8338B	0x0101
+#define PCI_DEVICE_ID_CMEDIA_CM8738	0x0111
+#define PCI_DEVICE_ID_CMEDIA_CM8738B	0x0112
+
+#define PCI_VENDOR_ID_LAVA		0x1407
+#define PCI_DEVICE_ID_LAVA_DSERIAL	0x0100 /* 2x 16550 */
+#define PCI_DEVICE_ID_LAVA_QUATRO_A	0x0101 /* 2x 16550, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_QUATRO_B	0x0102 /* 2x 16550, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_OCTO_A	0x0180 /* 4x 16550A, half of 8 port */
+#define PCI_DEVICE_ID_LAVA_OCTO_B	0x0181 /* 4x 16550A, half of 8 port */
+#define PCI_DEVICE_ID_LAVA_PORT_PLUS	0x0200 /* 2x 16650 */
+#define PCI_DEVICE_ID_LAVA_QUAD_A	0x0201 /* 2x 16650, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_QUAD_B	0x0202 /* 2x 16650, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_SSERIAL	0x0500 /* 1x 16550 */
+#define PCI_DEVICE_ID_LAVA_PORT_650	0x0600 /* 1x 16650 */
+#define PCI_DEVICE_ID_LAVA_PARALLEL	0x8000
+#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A	0x8002 /* The Lava Dual Parallel is */
+#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B	0x8003 /* two PCI devices on a card */
+#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR	0x8800
+
+#define PCI_VENDOR_ID_TIMEDIA		0x1409
+#define PCI_DEVICE_ID_TIMEDIA_1889	0x7168
+
+#define PCI_VENDOR_ID_OXSEMI		0x1415
+#define PCI_DEVICE_ID_OXSEMI_12PCI840	0x8403
+#define PCI_DEVICE_ID_OXSEMI_16PCI954	0x9501
+#define PCI_DEVICE_ID_OXSEMI_16PCI95N	0x9511
+#define PCI_DEVICE_ID_OXSEMI_16PCI954PP 0x9513
+#define PCI_DEVICE_ID_OXSEMI_16PCI952	0x9521
+
+#define PCI_VENDOR_ID_AIRONET		0x14b9
+#define PCI_DEVICE_ID_AIRONET_4800_1	0x0001
+#define PCI_DEVICE_ID_AIRONET_4800	0x4500 /* values switched?  see */
+#define PCI_DEVICE_ID_AIRONET_4500	0x4800 /* drivers/net/aironet4500_card.c */
+
+#define PCI_VENDOR_ID_TITAN		0x14D2
+#define PCI_DEVICE_ID_TITAN_010L	0x8001
+#define PCI_DEVICE_ID_TITAN_100L	0x8010
+#define PCI_DEVICE_ID_TITAN_110L	0x8011
+#define PCI_DEVICE_ID_TITAN_200L	0x8020
+#define PCI_DEVICE_ID_TITAN_210L	0x8021
+#define PCI_DEVICE_ID_TITAN_400L	0x8040
+#define PCI_DEVICE_ID_TITAN_800L	0x8080
+#define PCI_DEVICE_ID_TITAN_100		0xA001
+#define PCI_DEVICE_ID_TITAN_200		0xA005
+#define PCI_DEVICE_ID_TITAN_400		0xA003
+#define PCI_DEVICE_ID_TITAN_800B	0xA004
+
+#define PCI_VENDOR_ID_PANACOM		0x14d4
+#define PCI_DEVICE_ID_PANACOM_QUADMODEM 0x0400
+#define PCI_DEVICE_ID_PANACOM_DUALMODEM 0x0402
+
+#define PCI_VENDOR_ID_AFAVLAB		0x14db
+#define PCI_DEVICE_ID_AFAVLAB_P028	0x2180
+
+#define PCI_VENDOR_ID_BROADCOM		0x14e4
+#define PCI_DEVICE_ID_TIGON3_5700	0x1644
+#define PCI_DEVICE_ID_TIGON3_5701	0x1645
+#define PCI_DEVICE_ID_TIGON3_5702	0x1646
+#define PCI_DEVICE_ID_TIGON3_5703	0x1647
+#define PCI_DEVICE_ID_TIGON3_5704	0x1648
+#define PCI_DEVICE_ID_TIGON3_5704S_2	0x1649
+#define PCI_DEVICE_ID_TIGON3_5702FE	0x164d
+#define PCI_DEVICE_ID_TIGON3_5705	0x1653
+#define PCI_DEVICE_ID_TIGON3_5705_2	0x1654
+#define PCI_DEVICE_ID_TIGON3_5705M	0x165d
+#define PCI_DEVICE_ID_TIGON3_5705M_2	0x165e
+#define PCI_DEVICE_ID_TIGON3_5705F	0x166e
+#define PCI_DEVICE_ID_TIGON3_5782	0x1696
+#define PCI_DEVICE_ID_TIGON3_5788	0x169c
+#define PCI_DEVICE_ID_TIGON3_5702X	0x16a6
+#define PCI_DEVICE_ID_TIGON3_5703X	0x16a7
+#define PCI_DEVICE_ID_TIGON3_5704S	0x16a8
+#define PCI_DEVICE_ID_TIGON3_5702A3	0x16c6
+#define PCI_DEVICE_ID_TIGON3_5703A3	0x16c7
+#define PCI_DEVICE_ID_TIGON3_5901	0x170d
+#define PCI_DEVICE_ID_TIGON3_5901_2	0x170e
+#define PCI_DEVICE_ID_BCM4401		0x4401
+
+#define PCI_VENDOR_ID_ENE		0x1524
+#define PCI_DEVICE_ID_ENE_1211		0x1211
+#define PCI_DEVICE_ID_ENE_1225		0x1225
+#define PCI_DEVICE_ID_ENE_1410		0x1410
+#define PCI_DEVICE_ID_ENE_1420		0x1420
+
+#define PCI_VENDOR_ID_SYBA		0x1592
+#define PCI_DEVICE_ID_SYBA_2P_EPP	0x0782
+#define PCI_DEVICE_ID_SYBA_1P_ECP	0x0783
+
+#define PCI_VENDOR_ID_MORETON		0x15aa
+#define PCI_DEVICE_ID_RASTEL_2PORT	0x2000
+
+#define PCI_VENDOR_ID_ZOLTRIX		0x15b0
+#define PCI_DEVICE_ID_ZOLTRIX_2BD0	0x2bd0
+
+#define PCI_VENDOR_ID_PDC		0x15e9
+#define PCI_DEVICE_ID_PDC_ADMA100	0x1841
+
+#define PCI_VENDOR_ID_ALTIMA		0x173b
+#define PCI_DEVICE_ID_ALTIMA_AC1000	0x03e8
+#define PCI_DEVICE_ID_ALTIMA_AC1001	0x03e9
+#define PCI_DEVICE_ID_ALTIMA_AC9100	0x03ea
+#define PCI_DEVICE_ID_ALTIMA_AC1003	0x03eb
+
+#define PCI_VENDOR_ID_SYMPHONY		0x1c1c
+#define PCI_DEVICE_ID_SYMPHONY_101	0x0001
+
+#define PCI_VENDOR_ID_TEKRAM		0x1de1
+#define PCI_DEVICE_ID_TEKRAM_DC290	0xdc29
+
+#define PCI_VENDOR_ID_HINT		0x3388
+#define PCI_DEVICE_ID_HINT_VXPROII_IDE	0x8013
+
+#define PCI_VENDOR_ID_3DLABS		0x3d3d
+#define PCI_DEVICE_ID_3DLABS_300SX	0x0001
+#define PCI_DEVICE_ID_3DLABS_500TX	0x0002
+#define PCI_DEVICE_ID_3DLABS_DELTA	0x0003
+#define PCI_DEVICE_ID_3DLABS_PERMEDIA	0x0004
+#define PCI_DEVICE_ID_3DLABS_MX		0x0006
+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2	0x0007
+#define PCI_DEVICE_ID_3DLABS_GAMMA	0x0008
+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009
+
+#define PCI_VENDOR_ID_AVANCE		0x4005
+#define PCI_DEVICE_ID_AVANCE_ALG2064	0x2064
+#define PCI_DEVICE_ID_AVANCE_2302	0x2302
+
+#define PCI_VENDOR_ID_AKS		0x416c
+#define PCI_DEVICE_ID_AKS_ALADDINCARD	0x0100
+#define PCI_DEVICE_ID_AKS_CPC		0x0200
+
+#define PCI_VENDOR_ID_REDCREEK		0x4916
+#define PCI_DEVICE_ID_RC45		0x1960
+
+#define PCI_VENDOR_ID_NETVIN		0x4a14
+#define PCI_DEVICE_ID_NETVIN_NV5000SC	0x5000
+
+#define PCI_VENDOR_ID_S3		0x5333
+#define PCI_DEVICE_ID_S3_PLATO_PXS	0x0551
+#define PCI_DEVICE_ID_S3_ViRGE		0x5631
+#define PCI_DEVICE_ID_S3_TRIO		0x8811
+#define PCI_DEVICE_ID_S3_AURORA64VP	0x8812
+#define PCI_DEVICE_ID_S3_TRIO64UVP	0x8814
+#define PCI_DEVICE_ID_S3_ViRGE_VX	0x883d
+#define PCI_DEVICE_ID_S3_868		0x8880
+#define PCI_DEVICE_ID_S3_928		0x88b0
+#define PCI_DEVICE_ID_S3_864_1		0x88c0
+#define PCI_DEVICE_ID_S3_864_2		0x88c1
+#define PCI_DEVICE_ID_S3_964_1		0x88d0
+#define PCI_DEVICE_ID_S3_964_2		0x88d1
+#define PCI_DEVICE_ID_S3_968		0x88f0
+#define PCI_DEVICE_ID_S3_TRIO64V2	0x8901
+#define PCI_DEVICE_ID_S3_PLATO_PXG	0x8902
+#define PCI_DEVICE_ID_S3_ViRGE_DXGX	0x8a01
+#define PCI_DEVICE_ID_S3_ViRGE_GX2	0x8a10
+#define PCI_DEVICE_ID_S3_ViRGE_MX	0x8c01
+#define PCI_DEVICE_ID_S3_ViRGE_MXP	0x8c02
+#define PCI_DEVICE_ID_S3_ViRGE_MXPMV	0x8c03
+#define PCI_DEVICE_ID_S3_SONICVIBES	0xca00
+
+#define PCI_VENDOR_ID_DUNORD		0x5544
+#define PCI_DEVICE_ID_DUNORD_I3000	0x0001
+#define PCI_VENDOR_ID_GENROCO		0x5555
+#define PCI_DEVICE_ID_GENROCO_HFP832	0x0003
+
+#define PCI_VENDOR_ID_DCI		0x6666
+#define PCI_DEVICE_ID_DCI_PCCOM4	0x0001
+#define PCI_DEVICE_ID_DCI_PCCOM8	0x0002
+
+#define PCI_VENDOR_ID_INTEL		0x8086
+#define PCI_DEVICE_ID_INTEL_21145	0x0039
+#define PCI_DEVICE_ID_INTEL_21152BB	0xb152
+#define PCI_DEVICE_ID_INTEL_82375	0x0482
+#define PCI_DEVICE_ID_INTEL_82424	0x0483
+#define PCI_DEVICE_ID_INTEL_82378	0x0484
+#define PCI_DEVICE_ID_INTEL_82430	0x0486
+#define PCI_DEVICE_ID_INTEL_82434	0x04a3
+#define PCI_DEVICE_ID_INTEL_I960	0x0960
+#define PCI_DEVICE_ID_INTEL_I960RM	0x0962
+#define PCI_DEVICE_ID_INTEL_82542	0x1000
+#define PCI_DEVICE_ID_INTEL_82543GC_FIBER	0x1001
+#define PCI_DEVICE_ID_INTEL_82543GC_COPPER	0x1004
+#define PCI_DEVICE_ID_INTEL_82544EI_COPPER	0x1008
+#define PCI_DEVICE_ID_INTEL_82544EI_FIBER	0x1009
+#define PCI_DEVICE_ID_INTEL_82544GC_COPPER	0x100C
+#define PCI_DEVICE_ID_INTEL_82544GC_LOM		0x100D
+#define PCI_DEVICE_ID_INTEL_82540EM		0x100E
+#define PCI_DEVICE_ID_INTEL_82545EM_COPPER	0x100F
+#define PCI_DEVICE_ID_INTEL_82546EB_COPPER	0x1010
+#define PCI_DEVICE_ID_INTEL_82545EM_FIBER	0x1011
+#define PCI_DEVICE_ID_INTEL_82546EB_FIBER	0x1012
+#define PCI_DEVICE_ID_INTEL_82540EM_LOM		0x1015
+#define PCI_DEVICE_ID_INTEL_82559		0x1030
+
+#define PCI_DEVICE_ID_INTEL_82562ET	0x1031
+
+#define PCI_DEVICE_ID_INTEL_82815_MC	0x1130
+
+#define PCI_DEVICE_ID_INTEL_82559ER	0x1209
+#define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
+#define PCI_DEVICE_ID_INTEL_82092AA_1	0x1222
+#define PCI_DEVICE_ID_INTEL_7116	0x1223
+#define PCI_DEVICE_ID_INTEL_7205_0	0x255d
+#define PCI_DEVICE_ID_INTEL_82596	0x1226
+#define PCI_DEVICE_ID_INTEL_82865	0x1227
+#define PCI_DEVICE_ID_INTEL_82557	0x1229
+#define PCI_DEVICE_ID_INTEL_82437	0x122d
+#define PCI_DEVICE_ID_INTEL_82371FB_0	0x122e
+#define PCI_DEVICE_ID_INTEL_82371FB_1	0x1230
+#define PCI_DEVICE_ID_INTEL_82371MX	0x1234
+#define PCI_DEVICE_ID_INTEL_82437MX	0x1235
+#define PCI_DEVICE_ID_INTEL_82441	0x1237
+#define PCI_DEVICE_ID_INTEL_82380FB	0x124b
+#define PCI_DEVICE_ID_INTEL_82439	0x1250
+#define PCI_DEVICE_ID_INTEL_80960_RP	0x1960
+#define PCI_DEVICE_ID_INTEL_82845_HB	0x1a30
+#define PCI_DEVICE_ID_INTEL_82371SB_0	0x7000
+#define PCI_DEVICE_ID_INTEL_82371SB_1	0x7010
+#define PCI_DEVICE_ID_INTEL_82371SB_2	0x7020
+#define PCI_DEVICE_ID_INTEL_82437VX	0x7030
+#define PCI_DEVICE_ID_INTEL_82439TX	0x7100
+#define PCI_DEVICE_ID_INTEL_82371AB_0	0x7110
+#define PCI_DEVICE_ID_INTEL_82371AB	0x7111
+#define PCI_DEVICE_ID_INTEL_82371AB_2	0x7112
+#define PCI_DEVICE_ID_INTEL_82371AB_3	0x7113
+#define PCI_DEVICE_ID_INTEL_82801AA_0	0x2410
+#define PCI_DEVICE_ID_INTEL_82801AA_1	0x2411
+#define PCI_DEVICE_ID_INTEL_82801AA_2	0x2412
+#define PCI_DEVICE_ID_INTEL_82801AA_3	0x2413
+#define PCI_DEVICE_ID_INTEL_82801AA_5	0x2415
+#define PCI_DEVICE_ID_INTEL_82801AA_6	0x2416
+#define PCI_DEVICE_ID_INTEL_82801AA_8	0x2418
+#define PCI_DEVICE_ID_INTEL_82801AB_0	0x2420
+#define PCI_DEVICE_ID_INTEL_82801AB_1	0x2421
+#define PCI_DEVICE_ID_INTEL_82801AB_2	0x2422
+#define PCI_DEVICE_ID_INTEL_82801AB_3	0x2423
+#define PCI_DEVICE_ID_INTEL_82801AB_5	0x2425
+#define PCI_DEVICE_ID_INTEL_82801AB_6	0x2426
+#define PCI_DEVICE_ID_INTEL_82801AB_8	0x2428
+#define PCI_DEVICE_ID_INTEL_82801BA_0	0x2440
+#define PCI_DEVICE_ID_INTEL_82801BA_1	0x2442
+#define PCI_DEVICE_ID_INTEL_82801BA_2	0x2443
+#define PCI_DEVICE_ID_INTEL_82801BA_3	0x2444
+#define PCI_DEVICE_ID_INTEL_82801BA_4	0x2445
+#define PCI_DEVICE_ID_INTEL_82801BA_5	0x2446
+#define PCI_DEVICE_ID_INTEL_82801BA_6	0x2448
+#define PCI_DEVICE_ID_INTEL_82801BA_7	0x2449
+#define PCI_DEVICE_ID_INTEL_82801BA_8	0x244a
+#define PCI_DEVICE_ID_INTEL_82801BA_9	0x244b
+#define PCI_DEVICE_ID_INTEL_82801BA_10	0x244c
+#define PCI_DEVICE_ID_INTEL_82801BA_11	0x244e
+#define PCI_DEVICE_ID_INTEL_82801E_0	0x2450
+#define PCI_DEVICE_ID_INTEL_82801E_2	0x2452
+#define PCI_DEVICE_ID_INTEL_82801E_3	0x2453
+#define PCI_DEVICE_ID_INTEL_82801E_9	0x2459
+#define PCI_DEVICE_ID_INTEL_82801E_11	0x245B
+#define PCI_DEVICE_ID_INTEL_82801E_14	0x245D
+#define PCI_DEVICE_ID_INTEL_82801E_15	0x245E
+#define PCI_DEVICE_ID_INTEL_82801CA_0	0x2480
+#define PCI_DEVICE_ID_INTEL_82801CA_2	0x2482
+#define PCI_DEVICE_ID_INTEL_82801CA_3	0x2483
+#define PCI_DEVICE_ID_INTEL_82801CA_4	0x2484
+#define PCI_DEVICE_ID_INTEL_82801CA_5	0x2485
+#define PCI_DEVICE_ID_INTEL_82801CA_6	0x2486
+#define PCI_DEVICE_ID_INTEL_82801CA_7	0x2487
+#define PCI_DEVICE_ID_INTEL_82801CA_10	0x248a
+#define PCI_DEVICE_ID_INTEL_82801CA_11	0x248b
+#define PCI_DEVICE_ID_INTEL_82801CA_12	0x248c
+#define PCI_DEVICE_ID_INTEL_82801DB_0	0x24c0
+#define PCI_DEVICE_ID_INTEL_82801DB_2	0x24c2
+#define PCI_DEVICE_ID_INTEL_82801DB_3	0x24c3
+#define PCI_DEVICE_ID_INTEL_82801DB_4	0x24c4
+#define PCI_DEVICE_ID_INTEL_82801DB_5	0x24c5
+#define PCI_DEVICE_ID_INTEL_82801DB_6	0x24c6
+#define PCI_DEVICE_ID_INTEL_82801DB_7	0x24c7
+#define PCI_DEVICE_ID_INTEL_82801DB_10	0x24ca
+#define PCI_DEVICE_ID_INTEL_82801DB_11	0x24cb
+#define PCI_DEVICE_ID_INTEL_82801DB_12	0x24cc
+#define PCI_DEVICE_ID_INTEL_82801DB_13	0x24cd
+#define PCI_DEVICE_ID_INTEL_82801EB_0	0x24d0
+#define PCI_DEVICE_ID_INTEL_82801EB_1	0x24d1
+#define PCI_DEVICE_ID_INTEL_82801EB_2	0x24d2
+#define PCI_DEVICE_ID_INTEL_82801EB_3	0x24d3
+#define PCI_DEVICE_ID_INTEL_82801EB_4	0x24d4
+#define PCI_DEVICE_ID_INTEL_82801EB_5	0x24d5
+#define PCI_DEVICE_ID_INTEL_82801EB_6	0x24d6
+#define PCI_DEVICE_ID_INTEL_82801EB_7	0x24d7
+#define PCI_DEVICE_ID_INTEL_82801DB_10	0x24ca
+#define PCI_DEVICE_ID_INTEL_82801EB_11	0x24db
+#define PCI_DEVICE_ID_INTEL_82801EB_13	0x24dd
+#define PCI_DEVICE_ID_INTEL_ESB_0	0x25a0
+#define PCI_DEVICE_ID_INTEL_ESB_1	0x25a1
+#define PCI_DEVICE_ID_INTEL_ESB_2	0x25a2
+#define PCI_DEVICE_ID_INTEL_ESB_3	0x25a3
+#define PCI_DEVICE_ID_INTEL_ESB_31	0x25b0
+#define PCI_DEVICE_ID_INTEL_ESB_4	0x25a4
+#define PCI_DEVICE_ID_INTEL_ESB_5	0x25a6
+#define PCI_DEVICE_ID_INTEL_ESB_6	0x25a7
+#define PCI_DEVICE_ID_INTEL_ESB_7	0x25a9
+#define PCI_DEVICE_ID_INTEL_ESB_8	0x25aa
+#define PCI_DEVICE_ID_INTEL_ESB_9	0x25ab
+#define PCI_DEVICE_ID_INTEL_ESB_11	0x25ac
+#define PCI_DEVICE_ID_INTEL_ESB_12	0x25ad
+#define PCI_DEVICE_ID_INTEL_ESB_13	0x25ae
+#define PCI_DEVICE_ID_INTEL_ICH6_0	0x2640
+#define PCI_DEVICE_ID_INTEL_ICH6_1	0x2641
+#define PCI_DEVICE_ID_INTEL_ICH6_2	0x266f
+#define PCI_DEVICE_ID_INTEL_ICH6_3	0x266e
+#define PCI_DEVICE_ID_INTEL_82850_HB	0x2530
+#define PCI_DEVICE_ID_INTEL_82845G_HB	0x2560
+#define PCI_DEVICE_ID_INTEL_80310	0x530d
+#define PCI_DEVICE_ID_INTEL_82810_MC1	0x7120
+#define PCI_DEVICE_ID_INTEL_82810_IG1	0x7121
+#define PCI_DEVICE_ID_INTEL_82810_MC3	0x7122
+#define PCI_DEVICE_ID_INTEL_82810_IG3	0x7123
+#define PCI_DEVICE_ID_INTEL_82443LX_0	0x7180
+#define PCI_DEVICE_ID_INTEL_82443LX_1	0x7181
+#define PCI_DEVICE_ID_INTEL_82443BX_0	0x7190
+#define PCI_DEVICE_ID_INTEL_82443BX_1	0x7191
+#define PCI_DEVICE_ID_INTEL_82443BX_2	0x7192
+#define PCI_DEVICE_ID_INTEL_82443MX_0	0x7198
+#define PCI_DEVICE_ID_INTEL_82443MX_1	0x7199
+#define PCI_DEVICE_ID_INTEL_82443MX_2	0x719a
+#define PCI_DEVICE_ID_INTEL_82443MX_3	0x719b
+#define PCI_DEVICE_ID_INTEL_82443GX_0	0x71a0
+#define PCI_DEVICE_ID_INTEL_82443GX_1	0x71a1
+#define PCI_DEVICE_ID_INTEL_82443GX_2	0x71a2
+#define PCI_DEVICE_ID_INTEL_82372FB_0	0x7600
+#define PCI_DEVICE_ID_INTEL_82372FB_1	0x7601
+#define PCI_DEVICE_ID_INTEL_82372FB_2	0x7602
+#define PCI_DEVICE_ID_INTEL_82372FB_3	0x7603
+#define PCI_DEVICE_ID_INTEL_82454GX	0x84c4
+#define PCI_DEVICE_ID_INTEL_82450GX	0x84c5
+#define PCI_DEVICE_ID_INTEL_82451NX	0x84ca
+#define PCI_DEVICE_ID_INTEL_82454NX	0x84cb
+
+#define PCI_VENDOR_ID_COMPUTONE		0x8e0e
+#define PCI_DEVICE_ID_COMPUTONE_IP2EX	0x0291
+#define PCI_DEVICE_ID_COMPUTONE_PG	0x0302
+#define PCI_SUBVENDOR_ID_COMPUTONE	0x8e0e
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG4	0x0001
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG8	0x0002
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG6	0x0003
+
+#define PCI_VENDOR_ID_KTI		0x8e2e
+#define PCI_DEVICE_ID_KTI_ET32P2	0x3000
+
+#define PCI_VENDOR_ID_ADAPTEC		0x9004
+#define PCI_DEVICE_ID_ADAPTEC_7810	0x1078
+#define PCI_DEVICE_ID_ADAPTEC_7821	0x2178
+#define PCI_DEVICE_ID_ADAPTEC_38602	0x3860
+#define PCI_DEVICE_ID_ADAPTEC_7850	0x5078
+#define PCI_DEVICE_ID_ADAPTEC_7855	0x5578
+#define PCI_DEVICE_ID_ADAPTEC_5800	0x5800
+#define PCI_DEVICE_ID_ADAPTEC_3860	0x6038
+#define PCI_DEVICE_ID_ADAPTEC_1480A	0x6075
+#define PCI_DEVICE_ID_ADAPTEC_7860	0x6078
+#define PCI_DEVICE_ID_ADAPTEC_7861	0x6178
+#define PCI_DEVICE_ID_ADAPTEC_7870	0x7078
+#define PCI_DEVICE_ID_ADAPTEC_7871	0x7178
+#define PCI_DEVICE_ID_ADAPTEC_7872	0x7278
+#define PCI_DEVICE_ID_ADAPTEC_7873	0x7378
+#define PCI_DEVICE_ID_ADAPTEC_7874	0x7478
+#define PCI_DEVICE_ID_ADAPTEC_7895	0x7895
+#define PCI_DEVICE_ID_ADAPTEC_7880	0x8078
+#define PCI_DEVICE_ID_ADAPTEC_7881	0x8178
+#define PCI_DEVICE_ID_ADAPTEC_7882	0x8278
+#define PCI_DEVICE_ID_ADAPTEC_7883	0x8378
+#define PCI_DEVICE_ID_ADAPTEC_7884	0x8478
+#define PCI_DEVICE_ID_ADAPTEC_7885	0x8578
+#define PCI_DEVICE_ID_ADAPTEC_7886	0x8678
+#define PCI_DEVICE_ID_ADAPTEC_7887	0x8778
+#define PCI_DEVICE_ID_ADAPTEC_7888	0x8878
+#define PCI_DEVICE_ID_ADAPTEC_1030	0x8b78
+
+#define PCI_VENDOR_ID_ADAPTEC2		0x9005
+#define PCI_DEVICE_ID_ADAPTEC2_2940U2	0x0010
+#define PCI_DEVICE_ID_ADAPTEC2_2930U2	0x0011
+#define PCI_DEVICE_ID_ADAPTEC2_7890B	0x0013
+#define PCI_DEVICE_ID_ADAPTEC2_7890	0x001f
+#define PCI_DEVICE_ID_ADAPTEC2_3940U2	0x0050
+#define PCI_DEVICE_ID_ADAPTEC2_3950U2D	0x0051
+#define PCI_DEVICE_ID_ADAPTEC2_7896	0x005f
+#define PCI_DEVICE_ID_ADAPTEC2_7892A	0x0080
+#define PCI_DEVICE_ID_ADAPTEC2_7892B	0x0081
+#define PCI_DEVICE_ID_ADAPTEC2_7892D	0x0083
+#define PCI_DEVICE_ID_ADAPTEC2_7892P	0x008f
+#define PCI_DEVICE_ID_ADAPTEC2_7899A	0x00c0
+#define PCI_DEVICE_ID_ADAPTEC2_7899B	0x00c1
+#define PCI_DEVICE_ID_ADAPTEC2_7899D	0x00c3
+#define PCI_DEVICE_ID_ADAPTEC2_7899P	0x00cf
+
+#define PCI_VENDOR_ID_ATRONICS		0x907f
+#define PCI_DEVICE_ID_ATRONICS_2015	0x2015
+
+#define PCI_VENDOR_ID_HOLTEK		0x9412
+#define PCI_DEVICE_ID_HOLTEK_6565	0x6565
+
+#define PCI_VENDOR_ID_NETMOS		0x9710
+#define PCI_DEVICE_ID_NETMOS_9735	0x9735
+#define PCI_DEVICE_ID_NETMOS_9835	0x9835
+
+#define PCI_SUBVENDOR_ID_EXSYS		0xd84d
+#define PCI_SUBDEVICE_ID_EXSYS_4014	0x4014
+#define PCI_SUBDEVICE_ID_EXSYS_4055	0x4055
+
+#define PCI_VENDOR_ID_TIGERJET		0xe159
+#define PCI_DEVICE_ID_TIGERJET_300	0x0001
+#define PCI_DEVICE_ID_TIGERJET_100	0x0002
+
+#define PCI_VENDOR_ID_ARK		0xedd8
+#define PCI_DEVICE_ID_ARK_STING		0xa091
+#define PCI_DEVICE_ID_ARK_STINGARK	0xa099
+#define PCI_DEVICE_ID_ARK_2000MT	0xa0a1
+
+#define PCI_VENDOR_ID_MICROGATE		0x13c0
+#define PCI_DEVICE_ID_MICROGATE_USC	0x0010
+#define PCI_DEVICE_ID_MICROGATE_SCC	0x0020
+#define PCI_DEVICE_ID_MICROGATE_SCA	0x0030
diff --git a/include/pcmcia.h b/include/pcmcia.h
new file mode 100755
index 0000000..43d4510
--- /dev/null
+++ b/include/pcmcia.h
@@ -0,0 +1,311 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PCMCIA_H
+#define _PCMCIA_H
+
+#include <common.h>
+#include <config.h>
+
+/*
+ * Allow configuration to select PCMCIA slot,
+ * or try to generate a useful default
+ */
+#if ( CONFIG_COMMANDS & CFG_CMD_PCMCIA) || \
+    ((CONFIG_COMMANDS & CFG_CMD_IDE) && \
+	(defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
+
+#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
+
+					/* The RPX series use SLOT_B	*/
+#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
+# define CONFIG_PCMCIA_SLOT_B
+#elif defined(CONFIG_ADS)		/* The ADS  board uses SLOT_A	*/
+# define CONFIG_PCMCIA_SLOT_A
+#elif defined(CONFIG_FADS)		/* The FADS series are a mess	*/
+# if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821)
+#  define CONFIG_PCMCIA_SLOT_A
+# else
+#  define CONFIG_PCMCIA_SLOT_B
+# endif
+#elif defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)
+# define	CONFIG_PCMCIA_SLOT_B	/* The TQM8xxL use SLOT_B	*/
+#elif defined(CONFIG_SPD823TS)		/* The SPD8xx  use SLOT_B	*/
+# define CONFIG_PCMCIA_SLOT_B
+#elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)	/* The IVM* use SLOT_A	*/
+# define CONFIG_PCMCIA_SLOT_A
+#elif defined(CONFIG_LWMON)		/* The LWMON  use SLOT_B	*/
+# define CONFIG_PCMCIA_SLOT_B
+#elif defined(CONFIG_ICU862)		/* The ICU862 use SLOT_B	*/
+# define CONFIG_PCMCIA_SLOT_B
+#elif defined(CONFIG_C2MON)		/* The C2MON  use SLOT_B	*/
+# define CONFIG_PCMCIA_SLOT_B
+#elif defined(CONFIG_R360MPI)		/* The R360MPI use SLOT_B	*/
+# define CONFIG_PCMCIA_SLOT_B
+#elif defined(CONFIG_ATC)		/* The ATC use SLOT_A	*/
+# define CONFIG_PCMCIA_SLOT_A
+#elif defined(CONFIG_NETTA)
+# define CONFIG_PCMCIA_SLOT_A
+#elif defined(CONFIG_UC100)		/* The UC100 use SLOT_B	        */
+# define CONFIG_PCMCIA_SLOT_B
+#else
+# error "PCMCIA Slot not configured"
+#endif
+
+#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
+
+/* Make sure exactly one slot is defined - we support only one for now */
+#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
+#error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
+#endif
+#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
+#error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
+#endif
+
+#ifndef PCMCIA_SOCKETS_NO
+#define PCMCIA_SOCKETS_NO	1
+#endif
+#ifndef PCMCIA_MEM_WIN_NO
+#define PCMCIA_MEM_WIN_NO	4
+#endif
+#define PCMCIA_IO_WIN_NO	2
+
+/* define _slot_ to be able to optimize macros */
+#ifdef CONFIG_PCMCIA_SLOT_A
+# define _slot_			0
+# define PCMCIA_SLOT_MSG	"slot A"
+# define PCMCIA_SLOT_x		PCMCIA_PSLOT_A
+#else
+# define _slot_			1
+# define PCMCIA_SLOT_MSG	"slot B"
+# define PCMCIA_SLOT_x		PCMCIA_PSLOT_B
+#endif
+
+/*
+ * The TQM850L hardware has two pins swapped! Grrrrgh!
+ */
+#ifdef	CONFIG_TQM850L
+#define __MY_PCMCIA_GCRX_CXRESET	PCMCIA_GCRX_CXOE
+#define __MY_PCMCIA_GCRX_CXOE		PCMCIA_GCRX_CXRESET
+#else
+#define __MY_PCMCIA_GCRX_CXRESET	PCMCIA_GCRX_CXRESET
+#define __MY_PCMCIA_GCRX_CXOE		PCMCIA_GCRX_CXOE
+#endif
+
+/*
+ * This structure is used to address each window in the PCMCIA controller.
+ *
+ * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
+ * after pcmcia_win_t[n]...
+ */
+
+typedef struct {
+	ulong	br;
+	ulong	or;
+} pcmcia_win_t;
+
+/*
+ * Definitions for PCMCIA control registers to operate in IDE mode
+ *
+ * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
+ * to be done later (depending on CPU clock)
+ */
+
+/* Window 0:
+ *	Base: 0xFE100000	CS1
+ *	Port Size:     2 Bytes
+ *	Port Size:    16 Bit
+ *	Common Memory Space
+ */
+
+#define CFG_PCMCIA_PBR0		0xFE100000
+#define CFG_PCMCIA_POR0	    (	PCMCIA_BSIZE_2	\
+			    |	PCMCIA_PPS_16	\
+			    |	PCMCIA_PRS_MEM	\
+			    |	PCMCIA_SLOT_x	\
+			    |	PCMCIA_PV	\
+			    )
+
+/* Window 1:
+ *	Base: 0xFE100080	CS1
+ *	Port Size:     8 Bytes
+ *	Port Size:     8 Bit
+ *	Common Memory Space
+ */
+
+#define CFG_PCMCIA_PBR1		0xFE100080
+#define CFG_PCMCIA_POR1	    (	PCMCIA_BSIZE_8	\
+			    |	PCMCIA_PPS_8	\
+			    |	PCMCIA_PRS_MEM	\
+			    |	PCMCIA_SLOT_x	\
+			    |	PCMCIA_PV	\
+			    )
+
+/* Window 2:
+ *	Base: 0xFE100100	CS2
+ *	Port Size:     8 Bytes
+ *	Port Size:     8 Bit
+ *	Common Memory Space
+ */
+
+#define CFG_PCMCIA_PBR2		0xFE100100
+#define CFG_PCMCIA_POR2	    (	PCMCIA_BSIZE_8	\
+			    |	PCMCIA_PPS_8	\
+			    |	PCMCIA_PRS_MEM	\
+			    |	PCMCIA_SLOT_x	\
+			    |	PCMCIA_PV	\
+			    )
+
+/* Window 3:
+ *	not used
+ */
+#define CFG_PCMCIA_PBR3		0
+#define CFG_PCMCIA_POR3		0
+
+/* Window 4:
+ *	Base: 0xFE100C00	CS1
+ *	Port Size:     2 Bytes
+ *	Port Size:    16 Bit
+ *	Common Memory Space
+ */
+
+#define CFG_PCMCIA_PBR4		0xFE100C00
+#define CFG_PCMCIA_POR4	    (	PCMCIA_BSIZE_2	\
+			    |	PCMCIA_PPS_16	\
+			    |	PCMCIA_PRS_MEM	\
+			    |	PCMCIA_SLOT_x	\
+			    |	PCMCIA_PV	\
+			    )
+
+/* Window 5:
+ *	Base: 0xFE100C80	CS1
+ *	Port Size:     8 Bytes
+ *	Port Size:     8 Bit
+ *	Common Memory Space
+ */
+
+#define CFG_PCMCIA_PBR5		0xFE100C80
+#define CFG_PCMCIA_POR5	    (	PCMCIA_BSIZE_8	\
+			    |	PCMCIA_PPS_8	\
+			    |	PCMCIA_PRS_MEM	\
+			    |	PCMCIA_SLOT_x	\
+			    |	PCMCIA_PV	\
+			    )
+
+/* Window 6:
+ *	Base: 0xFE100D00	CS2
+ *	Port Size:     8 Bytes
+ *	Port Size:     8 Bit
+ *	Common Memory Space
+ */
+
+#define CFG_PCMCIA_PBR6		0xFE100D00
+#define CFG_PCMCIA_POR6	    (	PCMCIA_BSIZE_8	\
+			    |	PCMCIA_PPS_8	\
+			    |	PCMCIA_PRS_MEM	\
+			    |	PCMCIA_SLOT_x	\
+			    |	PCMCIA_PV	\
+			    )
+
+/* Window 7:
+ *	not used
+ */
+#define CFG_PCMCIA_PBR7		0
+#define CFG_PCMCIA_POR7		0
+
+/**********************************************************************/
+
+/*
+ * CIS Tupel codes
+ */
+#define CISTPL_NULL		0x00
+#define CISTPL_DEVICE		0x01
+#define CISTPL_LONGLINK_CB	0x02
+#define CISTPL_INDIRECT		0x03
+#define CISTPL_CONFIG_CB	0x04
+#define CISTPL_CFTABLE_ENTRY_CB 0x05
+#define CISTPL_LONGLINK_MFC	0x06
+#define CISTPL_BAR		0x07
+#define CISTPL_PWR_MGMNT	0x08
+#define CISTPL_EXTDEVICE	0x09
+#define CISTPL_CHECKSUM		0x10
+#define CISTPL_LONGLINK_A	0x11
+#define CISTPL_LONGLINK_C	0x12
+#define CISTPL_LINKTARGET	0x13
+#define CISTPL_NO_LINK		0x14
+#define CISTPL_VERS_1		0x15
+#define CISTPL_ALTSTR		0x16
+#define CISTPL_DEVICE_A		0x17
+#define CISTPL_JEDEC_C		0x18
+#define CISTPL_JEDEC_A		0x19
+#define CISTPL_CONFIG		0x1a
+#define CISTPL_CFTABLE_ENTRY	0x1b
+#define CISTPL_DEVICE_OC	0x1c
+#define CISTPL_DEVICE_OA	0x1d
+#define CISTPL_DEVICE_GEO	0x1e
+#define CISTPL_DEVICE_GEO_A	0x1f
+#define CISTPL_MANFID		0x20
+#define CISTPL_FUNCID		0x21
+#define CISTPL_FUNCE		0x22
+#define CISTPL_SWIL		0x23
+#define CISTPL_END		0xff
+
+/*
+ * CIS Function ID codes
+ */
+#define CISTPL_FUNCID_MULTI	0x00
+#define CISTPL_FUNCID_MEMORY	0x01
+#define CISTPL_FUNCID_SERIAL	0x02
+#define CISTPL_FUNCID_PARALLEL	0x03
+#define CISTPL_FUNCID_FIXED	0x04
+#define CISTPL_FUNCID_VIDEO	0x05
+#define CISTPL_FUNCID_NETWORK	0x06
+#define CISTPL_FUNCID_AIMS	0x07
+#define CISTPL_FUNCID_SCSI	0x08
+
+/*
+ * Fixed Disk FUNCE codes
+ */
+#define CISTPL_IDE_INTERFACE	0x01
+
+#define CISTPL_FUNCE_IDE_IFACE	0x01
+#define CISTPL_FUNCE_IDE_MASTER	0x02
+#define CISTPL_FUNCE_IDE_SLAVE	0x03
+
+/* First feature byte */
+#define CISTPL_IDE_SILICON	0x04
+#define CISTPL_IDE_UNIQUE	0x08
+#define CISTPL_IDE_DUAL		0x10
+
+/* Second feature byte */
+#define CISTPL_IDE_HAS_SLEEP	0x01
+#define CISTPL_IDE_HAS_STANDBY	0x02
+#define CISTPL_IDE_HAS_IDLE	0x04
+#define CISTPL_IDE_LOW_POWER	0x08
+#define CISTPL_IDE_REG_INHIBIT	0x10
+#define CISTPL_IDE_HAS_INDEX	0x20
+#define CISTPL_IDE_IOIS16	0x40
+
+#endif	/* CFG_CMD_PCMCIA || CFG_CMD_IDE && (CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT) */
+
+#endif /* _PCMCIA_H */
diff --git a/include/pcmcia/cirrus.h b/include/pcmcia/cirrus.h
new file mode 100755
index 0000000..cd34dd8
--- /dev/null
+++ b/include/pcmcia/cirrus.h
@@ -0,0 +1,180 @@
+/*
+ * cirrus.h 1.4 1999/10/25 20:03:34
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License.
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in which
+ * case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_CIRRUS_H
+#define _LINUX_CIRRUS_H
+
+#ifndef PCI_VENDOR_ID_CIRRUS
+#define PCI_VENDOR_ID_CIRRUS		0x1013
+#endif
+#ifndef PCI_DEVICE_ID_CIRRUS_6729
+#define PCI_DEVICE_ID_CIRRUS_6729	0x1100
+#endif
+#ifndef PCI_DEVICE_ID_CIRRUS_6832
+#define PCI_DEVICE_ID_CIRRUS_6832	0x1110
+#endif
+
+#define PD67_MISC_CTL_1		0x16	/* Misc control 1 */
+#define PD67_FIFO_CTL		0x17	/* FIFO control */
+#define PD67_MISC_CTL_2		0x1E	/* Misc control 2 */
+#define PD67_CHIP_INFO		0x1f	/* Chip information */
+#define PD67_ATA_CTL		0x026	/* 6730: ATA control */
+#define PD67_EXT_INDEX		0x2e	/* Extension index */
+#define PD67_EXT_DATA		0x2f	/* Extension data */
+
+/* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
+#define PD67_DATA_MASK0		0x01	/* Data mask 0 */
+#define PD67_DATA_MASK1		0x02	/* Data mask 1 */
+#define PD67_DMA_CTL		0x03	/* DMA control */
+
+/* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
+#define PD67_EXT_CTL_1		0x03	/* Extension control 1 */
+#define PD67_MEM_PAGE(n)	((n)+5)	/* PCI window bits 31:24 */
+#define PD67_EXTERN_DATA	0x0a
+#define PD67_MISC_CTL_3		0x25
+#define PD67_SMB_PWR_CTL	0x26
+
+/* I/O window address offset */
+#define PD67_IO_OFF(w)		(0x36+((w)<<1))
+
+/* Timing register sets */
+#define PD67_TIME_SETUP(n)	(0x3a + 3*(n))
+#define PD67_TIME_CMD(n)	(0x3b + 3*(n))
+#define PD67_TIME_RECOV(n)	(0x3c + 3*(n))
+
+/* Flags for PD67_MISC_CTL_1 */
+#define PD67_MC1_5V_DET		0x01	/* 5v detect */
+#define PD67_MC1_MEDIA_ENA	0x01	/* 6730: Multimedia enable */
+#define PD67_MC1_VCC_3V		0x02	/* 3.3v Vcc */
+#define PD67_MC1_PULSE_MGMT	0x04
+#define PD67_MC1_PULSE_IRQ	0x08
+#define PD67_MC1_SPKR_ENA	0x10
+#define PD67_MC1_INPACK_ENA	0x80
+
+/* Flags for PD67_FIFO_CTL */
+#define PD67_FIFO_EMPTY		0x80
+
+/* Flags for PD67_MISC_CTL_2 */
+#define PD67_MC2_FREQ_BYPASS	0x01
+#define PD67_MC2_DYNAMIC_MODE	0x02
+#define PD67_MC2_SUSPEND	0x04
+#define PD67_MC2_5V_CORE	0x08
+#define PD67_MC2_LED_ENA	0x10	/* IRQ 12 is LED enable */
+#define PD67_MC2_FAST_PCI	0x10	/* 6729: PCI bus > 25 MHz */
+#define PD67_MC2_3STATE_BIT7	0x20	/* Floppy change bit */
+#define PD67_MC2_DMA_MODE	0x40
+#define PD67_MC2_IRQ15_RI	0x80	/* IRQ 15 is ring enable */
+
+/* Flags for PD67_CHIP_INFO */
+#define PD67_INFO_SLOTS		0x20	/* 0 = 1 slot, 1 = 2 slots */
+#define PD67_INFO_CHIP_ID	0xc0
+#define PD67_INFO_REV		0x1c
+
+/* Fields in PD67_TIME_* registers */
+#define PD67_TIME_SCALE		0xc0
+#define PD67_TIME_SCALE_1	0x00
+#define PD67_TIME_SCALE_16	0x40
+#define PD67_TIME_SCALE_256	0x80
+#define PD67_TIME_SCALE_4096	0xc0
+#define PD67_TIME_MULT		0x3f
+
+/* Fields in PD67_DMA_CTL */
+#define PD67_DMA_MODE		0xc0
+#define PD67_DMA_OFF		0x00
+#define PD67_DMA_DREQ_INPACK	0x40
+#define PD67_DMA_DREQ_WP	0x80
+#define PD67_DMA_DREQ_BVD2	0xc0
+#define PD67_DMA_PULLUP		0x20	/* Disable socket pullups? */
+
+/* Fields in PD67_EXT_CTL_1 */
+#define PD67_EC1_VCC_PWR_LOCK	0x01
+#define PD67_EC1_AUTO_PWR_CLEAR	0x02
+#define PD67_EC1_LED_ENA	0x04
+#define PD67_EC1_INV_CARD_IRQ	0x08
+#define PD67_EC1_INV_MGMT_IRQ	0x10
+#define PD67_EC1_PULLUP_CTL	0x20
+
+/* Fields in PD67_MISC_CTL_3 */
+#define PD67_MC3_IRQ_MASK	0x03
+#define PD67_MC3_IRQ_PCPCI	0x00
+#define PD67_MC3_IRQ_EXTERN	0x01
+#define PD67_MC3_IRQ_PCIWAY	0x02
+#define PD67_MC3_IRQ_PCI	0x03
+#define PD67_MC3_PWR_MASK	0x0c
+#define PD67_MC3_PWR_SERIAL	0x00
+#define PD67_MC3_PWR_TI2202	0x08
+#define PD67_MC3_PWR_SMB	0x0c
+
+/* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
+
+/* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
+#define PD68_EXT_CTL_2			0x0b
+#define PD68_PCI_SPACE			0x22
+#define PD68_PCCARD_SPACE		0x23
+#define PD68_WINDOW_TYPE		0x24
+#define PD68_EXT_CSC			0x2e
+#define PD68_MISC_CTL_4			0x2f
+#define PD68_MISC_CTL_5			0x30
+#define PD68_MISC_CTL_6			0x31
+
+/* Extra flags in PD67_MISC_CTL_3 */
+#define PD68_MC3_HW_SUSP		0x10
+#define PD68_MC3_MM_EXPAND		0x40
+#define PD68_MC3_MM_ARM			0x80
+
+/* Bridge Control Register */
+#define  PD6832_BCR_MGMT_IRQ_ENA	0x0800
+
+/* Socket Number Register */
+#define PD6832_SOCKET_NUMBER		0x004c	/* 8 bit */
+
+
+typedef struct cirrus_state_t {
+    u_char		misc1, misc2;
+    u_char		timer[6];
+} cirrus_state_t;
+
+/* Cirrus options */
+static int has_dma = -1;
+static int has_led = -1;
+static int has_ring = -1;
+static int dynamic_mode = 0;
+static int freq_bypass = -1;
+#ifdef CONFIG_CPC45
+static int setup_time = 2;
+static int cmd_time = 6;
+static int recov_time = 1;
+#else
+static int setup_time = -1;
+static int cmd_time = -1;
+static int recov_time = -1;
+#endif
+
+
+#endif /* _LINUX_CIRRUS_H */
diff --git a/include/pcmcia/i82365.h b/include/pcmcia/i82365.h
new file mode 100755
index 0000000..0b432a8
--- /dev/null
+++ b/include/pcmcia/i82365.h
@@ -0,0 +1,154 @@
+/*
+ * i82365.h 1.21 2001/08/24 12:15:33
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License.
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_I82365_H
+#define _LINUX_I82365_H
+
+/* register definitions for the Intel 82365SL PCMCIA controller */
+
+/* Offsets for PCIC registers */
+#define I365_IDENT	0x00	/* Identification and revision */
+#define I365_STATUS	0x01	/* Interface status */
+#define I365_POWER	0x02	/* Power and RESETDRV control */
+#define I365_INTCTL	0x03	/* Interrupt and general control */
+#define I365_CSC	0x04	/* Card status change */
+#define I365_CSCINT	0x05	/* Card status change interrupt control */
+#define I365_ADDRWIN	0x06	/* Address window enable */
+#define I365_IOCTL	0x07	/* I/O control */
+#define I365_GENCTL	0x16	/* Card detect and general control */
+#define I365_GBLCTL	0x1E	/* Global control register */
+
+/* Offsets for I/O and memory window registers */
+#define I365_IO(map)	(0x08+((map)<<2))
+#define I365_MEM(map)	(0x10+((map)<<3))
+#define I365_W_START	0
+#define I365_W_STOP	2
+#define I365_W_OFF	4
+
+/* Flags for I365_STATUS */
+#define I365_CS_BVD1	0x01
+#define I365_CS_STSCHG	0x01
+#define I365_CS_BVD2	0x02
+#define I365_CS_SPKR	0x02
+#define I365_CS_DETECT	0x0C
+#define I365_CS_WRPROT	0x10
+#define I365_CS_READY	0x20	/* Inverted */
+#define I365_CS_POWERON	0x40
+#define I365_CS_GPI	0x80
+
+/* Flags for I365_POWER */
+#define I365_PWR_OFF	0x00	/* Turn off the socket */
+#define I365_PWR_OUT	0x80	/* Output enable */
+#define I365_PWR_NORESET 0x40	/* Disable RESETDRV on resume */
+#define I365_PWR_AUTO	0x20	/* Auto pwr switch enable */
+#define I365_VCC_MASK	0x18	/* Mask for turning off Vcc */
+/* There are different layouts for B-step and DF-step chips: the B
+   step has independent Vpp1/Vpp2 control, and the DF step has only
+   Vpp1 control, plus 3V control */
+#define I365_VCC_5V	0x10	/* Vcc = 5.0v */
+#define I365_VCC_3V	0x18	/* Vcc = 3.3v */
+#define I365_VPP2_MASK	0x0c	/* Mask for turning off Vpp2 */
+#define I365_VPP2_5V	0x04	/* Vpp2 = 5.0v */
+#define I365_VPP2_12V	0x08	/* Vpp2 = 12.0v */
+#define I365_VPP1_MASK	0x03	/* Mask for turning off Vpp1 */
+#define I365_VPP1_5V	0x01	/* Vpp2 = 5.0v */
+#define I365_VPP1_12V	0x02	/* Vpp2 = 12.0v */
+
+/* Flags for I365_INTCTL */
+#define I365_RING_ENA	0x80
+#define I365_PC_RESET	0x40
+#define I365_PC_IOCARD	0x20
+#define I365_INTR_ENA	0x10
+#define I365_IRQ_MASK	0x0F
+
+/* Flags for I365_CSC and I365_CSCINT*/
+#define I365_CSC_BVD1	0x01
+#define I365_CSC_STSCHG	0x01
+#define I365_CSC_BVD2	0x02
+#define I365_CSC_READY	0x04
+#define I365_CSC_DETECT	0x08
+#define I365_CSC_ANY	0x0F
+#define I365_CSC_GPI	0x10
+
+/* Flags for I365_ADDRWIN */
+#define I365_ADDR_MEMCS16	0x20
+#define I365_ENA_IO(map)	(0x40 << (map))
+#define I365_ENA_MEM(map)	(0x01 << (map))
+
+/* Flags for I365_IOCTL */
+#define I365_IOCTL_MASK(map)	(0x0F << (map<<2))
+#define I365_IOCTL_WAIT(map)	(0x08 << (map<<2))
+#define I365_IOCTL_0WS(map)	(0x04 << (map<<2))
+#define I365_IOCTL_IOCS16(map)	(0x02 << (map<<2))
+#define I365_IOCTL_16BIT(map)	(0x01 << (map<<2))
+
+/* Flags for I365_GENCTL */
+#define I365_CTL_16DELAY	0x01
+#define I365_CTL_RESET		0x02
+#define I365_CTL_GPI_ENA	0x04
+#define I365_CTL_GPI_CTL	0x08
+#define I365_CTL_RESUME		0x10
+#define I365_CTL_SW_IRQ		0x20
+
+/* Flags for I365_GBLCTL */
+#define I365_GBL_PWRDOWN	0x01
+#define I365_GBL_CSC_LEV	0x02
+#define I365_GBL_WRBACK		0x04
+#define I365_GBL_IRQ_0_LEV	0x08
+#define I365_GBL_IRQ_1_LEV	0x10
+
+/* Flags for memory window registers */
+#define I365_MEM_16BIT	0x8000	/* In memory start high byte */
+#define I365_MEM_0WS	0x4000
+#define I365_MEM_WS1	0x8000	/* In memory stop high byte */
+#define I365_MEM_WS0	0x4000
+#define I365_MEM_WRPROT	0x8000	/* In offset high byte */
+#define I365_MEM_REG	0x4000
+
+#define I365_REG(slot, reg)	(((slot) << 6) | (reg))
+
+/* Default ISA interrupt mask */
+#define I365_ISA_IRQ_MASK	0xdeb8	/* irq's 3-5,7,9-12,14,15 */
+
+/* Device ID's for PCI-to-PCMCIA bridges */
+
+#ifndef PCI_VENDOR_ID_INTEL
+#define PCI_VENDOR_ID_INTEL		0x8086
+#endif
+#ifndef PCI_DEVICE_ID_INTEL_82092AA_0
+#define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
+#endif
+#ifndef PCI_VENDOR_ID_OMEGA
+#define PCI_VENDOR_ID_OMEGA		0x119b
+#endif
+#ifndef PCI_DEVICE_ID_OMEGA_82C092G
+#define PCI_DEVICE_ID_OMEGA_82C092G	0x1221
+#endif
+
+#endif /* _LINUX_I82365_H */
diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h
new file mode 100755
index 0000000..aafae8a
--- /dev/null
+++ b/include/pcmcia/ss.h
@@ -0,0 +1,133 @@
+/*
+ * ss.h 1.31 2001/08/24 12:16:13
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License.
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_SS_H
+#define _LINUX_SS_H
+
+/* For RegisterCallback */
+typedef struct ss_callback_t {
+    void	(*handler)(void *info, u_int events);
+    void	*info;
+} ss_callback_t;
+
+/* Definitions for card status flags for GetStatus */
+#define SS_WRPROT	0x0001
+#define SS_CARDLOCK	0x0002
+#define SS_EJECTION	0x0004
+#define SS_INSERTION	0x0008
+#define SS_BATDEAD	0x0010
+#define SS_BATWARN	0x0020
+#define SS_READY	0x0040
+#define SS_DETECT	0x0080
+#define SS_POWERON	0x0100
+#define SS_GPI		0x0200
+#define SS_STSCHG	0x0400
+#define SS_CARDBUS	0x0800
+#define SS_3VCARD	0x1000
+#define SS_XVCARD	0x2000
+#define SS_PENDING	0x4000
+
+/* for InquireSocket */
+typedef struct socket_cap_t {
+    u_int	features;
+    u_int	irq_mask;
+    u_int	map_size;
+    u_char	pci_irq;
+    u_char	cardbus;
+    struct pci_bus *cb_bus;
+    struct bus_operations *bus;
+} socket_cap_t;
+
+/* InquireSocket capabilities */
+#define SS_CAP_PAGE_REGS	0x0001
+#define SS_CAP_VIRTUAL_BUS	0x0002
+#define SS_CAP_MEM_ALIGN	0x0004
+#define SS_CAP_STATIC_MAP	0x0008
+#define SS_CAP_PCCARD		0x4000
+#define SS_CAP_CARDBUS		0x8000
+
+/* for GetSocket, SetSocket */
+typedef struct socket_state_t {
+    u_int	flags;
+    u_int	csc_mask;
+    u_char	Vcc, Vpp;
+    u_char	io_irq;
+} socket_state_t;
+
+/* Socket configuration flags */
+#define SS_PWR_AUTO	0x0010
+#define SS_IOCARD	0x0020
+#define SS_RESET	0x0040
+#define SS_DMA_MODE	0x0080
+#define SS_SPKR_ENA	0x0100
+#define SS_OUTPUT_ENA	0x0200
+#define SS_ZVCARD	0x0400
+
+/* Flags for I/O port and memory windows */
+#define MAP_ACTIVE	0x01
+#define MAP_16BIT	0x02
+#define MAP_AUTOSZ	0x04
+#define MAP_0WS		0x08
+#define MAP_WRPROT	0x10
+#define MAP_ATTRIB	0x20
+#define MAP_USE_WAIT	0x40
+#define MAP_PREFETCH	0x80
+
+/* Use this just for bridge windows */
+#define MAP_IOSPACE	0x20
+
+typedef struct pccard_io_map {
+    u_char	map;
+    u_char	flags;
+    u_short	speed;
+    u_short	start, stop;
+} pccard_io_map;
+
+typedef struct pccard_mem_map {
+    u_char	map;
+    u_char	flags;
+    u_short	speed;
+    u_long	sys_start, sys_stop;
+    u_int	card_start;
+} pccard_mem_map;
+
+typedef struct cb_bridge_map {
+    u_char	map;
+    u_char	flags;
+    u_int	start, stop;
+} cb_bridge_map;
+
+enum ss_service {
+    SS_RegisterCallback, SS_InquireSocket,
+    SS_GetStatus, SS_GetSocket, SS_SetSocket,
+    SS_GetIOMap, SS_SetIOMap, SS_GetMemMap, SS_SetMemMap,
+    SS_GetBridge, SS_SetBridge, SS_ProcSetup
+};
+
+#endif /* _LINUX_SS_H */
diff --git a/include/pcmcia/ti113x.h b/include/pcmcia/ti113x.h
new file mode 100755
index 0000000..5453588
--- /dev/null
+++ b/include/pcmcia/ti113x.h
@@ -0,0 +1,234 @@
+/*
+ * ti113x.h 1.31 2002/05/12 18:19:47
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License.
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_TI113X_H
+#define _LINUX_TI113X_H
+
+#ifndef PCI_VENDOR_ID_TI
+#define PCI_VENDOR_ID_TI		0x104c
+#endif
+
+#ifndef PCI_DEVICE_ID_TI_1130
+#define PCI_DEVICE_ID_TI_1130		0xac12
+#endif
+#ifndef PCI_DEVICE_ID_TI_1031
+#define PCI_DEVICE_ID_TI_1031		0xac13
+#endif
+#ifndef PCI_DEVICE_ID_TI_1131
+#define PCI_DEVICE_ID_TI_1131		0xac15
+#endif
+#ifndef PCI_DEVICE_ID_TI_1210
+#define PCI_DEVICE_ID_TI_1210		0xac1a
+#endif
+#ifndef PCI_DEVICE_ID_TI_1211
+#define PCI_DEVICE_ID_TI_1211		0xac1e
+#endif
+#ifndef PCI_DEVICE_ID_TI_1220
+#define PCI_DEVICE_ID_TI_1220		0xac17
+#endif
+#ifndef PCI_DEVICE_ID_TI_1221
+#define PCI_DEVICE_ID_TI_1221		0xac19
+#endif
+#ifndef PCI_DEVICE_ID_TI_1250A
+#define PCI_DEVICE_ID_TI_1250A		0xac16
+#endif
+#ifndef PCI_DEVICE_ID_TI_1225
+#define PCI_DEVICE_ID_TI_1225		0xac1c
+#endif
+#ifndef PCI_DEVICE_ID_TI_1251A
+#define PCI_DEVICE_ID_TI_1251A		0xac1d
+#endif
+#ifndef PCI_DEVICE_ID_TI_1251B
+#define PCI_DEVICE_ID_TI_1251B		0xac1f
+#endif
+#ifndef PCI_DEVICE_ID_TI_1410
+#define PCI_DEVICE_ID_TI_1410		0xac50
+#endif
+#ifndef PCI_DEVICE_ID_TI_1420
+#define PCI_DEVICE_ID_TI_1420		0xac51
+#endif
+#ifndef PCI_DEVICE_ID_TI_1450
+#define PCI_DEVICE_ID_TI_1450		0xac1b
+#endif
+#ifndef PCI_DEVICE_ID_TI_1451
+#define PCI_DEVICE_ID_TI_1451		0xac52
+#endif
+#ifndef PCI_DEVICE_ID_TI_1510
+#define PCI_DEVICE_ID_TI_1510		0xac56
+#endif
+#ifndef PCI_DEVICE_ID_TI_4410
+#define PCI_DEVICE_ID_TI_4410		0xac41
+#endif
+#ifndef PCI_DEVICE_ID_TI_4450
+#define PCI_DEVICE_ID_TI_4450		0xac40
+#endif
+#ifndef PCI_DEVICE_ID_TI_4451
+#define PCI_DEVICE_ID_TI_4451		0xac42
+#endif
+
+/* Register definitions for TI 113X PCI-to-CardBus bridges */
+
+/* System Control Register */
+#define TI113X_SYSTEM_CONTROL		0x80	/* 32 bit */
+#define  TI113X_SCR_SMIROUTE		0x04000000
+#define  TI113X_SCR_SMISTATUS		0x02000000
+#define  TI113X_SCR_SMIENB		0x01000000
+#define  TI113X_SCR_VCCPROT		0x00200000
+#define  TI113X_SCR_REDUCEZV		0x00100000
+#define  TI113X_SCR_CDREQEN		0x00080000
+#define  TI113X_SCR_CDMACHAN		0x00070000
+#define  TI113X_SCR_SOCACTIVE		0x00002000
+#define  TI113X_SCR_PWRSTREAM		0x00000800
+#define  TI113X_SCR_DELAYUP		0x00000400
+#define  TI113X_SCR_DELAYDOWN		0x00000200
+#define  TI113X_SCR_INTERROGATE		0x00000100
+#define  TI113X_SCR_CLKRUN_SEL		0x00000080
+#define  TI113X_SCR_PWRSAVINGS		0x00000040
+#define  TI113X_SCR_SUBSYSRW		0x00000020
+#define  TI113X_SCR_CB_DPAR		0x00000010
+#define  TI113X_SCR_CDMA_EN		0x00000008
+#define  TI113X_SCR_ASYNC_IRQ		0x00000004
+#define  TI113X_SCR_KEEPCLK		0x00000002
+#define  TI113X_SCR_CLKRUN_ENA		0x00000001
+
+#define  TI122X_SCR_SER_STEP		0xc0000000
+#define  TI122X_SCR_INTRTIE		0x20000000
+#define  TI122X_SCR_P2CCLK		0x08000000
+#define  TI122X_SCR_CBRSVD		0x00400000
+#define  TI122X_SCR_MRBURSTDN		0x00008000
+#define  TI122X_SCR_MRBURSTUP		0x00004000
+#define  TI122X_SCR_RIMUX		0x00000001
+
+/* Multimedia Control Register */
+#define TI1250_MULTIMEDIA_CTL		0x84	/* 8 bit */
+#define  TI1250_MMC_ZVOUTEN		0x80
+#define  TI1250_MMC_PORTSEL		0x40
+#define  TI1250_MMC_ZVEN1		0x02
+#define  TI1250_MMC_ZVEN0		0x01
+
+#define TI1250_GENERAL_STATUS		0x85	/* 8 bit */
+#define TI1250_GPIO0_CONTROL		0x88	/* 8 bit */
+#define TI1250_GPIO1_CONTROL		0x89	/* 8 bit */
+#define TI1250_GPIO2_CONTROL		0x8a	/* 8 bit */
+#define TI1250_GPIO3_CONTROL		0x8b	/* 8 bit */
+#define TI12XX_IRQMUX			0x8c	/* 32 bit */
+
+/* Retry Status Register */
+#define TI113X_RETRY_STATUS		0x90	/* 8 bit */
+#define  TI113X_RSR_PCIRETRY		0x80
+#define  TI113X_RSR_CBRETRY		0x40
+#define  TI113X_RSR_TEXP_CBB		0x20
+#define  TI113X_RSR_MEXP_CBB		0x10
+#define  TI113X_RSR_TEXP_CBA		0x08
+#define  TI113X_RSR_MEXP_CBA		0x04
+#define  TI113X_RSR_TEXP_PCI		0x02
+#define  TI113X_RSR_MEXP_PCI		0x01
+
+/* Card Control Register */
+#define TI113X_CARD_CONTROL		0x91	/* 8 bit */
+#define  TI113X_CCR_RIENB		0x80
+#define  TI113X_CCR_ZVENABLE		0x40
+#define  TI113X_CCR_PCI_IRQ_ENA		0x20
+#define  TI113X_CCR_PCI_IREQ		0x10
+#define  TI113X_CCR_PCI_CSC		0x08
+#define  TI113X_CCR_SPKROUTEN		0x02
+#define  TI113X_CCR_IFG			0x01
+
+#define  TI1220_CCR_PORT_SEL		0x20
+#define  TI122X_CCR_AUD2MUX		0x04
+
+/* Device Control Register */
+#define TI113X_DEVICE_CONTROL		0x92	/* 8 bit */
+#define  TI113X_DCR_5V_FORCE		0x40
+#define  TI113X_DCR_3V_FORCE		0x20
+#define  TI113X_DCR_IMODE_MASK		0x06
+#define  TI113X_DCR_IMODE_ISA		0x02
+#define  TI113X_DCR_IMODE_SERIAL	0x04
+
+#define  TI12XX_DCR_IMODE_PCI_ONLY	0x00
+#define  TI12XX_DCR_IMODE_ALL_SERIAL	0x06
+
+/* Buffer Control Register */
+#define TI113X_BUFFER_CONTROL		0x93	/* 8 bit */
+#define  TI113X_BCR_CB_READ_DEPTH	0x08
+#define  TI113X_BCR_CB_WRITE_DEPTH	0x04
+#define  TI113X_BCR_PCI_READ_DEPTH	0x02
+#define  TI113X_BCR_PCI_WRITE_DEPTH	0x01
+
+/* Diagnostic Register */
+#define TI1250_DIAGNOSTIC		0x93	/* 8 bit */
+#define  TI1250_DIAG_TRUE_VALUE		0x80
+#define  TI1250_DIAG_PCI_IREQ		0x40
+#define  TI1250_DIAG_PCI_CSC		0x20
+#define  TI1250_DIAG_ASYNC_CSC		0x01
+
+/* DMA Registers */
+#define TI113X_DMA_0			0x94	/* 32 bit */
+#define TI113X_DMA_1			0x98	/* 32 bit */
+
+/* ExCA IO offset registers */
+#define TI113X_IO_OFFSET(map)		(0x36+((map)<<1))
+
+/* Data structure for tracking vendor-specific state */
+typedef struct ti113x_state_t {
+    u32			sysctl;		/* TI113X_SYSTEM_CONTROL */
+    u8			cardctl;	/* TI113X_CARD_CONTROL */
+    u8			devctl;		/* TI113X_DEVICE_CONTROL */
+    u8			diag;		/* TI1250_DIAGNOSTIC */
+    u32			irqmux;		/* TI12XX_IRQMUX */
+} ti113x_state_t;
+
+#define TI_PCIC_ID \
+    IS_TI1130, IS_TI1131, IS_TI1031, IS_TI1210, IS_TI1211,	\
+    IS_TI1220, IS_TI1221, IS_TI1225, IS_TI1250A, IS_TI1251A,	\
+    IS_TI1251B, IS_TI1410, IS_TI1420, IS_TI1450, IS_TI1451,	\
+    IS_TI1510, IS_TI4410, IS_TI4450, IS_TI4451
+
+#define TI_PCIC_INFO \
+    { "TI 1130",  IS_TI|IS_CARDBUS, ID(TI, 1130) }, \
+    { "TI 1131",  IS_TI|IS_CARDBUS, ID(TI, 1131) }, \
+    { "TI 1031",  IS_TI|IS_CARDBUS, ID(TI, 1031) }, \
+    { "TI 1210",  IS_TI|IS_CARDBUS, ID(TI, 1210) }, \
+    { "TI 1211",  IS_TI|IS_CARDBUS, ID(TI, 1211) }, \
+    { "TI 1220",  IS_TI|IS_CARDBUS, ID(TI, 1220) }, \
+    { "TI 1221",  IS_TI|IS_CARDBUS, ID(TI, 1221) }, \
+    { "TI 1225",  IS_TI|IS_CARDBUS, ID(TI, 1225) }, \
+    { "TI 1250A", IS_TI|IS_CARDBUS, ID(TI, 1250A) }, \
+    { "TI 1251A", IS_TI|IS_CARDBUS, ID(TI, 1251A) }, \
+    { "TI 1251B", IS_TI|IS_CARDBUS, ID(TI, 1251B) }, \
+    { "TI 1410",  IS_TI|IS_CARDBUS, ID(TI, 1410) }, \
+    { "TI 1420",  IS_TI|IS_CARDBUS, ID(TI, 1420) }, \
+    { "TI 1450",  IS_TI|IS_CARDBUS, ID(TI, 1450) }, \
+    { "TI 1451",  IS_TI|IS_CARDBUS, ID(TI, 1451) }, \
+    { "TI 1510",  IS_TI|IS_CARDBUS, ID(TI, 1510) }, \
+    { "TI 4410",  IS_TI|IS_CARDBUS, ID(TI, 4410) }, \
+    { "TI 4450",  IS_TI|IS_CARDBUS, ID(TI, 4450) }, \
+    { "TI 4451",  IS_TI|IS_CARDBUS, ID(TI, 4451) }
+
+#endif /* _LINUX_TI113X_H */
diff --git a/include/pcmcia/yenta.h b/include/pcmcia/yenta.h
new file mode 100755
index 0000000..5cd58a7
--- /dev/null
+++ b/include/pcmcia/yenta.h
@@ -0,0 +1,156 @@
+/*
+ * yenta.h 1.20 2001/08/24 12:15:34
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License.
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_YENTA_H
+#define _LINUX_YENTA_H
+
+/* PCI Configuration Registers */
+
+#define PCI_STATUS_CAPLIST		0x10
+#define PCI_CB_CAPABILITY_POINTER	0x14	/* 8 bit */
+#define PCI_CAPABILITY_ID		0x00	/* 8 bit */
+#define  PCI_CAPABILITY_PM		0x01
+#define PCI_NEXT_CAPABILITY		0x01	/* 8 bit */
+#define PCI_PM_CAPABILITIES		0x02	/* 16 bit */
+#define  PCI_PMCAP_PME_D3COLD		0x8000
+#define  PCI_PMCAP_PME_D3HOT		0x4000
+#define  PCI_PMCAP_PME_D2		0x2000
+#define  PCI_PMCAP_PME_D1		0x1000
+#define  PCI_PMCAP_PME_D0		0x0800
+#define  PCI_PMCAP_D2_CAP		0x0400
+#define  PCI_PMCAP_D1_CAP		0x0200
+#define  PCI_PMCAP_DYN_DATA		0x0100
+#define  PCI_PMCAP_DSI			0x0020
+#define  PCI_PMCAP_AUX_PWR		0x0010
+#define  PCI_PMCAP_PMECLK		0x0008
+#define  PCI_PMCAP_VERSION_MASK		0x0007
+#define PCI_PM_CONTROL_STATUS		0x04	/* 16 bit */
+#define  PCI_PMCS_PME_STATUS		0x8000
+#define  PCI_PMCS_DATASCALE_MASK	0x6000
+#define  PCI_PMCS_DATASCALE_SHIFT	13
+#define  PCI_PMCS_DATASEL_MASK		0x1e00
+#define  PCI_PMCS_DATASEL_SHIFT		9
+#define  PCI_PMCS_PME_ENABLE		0x0100
+#define  PCI_PMCS_PWR_STATE_MASK	0x0003
+#define  PCI_PMCS_PWR_STATE_D0		0x0000
+#define  PCI_PMCS_PWR_STATE_D1		0x0001
+#define  PCI_PMCS_PWR_STATE_D2		0x0002
+#define  PCI_PMCS_PWR_STATE_D3		0x0003
+#define PCI_PM_BRIDGE_EXT		0x06	/* 8 bit */
+#define PCI_PM_DATA			0x07	/* 8 bit */
+
+#define CB_PRIMARY_BUS			0x18	/* 8 bit */
+#define CB_CARDBUS_BUS			0x19	/* 8 bit */
+#define CB_SUBORD_BUS			0x1a	/* 8 bit */
+#define CB_LATENCY_TIMER		0x1b	/* 8 bit */
+
+#define CB_MEM_BASE(m)			(0x1c + 8*(m))
+#define CB_MEM_LIMIT(m)			(0x20 + 8*(m))
+#define CB_IO_BASE(m)			(0x2c + 8*(m))
+#define CB_IO_LIMIT(m)			(0x30 + 8*(m))
+
+#define CB_BRIDGE_CONTROL		0x3e	/* 16 bit */
+#define  CB_BCR_PARITY_ENA		0x0001
+#define  CB_BCR_SERR_ENA		0x0002
+#define  CB_BCR_ISA_ENA			0x0004
+#define  CB_BCR_VGA_ENA			0x0008
+#define  CB_BCR_MABORT			0x0020
+#define  CB_BCR_CB_RESET		0x0040
+#define  CB_BCR_ISA_IRQ			0x0080
+#define  CB_BCR_PREFETCH(m)		(0x0100 << (m))
+#define  CB_BCR_WRITE_POST		0x0400
+
+#define CB_LEGACY_MODE_BASE		0x44
+
+/* Memory mapped registers */
+
+#define CB_SOCKET_EVENT			0x0000
+#define  CB_SE_CSTSCHG			0x00000001
+#define  CB_SE_CCD			0x00000006
+#define  CB_SE_CCD1			0x00000002
+#define  CB_SE_CCD2			0x00000004
+#define  CB_SE_PWRCYCLE			0x00000008
+
+#define CB_SOCKET_MASK			0x0004
+#define  CB_SM_CSTSCHG			0x00000001
+#define  CB_SM_CCD			0x00000006
+#define  CB_SM_PWRCYCLE			0x00000008
+
+#define CB_SOCKET_STATE			0x0008
+#define  CB_SS_CSTSCHG			0x00000001
+#define  CB_SS_CCD			0x00000006
+#define  CB_SS_CCD1			0x00000002
+#define  CB_SS_CCD2			0x00000004
+#define  CB_SS_PWRCYCLE			0x00000008
+#define  CB_SS_16BIT			0x00000010
+#define  CB_SS_32BIT			0x00000020
+#define  CB_SS_CINT			0x00000040
+#define  CB_SS_BADCARD			0x00000080
+#define  CB_SS_DATALOST			0x00000100
+#define  CB_SS_BADVCC			0x00000200
+#define  CB_SS_5VCARD			0x00000400
+#define  CB_SS_3VCARD			0x00000800
+#define  CB_SS_XVCARD			0x00001000
+#define  CB_SS_YVCARD			0x00002000
+#define  CB_SS_VSENSE			0x00003c86
+#define  CB_SS_5VSOCKET			0x10000000
+#define  CB_SS_3VSOCKET			0x20000000
+#define  CB_SS_XVSOCKET			0x40000000
+#define  CB_SS_YVSOCKET			0x80000000
+
+#define CB_SOCKET_FORCE			0x000c
+#define  CB_SF_CVSTEST			0x00004000
+
+#define CB_SOCKET_CONTROL		0x0010
+#define  CB_SC_VPP_MASK			0x00000007
+#define   CB_SC_VPP_OFF			0x00000000
+#define   CB_SC_VPP_12V			0x00000001
+#define   CB_SC_VPP_5V			0x00000002
+#define   CB_SC_VPP_3V			0x00000003
+#define   CB_SC_VPP_XV			0x00000004
+#define   CB_SC_VPP_YV			0x00000005
+#define  CB_SC_VCC_MASK			0x00000070
+#define   CB_SC_VCC_OFF			0x00000000
+#define   CB_SC_VCC_5V			0x00000020
+#define   CB_SC_VCC_3V			0x00000030
+#define   CB_SC_VCC_XV			0x00000040
+#define   CB_SC_VCC_YV			0x00000050
+#define  CB_SC_CCLK_STOP		0x00000080
+
+#define CB_SOCKET_POWER			0x0020
+#define  CB_SP_CLK_CTRL			0x00000001
+#define  CB_SP_CLK_CTRL_ENA		0x00010000
+#define  CB_SP_CLK_MODE			0x01000000
+#define  CB_SP_ACCESS			0x02000000
+
+/* Address bits 31..24 for memory windows for 16-bit cards,
+   accessable only by memory mapping the 16-bit register set */
+#define CB_MEM_PAGE(map)		(0x40 + (map))
+
+#endif /* _LINUX_YENTA_H */
diff --git a/include/post.h b/include/post.h
new file mode 100755
index 0000000..cdefbdd
--- /dev/null
+++ b/include/post.h
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _POST_H
+#define _POST_H
+
+#ifndef	__ASSEMBLY__
+#include <common.h>
+#endif
+
+#ifdef CONFIG_POST
+
+#define POST_POWERON		0x01	/* test runs on power-on booting */
+#define POST_NORMAL		0x02	/* test runs on normal booting */
+#define POST_SLOWTEST		0x04	/* test is slow, enabled by key press */
+#define POST_POWERTEST		0x08	/* test runs after watchdog reset */
+
+#define POST_COLDBOOT		0x80	/* first boot after power-on */
+
+#define POST_ROM		0x0100	/* test runs in ROM */
+#define POST_RAM		0x0200	/* test runs in RAM */
+#define POST_MANUAL		0x0400	/* test runs on diag command */
+#define POST_REBOOT		0x0800	/* test may cause rebooting */
+#define POST_PREREL             0x1000  /* test runs before relocation */
+
+#define POST_MEM		(POST_RAM | POST_ROM)
+#define POST_ALWAYS		(POST_NORMAL	| \
+				 POST_SLOWTEST	| \
+				 POST_MANUAL	| \
+				 POST_POWERON	)
+
+#ifndef	__ASSEMBLY__
+
+struct post_test {
+	char *name;
+	char *cmd;
+	char *desc;
+	int flags;
+	int (*test) (int flags);
+	int (*init_f) (void);
+	void (*reloc) (void);
+	unsigned long testid;
+};
+int post_init_f (void);
+void post_bootmode_init (void);
+int post_bootmode_get (unsigned int * last_test);
+void post_bootmode_clear (void);
+void post_output_backlog ( void );
+int post_run (char *name, int flags);
+int post_info (char *name);
+int post_log (char *format, ...);
+void post_reloc (void);
+unsigned long post_time_ms (unsigned long base);
+
+extern struct post_test post_list[];
+extern unsigned int post_list_size;
+extern int post_hotkeys_pressed(void);
+
+#endif /* __ASSEMBLY__ */
+
+#define CFG_POST_RTC		0x00000001
+#define CFG_POST_WATCHDOG	0x00000002
+#define CFG_POST_MEMORY		0x00000004
+#define CFG_POST_CPU		0x00000008
+#define CFG_POST_I2C		0x00000010
+#define CFG_POST_CACHE		0x00000020
+#define CFG_POST_UART		0x00000040
+#define CFG_POST_ETHER		0x00000080
+#define CFG_POST_SPI		0x00000100
+#define CFG_POST_USB		0x00000200
+#define CFG_POST_SPR		0x00000400
+#define CFG_POST_SYSMON		0x00000800
+#define CFG_POST_DSP		0x00001000
+#define CFG_POST_CODEC		0x00002000
+
+#endif /* CONFIG_POST */
+
+#endif /* _POST_H */
diff --git a/include/ppc405.h b/include/ppc405.h
new file mode 100755
index 0000000..4470240
--- /dev/null
+++ b/include/ppc405.h
@@ -0,0 +1,695 @@
+/*----------------------------------------------------------------------------+
+|
+|       This source code has been made available to you by IBM on an AS-IS
+|       basis.  Anyone receiving this source is licensed under IBM
+|       copyrights to use it in any way he or she deems fit, including
+|       copying it, modifying it, compiling it, and redistributing it either
+|       with or without modifications.  No license under IBM patents or
+|       patent applications is to be implied by the copyright license.
+|
+|       Any user of this software should understand that IBM cannot provide
+|       technical support for this software and will not be responsible for
+|       any consequences resulting from the use of this software.
+|
+|       Any person who transfers this source code or any derivative work
+|       must include the IBM copyright notice, this paragraph, and the
+|       preceding two paragraphs in the transferred software.
+|
+|       COPYRIGHT   I B M   CORPORATION 1999
+|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+
+#ifndef	__PPC405_H__
+#define __PPC405_H__
+
+/*--------------------------------------------------------------------- */
+/* Special Purpose Registers						*/
+/*--------------------------------------------------------------------- */
+	#define  srr2  0x3de      /* save/restore register 2 */
+	#define  srr3  0x3df      /* save/restore register 3 */
+	#define  dbsr  0x3f0      /* debug status register */
+	#define  dbcr0 0x3f2      /* debug control register 0 */
+	#define  dbcr1 0x3bd      /* debug control register 1 */
+	#define  iac1  0x3f4      /* instruction address comparator 1 */
+	#define  iac2  0x3f5      /* instruction address comparator 2 */
+	#define  iac3  0x3b4      /* instruction address comparator 3 */
+	#define  iac4  0x3b5      /* instruction address comparator 4 */
+	#define  dac1  0x3f6      /* data address comparator 1 */
+	#define  dac2  0x3f7      /* data address comparator 2 */
+	#define  dccr  0x3fa      /* data cache control register */
+	#define  iccr  0x3fb      /* instruction cache control register */
+	#define  esr   0x3d4      /* execption syndrome register */
+	#define  dear  0x3d5      /* data exeption address register */
+	#define  evpr  0x3d6      /* exeption vector prefix register */
+	#define  tsr   0x3d8      /* timer status register */
+	#define  tcr   0x3da      /* timer control register */
+	#define  pit   0x3db      /* programmable interval timer */
+	#define  sgr   0x3b9      /* storage guarded reg      */
+	#define  dcwr  0x3ba      /* data cache write-thru reg*/
+	#define  sler  0x3bb      /* storage little-endian reg */
+	#define  cdbcr 0x3d7      /* cache debug cntrl reg    */
+	#define  icdbdr 0x3d3     /* instr cache dbug data reg*/
+	#define  ccr0  0x3b3      /* core configuration register */
+	#define  dvc1  0x3b6      /* data value compare register 1 */
+	#define  dvc2  0x3b7      /* data value compare register 2 */
+	#define  pid   0x3b1      /* process ID */
+	#define  su0r  0x3bc      /* storage user-defined register 0 */
+	#define  zpr   0x3b0      /* zone protection regsiter */
+
+	#define  tbl   0x11c      /* time base lower - privileged write */
+	#define  tbu   0x11d      /* time base upper - privileged write */
+
+	#define  sprg4r 0x104     /* Special purpose general 4 - read only */
+	#define  sprg5r 0x105     /* Special purpose general 5 - read only */
+	#define  sprg6r 0x106     /* Special purpose general 6 - read only */
+	#define  sprg7r 0x107     /* Special purpose general 7 - read only */
+	#define  sprg4w 0x114     /* Special purpose general 4 - write only */
+	#define  sprg5w 0x115     /* Special purpose general 5 - write only */
+	#define  sprg6w 0x116     /* Special purpose general 6 - write only */
+	#define  sprg7w 0x117     /* Special purpose general 7 - write only */
+
+/******************************************************************************
+ * Special for PPC405GP
+ ******************************************************************************/
+
+/******************************************************************************
+ * DMA
+ ******************************************************************************/
+#define DMA_DCR_BASE 0x100
+#define dmacr0  (DMA_DCR_BASE+0x00)  /* DMA channel control register 0       */
+#define dmact0  (DMA_DCR_BASE+0x01)  /* DMA count register 0                 */
+#define dmada0  (DMA_DCR_BASE+0x02)  /* DMA destination address register 0   */
+#define dmasa0  (DMA_DCR_BASE+0x03)  /* DMA source address register 0        */
+#define dmasb0  (DMA_DCR_BASE+0x04)  /* DMA scatter/gather descriptor addr 0 */
+#define dmacr1  (DMA_DCR_BASE+0x08)  /* DMA channel control register 1       */
+#define dmact1  (DMA_DCR_BASE+0x09)  /* DMA count register 1                 */
+#define dmada1  (DMA_DCR_BASE+0x0a)  /* DMA destination address register 1   */
+#define dmasa1  (DMA_DCR_BASE+0x0b)  /* DMA source address register 1        */
+#define dmasb1  (DMA_DCR_BASE+0x0c)  /* DMA scatter/gather descriptor addr 1 */
+#define dmacr2  (DMA_DCR_BASE+0x10)  /* DMA channel control register 2       */
+#define dmact2  (DMA_DCR_BASE+0x11)  /* DMA count register 2                 */
+#define dmada2  (DMA_DCR_BASE+0x12)  /* DMA destination address register 2   */
+#define dmasa2  (DMA_DCR_BASE+0x13)  /* DMA source address register 2        */
+#define dmasb2  (DMA_DCR_BASE+0x14)  /* DMA scatter/gather descriptor addr 2 */
+#define dmacr3  (DMA_DCR_BASE+0x18)  /* DMA channel control register 3       */
+#define dmact3  (DMA_DCR_BASE+0x19)  /* DMA count register 3                 */
+#define dmada3  (DMA_DCR_BASE+0x1a)  /* DMA destination address register 3   */
+#define dmasa3  (DMA_DCR_BASE+0x1b)  /* DMA source address register 3        */
+#define dmasb3  (DMA_DCR_BASE+0x1c)  /* DMA scatter/gather descriptor addr 3 */
+#define dmasr   (DMA_DCR_BASE+0x20)  /* DMA status register                  */
+#define dmasgc  (DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
+#define dmaadr  (DMA_DCR_BASE+0x24)  /* DMA address decode register          */
+
+/******************************************************************************
+ * Universal interrupt controller
+ ******************************************************************************/
+#define UIC_DCR_BASE 0xc0
+#define uicsr        (UIC_DCR_BASE+0x0)  /* UIC status                       */
+#define uicsrs       (UIC_DCR_BASE+0x1)  /* UIC status set                   */
+#define uicer        (UIC_DCR_BASE+0x2)  /* UIC enable                       */
+#define uiccr        (UIC_DCR_BASE+0x3)  /* UIC critical                     */
+#define uicpr        (UIC_DCR_BASE+0x4)  /* UIC polarity                     */
+#define uictr        (UIC_DCR_BASE+0x5)  /* UIC triggering                   */
+#define uicmsr       (UIC_DCR_BASE+0x6)  /* UIC masked status                */
+#define uicvr        (UIC_DCR_BASE+0x7)  /* UIC vector                       */
+#define uicvcr       (UIC_DCR_BASE+0x8)  /* UIC vector configuration         */
+
+/*-----------------------------------------------------------------------------+
+|  Universal interrupt controller interrupts
++-----------------------------------------------------------------------------*/
+#define UIC_UART0     0x80000000      /* UART 0                             */
+#define UIC_UART1     0x40000000      /* UART 1                             */
+#define UIC_IIC       0x20000000      /* IIC                                */
+#define UIC_EXT_MAST  0x10000000      /* External Master                    */
+#define UIC_PCI       0x08000000      /* PCI write to command reg           */
+#define UIC_DMA0      0x04000000      /* DMA chan. 0                        */
+#define UIC_DMA1      0x02000000      /* DMA chan. 1                        */
+#define UIC_DMA2      0x01000000      /* DMA chan. 2                        */
+#define UIC_DMA3      0x00800000      /* DMA chan. 3                        */
+#define UIC_EMAC_WAKE 0x00400000      /* EMAC wake up                       */
+#define UIC_MAL_SERR  0x00200000      /* MAL SERR                           */
+#define UIC_MAL_TXEOB 0x00100000      /* MAL TXEOB                          */
+#define UIC_MAL_RXEOB 0x00080000      /* MAL RXEOB                          */
+#define UIC_MAL_TXDE  0x00040000      /* MAL TXDE                           */
+#define UIC_MAL_RXDE  0x00020000      /* MAL RXDE                           */
+#define UIC_ENET      0x00010000      /* Ethernet0                          */
+#define UIC_ENET1     0x00004000      /* Ethernet1 on 405EP                 */
+#define UIC_ECC_CE    0x00004000      /* ECC Correctable Error on 405GP     */
+#define UIC_EXT_PCI_SERR 0x00008000   /* External PCI SERR#                 */
+#define UIC_PCI_PM    0x00002000      /* PCI Power Management               */
+#define UIC_EXT0      0x00000040      /* External  interrupt 0              */
+#define UIC_EXT1      0x00000020      /* External  interrupt 1              */
+#define UIC_EXT2      0x00000010      /* External  interrupt 2              */
+#define UIC_EXT3      0x00000008      /* External  interrupt 3              */
+#define UIC_EXT4      0x00000004      /* External  interrupt 4              */
+#define UIC_EXT5      0x00000002      /* External  interrupt 5              */
+#define UIC_EXT6      0x00000001      /* External  interrupt 6              */
+
+/******************************************************************************
+ * SDRAM Controller
+ ******************************************************************************/
+#define SDRAM_DCR_BASE 0x10
+#define memcfga  (SDRAM_DCR_BASE+0x0)   /* Memory configuration address reg  */
+#define memcfgd  (SDRAM_DCR_BASE+0x1)   /* Memory configuration data    reg  */
+  /* values for memcfga register - indirect addressing of these regs */
+#ifndef CONFIG_405EP
+  #define mem_besra   0x00    /* bus error syndrome reg a	     */
+  #define mem_besrsa  0x04    /* bus error syndrome reg set a	     */
+  #define mem_besrb   0x08    /* bus error syndrome reg b	     */
+  #define mem_besrsb  0x0c    /* bus error syndrome reg set b	     */
+  #define mem_bear    0x10    /* bus error address reg		     */
+#endif
+  #define mem_mcopt1  0x20    /* memory controller options 1	     */
+  #define mem_rtr     0x30    /* refresh timer reg		     */
+  #define mem_pmit    0x34    /* power management idle timer	     */
+  #define mem_mb0cf   0x40    /* memory bank 0 configuration	     */
+  #define mem_mb1cf   0x44    /* memory bank 1 configuration	     */
+#ifndef CONFIG_405EP
+  #define mem_mb2cf   0x48    /* memory bank 2 configuration	     */
+  #define mem_mb3cf   0x4c    /* memory bank 3 configuration	     */
+#endif
+  #define mem_sdtr1   0x80    /* timing reg 1			     */
+#ifndef CONFIG_405EP
+  #define mem_ecccf   0x94    /* ECC configuration		     */
+  #define mem_eccerr  0x98    /* ECC error status		     */
+#endif
+
+#ifndef CONFIG_405EP
+/******************************************************************************
+ * Decompression Controller
+ ******************************************************************************/
+#define DECOMP_DCR_BASE 0x14
+#define kiar  (DECOMP_DCR_BASE+0x0)  /* Decompression controller addr reg    */
+#define kidr  (DECOMP_DCR_BASE+0x1)  /* Decompression controller data reg    */
+  /* values for kiar register - indirect addressing of these regs */
+  #define kitor0      0x00    /* index table origin register 0	      */
+  #define kitor1      0x01    /* index table origin register 1	      */
+  #define kitor2      0x02    /* index table origin register 2	      */
+  #define kitor3      0x03    /* index table origin register 3	      */
+  #define kaddr0      0x04    /* address decode definition regsiter 0 */
+  #define kaddr1      0x05    /* address decode definition regsiter 1 */
+  #define kconf       0x40    /* decompression core config register   */
+  #define kid         0x41    /* decompression core ID     register   */
+  #define kver        0x42    /* decompression core version # reg     */
+  #define kpear       0x50    /* bus error addr reg (PLB addr)        */
+  #define kbear       0x51    /* bus error addr reg (DCP to EBIU addr)*/
+  #define kesr0       0x52    /* bus error status reg 0  (R/clear)    */
+  #define kesr0s      0x53    /* bus error status reg 0  (set)        */
+  /* There are 0x400 of the following registers, from krom0 to krom3ff*/
+  /* Only the first one is given here.                                */
+  #define krom0      0x400    /* SRAM/ROM read/write                  */
+#endif
+
+/******************************************************************************
+ * Power Management
+ ******************************************************************************/
+#define POWERMAN_DCR_BASE 0xb8
+#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status             */
+#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable             */
+#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force              */
+
+/******************************************************************************
+ * Extrnal Bus Controller
+ ******************************************************************************/
+#define EBC_DCR_BASE 0x12
+#define ebccfga (EBC_DCR_BASE+0x0)   /* External bus controller addr reg     */
+#define ebccfgd (EBC_DCR_BASE+0x1)   /* External bus controller data reg     */
+  /* values for ebccfga register - indirect addressing of these regs */
+  #define pb0cr       0x00    /* periph bank 0 config reg            */
+  #define pb1cr       0x01    /* periph bank 1 config reg            */
+  #define pb2cr       0x02    /* periph bank 2 config reg            */
+  #define pb3cr       0x03    /* periph bank 3 config reg            */
+  #define pb4cr       0x04    /* periph bank 4 config reg            */
+#ifndef CONFIG_405EP
+  #define pb5cr       0x05    /* periph bank 5 config reg            */
+  #define pb6cr       0x06    /* periph bank 6 config reg            */
+  #define pb7cr       0x07    /* periph bank 7 config reg            */
+#endif
+  #define pb0ap       0x10    /* periph bank 0 access parameters     */
+  #define pb1ap       0x11    /* periph bank 1 access parameters     */
+  #define pb2ap       0x12    /* periph bank 2 access parameters     */
+  #define pb3ap       0x13    /* periph bank 3 access parameters     */
+  #define pb4ap       0x14    /* periph bank 4 access parameters     */
+#ifndef CONFIG_405EP
+  #define pb5ap       0x15    /* periph bank 5 access parameters     */
+  #define pb6ap       0x16    /* periph bank 6 access parameters     */
+  #define pb7ap       0x17    /* periph bank 7 access parameters     */
+#endif
+  #define pbear       0x20    /* periph bus error addr reg           */
+  #define pbesr0      0x21    /* periph bus error status reg 0       */
+  #define pbesr1      0x22    /* periph bus error status reg 1       */
+  #define epcr        0x23    /* external periph control reg         */
+
+#ifdef CONFIG_405EP
+/******************************************************************************
+ * Control
+ ******************************************************************************/
+#define CNTRL_DCR_BASE 0x0f0
+#define cpc0_pllmr0   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register 0                */
+#define cpc0_boot     (CNTRL_DCR_BASE+0x1)  /* Clock status register               */
+#define cpc0_epctl    (CNTRL_DCR_BASE+0x3)  /* EMAC to PHY control register        */
+#define cpc0_pllmr1   (CNTRL_DCR_BASE+0x4)  /* PLL mode  register 1                */
+#define cpc0_ucr      (CNTRL_DCR_BASE+0x5)  /* UART control register               */
+#define cpc0_pci      (CNTRL_DCR_BASE+0x9)  /* PCI control register                */
+
+#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register          */
+#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register   */
+#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register      */
+#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register*/
+#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register          */
+#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register        */
+#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register          */
+#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register             */
+#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR                    */
+#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register         */
+
+/* Bit definitions */
+#define PLLMR0_CPU_DIV_MASK      0x00300000     /* CPU clock divider */
+#define PLLMR0_CPU_DIV_BYPASS    0x00000000
+#define PLLMR0_CPU_DIV_2         0x00100000
+#define PLLMR0_CPU_DIV_3         0x00200000
+#define PLLMR0_CPU_DIV_4         0x00300000
+
+#define PLLMR0_CPU_TO_PLB_MASK   0x00030000     /* CPU:PLB Frequency Divisor */
+#define PLLMR0_CPU_PLB_DIV_1     0x00000000
+#define PLLMR0_CPU_PLB_DIV_2     0x00010000
+#define PLLMR0_CPU_PLB_DIV_3     0x00020000
+#define PLLMR0_CPU_PLB_DIV_4     0x00030000
+
+#define PLLMR0_OPB_TO_PLB_MASK   0x00003000     /* OPB:PLB Frequency Divisor */
+#define PLLMR0_OPB_PLB_DIV_1     0x00000000
+#define PLLMR0_OPB_PLB_DIV_2     0x00001000
+#define PLLMR0_OPB_PLB_DIV_3     0x00002000
+#define PLLMR0_OPB_PLB_DIV_4     0x00003000
+
+#define PLLMR0_EXB_TO_PLB_MASK   0x00000300     /* External Bus:PLB Divisor  */
+#define PLLMR0_EXB_PLB_DIV_2     0x00000000
+#define PLLMR0_EXB_PLB_DIV_3     0x00000100
+#define PLLMR0_EXB_PLB_DIV_4     0x00000200
+#define PLLMR0_EXB_PLB_DIV_5     0x00000300
+
+#define PLLMR0_MAL_TO_PLB_MASK   0x00000030     /* MAL:PLB Divisor  */
+#define PLLMR0_MAL_PLB_DIV_1     0x00000000
+#define PLLMR0_MAL_PLB_DIV_2     0x00000010
+#define PLLMR0_MAL_PLB_DIV_3     0x00000020
+#define PLLMR0_MAL_PLB_DIV_4     0x00000030
+
+#define PLLMR0_PCI_TO_PLB_MASK   0x00000003     /* PCI:PLB Frequency Divisor */
+#define PLLMR0_PCI_PLB_DIV_1     0x00000000
+#define PLLMR0_PCI_PLB_DIV_2     0x00000001
+#define PLLMR0_PCI_PLB_DIV_3     0x00000002
+#define PLLMR0_PCI_PLB_DIV_4     0x00000003
+
+#define PLLMR1_SSCS_MASK         0x80000000     /* Select system clock source */
+#define PLLMR1_PLLR_MASK         0x40000000     /* PLL reset */
+#define PLLMR1_FBMUL_MASK        0x00F00000     /* PLL feedback multiplier value */
+#define PLLMR1_FBMUL_DIV_16      0x00000000
+#define PLLMR1_FBMUL_DIV_1       0x00100000
+#define PLLMR1_FBMUL_DIV_2       0x00200000
+#define PLLMR1_FBMUL_DIV_3       0x00300000
+#define PLLMR1_FBMUL_DIV_4       0x00400000
+#define PLLMR1_FBMUL_DIV_5       0x00500000
+#define PLLMR1_FBMUL_DIV_6       0x00600000
+#define PLLMR1_FBMUL_DIV_7       0x00700000
+#define PLLMR1_FBMUL_DIV_8       0x00800000
+#define PLLMR1_FBMUL_DIV_9       0x00900000
+#define PLLMR1_FBMUL_DIV_10      0x00A00000
+#define PLLMR1_FBMUL_DIV_11      0x00B00000
+#define PLLMR1_FBMUL_DIV_12      0x00C00000
+#define PLLMR1_FBMUL_DIV_13      0x00D00000
+#define PLLMR1_FBMUL_DIV_14      0x00E00000
+#define PLLMR1_FBMUL_DIV_15      0x00F00000
+
+#define PLLMR1_FWDVA_MASK        0x00070000     /* PLL forward divider A value */
+#define PLLMR1_FWDVA_DIV_8       0x00000000
+#define PLLMR1_FWDVA_DIV_7       0x00010000
+#define PLLMR1_FWDVA_DIV_6       0x00020000
+#define PLLMR1_FWDVA_DIV_5       0x00030000
+#define PLLMR1_FWDVA_DIV_4       0x00040000
+#define PLLMR1_FWDVA_DIV_3       0x00050000
+#define PLLMR1_FWDVA_DIV_2       0x00060000
+#define PLLMR1_FWDVA_DIV_1       0x00070000
+#define PLLMR1_FWDVB_MASK        0x00007000     /* PLL forward divider B value */
+#define PLLMR1_TUNING_MASK       0x000003FF     /* PLL tune bits */
+
+/* Defines for CPC0_EPRCSR register */
+#define CPC0_EPRCSR_E0NFE          0x80000000
+#define CPC0_EPRCSR_E1NFE          0x40000000
+#define CPC0_EPRCSR_E1RPP          0x00000080
+#define CPC0_EPRCSR_E0RPP          0x00000040
+#define CPC0_EPRCSR_E1ERP          0x00000020
+#define CPC0_EPRCSR_E0ERP          0x00000010
+#define CPC0_EPRCSR_E1PCI          0x00000002
+#define CPC0_EPRCSR_E0PCI          0x00000001
+
+/* Defines for CPC0_PCI Register */
+#define CPC0_PCI_SPE                       0x00000010 /* PCIINT/WE select       */
+#define CPC0_PCI_HOST_CFG_EN               0x00000008 /* PCI host config Enable */
+#define CPC0_PCI_ARBIT_EN                  0x00000001 /* PCI Internal Arb Enabled*/
+
+/* Defines for CPC0_BOOR Register */
+#define CPC0_BOOT_SEP                      0x00000002 /* serial EEPROM present  */
+
+/* Defines for CPC0_PLLMR1 Register fields */
+#define PLL_ACTIVE                 0x80000000
+#define CPC0_PLLMR1_SSCS           0x80000000
+#define PLL_RESET                  0x40000000
+#define CPC0_PLLMR1_PLLR           0x40000000
+    /* Feedback multiplier */
+#define PLL_FBKDIV                 0x00F00000
+#define CPC0_PLLMR1_FBDV           0x00F00000
+#define PLL_FBKDIV_16              0x00000000
+#define PLL_FBKDIV_1               0x00100000
+#define PLL_FBKDIV_2               0x00200000
+#define PLL_FBKDIV_3               0x00300000
+#define PLL_FBKDIV_4               0x00400000
+#define PLL_FBKDIV_5               0x00500000
+#define PLL_FBKDIV_6               0x00600000
+#define PLL_FBKDIV_7               0x00700000
+#define PLL_FBKDIV_8               0x00800000
+#define PLL_FBKDIV_9               0x00900000
+#define PLL_FBKDIV_10              0x00A00000
+#define PLL_FBKDIV_11              0x00B00000
+#define PLL_FBKDIV_12              0x00C00000
+#define PLL_FBKDIV_13              0x00D00000
+#define PLL_FBKDIV_14              0x00E00000
+#define PLL_FBKDIV_15              0x00F00000
+    /* Forward A divisor */
+#define PLL_FWDDIVA                0x00070000
+#define CPC0_PLLMR1_FWDVA          0x00070000
+#define PLL_FWDDIVA_8              0x00000000
+#define PLL_FWDDIVA_7              0x00010000
+#define PLL_FWDDIVA_6              0x00020000
+#define PLL_FWDDIVA_5              0x00030000
+#define PLL_FWDDIVA_4              0x00040000
+#define PLL_FWDDIVA_3              0x00050000
+#define PLL_FWDDIVA_2              0x00060000
+#define PLL_FWDDIVA_1              0x00070000
+    /* Forward B divisor */
+#define PLL_FWDDIVB                0x00007000
+#define CPC0_PLLMR1_FWDVB          0x00007000
+#define PLL_FWDDIVB_8              0x00000000
+#define PLL_FWDDIVB_7              0x00001000
+#define PLL_FWDDIVB_6              0x00002000
+#define PLL_FWDDIVB_5              0x00003000
+#define PLL_FWDDIVB_4              0x00004000
+#define PLL_FWDDIVB_3              0x00005000
+#define PLL_FWDDIVB_2              0x00006000
+#define PLL_FWDDIVB_1              0x00007000
+    /* PLL tune bits */
+#define PLL_TUNE_MASK            0x000003FF
+#define PLL_TUNE_2_M_3           0x00000133     /*  2 <= M <= 3               */
+#define PLL_TUNE_4_M_6           0x00000134     /*  3 <  M <= 6               */
+#define PLL_TUNE_7_M_10          0x00000138     /*  6 <  M <= 10              */
+#define PLL_TUNE_11_M_14         0x0000013C     /* 10 <  M <= 14              */
+#define PLL_TUNE_15_M_40         0x0000023E     /* 14 <  M <= 40              */
+#define PLL_TUNE_VCO_LOW         0x00000000     /* 500MHz <= VCO <=  800MHz   */
+#define PLL_TUNE_VCO_HI          0x00000080     /* 800MHz <  VCO <= 1000MHz   */
+
+/* Defines for CPC0_PLLMR0 Register fields */
+    /* CPU divisor */
+#define PLL_CPUDIV                 0x00300000
+#define CPC0_PLLMR0_CCDV           0x00300000
+#define PLL_CPUDIV_1               0x00000000
+#define PLL_CPUDIV_2               0x00100000
+#define PLL_CPUDIV_3               0x00200000
+#define PLL_CPUDIV_4               0x00300000
+    /* PLB divisor */
+#define PLL_PLBDIV                 0x00030000
+#define CPC0_PLLMR0_CBDV           0x00030000
+#define PLL_PLBDIV_1               0x00000000
+#define PLL_PLBDIV_2               0x00010000
+#define PLL_PLBDIV_3               0x00020000
+#define PLL_PLBDIV_4               0x00030000
+    /* OPB divisor */
+#define PLL_OPBDIV                 0x00003000
+#define CPC0_PLLMR0_OPDV           0x00003000
+#define PLL_OPBDIV_1               0x00000000
+#define PLL_OPBDIV_2               0x00001000
+#define PLL_OPBDIV_3               0x00002000
+#define PLL_OPBDIV_4               0x00003000
+    /* EBC divisor */
+#define PLL_EXTBUSDIV              0x00000300
+#define CPC0_PLLMR0_EPDV           0x00000300
+#define PLL_EXTBUSDIV_2            0x00000000
+#define PLL_EXTBUSDIV_3            0x00000100
+#define PLL_EXTBUSDIV_4            0x00000200
+#define PLL_EXTBUSDIV_5            0x00000300
+    /* MAL divisor */
+#define PLL_MALDIV                 0x00000030
+#define CPC0_PLLMR0_MPDV           0x00000030
+#define PLL_MALDIV_1               0x00000000
+#define PLL_MALDIV_2               0x00000010
+#define PLL_MALDIV_3               0x00000020
+#define PLL_MALDIV_4               0x00000030
+    /* PCI divisor */
+#define PLL_PCIDIV                 0x00000003
+#define CPC0_PLLMR0_PPFD           0x00000003
+#define PLL_PCIDIV_1               0x00000000
+#define PLL_PCIDIV_2               0x00000001
+#define PLL_PCIDIV_3               0x00000002
+#define PLL_PCIDIV_4               0x00000003
+
+/*
+ *-------------------------------------------------------------------------------
+ * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
+ * assuming a 33.3MHz input clock to the 405EP.
+ *-------------------------------------------------------------------------------
+ */
+#define PLLMR0_266_133_66  (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+			    PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+			    PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_266_133_66  (PLL_FBKDIV_8  |  \
+			    PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+			    PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PLLMR0_133_66_66_33  (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_133_66_66_33  (PLL_FBKDIV_4  |  \
+			      PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
+			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8  |  \
+			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+			      PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8  |  \
+			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+/*
+ * PLL Voltage Controlled Oscillator (VCO) definitions
+ * Maximum and minimum values (in MHz) for correct PLL operation.
+ */
+#define VCO_MIN     500
+#define VCO_MAX     1000
+#else /* #ifdef CONFIG_405EP */
+/******************************************************************************
+ * Control
+ ******************************************************************************/
+#define CNTRL_DCR_BASE 0x0b0
+#define pllmd   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register                  */
+#define cntrl0  (CNTRL_DCR_BASE+0x1)  /* Control 0 register                  */
+#define cntrl1  (CNTRL_DCR_BASE+0x2)  /* Control 1 register		     */
+#define reset   (CNTRL_DCR_BASE+0x3)  /* reset register			     */
+#define strap   (CNTRL_DCR_BASE+0x4)  /* strap register		   	     */
+
+#define ecr     (0xaa)                /* edge conditioner register (405gpr)  */
+
+/* Bit definitions */
+#define PLLMR_FWD_DIV_MASK      0xE0000000     /* Forward Divisor */
+#define PLLMR_FWD_DIV_BYPASS    0xE0000000
+#define PLLMR_FWD_DIV_3         0xA0000000
+#define PLLMR_FWD_DIV_4         0x80000000
+#define PLLMR_FWD_DIV_6         0x40000000
+
+#define PLLMR_FB_DIV_MASK       0x1E000000     /* Feedback Divisor */
+#define PLLMR_FB_DIV_1          0x02000000
+#define PLLMR_FB_DIV_2          0x04000000
+#define PLLMR_FB_DIV_3          0x06000000
+#define PLLMR_FB_DIV_4          0x08000000
+
+#define PLLMR_TUNING_MASK       0x01F80000
+
+#define PLLMR_CPU_TO_PLB_MASK   0x00060000     /* CPU:PLB Frequency Divisor */
+#define PLLMR_CPU_PLB_DIV_1     0x00000000
+#define PLLMR_CPU_PLB_DIV_2     0x00020000
+#define PLLMR_CPU_PLB_DIV_3     0x00040000
+#define PLLMR_CPU_PLB_DIV_4     0x00060000
+
+#define PLLMR_OPB_TO_PLB_MASK   0x00018000     /* OPB:PLB Frequency Divisor */
+#define PLLMR_OPB_PLB_DIV_1     0x00000000
+#define PLLMR_OPB_PLB_DIV_2     0x00008000
+#define PLLMR_OPB_PLB_DIV_3     0x00010000
+#define PLLMR_OPB_PLB_DIV_4     0x00018000
+
+#define PLLMR_PCI_TO_PLB_MASK   0x00006000     /* PCI:PLB Frequency Divisor */
+#define PLLMR_PCI_PLB_DIV_1     0x00000000
+#define PLLMR_PCI_PLB_DIV_2     0x00002000
+#define PLLMR_PCI_PLB_DIV_3     0x00004000
+#define PLLMR_PCI_PLB_DIV_4     0x00006000
+
+#define PLLMR_EXB_TO_PLB_MASK   0x00001800     /* External Bus:PLB Divisor  */
+#define PLLMR_EXB_PLB_DIV_2     0x00000000
+#define PLLMR_EXB_PLB_DIV_3     0x00000800
+#define PLLMR_EXB_PLB_DIV_4     0x00001000
+#define PLLMR_EXB_PLB_DIV_5     0x00001800
+
+/* definitions for PPC405GPr (new mode strapping) */
+#define PLLMR_FWDB_DIV_MASK     0x00000007     /* Forward Divisor B */
+
+#define PSR_PLL_FWD_MASK        0xC0000000
+#define PSR_PLL_FDBACK_MASK     0x30000000
+#define PSR_PLL_TUNING_MASK     0x0E000000
+#define PSR_PLB_CPU_MASK        0x01800000
+#define PSR_OPB_PLB_MASK        0x00600000
+#define PSR_PCI_PLB_MASK        0x00180000
+#define PSR_EB_PLB_MASK         0x00060000
+#define PSR_ROM_WIDTH_MASK      0x00018000
+#define PSR_ROM_LOC             0x00004000
+#define PSR_PCI_ASYNC_EN        0x00001000
+#define PSR_PERCLK_SYNC_MODE_EN 0x00000800     /* PPC405GPr only */
+#define PSR_PCI_ARBIT_EN        0x00000400
+#define PSR_NEW_MODE_EN         0x00000020     /* PPC405GPr only */
+
+#ifndef CONFIG_IOP480
+/*
+ * PLL Voltage Controlled Oscillator (VCO) definitions
+ * Maximum and minimum values (in MHz) for correct PLL operation.
+ */
+#define VCO_MIN     400
+#define VCO_MAX     800
+#endif /* #ifndef CONFIG_IOP480 */
+#endif /* #ifdef CONFIG_405EP */
+
+/******************************************************************************
+ * Memory Access Layer
+ ******************************************************************************/
+#define MAL_DCR_BASE 0x180
+#define malmcr  (MAL_DCR_BASE+0x00)  /* MAL Config reg                       */
+#define malesr  (MAL_DCR_BASE+0x01)  /* Error Status reg (Read/Clear)        */
+#define malier  (MAL_DCR_BASE+0x02)  /* Interrupt enable reg                 */
+#define maldbr  (MAL_DCR_BASE+0x03)  /* Mal Debug reg (Read only)            */
+#define maltxcasr  (MAL_DCR_BASE+0x04)  /* TX Channel active reg (set)       */
+#define maltxcarr  (MAL_DCR_BASE+0x05)  /* TX Channel active reg (Reset)     */
+#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg   */
+#define maltxdeir  (MAL_DCR_BASE+0x07)  /* TX Descr. Error Int reg           */
+#define malrxcasr  (MAL_DCR_BASE+0x10)  /* RX Channel active reg (set)       */
+#define malrxcarr  (MAL_DCR_BASE+0x11)  /* RX Channel active reg (Reset)     */
+#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg   */
+#define malrxdeir  (MAL_DCR_BASE+0x13)  /* RX Descr. Error Int reg           */
+#define maltxctp0r (MAL_DCR_BASE+0x20)  /* TX 0 Channel table pointer reg    */
+#define maltxctp1r (MAL_DCR_BASE+0x21)  /* TX 1 Channel table pointer reg    */
+#define maltxctp2r (MAL_DCR_BASE+0x22)  /* TX 2 Channel table pointer reg    */
+#define malrxctp0r (MAL_DCR_BASE+0x40)  /* RX 0 Channel table pointer reg    */
+#define malrxctp1r (MAL_DCR_BASE+0x41)  /* RX 1 Channel table pointer reg    */
+#define malrcbs0   (MAL_DCR_BASE+0x60)  /* RX 0 Channel buffer size reg      */
+#define malrcbs1   (MAL_DCR_BASE+0x61)  /* RX 1 Channel buffer size reg      */
+
+/*-----------------------------------------------------------------------------
+| IIC Register Offsets
+'----------------------------------------------------------------------------*/
+#define    IICMDBUF         0x00
+#define    IICSDBUF         0x02
+#define    IICLMADR         0x04
+#define    IICHMADR         0x05
+#define    IICCNTL          0x06
+#define    IICMDCNTL        0x07
+#define    IICSTS           0x08
+#define    IICEXTSTS        0x09
+#define    IICLSADR         0x0A
+#define    IICHSADR         0x0B
+#define    IICCLKDIV        0x0C
+#define    IICINTRMSK       0x0D
+#define    IICXFRCNT        0x0E
+#define    IICXTCNTLSS      0x0F
+#define    IICDIRECTCNTL    0x10
+
+/*-----------------------------------------------------------------------------
+| UART Register Offsets
+'----------------------------------------------------------------------------*/
+#define		DATA_REG	0x00
+#define		DL_LSB    	0x00
+#define		DL_MSB  	0x01
+#define		INT_ENABLE      0x01
+#define		FIFO_CONTROL    0x02
+#define		LINE_CONTROL    0x03
+#define		MODEM_CONTROL   0x04
+#define		LINE_STATUS  	0x05
+#define		MODEM_STATUS    0x06
+#define		SCRATCH         0x07
+
+/******************************************************************************
+ * On Chip Memory
+ ******************************************************************************/
+#define OCM_DCR_BASE 0x018
+#define ocmisarc   (OCM_DCR_BASE+0x00)  /* OCM I-side address compare reg    */
+#define ocmiscntl  (OCM_DCR_BASE+0x01)  /* OCM I-side control reg            */
+#define ocmdsarc   (OCM_DCR_BASE+0x02)  /* OCM D-side address compare reg    */
+#define ocmdscntl  (OCM_DCR_BASE+0x03)  /* OCM D-side control reg            */
+
+/******************************************************************************
+ * GPIO macro register defines
+ ******************************************************************************/
+#define GPIO_BASE  0xEF600700
+#define GPIO0_OR               (GPIO_BASE+0x0)
+#define GPIO0_TCR              (GPIO_BASE+0x4)
+#define GPIO0_OSRH             (GPIO_BASE+0x8)
+#define GPIO0_OSRL             (GPIO_BASE+0xC)
+#define GPIO0_TSRH             (GPIO_BASE+0x10)
+#define GPIO0_TSRL             (GPIO_BASE+0x14)
+#define GPIO0_ODR              (GPIO_BASE+0x18)
+#define GPIO0_IR               (GPIO_BASE+0x1C)
+#define GPIO0_RR1              (GPIO_BASE+0x20)
+#define GPIO0_RR2              (GPIO_BASE+0x24)
+#define GPIO0_ISR1H            (GPIO_BASE+0x30)
+#define GPIO0_ISR1L            (GPIO_BASE+0x34)
+#define GPIO0_ISR2H            (GPIO_BASE+0x38)
+#define GPIO0_ISR2L            (GPIO_BASE+0x3C)
+
+
+/*
+ * Macro for accessing the indirect EBC register
+ */
+#define mtebc(reg, data)  mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
+#define mfebc(reg, data)  mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
+
+
+#ifndef __ASSEMBLY__
+
+typedef struct
+{
+  unsigned long pllFwdDiv;
+  unsigned long pllFwdDivB;
+  unsigned long pllFbkDiv;
+  unsigned long pllPlbDiv;
+  unsigned long pllPciDiv;
+  unsigned long pllExtBusDiv;
+  unsigned long pllOpbDiv;
+  unsigned long freqVCOMhz;             /* in MHz                          */
+  unsigned long freqProcessor;
+  unsigned long freqPLB;
+  unsigned long freqPCI;
+  unsigned long pciIntArbEn;            /* Internal PCI arbiter is enabled */
+  unsigned long pciClkSync;             /* PCI clock is synchronous        */
+  unsigned long freqVCOHz;
+} PPC405_SYS_INFO;
+
+#endif  /* _ASMLANGUAGE */
+
+#define RESET_VECTOR	0xfffffffc
+#define CACHELINE_MASK	(CFG_CACHELINE_SIZE - 1) /* Address mask for cache
+						     line aligned data. */
+
+#endif	/* __PPC405_H__ */
diff --git a/include/ppc440.h b/include/ppc440.h
new file mode 100755
index 0000000..018f7be
--- /dev/null
+++ b/include/ppc440.h
@@ -0,0 +1,1461 @@
+/*----------------------------------------------------------------------------+
+|
+|	This source code has been made available to you by IBM on an AS-IS
+|	basis.	Anyone receiving this source is licensed under IBM
+|	copyrights to use it in any way he or she deems fit, including
+|	copying it, modifying it, compiling it, and redistributing it either
+|	with or without modifications.	No license under IBM patents or
+|	patent applications is to be implied by the copyright license.
+|
+|	Any user of this software should understand that IBM cannot provide
+|	technical support for this software and will not be responsible for
+|	any consequences resulting from the use of this software.
+|
+|	Any person who transfers this source code or any derivative work
+|	must include the IBM copyright notice, this paragraph, and the
+|	preceding two paragraphs in the transferred software.
+|
+|	COPYRIGHT   I B M   CORPORATION 1999
+|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+
+#ifndef __PPC440_H__
+#define __PPC440_H__
+
+/*--------------------------------------------------------------------- */
+/* Special Purpose Registers						*/
+/*--------------------------------------------------------------------- */
+#define	 dec	0x016	/* decrementer */
+#define	 srr0	0x01a	/* save/restore register 0 */
+#define	 srr1	0x01b	/* save/restore register 1 */
+#define	 pid	0x030	/* process id */
+#define	 decar	0x036	/* decrementer auto-reload */
+#define	 csrr0	0x03a	/* critical save/restore register 0 */
+#define	 csrr1	0x03b	/* critical save/restore register 1 */
+#define	 dear	0x03d	/* data exception address register */
+#define	 esr	0x03e	/* exception syndrome register */
+#define	 ivpr	0x03f	/* interrupt prefix register */
+#define	 usprg0 0x100	/* user special purpose register general 0 */
+#define	 usprg1 0x110	/* user special purpose register general 1 */
+#define	 sprg1	0x111	/* special purpose register general 1 */
+#define	 sprg2	0x112	/* special purpose register general 2 */
+#define	 sprg3	0x113	/* special purpose register general 3 */
+#define	 sprg4	0x114	/* special purpose register general 4 */
+#define	 sprg5	0x115	/* special purpose register general 5 */
+#define	 sprg6	0x116	/* special purpose register general 6 */
+#define	 sprg7	0x117	/* special purpose register general 7 */
+#define	 tbl	0x11c	/* time base lower (supervisor)*/
+#define	 tbu	0x11d	/* time base upper (supervisor)*/
+#define	 pir	0x11e	/* processor id register */
+/*#define  pvr	0x11f	 processor version register */
+#define	 dbsr	0x130	/* debug status register */
+#define	 dbcr0	0x134	/* debug control register 0 */
+#define	 dbcr1	0x135	/* debug control register 1 */
+#define	 dbcr2	0x136	/* debug control register 2 */
+#define	 iac1	0x138	/* instruction address compare 1 */
+#define	 iac2	0x139	/* instruction address compare 2 */
+#define	 iac3	0x13a	/* instruction address compare 3 */
+#define	 iac4	0x13b	/* instruction address compare 4 */
+#define	 dac1	0x13c	/* data address compare 1 */
+#define	 dac2	0x13d	/* data address compare 2 */
+#define	 dvc1	0x13e	/* data value compare 1 */
+#define	 dvc2	0x13f	/* data value compare 2 */
+#define	 tsr	0x150	/* timer status register */
+#define	 tcr	0x154	/* timer control register */
+#define	 ivor0	0x190	/* interrupt vector offset register 0 */
+#define	 ivor1	0x191	/* interrupt vector offset register 1 */
+#define	 ivor2	0x192	/* interrupt vector offset register 2 */
+#define	 ivor3	0x193	/* interrupt vector offset register 3 */
+#define	 ivor4	0x194	/* interrupt vector offset register 4 */
+#define	 ivor5	0x195	/* interrupt vector offset register 5 */
+#define	 ivor6	0x196	/* interrupt vector offset register 6 */
+#define	 ivor7	0x197	/* interrupt vector offset register 7 */
+#define	 ivor8	0x198	/* interrupt vector offset register 8 */
+#define	 ivor9	0x199	/* interrupt vector offset register 9 */
+#define	 ivor10 0x19a	/* interrupt vector offset register 10 */
+#define	 ivor11 0x19b	/* interrupt vector offset register 11 */
+#define	 ivor12 0x19c	/* interrupt vector offset register 12 */
+#define	 ivor13 0x19d	/* interrupt vector offset register 13 */
+#define	 ivor14 0x19e	/* interrupt vector offset register 14 */
+#define	 ivor15 0x19f	/* interrupt vector offset register 15 */
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#define	 mcsrr0 0x23a	/* machine check save/restore register 0 */
+#define	 mcsrr1 0x23b	/* mahcine check save/restore register 1 */
+#define	 mcsr	0x23c	/* machine check status register */
+#endif
+#define	 inv0	0x370	/* instruction cache normal victim 0 */
+#define	 inv1	0x371	/* instruction cache normal victim 1 */
+#define	 inv2	0x372	/* instruction cache normal victim 2 */
+#define	 inv3	0x373	/* instruction cache normal victim 3 */
+#define	 itv0	0x374	/* instruction cache transient victim 0 */
+#define	 itv1	0x375	/* instruction cache transient victim 1 */
+#define	 itv2	0x376	/* instruction cache transient victim 2 */
+#define	 itv3	0x377	/* instruction cache transient victim 3 */
+#define	 dnv0	0x390	/* data cache normal victim 0 */
+#define	 dnv1	0x391	/* data cache normal victim 1 */
+#define	 dnv2	0x392	/* data cache normal victim 2 */
+#define	 dnv3	0x393	/* data cache normal victim 3 */
+#define	 dtv0	0x394	/* data cache transient victim 0 */
+#define	 dtv1	0x395	/* data cache transient victim 1 */
+#define	 dtv2	0x396	/* data cache transient victim 2 */
+#define	 dtv3	0x397	/* data cache transient victim 3 */
+#define	 dvlim	0x398	/* data cache victim limit */
+#define	 ivlim	0x399	/* instruction cache victim limit */
+#define	 rstcfg 0x39b	/* reset configuration */
+#define	 dcdbtrl 0x39c	/* data cache debug tag register low */
+#define	 dcdbtrh 0x39d	/* data cache debug tag register high */
+#define	 icdbtrl 0x39e	/* instruction cache debug tag register low */
+#define	 icdbtrh 0x39f	/* instruction cache debug tag register high */
+#define	 mmucr	0x3b2	/* mmu control register */
+#define	 ccr0	0x3b3	/* core configuration register 0 */
+#define  ccr1  	0x378	/* core configuration for 440x5 only */
+#define	 icdbdr 0x3d3	/* instruction cache debug data register */
+#define	 dbdr	0x3f3	/* debug data register */
+
+/******************************************************************************
+ * DCRs & Related
+ ******************************************************************************/
+
+/*-----------------------------------------------------------------------------
+ | Clocking Controller
+ +----------------------------------------------------------------------------*/
+#define CLOCKING_DCR_BASE 0x0c
+#define clkcfga	 (CLOCKING_DCR_BASE+0x0)
+#define clkcfgd	 (CLOCKING_DCR_BASE+0x1)
+
+/* values for clkcfga register - indirect addressing of these regs */
+#define clk_clkukpd	0x0020
+#define clk_pllc	0x0040
+#define clk_plld	0x0060
+#define clk_primad	0x0080
+#define clk_primbd	0x00a0
+#define clk_opbd	0x00c0
+#define clk_perd	0x00e0
+#define clk_mald	0x0100
+#define clk_spcid   	0x0120
+#define clk_icfg	0x0140
+
+/* 440gx sdr register definations */
+#define SDR_DCR_BASE	0x0e
+#define sdrcfga		(SDR_DCR_BASE+0x0)
+#define sdrcfgd		(SDR_DCR_BASE+0x1)
+#define sdr_sdstp0	0x0020	    /* */
+#define sdr_sdstp1	0x0021	    /* */
+#define sdr_pinstp	0x0040
+#define sdr_sdcs	0x0060
+#define sdr_ecid0	0x0080
+#define sdr_ecid1	0x0081
+#define sdr_ecid2	0x0082
+#define sdr_jtag	0x00c0
+#define sdr_ddrdl	0x00e0
+#define sdr_ebc		0x0100
+#define sdr_uart0	0x0120	/* UART0 Config */
+#define sdr_uart1	0x0121	/* UART1 Config */
+#define sdr_uart2	0x0122	/* UART2 Config */
+#define sdr_uart3	0x0123	/* UART3 Config */
+#define sdr_cp440	0x0180
+#define sdr_xcr		0x01c0
+#define sdr_xpllc	0x01c1
+#define sdr_xplld	0x01c2
+#define sdr_srst	0x0200
+#define sdr_slpipe	0x0220
+#define sdr_amp0        0x0240  /* Override PLB4 prioritiy for up to 8 masters */
+#define sdr_amp1        0x0241  /* Override PLB3 prioritiy for up to 8 masters */
+#define sdr_mirq0	0x0260
+#define sdr_mirq1	0x0261
+#define sdr_maltbl	0x0280
+#define sdr_malrbl	0x02a0
+#define sdr_maltbs	0x02c0
+#define sdr_malrbs	0x02e0
+#define sdr_pci0        0x0300
+#define sdr_usb0        0x0320
+#define sdr_cust0	0x4000
+#define sdr_sdstp2	0x4001
+#define sdr_cust1	0x4002
+#define sdr_sdstp3	0x4003
+#define sdr_pfc0	0x4100	/* Pin Function 0 */
+#define sdr_pfc1	0x4101	/* Pin Function 1 */
+#define sdr_plbtr	0x4200
+#define sdr_mfr		0x4300	/* SDR0_MFR reg */
+
+/*-----------------------------------------------------------------------------
+ | SDRAM Controller
+ +----------------------------------------------------------------------------*/
+#define SDRAM_DCR_BASE 0x10
+#define memcfga	 (SDRAM_DCR_BASE+0x0)	/* Memory configuration address reg */
+#define memcfgd	 (SDRAM_DCR_BASE+0x1)	/* Memory configuration data reg    */
+
+/* values for memcfga register - indirect addressing of these regs	    */
+#define mem_besr0_clr	0x0000	/* bus error status reg 0 (clr)		    */
+#define mem_besr0_set	0x0004	/* bus error status reg 0 (set)		    */
+#define mem_besr1_clr	0x0008	/* bus error status reg 1 (clr)		    */
+#define mem_besr1_set	0x000c	/* bus error status reg 1 (set)		    */
+#define mem_bear	0x0010	/* bus error address reg		    */
+#define mem_mirq_clr	0x0011	/* bus master interrupt (clr)		    */
+#define mem_mirq_set	0x0012	/* bus master interrupt (set)		    */
+#define mem_slio	0x0018	/* ddr sdram slave interface options	    */
+#define mem_cfg0	0x0020	/* ddr sdram options 0			    */
+#define mem_cfg1	0x0021	/* ddr sdram options 1			    */
+#define mem_devopt	0x0022	/* ddr sdram device options		    */
+#define mem_mcsts	0x0024	/* memory controller status		    */
+#define mem_rtr		0x0030	/* refresh timer register		    */
+#define mem_pmit	0x0034	/* power management idle timer		    */
+#define mem_uabba	0x0038	/* plb UABus base address		    */
+#define mem_b0cr	0x0040	/* ddr sdram bank 0 configuration	    */
+#define mem_b1cr	0x0044	/* ddr sdram bank 1 configuration	    */
+#define mem_b2cr	0x0048	/* ddr sdram bank 2 configuration	    */
+#define mem_b3cr	0x004c	/* ddr sdram bank 3 configuration	    */
+#define mem_tr0		0x0080	/* sdram timing register 0		    */
+#define mem_tr1		0x0081	/* sdram timing register 1		    */
+#define mem_clktr	0x0082	/* ddr clock timing register		    */
+#define mem_wddctr	0x0083	/* write data/dm/dqs clock timing reg	    */
+#define mem_dlycal	0x0084	/* delay line calibration register	    */
+#define mem_eccesr	0x0098	/* ECC error status			    */
+
+/*-----------------------------------------------------------------------------
+ | External Bus Controller
+ +----------------------------------------------------------------------------*/
+#define EBC_DCR_BASE 0x12
+#define ebccfga (EBC_DCR_BASE+0x0)   /* External bus controller addr reg     */
+#define ebccfgd (EBC_DCR_BASE+0x1)   /* External bus controller data reg     */
+/* values for ebccfga register - indirect addressing of these regs */
+#define pb0cr		0x00	/* periph bank 0 config reg		*/
+#define pb1cr		0x01	/* periph bank 1 config reg		*/
+#define pb2cr		0x02	/* periph bank 2 config reg		*/
+#define pb3cr		0x03	/* periph bank 3 config reg		*/
+#define pb4cr		0x04	/* periph bank 4 config reg		*/
+#define pb5cr		0x05	/* periph bank 5 config reg		*/
+#define pb6cr		0x06	/* periph bank 6 config reg		*/
+#define pb7cr		0x07	/* periph bank 7 config reg		*/
+#define pb0ap		0x10	/* periph bank 0 access parameters	*/
+#define pb1ap		0x11	/* periph bank 1 access parameters	*/
+#define pb2ap		0x12	/* periph bank 2 access parameters	*/
+#define pb3ap		0x13	/* periph bank 3 access parameters	*/
+#define pb4ap		0x14	/* periph bank 4 access parameters	*/
+#define pb5ap		0x15	/* periph bank 5 access parameters	*/
+#define pb6ap		0x16	/* periph bank 6 access parameters	*/
+#define pb7ap		0x17	/* periph bank 7 access parameters	*/
+#define pbear		0x20	/* periph bus error addr reg		*/
+#define pbesr		0x21	/* periph bus error status reg		*/
+#define xbcfg		0x23	/* external bus configuration reg	*/
+#define xbcid		0x24	/* external bus core id reg		*/
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+
+/* PLB4 to PLB3 Bridge OUT */
+#define P4P3_DCR_BASE           0x020
+#define p4p3_esr0_read          (P4P3_DCR_BASE+0x0)
+#define p4p3_esr0_write         (P4P3_DCR_BASE+0x1)
+#define p4p3_eadr               (P4P3_DCR_BASE+0x2)
+#define p4p3_euadr              (P4P3_DCR_BASE+0x3)
+#define p4p3_esr1_read          (P4P3_DCR_BASE+0x4)
+#define p4p3_esr1_write         (P4P3_DCR_BASE+0x5)
+#define p4p3_confg              (P4P3_DCR_BASE+0x6)
+#define p4p3_pic                (P4P3_DCR_BASE+0x7)
+#define p4p3_peir               (P4P3_DCR_BASE+0x8)
+#define p4p3_rev                (P4P3_DCR_BASE+0xA)
+
+/* PLB3 to PLB4 Bridge IN */
+#define P3P4_DCR_BASE           0x030
+#define p3p4_esr0_read          (P3P4_DCR_BASE+0x0)
+#define p3p4_esr0_write         (P3P4_DCR_BASE+0x1)
+#define p3p4_eadr               (P3P4_DCR_BASE+0x2)
+#define p3p4_euadr              (P3P4_DCR_BASE+0x3)
+#define p3p4_esr1_read          (P3P4_DCR_BASE+0x4)
+#define p3p4_esr1_write         (P3P4_DCR_BASE+0x5)
+#define p3p4_confg              (P3P4_DCR_BASE+0x6)
+#define p3p4_pic                (P3P4_DCR_BASE+0x7)
+#define p3p4_peir               (P3P4_DCR_BASE+0x8)
+#define p3p4_rev                (P3P4_DCR_BASE+0xA)
+
+/* PLB3 Arbiter */
+#define PLB3_DCR_BASE           0x070
+#define plb3_revid              (PLB3_DCR_BASE+0x2)
+#define plb3_besr               (PLB3_DCR_BASE+0x3)
+#define plb3_bear               (PLB3_DCR_BASE+0x6)
+#define plb3_acr                (PLB3_DCR_BASE+0x7)
+
+/* PLB4 Arbiter - PowerPC440EP Pass1 */
+#define PLB4_DCR_BASE           0x080
+#define plb4_revid              (PLB4_DCR_BASE+0x2)
+#define plb4_acr                (PLB4_DCR_BASE+0x3)
+#define plb4_besr               (PLB4_DCR_BASE+0x4)
+#define plb4_bearl              (PLB4_DCR_BASE+0x6)
+#define plb4_bearh              (PLB4_DCR_BASE+0x7)
+
+/* Nebula PLB4 Arbiter - PowerPC440EP */
+#define PLB_ARBITER_BASE   0x80
+
+#define plb0_revid                (PLB_ARBITER_BASE+ 0x00)
+#define plb0_acr                  (PLB_ARBITER_BASE+ 0x01)
+#define   plb0_acr_ppm_mask             0xF0000000
+#define   plb0_acr_ppm_fixed            0x00000000
+#define   plb0_acr_ppm_fair             0xD0000000
+#define   plb0_acr_hbu_mask             0x08000000
+#define   plb0_acr_hbu_disabled         0x00000000
+#define   plb0_acr_hbu_enabled          0x08000000
+#define   plb0_acr_rdp_mask             0x06000000
+#define   plb0_acr_rdp_disabled         0x00000000
+#define   plb0_acr_rdp_2deep            0x02000000
+#define   plb0_acr_rdp_3deep            0x04000000
+#define   plb0_acr_rdp_4deep            0x06000000
+#define   plb0_acr_wrp_mask             0x01000000
+#define   plb0_acr_wrp_disabled         0x00000000
+#define   plb0_acr_wrp_2deep            0x01000000
+
+#define plb0_besrl                (PLB_ARBITER_BASE+ 0x02)
+#define plb0_besrh                (PLB_ARBITER_BASE+ 0x03)
+#define plb0_bearl                (PLB_ARBITER_BASE+ 0x04)
+#define plb0_bearh                (PLB_ARBITER_BASE+ 0x05)
+#define plb0_ccr                  (PLB_ARBITER_BASE+ 0x08)
+
+#define plb1_acr                  (PLB_ARBITER_BASE+ 0x09)
+#define   plb1_acr_ppm_mask             0xF0000000
+#define   plb1_acr_ppm_fixed            0x00000000
+#define   plb1_acr_ppm_fair             0xD0000000
+#define   plb1_acr_hbu_mask             0x08000000
+#define   plb1_acr_hbu_disabled         0x00000000
+#define   plb1_acr_hbu_enabled          0x08000000
+#define   plb1_acr_rdp_mask             0x06000000
+#define   plb1_acr_rdp_disabled         0x00000000
+#define   plb1_acr_rdp_2deep            0x02000000
+#define   plb1_acr_rdp_3deep            0x04000000
+#define   plb1_acr_rdp_4deep            0x06000000
+#define   plb1_acr_wrp_mask             0x01000000
+#define   plb1_acr_wrp_disabled         0x00000000
+#define   plb1_acr_wrp_2deep            0x01000000
+
+#define plb1_besrl                (PLB_ARBITER_BASE+ 0x0A)
+#define plb1_besrh                (PLB_ARBITER_BASE+ 0x0B)
+#define plb1_bearl                (PLB_ARBITER_BASE+ 0x0C)
+#define plb1_bearh                (PLB_ARBITER_BASE+ 0x0D)
+
+/* Pin Function Control Register 1 */
+#define SDR0_PFC1                    0x4101
+#define   SDR0_PFC1_U1ME_MASK         0x02000000    /* UART1 Mode Enable */
+#define   SDR0_PFC1_U1ME_DSR_DTR      0x00000000      /* UART1 in DSR/DTR Mode */
+#define   SDR0_PFC1_U1ME_CTS_RTS      0x02000000      /* UART1 in CTS/RTS Mode */
+#define   SDR0_PFC1_U0ME_MASK         0x00080000    /* UART0 Mode Enable */
+#define   SDR0_PFC1_U0ME_DSR_DTR      0x00000000      /* UART0 in DSR/DTR Mode */
+#define   SDR0_PFC1_U0ME_CTS_RTS      0x00080000      /* UART0 in CTS/RTS Mode */
+#define   SDR0_PFC1_U0IM_MASK         0x00040000    /* UART0 Interface Mode */
+#define   SDR0_PFC1_U0IM_8PINS        0x00000000      /* UART0 Interface Mode 8 pins */
+#define   SDR0_PFC1_U0IM_4PINS        0x00040000      /* UART0 Interface Mode 4 pins */
+#define   SDR0_PFC1_SIS_MASK          0x00020000    /* SCP or IIC1 Selection */
+#define   SDR0_PFC1_SIS_SCP_SEL       0x00000000      /* SCP Selected */
+#define   SDR0_PFC1_SIS_IIC1_SEL      0x00020000      /* IIC1 Selected */
+#define   SDR0_PFC1_UES_MASK          0x00010000    /* USB2D_RX_Active / EBC_Hold Req Selection */
+#define   SDR0_PFC1_UES_USB2D_SEL     0x00000000      /* USB2D_RX_Active Selected */
+#define   SDR0_PFC1_UES_EBCHR_SEL     0x00010000      /* EBC_Hold Req Selected */
+#define   SDR0_PFC1_DIS_MASK          0x00008000    /* DMA_Req(1) / UIC_IRQ(5) Selection */
+#define   SDR0_PFC1_DIS_DMAR_SEL      0x00000000      /* DMA_Req(1) Selected */
+#define   SDR0_PFC1_DIS_UICIRQ5_SEL   0x00008000      /* UIC_IRQ(5) Selected */
+#define   SDR0_PFC1_ERE_MASK          0x00004000    /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
+#define   SDR0_PFC1_ERE_EXTR_SEL      0x00000000      /* EBC Mast.Ext.Req.En. Selected */
+#define   SDR0_PFC1_ERE_GPIO0_27_SEL  0x00004000      /* GPIO0(27) Selected */
+#define   SDR0_PFC1_UPR_MASK          0x00002000    /* USB2 Device Packet Reject Selection */
+#define   SDR0_PFC1_UPR_DISABLE       0x00000000      /* USB2 Device Packet Reject Disable */
+#define   SDR0_PFC1_UPR_ENABLE        0x00002000      /* USB2 Device Packet Reject Enable */
+
+#define   SDR0_PFC1_PLB_PME_MASK      0x00001000    /* PLB3/PLB4 Perf. Monitor En. Selection */
+#define   SDR0_PFC1_PLB_PME_PLB3_SEL  0x00000000      /* PLB3 Performance Monitor Enable */
+#define   SDR0_PFC1_PLB_PME_PLB4_SEL  0x00001000      /* PLB3 Performance Monitor Enable */
+#define   SDR0_PFC1_GFGGI_MASK        0x0000000F    /* GPT Frequency Generation Gated In */
+
+/* USB Control Register */
+#define SDR0_USB0                    0x0320
+#define   SDR0_USB0_USB_DEVSEL_MASK   0x00000002    /* USB Device Selection */
+#define   SDR0_USB0_USB20D_DEVSEL     0x00000000      /* USB2.0 Device Selected */
+#define   SDR0_USB0_USB11D_DEVSEL     0x00000002      /* USB1.1 Device Selected */
+#define   SDR0_USB0_LEEN_MASK         0x00000001    /* Little Endian selection */
+#define   SDR0_USB0_LEEN_DISABLE      0x00000000      /* Little Endian Disable */
+#define   SDR0_USB0_LEEN_ENABLE       0x00000001      /* Little Endian Enable */
+
+/* CUST0 Customer Configuration Register0 */
+#define SDR0_CUST0                   0x4000
+#define   SDR0_CUST0_MUX_E_N_G_MASK   0xC0000000     /* Mux_Emac_NDFC_GPIO */
+#define   SDR0_CUST0_MUX_EMAC_SEL     0x40000000       /* Emac Selection */
+#define   SDR0_CUST0_MUX_NDFC_SEL     0x80000000       /* NDFC Selection */
+#define   SDR0_CUST0_MUX_GPIO_SEL     0xC0000000       /* GPIO Selection */
+
+#define   SDR0_CUST0_NDFC_EN_MASK     0x20000000     /* NDFC Enable Mask */
+#define   SDR0_CUST0_NDFC_ENABLE      0x20000000       /* NDFC Enable */
+#define   SDR0_CUST0_NDFC_DISABLE     0x00000000       /* NDFC Disable */
+
+#define   SDR0_CUST0_NDFC_BW_MASK     0x10000000     /* NDFC Boot Width */
+#define   SDR0_CUST0_NDFC_BW_16_BIT   0x10000000       /* NDFC Boot Width = 16 Bit */
+#define   SDR0_CUST0_NDFC_BW_8_BIT    0x00000000       /* NDFC Boot Width =  8 Bit */
+
+#define   SDR0_CUST0_NDFC_BP_MASK     0x0F000000     /* NDFC Boot Page */
+#define   SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
+#define   SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
+
+#define   SDR0_CUST0_NDFC_BAC_MASK    0x00C00000     /* NDFC Boot Address Cycle */
+#define   SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
+#define   SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
+
+#define   SDR0_CUST0_NDFC_ARE_MASK    0x00200000     /* NDFC Auto Read Enable */
+#define   SDR0_CUST0_NDFC_ARE_ENABLE  0x00200000       /* NDFC Auto Read Enable */
+#define   SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000       /* NDFC Auto Read Disable */
+
+#define   SDR0_CUST0_NRB_MASK         0x00100000     /* NDFC Ready / Busy */
+#define   SDR0_CUST0_NRB_BUSY         0x00100000       /* Busy */
+#define   SDR0_CUST0_NRB_READY        0x00000000       /* Ready */
+
+#define   SDR0_CUST0_NDRSC_MASK       0x0000FFF0     /* NDFC Device Reset Count Mask */
+#define   SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
+#define   SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
+
+#define   SDR0_CUST0_CHIPSELGAT_MASK  0x0000000F     /* Chip Select Gating Mask */
+#define   SDR0_CUST0_CHIPSELGAT_DIS   0x00000000       /* Chip Select Gating Disable */
+#define   SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F       /* All Chip Select Gating Enable */
+#define   SDR0_CUST0_CHIPSELGAT_EN0   0x00000008       /* Chip Select0 Gating Enable */
+#define   SDR0_CUST0_CHIPSELGAT_EN1   0x00000004       /* Chip Select1 Gating Enable */
+#define   SDR0_CUST0_CHIPSELGAT_EN2   0x00000002       /* Chip Select2 Gating Enable */
+#define   SDR0_CUST0_CHIPSELGAT_EN3   0x00000001       /* Chip Select3 Gating Enable */
+
+/* CUST1 Customer Configuration Register1 */
+#define   SDR0_CUST1                 0x4002
+#define   SDR0_CUST1_NDRSC_MASK       0xFFFF0000     /* NDRSC Device Read Count */
+#define   SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
+#define   SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
+
+/* Pin Function Control Register 0 */
+#define SDR0_PFC0                    0x4100
+#define   SDR0_PFC0_CPU_TR_EN_MASK    0x00000100    /* CPU Trace Enable Mask */
+#define   SDR0_PFC0_CPU_TRACE_EN      0x00000100      /* CPU Trace Enable */
+#define   SDR0_PFC0_CPU_TRACE_DIS     0x00000100      /* CPU Trace Disable */
+#define   SDR0_PFC0_CTE_ENCODE(n)    ((((unsigned long)(n))&0x01)<<8)
+#define   SDR0_PFC0_CTE_DECODE(n)    ((((unsigned long)(n))>>8)&0x01)
+
+/* Pin Function Control Register 1 */
+#define SDR0_PFC1                    0x4101
+#define   SDR0_PFC1_U1ME_MASK         0x02000000    /* UART1 Mode Enable */
+#define   SDR0_PFC1_U1ME_DSR_DTR      0x00000000      /* UART1 in DSR/DTR Mode */
+#define   SDR0_PFC1_U1ME_CTS_RTS      0x02000000      /* UART1 in CTS/RTS Mode */
+#define   SDR0_PFC1_U0ME_MASK         0x00080000    /* UART0 Mode Enable */
+#define   SDR0_PFC1_U0ME_DSR_DTR      0x00000000      /* UART0 in DSR/DTR Mode */
+#define   SDR0_PFC1_U0ME_CTS_RTS      0x00080000      /* UART0 in CTS/RTS Mode */
+#define   SDR0_PFC1_U0IM_MASK         0x00040000    /* UART0 Interface Mode */
+#define   SDR0_PFC1_U0IM_8PINS        0x00000000      /* UART0 Interface Mode 8 pins */
+#define   SDR0_PFC1_U0IM_4PINS        0x00040000      /* UART0 Interface Mode 4 pins */
+#define   SDR0_PFC1_SIS_MASK          0x00020000    /* SCP or IIC1 Selection */
+#define   SDR0_PFC1_SIS_SCP_SEL       0x00000000      /* SCP Selected */
+#define   SDR0_PFC1_SIS_IIC1_SEL      0x00020000      /* IIC1 Selected */
+#define   SDR0_PFC1_UES_MASK          0x00010000    /* USB2D_RX_Active / EBC_Hold Req Selection */
+#define   SDR0_PFC1_UES_USB2D_SEL     0x00000000      /* USB2D_RX_Active Selected */
+#define   SDR0_PFC1_UES_EBCHR_SEL     0x00010000      /* EBC_Hold Req Selected */
+#define   SDR0_PFC1_DIS_MASK          0x00008000    /* DMA_Req(1) / UIC_IRQ(5) Selection */
+#define   SDR0_PFC1_DIS_DMAR_SEL      0x00000000      /* DMA_Req(1) Selected */
+#define   SDR0_PFC1_DIS_UICIRQ5_SEL   0x00008000      /* UIC_IRQ(5) Selected */
+#define   SDR0_PFC1_ERE_MASK          0x00004000    /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
+#define   SDR0_PFC1_ERE_EXTR_SEL      0x00000000      /* EBC Mast.Ext.Req.En. Selected */
+#define   SDR0_PFC1_ERE_GPIO0_27_SEL  0x00004000      /* GPIO0(27) Selected */
+#define   SDR0_PFC1_UPR_MASK          0x00002000    /* USB2 Device Packet Reject Selection */
+#define   SDR0_PFC1_UPR_DISABLE       0x00000000      /* USB2 Device Packet Reject Disable */
+#define   SDR0_PFC1_UPR_ENABLE        0x00002000      /* USB2 Device Packet Reject Enable */
+
+#define   SDR0_PFC1_PLB_PME_MASK      0x00001000    /* PLB3/PLB4 Perf. Monitor En. Selection */
+#define   SDR0_PFC1_PLB_PME_PLB3_SEL  0x00000000      /* PLB3 Performance Monitor Enable */
+#define   SDR0_PFC1_PLB_PME_PLB4_SEL  0x00001000      /* PLB3 Performance Monitor Enable */
+#define   SDR0_PFC1_GFGGI_MASK        0x0000000F    /* GPT Frequency Generation Gated In */
+
+/* Miscealleneaous Function Reg. */
+#define SDR0_MFR                     0x4300
+#define   SDR0_MFR_ETH0_CLK_SEL        0x08000000   /* Ethernet0 Clock Select */
+#define   SDR0_MFR_ETH1_CLK_SEL        0x04000000   /* Ethernet1 Clock Select */
+#define   SDR0_MFR_ZMII_MODE_MASK      0x03000000   /* ZMII Mode Mask */
+#define   SDR0_MFR_ZMII_MODE_MII       0x00000000     /* ZMII Mode MII */
+#define   SDR0_MFR_ZMII_MODE_SMII      0x01000000     /* ZMII Mode SMII */
+#define   SDR0_MFR_ZMII_MODE_RMII_10M  0x02000000     /* ZMII Mode RMII - 10 Mbs */
+#define   SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000     /* ZMII Mode RMII - 100 Mbs */
+#define   SDR0_MFR_ZMII_MODE_BIT0      0x02000000     /* ZMII Mode Bit0 */
+#define   SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
+#define   SDR0_MFR_ZM_ENCODE(n)        ((((unsigned long)(n))&0x3)<<24)
+#define   SDR0_MFR_ZM_DECODE(n)        ((((unsigned long)(n))<<24)&0x3)
+
+#define   SDR0_MFR_ERRATA3_EN0         0x00800000
+#define   SDR0_MFR_ERRATA3_EN1         0x00400000
+#define   SDR0_MFR_PKT_REJ_MASK        0x00300000   /* Pkt Rej. Enable Mask */
+#define   SDR0_MFR_PKT_REJ_EN          0x00300000   /* Pkt Rej. Enable on both EMAC3 0-1 */
+#define   SDR0_MFR_PKT_REJ_EN0         0x00200000   /* Pkt Rej. Enable on EMAC3(0) */
+#define   SDR0_MFR_PKT_REJ_EN1         0x00100000   /* Pkt Rej. Enable on EMAC3(1) */
+#define   SDR0_MFR_PKT_REJ_POL         0x00080000   /* Packet Reject Polarity */
+
+#else
+
+/*-----------------------------------------------------------------------------
+ | Internal SRAM
+ +----------------------------------------------------------------------------*/
+#define ISRAM0_DCR_BASE 0x020
+#define isram0_sb0cr	(ISRAM0_DCR_BASE+0x00)	/* SRAM bank config 0*/
+#define isram0_sb1cr	(ISRAM0_DCR_BASE+0x01)	/* SRAM bank config 1*/
+#define isram0_sb2cr	(ISRAM0_DCR_BASE+0x02)	/* SRAM bank config 2*/
+#define isram0_sb3cr	(ISRAM0_DCR_BASE+0x03)	/* SRAM bank config 3*/
+#define isram0_bear	(ISRAM0_DCR_BASE+0x04)	/* SRAM bus error addr reg */
+#define isram0_besr0	(ISRAM0_DCR_BASE+0x05)	/* SRAM bus error status reg 0 */
+#define isram0_besr1	(ISRAM0_DCR_BASE+0x06)	/* SRAM bus error status reg 1 */
+#define isram0_pmeg	(ISRAM0_DCR_BASE+0x07)	/* SRAM power management */
+#define isram0_cid	(ISRAM0_DCR_BASE+0x08)	/* SRAM bus core id reg */
+#define isram0_revid	(ISRAM0_DCR_BASE+0x09)	/* SRAM bus revision id reg */
+#define isram0_dpc	(ISRAM0_DCR_BASE+0x0a)	/* SRAM data parity check reg */
+
+/*-----------------------------------------------------------------------------
+ | L2 Cache
+ +----------------------------------------------------------------------------*/
+#if defined (CONFIG_440GX) || defined(CONFIG_440SP)
+#define L2_CACHE_BASE	0x030
+#define l2_cache_cfg	(L2_CACHE_BASE+0x00)	/* L2 Cache Config	*/
+#define l2_cache_cmd	(L2_CACHE_BASE+0x01)	/* L2 Cache Command	*/
+#define l2_cache_addr	(L2_CACHE_BASE+0x02)	/* L2 Cache Address	*/
+#define l2_cache_data	(L2_CACHE_BASE+0x03)	/* L2 Cache Data	*/
+#define l2_cache_stat	(L2_CACHE_BASE+0x04)	/* L2 Cache Status	*/
+#define l2_cache_cver	(L2_CACHE_BASE+0x05)	/* L2 Cache Revision ID */
+#define l2_cache_snp0	(L2_CACHE_BASE+0x06)	/* L2 Cache Snoop reg 0 */
+#define l2_cache_snp1	(L2_CACHE_BASE+0x07)	/* L2 Cache Snoop reg 1 */
+
+#endif /* CONFIG_440GX */
+#endif /* !CONFIG_440EP !CONFIG_440GR*/
+
+/*-----------------------------------------------------------------------------
+ | On-Chip Buses
+ +----------------------------------------------------------------------------*/
+/* TODO: as needed */
+
+/*-----------------------------------------------------------------------------
+ | Clocking, Power Management and Chip Control
+ +----------------------------------------------------------------------------*/
+#define CNTRL_DCR_BASE 0x0b0
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#define cpc0_er		(CNTRL_DCR_BASE+0x00)	/* CPM enable register		*/
+#define cpc0_fr		(CNTRL_DCR_BASE+0x01)	/* CPM force register		*/
+#define cpc0_sr		(CNTRL_DCR_BASE+0x02)	/* CPM status register		*/
+#else
+#define cpc0_sr		(CNTRL_DCR_BASE+0x00)	/* CPM status register		*/
+#define cpc0_er		(CNTRL_DCR_BASE+0x01)	/* CPM enable register		*/
+#define cpc0_fr		(CNTRL_DCR_BASE+0x02)	/* CPM force register		*/
+#endif
+
+#define cpc0_sys0	(CNTRL_DCR_BASE+0x30)	/* System configuration reg 0	*/
+#define cpc0_sys1	(CNTRL_DCR_BASE+0x31)	/* System configuration reg 1	*/
+#define cpc0_cust0	(CNTRL_DCR_BASE+0x32)	/* Customer configuration reg 0 */
+#define cpc0_cust1	(CNTRL_DCR_BASE+0x33)	/* Customer configuration reg 1 */
+
+#define cpc0_strp0	(CNTRL_DCR_BASE+0x34)	/* Power-on config reg 0 (RO)	*/
+#define cpc0_strp1	(CNTRL_DCR_BASE+0x35)	/* Power-on config reg 1 (RO)	*/
+#define cpc0_strp2	(CNTRL_DCR_BASE+0x36)	/* Power-on config reg 2 (RO)	*/
+#define cpc0_strp3	(CNTRL_DCR_BASE+0x37)	/* Power-on config reg 3 (RO)	*/
+
+#define cpc0_gpio	(CNTRL_DCR_BASE+0x38)	/* GPIO config reg (440GP)	*/
+
+#define cntrl0		(CNTRL_DCR_BASE+0x3b)	/* Control 0 register		*/
+#define cntrl1		(CNTRL_DCR_BASE+0x3a)	/* Control 1 register		*/
+
+/*-----------------------------------------------------------------------------
+ | Universal interrupt controller
+ +----------------------------------------------------------------------------*/
+#define UIC0_DCR_BASE 0xc0
+#define uic0sr	(UIC0_DCR_BASE+0x0)   /* UIC0 status			   */
+#define uic0er	(UIC0_DCR_BASE+0x2)   /* UIC0 enable			   */
+#define uic0cr	(UIC0_DCR_BASE+0x3)   /* UIC0 critical			   */
+#define uic0pr	(UIC0_DCR_BASE+0x4)   /* UIC0 polarity			   */
+#define uic0tr	(UIC0_DCR_BASE+0x5)   /* UIC0 triggering		   */
+#define uic0msr (UIC0_DCR_BASE+0x6)   /* UIC0 masked status		   */
+#define uic0vr	(UIC0_DCR_BASE+0x7)   /* UIC0 vector			   */
+#define uic0vcr (UIC0_DCR_BASE+0x8)   /* UIC0 vector configuration	   */
+
+#define UIC1_DCR_BASE 0xd0
+#define uic1sr	(UIC1_DCR_BASE+0x0)   /* UIC1 status			   */
+#define uic1er	(UIC1_DCR_BASE+0x2)   /* UIC1 enable			   */
+#define uic1cr	(UIC1_DCR_BASE+0x3)   /* UIC1 critical			   */
+#define uic1pr	(UIC1_DCR_BASE+0x4)   /* UIC1 polarity			   */
+#define uic1tr	(UIC1_DCR_BASE+0x5)   /* UIC1 triggering		   */
+#define uic1msr (UIC1_DCR_BASE+0x6)   /* UIC1 masked status		   */
+#define uic1vr	(UIC1_DCR_BASE+0x7)   /* UIC1 vector			   */
+#define uic1vcr (UIC1_DCR_BASE+0x8)   /* UIC1 vector configuration	   */
+
+#if defined(CONFIG_440GX)
+#define UIC2_DCR_BASE 0x210
+#define uic2sr	(UIC2_DCR_BASE+0x0)   /* UIC2 status			   */
+#define uic2er	(UIC2_DCR_BASE+0x2)   /* UIC2 enable			   */
+#define uic2cr	(UIC2_DCR_BASE+0x3)   /* UIC2 critical			   */
+#define uic2pr	(UIC2_DCR_BASE+0x4)   /* UIC2 polarity			   */
+#define uic2tr	(UIC2_DCR_BASE+0x5)   /* UIC2 triggering		   */
+#define uic2msr (UIC2_DCR_BASE+0x6)   /* UIC2 masked status		   */
+#define uic2vr	(UIC2_DCR_BASE+0x7)   /* UIC2 vector			   */
+#define uic2vcr (UIC2_DCR_BASE+0x8)   /* UIC2 vector configuration	   */
+
+
+#define UIC_DCR_BASE 0x200
+#define uicb0sr	 (UIC_DCR_BASE+0x0)   /* UIC Base Status Register	   */
+#define uicb0er	 (UIC_DCR_BASE+0x2)   /* UIC Base enable		   */
+#define uicb0cr	 (UIC_DCR_BASE+0x3)   /* UIC Base critical		   */
+#define uicb0pr	 (UIC_DCR_BASE+0x4)   /* UIC Base polarity		   */
+#define uicb0tr	 (UIC_DCR_BASE+0x5)   /* UIC Base triggering		   */
+#define uicb0msr (UIC_DCR_BASE+0x6)   /* UIC Base masked status		   */
+#define uicb0vr	 (UIC_DCR_BASE+0x7)   /* UIC Base vector		   */
+#define uicb0vcr (UIC_DCR_BASE+0x8)   /* UIC Base vector configuration	   */
+#endif /* CONFIG_440GX */
+
+/* The following is for compatibility with 405 code */
+#define uicsr  uic0sr
+#define uicer  uic0er
+#define uiccr  uic0cr
+#define uicpr  uic0pr
+#define uictr  uic0tr
+#define uicmsr uic0msr
+#define uicvr  uic0vr
+#define uicvcr uic0vcr
+
+/*-----------------------------------------------------------------------------
+ | DMA
+ +----------------------------------------------------------------------------*/
+#define DMA_DCR_BASE 0x100
+#define dmacr0	(DMA_DCR_BASE+0x00)  /* DMA channel control register 0	     */
+#define dmact0	(DMA_DCR_BASE+0x01)  /* DMA count register 0		     */
+#define dmasah0 (DMA_DCR_BASE+0x02)  /* DMA source address high 0	     */
+#define dmasal0 (DMA_DCR_BASE+0x03)  /* DMA source address low 0	     */
+#define dmadah0 (DMA_DCR_BASE+0x04)  /* DMA destination address high 0	     */
+#define dmadal0 (DMA_DCR_BASE+0x05)  /* DMA destination address low 0	     */
+#define dmasgh0 (DMA_DCR_BASE+0x06)  /* DMA scatter/gather desc addr high 0  */
+#define dmasgl0 (DMA_DCR_BASE+0x07)  /* DMA scatter/gather desc addr low 0   */
+#define dmacr1	(DMA_DCR_BASE+0x08)  /* DMA channel control register 1	     */
+#define dmact1	(DMA_DCR_BASE+0x09)  /* DMA count register 1		     */
+#define dmasah1 (DMA_DCR_BASE+0x0a)  /* DMA source address high 1	     */
+#define dmasal1 (DMA_DCR_BASE+0x0b)  /* DMA source address low 1	     */
+#define dmadah1 (DMA_DCR_BASE+0x0c)  /* DMA destination address high 1	     */
+#define dmadal1 (DMA_DCR_BASE+0x0d)  /* DMA destination address low 1	     */
+#define dmasgh1 (DMA_DCR_BASE+0x0e)  /* DMA scatter/gather desc addr high 1  */
+#define dmasgl1 (DMA_DCR_BASE+0x0f)  /* DMA scatter/gather desc addr low 1   */
+#define dmacr2	(DMA_DCR_BASE+0x10)  /* DMA channel control register 2	     */
+#define dmact2	(DMA_DCR_BASE+0x11)  /* DMA count register 2		     */
+#define dmasah2 (DMA_DCR_BASE+0x12)  /* DMA source address high 2	     */
+#define dmasal2 (DMA_DCR_BASE+0x13)  /* DMA source address low 2	     */
+#define dmadah2 (DMA_DCR_BASE+0x14)  /* DMA destination address high 2	     */
+#define dmadal2 (DMA_DCR_BASE+0x15)  /* DMA destination address low 2	     */
+#define dmasgh2 (DMA_DCR_BASE+0x16)  /* DMA scatter/gather desc addr high 2  */
+#define dmasgl2 (DMA_DCR_BASE+0x17)  /* DMA scatter/gather desc addr low 2   */
+#define dmacr3	(DMA_DCR_BASE+0x18)  /* DMA channel control register 2	     */
+#define dmact3	(DMA_DCR_BASE+0x19)  /* DMA count register 2		     */
+#define dmasah3 (DMA_DCR_BASE+0x1a)  /* DMA source address high 2	     */
+#define dmasal3 (DMA_DCR_BASE+0x1b)  /* DMA source address low 2	     */
+#define dmadah3 (DMA_DCR_BASE+0x1c)  /* DMA destination address high 2	     */
+#define dmadal3 (DMA_DCR_BASE+0x1d)  /* DMA destination address low 2	     */
+#define dmasgh3 (DMA_DCR_BASE+0x1e)  /* DMA scatter/gather desc addr high 2  */
+#define dmasgl3 (DMA_DCR_BASE+0x1f)  /* DMA scatter/gather desc addr low 2   */
+#define dmasr	(DMA_DCR_BASE+0x20)  /* DMA status register		     */
+#define dmasgc	(DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
+#define dmaslp	(DMA_DCR_BASE+0x25)  /* DMA sleep mode register		     */
+#define dmapol	(DMA_DCR_BASE+0x26)  /* DMA polarity configuration register  */
+
+/*-----------------------------------------------------------------------------
+ | Memory Access Layer
+ +----------------------------------------------------------------------------*/
+#define MAL_DCR_BASE 0x180
+#define malmcr	    (MAL_DCR_BASE+0x00) /* MAL Config reg		    */
+#define malesr	    (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear)    */
+#define malier	    (MAL_DCR_BASE+0x02) /* Interrupt enable reg		    */
+#define maldbr	    (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only)	    */
+#define maltxcasr   (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)	    */
+#define maltxcarr   (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset)    */
+#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg  */
+#define maltxdeir   (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg	    */
+#define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg		    */
+#define maltxbattr  (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg	    */
+#define malrxcasr   (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)	    */
+#define malrxcarr   (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset)    */
+#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg  */
+#define malrxdeir   (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg	    */
+#define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg		    */
+#define malrxbattr  (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg	    */
+#define maltxctp0r  (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg   */
+#define maltxctp1r  (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg   */
+#define maltxctp2r  (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg   */
+#define maltxctp3r  (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg   */
+#define malrxctp0r  (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg   */
+#define malrxctp1r  (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg   */
+#if defined(CONFIG_440GX)
+#define malrxctp2r  (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg   */
+#define malrxctp3r  (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg   */
+#endif /* CONFIG_440GX */
+#define malrcbs0    (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg	    */
+#define malrcbs1    (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg	    */
+#if defined(CONFIG_440GX)
+#define malrcbs2    (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg	    */
+#define malrcbs3    (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg	    */
+#endif /* CONFIG_440GX */
+
+
+/*---------------------------------------------------------------------------+
+|  Universal interrupt controller 0 interrupts (UIC0)
++---------------------------------------------------------------------------*/
+#if defined(CONFIG_440SP)
+#define UIC_U0		0x80000000	/* UART 0			    */
+#define UIC_U1		0x40000000	/* UART 1			    */
+#define UIC_IIC0	0x20000000	/* IIC				    */
+#define UIC_IIC1	0x10000000	/* IIC				    */
+#define UIC_PIM		0x08000000	/* PCI0 inbound message		    */
+#define UIC_PCRW	0x04000000	/* PCI0 command write register	    */
+#define UIC_PPM		0x02000000	/* PCI0 power management	    */
+#define UIC_PVPD	0x01000000	/* PCI0 VPD Access		    */
+#define UIC_MSI0	0x00800000	/* PCI0 MSI level 0		    */
+#define UIC_P1IM	0x00400000	/* PCI1 Inbound Message		    */
+#define UIC_P1CRW	0x00200000	/* PCI1 command write register	    */
+#define UIC_P1PM	0x00100000	/* PCI1 power management	    */
+#define UIC_P1VPD	0x00080000	/* PCI1 VPD Access		    */
+#define UIC_P1MSI0	0x00040000	/* PCI1 MSI level 0		    */
+#define UIC_P2IM	0x00020000	/* PCI2 inbound message		    */
+#define UIC_P2CRW	0x00010000	/* PCI2 command register write	    */
+#define UIC_P2PM	0x00008000	/* PCI2 power management	    */
+#define UIC_P2VPD	0x00004000	/* PCI2 VPD access		    */
+#define UIC_P2MSI0	0x00002000	/* PCI2 MSI level 0		    */
+#define UIC_D0CPF	0x00001000	/* DMA0 command pointer		    */
+#define UIC_D0CSF	0x00000800	/* DMA0 command status		    */
+#define UIC_D1CPF	0x00000400	/* DMA1 command pointer		    */
+#define UIC_D1CSF	0x00000200	/* DMA1 command status		    */
+#define UIC_I2OID	0x00000100	/* I2O inbound doorbell		    */
+#define UIC_I2OPLF	0x00000080	/* I2O inbound post list	    */
+#define UIC_I2O0LL	0x00000040	/* I2O0 low latency PLB write	    */
+#define UIC_I2O1LL	0x00000020	/* I2O1 low latency PLB write	    */
+#define UIC_I2O0HB	0x00000010	/* I2O0 high bandwidth PLB write    */
+#define UIC_I2O1HB	0x00000008	/* I2O1 high bandwidth PLB write    */
+#define UIC_GPTCT	0x00000004	/* GPT count timer		    */
+#define UIC_UIC1NC	0x00000002	/* UIC1 non-critical interrupt	    */
+#define UIC_UIC1C	0x00000001	/* UIC1 critical interrupt	    */
+#else  /* CONFIG_440SP */
+#define UIC_U0		0x80000000	/* UART 0			    */
+#define UIC_U1		0x40000000	/* UART 1			    */
+#define UIC_IIC0	0x20000000	/* IIC				    */
+#define UIC_IIC1	0x10000000	/* IIC				    */
+#define UIC_PIM		0x08000000	/* PCI inbound message		    */
+#define UIC_PCRW	0x04000000	/* PCI command register write	    */
+#define UIC_PPM		0x02000000	/* PCI power management		    */
+#define UIC_MSI0	0x01000000	/* PCI MSI level 0		    */
+#define UIC_MSI1	0x00800000	/* PCI MSI level 1		    */
+#define UIC_MSI2	0x00400000	/* PCI MSI level 2		    */
+#define UIC_MTE		0x00200000	/* MAL TXEOB			    */
+#define UIC_MRE		0x00100000	/* MAL RXEOB			    */
+#define UIC_D0		0x00080000	/* DMA channel 0		    */
+#define UIC_D1		0x00040000	/* DMA channel 1		    */
+#define UIC_D2		0x00020000	/* DMA channel 2		    */
+#define UIC_D3		0x00010000	/* DMA channel 3		    */
+#define UIC_RSVD0	0x00008000	/* Reserved			    */
+#define UIC_RSVD1	0x00004000	/* Reserved			    */
+#define UIC_CT0		0x00002000	/* GPT compare timer 0		    */
+#define UIC_CT1		0x00001000	/* GPT compare timer 1		    */
+#define UIC_CT2		0x00000800	/* GPT compare timer 2		    */
+#define UIC_CT3		0x00000400	/* GPT compare timer 3		    */
+#define UIC_CT4		0x00000200	/* GPT compare timer 4		    */
+#define UIC_EIR0	0x00000100	/* External interrupt 0		    */
+#define UIC_EIR1	0x00000080	/* External interrupt 1		    */
+#define UIC_EIR2	0x00000040	/* External interrupt 2		    */
+#define UIC_EIR3	0x00000020	/* External interrupt 3		    */
+#define UIC_EIR4	0x00000010	/* External interrupt 4		    */
+#define UIC_EIR5	0x00000008	/* External interrupt 5		    */
+#define UIC_EIR6	0x00000004	/* External interrupt 6		    */
+#define UIC_UIC1NC	0x00000002	/* UIC1 non-critical interrupt	    */
+#define UIC_UIC1C	0x00000001	/* UIC1 critical interrupt	    */
+#endif /* CONFIG_440SP */
+
+/* For compatibility with 405 code */
+#define UIC_MAL_TXEOB	UIC_MTE
+#define UIC_MAL_RXEOB	UIC_MRE
+
+/*---------------------------------------------------------------------------+
+|  Universal interrupt controller 1 interrupts (UIC1)
++---------------------------------------------------------------------------*/
+#if defined(CONFIG_440SP)
+#define UIC_EIR0	0x80000000	/* External interrupt 0		    */
+#define UIC_MS		0x40000000	/* MAL SERR			    */
+#define UIC_MTDE	0x20000000	/* MAL TXDE			    */
+#define UIC_MRDE	0x10000000	/* MAL RXDE			    */
+#define UIC_DECE	0x08000000	/* DDR SDRAM correctible error	    */
+#define UIC_EBCO	0x04000000	/* EBCO interrupt status	    */
+#define UIC_MTE		0x02000000	/* MAL TXEOB			    */
+#define UIC_MRE		0x01000000	/* MAL RXEOB			    */
+#define UIC_P0MSI1	0x00800000	/* PCI0 MSI level 1		    */
+#define UIC_P1MSI1	0x00400000	/* PCI1 MSI level 1		    */
+#define UIC_P2MSI1	0x00200000	/* PCI2 MSI level 1		    */
+#define UIC_L2C		0x00100000	/* L2 cache			    */
+#define UIC_CT0		0x00080000	/* GPT compare timer 0		    */
+#define UIC_CT1		0x00040000	/* GPT compare timer 1		    */
+#define UIC_CT2		0x00020000	/* GPT compare timer 2		    */
+#define UIC_CT3		0x00010000	/* GPT compare timer 3		    */
+#define UIC_CT4		0x00008000	/* GPT compare timer 4		    */
+#define UIC_EIR1	0x00004000	/* External interrupt 1		    */
+#define UIC_EIR2	0x00002000	/* External interrupt 2		    */
+#define UIC_EIR3	0x00001000	/* External interrupt 3		    */
+#define UIC_EIR4	0x00000800	/* External interrupt 4		    */
+#define UIC_EIR5	0x00000400	/* External interrupt 5		    */
+#define UIC_DMAE	0x00000200	/* DMA error			    */
+#define UIC_I2OE	0x00000100	/* I2O error			    */
+#define UIC_SRE		0x00000080	/* Serial ROM error		    */
+#define UIC_P0AE	0x00000040	/* PCI0 asynchronous error	    */
+#define UIC_P1AE	0x00000020	/* PCI1 asynchronous error	    */
+#define UIC_P2AE	0x00000010	/* PCI2 asynchronous error	    */
+#define UIC_ETH0	0x00000008	/* Ethernet 0			    */
+#define UIC_EWU0	0x00000004	/* Ethernet 0 wakeup		    */
+#define UIC_ETH1	0x00000002	/* Reserved			    */
+#define UIC_XOR		0x00000001	/* XOR				    */
+#else /* CONFIG_440SP */
+#define UIC_MS		0x80000000	/* MAL SERR			    */
+#define UIC_MTDE	0x40000000	/* MAL TXDE			    */
+#define UIC_MRDE	0x20000000	/* MAL RXDE			    */
+#define UIC_DEUE	0x10000000	/* DDR SDRAM ECC uncorrectible error*/
+#define UIC_DECE	0x08000000	/* DDR SDRAM correctible error	    */
+#define UIC_EBCO	0x04000000	/* EBCO interrupt status	    */
+#define UIC_EBMI	0x02000000	/* EBMI interrupt status	    */
+#define UIC_OPB		0x01000000	/* OPB to PLB bridge interrupt stat */
+#define UIC_MSI3	0x00800000	/* PCI MSI level 3		    */
+#define UIC_MSI4	0x00400000	/* PCI MSI level 4		    */
+#define UIC_MSI5	0x00200000	/* PCI MSI level 5		    */
+#define UIC_MSI6	0x00100000	/* PCI MSI level 6		    */
+#define UIC_MSI7	0x00080000	/* PCI MSI level 7		    */
+#define UIC_MSI8	0x00040000	/* PCI MSI level 8		    */
+#define UIC_MSI9	0x00020000	/* PCI MSI level 9		    */
+#define UIC_MSI10	0x00010000	/* PCI MSI level 10		    */
+#define UIC_MSI11	0x00008000	/* PCI MSI level 11		    */
+#define UIC_PPMI	0x00004000	/* PPM interrupt status		    */
+#define UIC_EIR7	0x00002000	/* External interrupt 7		    */
+#define UIC_EIR8	0x00001000	/* External interrupt 8		    */
+#define UIC_EIR9	0x00000800	/* External interrupt 9		    */
+#define UIC_EIR10	0x00000400	/* External interrupt 10	    */
+#define UIC_EIR11	0x00000200	/* External interrupt 11	    */
+#define UIC_EIR12	0x00000100	/* External interrupt 12	    */
+#define UIC_SRE		0x00000080	/* Serial ROM error		    */
+#define UIC_RSVD2	0x00000040	/* Reserved			    */
+#define UIC_RSVD3	0x00000020	/* Reserved			    */
+#define UIC_PAE		0x00000010	/* PCI asynchronous error	    */
+#define UIC_ETH0	0x00000008	/* Ethernet 0			    */
+#define UIC_EWU0	0x00000004	/* Ethernet 0 wakeup		    */
+#define UIC_ETH1	0x00000002	/* Ethernet 1			    */
+#define UIC_EWU1	0x00000001	/* Ethernet 1 wakeup		    */
+#endif /* CONFIG_440SP */
+
+/* For compatibility with 405 code */
+#define UIC_MAL_SERR	UIC_MS
+#define UIC_MAL_TXDE	UIC_MTDE
+#define UIC_MAL_RXDE	UIC_MRDE
+#define UIC_ENET	UIC_ETH0
+
+/*---------------------------------------------------------------------------+
+|  Universal interrupt controller 2 interrupts (UIC2)
++---------------------------------------------------------------------------*/
+#if defined(CONFIG_440GX)
+#define UIC_ETH2	0x80000000	/* Ethernet 2			    */
+#define UIC_EWU2	0x40000000	/* Ethernet 2 wakeup		    */
+#define UIC_ETH3	0x20000000	/* Ethernet 3			    */
+#define UIC_EWU3	0x10000000	/* Ethernet 3 wakeup		    */
+#define UIC_TAH0	0x08000000	/* TAH 0			    */
+#define UIC_TAH1	0x04000000	/* TAH 1			    */
+#define UIC_IMUOBFQ	0x02000000	/* IMU outbound free queue	    */
+#define UIC_IMUIBPQ	0x01000000	/* IMU inbound post queue	    */
+#define UIC_IMUIRQDB	0x00800000	/* IMU irq doorbell		    */
+#define UIC_IMUIBDB	0x00400000	/* IMU inbound doorbell		    */
+#define UIC_IMUMSG0	0x00200000	/* IMU inbound message 0	    */
+#define UIC_IMUMSG1	0x00100000	/* IMU inbound message 1	    */
+#define UIC_IMUTO	0x00080000	/* IMU timeout			    */
+#define UIC_MSI12	0x00040000	/* PCI MSI level 12		    */
+#define UIC_MSI13	0x00020000	/* PCI MSI level 13		    */
+#define UIC_MSI14	0x00010000	/* PCI MSI level 14		    */
+#define UIC_MSI15	0x00008000	/* PCI MSI level 15		    */
+#define UIC_EIR13	0x00004000	/* External interrupt 13	    */
+#define UIC_EIR14	0x00002000	/* External interrupt 14	    */
+#define UIC_EIR15	0x00001000	/* External interrupt 15	    */
+#define UIC_EIR16	0x00000800	/* External interrupt 16	    */
+#define UIC_EIR17	0x00000400	/* External interrupt 17	    */
+#define UIC_PCIVPD	0x00000200	/* PCI VPD			    */
+#define UIC_L2C		0x00000100	/* L2 Cache			    */
+#define UIC_ETH2PCS	0x00000080	/* Ethernet 2 PCS		    */
+#define UIC_ETH3PCS	0x00000040	/* Ethernet 3 PCS		    */
+#define UIC_RSVD26	0x00000020	/* Reserved			    */
+#define UIC_RSVD27	0x00000010	/* Reserved			    */
+#define UIC_RSVD28	0x00000008	/* Reserved			    */
+#define UIC_RSVD29	0x00000004	/* Reserved			    */
+#define UIC_RSVD30	0x00000002	/* Reserved			    */
+#define UIC_RSVD31	0x00000001	/* Reserved			    */
+#endif	/* CONFIG_440GX */
+
+/*---------------------------------------------------------------------------+
+|  Universal interrupt controller Base 0 interrupts (UICB0)
++---------------------------------------------------------------------------*/
+#if defined(CONFIG_440GX)
+#define UICB0_UIC0CI	0x80000000	/* UIC0 Critical Interrupt	    */
+#define UICB0_UIC0NCI	0x40000000	/* UIC0 Noncritical Interrupt	    */
+#define UICB0_UIC1CI	0x20000000	/* UIC1 Critical Interrupt	    */
+#define UICB0_UIC1NCI	0x10000000	/* UIC1 Noncritical Interrupt	    */
+#define UICB0_UIC2CI	0x08000000	/* UIC2 Critical Interrupt	    */
+#define UICB0_UIC2NCI	0x04000000	/* UIC2 Noncritical Interrupt	    */
+
+#define UICB0_ALL		(UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
+						 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
+#endif /* CONFIG_440GX */
+
+/*-----------------------------------------------------------------------------+
+|  External Bus Controller Bit Settings
++-----------------------------------------------------------------------------*/
+#define EBC_CFGADDR_MASK		0x0000003F
+
+#define EBC_BXCR_BAS_ENCODE(n)	((((unsigned long)(n))&0xFFF00000)<<0)
+#define EBC_BXCR_BS_MASK		0x000E0000
+#define EBC_BXCR_BS_1MB			0x00000000
+#define EBC_BXCR_BS_2MB			0x00020000
+#define EBC_BXCR_BS_4MB			0x00040000
+#define EBC_BXCR_BS_8MB			0x00060000
+#define EBC_BXCR_BS_16MB		0x00080000
+#define EBC_BXCR_BS_32MB		0x000A0000
+#define EBC_BXCR_BS_64MB		0x000C0000
+#define EBC_BXCR_BS_128MB		0x000E0000
+#define EBC_BXCR_BU_MASK		0x00018000
+#define EBC_BXCR_BU_R			0x00008000
+#define EBC_BXCR_BU_W			0x00010000
+#define EBC_BXCR_BU_RW			0x00018000
+#define EBC_BXCR_BW_MASK		0x00006000
+#define EBC_BXCR_BW_8BIT		0x00000000
+#define EBC_BXCR_BW_16BIT		0x00002000
+#define EBC_BXCR_BW_32BIT		0x00006000
+#define EBC_BXAP_BME_ENABLED		0x80000000
+#define EBC_BXAP_BME_DISABLED		0x00000000
+#define EBC_BXAP_TWT_ENCODE(n)		((((unsigned long)(n))&0xFF)<<23)
+#define EBC_BXAP_BCE_DISABLE		0x00000000
+#define EBC_BXAP_BCE_ENABLE		0x00400000
+#define EBC_BXAP_BCT_MASK		0x00300000
+#define EBC_BXAP_BCT_2TRANS		0x00000000
+#define EBC_BXAP_BCT_4TRANS		0x00100000
+#define EBC_BXAP_BCT_8TRANS		0x00200000
+#define EBC_BXAP_BCT_16TRANS		0x00300000
+#define EBC_BXAP_CSN_ENCODE(n)		((((unsigned long)(n))&0x3)<<18)
+#define EBC_BXAP_OEN_ENCODE(n)		((((unsigned long)(n))&0x3)<<16)
+#define EBC_BXAP_WBN_ENCODE(n)		((((unsigned long)(n))&0x3)<<14)
+#define EBC_BXAP_WBF_ENCODE(n)		((((unsigned long)(n))&0x3)<<12)
+#define EBC_BXAP_TH_ENCODE(n)		((((unsigned long)(n))&0x7)<<9)
+#define EBC_BXAP_RE_ENABLED		0x00000100
+#define EBC_BXAP_RE_DISABLED		0x00000000
+#define EBC_BXAP_SOR_DELAYED		0x00000000
+#define EBC_BXAP_SOR_NONDELAYED		0x00000080
+#define EBC_BXAP_BEM_WRITEONLY		0x00000000
+#define EBC_BXAP_BEM_RW			0x00000040
+#define EBC_BXAP_PEN_DISABLED		0x00000000
+
+#define EBC_CFG_LE_MASK			0x80000000
+#define EBC_CFG_LE_UNLOCK		0x00000000
+#define EBC_CFG_LE_LOCK			0x80000000
+#define EBC_CFG_PTD_MASK		0x40000000
+#define EBC_CFG_PTD_ENABLE		0x00000000
+#define EBC_CFG_PTD_DISABLE		0x40000000
+#define EBC_CFG_RTC_MASK		0x38000000
+#define EBC_CFG_RTC_16PERCLK		0x00000000
+#define EBC_CFG_RTC_32PERCLK		0x08000000
+#define EBC_CFG_RTC_64PERCLK		0x10000000
+#define EBC_CFG_RTC_128PERCLK		0x18000000
+#define EBC_CFG_RTC_256PERCLK		0x20000000
+#define EBC_CFG_RTC_512PERCLK		0x28000000
+#define EBC_CFG_RTC_1024PERCLK		0x30000000
+#define EBC_CFG_RTC_2048PERCLK		0x38000000
+#define EBC_CFG_ATC_MASK		0x04000000
+#define EBC_CFG_ATC_HI			0x00000000
+#define EBC_CFG_ATC_PREVIOUS		0x04000000
+#define EBC_CFG_DTC_MASK		0x02000000
+#define EBC_CFG_DTC_HI			0x00000000
+#define EBC_CFG_DTC_PREVIOUS		0x02000000
+#define EBC_CFG_CTC_MASK		0x01000000
+#define EBC_CFG_CTC_HI			0x00000000
+#define EBC_CFG_CTC_PREVIOUS		0x01000000
+#define EBC_CFG_OEO_MASK		0x00800000
+#define EBC_CFG_OEO_HI			0x00000000
+#define EBC_CFG_OEO_PREVIOUS		0x00800000
+#define EBC_CFG_EMC_MASK		0x00400000
+#define EBC_CFG_EMC_NONDEFAULT		0x00000000
+#define EBC_CFG_EMC_DEFAULT		0x00400000
+#define EBC_CFG_PME_MASK		0x00200000
+#define EBC_CFG_PME_DISABLE		0x00000000
+#define EBC_CFG_PME_ENABLE		0x00200000
+#define EBC_CFG_PMT_MASK		0x001F0000
+#define EBC_CFG_PMT_ENCODE(n)		((((unsigned long)(n))&0x1F)<<12)
+#define EBC_CFG_PR_MASK			0x0000C000
+#define EBC_CFG_PR_16			0x00000000
+#define EBC_CFG_PR_32			0x00004000
+#define EBC_CFG_PR_64			0x00008000
+#define EBC_CFG_PR_128			0x0000C000
+
+/*-----------------------------------------------------------------------------+
+|  SDR0 Bit Settings
++-----------------------------------------------------------------------------*/
+#define SDR0_SDCS_SDD			(0x80000000 >> 31)
+
+#if defined(CONFIG_440GP)
+#define CPC0_STRP1_PAE_MASK		(0x80000000 >> 11)
+#define CPC0_STRP1_PISE_MASK		(0x80000000 >> 13)
+#endif /* defined(CONFIG_440GP) */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 13)
+#define SDR0_SDSTP1_PISE_MASK		(0x80000000 >> 15)
+#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define SDR0_SDSTP1_PAE_MASK		(0x80000000 >> 21)
+#define SDR0_SDSTP1_PAME_MASK		(0x80000000 >> 27)
+#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+
+#define SDR0_UARTX_UXICS_MASK		0xF0000000
+#define SDR0_UARTX_UXICS_PLB		0x20000000
+#define SDR0_UARTX_UXEC_MASK		0x00800000
+#define SDR0_UARTX_UXEC_INT		0x00000000
+#define SDR0_UARTX_UXEC_EXT		0x00800000
+#define SDR0_UARTX_UXDTE_MASK		0x00400000
+#define SDR0_UARTX_UXDTE_DISABLE	0x00000000
+#define SDR0_UARTX_UXDTE_ENABLE		0x00400000
+#define SDR0_UARTX_UXDRE_MASK		0x00200000
+#define SDR0_UARTX_UXDRE_DISABLE	0x00000000
+#define SDR0_UARTX_UXDRE_ENABLE		0x00200000
+#define SDR0_UARTX_UXDC_MASK		0x00100000
+#define SDR0_UARTX_UXDC_NOTCLEARED	0x00000000
+#define SDR0_UARTX_UXDC_CLEARED		0x00100000
+#define SDR0_UARTX_UXDIV_MASK		0x000000FF
+#define SDR0_UARTX_UXDIV_ENCODE(n)	((((unsigned long)(n))&0xFF)<<0)
+#define SDR0_UARTX_UXDIV_DECODE(n)	((((((unsigned long)(n))>>0)-1)&0xFF)+1)
+
+#define SDR0_CPU440_EARV_MASK		0x30000000
+#define SDR0_CPU440_EARV_EBC		0x10000000
+#define SDR0_CPU440_EARV_PCI		0x20000000
+#define SDR0_CPU440_EARV_ENCODE(n)	((((unsigned long)(n))&0x03)<<28)
+#define SDR0_CPU440_EARV_DECODE(n)	((((unsigned long)(n))>>28)&0x03)
+#define SDR0_CPU440_NTO1_MASK		0x00000002
+#define SDR0_CPU440_NTO1_NTOP		0x00000000
+#define SDR0_CPU440_NTO1_NTO1		0x00000002
+#define SDR0_CPU440_NTO1_ENCODE(n)	((((unsigned long)(n))&0x01)<<1)
+#define SDR0_CPU440_NTO1_DECODE(n)	((((unsigned long)(n))>>1)&0x01)
+
+#define SDR0_XCR_PAE_MASK		0x80000000
+#define SDR0_XCR_PAE_DISABLE		0x00000000
+#define SDR0_XCR_PAE_ENABLE		0x80000000
+#define SDR0_XCR_PAE_ENCODE(n)		((((unsigned long)(n))&0x01)<<31)
+#define SDR0_XCR_PAE_DECODE(n)		((((unsigned long)(n))>>31)&0x01)
+#define SDR0_XCR_PHCE_MASK		0x40000000
+#define SDR0_XCR_PHCE_DISABLE		0x00000000
+#define SDR0_XCR_PHCE_ENABLE		0x40000000
+#define SDR0_XCR_PHCE_ENCODE(n)		((((unsigned long)(n))&0x01)<<30)
+#define SDR0_XCR_PHCE_DECODE(n)		((((unsigned long)(n))>>30)&0x01)
+#define SDR0_XCR_PISE_MASK		0x20000000
+#define SDR0_XCR_PISE_DISABLE		0x00000000
+#define SDR0_XCR_PISE_ENABLE		0x20000000
+#define SDR0_XCR_PISE_ENCODE(n)		((((unsigned long)(n))&0x01)<<29)
+#define SDR0_XCR_PISE_DECODE(n)		((((unsigned long)(n))>>29)&0x01)
+#define SDR0_XCR_PCWE_MASK		0x10000000
+#define SDR0_XCR_PCWE_DISABLE		0x00000000
+#define SDR0_XCR_PCWE_ENABLE		0x10000000
+#define SDR0_XCR_PCWE_ENCODE(n)		((((unsigned long)(n))&0x01)<<28)
+#define SDR0_XCR_PCWE_DECODE(n)		((((unsigned long)(n))>>28)&0x01)
+#define SDR0_XCR_PPIM_MASK		0x0F000000
+#define SDR0_XCR_PPIM_ENCODE(n)		((((unsigned long)(n))&0x0F)<<24)
+#define SDR0_XCR_PPIM_DECODE(n)		((((unsigned long)(n))>>24)&0x0F)
+#define SDR0_XCR_PR64E_MASK		0x00800000
+#define SDR0_XCR_PR64E_DISABLE		0x00000000
+#define SDR0_XCR_PR64E_ENABLE		0x00800000
+#define SDR0_XCR_PR64E_ENCODE(n)	((((unsigned long)(n))&0x01)<<23)
+#define SDR0_XCR_PR64E_DECODE(n)	((((unsigned long)(n))>>23)&0x01)
+#define SDR0_XCR_PXFS_MASK		0x00600000
+#define SDR0_XCR_PXFS_HIGH		0x00000000
+#define SDR0_XCR_PXFS_MED		0x00200000
+#define SDR0_XCR_PXFS_LOW		0x00400000
+#define SDR0_XCR_PXFS_ENCODE(n)		((((unsigned long)(n))&0x03)<<21)
+#define SDR0_XCR_PXFS_DECODE(n)		((((unsigned long)(n))>>21)&0x03)
+#define SDR0_XCR_PDM_MASK		0x00000040
+#define SDR0_XCR_PDM_MULTIPOINT		0x00000000
+#define SDR0_XCR_PDM_P2P		0x00000040
+#define SDR0_XCR_PDM_ENCODE(n)		((((unsigned long)(n))&0x01)<<19)
+#define SDR0_XCR_PDM_DECODE(n)		((((unsigned long)(n))>>19)&0x01)
+
+#define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000
+#define SDR0_PFC0_GEIE_MASK		0x00003E00
+#define SDR0_PFC0_GEIE_TRE		0x00003E00
+#define SDR0_PFC0_GEIE_NOTRE		0x00000000
+#define SDR0_PFC0_TRE_MASK		0x00000100
+#define SDR0_PFC0_TRE_DISABLE		0x00000000
+#define SDR0_PFC0_TRE_ENABLE		0x00000100
+#define SDR0_PFC0_TRE_ENCODE(n)		((((unsigned long)(n))&0x01)<<8)
+#define SDR0_PFC0_TRE_DECODE(n)		((((unsigned long)(n))>>8)&0x01)
+
+#define SDR0_PFC1_UART1_DSR_CTS_MASK	0x02000000
+#define SDR0_PFC1_EPS_MASK		0x01C00000
+#define SDR0_PFC1_EPS_GROUP0		0x00000000
+#define SDR0_PFC1_EPS_GROUP1		0x00400000
+#define SDR0_PFC1_EPS_GROUP2		0x00800000
+#define SDR0_PFC1_EPS_GROUP3		0x00C00000
+#define SDR0_PFC1_EPS_GROUP4		0x01000000
+#define SDR0_PFC1_EPS_GROUP5		0x01400000
+#define SDR0_PFC1_EPS_GROUP6		0x01800000
+#define SDR0_PFC1_EPS_GROUP7		0x01C00000
+#define SDR0_PFC1_EPS_ENCODE(n)		((((unsigned long)(n))&0x07)<<22)
+#define SDR0_PFC1_EPS_DECODE(n)		((((unsigned long)(n))>>22)&0x07)
+#define SDR0_PFC1_RMII_MASK		0x00200000
+#define SDR0_PFC1_RMII_100MBIT		0x00000000
+#define SDR0_PFC1_RMII_10MBIT		0x00200000
+#define SDR0_PFC1_RMII_ENCODE(n)	((((unsigned long)(n))&0x01)<<21)
+#define SDR0_PFC1_RMII_DECODE(n)	((((unsigned long)(n))>>21)&0x01)
+#define SDR0_PFC1_CTEMS_MASK		0x00100000
+#define SDR0_PFC1_CTEMS_EMS		0x00000000
+#define SDR0_PFC1_CTEMS_CPUTRACE	0x00100000
+
+#define SDR0_MFR_TAH0_MASK		0x80000000
+#define SDR0_MFR_TAH0_ENABLE		0x00000000
+#define SDR0_MFR_TAH0_DISABLE		0x80000000
+#define SDR0_MFR_TAH1_MASK		0x40000000
+#define SDR0_MFR_TAH1_ENABLE		0x00000000
+#define SDR0_MFR_TAH1_DISABLE		0x40000000
+#define SDR0_MFR_PCM_MASK		0x20000000
+#define SDR0_MFR_PCM_PPC440GX		0x00000000
+#define SDR0_MFR_PCM_PPC440GP		0x20000000
+#define SDR0_MFR_ECS_MASK		0x10000000
+#define SDR0_MFR_ECS_INTERNAL		0x10000000
+
+#define SDR0_MFR_ETH0_CLK_SEL        0x08000000   /* Ethernet0 Clock Select */
+#define SDR0_MFR_ETH1_CLK_SEL        0x04000000   /* Ethernet1 Clock Select */
+#define SDR0_MFR_ZMII_MODE_MASK      0x03000000   /* ZMII Mode Mask   */
+#define SDR0_MFR_ZMII_MODE_MII       0x00000000     /* ZMII Mode MII  */
+#define SDR0_MFR_ZMII_MODE_SMII      0x01000000     /* ZMII Mode SMII */
+#define SDR0_MFR_ZMII_MODE_RMII_10M  0x02000000     /* ZMII Mode RMII - 10 Mbs   */
+#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000     /* ZMII Mode RMII - 100 Mbs  */
+#define SDR0_MFR_ZMII_MODE_BIT0      0x02000000     /* ZMII Mode Bit0 */
+#define SDR0_MFR_ZMII_MODE_BIT1      0x01000000     /* ZMII Mode Bit1 */
+#define SDR0_MFR_ERRATA3_EN0         0x00800000
+#define SDR0_MFR_ERRATA3_EN1         0x00400000
+#define SDR0_MFR_PKT_REJ_MASK        0x00300000   /* Pkt Rej. Enable Mask */
+#define SDR0_MFR_PKT_REJ_EN          0x00300000   /* Pkt Rej. Enable on both EMAC3 0-1 */
+#define SDR0_MFR_PKT_REJ_EN0         0x00200000   /* Pkt Rej. Enable on EMAC3(0) */
+#define SDR0_MFR_PKT_REJ_EN1         0x00100000   /* Pkt Rej. Enable on EMAC3(1) */
+#define SDR0_MFR_PKT_REJ_POL         0x00080000   /* Packet Reject Polarity      */
+
+#define SDR0_SRST_BGO			0x80000000
+#define SDR0_SRST_PLB			0x40000000
+#define SDR0_SRST_EBC			0x20000000
+#define SDR0_SRST_OPB			0x10000000
+#define SDR0_SRST_UART0			0x08000000
+#define SDR0_SRST_UART1			0x04000000
+#define SDR0_SRST_IIC0			0x02000000
+#define SDR0_SRST_IIC1			0x01000000
+#define SDR0_SRST_GPIO			0x00800000
+#define SDR0_SRST_GPT			0x00400000
+#define SDR0_SRST_DMC			0x00200000
+#define SDR0_SRST_PCI			0x00100000
+#define SDR0_SRST_EMAC0			0x00080000
+#define SDR0_SRST_EMAC1			0x00040000
+#define SDR0_SRST_CPM			0x00020000
+#define SDR0_SRST_IMU			0x00010000
+#define SDR0_SRST_UIC01			0x00008000
+#define SDR0_SRST_UICB2			0x00004000
+#define SDR0_SRST_SRAM			0x00002000
+#define SDR0_SRST_EBM			0x00001000
+#define SDR0_SRST_BGI			0x00000800
+#define SDR0_SRST_DMA			0x00000400
+#define SDR0_SRST_DMAC			0x00000200
+#define SDR0_SRST_MAL			0x00000100
+#define SDR0_SRST_ZMII			0x00000080
+#define SDR0_SRST_GPTR			0x00000040
+#define SDR0_SRST_PPM			0x00000020
+#define SDR0_SRST_EMAC2			0x00000010
+#define SDR0_SRST_EMAC3			0x00000008
+#define SDR0_SRST_RGMII			0x00000001
+
+/*-----------------------------------------------------------------------------+
+|  Clocking
++-----------------------------------------------------------------------------*/
+#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP)
+#define PLLSYS0_TUNE_MASK	0xffc00000	/* PLL TUNE bits	    */
+#define PLLSYS0_FB_DIV_MASK	0x003c0000	/* Feedback divisor	    */
+#define PLLSYS0_FWD_DIV_A_MASK	0x00038000	/* Forward divisor A	    */
+#define PLLSYS0_FWD_DIV_B_MASK	0x00007000	/* Forward divisor B	    */
+#define PLLSYS0_OPB_DIV_MASK	0x00000c00	/* OPB divisor		    */
+#define PLLSYS0_EPB_DIV_MASK	0x00000300	/* EPB divisor		    */
+#define PLLSYS0_EXTSL_MASK	0x00000080	/* PerClk feedback path	    */
+#define PLLSYS0_RW_MASK		0x00000060	/* ROM width		    */
+#define PLLSYS0_RL_MASK		0x00000010	/* ROM location		    */
+#define PLLSYS0_ZMII_SEL_MASK	0x0000000c	/* ZMII selection	    */
+#define PLLSYS0_BYPASS_MASK	0x00000002	/* Bypass PLL		    */
+#define PLLSYS0_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio	    */
+
+#define PLL_VCO_FREQ_MIN	500		/* Min VCO freq (MHz)	    */
+#define PLL_VCO_FREQ_MAX	1000		/* Max VCO freq (MHz)	    */
+#define PLL_CPU_FREQ_MAX	400		/* Max CPU freq (MHz)	    */
+#define PLL_PLB_FREQ_MAX	133		/* Max PLB freq (MHz)	    */
+#else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
+#define PLLSYS0_ENG_MASK	0x80000000	/* 0 = SysClk, 1 = PLL VCO */
+#define PLLSYS0_SRC_MASK	0x40000000	/* 0 = PLL A, 1 = PLL B */
+#define PLLSYS0_SEL_MASK	0x38000000	/* 0 = PLL, 1 = CPU, 5 = PerClk */
+#define PLLSYS0_TUNE_MASK	0x07fe0000	/* PLL Tune bits */
+#define PLLSYS0_FB_DIV_MASK	0x0001f000	/* Feedback divisor */
+#define PLLSYS0_FWD_DIV_A_MASK	0x00000f00	/* Fwd Div A */
+#define PLLSYS0_FWD_DIV_B_MASK	0x000000e0	/* Fwd Div B */
+#define PLLSYS0_PRI_DIV_B_MASK	0x0000001c	/* PLL Primary Divisor B */
+#define PLLSYS0_OPB_DIV_MASK	0x00000003	/* OPB Divisor */
+
+#define PLLC_ENG_MASK       0x20000000  /* PLL primary forward divisor source   */
+#define PLLC_SRC_MASK       0x20000000  /* PLL feedback source   */
+#define PLLD_FBDV_MASK      0x1f000000  /* PLL Feedback Divisor  */
+#define PLLD_FWDVA_MASK     0x000f0000  /* PLL Forward Divisor A */
+#define PLLD_FWDVB_MASK     0x00000700  /* PLL Forward Divisor B */
+#define PLLD_LFBDV_MASK     0x0000003f  /* PLL Local Feedback Divisor */
+
+#define OPBDDV_MASK         0x03000000  /* OPB Clock Divisor Register */
+#define PERDV_MASK          0x07000000  /* Periferal Clock Divisor */
+#define PRADV_MASK          0x07000000  /* Primary Divisor A */
+#define PRBDV_MASK          0x07000000  /* Primary Divisor B */
+#define SPCID_MASK          0x03000000  /* Sync PCI Divisor  */
+
+#define PLL_VCO_FREQ_MIN	500		/* Min VCO freq (MHz)	    */
+#define PLL_VCO_FREQ_MAX	1000		/* Max VCO freq (MHz)	    */
+#define PLL_CPU_FREQ_MAX	400		/* Max CPU freq (MHz)	    */
+#define PLL_PLB_FREQ_MAX	133		/* Max PLB freq (MHz)	    */
+
+/* Strap 1 Register */
+#define PLLSYS1_LF_DIV_MASK	0xfc000000	/* PLL Local Feedback Divisor */
+#define PLLSYS1_PERCLK_DIV_MASK 0x03000000	/* Peripheral Clk Divisor */
+#define PLLSYS1_MAL_DIV_MASK	0x00c00000	/* MAL Clk Divisor */
+#define PLLSYS1_RW_MASK		0x00300000	/* ROM width */
+#define PLLSYS1_EAR_MASK	0x00080000	/* ERAP Addres reset vector */
+#define PLLSYS1_PAE_MASK	0x00040000	/* PCI arbitor enable */
+#define PLLSYS1_PCHE_MASK	0x00020000	/* PCI host config enable */
+#define PLLSYS1_PISE_MASK	0x00010000	/* PCI init seq. enable */
+#define PLLSYS1_PCWE_MASK	0x00008000	/* PCI local cpu wait enable */
+#define PLLSYS1_PPIM_MASK	0x00007800	/* PCI inbound map */
+#define PLLSYS1_PR64E_MASK	0x00000400	/* PCI init Req64 enable */
+#define PLLSYS1_PXFS_MASK	0x00000300	/* PCI-X Freq Sel */
+#define PLLSYS1_RSVD_MASK	0x00000080	/* RSVD */
+#define PLLSYS1_PDM_MASK	0x00000040	/* PCI-X Driver Mode */
+#define PLLSYS1_EPS_MASK	0x00000038	/* Ethernet Pin Select */
+#define PLLSYS1_RMII_MASK	0x00000004	/* RMII Mode */
+#define PLLSYS1_TRE_MASK	0x00000002	/* GPIO Trace Enable */
+#define PLLSYS1_NTO1_MASK	0x00000001	/* CPU:PLB N-to-1 ratio */
+#endif /* CONFIG_440GX */
+
+/*-----------------------------------------------------------------------------
+| IIC Register Offsets
+'----------------------------------------------------------------------------*/
+#define IICMDBUF		0x00
+#define IICSDBUF		0x02
+#define IICLMADR		0x04
+#define IICHMADR		0x05
+#define IICCNTL			0x06
+#define IICMDCNTL		0x07
+#define IICSTS			0x08
+#define IICEXTSTS		0x09
+#define IICLSADR		0x0A
+#define IICHSADR		0x0B
+#define IICCLKDIV		0x0C
+#define IICINTRMSK		0x0D
+#define IICXFRCNT		0x0E
+#define IICXTCNTLSS		0x0F
+#define IICDIRECTCNTL		0x10
+
+/*-----------------------------------------------------------------------------
+| UART Register Offsets
+'----------------------------------------------------------------------------*/
+#define DATA_REG		0x00
+#define DL_LSB			0x00
+#define DL_MSB			0x01
+#define INT_ENABLE		0x01
+#define FIFO_CONTROL		0x02
+#define LINE_CONTROL		0x03
+#define MODEM_CONTROL		0x04
+#define LINE_STATUS		0x05
+#define MODEM_STATUS		0x06
+#define SCRATCH			0x07
+
+/*-----------------------------------------------------------------------------
+| PCI Internal Registers et. al. (accessed via plb)
++----------------------------------------------------------------------------*/
+#define PCIX0_CFGADR		(CFG_PCI_BASE + 0x0ec00000)
+#define PCIX0_CFGDATA		(CFG_PCI_BASE + 0x0ec00004)
+#define PCIX0_CFGBASE		(CFG_PCI_BASE + 0x0ec80000)
+#define PCIX0_IOBASE		(CFG_PCI_BASE + 0x08000000)
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+
+/* PCI Local Configuration Registers
+   --------------------------------- */
+#define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000)    /* Real => 0x0EF400000 */
+
+/* PCI Master Local Configuration Registers */
+#define PCIX0_PMM0LA         (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
+#define PCIX0_PMM0MA         (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
+#define PCIX0_PMM0PCILA      (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
+#define PCIX0_PMM0PCIHA      (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
+#define PCIX0_PMM1LA         (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
+#define PCIX0_PMM1MA         (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
+#define PCIX0_PMM1PCILA      (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
+#define PCIX0_PMM1PCIHA      (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
+#define PCIX0_PMM2LA         (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
+#define PCIX0_PMM2MA         (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
+#define PCIX0_PMM2PCILA      (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
+#define PCIX0_PMM2PCIHA      (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
+
+/* PCI Target Local Configuration Registers */
+#define PCIX0_PTM1MS         (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
+#define PCIX0_PTM1LA         (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
+#define PCIX0_PTM2MS         (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
+#define PCIX0_PTM2LA         (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
+
+#else
+
+#define PCIX0_VENDID		(PCIX0_CFGBASE + PCI_VENDOR_ID )
+#define PCIX0_DEVID		(PCIX0_CFGBASE + PCI_DEVICE_ID )
+#define PCIX0_CMD		(PCIX0_CFGBASE + PCI_COMMAND )
+#define PCIX0_STATUS		(PCIX0_CFGBASE + PCI_STATUS )
+#define PCIX0_REVID		(PCIX0_CFGBASE + PCI_REVISION_ID )
+#define PCIX0_CLS		(PCIX0_CFGBASE + PCI_CLASS_CODE)
+#define PCIX0_CACHELS		(PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
+#define PCIX0_LATTIM		(PCIX0_CFGBASE + PCI_LATENCY_TIMER )
+#define PCIX0_HDTYPE		(PCIX0_CFGBASE + PCI_HEADER_TYPE )
+#define PCIX0_BIST		(PCIX0_CFGBASE + PCI_BIST )
+#define PCIX0_BAR0		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
+#define PCIX0_BAR1		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
+#define PCIX0_BAR2		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
+#define PCIX0_BAR3		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
+#define PCIX0_BAR4		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
+#define PCIX0_BAR5		(PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
+#define PCIX0_CISPTR		(PCIX0_CFGBASE + PCI_CARDBUS_CIS )
+#define PCIX0_SBSYSVID		(PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
+#define PCIX0_SBSYSID		(PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
+#define PCIX0_EROMBA		(PCIX0_CFGBASE + PCI_ROM_ADDRESS )
+#define PCIX0_CAP		(PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
+#define PCIX0_RES0		(PCIX0_CFGBASE + 0x0035 )
+#define PCIX0_RES1		(PCIX0_CFGBASE + 0x0036 )
+#define PCIX0_RES2		(PCIX0_CFGBASE + 0x0038 )
+#define PCIX0_INTLN		(PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
+#define PCIX0_INTPN		(PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
+#define PCIX0_MINGNT		(PCIX0_CFGBASE + PCI_MIN_GNT )
+#define PCIX0_MAXLTNCY		(PCIX0_CFGBASE + PCI_MAX_LAT )
+
+#define PCIX0_BRDGOPT1		(PCIX0_CFGBASE + 0x0040)
+#define PCIX0_BRDGOPT2		(PCIX0_CFGBASE + 0x0044)
+
+#define PCIX0_POM0LAL		(PCIX0_CFGBASE + 0x0068)
+#define PCIX0_POM0LAH		(PCIX0_CFGBASE + 0x006c)
+#define PCIX0_POM0SA		(PCIX0_CFGBASE + 0x0070)
+#define PCIX0_POM0PCIAL		(PCIX0_CFGBASE + 0x0074)
+#define PCIX0_POM0PCIAH		(PCIX0_CFGBASE + 0x0078)
+#define PCIX0_POM1LAL		(PCIX0_CFGBASE + 0x007c)
+#define PCIX0_POM1LAH		(PCIX0_CFGBASE + 0x0080)
+#define PCIX0_POM1SA		(PCIX0_CFGBASE + 0x0084)
+#define PCIX0_POM1PCIAL		(PCIX0_CFGBASE + 0x0088)
+#define PCIX0_POM1PCIAH		(PCIX0_CFGBASE + 0x008c)
+#define PCIX0_POM2SA		(PCIX0_CFGBASE + 0x0090)
+
+#define PCIX0_PIM0SA		(PCIX0_CFGBASE + 0x0098)
+#define PCIX0_PIM0LAL		(PCIX0_CFGBASE + 0x009c)
+#define PCIX0_PIM0LAH		(PCIX0_CFGBASE + 0x00a0)
+#define PCIX0_PIM1SA		(PCIX0_CFGBASE + 0x00a4)
+#define PCIX0_PIM1LAL		(PCIX0_CFGBASE + 0x00a8)
+#define PCIX0_PIM1LAH		(PCIX0_CFGBASE + 0x00ac)
+#define PCIX0_PIM2SA		(PCIX0_CFGBASE + 0x00b0)
+#define PCIX0_PIM2LAL		(PCIX0_CFGBASE + 0x00b4)
+#define PCIX0_PIM2LAH		(PCIX0_CFGBASE + 0x00b8)
+
+#define PCIX0_STS		(PCIX0_CFGBASE + 0x00e0)
+
+#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
+
+/******************************************************************************
+ * GPIO macro register defines
+ ******************************************************************************/
+#if defined(CONFIG_440GP)
+#define GPIO_BASE0             (CFG_PERIPHERAL_BASE+0x00000700)
+
+#define GPIO0_OR               (GPIO_BASE0+0x0)
+#define GPIO0_TCR              (GPIO_BASE0+0x4)
+#define GPIO0_ODR              (GPIO_BASE0+0x18)
+#define GPIO0_IR               (GPIO_BASE0+0x1C)
+#endif /* CONFIG_440GP */
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define GPIO_BASE0             (CFG_PERIPHERAL_BASE+0x00000B00)
+#define GPIO_BASE1             (CFG_PERIPHERAL_BASE+0x00000C00)
+
+#define GPIO0_OR               (GPIO_BASE0+0x0)
+#define GPIO0_TCR              (GPIO_BASE0+0x4)
+#define GPIO0_OSRL             (GPIO_BASE0+0x8)
+#define GPIO0_OSRH             (GPIO_BASE0+0xC)
+#define GPIO0_TSRL             (GPIO_BASE0+0x10)
+#define GPIO0_TSRH             (GPIO_BASE0+0x14)
+#define GPIO0_ODR              (GPIO_BASE0+0x18)
+#define GPIO0_IR               (GPIO_BASE0+0x1C)
+#define GPIO0_RR1              (GPIO_BASE0+0x20)
+#define GPIO0_RR2              (GPIO_BASE0+0x24)
+#define GPIO0_RR3	       (GPIO_BASE0+0x28)
+#define GPIO0_ISR1L            (GPIO_BASE0+0x30)
+#define GPIO0_ISR1H            (GPIO_BASE0+0x34)
+#define GPIO0_ISR2L            (GPIO_BASE0+0x38)
+#define GPIO0_ISR2H            (GPIO_BASE0+0x3C)
+#define GPIO0_ISR3L            (GPIO_BASE0+0x40)
+#define GPIO0_ISR3H            (GPIO_BASE0+0x44)
+
+#define GPIO1_OR               (GPIO_BASE1+0x0)
+#define GPIO1_TCR              (GPIO_BASE1+0x4)
+#define GPIO1_OSRL             (GPIO_BASE1+0x8)
+#define GPIO1_OSRH             (GPIO_BASE1+0xC)
+#define GPIO1_TSRL             (GPIO_BASE1+0x10)
+#define GPIO1_TSRH             (GPIO_BASE1+0x14)
+#define GPIO1_ODR              (GPIO_BASE1+0x18)
+#define GPIO1_IR               (GPIO_BASE1+0x1C)
+#define GPIO1_RR1              (GPIO_BASE1+0x20)
+#define GPIO1_RR2              (GPIO_BASE1+0x24)
+#define GPIO1_RR3              (GPIO_BASE1+0x28)
+#define GPIO1_ISR1L            (GPIO_BASE1+0x30)
+#define GPIO1_ISR1H            (GPIO_BASE1+0x34)
+#define GPIO1_ISR2L            (GPIO_BASE1+0x38)
+#define GPIO1_ISR2H            (GPIO_BASE1+0x3C)
+#define GPIO1_ISR3L            (GPIO_BASE1+0x40)
+#define GPIO1_ISR3H            (GPIO_BASE1+0x44)
+#endif
+
+/*
+ * Macros for accessing the indirect EBC registers
+ */
+#define mtebc(reg, data)	mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
+#define mfebc(reg, data)	mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
+
+/*
+ * Macros for accessing the indirect SDRAM controller registers
+ */
+#define mtsdram(reg, data)	mtdcr(memcfga,reg);mtdcr(memcfgd,data)
+#define mfsdram(reg, data)	mtdcr(memcfga,reg);data = mfdcr(memcfgd)
+
+/*
+ * Macros for accessing the indirect clocking controller registers
+ */
+#define mtclk(reg, data)	mtdcr(clkcfga,reg);mtdcr(clkcfgd,data)
+#define mfclk(reg, data)	mtdcr(clkcfga,reg);data = mfdcr(clkcfgd)
+
+/*
+ * Macros for accessing the sdr controller registers
+ */
+#define mtsdr(reg, data)	mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data)
+#define mfsdr(reg, data)	mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd)
+
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+	unsigned long pllFwdDivA;
+	unsigned long pllFwdDivB;
+	unsigned long pllFbkDiv;
+	unsigned long pllOpbDiv;
+	unsigned long pllPciDiv;
+	unsigned long pllExtBusDiv;
+	unsigned long freqVCOMhz;	/* in MHz			   */
+	unsigned long freqProcessor;
+	unsigned long freqTmrClk;
+	unsigned long freqPLB;
+	unsigned long freqOPB;
+	unsigned long freqEPB;
+	unsigned long freqPCI;
+	unsigned long pciIntArbEn;            /* Internal PCI arbiter is enabled */
+	unsigned long pciClkSync;             /* PCI clock is synchronous        */
+} PPC440_SYS_INFO;
+
+#endif	/* _ASMLANGUAGE */
+
+#define RESET_VECTOR		0xfffffffc
+#define CACHELINE_MASK		(CFG_CACHELINE_SIZE - 1) /* Address mask for		*/
+							 /* cache line aligned data.	*/
+
+#endif	/* __PPC440_H__ */
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
new file mode 100755
index 0000000..67759c7
--- /dev/null
+++ b/include/ppc4xx.h
@@ -0,0 +1,32 @@
+/*----------------------------------------------------------------------------+
+|
+|       This source code has been made available to you by IBM on an AS-IS
+|       basis.  Anyone receiving this source is licensed under IBM
+|       copyrights to use it in any way he or she deems fit, including
+|       copying it, modifying it, compiling it, and redistributing it either
+|       with or without modifications.  No license under IBM patents or
+|       patent applications is to be implied by the copyright license.
+|
+|       Any user of this software should understand that IBM cannot provide
+|       technical support for this software and will not be responsible for
+|       any consequences resulting from the use of this software.
+|
+|       Any person who transfers this source code or any derivative work
+|       must include the IBM copyright notice, this paragraph, and the
+|       preceding two paragraphs in the transferred software.
+|
+|       COPYRIGHT   I B M   CORPORATION 1999
+|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+
+#ifndef	__PPC4XX_H__
+#define __PPC4XX_H__
+
+
+#if defined(CONFIG_440)
+#include <ppc440.h>
+#else
+#include <ppc405.h>
+#endif
+
+#endif	/* __PPC4XX_H__ */
diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
new file mode 100755
index 0000000..d6d33b6
--- /dev/null
+++ b/include/ppc4xx_enet.h
@@ -0,0 +1,478 @@
+/*----------------------------------------------------------------------------+
+|
+|	This source code has been made available to you by IBM on an AS-IS
+|	basis.	Anyone receiving this source is licensed under IBM
+|	copyrights to use it in any way he or she deems fit, including
+|	copying it, modifying it, compiling it, and redistributing it either
+|	with or without modifications.	No license under IBM patents or
+|	patent applications is to be implied by the copyright license.
+|
+|	Any user of this software should understand that IBM cannot provide
+|	technical support for this software and will not be responsible for
+|	any consequences resulting from the use of this software.
+|
+|	Any person who transfers this source code or any derivative work
+|	must include the IBM copyright notice, this paragraph, and the
+|	preceding two paragraphs in the transferred software.
+|
+|	COPYRIGHT   I B M   CORPORATION 1999
+|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+|
+|  File Name:	enetemac.h
+|
+|  Function:	Header file for the EMAC3 macro on the 405GP.
+|
+|  Author:	Mark Wisner
+|
+|  Change Activity-
+|
+|  Date	       Description of Change					   BY
+|  ---------   ---------------------					   ---
+|  29-Apr-99   Created							   MKW
+|
++----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------+
+|  19-Nov-03   Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
+|	       ported to handle 440GP and 440GX multiple EMACs
++----------------------------------------------------------------------------*/
+
+#ifndef _PPC4XX_ENET_H_
+#define _PPC4XX_ENET_H_
+
+#include <net.h>
+#include "405_mal.h"
+
+
+/*-----------------------------------------------------------------------------+
+| General enternet defines.  802 frames are not supported.
++-----------------------------------------------------------------------------*/
+#define ENET_ADDR_LENGTH		6
+#define ENET_ARPTYPE			0x806
+#define ARP_REQUEST			1
+#define ARP_REPLY			2
+#define ENET_IPTYPE			0x800
+#define ARP_CACHE_SIZE			5
+
+#define NUM_TX_BUFF 1
+#define NUM_RX_BUFF PKTBUFSRX
+
+struct enet_frame {
+   unsigned char	dest_addr[ENET_ADDR_LENGTH];
+   unsigned char	source_addr[ENET_ADDR_LENGTH];
+   unsigned short	type;
+   unsigned char	enet_data[1];
+};
+
+struct arp_entry {
+   unsigned long	inet_address;
+   unsigned char	mac_address[ENET_ADDR_LENGTH];
+   unsigned long	valid;
+   unsigned long	sec;
+   unsigned long	nsec;
+};
+
+
+/* Statistic Areas */
+#define MAX_ERR_LOG 10
+
+typedef struct emac_stats_st{	/* Statistic Block */
+	int data_len_err;
+	int rx_frames;
+	int rx;
+	int rx_prot_err;
+	int int_err;
+	int pkts_tx;
+	int pkts_rx;
+	int pkts_handled;
+	short tx_err_log[MAX_ERR_LOG];
+	short rx_err_log[MAX_ERR_LOG];
+} EMAC_STATS_ST, *EMAC_STATS_PST;
+
+/* Structure containing variables used by the shared code (4xx_enet.c) */
+typedef struct emac_4xx_hw_st {
+    uint32_t		hw_addr;		/* EMAC offset */
+    uint32_t		tah_addr;		/* TAH offset */
+    uint32_t		phy_id;
+    uint32_t		phy_addr;
+    uint32_t		original_fc;
+    uint32_t		txcw;
+    uint32_t		autoneg_failed;
+    uint32_t		emac_ier;
+    volatile mal_desc_t *tx;
+    volatile mal_desc_t *rx;
+    bd_t		*bis;	/* for eth_init upon mal error */
+    mal_desc_t		*alloc_tx_buf;
+    mal_desc_t		*alloc_rx_buf;
+    char		*txbuf_ptr;
+    uint16_t		devnum;
+    int			get_link_status;
+    int			tbi_compatibility_en;
+    int			tbi_compatibility_on;
+    int			fc_send_xon;
+    int			report_tx_early;
+    int			first_init;
+    int			tx_err_index;
+    int			rx_err_index;
+    int			rx_slot;			/* MAL Receive Slot */
+    int			rx_i_index;		/* Receive Interrupt Queue Index */
+    int			rx_u_index;		/* Receive User Queue Index */
+    int			tx_slot;			/* MAL Transmit Slot */
+    int			tx_i_index;		/* Transmit Interrupt Queue Index */
+    int			tx_u_index;		/* Transmit User Queue Index */
+    int			rx_ready[NUM_RX_BUFF];	/* Receive Ready Queue */
+    int			tx_run[NUM_TX_BUFF];	/* Transmit Running Queue */
+    int			is_receiving;	/* sync with eth interrupt */
+    int			print_speed;	/* print speed message upon start */
+    EMAC_STATS_ST	stats;
+} EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
+
+
+#if defined(CONFIG_440GX)
+#define EMAC_NUM_DEV	    4
+#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) &&	\
+	defined(CONFIG_NET_MULTI) &&			\
+	!defined(CONFIG_440SP)
+#define EMAC_NUM_DEV	    2
+#else
+#define EMAC_NUM_DEV	    1
+#endif
+
+
+/*ZMII Bridge Register addresses */
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0D00)
+#else
+#define ZMII_BASE			(CFG_PERIPHERAL_BASE + 0x0780)
+#endif
+#define ZMII_FER			(ZMII_BASE)
+#define ZMII_SSR			(ZMII_BASE + 4)
+#define ZMII_SMIISR			(ZMII_BASE + 8)
+
+#define ZMII_RMII			0x22000000
+#define ZMII_MDI0			0x80000000
+
+/* ZMII FER Register Bit Definitions */
+#define ZMII_FER_MDI		(0x8)
+#define ZMII_FER_SMII		(0x4)
+#define ZMII_FER_RMII		(0x2)
+#define ZMII_FER_MII		(0x1)
+
+#define ZMII_FER_RSVD11		(0x00200000)
+#define ZMII_FER_RSVD10		(0x00100000)
+#define ZMII_FER_RSVD14_31	(0x0003FFFF)
+
+#define ZMII_FER_V(__x)		(((3 - __x) * 4) + 16)
+
+
+/* ZMII Speed Selection Register Bit Definitions */
+#define ZMII_SSR_SCI		(0x4)
+#define ZMII_SSR_FSS		(0x2)
+#define ZMII_SSR_SP		(0x1)
+#define ZMII_SSR_RSVD16_31	(0x0000FFFF)
+
+#define ZMII_SSR_V(__x)		(((3 - __x) * 4) + 16)
+
+
+/* ZMII SMII Status Register Bit Definitions */
+#define ZMII_SMIISR_E1		(0x80)
+#define ZMII_SMIISR_EC		(0x40)
+#define ZMII_SMIISR_EN		(0x20)
+#define ZMII_SMIISR_EJ		(0x10)
+#define ZMII_SMIISR_EL		(0x08)
+#define ZMII_SMIISR_ED		(0x04)
+#define ZMII_SMIISR_ES		(0x02)
+#define ZMII_SMIISR_EF		(0x01)
+
+#define ZMII_SMIISR_V(__x)	((3 - __x) * 8)
+
+/* RGMII Register Addresses */
+#define RGMII_BASE		(CFG_PERIPHERAL_BASE + 0x0790)
+#define RGMII_FER		(RGMII_BASE + 0x00)
+#define RGMII_SSR		(RGMII_BASE + 0x04)
+
+/* RGMII Function Enable (FER) Register Bit Definitions */
+/* Note: for EMAC 2 and 3 only, 440GX only */
+#define RGMII_FER_DIS		(0x00)
+#define RGMII_FER_RTBI		(0x04)
+#define RGMII_FER_RGMII		(0x05)
+#define RGMII_FER_TBI		(0x06)
+#define RGMII_FER_GMII		(0x07)
+
+#define RGMII_FER_V(__x)	((__x - 2) * 4)
+
+/* RGMII Speed Selection Register Bit Definitions */
+#define RGMII_SSR_SP_10MBPS	(0x00)
+#define RGMII_SSR_SP_100MBPS	(0x02)
+#define RGMII_SSR_SP_1000MBPS	(0x04)
+
+#define RGMII_SSR_V(__x)	((__x -2) * 8)
+
+
+/*---------------------------------------------------------------------------+
+|  TCP/IP Acceleration Hardware (TAH) 440GX Only
++---------------------------------------------------------------------------*/
+#if defined(CONFIG_440GX)
+#define TAH_BASE		(CFG_PERIPHERAL_BASE + 0x0B50)
+#define TAH_REVID		(TAH_BASE + 0x0)    /* Revision ID (RO)*/
+#define TAH_MR			(TAH_BASE + 0x10)   /* Mode Register (R/W) */
+#define TAH_SSR0		(TAH_BASE + 0x14)   /* Segment Size Reg 0 (R/W) */
+#define TAH_SSR1		(TAH_BASE + 0x18)   /* Segment Size Reg 1 (R/W) */
+#define TAH_SSR2		(TAH_BASE + 0x1C)   /* Segment Size Reg 2 (R/W) */
+#define TAH_SSR3		(TAH_BASE + 0x20)   /* Segment Size Reg 3 (R/W) */
+#define TAH_SSR4		(TAH_BASE + 0x24)   /* Segment Size Reg 4 (R/W) */
+#define TAH_SSR5		(TAH_BASE + 0x28)   /* Segment Size Reg 5 (R/W) */
+#define TAH_TSR			(TAH_BASE + 0x2C)   /* Transmit Status Register (RO) */
+
+/* TAH Revision */
+#define TAH_REV_RN_M		(0x000FFF00)	    /* Revision Number */
+#define TAH_REV_BN_M		(0x000000FF)	    /* Branch Revision Number */
+
+#define TAH_REV_RN_V		(8)
+#define TAH_REV_BN_V		(0)
+
+/* TAH Mode Register */
+#define TAH_MR_CVR		(0x80000000)	    /* Checksum verification on RX */
+#define TAH_MR_SR		(0x40000000)	    /* Software reset */
+#define TAH_MR_ST		(0x3F000000)	    /* Send Threshold */
+#define TAH_MR_TFS		(0x00E00000)	    /* Transmit FIFO size */
+#define TAH_MR_DTFP		(0x00100000)	    /* Disable TX FIFO parity */
+#define TAH_MR_DIG		(0x00080000)	    /* Disable interrupt generation */
+#define TAH_MR_RSVD		(0x0007FFFF)	    /* Reserved */
+
+#define TAH_MR_ST_V		(20)
+#define TAH_MR_TFS_V		(17)
+
+#define TAH_MR_TFS_2K		(0x1)		    /* Transmit FIFO size 2Kbyte */
+#define TAH_MR_TFS_4K		(0x2)		    /* Transmit FIFO size 4Kbyte */
+#define TAH_MR_TFS_6K		(0x3)		    /* Transmit FIFO size 6Kbyte */
+#define TAH_MR_TFS_8K		(0x4)		    /* Transmit FIFO size 8Kbyte */
+#define TAH_MR_TFS_10K		(0x5)		    /* Transmit FIFO size 10Kbyte (max)*/
+
+
+/* TAH Segment Size Registers 0:5 */
+#define TAH_SSR_RSVD0		(0xC0000000)	    /* Reserved */
+#define TAH_SSR_SS		(0x3FFE0000)	    /* Segment size in multiples of 2 */
+#define TAH_SSR_RSVD1		(0x0001FFFF)	    /* Reserved */
+
+/* TAH Transmit Status Register */
+#define TAH_TSR_TFTS		(0x80000000)	    /* Transmit FIFO too small */
+#define TAH_TSR_UH		(0x40000000)	    /* Unrecognized header */
+#define TAH_TSR_NIPF		(0x20000000)	    /* Not IPv4 */
+#define TAH_TSR_IPOP		(0x10000000)	    /* IP option present */
+#define TAH_TSR_NISF		(0x08000000)	    /* No IEEE SNAP format */
+#define TAH_TSR_ILTS		(0x04000000)	    /* IP length too short */
+#define TAH_TSR_IPFP		(0x02000000)	    /* IP fragment present */
+#define TAH_TSR_UP		(0x01000000)	    /* Unsupported protocol */
+#define TAH_TSR_TFP		(0x00800000)	    /* TCP flags present */
+#define TAH_TSR_SUDP		(0x00400000)	    /* Segmentation for UDP */
+#define TAH_TSR_DLM		(0x00200000)	    /* Data length mismatch */
+#define TAH_TSR_SIEEE		(0x00100000)	    /* Segmentation for IEEE */
+#define TAH_TSR_TFPE		(0x00080000)	    /* Transmit FIFO parity error */
+#define TAH_TSR_SSTS		(0x00040000)	    /* Segment size too small */
+#define TAH_TSR_RSVD		(0x0003FFFF)	    /* Reserved */
+#endif /* CONFIG_440GX */
+
+
+/* Ethernet MAC Regsiter Addresses */
+#if defined(CONFIG_440)
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0E00)
+#else
+#define EMAC_BASE			    (CFG_PERIPHERAL_BASE + 0x0800)
+#endif
+#else
+#define EMAC_BASE 			0xEF600800
+#endif
+
+#define EMAC_M0				    (EMAC_BASE)
+#define EMAC_M1				    (EMAC_BASE + 4)
+#define EMAC_TXM0				(EMAC_BASE + 8)
+#define EMAC_TXM1				(EMAC_BASE + 12)
+#define EMAC_RXM				(EMAC_BASE + 16)
+#define EMAC_ISR				(EMAC_BASE + 20)
+#define EMAC_IER				(EMAC_BASE + 24)
+#define EMAC_IAH				(EMAC_BASE + 28)
+#define EMAC_IAL				(EMAC_BASE + 32)
+#define EMAC_VLAN_TPID_REG		(EMAC_BASE + 36)
+#define EMAC_VLAN_TCI_REG		(EMAC_BASE + 40)
+#define EMAC_PAUSE_TIME_REG	(EMAC_BASE + 44)
+#define EMAC_IND_HASH_1			(EMAC_BASE + 48)
+#define EMAC_IND_HASH_2			(EMAC_BASE + 52)
+#define EMAC_IND_HASH_3			(EMAC_BASE + 56)
+#define EMAC_IND_HASH_4			(EMAC_BASE + 60)
+#define EMAC_GRP_HASH_1			(EMAC_BASE + 64)
+#define EMAC_GRP_HASH_2			(EMAC_BASE + 68)
+#define EMAC_GRP_HASH_3			(EMAC_BASE + 72)
+#define EMAC_GRP_HASH_4			(EMAC_BASE + 76)
+#define EMAC_LST_SRC_LOW		(EMAC_BASE + 80)
+#define EMAC_LST_SRC_HI			(EMAC_BASE + 84)
+#define EMAC_I_FRAME_GAP_REG	(EMAC_BASE + 88)
+#define EMAC_STACR			    (EMAC_BASE + 92)
+#define EMAC_TRTR				(EMAC_BASE + 96)
+#define EMAC_RX_HI_LO_WMARK		(EMAC_BASE + 100)
+
+/* bit definitions */
+/* MODE REG 0 */
+#define EMAC_M0_RXI			    (0x80000000)
+#define EMAC_M0_TXI			    (0x40000000)
+#define EMAC_M0_SRST			(0x20000000)
+#define EMAC_M0_TXE			    (0x10000000)
+#define EMAC_M0_RXE			    (0x08000000)
+#define EMAC_M0_WKE			    (0x04000000)
+
+/* on 440GX EMAC_MR1 has a different layout! */
+#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
+/* MODE Reg 1 */
+#define EMAC_M1_FDE		(0x80000000)
+#define EMAC_M1_ILE		(0x40000000)
+#define EMAC_M1_VLE		(0x20000000)
+#define EMAC_M1_EIFC			(0x10000000)
+#define EMAC_M1_APP			    (0x08000000)
+#define EMAC_M1_RSVD			(0x06000000)
+#define EMAC_M1_IST			    (0x01000000)
+#define EMAC_M1_MF_1000MBPS		(0x00800000)	/* 0's for 10MBPS */
+#define EMAC_M1_MF_100MBPS		(0x00400000)
+#define EMAC_M1_RFS_16K			(0x00280000)	/* ~4k for 512 byte */
+#define EMAC_M1_RFS_8K			(0x00200000)	/* ~4k for 512 byte */
+#define EMAC_M1_RFS_4K			(0x00180000)	/* ~4k for 512 byte */
+#define EMAC_M1_RFS_2K			(0x00100000)
+#define EMAC_M1_RFS_1K			(0x00080000)
+#define EMAC_M1_TX_FIFO_16K		(0x00050000)	/* 0's for 512 byte */
+#define EMAC_M1_TX_FIFO_8K		(0x00040000)
+#define EMAC_M1_TX_FIFO_4K		(0x00030000)
+#define EMAC_M1_TX_FIFO_2K	(0x00020000)
+#define EMAC_M1_TX_FIFO_1K		(0x00010000)
+#define EMAC_M1_TR_MULTI		(0x00008000)	/* 0'x for single packet */
+#define EMAC_M1_MWSW		(0x00007000)
+#define EMAC_M1_JUMBO_ENABLE	(0x00000800)
+#define EMAC_M1_IPPA		(0x000007c0)
+#define EMAC_M1_OBCI_GT100	(0x00000020)
+#define EMAC_M1_OBCI_100	(0x00000018)
+#define EMAC_M1_OBCI_83		(0x00000010)
+#define EMAC_M1_OBCI_66		(0x00000008)
+#define EMAC_M1_RSVD1		(0x00000007)
+#else /* defined(CONFIG_440GX) */
+/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
+#define EMAC_M1_FDE			0x80000000
+#define EMAC_M1_ILE			0x40000000
+#define EMAC_M1_VLE			0x20000000
+#define EMAC_M1_EIFC			0x10000000
+#define EMAC_M1_APP			0x08000000
+#define EMAC_M1_AEMI			0x02000000
+#define EMAC_M1_IST			0x01000000
+#define EMAC_M1_MF_1000MBPS		0x00800000	/* 0's for 10MBPS */
+#define EMAC_M1_MF_100MBPS		0x00400000
+#define EMAC_M1_RFS_4K			0x00300000	/* ~4k for 512 byte */
+#define EMAC_M1_RFS_2K			0x00200000
+#define EMAC_M1_RFS_1K			0x00100000
+#define EMAC_M1_TX_FIFO_2K		0x00080000	/* 0's for 512 byte */
+#define EMAC_M1_TX_FIFO_1K		0x00040000
+#define EMAC_M1_TR0_DEPEND		0x00010000	/* 0'x for single packet */
+#define EMAC_M1_TR0_MULTI		0x00008000
+#define EMAC_M1_TR1_DEPEND		0x00004000
+#define EMAC_M1_TR1_MULTI		0x00002000
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define EMAC_M1_JUMBO_ENABLE		0x00001000
+#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+#endif /* defined(CONFIG_440GX) */
+
+/* Transmit Mode Register 0 */
+#define EMAC_TXM0_GNP0			(0x80000000)
+#define EMAC_TXM0_GNP1			(0x40000000)
+#define EMAC_TXM0_GNPD			(0x20000000)
+#define EMAC_TXM0_FC			(0x10000000)
+
+/* Receive Mode Register */
+#define EMAC_RMR_SP		(0x80000000)
+#define EMAC_RMR_SFCS		(0x40000000)
+#define EMAC_RMR_ARRP		(0x20000000)
+#define EMAC_RMR_ARP		(0x10000000)
+#define EMAC_RMR_AROP		(0x08000000)
+#define EMAC_RMR_ARPI		(0x04000000)
+#define EMAC_RMR_PPP		(0x02000000)
+#define EMAC_RMR_PME		(0x01000000)
+#define EMAC_RMR_PMME		(0x00800000)
+#define EMAC_RMR_IAE		(0x00400000)
+#define EMAC_RMR_MIAE		(0x00200000)
+#define EMAC_RMR_BAE		(0x00100000)
+#define EMAC_RMR_MAE		(0x00080000)
+
+/* Interrupt Status & enable Regs */
+#define EMAC_ISR_OVR		(0x02000000)
+#define EMAC_ISR_PP		(0x01000000)
+#define EMAC_ISR_BP		(0x00800000)
+#define EMAC_ISR_RP		(0x00400000)
+#define EMAC_ISR_SE			(0x00200000)
+#define EMAC_ISR_SYE			(0x00100000)
+#define EMAC_ISR_BFCS			(0x00080000)
+#define EMAC_ISR_PTLE			(0x00040000)
+#define EMAC_ISR_ORE			(0x00020000)
+#define EMAC_ISR_IRE			(0x00010000)
+#define EMAC_ISR_DBDM			(0x00000200)
+#define EMAC_ISR_DB0			(0x00000100)
+#define EMAC_ISR_SE0			(0x00000080)
+#define EMAC_ISR_TE0			(0x00000040)
+#define EMAC_ISR_DB1			(0x00000020)
+#define EMAC_ISR_SE1			(0x00000010)
+#define EMAC_ISR_TE1			(0x00000008)
+#define EMAC_ISR_MOS			(0x00000002)
+#define EMAC_ISR_MOF			(0x00000001)
+
+
+/* STA CONTROL REG */
+#define EMAC_STACR_OC			(0x00008000)
+#define EMAC_STACR_PHYE			(0x00004000)
+#define EMAC_STACR_WRITE		(0x00002000)
+#define EMAC_STACR_READ			(0x00001000)
+#define EMAC_STACR_CLK_83MHZ	(0x00000800)  /* 0's for 50Mhz */
+#define EMAC_STACR_CLK_66MHZ	(0x00000400)
+#define EMAC_STACR_CLK_100MHZ	(0x00000C00)
+
+/* Transmit Request Threshold Register */
+#define EMAC_TRTR_256			(0x18000000)   /* 0's for 64 Bytes */
+#define EMAC_TRTR_192			(0x10000000)
+#define EMAC_TRTR_128			(0x01000000)
+
+/* the follwing defines are for the MadMAL status and control registers. */
+/* For bits 0..5 look at the mal.h file					 */
+#define EMAC_TX_CTRL_GFCS	(0x0200)
+#define EMAC_TX_CTRL_GP		(0x0100)
+#define EMAC_TX_CTRL_ISA	(0x0080)
+#define EMAC_TX_CTRL_RSA	(0x0040)
+#define EMAC_TX_CTRL_IVT	(0x0020)
+#define EMAC_TX_CTRL_RVT	(0x0010)
+
+#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
+
+#define EMAC_TX_ST_BFCS		(0x0200)
+#define EMAC_TX_ST_BPP		(0x0100)
+#define EMAC_TX_ST_LCS		(0x0080)
+#define EMAC_TX_ST_ED		(0x0040)
+#define EMAC_TX_ST_EC		(0x0020)
+#define EMAC_TX_ST_LC		(0x0010)
+#define EMAC_TX_ST_MC		(0x0008)
+#define EMAC_TX_ST_SC		(0x0004)
+#define EMAC_TX_ST_UR		(0x0002)
+#define EMAC_TX_ST_SQE		(0x0001)
+
+#define EMAC_TX_ST_DEFAULT	(0x03F3)
+
+
+/* madmal receive status / Control bits */
+
+#define EMAC_RX_ST_OE		(0x0200)
+#define EMAC_RX_ST_PP		(0x0100)
+#define EMAC_RX_ST_BP		(0x0080)
+#define EMAC_RX_ST_RP		(0x0040)
+#define EMAC_RX_ST_SE		(0x0020)
+#define EMAC_RX_ST_AE		(0x0010)
+#define EMAC_RX_ST_BFCS		(0x0008)
+#define EMAC_RX_ST_PTL		(0x0004)
+#define EMAC_RX_ST_ORE		(0x0002)
+#define EMAC_RX_ST_IRE		(0x0001)
+/* all the errors we care about */
+#define EMAC_RX_ERRORS		(0x03FF)
+
+#endif /* _PPC4XX_ENET_H_ */
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
new file mode 100755
index 0000000..72d690e
--- /dev/null
+++ b/include/ppc_asm.tmpl
@@ -0,0 +1,322 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains all the macros and symbols which define
+ * a PowerPC assembly language environment.
+ */
+#ifndef	__PPC_ASM_TMPL__
+#define __PPC_ASM_TMPL__
+
+/***************************************************************************
+ *
+ * These definitions simplify the ugly declarations necessary for GOT
+ * definitions.
+ *
+ * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
+ *
+ * Uses r14 to access the GOT
+ */
+
+#define START_GOT			\
+	.section	".got2","aw";	\
+.LCTOC1 = .+32768
+
+#define END_GOT				\
+	.text
+
+#define GET_GOT				\
+	bl	1f		;	\
+	.text	2		;	\
+0:	.long	.LCTOC1-1f	;	\
+	.text			;	\
+1:	mflr	r14		;	\
+	lwz	r0,0b-1b(r14)	;	\
+	add	r14,r0,r14	;
+
+#define GOT_ENTRY(NAME)		.L_ ## NAME = . - .LCTOC1 ; .long NAME
+
+#define GOT(NAME)		.L_ ## NAME (r14)
+
+
+/***************************************************************************
+ * Register names
+ */
+#define	r0	0
+#define	r1	1
+#define	r2	2
+#define	r3	3
+#define	r4	4
+#define	r5	5
+#define	r6	6
+#define	r7	7
+#define	r8	8
+#define	r9	9
+#define	r10	10
+#define	r11	11
+#define	r12	12
+#define	r13	13
+#define	r14	14
+#define	r15	15
+#define	r16	16
+#define	r17	17
+#define	r18	18
+#define	r19	19
+#define	r20	20
+#define	r21	21
+#define	r22	22
+#define	r23	23
+#define	r24	24
+#define	r25	25
+#define	r26	26
+#define	r27	27
+#define	r28	28
+#define	r29	29
+#define	r30	30
+#define	r31	31
+
+
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC824X)
+
+/* Some special registers */
+
+#define ICR	148	/* Interrupt Cause Register (37-44) */
+#define DER	149
+#define COUNTA	150	/* Breakpoint Counter	    (37-44) */
+#define COUNTB	151	/* Breakpoint Counter	    (37-44) */
+#define LCTRL1	156	/* Load/Store Support	    (37-40) */
+#define LCTRL2	157	/* Load/Store Support	    (37-41) */
+#define ICTRL	158
+
+#endif	/* CONFIG_8xx, CONFIG_MPC824X */
+
+
+#if  defined(CONFIG_5xx)
+/* Some special purpose registers */
+#define DER	149		/* Debug Enable Register	    	*/
+#define COUNTA	150		/* Breakpoint Counter	    	 	*/
+#define COUNTB	151		/* Breakpoint Counter	    	 	*/
+#define LCTRL1	156		/* Load/Store Support	    	 	*/
+#define LCTRL2	157		/* Load/Store Support	    	 	*/
+#define ICTRL	158		/* I-Bus Support Control Register	*/
+#define EID	81
+#endif	/* CONFIG_5xx */
+
+#if defined(CONFIG_8xx)
+
+/* Registers in the processor's internal memory map that we use.
+*/
+#define SYPCR	0x00000004
+#define BR0	0x00000100
+#define OR0	0x00000104
+#define BR1	0x00000108
+#define OR1	0x0000010c
+#define BR2	0x00000110
+#define OR2	0x00000114
+#define BR3	0x00000118
+#define OR3	0x0000011c
+#define BR4	0x00000120
+#define OR4	0x00000124
+
+#define MAR	0x00000164
+#define MCR	0x00000168
+#define MAMR	0x00000170
+#define MBMR	0x00000174
+#define MSTAT	0x00000178
+#define MPTPR	0x0000017a
+#define MDR	0x0000017c
+
+#define TBSCR	0x00000200
+#define TBREFF0	0x00000204
+
+#define PLPRCR	0x00000284
+
+#elif defined(CONFIG_8260)
+
+#define HID2		1011
+
+#define HID0_IFEM	(1<<7)
+
+#define HID0_ICE_BITPOS	16
+#define HID0_DCE_BITPOS	17
+
+#define IM_REGBASE	0x10000
+#define IM_SYPCR	(IM_REGBASE+0x0004)
+#define IM_SWSR		(IM_REGBASE+0x000e)
+#define IM_BR0		(IM_REGBASE+0x0100)
+#define IM_OR0		(IM_REGBASE+0x0104)
+#define IM_BR1		(IM_REGBASE+0x0108)
+#define IM_OR1		(IM_REGBASE+0x010c)
+#define IM_BR2		(IM_REGBASE+0x0110)
+#define IM_OR2		(IM_REGBASE+0x0114)
+#define IM_MPTPR	(IM_REGBASE+0x0184)
+#define IM_PSDMR	(IM_REGBASE+0x0190)
+#define IM_PSRT		(IM_REGBASE+0x019c)
+#define IM_IMMR		(IM_REGBASE+0x01a8)
+#define IM_SCCR		(IM_REGBASE+0x0c80)
+
+#elif defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8220)
+
+#define HID0_ICE_BITPOS	16
+#define HID0_DCE_BITPOS	17
+
+#endif
+
+#define curptr r2
+
+#define SYNC \
+	sync; \
+	isync
+
+/*
+ * Macros for storing registers into and loading registers from
+ * exception frames.
+ */
+#define SAVE_GPR(n, base)	stw	n,GPR0+4*(n)(base)
+#define SAVE_2GPRS(n, base)	SAVE_GPR(n, base); SAVE_GPR(n+1, base)
+#define SAVE_4GPRS(n, base)	SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
+#define SAVE_8GPRS(n, base)	SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
+#define SAVE_10GPRS(n, base)	SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
+#define REST_GPR(n, base)	lwz	n,GPR0+4*(n)(base)
+#define REST_2GPRS(n, base)	REST_GPR(n, base); REST_GPR(n+1, base)
+#define REST_4GPRS(n, base)	REST_2GPRS(n, base); REST_2GPRS(n+2, base)
+#define REST_8GPRS(n, base)	REST_4GPRS(n, base); REST_4GPRS(n+4, base)
+#define REST_10GPRS(n, base)	REST_8GPRS(n, base); REST_2GPRS(n+8, base)
+
+/*
+ * GCC sometimes accesses words at negative offsets from the stack
+ * pointer, although the SysV ABI says it shouldn't.  To cope with
+ * this, we leave this much untouched space on the stack on exception
+ * entry.
+ */
+#define STACK_UNDERHEAD	64
+
+/*
+ * Exception entry code.  This code runs with address translation
+ * turned off, i.e. using physical addresses.
+ * We assume sprg3 has the physical address of the current
+ * task's thread_struct.
+ */
+#define EXCEPTION_PROLOG	\
+	mtspr	SPRG0,r20;	\
+	mtspr	SPRG1,r21;	\
+	mfcr	r20;		\
+	subi	r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD;	/* alloc exc. frame */\
+	stw	r20,_CCR(r21);		/* save registers */ \
+	stw	r22,GPR22(r21);	\
+	stw	r23,GPR23(r21);	\
+	mfspr	r20,SPRG0;	\
+	stw	r20,GPR20(r21);	\
+	mfspr	r22,SPRG1;	\
+	stw	r22,GPR21(r21);	\
+	mflr	r20;		\
+	stw	r20,_LINK(r21);	\
+	mfctr	r22;		\
+	stw	r22,_CTR(r21);	\
+	mfspr	r20,XER;	\
+	stw	r20,_XER(r21);	\
+	mfspr	r22,SRR0;	\
+	mfspr	r23,SRR1;	\
+	stw	r0,GPR0(r21);	\
+	stw	r1,GPR1(r21);	\
+	stw	r2,GPR2(r21);	\
+	stw	r1,0(r21);	\
+	mr	r1,r21;			/* set new kernel sp */	\
+	SAVE_4GPRS(3, r21);
+/*
+ * Note: code which follows this uses cr0.eq (set if from kernel),
+ * r21, r22 (SRR0), and r23 (SRR1).
+ */
+
+/*
+ * Critical exception entry code.  This is just like the other exception
+ * code except that it uses SRR2 and SRR3 instead of SRR0 and SRR1.
+ */
+#define CRITICAL_EXCEPTION_PROLOG       \
+	mtspr   SPRG0,r20;      \
+	mtspr   SPRG1,r21;      \
+	mfcr    r20;            \
+	subi    r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD;  /* alloc exc. frame */\
+	stw     r20,_CCR(r21);          /* save registers */ \
+	stw     r22,GPR22(r21); \
+	stw     r23,GPR23(r21); \
+	mfspr   r20,SPRG0;      \
+	stw     r20,GPR20(r21); \
+	mfspr   r22,SPRG1;      \
+	stw     r22,GPR21(r21); \
+	mflr    r20;            \
+	stw     r20,_LINK(r21); \
+	mfctr   r22;            \
+	stw     r22,_CTR(r21);  \
+	mfspr   r20,XER;        \
+	stw     r20,_XER(r21);  \
+	mfspr   r22,990;        /* SRR2 */      \
+	mfspr   r23,991;        /* SRR3 */      \
+	stw     r0,GPR0(r21);   \
+	stw     r1,GPR1(r21);   \
+	stw     r2,GPR2(r21);   \
+	stw     r1,0(r21);      \
+	mr      r1,r21;                 /* set new kernel sp */ \
+	SAVE_4GPRS(3, r21);
+/*
+ * Note: code which follows this uses cr0.eq (set if from kernel),
+ * r21, r22 (SRR2), and r23 (SRR3).
+ */
+
+/*
+ * Exception vectors.
+ *
+ * The data words for `hdlr' and `int_return' are initialized with
+ * OFFSET values only; they must be relocated first before they can
+ * be used!
+ */
+#define STD_EXCEPTION(n, label, hdlr)			\
+	. = n;						\
+label:							\
+	EXCEPTION_PROLOG;				\
+	lwz	r3,GOT(transfer_to_handler);		\
+	mtlr	r3;					\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;		\
+	li	r20,MSR_KERNEL;				\
+	rlwimi	r20,r23,0,25,25;			\
+	blrl	; 					\
+.L_ ## label :						\
+	.long	hdlr - _start + EXC_OFF_SYS_RESET;	\
+	.long	int_return - _start + EXC_OFF_SYS_RESET
+
+
+#define CRIT_EXCEPTION(n, label, hdlr)                  \
+	. = n;                                          \
+label:                                                  \
+	CRITICAL_EXCEPTION_PROLOG;                      \
+	lwz     r3,GOT(transfer_to_handler);            \
+	mtlr    r3;                                     \
+	addi    r3,r1,STACK_FRAME_OVERHEAD;             \
+	li      r20,MSR_KERNEL;                         \
+	rlwimi  r20,r23,0,25,25;                        \
+	blrl    ;                                       \
+.L_ ## label :                                          \
+	.long   hdlr - _start + EXC_OFF_SYS_RESET;      \
+	.long   crit_return - _start + EXC_OFF_SYS_RESET
+
+#endif	/* __PPC_ASM_TMPL__ */
diff --git a/include/ppc_defs.h b/include/ppc_defs.h
new file mode 100755
index 0000000..8b2b3b5
--- /dev/null
+++ b/include/ppc_defs.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * WARNING! This file is automatically generated - DO NOT EDIT!
+ */
+#define	KERNELBASE	-1073741824
+#define	STATE	0
+#define	NEXT_TASK	64
+#define	COUNTER	52
+#define	PROCESSOR	916
+#define	SIGPENDING	8
+#define	TSS	576
+#define	MM	880
+#define	TASK_STRUCT_SIZE	928
+#define	KSP	0
+#define	PG_TABLES	4
+#define	PGD	8
+#define	LAST_SYSCALL	20
+#define	PT_REGS	12
+#define	PF_TRACESYS	32
+#define	TASK_FLAGS	4
+#define	TSS_FPR0	24
+#define	TSS_FPSCR	284
+#define	TSS_SMP_FORK_RET	288
+#define	TASK_UNION_SIZE	8192
+#define	STACK_FRAME_OVERHEAD	16
+#define	INT_FRAME_SIZE	192
+#define	GPR0	16
+#define	GPR1	20
+#define	GPR2	24
+#define	GPR3	28
+#define	GPR4	32
+#define	GPR5	36
+#define	GPR6	40
+#define	GPR7	44
+#define	GPR8	48
+#define	GPR9	52
+#define	GPR10	56
+#define	GPR11	60
+#define	GPR12	64
+#define	GPR13	68
+#define	GPR14	72
+#define	GPR15	76
+#define	GPR16	80
+#define	GPR17	84
+#define	GPR18	88
+#define	GPR19	92
+#define	GPR20	96
+#define	GPR21	100
+#define	GPR22	104
+#define	GPR23	108
+#define	GPR24	112
+#define	GPR25	116
+#define	GPR26	120
+#define	GPR27	124
+#define	GPR28	128
+#define	GPR29	132
+#define	GPR30	136
+#define	GPR31	140
+#define	_NIP	144
+#define	_MSR	148
+#define	_CTR	156
+#define	_LINK	160
+#define	_CCR	168
+#define	_XER	164
+#define	_DAR	180
+#define	_DSISR	184
+#define	ORIG_GPR3	152
+#define	RESULT	188
+#define	TRAP	176
diff --git a/include/ps2mult.h b/include/ps2mult.h
new file mode 100755
index 0000000..e685817
--- /dev/null
+++ b/include/ps2mult.h
@@ -0,0 +1,155 @@
+#ifndef __LINUX_PS2MULT_H
+#define __LINUX_PS2MULT_H
+
+#define kbd_request_region()		ps2mult_init()
+#define kbd_request_irq(handler)	ps2mult_request_irq(handler)
+
+#define kbd_read_input()		ps2mult_read_input()
+#define kbd_read_status()		ps2mult_read_status()
+#define kbd_write_output(val)		ps2mult_write_output(val)
+#define kbd_write_command(val)		ps2mult_write_command(val)
+
+#define aux_request_irq(hand, dev_id)	0
+#define aux_free_irq(dev_id)
+
+#define PS2MULT_KB_SELECTOR		0xA0
+#define PS2MULT_MS_SELECTOR		0xA1
+#define PS2MULT_ESCAPE			0x7D
+#define PS2MULT_BSYNC			0x7E
+#define PS2MULT_SESSION_START		0x55
+#define PS2MULT_SESSION_END		0x56
+
+#define	PS2BUF_SIZE			512	/* power of 2, please */
+
+#ifndef CONFIG_PS2MULT_DELAY
+#define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
+#endif
+
+  /* PS/2 controller interface (include/asm/keyboard.h)
+   */
+extern int ps2mult_init (void);
+extern int ps2mult_request_irq(void (*handler)(void *));
+extern u_char ps2mult_read_input(void);
+extern u_char ps2mult_read_status(void);
+extern void ps2mult_write_output(u_char val);
+extern void ps2mult_write_command(u_char val);
+
+extern void ps2mult_early_init (void);
+extern void ps2mult_callback (int in_cnt);
+
+  /* Simple serial interface
+   */
+extern int ps2ser_init(void);
+extern void ps2ser_putc(int chr);
+extern int ps2ser_getc(void);
+extern int ps2ser_check(void);
+
+
+  /* Serial related stuff
+   */
+struct serial_state {
+	int	baud_base;
+	int	irq;
+	u8	*iomem_base;
+};
+
+#define UART_RX		0	/* In:  Receive buffer (DLAB=0) */
+#define UART_TX		0	/* Out: Transmit buffer (DLAB=0) */
+#define UART_DLL	0	/* Out: Divisor Latch Low (DLAB=1) */
+
+#define UART_DLM	1	/* Out: Divisor Latch High (DLAB=1) */
+#define UART_IER	1	/* Out: Interrupt Enable Register */
+
+#define UART_IIR	2	/* In:  Interrupt ID Register */
+#define UART_FCR	2	/* Out: FIFO Control Register */
+
+#define UART_LCR	3	/* Out: Line Control Register */
+#define UART_MCR	4	/* Out: Modem Control Register */
+#define UART_LSR	5	/* In:  Line Status Register */
+#define UART_MSR	6	/* In:  Modem Status Register */
+#define UART_SCR	7	/* I/O: Scratch Register */
+
+/*
+ * These are the definitions for the FIFO Control Register
+ * (16650 only)
+ */
+#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
+#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
+
+/*
+ * These are the definitions for the Line Control Register
+ *
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define UART_LCR_DLAB	0x80	/* Divisor latch access bit */
+#define UART_LCR_SBC	0x40	/* Set break control */
+#define UART_LCR_SPAR	0x20	/* Stick parity (?) */
+#define UART_LCR_EPAR	0x10	/* Even parity select */
+#define UART_LCR_PARITY	0x08	/* Parity Enable */
+#define UART_LCR_STOP	0x04	/* Stop bits: 0=1 stop bit, 1= 2 stop bits */
+#define UART_LCR_WLEN5  0x00	/* Wordlength: 5 bits */
+#define UART_LCR_WLEN6  0x01	/* Wordlength: 6 bits */
+#define UART_LCR_WLEN7  0x02	/* Wordlength: 7 bits */
+#define UART_LCR_WLEN8  0x03	/* Wordlength: 8 bits */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_TEMT	0x40	/* Transmitter empty */
+#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
+#define UART_LSR_BI	0x10	/* Break interrupt indicator */
+#define UART_LSR_FE	0x08	/* Frame error indicator */
+#define UART_LSR_PE	0x04	/* Parity error indicator */
+#define UART_LSR_OE	0x02	/* Overrun error indicator */
+#define UART_LSR_DR	0x01	/* Receiver data ready */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
+#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
+
+#define UART_IIR_MSI	0x00	/* Modem status interrupt */
+#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
+#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
+#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
+#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
+#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
+#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
+
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
+#define UART_MCR_OUT2	0x08	/* Out2 complement */
+#define UART_MCR_OUT1	0x04	/* Out1 complement */
+#define UART_MCR_RTS	0x02	/* RTS complement */
+#define UART_MCR_DTR	0x01	/* DTR complement */
+
+/*
+ * These are the definitions for the Modem Status Register
+ */
+#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
+#define UART_MSR_RI	0x40	/* Ring Indicator */
+#define UART_MSR_DSR	0x20	/* Data Set Ready */
+#define UART_MSR_CTS	0x10	/* Clear to Send */
+#define UART_MSR_DDCD	0x08	/* Delta DCD */
+#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
+#define UART_MSR_DDSR	0x02	/* Delta DSR */
+#define UART_MSR_DCTS	0x01	/* Delta CTS */
+#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */
+
+#endif /* __LINUX_PS2MULT_H */
diff --git a/include/reiserfs.h b/include/reiserfs.h
new file mode 100755
index 0000000..c465b3c
--- /dev/null
+++ b/include/reiserfs.h
@@ -0,0 +1,82 @@
+/*
+ *  Copyright 2000-2002 by Hans Reiser, licensing governed by reiserfs/README
+ *
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 2000, 2001  Free Software Foundation, Inc.
+ *
+ *  (C) Copyright 2003 Sysgo Real-Time Solutions, AG <www.elinos.com>
+ *  Pavel Bartusek <pba@sysgo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* An implementation for the ReiserFS filesystem ported from GRUB.
+ * Some parts of this code (mainly the structures and defines) are
+ * from the original reiser fs code, as found in the linux kernel.
+ */
+
+
+#define SECTOR_SIZE		0x200
+#define SECTOR_BITS		9
+
+/* Error codes */
+typedef enum
+{
+  ERR_NONE = 0,
+  ERR_BAD_FILENAME,
+  ERR_BAD_FILETYPE,
+  ERR_BAD_GZIP_DATA,
+  ERR_BAD_GZIP_HEADER,
+  ERR_BAD_PART_TABLE,
+  ERR_BAD_VERSION,
+  ERR_BELOW_1MB,
+  ERR_BOOT_COMMAND,
+  ERR_BOOT_FAILURE,
+  ERR_BOOT_FEATURES,
+  ERR_DEV_FORMAT,
+  ERR_DEV_VALUES,
+  ERR_EXEC_FORMAT,
+  ERR_FILELENGTH,
+  ERR_FILE_NOT_FOUND,
+  ERR_FSYS_CORRUPT,
+  ERR_FSYS_MOUNT,
+  ERR_GEOM,
+  ERR_NEED_LX_KERNEL,
+  ERR_NEED_MB_KERNEL,
+  ERR_NO_DISK,
+  ERR_NO_PART,
+  ERR_NUMBER_PARSING,
+  ERR_OUTSIDE_PART,
+  ERR_READ,
+  ERR_SYMLINK_LOOP,
+  ERR_UNRECOGNIZED,
+  ERR_WONT_FIT,
+  ERR_WRITE,
+  ERR_BAD_ARGUMENT,
+  ERR_UNALIGNED,
+  ERR_PRIVILEGED,
+  ERR_DEV_NEED_INIT,
+  ERR_NO_DISK_SPACE,
+  ERR_NUMBER_OVERFLOW,
+
+  MAX_ERR_NUM
+} reiserfs_error_t;
+
+
+extern int reiserfs_set_blk_dev(block_dev_desc_t *rbdd, int part);
+extern int reiserfs_ls (char *dirname);
+extern int reiserfs_open (char *filename);
+extern int reiserfs_read (char *buf, unsigned len);
+extern int reiserfs_mount (unsigned part_length);
diff --git a/include/rtc.h b/include/rtc.h
new file mode 100755
index 0000000..15f3571
--- /dev/null
+++ b/include/rtc.h
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Generic RTC interface.
+ */
+#ifndef _RTC_H_
+#define _RTC_H_
+
+/*
+ * The struct used to pass data from the generic interface code to
+ * the hardware dependend low-level code ande vice versa. Identical
+ * to struct rtc_time used by the Linux kernel.
+ *
+ * Note that there are small but significant differences to the
+ * common "struct time":
+ *
+ * 		struct time:		struct rtc_time:
+ * tm_mon	0 ... 11		1 ... 12
+ * tm_year	years since 1900	years since 0
+ */
+
+struct rtc_time {
+	int tm_sec;
+	int tm_min;
+	int tm_hour;
+	int tm_mday;
+	int tm_mon;
+	int tm_year;
+	int tm_wday;
+	int tm_yday;
+	int tm_isdst;
+};
+
+void rtc_get (struct rtc_time *);
+void rtc_set (struct rtc_time *);
+void rtc_reset (void);
+
+void GregorianDay (struct rtc_time *);
+void to_tm (int, struct rtc_time *);
+unsigned long mktime (unsigned int, unsigned int, unsigned int,
+		      unsigned int, unsigned int, unsigned int);
+
+#endif	/* _RTC_H_ */
diff --git a/include/s3c2400.h b/include/s3c2400.h
new file mode 100755
index 0000000..bc1f1e9
--- /dev/null
+++ b/include/s3c2400.h
@@ -0,0 +1,554 @@
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME	    : s3c2400.h
+ * Version  : 31.3.2003
+ *
+ * Based on S3C2400X User's manual Rev 1.1
+ ************************************************/
+
+#ifndef __S3C2400_H__
+#define __S3C2400_H__
+
+#define S3C24X0_UART_CHANNELS	2
+#define S3C24X0_SPI_CHANNELS	1
+#define PALETTE			(0x14A00400)	/* SJS */
+
+typedef enum {
+	S3C24X0_UART0,
+	S3C24X0_UART1,
+} S3C24X0_UARTS_NR;
+
+/* S3C2400 device base addresses */
+#define S3C24X0_MEMCTL_BASE		0x14000000
+#define S3C24X0_USB_HOST_BASE		0x14200000
+#define S3C24X0_INTERRUPT_BASE		0x14400000
+#define S3C24X0_DMA_BASE		0x14600000
+#define S3C24X0_CLOCK_POWER_BASE	0x14800000
+#define S3C24X0_LCD_BASE		0x14A00000
+#define S3C24X0_UART_BASE		0x15000000
+#define S3C24X0_TIMER_BASE		0x15100000
+#define S3C24X0_USB_DEVICE_BASE		0x15200140
+#define S3C24X0_WATCHDOG_BASE		0x15300000
+#define S3C24X0_I2C_BASE		0x15400000
+#define S3C24X0_I2S_BASE		0x15508000
+#define S3C24X0_GPIO_BASE		0x15600000
+#define S3C24X0_RTC_BASE		0x15700000
+#define S3C24X0_ADC_BASE		0x15800000
+#define S3C24X0_SPI_BASE		0x15900000
+#define S3C2400_MMC_BASE		0x15A00000
+
+/* include common stuff */
+#include <s3c24x0.h>
+
+
+static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void)
+{
+	return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
+}
+static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void)
+{
+	return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
+}
+static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void)
+{
+	return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
+}
+static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void)
+{
+	return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
+}
+static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void)
+{
+	return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
+}
+static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void)
+{
+	return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
+}
+static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
+{
+	return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
+}
+static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void)
+{
+	return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
+}
+static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void)
+{
+	return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
+}
+static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void)
+{
+	return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
+}
+static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void)
+{
+	return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
+}
+static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void)
+{
+	return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
+}
+static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void)
+{
+	return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
+}
+static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void)
+{
+	return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
+}
+static inline S3C2400_ADC * const S3C2400_GetBase_ADC(void)
+{
+	return (S3C2400_ADC * const)S3C24X0_ADC_BASE;
+}
+static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void)
+{
+	return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
+}
+static inline S3C2400_MMC * const S3C2400_GetBase_MMC(void)
+{
+	return (S3C2400_MMC * const)S3C2400_MMC_BASE;
+}
+
+#if 0
+/* Memory control */
+#define rBWSCON		(*(volatile unsigned *)0x14000000)
+#define rBANKCON0	(*(volatile unsigned *)0x14000004)
+#define rBANKCON1	(*(volatile unsigned *)0x14000008)
+#define rBANKCON2	(*(volatile unsigned *)0x1400000C)
+#define rBANKCON3	(*(volatile unsigned *)0x14000010)
+#define rBANKCON4	(*(volatile unsigned *)0x14000014)
+#define rBANKCON5	(*(volatile unsigned *)0x14000018)
+#define rBANKCON6	(*(volatile unsigned *)0x1400001C)
+#define rBANKCON7	(*(volatile unsigned *)0x14000020)
+#define rREFRESH	(*(volatile unsigned *)0x14000024)
+#define rBANKSIZE	(*(volatile unsigned *)0x14000028)
+#define rMRSRB6		(*(volatile unsigned *)0x1400002C)
+#define rMRSRB7		(*(volatile unsigned *)0x14000030)
+
+
+/* INTERRUPT */
+#define rSRCPND		(*(volatile unsigned *)0x14400000)
+#define rINTMOD		(*(volatile unsigned *)0x14400004)
+#define rINTMSK		(*(volatile unsigned *)0x14400008)
+#define rPRIORITY	(*(volatile unsigned *)0x1440000C)
+#define rINTPND		(*(volatile unsigned *)0x14400010)
+#define rINTOFFSET	(*(volatile unsigned *)0x14400014)
+
+
+/* DMA */
+#define rDISRC0		(*(volatile unsigned *)0x14600000)
+#define rDIDST0		(*(volatile unsigned *)0x14600004)
+#define rDCON0		(*(volatile unsigned *)0x14600008)
+#define rDSTAT0		(*(volatile unsigned *)0x1460000C)
+#define rDCSRC0		(*(volatile unsigned *)0x14600010)
+#define rDCDST0		(*(volatile unsigned *)0x14600014)
+#define rDMASKTRIG0	(*(volatile unsigned *)0x14600018)
+#define rDISRC1		(*(volatile unsigned *)0x14600020)
+#define rDIDST1		(*(volatile unsigned *)0x14600024)
+#define rDCON1		(*(volatile unsigned *)0x14600028)
+#define rDSTAT1		(*(volatile unsigned *)0x1460002C)
+#define rDCSRC1		(*(volatile unsigned *)0x14600030)
+#define rDCDST1		(*(volatile unsigned *)0x14600034)
+#define rDMASKTRIG1	(*(volatile unsigned *)0x14600038)
+#define rDISRC2		(*(volatile unsigned *)0x14600040)
+#define rDIDST2		(*(volatile unsigned *)0x14600044)
+#define rDCON2		(*(volatile unsigned *)0x14600048)
+#define rDSTAT2		(*(volatile unsigned *)0x1460004C)
+#define rDCSRC2		(*(volatile unsigned *)0x14600050)
+#define rDCDST2		(*(volatile unsigned *)0x14600054)
+#define rDMASKTRIG2	(*(volatile unsigned *)0x14600058)
+#define rDISRC3		(*(volatile unsigned *)0x14600060)
+#define rDIDST3		(*(volatile unsigned *)0x14600064)
+#define rDCON3		(*(volatile unsigned *)0x14600068)
+#define rDSTAT3		(*(volatile unsigned *)0x1460006C)
+#define rDCSRC3		(*(volatile unsigned *)0x14600070)
+#define rDCDST3		(*(volatile unsigned *)0x14600074)
+#define rDMASKTRIG3	(*(volatile unsigned *)0x14600078)
+
+
+/* CLOCK & POWER MANAGEMENT */
+#define rLOCKTIME	(*(volatile unsigned *)0x14800000)
+#define rMPLLCON	(*(volatile unsigned *)0x14800004)
+#define rUPLLCON	(*(volatile unsigned *)0x14800008)
+#define rCLKCON		(*(volatile unsigned *)0x1480000C)
+#define rCLKSLOW	(*(volatile unsigned *)0x14800010)
+#define rCLKDIVN	(*(volatile unsigned *)0x14800014)
+
+
+/* LCD CONTROLLER */
+#define rLCDCON1	(*(volatile unsigned *)0x14A00000)
+#define rLCDCON2	(*(volatile unsigned *)0x14A00004)
+#define rLCDCON3	(*(volatile unsigned *)0x14A00008)
+#define rLCDCON4	(*(volatile unsigned *)0x14A0000C)
+#define rLCDCON5	(*(volatile unsigned *)0x14A00010)
+#define rLCDSADDR1	(*(volatile unsigned *)0x14A00014)
+#define rLCDSADDR2	(*(volatile unsigned *)0x14A00018)
+#define rLCDSADDR3	(*(volatile unsigned *)0x14A0001C)
+#define rREDLUT		(*(volatile unsigned *)0x14A00020)
+#define rGREENLUT	(*(volatile unsigned *)0x14A00024)
+#define rBLUELUT	(*(volatile unsigned *)0x14A00028)
+#define rDP1_2		(*(volatile unsigned *)0x14A0002C)
+#define rDP4_7		(*(volatile unsigned *)0x14A00030)
+#define rDP3_5		(*(volatile unsigned *)0x14A00034)
+#define rDP2_3		(*(volatile unsigned *)0x14A00038)
+#define rDP5_7		(*(volatile unsigned *)0x14A0003c)
+#define rDP3_4		(*(volatile unsigned *)0x14A00040)
+#define rDP4_5		(*(volatile unsigned *)0x14A00044)
+#define rDP6_7		(*(volatile unsigned *)0x14A00048)
+#define rDITHMODE	(*(volatile unsigned *)0x14A0004C)
+#define rTPAL		(*(volatile unsigned *)0x14A00050)
+#define PALETTE		(0x14A00400)	/* SJS */
+
+
+/* UART */
+#define rULCON0		(*(volatile unsigned char *)0x15000000)
+#define rUCON0		(*(volatile unsigned short *)0x15000004)
+#define rUFCON0		(*(volatile unsigned char *)0x15000008)
+#define rUMCON0		(*(volatile unsigned char *)0x1500000C)
+#define rUTRSTAT0	(*(volatile unsigned char *)0x15000010)
+#define rUERSTAT0	(*(volatile unsigned char *)0x15000014)
+#define rUFSTAT0	(*(volatile unsigned short *)0x15000018)
+#define rUMSTAT0	(*(volatile unsigned char *)0x1500001C)
+#define rUBRDIV0	(*(volatile unsigned short *)0x15000028)
+
+#define rULCON1		(*(volatile unsigned char *)0x15004000)
+#define rUCON1		(*(volatile unsigned short *)0x15004004)
+#define rUFCON1		(*(volatile unsigned char *)0x15004008)
+#define rUMCON1		(*(volatile unsigned char *)0x1500400C)
+#define rUTRSTAT1	(*(volatile unsigned char *)0x15004010)
+#define rUERSTAT1	(*(volatile unsigned char *)0x15004014)
+#define rUFSTAT1	(*(volatile unsigned short *)0x15004018)
+#define rUMSTAT1	(*(volatile unsigned char *)0x1500401C)
+#define rUBRDIV1	(*(volatile unsigned short *)0x15004028)
+
+#ifdef __BIG_ENDIAN
+#define rUTXH0		(*(volatile unsigned char *)0x15000023)
+#define rURXH0		(*(volatile unsigned char *)0x15000027)
+#define rUTXH1		(*(volatile unsigned char *)0x15004023)
+#define rURXH1		(*(volatile unsigned char *)0x15004027)
+
+#define WrUTXH0(ch)	(*(volatile unsigned char *)0x15000023)=(unsigned char)(ch)
+#define RdURXH0()	(*(volatile unsigned char *)0x15000027)
+#define WrUTXH1(ch)	(*(volatile unsigned char *)0x15004023)=(unsigned char)(ch)
+#define RdURXH1()	(*(volatile unsigned char *)0x15004027)
+
+#define UTXH0		(0x15000020+3)  /* byte_access address by DMA */
+#define URXH0		(0x15000024+3)
+#define UTXH1		(0x15004020+3)
+#define URXH1		(0x15004024+3)
+
+#else /* Little Endian */
+#define rUTXH0		(*(volatile unsigned char *)0x15000020)
+#define rURXH0		(*(volatile unsigned char *)0x15000024)
+#define rUTXH1		(*(volatile unsigned char *)0x15004020)
+#define rURXH1		(*(volatile unsigned char *)0x15004024)
+
+#define WrUTXH0(ch)	(*(volatile unsigned char *)0x15000020)=(unsigned char)(ch)
+#define RdURXH0()	(*(volatile unsigned char *)0x15000024)
+#define WrUTXH1(ch)	(*(volatile unsigned char *)0x15004020)=(unsigned char)(ch)
+#define RdURXH1()	(*(volatile unsigned char *)0x15004024)
+
+#define UTXH0		(0x15000020)    /* byte_access address by DMA */
+#define URXH0		(0x15000024)
+#define UTXH1		(0x15004020)
+#define URXH1		(0x15004024)
+#endif
+
+
+/* PWM TIMER */
+#define rTCFG0		(*(volatile unsigned *)0x15100000)
+#define rTCFG1		(*(volatile unsigned *)0x15100004)
+#define rTCON		(*(volatile unsigned *)0x15100008)
+#define rTCNTB0		(*(volatile unsigned *)0x1510000C)
+#define rTCMPB0		(*(volatile unsigned *)0x15100010)
+#define rTCNTO0		(*(volatile unsigned *)0x15100014)
+#define rTCNTB1		(*(volatile unsigned *)0x15100018)
+#define rTCMPB1		(*(volatile unsigned *)0x1510001C)
+#define rTCNTO1		(*(volatile unsigned *)0x15100020)
+#define rTCNTB2		(*(volatile unsigned *)0x15100024)
+#define rTCMPB2		(*(volatile unsigned *)0x15100028)
+#define rTCNTO2		(*(volatile unsigned *)0x1510002C)
+#define rTCNTB3		(*(volatile unsigned *)0x15100030)
+#define rTCMPB3		(*(volatile unsigned *)0x15100034)
+#define rTCNTO3		(*(volatile unsigned *)0x15100038)
+#define rTCNTB4		(*(volatile unsigned *)0x1510003C)
+#define rTCNTO4		(*(volatile unsigned *)0x15100040)
+
+
+/* USB DEVICE */
+#define rFUNC_ADDR_REG	(*(volatile unsigned *)0x15200140)
+#define rPWR_REG	(*(volatile unsigned *)0x15200144)
+#define rINT_REG	(*(volatile unsigned *)0x15200148)
+#define rINT_MASK_REG	(*(volatile unsigned *)0x1520014C)
+#define rFRAME_NUM_REG	(*(volatile unsigned *)0x15200150)
+#define rRESUME_CON_REG	(*(volatile unsigned *)0x15200154)
+#define rEP0_CSR	(*(volatile unsigned *)0x15200160)
+#define rEP0_MAXP	(*(volatile unsigned *)0x15200164)
+#define rEP0_OUT_CNT	(*(volatile unsigned *)0x15200168)
+#define rEP0_FIFO	(*(volatile unsigned *)0x1520016C)
+#define rEP1_IN_CSR	(*(volatile unsigned *)0x15200180)
+#define rEP1_IN_MAXP	(*(volatile unsigned *)0x15200184)
+#define rEP1_FIFO	(*(volatile unsigned *)0x15200188)
+#define rEP2_IN_CSR	(*(volatile unsigned *)0x15200190)
+#define rEP2_IN_MAXP	(*(volatile unsigned *)0x15200194)
+#define rEP2_FIFO	(*(volatile unsigned *)0x15200198)
+#define rEP3_OUT_CSR	(*(volatile unsigned *)0x152001A0)
+#define rEP3_OUT_MAXP	(*(volatile unsigned *)0x152001A4)
+#define rEP3_OUT_CNT	(*(volatile unsigned *)0x152001A8)
+#define rEP3_FIFO	(*(volatile unsigned *)0x152001AC)
+#define rEP4_OUT_CSR	(*(volatile unsigned *)0x152001B0)
+#define rEP4_OUT_MAXP	(*(volatile unsigned *)0x152001B4)
+#define rEP4_OUT_CNT	(*(volatile unsigned *)0x152001B8)
+#define rEP4_FIFO	(*(volatile unsigned *)0x152001BC)
+#define rDMA_CON	(*(volatile unsigned *)0x152001C0)
+#define rDMA_UNIT	(*(volatile unsigned *)0x152001C4)
+#define rDMA_FIFO	(*(volatile unsigned *)0x152001C8)
+#define rDMA_TX		(*(volatile unsigned *)0x152001CC)
+#define rTEST_MODE	(*(volatile unsigned *)0x152001F4)
+#define rIN_CON_REG	(*(volatile unsigned *)0x152001F8)
+
+
+/* WATCH DOG TIMER */
+#define rWTCON		(*(volatile unsigned *)0x15300000)
+#define rWTDAT		(*(volatile unsigned *)0x15300004)
+#define rWTCNT		(*(volatile unsigned *)0x15300008)
+
+
+/* IIC */
+#define rIICCON		(*(volatile unsigned *)0x15400000)
+#define rIICSTAT	(*(volatile unsigned *)0x15400004)
+#define rIICADD		(*(volatile unsigned *)0x15400008)
+#define rIICDS		(*(volatile unsigned *)0x1540000C)
+
+
+/* IIS */
+#define rIISCON		(*(volatile unsigned *)0x15508000)
+#define rIISMOD		(*(volatile unsigned *)0x15508004)
+#define rIISPSR		(*(volatile unsigned *)0x15508008)
+#define rIISFIFCON	(*(volatile unsigned *)0x1550800C)
+
+#ifdef __BIG_ENDIAN
+#define IISFIF		((volatile unsigned short *)0x15508012)
+
+#else /* Little Endian */
+#define IISFIF		((volatile unsigned short *)0x15508010)
+#endif
+
+
+/* I/O PORT */
+#define rPACON		(*(volatile unsigned *)0x15600000)
+#define rPADAT		(*(volatile unsigned *)0x15600004)
+
+#define rPBCON		(*(volatile unsigned *)0x15600008)
+#define rPBDAT		(*(volatile unsigned *)0x1560000C)
+#define rPBUP		(*(volatile unsigned *)0x15600010)
+
+#define rPCCON		(*(volatile unsigned *)0x15600014)
+#define rPCDAT		(*(volatile unsigned *)0x15600018)
+#define rPCUP		(*(volatile unsigned *)0x1560001C)
+
+#define rPDCON		(*(volatile unsigned *)0x15600020)
+#define rPDDAT		(*(volatile unsigned *)0x15600024)
+#define rPDUP		(*(volatile unsigned *)0x15600028)
+
+#define rPECON		(*(volatile unsigned *)0x1560002C)
+#define rPEDAT		(*(volatile unsigned *)0x15600030)
+#define rPEUP		(*(volatile unsigned *)0x15600034)
+
+#define rPFCON		(*(volatile unsigned *)0x15600038)
+#define rPFDAT		(*(volatile unsigned *)0x1560003C)
+#define rPFUP		(*(volatile unsigned *)0x15600040)
+
+#define rPGCON		(*(volatile unsigned *)0x15600044)
+#define rPGDAT		(*(volatile unsigned *)0x15600048)
+#define rPGUP		(*(volatile unsigned *)0x1560004C)
+
+#define rOPENCR		(*(volatile unsigned *)0x15600050)
+#define rMISCCR		(*(volatile unsigned *)0x15600054)
+#define rEXTINT		(*(volatile unsigned *)0x15600058)
+
+
+/* RTC */
+#ifdef __BIG_ENDIAN
+#define rRTCCON		(*(volatile unsigned char *)0x15700043)
+#define rRTCALM		(*(volatile unsigned char *)0x15700053)
+#define rALMSEC		(*(volatile unsigned char *)0x15700057)
+#define rALMMIN		(*(volatile unsigned char *)0x1570005B)
+#define rALMHOUR	(*(volatile unsigned char *)0x1570005F)
+#define rALMDAY		(*(volatile unsigned char *)0x15700063)
+#define rALMMON		(*(volatile unsigned char *)0x15700067)
+#define rALMYEAR	(*(volatile unsigned char *)0x1570006B)
+#define rRTCRST		(*(volatile unsigned char *)0x1570006F)
+#define rBCDSEC		(*(volatile unsigned char *)0x15700073)
+#define rBCDMIN		(*(volatile unsigned char *)0x15700077)
+#define rBCDHOUR	(*(volatile unsigned char *)0x1570007B)
+#define rBCDDAY		(*(volatile unsigned char *)0x1570007F)
+#define rBCDDATE	(*(volatile unsigned char *)0x15700083)
+#define rBCDMON		(*(volatile unsigned char *)0x15700087)
+#define rBCDYEAR	(*(volatile unsigned char *)0x1570008B)
+#define rTICINT		(*(volatile unsigned char *)0x15700047)
+
+#else /* Little Endian */
+#define rRTCCON		(*(volatile unsigned char *)0x15700040)
+#define rRTCALM		(*(volatile unsigned char *)0x15700050)
+#define rALMSEC		(*(volatile unsigned char *)0x15700054)
+#define rALMMIN		(*(volatile unsigned char *)0x15700058)
+#define rALMHOUR	(*(volatile unsigned char *)0x1570005C)
+#define rALMDAY		(*(volatile unsigned char *)0x15700060)
+#define rALMMON		(*(volatile unsigned char *)0x15700064)
+#define rALMYEAR	(*(volatile unsigned char *)0x15700068)
+#define rRTCRST		(*(volatile unsigned char *)0x1570006C)
+#define rBCDSEC		(*(volatile unsigned char *)0x15700070)
+#define rBCDMIN		(*(volatile unsigned char *)0x15700074)
+#define rBCDHOUR	(*(volatile unsigned char *)0x15700078)
+#define rBCDDAY		(*(volatile unsigned char *)0x1570007C)
+#define rBCDDATE	(*(volatile unsigned char *)0x15700080)
+#define rBCDMON		(*(volatile unsigned char *)0x15700084)
+#define rBCDYEAR	(*(volatile unsigned char *)0x15700088)
+#define rTICINT		(*(volatile unsigned char *)0x15700044)
+#endif
+
+
+/* ADC */
+#define rADCCON		(*(volatile unsigned *)0x15800000)
+#define rADCDAT		(*(volatile unsigned *)0x15800004)
+
+
+/* SPI */
+#define rSPCON		(*(volatile unsigned *)0x15900000)
+#define rSPSTA		(*(volatile unsigned *)0x15900004)
+#define rSPPIN		(*(volatile unsigned *)0x15900008)
+#define rSPPRE		(*(volatile unsigned *)0x1590000C)
+#define rSPTDAT		(*(volatile unsigned *)0x15900010)
+#define rSPRDAT		(*(volatile unsigned *)0x15900014)
+
+
+/* MMC INTERFACE */
+#define rMMCON		(*(volatile unsigned *)0x15a00000)
+#define rMMCRR		(*(volatile unsigned *)0x15a00004)
+#define rMMFCON		(*(volatile unsigned *)0x15a00008)
+#define rMMSTA		(*(volatile unsigned *)0x15a0000C)
+#define rMMFSTA		(*(volatile unsigned *)0x15a00010)
+#define rMMPRE		(*(volatile unsigned *)0x15a00014)
+#define rMMLEN		(*(volatile unsigned *)0x15a00018)
+#define rMMCR7		(*(volatile unsigned *)0x15a0001C)
+#define rMMRSP0		(*(volatile unsigned *)0x15a00020)
+#define rMMRSP1		(*(volatile unsigned *)0x15a00024)
+#define rMMRSP2		(*(volatile unsigned *)0x15a00028)
+#define rMMRSP3		(*(volatile unsigned *)0x15a0002C)
+#define rMMCMD0		(*(volatile unsigned *)0x15a00030)
+#define rMMCMD1		(*(volatile unsigned *)0x15a00034)
+#define rMMCR16		(*(volatile unsigned *)0x15a00038)
+#define rMMDAT		(*(volatile unsigned *)0x15a0003C)
+
+
+/* ISR */
+#define pISR_RESET	(*(unsigned *)(_ISR_STARTADDRESS+0x0))
+#define pISR_UNDEF	(*(unsigned *)(_ISR_STARTADDRESS+0x4))
+#define pISR_SWI	(*(unsigned *)(_ISR_STARTADDRESS+0x8))
+#define pISR_PABORT	(*(unsigned *)(_ISR_STARTADDRESS+0xC))
+#define pISR_DABORT	(*(unsigned *)(_ISR_STARTADDRESS+0x10))
+#define pISR_RESERVED	(*(unsigned *)(_ISR_STARTADDRESS+0x14))
+#define pISR_IRQ	(*(unsigned *)(_ISR_STARTADDRESS+0x18))
+#define pISR_FIQ	(*(unsigned *)(_ISR_STARTADDRESS+0x1C))
+
+#define pISR_EINT0	(*(unsigned *)(_ISR_STARTADDRESS+0x20))
+#define pISR_EINT1	(*(unsigned *)(_ISR_STARTADDRESS+0x24))
+#define pISR_EINT2	(*(unsigned *)(_ISR_STARTADDRESS+0x28))
+#define pISR_EINT3	(*(unsigned *)(_ISR_STARTADDRESS+0x2C))
+#define pISR_EINT4	(*(unsigned *)(_ISR_STARTADDRESS+0x30))
+#define pISR_EINT5	(*(unsigned *)(_ISR_STARTADDRESS+0x34))
+#define pISR_EINT6	(*(unsigned *)(_ISR_STARTADDRESS+0x38))
+#define pISR_EINT7	(*(unsigned *)(_ISR_STARTADDRESS+0x3C))
+#define pISR_TICK	(*(unsigned *)(_ISR_STARTADDRESS+0x40))
+#define pISR_WDT	(*(unsigned *)(_ISR_STARTADDRESS+0x44))
+#define pISR_TIMER0	(*(unsigned *)(_ISR_STARTADDRESS+0x48))
+#define pISR_TIMER1	(*(unsigned *)(_ISR_STARTADDRESS+0x4C))
+#define pISR_TIMER2	(*(unsigned *)(_ISR_STARTADDRESS+0x50))
+#define pISR_TIMER3	(*(unsigned *)(_ISR_STARTADDRESS+0x54))
+#define pISR_TIMER4	(*(unsigned *)(_ISR_STARTADDRESS+0x58))
+#define pISR_UERR01	(*(unsigned *)(_ISR_STARTADDRESS+0x5C))
+#define pISR_NOTUSED	(*(unsigned *)(_ISR_STARTADDRESS+0x60))
+#define pISR_DMA0	(*(unsigned *)(_ISR_STARTADDRESS+0x64))
+#define pISR_DMA1	(*(unsigned *)(_ISR_STARTADDRESS+0x68))
+#define pISR_DMA2	(*(unsigned *)(_ISR_STARTADDRESS+0x6C))
+#define pISR_DMA3	(*(unsigned *)(_ISR_STARTADDRESS+0x70))
+#define pISR_MMC	(*(unsigned *)(_ISR_STARTADDRESS+0x74))
+#define pISR_SPI	(*(unsigned *)(_ISR_STARTADDRESS+0x78))
+#define pISR_URXD0	(*(unsigned *)(_ISR_STARTADDRESS+0x7C))
+#define pISR_URXD1	(*(unsigned *)(_ISR_STARTADDRESS+0x80))
+#define pISR_USBD	(*(unsigned *)(_ISR_STARTADDRESS+0x84))
+#define pISR_USBH	(*(unsigned *)(_ISR_STARTADDRESS+0x88))
+#define pISR_IIC	(*(unsigned *)(_ISR_STARTADDRESS+0x8C))
+#define pISR_UTXD0	(*(unsigned *)(_ISR_STARTADDRESS+0x90))
+#define pISR_UTXD1	(*(unsigned *)(_ISR_STARTADDRESS+0x94))
+#define pISR_RTC	(*(unsigned *)(_ISR_STARTADDRESS+0x98))
+#define pISR_ADC	(*(unsigned *)(_ISR_STARTADDRESS+0xA0))
+
+
+/* PENDING BIT */
+#define BIT_EINT0	(0x1)
+#define BIT_EINT1	(0x1<<1)
+#define BIT_EINT2	(0x1<<2)
+#define BIT_EINT3	(0x1<<3)
+#define BIT_EINT4	(0x1<<4)
+#define BIT_EINT5	(0x1<<5)
+#define BIT_EINT6	(0x1<<6)
+#define BIT_EINT7	(0x1<<7)
+#define BIT_TICK	(0x1<<8)
+#define BIT_WDT		(0x1<<9)
+#define BIT_TIMER0	(0x1<<10)
+#define BIT_TIMER1	(0x1<<11)
+#define BIT_TIMER2	(0x1<<12)
+#define BIT_TIMER3	(0x1<<13)
+#define BIT_TIMER4	(0x1<<14)
+#define BIT_UERR01	(0x1<<15)
+#define BIT_NOTUSED	(0x1<<16)
+#define BIT_DMA0	(0x1<<17)
+#define BIT_DMA1	(0x1<<18)
+#define BIT_DMA2	(0x1<<19)
+#define BIT_DMA3	(0x1<<20)
+#define BIT_MMC		(0x1<<21)
+#define BIT_SPI		(0x1<<22)
+#define BIT_URXD0	(0x1<<23)
+#define BIT_URXD1	(0x1<<24)
+#define BIT_USBD	(0x1<<25)
+#define BIT_USBH	(0x1<<26)
+#define BIT_IIC		(0x1<<27)
+#define BIT_UTXD0	(0x1<<28)
+#define BIT_UTXD1	(0x1<<29)
+#define BIT_RTC		(0x1<<30)
+#define BIT_ADC		(0x1<<31)
+#define BIT_ALLMSK	(0xFFFFFFFF)
+
+#define ClearPending(bit) {\
+		 rSRCPND = bit;\
+		 rINTPND = bit;\
+		 rINTPND;\
+		 }
+/* Wait until rINTPND is changed for the case that the ISR is very short. */
+#endif
+#endif /*__S3C2400_H__*/
diff --git a/include/s3c2410.h b/include/s3c2410.h
new file mode 100755
index 0000000..86495f6
--- /dev/null
+++ b/include/s3c2410.h
@@ -0,0 +1,227 @@
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME	    : s3c2410.h
+ * Version  : 31.3.2003
+ *
+ * Based on S3C2410X User's manual Rev 1.1
+ ************************************************/
+
+#ifndef __S3C2410_H__
+#define __S3C2410_H__
+
+#define S3C24X0_UART_CHANNELS	3
+#define S3C24X0_SPI_CHANNELS	2
+
+/* S3C2410 only supports 512 Byte HW ECC */
+#define S3C2410_ECCSIZE		512
+#define S3C2410_ECCBYTES	3
+
+typedef enum {
+	S3C24X0_UART0,
+	S3C24X0_UART1,
+	S3C24X0_UART2
+} S3C24X0_UARTS_NR;
+
+/* S3C2410 device base addresses */
+#define S3C24X0_MEMCTL_BASE		0x48000000
+#define S3C24X0_USB_HOST_BASE		0x49000000
+#define S3C24X0_INTERRUPT_BASE		0x4A000000
+#define S3C24X0_DMA_BASE		0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE	0x4C000000
+#define S3C24X0_LCD_BASE		0x4D000000
+#define S3C2410_NAND_BASE		0x4E000000
+#define S3C24X0_UART_BASE		0x50000000
+#define S3C24X0_TIMER_BASE		0x51000000
+#define S3C24X0_USB_DEVICE_BASE		0x52000140
+#define S3C24X0_WATCHDOG_BASE		0x53000000
+#define S3C24X0_I2C_BASE		0x54000000
+#define S3C24X0_I2S_BASE		0x55000000
+#define S3C24X0_GPIO_BASE		0x56000000
+#define S3C24X0_RTC_BASE		0x57000000
+#define S3C2410_ADC_BASE		0x58000000
+#define S3C24X0_SPI_BASE		0x59000000
+#define S3C2410_SDI_BASE		0x5A000000
+
+
+/* include common stuff */
+#include <s3c24x0.h>
+
+
+static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void)
+{
+	return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
+}
+static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void)
+{
+	return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
+}
+static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void)
+{
+	return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
+}
+static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void)
+{
+	return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
+}
+static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void)
+{
+	return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
+}
+static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void)
+{
+	return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
+}
+static inline S3C2410_NAND * const S3C2410_GetBase_NAND(void)
+{
+	return (S3C2410_NAND * const)S3C2410_NAND_BASE;
+}
+static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
+{
+	return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
+}
+static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void)
+{
+	return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
+}
+static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void)
+{
+	return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
+}
+static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void)
+{
+	return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
+}
+static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void)
+{
+	return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
+}
+static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void)
+{
+	return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
+}
+static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void)
+{
+	return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
+}
+static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void)
+{
+	return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
+}
+static inline S3C2410_ADC * const S3C2410_GetBase_ADC(void)
+{
+	return (S3C2410_ADC * const)S3C2410_ADC_BASE;
+}
+static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void)
+{
+	return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
+}
+static inline S3C2410_SDI * const S3C2410_GetBase_SDI(void)
+{
+	return (S3C2410_SDI * const)S3C2410_SDI_BASE;
+}
+
+
+/* ISR */
+#define pISR_RESET		(*(unsigned *)(_ISR_STARTADDRESS+0x0))
+#define pISR_UNDEF		(*(unsigned *)(_ISR_STARTADDRESS+0x4))
+#define pISR_SWI		(*(unsigned *)(_ISR_STARTADDRESS+0x8))
+#define pISR_PABORT		(*(unsigned *)(_ISR_STARTADDRESS+0xC))
+#define pISR_DABORT		(*(unsigned *)(_ISR_STARTADDRESS+0x10))
+#define pISR_RESERVED		(*(unsigned *)(_ISR_STARTADDRESS+0x14))
+#define pISR_IRQ		(*(unsigned *)(_ISR_STARTADDRESS+0x18))
+#define pISR_FIQ		(*(unsigned *)(_ISR_STARTADDRESS+0x1C))
+
+#define pISR_EINT0		(*(unsigned *)(_ISR_STARTADDRESS+0x20))
+#define pISR_EINT1		(*(unsigned *)(_ISR_STARTADDRESS+0x24))
+#define pISR_EINT2		(*(unsigned *)(_ISR_STARTADDRESS+0x28))
+#define pISR_EINT3		(*(unsigned *)(_ISR_STARTADDRESS+0x2C))
+#define pISR_EINT4_7		(*(unsigned *)(_ISR_STARTADDRESS+0x30))
+#define pISR_EINT8_23		(*(unsigned *)(_ISR_STARTADDRESS+0x34))
+#define pISR_BAT_FLT		(*(unsigned *)(_ISR_STARTADDRESS+0x3C))
+#define pISR_TICK		(*(unsigned *)(_ISR_STARTADDRESS+0x40))
+#define pISR_WDT		(*(unsigned *)(_ISR_STARTADDRESS+0x44))
+#define pISR_TIMER0		(*(unsigned *)(_ISR_STARTADDRESS+0x48))
+#define pISR_TIMER1		(*(unsigned *)(_ISR_STARTADDRESS+0x4C))
+#define pISR_TIMER2		(*(unsigned *)(_ISR_STARTADDRESS+0x50))
+#define pISR_TIMER3		(*(unsigned *)(_ISR_STARTADDRESS+0x54))
+#define pISR_TIMER4		(*(unsigned *)(_ISR_STARTADDRESS+0x58))
+#define pISR_UART2		(*(unsigned *)(_ISR_STARTADDRESS+0x5C))
+#define pISR_NOTUSED		(*(unsigned *)(_ISR_STARTADDRESS+0x60))
+#define pISR_DMA0		(*(unsigned *)(_ISR_STARTADDRESS+0x64))
+#define pISR_DMA1		(*(unsigned *)(_ISR_STARTADDRESS+0x68))
+#define pISR_DMA2		(*(unsigned *)(_ISR_STARTADDRESS+0x6C))
+#define pISR_DMA3		(*(unsigned *)(_ISR_STARTADDRESS+0x70))
+#define pISR_SDI		(*(unsigned *)(_ISR_STARTADDRESS+0x74))
+#define pISR_SPI0		(*(unsigned *)(_ISR_STARTADDRESS+0x78))
+#define pISR_UART1		(*(unsigned *)(_ISR_STARTADDRESS+0x7C))
+#define pISR_USBD		(*(unsigned *)(_ISR_STARTADDRESS+0x84))
+#define pISR_USBH		(*(unsigned *)(_ISR_STARTADDRESS+0x88))
+#define pISR_IIC		(*(unsigned *)(_ISR_STARTADDRESS+0x8C))
+#define pISR_UART0		(*(unsigned *)(_ISR_STARTADDRESS+0x90))
+#define pISR_SPI1		(*(unsigned *)(_ISR_STARTADDRESS+0x94))
+#define pISR_RTC		(*(unsigned *)(_ISR_STARTADDRESS+0x98))
+#define pISR_ADC		(*(unsigned *)(_ISR_STARTADDRESS+0xA0))
+
+
+/* PENDING BIT */
+#define BIT_EINT0		(0x1)
+#define BIT_EINT1		(0x1<<1)
+#define BIT_EINT2		(0x1<<2)
+#define BIT_EINT3		(0x1<<3)
+#define BIT_EINT4_7		(0x1<<4)
+#define BIT_EINT8_23		(0x1<<5)
+#define BIT_BAT_FLT		(0x1<<7)
+#define BIT_TICK		(0x1<<8)
+#define BIT_WDT			(0x1<<9)
+#define BIT_TIMER0		(0x1<<10)
+#define BIT_TIMER1		(0x1<<11)
+#define BIT_TIMER2		(0x1<<12)
+#define BIT_TIMER3		(0x1<<13)
+#define BIT_TIMER4		(0x1<<14)
+#define BIT_UART2		(0x1<<15)
+#define BIT_LCD			(0x1<<16)
+#define BIT_DMA0		(0x1<<17)
+#define BIT_DMA1		(0x1<<18)
+#define BIT_DMA2		(0x1<<19)
+#define BIT_DMA3		(0x1<<20)
+#define BIT_SDI			(0x1<<21)
+#define BIT_SPI0		(0x1<<22)
+#define BIT_UART1		(0x1<<23)
+#define BIT_USBD		(0x1<<25)
+#define BIT_USBH		(0x1<<26)
+#define BIT_IIC			(0x1<<27)
+#define BIT_UART0		(0x1<<28)
+#define BIT_SPI1		(0x1<<29)
+#define BIT_RTC			(0x1<<30)
+#define BIT_ADC			(0x1<<31)
+#define BIT_ALLMSK		(0xFFFFFFFF)
+
+#define ClearPending(bit) {\
+		 rSRCPND = bit;\
+		 rINTPND = bit;\
+		 rINTPND;\
+		 }
+/* Wait until rINTPND is changed for the case that the ISR is very short. */
+#endif /*__S3C2410_H__*/
diff --git a/include/s3c24x0.h b/include/s3c24x0.h
new file mode 100755
index 0000000..71f35a5
--- /dev/null
+++ b/include/s3c24x0.h
@@ -0,0 +1,1135 @@
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME	    : s3c24x0.h
+ * Version  : 31.3.2003
+ *
+ * common stuff for SAMSUNG S3C24X0 SoC
+ ************************************************/
+
+#ifndef __S3C24X0_H__
+#define __S3C24X0_H__
+
+typedef volatile u8	S3C24X0_REG8;
+typedef volatile u16	S3C24X0_REG16;
+typedef volatile u32	S3C24X0_REG32;
+
+/* Memory controller (see manual chapter 5) */
+typedef struct {
+	S3C24X0_REG32	BWSCON;
+	S3C24X0_REG32	BANKCON[8];
+	S3C24X0_REG32	REFRESH;
+	S3C24X0_REG32	BANKSIZE;
+	S3C24X0_REG32	MRSRB6;
+	S3C24X0_REG32	MRSRB7;
+} /*__attribute__((__packed__))*/ S3C24X0_MEMCTL;
+
+
+/* USB HOST (see manual chapter 12) */
+typedef struct {
+	S3C24X0_REG32	HcRevision;
+	S3C24X0_REG32	HcControl;
+	S3C24X0_REG32	HcCommonStatus;
+	S3C24X0_REG32	HcInterruptStatus;
+	S3C24X0_REG32	HcInterruptEnable;
+	S3C24X0_REG32	HcInterruptDisable;
+	S3C24X0_REG32	HcHCCA;
+	S3C24X0_REG32	HcPeriodCuttendED;
+	S3C24X0_REG32	HcControlHeadED;
+	S3C24X0_REG32	HcControlCurrentED;
+	S3C24X0_REG32	HcBulkHeadED;
+	S3C24X0_REG32	HcBuldCurrentED;
+	S3C24X0_REG32	HcDoneHead;
+	S3C24X0_REG32	HcRmInterval;
+	S3C24X0_REG32	HcFmRemaining;
+	S3C24X0_REG32	HcFmNumber;
+	S3C24X0_REG32	HcPeriodicStart;
+	S3C24X0_REG32	HcLSThreshold;
+	S3C24X0_REG32	HcRhDescriptorA;
+	S3C24X0_REG32	HcRhDescriptorB;
+	S3C24X0_REG32	HcRhStatus;
+	S3C24X0_REG32	HcRhPortStatus1;
+	S3C24X0_REG32	HcRhPortStatus2;
+} /*__attribute__((__packed__))*/ S3C24X0_USB_HOST;
+
+
+/* INTERRUPT (see manual chapter 14) */
+typedef struct {
+	S3C24X0_REG32	SRCPND;
+	S3C24X0_REG32	INTMOD;
+	S3C24X0_REG32	INTMSK;
+	S3C24X0_REG32	PRIORITY;
+	S3C24X0_REG32	INTPND;
+	S3C24X0_REG32	INTOFFSET;
+#ifdef CONFIG_S3C2410
+	S3C24X0_REG32	SUBSRCPND;
+	S3C24X0_REG32	INTSUBMSK;
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_INTERRUPT;
+
+
+/* DMAS (see manual chapter 8) */
+typedef struct {
+	S3C24X0_REG32	DISRC;
+#ifdef CONFIG_S3C2410
+	S3C24X0_REG32	DISRCC;
+#endif
+	S3C24X0_REG32	DIDST;
+#ifdef CONFIG_S3C2410
+	S3C24X0_REG32	DIDSTC;
+#endif
+	S3C24X0_REG32	DCON;
+	S3C24X0_REG32	DSTAT;
+	S3C24X0_REG32	DCSRC;
+	S3C24X0_REG32	DCDST;
+	S3C24X0_REG32	DMASKTRIG;
+#ifdef CONFIG_S3C2400
+	S3C24X0_REG32	res[1];
+#endif
+#ifdef CONFIG_S3C2410
+	S3C24X0_REG32	res[7];
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_DMA;
+
+typedef struct {
+	S3C24X0_DMA	dma[4];
+} /*__attribute__((__packed__))*/ S3C24X0_DMAS;
+
+
+/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
+/*                          (see S3C2410 manual chapter 7) */
+typedef struct {
+	S3C24X0_REG32	LOCKTIME;
+	S3C24X0_REG32	MPLLCON;
+	S3C24X0_REG32	UPLLCON;
+	S3C24X0_REG32	CLKCON;
+	S3C24X0_REG32	CLKSLOW;
+	S3C24X0_REG32	CLKDIVN;
+} /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;
+
+
+/* LCD CONTROLLER (see manual chapter 15) */
+typedef struct {
+	S3C24X0_REG32	LCDCON1;
+	S3C24X0_REG32	LCDCON2;
+	S3C24X0_REG32	LCDCON3;
+	S3C24X0_REG32	LCDCON4;
+	S3C24X0_REG32	LCDCON5;
+	S3C24X0_REG32	LCDSADDR1;
+	S3C24X0_REG32	LCDSADDR2;
+	S3C24X0_REG32	LCDSADDR3;
+	S3C24X0_REG32	REDLUT;
+	S3C24X0_REG32	GREENLUT;
+	S3C24X0_REG32	BLUELUT;
+	S3C24X0_REG32	res[8];
+	S3C24X0_REG32	DITHMODE;
+	S3C24X0_REG32	TPAL;
+#ifdef CONFIG_S3C2410
+	S3C24X0_REG32	LCDINTPND;
+	S3C24X0_REG32	LCDSRCPND;
+	S3C24X0_REG32	LCDINTMSK;
+	S3C24X0_REG32	LPCSEL;
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_LCD;
+
+
+/* NAND FLASH (see S3C2410 manual chapter 6) */
+typedef struct {
+	S3C24X0_REG32	NFCONF;
+	S3C24X0_REG32	NFCMD;
+	S3C24X0_REG32	NFADDR;
+	S3C24X0_REG32	NFDATA;
+	S3C24X0_REG32	NFSTAT;
+	S3C24X0_REG32	NFECC;
+} /*__attribute__((__packed__))*/ S3C2410_NAND;
+
+
+/* UART (see manual chapter 11) */
+typedef struct {
+	S3C24X0_REG32	ULCON;
+	S3C24X0_REG32	UCON;
+	S3C24X0_REG32	UFCON;
+	S3C24X0_REG32	UMCON;
+	S3C24X0_REG32	UTRSTAT;
+	S3C24X0_REG32	UERSTAT;
+	S3C24X0_REG32	UFSTAT;
+	S3C24X0_REG32	UMSTAT;
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	UTXH;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	URXH;
+#else /* Little Endian */
+	S3C24X0_REG8	UTXH;
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	URXH;
+	S3C24X0_REG8	res2[3];
+#endif
+	S3C24X0_REG32	UBRDIV;
+} /*__attribute__((__packed__))*/ S3C24X0_UART;
+
+
+/* PWM TIMER (see manual chapter 10) */
+typedef struct {
+	S3C24X0_REG32	TCNTB;
+	S3C24X0_REG32	TCMPB;
+	S3C24X0_REG32	TCNTO;
+} /*__attribute__((__packed__))*/ S3C24X0_TIMER;
+
+typedef struct {
+	S3C24X0_REG32	TCFG0;
+	S3C24X0_REG32	TCFG1;
+	S3C24X0_REG32	TCON;
+	S3C24X0_TIMER	ch[4];
+	S3C24X0_REG32	TCNTB4;
+	S3C24X0_REG32	TCNTO4;
+} /*__attribute__((__packed__))*/ S3C24X0_TIMERS;
+
+
+/* USB DEVICE (see manual chapter 13) */
+typedef struct {
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG8	res[3];
+	S3C24X0_REG8	EP_FIFO_REG;
+#else /*  little endian */
+	S3C24X0_REG8	EP_FIFO_REG;
+	S3C24X0_REG8	res[3];
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_FIFOS;
+
+typedef struct {
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	EP_DMA_CON;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	EP_DMA_UNIT;
+	S3C24X0_REG8	res3[3];
+	S3C24X0_REG8	EP_DMA_FIFO;
+	S3C24X0_REG8	res4[3];
+	S3C24X0_REG8	EP_DMA_TTC_L;
+	S3C24X0_REG8	res5[3];
+	S3C24X0_REG8	EP_DMA_TTC_M;
+	S3C24X0_REG8	res6[3];
+	S3C24X0_REG8	EP_DMA_TTC_H;
+#else /*  little endian */
+	S3C24X0_REG8	EP_DMA_CON;
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	EP_DMA_UNIT;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	EP_DMA_FIFO;
+	S3C24X0_REG8	res3[3];
+	S3C24X0_REG8	EP_DMA_TTC_L;
+	S3C24X0_REG8	res4[3];
+	S3C24X0_REG8	EP_DMA_TTC_M;
+	S3C24X0_REG8	res5[3];
+	S3C24X0_REG8	EP_DMA_TTC_H;
+	S3C24X0_REG8	res6[3];
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_DMAS;
+
+typedef struct {
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	FUNC_ADDR_REG;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	PWR_REG;
+	S3C24X0_REG8	res3[3];
+	S3C24X0_REG8	EP_INT_REG;
+	S3C24X0_REG8	res4[15];
+	S3C24X0_REG8	USB_INT_REG;
+	S3C24X0_REG8	res5[3];
+	S3C24X0_REG8	EP_INT_EN_REG;
+	S3C24X0_REG8	res6[15];
+	S3C24X0_REG8	USB_INT_EN_REG;
+	S3C24X0_REG8	res7[3];
+	S3C24X0_REG8	FRAME_NUM1_REG;
+	S3C24X0_REG8	res8[3];
+	S3C24X0_REG8	FRAME_NUM2_REG;
+	S3C24X0_REG8	res9[3];
+	S3C24X0_REG8	INDEX_REG;
+	S3C24X0_REG8	res10[7];
+	S3C24X0_REG8	MAXP_REG;
+	S3C24X0_REG8	res11[3];
+	S3C24X0_REG8	EP0_CSR_IN_CSR1_REG;
+	S3C24X0_REG8	res12[3];
+	S3C24X0_REG8	IN_CSR2_REG;
+	S3C24X0_REG8	res13[7];
+	S3C24X0_REG8	OUT_CSR1_REG;
+	S3C24X0_REG8	res14[3];
+	S3C24X0_REG8	OUT_CSR2_REG;
+	S3C24X0_REG8	res15[3];
+	S3C24X0_REG8	OUT_FIFO_CNT1_REG;
+	S3C24X0_REG8	res16[3];
+	S3C24X0_REG8	OUT_FIFO_CNT2_REG;
+#else /*  little endian */
+	S3C24X0_REG8	FUNC_ADDR_REG;
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	PWR_REG;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	EP_INT_REG;
+	S3C24X0_REG8	res3[15];
+	S3C24X0_REG8	USB_INT_REG;
+	S3C24X0_REG8	res4[3];
+	S3C24X0_REG8	EP_INT_EN_REG;
+	S3C24X0_REG8	res5[15];
+	S3C24X0_REG8	USB_INT_EN_REG;
+	S3C24X0_REG8	res6[3];
+	S3C24X0_REG8	FRAME_NUM1_REG;
+	S3C24X0_REG8	res7[3];
+	S3C24X0_REG8	FRAME_NUM2_REG;
+	S3C24X0_REG8	res8[3];
+	S3C24X0_REG8	INDEX_REG;
+	S3C24X0_REG8	res9[7];
+	S3C24X0_REG8	MAXP_REG;
+	S3C24X0_REG8	res10[7];
+	S3C24X0_REG8	EP0_CSR_IN_CSR1_REG;
+	S3C24X0_REG8	res11[3];
+	S3C24X0_REG8	IN_CSR2_REG;
+	S3C24X0_REG8	res12[3];
+	S3C24X0_REG8	OUT_CSR1_REG;
+	S3C24X0_REG8	res13[7];
+	S3C24X0_REG8	OUT_CSR2_REG;
+	S3C24X0_REG8	res14[3];
+	S3C24X0_REG8	OUT_FIFO_CNT1_REG;
+	S3C24X0_REG8	res15[3];
+	S3C24X0_REG8	OUT_FIFO_CNT2_REG;
+	S3C24X0_REG8	res16[3];
+#endif /*  __BIG_ENDIAN */
+	S3C24X0_USB_DEV_FIFOS	fifo[5];
+	S3C24X0_USB_DEV_DMAS	dma[5];
+} /*__attribute__((__packed__))*/ S3C24X0_USB_DEVICE;
+
+
+/* WATCH DOG TIMER (see manual chapter 18) */
+typedef struct {
+	S3C24X0_REG32	WTCON;
+	S3C24X0_REG32	WTDAT;
+	S3C24X0_REG32	WTCNT;
+} /*__attribute__((__packed__))*/ S3C24X0_WATCHDOG;
+
+
+/* IIC (see manual chapter 20) */
+typedef struct {
+	S3C24X0_REG32	IICCON;
+	S3C24X0_REG32	IICSTAT;
+	S3C24X0_REG32	IICADD;
+	S3C24X0_REG32	IICDS;
+} /*__attribute__((__packed__))*/ S3C24X0_I2C;
+
+
+/* IIS (see manual chapter 21) */
+typedef struct {
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG16	res1;
+	S3C24X0_REG16	IISCON;
+	S3C24X0_REG16	res2;
+	S3C24X0_REG16	IISMOD;
+	S3C24X0_REG16	res3;
+	S3C24X0_REG16	IISPSR;
+	S3C24X0_REG16	res4;
+	S3C24X0_REG16	IISFCON;
+	S3C24X0_REG16	res5;
+	S3C24X0_REG16	IISFIFO;
+#else /*  little endian */
+	S3C24X0_REG16	IISCON;
+	S3C24X0_REG16	res1;
+	S3C24X0_REG16	IISMOD;
+	S3C24X0_REG16	res2;
+	S3C24X0_REG16	IISPSR;
+	S3C24X0_REG16	res3;
+	S3C24X0_REG16	IISFCON;
+	S3C24X0_REG16	res4;
+	S3C24X0_REG16	IISFIFO;
+	S3C24X0_REG16	res5;
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_I2S;
+
+
+/* I/O PORT (see manual chapter 9) */
+typedef struct {
+#ifdef CONFIG_S3C2400
+	S3C24X0_REG32	PACON;
+	S3C24X0_REG32	PADAT;
+
+	S3C24X0_REG32	PBCON;
+	S3C24X0_REG32	PBDAT;
+	S3C24X0_REG32	PBUP;
+
+	S3C24X0_REG32	PCCON;
+	S3C24X0_REG32	PCDAT;
+	S3C24X0_REG32	PCUP;
+
+	S3C24X0_REG32	PDCON;
+	S3C24X0_REG32	PDDAT;
+	S3C24X0_REG32	PDUP;
+
+	S3C24X0_REG32	PECON;
+	S3C24X0_REG32	PEDAT;
+	S3C24X0_REG32	PEUP;
+
+	S3C24X0_REG32	PFCON;
+	S3C24X0_REG32	PFDAT;
+	S3C24X0_REG32	PFUP;
+
+	S3C24X0_REG32	PGCON;
+	S3C24X0_REG32	PGDAT;
+	S3C24X0_REG32	PGUP;
+
+	S3C24X0_REG32	OPENCR;
+
+	S3C24X0_REG32	MISCCR;
+	S3C24X0_REG32	EXTINT;
+#endif
+#ifdef CONFIG_S3C2410
+	S3C24X0_REG32	GPACON;
+	S3C24X0_REG32	GPADAT;
+	S3C24X0_REG32	res1[2];
+	S3C24X0_REG32	GPBCON;
+	S3C24X0_REG32	GPBDAT;
+	S3C24X0_REG32	GPBUP;
+	S3C24X0_REG32	res2;
+	S3C24X0_REG32	GPCCON;
+	S3C24X0_REG32	GPCDAT;
+	S3C24X0_REG32	GPCUP;
+	S3C24X0_REG32	res3;
+	S3C24X0_REG32	GPDCON;
+	S3C24X0_REG32	GPDDAT;
+	S3C24X0_REG32	GPDUP;
+	S3C24X0_REG32	res4;
+	S3C24X0_REG32	GPECON;
+	S3C24X0_REG32	GPEDAT;
+	S3C24X0_REG32	GPEUP;
+	S3C24X0_REG32	res5;
+	S3C24X0_REG32	GPFCON;
+	S3C24X0_REG32	GPFDAT;
+	S3C24X0_REG32	GPFUP;
+	S3C24X0_REG32	res6;
+	S3C24X0_REG32	GPGCON;
+	S3C24X0_REG32	GPGDAT;
+	S3C24X0_REG32	GPGUP;
+	S3C24X0_REG32	res7;
+	S3C24X0_REG32	GPHCON;
+	S3C24X0_REG32	GPHDAT;
+	S3C24X0_REG32	GPHUP;
+	S3C24X0_REG32	res8;
+
+	S3C24X0_REG32	MISCCR;
+	S3C24X0_REG32	DCLKCON;
+	S3C24X0_REG32	EXTINT0;
+	S3C24X0_REG32	EXTINT1;
+	S3C24X0_REG32	EXTINT2;
+	S3C24X0_REG32	EINTFLT0;
+	S3C24X0_REG32	EINTFLT1;
+	S3C24X0_REG32	EINTFLT2;
+	S3C24X0_REG32	EINTFLT3;
+	S3C24X0_REG32	EINTMASK;
+	S3C24X0_REG32	EINTPEND;
+	S3C24X0_REG32	GSTATUS0;
+	S3C24X0_REG32	GSTATUS1;
+	S3C24X0_REG32	GSTATUS2;
+	S3C24X0_REG32	GSTATUS3;
+	S3C24X0_REG32	GSTATUS4;
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_GPIO;
+
+
+/* RTC (see manual chapter 17) */
+typedef struct {
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG8	res1[67];
+	S3C24X0_REG8	RTCCON;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	TICNT;
+	S3C24X0_REG8	res3[11];
+	S3C24X0_REG8	RTCALM;
+	S3C24X0_REG8	res4[3];
+	S3C24X0_REG8	ALMSEC;
+	S3C24X0_REG8	res5[3];
+	S3C24X0_REG8	ALMMIN;
+	S3C24X0_REG8	res6[3];
+	S3C24X0_REG8	ALMHOUR;
+	S3C24X0_REG8	res7[3];
+	S3C24X0_REG8	ALMDATE;
+	S3C24X0_REG8	res8[3];
+	S3C24X0_REG8	ALMMON;
+	S3C24X0_REG8	res9[3];
+	S3C24X0_REG8	ALMYEAR;
+	S3C24X0_REG8	res10[3];
+	S3C24X0_REG8	RTCRST;
+	S3C24X0_REG8	res11[3];
+	S3C24X0_REG8	BCDSEC;
+	S3C24X0_REG8	res12[3];
+	S3C24X0_REG8	BCDMIN;
+	S3C24X0_REG8	res13[3];
+	S3C24X0_REG8	BCDHOUR;
+	S3C24X0_REG8	res14[3];
+	S3C24X0_REG8	BCDDATE;
+	S3C24X0_REG8	res15[3];
+	S3C24X0_REG8	BCDDAY;
+	S3C24X0_REG8	res16[3];
+	S3C24X0_REG8	BCDMON;
+	S3C24X0_REG8	res17[3];
+	S3C24X0_REG8	BCDYEAR;
+#else /*  little endian */
+	S3C24X0_REG8	res0[64];
+	S3C24X0_REG8	RTCCON;
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	TICNT;
+	S3C24X0_REG8	res2[11];
+	S3C24X0_REG8	RTCALM;
+	S3C24X0_REG8	res3[3];
+	S3C24X0_REG8	ALMSEC;
+	S3C24X0_REG8	res4[3];
+	S3C24X0_REG8	ALMMIN;
+	S3C24X0_REG8	res5[3];
+	S3C24X0_REG8	ALMHOUR;
+	S3C24X0_REG8	res6[3];
+	S3C24X0_REG8	ALMDATE;
+	S3C24X0_REG8	res7[3];
+	S3C24X0_REG8	ALMMON;
+	S3C24X0_REG8	res8[3];
+	S3C24X0_REG8	ALMYEAR;
+	S3C24X0_REG8	res9[3];
+	S3C24X0_REG8	RTCRST;
+	S3C24X0_REG8	res10[3];
+	S3C24X0_REG8	BCDSEC;
+	S3C24X0_REG8	res11[3];
+	S3C24X0_REG8	BCDMIN;
+	S3C24X0_REG8	res12[3];
+	S3C24X0_REG8	BCDHOUR;
+	S3C24X0_REG8	res13[3];
+	S3C24X0_REG8	BCDDATE;
+	S3C24X0_REG8	res14[3];
+	S3C24X0_REG8	BCDDAY;
+	S3C24X0_REG8	res15[3];
+	S3C24X0_REG8	BCDMON;
+	S3C24X0_REG8	res16[3];
+	S3C24X0_REG8	BCDYEAR;
+	S3C24X0_REG8	res17[3];
+#endif
+} /*__attribute__((__packed__))*/ S3C24X0_RTC;
+
+
+/* ADC (see manual chapter 16) */
+typedef struct {
+	S3C24X0_REG32	ADCCON;
+	S3C24X0_REG32	ADCDAT;
+} /*__attribute__((__packed__))*/ S3C2400_ADC;
+
+
+/* ADC (see manual chapter 16) */
+typedef struct {
+	S3C24X0_REG32	ADCCON;
+	S3C24X0_REG32	ADCTSC;
+	S3C24X0_REG32	ADCDLY;
+	S3C24X0_REG32	ADCDAT0;
+	S3C24X0_REG32	ADCDAT1;
+} /*__attribute__((__packed__))*/ S3C2410_ADC;
+
+
+/* SPI (see manual chapter 22) */
+typedef struct {
+	S3C24X0_REG32	SPCON;
+	S3C24X0_REG32	SPSTA;
+	S3C24X0_REG32	SPPIN;
+	S3C24X0_REG32	SPPRE;
+	S3C24X0_REG32	SPTDAT;
+	S3C24X0_REG32	SPRDAT;
+	S3C24X0_REG32	res[2];
+} __attribute__((__packed__)) S3C24X0_SPI_CHANNEL;
+
+typedef struct {
+	S3C24X0_SPI_CHANNEL	ch[S3C24X0_SPI_CHANNELS];
+} /*__attribute__((__packed__))*/ S3C24X0_SPI;
+
+
+/* MMC INTERFACE (see S3C2400 manual chapter 19) */
+typedef struct {
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	MMCON;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	MMCRR;
+	S3C24X0_REG8	res3[3];
+	S3C24X0_REG8	MMFCON;
+	S3C24X0_REG8	res4[3];
+	S3C24X0_REG8	MMSTA;
+	S3C24X0_REG16	res5;
+	S3C24X0_REG16	MMFSTA;
+	S3C24X0_REG8	res6[3];
+	S3C24X0_REG8	MMPRE;
+	S3C24X0_REG16	res7;
+	S3C24X0_REG16	MMLEN;
+	S3C24X0_REG8	res8[3];
+	S3C24X0_REG8	MMCR7;
+	S3C24X0_REG32	MMRSP[4];
+	S3C24X0_REG8	res9[3];
+	S3C24X0_REG8	MMCMD0;
+	S3C24X0_REG32	MMCMD1;
+	S3C24X0_REG16	res10;
+	S3C24X0_REG16	MMCR16;
+	S3C24X0_REG8	res11[3];
+	S3C24X0_REG8	MMDAT;
+#else
+	S3C24X0_REG8	MMCON;
+	S3C24X0_REG8	res1[3];
+	S3C24X0_REG8	MMCRR;
+	S3C24X0_REG8	res2[3];
+	S3C24X0_REG8	MMFCON;
+	S3C24X0_REG8	res3[3];
+	S3C24X0_REG8	MMSTA;
+	S3C24X0_REG8	res4[3];
+	S3C24X0_REG16	MMFSTA;
+	S3C24X0_REG16	res5;
+	S3C24X0_REG8	MMPRE;
+	S3C24X0_REG8	res6[3];
+	S3C24X0_REG16	MMLEN;
+	S3C24X0_REG16	res7;
+	S3C24X0_REG8	MMCR7;
+	S3C24X0_REG8	res8[3];
+	S3C24X0_REG32	MMRSP[4];
+	S3C24X0_REG8	MMCMD0;
+	S3C24X0_REG8	res9[3];
+	S3C24X0_REG32	MMCMD1;
+	S3C24X0_REG16	MMCR16;
+	S3C24X0_REG16	res10;
+	S3C24X0_REG8	MMDAT;
+	S3C24X0_REG8	res11[3];
+#endif
+} /*__attribute__((__packed__))*/ S3C2400_MMC;
+
+
+/* SD INTERFACE (see S3C2410 manual chapter 19) */
+typedef struct {
+	S3C24X0_REG32	SDICON;
+	S3C24X0_REG32	SDIPRE;
+	S3C24X0_REG32	SDICARG;
+	S3C24X0_REG32	SDICCON;
+	S3C24X0_REG32	SDICSTA;
+	S3C24X0_REG32	SDIRSP0;
+	S3C24X0_REG32	SDIRSP1;
+	S3C24X0_REG32	SDIRSP2;
+	S3C24X0_REG32	SDIRSP3;
+	S3C24X0_REG32	SDIDTIMER;
+	S3C24X0_REG32	SDIBSIZE;
+	S3C24X0_REG32	SDIDCON;
+	S3C24X0_REG32	SDIDCNT;
+	S3C24X0_REG32	SDIDSTA;
+	S3C24X0_REG32	SDIFSTA;
+#ifdef __BIG_ENDIAN
+	S3C24X0_REG8	res[3];
+	S3C24X0_REG8	SDIDAT;
+#else
+	S3C24X0_REG8	SDIDAT;
+	S3C24X0_REG8	res[3];
+#endif
+	S3C24X0_REG32	SDIIMSK;
+} /*__attribute__((__packed__))*/ S3C2410_SDI;
+
+
+#if 0
+/* Memory control */
+#define rBWSCON			(*(volatile unsigned *)0x48000000)
+#define rBANKCON0		(*(volatile unsigned *)0x48000004)
+#define rBANKCON1		(*(volatile unsigned *)0x48000008)
+#define rBANKCON2		(*(volatile unsigned *)0x4800000C)
+#define rBANKCON3		(*(volatile unsigned *)0x48000010)
+#define rBANKCON4		(*(volatile unsigned *)0x48000014)
+#define rBANKCON5		(*(volatile unsigned *)0x48000018)
+#define rBANKCON6		(*(volatile unsigned *)0x4800001C)
+#define rBANKCON7		(*(volatile unsigned *)0x48000020)
+#define rREFRESH		(*(volatile unsigned *)0x48000024)
+#define rBANKSIZE		(*(volatile unsigned *)0x48000028)
+#define rMRSRB6			(*(volatile unsigned *)0x4800002C)
+#define rMRSRB7			(*(volatile unsigned *)0x48000030)
+
+
+/* USB HOST */
+#define rHcRevision		(*(volatile unsigned *)0x49000000)
+#define rHcControl		(*(volatile unsigned *)0x49000004)
+#define rHcCommonStatus		(*(volatile unsigned *)0x49000008)
+#define rHcInterruptStatus	(*(volatile unsigned *)0x4900000C)
+#define rHcInterruptEnable	(*(volatile unsigned *)0x49000010)
+#define rHcInterruptDisable	(*(volatile unsigned *)0x49000014)
+#define rHcHCCA			(*(volatile unsigned *)0x49000018)
+#define rHcPeriodCuttendED	(*(volatile unsigned *)0x4900001C)
+#define rHcControlHeadED	(*(volatile unsigned *)0x49000020)
+#define rHcControlCurrentED	(*(volatile unsigned *)0x49000024)
+#define rHcBulkHeadED		(*(volatile unsigned *)0x49000028)
+#define rHcBuldCurrentED	(*(volatile unsigned *)0x4900002C)
+#define rHcDoneHead		(*(volatile unsigned *)0x49000030)
+#define rHcRmInterval		(*(volatile unsigned *)0x49000034)
+#define rHcFmRemaining		(*(volatile unsigned *)0x49000038)
+#define rHcFmNumber		(*(volatile unsigned *)0x4900003C)
+#define rHcPeriodicStart	(*(volatile unsigned *)0x49000040)
+#define rHcLSThreshold		(*(volatile unsigned *)0x49000044)
+#define rHcRhDescriptorA	(*(volatile unsigned *)0x49000048)
+#define rHcRhDescriptorB	(*(volatile unsigned *)0x4900004C)
+#define rHcRhStatus		(*(volatile unsigned *)0x49000050)
+#define rHcRhPortStatus1	(*(volatile unsigned *)0x49000054)
+#define rHcRhPortStatus2	(*(volatile unsigned *)0x49000058)
+
+
+/* INTERRUPT */
+#define rSRCPND			(*(volatile unsigned *)0x4A000000)
+#define rINTMOD			(*(volatile unsigned *)0x4A000004)
+#define rINTMSK			(*(volatile unsigned *)0x4A000008)
+#define rPRIORITY		(*(volatile unsigned *)0x4A00000C)
+#define rINTPND			(*(volatile unsigned *)0x4A000010)
+#define rINTOFFSET		(*(volatile unsigned *)0x4A000014)
+#define rSUBSRCPND		(*(volatile unsigned *)0x4A000018)
+#define rINTSUBMSK		(*(volatile unsigned *)0x4A00001C)
+
+
+/* DMA */
+#define rDISRC0			(*(volatile unsigned *)0x4B000000)
+#define rDISRCC0		(*(volatile unsigned *)0x4B000004)
+#define rDIDST0			(*(volatile unsigned *)0x4B000008)
+#define rDIDSTC0		(*(volatile unsigned *)0x4B00000C)
+#define rDCON0			(*(volatile unsigned *)0x4B000010)
+#define rDSTAT0			(*(volatile unsigned *)0x4B000014)
+#define rDCSRC0			(*(volatile unsigned *)0x4B000018)
+#define rDCDST0			(*(volatile unsigned *)0x4B00001C)
+#define rDMASKTRIG0		(*(volatile unsigned *)0x4B000020)
+#define rDISRC1			(*(volatile unsigned *)0x4B000040)
+#define rDISRCC1		(*(volatile unsigned *)0x4B000044)
+#define rDIDST1			(*(volatile unsigned *)0x4B000048)
+#define rDIDSTC1		(*(volatile unsigned *)0x4B00004C)
+#define rDCON1			(*(volatile unsigned *)0x4B000050)
+#define rDSTAT1			(*(volatile unsigned *)0x4B000054)
+#define rDCSRC1			(*(volatile unsigned *)0x4B000058)
+#define rDCDST1			(*(volatile unsigned *)0x4B00005C)
+#define rDMASKTRIG1		(*(volatile unsigned *)0x4B000060)
+#define rDISRC2			(*(volatile unsigned *)0x4B000080)
+#define rDISRCC2		(*(volatile unsigned *)0x4B000084)
+#define rDIDST2			(*(volatile unsigned *)0x4B000088)
+#define rDIDSTC2		(*(volatile unsigned *)0x4B00008C)
+#define rDCON2			(*(volatile unsigned *)0x4B000090)
+#define rDSTAT2			(*(volatile unsigned *)0x4B000094)
+#define rDCSRC2			(*(volatile unsigned *)0x4B000098)
+#define rDCDST2			(*(volatile unsigned *)0x4B00009C)
+#define rDMASKTRIG2		(*(volatile unsigned *)0x4B0000A0)
+#define rDISRC3			(*(volatile unsigned *)0x4B0000C0)
+#define rDISRCC3		(*(volatile unsigned *)0x4B0000C4)
+#define rDIDST3			(*(volatile unsigned *)0x4B0000C8)
+#define rDIDSTC3		(*(volatile unsigned *)0x4B0000CC)
+#define rDCON3			(*(volatile unsigned *)0x4B0000D0)
+#define rDSTAT3			(*(volatile unsigned *)0x4B0000D4)
+#define rDCSRC3			(*(volatile unsigned *)0x4B0000D8)
+#define rDCDST3			(*(volatile unsigned *)0x4B0000DC)
+#define rDMASKTRIG3		(*(volatile unsigned *)0x4B0000E0)
+
+
+/* CLOCK & POWER MANAGEMENT */
+#define rLOCKTIME		(*(volatile unsigned *)0x4C000000)
+#define rMPLLCON		(*(volatile unsigned *)0x4C000004)
+#define rUPLLCON		(*(volatile unsigned *)0x4C000008)
+#define rCLKCON			(*(volatile unsigned *)0x4C00000C)
+#define rCLKSLOW		(*(volatile unsigned *)0x4C000010)
+#define rCLKDIVN		(*(volatile unsigned *)0x4C000014)
+
+
+/* LCD CONTROLLER */
+#define rLCDCON1		(*(volatile unsigned *)0x4D000000)
+#define rLCDCON2		(*(volatile unsigned *)0x4D000004)
+#define rLCDCON3		(*(volatile unsigned *)0x4D000008)
+#define rLCDCON4		(*(volatile unsigned *)0x4D00000C)
+#define rLCDCON5		(*(volatile unsigned *)0x4D000010)
+#define rLCDSADDR1		(*(volatile unsigned *)0x4D000014)
+#define rLCDSADDR2		(*(volatile unsigned *)0x4D000018)
+#define rLCDSADDR3		(*(volatile unsigned *)0x4D00001C)
+#define rREDLUT			(*(volatile unsigned *)0x4D000020)
+#define rGREENLUT		(*(volatile unsigned *)0x4D000024)
+#define rBLUELUT		(*(volatile unsigned *)0x4D000028)
+#define rDITHMODE		(*(volatile unsigned *)0x4D00004C)
+#define rTPAL			(*(volatile unsigned *)0x4D000050)
+#define rLCDINTPND		(*(volatile unsigned *)0x4D000054)
+#define rLCDSRCPND		(*(volatile unsigned *)0x4D000058)
+#define rLCDINTMSK		(*(volatile unsigned *)0x4D00005C)
+
+
+/* NAND FLASH */
+#define rNFCONF			(*(volatile unsigned *)0x4E000000)
+#define rNFCMD			(*(volatile unsigned *)0x4E000004)
+#define rNFADDR			(*(volatile unsigned *)0x4E000008)
+#define rNFDATA			(*(volatile unsigned *)0x4E00000C)
+#define rNFSTAT			(*(volatile unsigned *)0x4E000010)
+#define rNFECC			(*(volatile unsigned *)0x4E000014)
+
+
+/* UART */
+#define rULCON0			(*(volatile unsigned *)0x50000000)
+#define rUCON0			(*(volatile unsigned *)0x50000004)
+#define rUFCON0			(*(volatile unsigned *)0x50000008)
+#define rUMCON0			(*(volatile unsigned *)0x5000000C)
+#define rUTRSTAT0		(*(volatile unsigned *)0x50000010)
+#define rUERSTAT0		(*(volatile unsigned *)0x50000014)
+#define rUFSTAT0		(*(volatile unsigned *)0x50000018)
+#define rUMSTAT0		(*(volatile unsigned *)0x5000001C)
+#define rUBRDIV0		(*(volatile unsigned *)0x50000028)
+
+#define rULCON1			(*(volatile unsigned *)0x50004000)
+#define rUCON1			(*(volatile unsigned *)0x50004004)
+#define rUFCON1			(*(volatile unsigned *)0x50004008)
+#define rUMCON1			(*(volatile unsigned *)0x5000400C)
+#define rUTRSTAT1		(*(volatile unsigned *)0x50004010)
+#define rUERSTAT1		(*(volatile unsigned *)0x50004014)
+#define rUFSTAT1		(*(volatile unsigned *)0x50004018)
+#define rUMSTAT1		(*(volatile unsigned *)0x5000401C)
+#define rUBRDIV1		(*(volatile unsigned *)0x50004028)
+
+#define rULCON2			(*(volatile unsigned *)0x50008000)
+#define rUCON2			(*(volatile unsigned *)0x50008004)
+#define rUFCON2			(*(volatile unsigned *)0x50008008)
+#define rUTRSTAT2		(*(volatile unsigned *)0x50008010)
+#define rUERSTAT2		(*(volatile unsigned *)0x50008014)
+#define rUFSTAT2		(*(volatile unsigned *)0x50008018)
+#define rUBRDIV2		(*(volatile unsigned *)0x50008028)
+
+#ifdef __BIG_ENDIAN
+#define rUTXH0			(*(volatile unsigned char *)0x50000023)
+#define rURXH0			(*(volatile unsigned char *)0x50000027)
+#define rUTXH1			(*(volatile unsigned char *)0x50004023)
+#define rURXH1			(*(volatile unsigned char *)0x50004027)
+#define rUTXH2			(*(volatile unsigned char *)0x50008023)
+#define rURXH2			(*(volatile unsigned char *)0x50008027)
+
+#define WrUTXH0(ch)		(*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
+#define RdURXH0()		(*(volatile unsigned char *)0x50000027)
+#define WrUTXH1(ch)		(*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
+#define RdURXH1()		(*(volatile unsigned char *)0x50004027)
+#define WrUTXH2(ch)		(*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
+#define RdURXH2()		(*(volatile unsigned char *)0x50008027)
+
+#define UTXH0			(0x50000020+3)  /* byte_access address by DMA */
+#define URXH0			(0x50000024+3)
+#define UTXH1			(0x50004020+3)
+#define URXH1			(0x50004024+3)
+#define UTXH2			(0x50008020+3)
+#define URXH2			(0x50008024+3)
+
+#else /* Little Endian */
+#define rUTXH0			(*(volatile unsigned char *)0x50000020)
+#define rURXH0			(*(volatile unsigned char *)0x50000024)
+#define rUTXH1			(*(volatile unsigned char *)0x50004020)
+#define rURXH1			(*(volatile unsigned char *)0x50004024)
+#define rUTXH2			(*(volatile unsigned char *)0x50008020)
+#define rURXH2			(*(volatile unsigned char *)0x50008024)
+
+#define WrUTXH0(ch)		(*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
+#define RdURXH0()		(*(volatile unsigned char *)0x50000024)
+#define WrUTXH1(ch)		(*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
+#define RdURXH1()		(*(volatile unsigned char *)0x50004024)
+#define WrUTXH2(ch)		(*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
+#define RdURXH2()		(*(volatile unsigned char *)0x50008024)
+
+#define UTXH0			(0x50000020)    /* byte_access address by DMA */
+#define URXH0			(0x50000024)
+#define UTXH1			(0x50004020)
+#define URXH1			(0x50004024)
+#define UTXH2			(0x50008020)
+#define URXH2			(0x50008024)
+#endif
+
+
+/* PWM TIMER */
+#define rTCFG0			(*(volatile unsigned *)0x51000000)
+#define rTCFG1			(*(volatile unsigned *)0x51000004)
+#define rTCON			(*(volatile unsigned *)0x51000008)
+#define rTCNTB0			(*(volatile unsigned *)0x5100000C)
+#define rTCMPB0			(*(volatile unsigned *)0x51000010)
+#define rTCNTO0			(*(volatile unsigned *)0x51000014)
+#define rTCNTB1			(*(volatile unsigned *)0x51000018)
+#define rTCMPB1			(*(volatile unsigned *)0x5100001C)
+#define rTCNTO1			(*(volatile unsigned *)0x51000020)
+#define rTCNTB2			(*(volatile unsigned *)0x51000024)
+#define rTCMPB2			(*(volatile unsigned *)0x51000028)
+#define rTCNTO2			(*(volatile unsigned *)0x5100002C)
+#define rTCNTB3			(*(volatile unsigned *)0x51000030)
+#define rTCMPB3			(*(volatile unsigned *)0x51000034)
+#define rTCNTO3			(*(volatile unsigned *)0x51000038)
+#define rTCNTB4			(*(volatile unsigned *)0x5100003C)
+#define rTCNTO4			(*(volatile unsigned *)0x51000040)
+
+
+/* USB DEVICE */
+#ifdef __BIG_ENDIAN
+#define rFUNC_ADDR_REG		(*(volatile unsigned char *)0x52000143)
+#define rPWR_REG		(*(volatile unsigned char *)0x52000147)
+#define rEP_INT_REG		(*(volatile unsigned char *)0x5200014B)
+#define rUSB_INT_REG		(*(volatile unsigned char *)0x5200015B)
+#define rEP_INT_EN_REG		(*(volatile unsigned char *)0x5200015F)
+#define rUSB_INT_EN_REG		(*(volatile unsigned char *)0x5200016F)
+#define rFRAME_NUM1_REG		(*(volatile unsigned char *)0x52000173)
+#define rFRAME_NUM2_REG		(*(volatile unsigned char *)0x52000177)
+#define rINDEX_REG		(*(volatile unsigned char *)0x5200017B)
+#define rMAXP_REG		(*(volatile unsigned char *)0x52000183)
+#define rEP0_CSR		(*(volatile unsigned char *)0x52000187)
+#define rIN_CSR1_REG		(*(volatile unsigned char *)0x52000187)
+#define rIN_CSR2_REG		(*(volatile unsigned char *)0x5200018B)
+#define rOUT_CSR1_REG		(*(volatile unsigned char *)0x52000193)
+#define rOUT_CSR2_REG		(*(volatile unsigned char *)0x52000197)
+#define rOUT_FIFO_CNT1_REG	(*(volatile unsigned char *)0x5200019B)
+#define rOUT_FIFO_CNT2_REG	(*(volatile unsigned char *)0x5200019F)
+#define rEP0_FIFO		(*(volatile unsigned char *)0x520001C3)
+#define rEP1_FIFO		(*(volatile unsigned char *)0x520001C7)
+#define rEP2_FIFO		(*(volatile unsigned char *)0x520001CB)
+#define rEP3_FIFO		(*(volatile unsigned char *)0x520001CF)
+#define rEP4_FIFO		(*(volatile unsigned char *)0x520001D3)
+#define rEP1_DMA_CON		(*(volatile unsigned char *)0x52000203)
+#define rEP1_DMA_UNIT		(*(volatile unsigned char *)0x52000207)
+#define rEP1_DMA_FIFO		(*(volatile unsigned char *)0x5200020B)
+#define rEP1_DMA_TX_LO		(*(volatile unsigned char *)0x5200020F)
+#define rEP1_DMA_TX_MD		(*(volatile unsigned char *)0x52000213)
+#define rEP1_DMA_TX_HI		(*(volatile unsigned char *)0x52000217)
+#define rEP2_DMA_CON		(*(volatile unsigned char *)0x5200021B)
+#define rEP2_DMA_UNIT		(*(volatile unsigned char *)0x5200021F)
+#define rEP2_DMA_FIFO		(*(volatile unsigned char *)0x52000223)
+#define rEP2_DMA_TX_LO		(*(volatile unsigned char *)0x52000227)
+#define rEP2_DMA_TX_MD		(*(volatile unsigned char *)0x5200022B)
+#define rEP2_DMA_TX_HI		(*(volatile unsigned char *)0x5200022F)
+#define rEP3_DMA_CON		(*(volatile unsigned char *)0x52000243)
+#define rEP3_DMA_UNIT		(*(volatile unsigned char *)0x52000247)
+#define rEP3_DMA_FIFO		(*(volatile unsigned char *)0x5200024B)
+#define rEP3_DMA_TX_LO		(*(volatile unsigned char *)0x5200024F)
+#define rEP3_DMA_TX_MD		(*(volatile unsigned char *)0x52000253)
+#define rEP3_DMA_TX_HI		(*(volatile unsigned char *)0x52000257)
+#define rEP4_DMA_CON		(*(volatile unsigned char *)0x5200025B)
+#define rEP4_DMA_UNIT		(*(volatile unsigned char *)0x5200025F)
+#define rEP4_DMA_FIFO		(*(volatile unsigned char *)0x52000263)
+#define rEP4_DMA_TX_LO		(*(volatile unsigned char *)0x52000267)
+#define rEP4_DMA_TX_MD		(*(volatile unsigned char *)0x5200026B)
+#define rEP4_DMA_TX_HI		(*(volatile unsigned char *)0x5200026F)
+#else /*  little endian */
+#define rFUNC_ADDR_REG		(*(volatile unsigned char *)0x52000140)
+#define rPWR_REG		(*(volatile unsigned char *)0x52000144)
+#define rEP_INT_REG		(*(volatile unsigned char *)0x52000148)
+#define rUSB_INT_REG		(*(volatile unsigned char *)0x52000158)
+#define rEP_INT_EN_REG		(*(volatile unsigned char *)0x5200015C)
+#define rUSB_INT_EN_REG		(*(volatile unsigned char *)0x5200016C)
+#define rFRAME_NUM1_REG		(*(volatile unsigned char *)0x52000170)
+#define rFRAME_NUM2_REG		(*(volatile unsigned char *)0x52000174)
+#define rINDEX_REG		(*(volatile unsigned char *)0x52000178)
+#define rMAXP_REG		(*(volatile unsigned char *)0x52000180)
+#define rEP0_CSR		(*(volatile unsigned char *)0x52000184)
+#define rIN_CSR1_REG		(*(volatile unsigned char *)0x52000184)
+#define rIN_CSR2_REG		(*(volatile unsigned char *)0x52000188)
+#define rOUT_CSR1_REG		(*(volatile unsigned char *)0x52000190)
+#define rOUT_CSR2_REG		(*(volatile unsigned char *)0x52000194)
+#define rOUT_FIFO_CNT1_REG	(*(volatile unsigned char *)0x52000198)
+#define rOUT_FIFO_CNT2_REG	(*(volatile unsigned char *)0x5200019C)
+#define rEP0_FIFO		(*(volatile unsigned char *)0x520001C0)
+#define rEP1_FIFO		(*(volatile unsigned char *)0x520001C4)
+#define rEP2_FIFO		(*(volatile unsigned char *)0x520001C8)
+#define rEP3_FIFO		(*(volatile unsigned char *)0x520001CC)
+#define rEP4_FIFO		(*(volatile unsigned char *)0x520001D0)
+#define rEP1_DMA_CON		(*(volatile unsigned char *)0x52000200)
+#define rEP1_DMA_UNIT		(*(volatile unsigned char *)0x52000204)
+#define rEP1_DMA_FIFO		(*(volatile unsigned char *)0x52000208)
+#define rEP1_DMA_TX_LO		(*(volatile unsigned char *)0x5200020C)
+#define rEP1_DMA_TX_MD		(*(volatile unsigned char *)0x52000210)
+#define rEP1_DMA_TX_HI		(*(volatile unsigned char *)0x52000214)
+#define rEP2_DMA_CON		(*(volatile unsigned char *)0x52000218)
+#define rEP2_DMA_UNIT		(*(volatile unsigned char *)0x5200021C)
+#define rEP2_DMA_FIFO		(*(volatile unsigned char *)0x52000220)
+#define rEP2_DMA_TX_LO		(*(volatile unsigned char *)0x52000224)
+#define rEP2_DMA_TX_MD		(*(volatile unsigned char *)0x52000228)
+#define rEP2_DMA_TX_HI		(*(volatile unsigned char *)0x5200022C)
+#define rEP3_DMA_CON		(*(volatile unsigned char *)0x52000240)
+#define rEP3_DMA_UNIT		(*(volatile unsigned char *)0x52000244)
+#define rEP3_DMA_FIFO		(*(volatile unsigned char *)0x52000248)
+#define rEP3_DMA_TX_LO		(*(volatile unsigned char *)0x5200024C)
+#define rEP3_DMA_TX_MD		(*(volatile unsigned char *)0x52000250)
+#define rEP3_DMA_TX_HI		(*(volatile unsigned char *)0x52000254)
+#define rEP4_DMA_CON		(*(volatile unsigned char *)0x52000258)
+#define rEP4_DMA_UNIT		(*(volatile unsigned char *)0x5200025C)
+#define rEP4_DMA_FIFO		(*(volatile unsigned char *)0x52000260)
+#define rEP4_DMA_TX_LO		(*(volatile unsigned char *)0x52000264)
+#define rEP4_DMA_TX_MD		(*(volatile unsigned char *)0x52000268)
+#define rEP4_DMA_TX_HI		(*(volatile unsigned char *)0x5200026C)
+#endif /*  __BIG_ENDIAN */
+
+
+/* WATCH DOG TIMER */
+#define rWTCON			(*(volatile unsigned *)0x53000000)
+#define rWTDAT			(*(volatile unsigned *)0x53000004)
+#define rWTCNT			(*(volatile unsigned *)0x53000008)
+
+
+/* IIC */
+#define rIICCON			(*(volatile unsigned *)0x54000000)
+#define rIICSTAT		(*(volatile unsigned *)0x54000004)
+#define rIICADD			(*(volatile unsigned *)0x54000008)
+#define rIICDS			(*(volatile unsigned *)0x5400000C)
+
+
+/* IIS */
+#define rIISCON			(*(volatile unsigned *)0x55000000)
+#define rIISMOD			(*(volatile unsigned *)0x55000004)
+#define rIISPSR			(*(volatile unsigned *)0x55000008)
+#define rIISFCON		(*(volatile unsigned *)0x5500000C)
+
+#ifdef __BIG_ENDIAN
+#define IISFIF			((volatile unsigned short *)0x55000012)
+#else /*  little endian */
+#define IISFIF			((volatile unsigned short *)0x55000010)
+#endif
+
+
+/* I/O PORT */
+#define rGPACON			(*(volatile unsigned *)0x56000000)
+#define rGPADAT			(*(volatile unsigned *)0x56000004)
+
+#define rGPBCON			(*(volatile unsigned *)0x56000010)
+#define rGPBDAT			(*(volatile unsigned *)0x56000014)
+#define rGPBUP			(*(volatile unsigned *)0x56000018)
+
+#define rGPCCON			(*(volatile unsigned *)0x56000020)
+#define rGPCDAT			(*(volatile unsigned *)0x56000024)
+#define rGPCUP			(*(volatile unsigned *)0x56000028)
+
+#define rGPDCON			(*(volatile unsigned *)0x56000030)
+#define rGPDDAT			(*(volatile unsigned *)0x56000034)
+#define rGPDUP			(*(volatile unsigned *)0x56000038)
+
+#define rGPECON			(*(volatile unsigned *)0x56000040)
+#define rGPEDAT			(*(volatile unsigned *)0x56000044)
+#define rGPEUP			(*(volatile unsigned *)0x56000048)
+
+#define rGPFCON			(*(volatile unsigned *)0x56000050)
+#define rGPFDAT			(*(volatile unsigned *)0x56000054)
+#define rGPFUP			(*(volatile unsigned *)0x56000058)
+
+#define rGPGCON			(*(volatile unsigned *)0x56000060)
+#define rGPGDAT			(*(volatile unsigned *)0x56000064)
+#define rGPGUP			(*(volatile unsigned *)0x56000068)
+
+#define rGPHCON			(*(volatile unsigned *)0x56000070)
+#define rGPHDAT			(*(volatile unsigned *)0x56000074)
+#define rGPHUP			(*(volatile unsigned *)0x56000078)
+
+#define rMISCCR			(*(volatile unsigned *)0x56000080)
+#define rDCLKCON		(*(volatile unsigned *)0x56000084)
+#define rEXTINT0		(*(volatile unsigned *)0x56000088)
+#define rEXTINT1		(*(volatile unsigned *)0x5600008C)
+#define rEXTINT2		(*(volatile unsigned *)0x56000090)
+#define rEINTFLT0		(*(volatile unsigned *)0x56000094)
+#define rEINTFLT1		(*(volatile unsigned *)0x56000098)
+#define rEINTFLT2		(*(volatile unsigned *)0x5600009C)
+#define rEINTFLT3		(*(volatile unsigned *)0x560000A0)
+#define rEINTMASK		(*(volatile unsigned *)0x560000A4)
+#define rEINTPEND		(*(volatile unsigned *)0x560000A8)
+#define rGSTATUS0		(*(volatile unsigned *)0x560000AC)
+#define rGSTATUS1		(*(volatile unsigned *)0x560000B0)
+
+
+/* RTC */
+#ifdef __BIG_ENDIAN
+#define rRTCCON			(*(volatile unsigned char *)0x57000043)
+#define rTICNT			(*(volatile unsigned char *)0x57000047)
+#define rRTCALM			(*(volatile unsigned char *)0x57000053)
+#define rALMSEC			(*(volatile unsigned char *)0x57000057)
+#define rALMMIN			(*(volatile unsigned char *)0x5700005B)
+#define rALMHOUR		(*(volatile unsigned char *)0x5700005F)
+#define rALMDATE		(*(volatile unsigned char *)0x57000063)
+#define rALMMON			(*(volatile unsigned char *)0x57000067)
+#define rALMYEAR		(*(volatile unsigned char *)0x5700006B)
+#define rRTCRST			(*(volatile unsigned char *)0x5700006F)
+#define rBCDSEC			(*(volatile unsigned char *)0x57000073)
+#define rBCDMIN			(*(volatile unsigned char *)0x57000077)
+#define rBCDHOUR		(*(volatile unsigned char *)0x5700007B)
+#define rBCDDATE		(*(volatile unsigned char *)0x5700007F)
+#define rBCDDAY			(*(volatile unsigned char *)0x57000083)
+#define rBCDMON			(*(volatile unsigned char *)0x57000087)
+#define rBCDYEAR		(*(volatile unsigned char *)0x5700008B)
+#else /*  little endian */
+#define rRTCCON			(*(volatile unsigned char *)0x57000040)
+#define rTICNT			(*(volatile unsigned char *)0x57000044)
+#define rRTCALM			(*(volatile unsigned char *)0x57000050)
+#define rALMSEC			(*(volatile unsigned char *)0x57000054)
+#define rALMMIN			(*(volatile unsigned char *)0x57000058)
+#define rALMHOUR		(*(volatile unsigned char *)0x5700005C)
+#define rALMDATE		(*(volatile unsigned char *)0x57000060)
+#define rALMMON			(*(volatile unsigned char *)0x57000064)
+#define rALMYEAR		(*(volatile unsigned char *)0x57000068)
+#define rRTCRST			(*(volatile unsigned char *)0x5700006C)
+#define rBCDSEC			(*(volatile unsigned char *)0x57000070)
+#define rBCDMIN			(*(volatile unsigned char *)0x57000074)
+#define rBCDHOUR		(*(volatile unsigned char *)0x57000078)
+#define rBCDDATE		(*(volatile unsigned char *)0x5700007C)
+#define rBCDDAY			(*(volatile unsigned char *)0x57000080)
+#define rBCDMON			(*(volatile unsigned char *)0x57000084)
+#define rBCDYEAR		(*(volatile unsigned char *)0x57000088)
+#endif
+
+
+/* ADC */
+#define rADCCON			(*(volatile unsigned *)0x58000000)
+#define rADCTSC			(*(volatile unsigned *)0x58000004)
+#define rADCDLY			(*(volatile unsigned *)0x58000008)
+#define rADCDAT0		(*(volatile unsigned *)0x5800000C)
+#define rADCDAT1		(*(volatile unsigned *)0x58000010)
+
+
+/* SPI */
+#define rSPCON0			(*(volatile unsigned *)0x59000000)
+#define rSPSTA0			(*(volatile unsigned *)0x59000004)
+#define rSPPIN0			(*(volatile unsigned *)0x59000008)
+#define rSPPRE0			(*(volatile unsigned *)0x5900000C)
+#define rSPTDAT0		(*(volatile unsigned *)0x59000010)
+#define rSPRDAT0		(*(volatile unsigned *)0x59000014)
+#define rSPCON1			(*(volatile unsigned *)0x59000020)
+#define rSPSTA1			(*(volatile unsigned *)0x59000024)
+#define rSPPIN1			(*(volatile unsigned *)0x59000028)
+#define rSPPRE1			(*(volatile unsigned *)0x5900002C)
+#define rSPTDAT1		(*(volatile unsigned *)0x59000030)
+#define rSPRDAT1		(*(volatile unsigned *)0x59000034)
+
+
+/* SD INTERFACE */
+#define rSDICON			(*(volatile unsigned *)0x5A000000)
+#define rSDIPRE			(*(volatile unsigned *)0x5A000004)
+#define rSDICmdArg		(*(volatile unsigned *)0x5A000008)
+#define rSDICmdCon		(*(volatile unsigned *)0x5A00000C)
+#define rSDICmdSta		(*(volatile unsigned *)0x5A000010)
+#define rSDIRSP0		(*(volatile unsigned *)0x5A000014)
+#define rSDIRSP1		(*(volatile unsigned *)0x5A000018)
+#define rSDIRSP2		(*(volatile unsigned *)0x5A00001C)
+#define rSDIRSP3		(*(volatile unsigned *)0x5A000020)
+#define rSDIDTimer		(*(volatile unsigned *)0x5A000024)
+#define rSDIBSize		(*(volatile unsigned *)0x5A000028)
+#define rSDIDatCon		(*(volatile unsigned *)0x5A00002C)
+#define rSDIDatCnt		(*(volatile unsigned *)0x5A000030)
+#define rSDIDatSta		(*(volatile unsigned *)0x5A000034)
+#define rSDIFSTA		(*(volatile unsigned *)0x5A000038)
+#ifdef __BIG_ENDIAN
+#define rSDIDAT			(*(volatile unsigned char *)0x5A00003F)
+#else
+#define rSDIDAT			(*(volatile unsigned char *)0x5A00003C)
+#endif
+#define rSDIIntMsk		(*(volatile unsigned *)0x5A000040)
+
+#endif
+
+#endif /*__S3C24X0_H__*/
diff --git a/include/s_record.h b/include/s_record.h
new file mode 100755
index 0000000..07806d5
--- /dev/null
+++ b/include/s_record.h
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*--------------------------------------------------------------------------
+ *
+ * Motorola S-Record Format:
+ *
+ * Motorola S-Records are an industry-standard format for
+ * transmitting binary files to target systems and PROM
+ * programmers. LSI Logic have extended this standard to include
+ * an S4-record containing an address and a symbol.
+ *
+ * The extended S-record standard is as follows:
+ *
+ * S<type><length><address><data....><checksum>
+ * S4<length><address><name>,<checksum>
+ *
+ * Where:
+ *
+ * type
+ *     is the record type. Where:
+ *
+ *     0  starting record (optional)
+ *     1  data record with 16-bit address
+ *     2  data record with 24-bit address
+ *     3  data record with 32-bit address
+ *     4  symbol record (LSI extension)
+ *     5  number of data records in preceeding block
+ *     6  unused
+ *     7  ending record for S3 records
+ *     8  ending record for S2 records
+ *     9  ending record for S1 records
+ *
+ * length
+ *     is two hex characters. This defines the length of the
+ *     record in bytes (not characters). It includes the address
+ *     field, the data field, and the checksum field.
+ *
+ * address
+ *     is 4, 6, or 8 characters. Corresponding to a 16-, 24-, or
+ *     32-bit address. The address field for S4 records is
+ *     always 32 bits.
+ *
+ * data
+ *
+ *     Are the data bytes. Each pair of hex characters represent
+ *     one byte in memory.
+ *
+ * name
+ *     Is the symbol name. The symbol is terminated by a ','.
+ *
+ * checksum
+ *     Is the one's complement of the 8-bit checksum.
+ *
+ * Example
+ *
+ * S0030000FC
+ * .
+ * .
+ * S325000004403C0880018D08DD900000000011000026000000003C0880012508DC50C50000B401
+ * S32500000460C50100B8C50200BCC50300C0C50400C4C50500C8C50600CCC50700D0C50800D4FA
+ * S32500000480C50900D8C50A00DCC50B00E0C50C00E4C50D00E8C50E00ECC50F00F0C51000F49A
+ * S325000004A0C51100F8C51200FCC5130100C5140104C5150108C516010CC5170110C518011434
+ * .
+ * .
+ * S70500000000FA
+ *
+ * The S0 record starts the file. The S3 records contain the
+ * data. The S7 record contains the entry address and terminates
+ * the download.
+ *
+ *--------------------------------------------------------------------------
+ */
+
+#define SREC_START	0	/* Start Record (module name)		    */
+#define SREC_DATA2	1	/* Data  Record with 2 byte address	    */
+#define SREC_DATA3	2	/* Data  Record with 3 byte address	    */
+#define SREC_DATA4	3	/* Data  Record with 4 byte address	    */
+#define SREC_COUNT	5	/* Count Record (previously transmitted)    */
+#define SREC_END4 	7	/* End   Record with 4 byte start address   */
+#define SREC_END3 	8	/* End   Record with 3 byte start address   */
+#define SREC_END2 	9	/* End   Record with 2 byte start address   */
+#define SREC_EMPTY	10	/* Empty Record without any data	    */
+
+#define SREC_REC_OK  SREC_EMPTY /* last code without error condition	    */
+
+#define SREC_E_BADTYPE	-1	/* no valid S-Record		            */
+#define SREC_E_NOSREC	-2	/* line format differs from s-record	    */
+#define SREC_E_BADCHKS	-3	/* checksum error in an s-record line	    */
+
+#define SREC_MAXRECLEN	(512 + 4)   /* max ASCII record length		    */
+#define SREC_MAXBINLEN	255	    /* resulting binary length		    */
+
+int srec_decode (char *input, int *count, ulong *addr, char *data);
diff --git a/include/sa1100.h b/include/sa1100.h
new file mode 100755
index 0000000..e69de29
--- /dev/null
+++ b/include/sa1100.h
diff --git a/include/scsi.h b/include/scsi.h
new file mode 100755
index 0000000..2be4d40
--- /dev/null
+++ b/include/scsi.h
@@ -0,0 +1,208 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+ #ifndef _SCSI_H
+ #define _SCSI_H
+
+typedef struct SCSI_cmd_block{
+	unsigned char		cmd[16];					/* command				   */
+	unsigned char		sense_buf[64];		/* for request sense */
+	unsigned char		status;						/* SCSI Status			 */
+	unsigned char		target;						/* Target ID				 */
+	unsigned char		lun;							/* Target LUN        */
+	unsigned char		cmdlen;						/* command len				*/
+	unsigned long		datalen;					/* Total data length	*/
+	unsigned char	*	pdata; 						/* pointer to data		*/
+	unsigned char		msgout[12];				/* Messge out buffer (NOT USED) */
+	unsigned char		msgin[12];				/* Message in buffer	*/
+	unsigned char		sensecmdlen;			/* Sense command len	*/
+	unsigned long		sensedatalen;			/* Sense data len			*/
+	unsigned char		sensecmd[6];			/* Sense command			*/
+	unsigned long		contr_stat;				/* Controller Status	*/
+	unsigned long		trans_bytes;			/* tranfered bytes		*/
+
+	unsigned int		priv;
+}ccb;
+
+/*-----------------------------------------------------------
+**
+**	SCSI  constants.
+**
+**-----------------------------------------------------------
+*/
+
+/*
+**	Messages
+*/
+
+#define	M_COMPLETE	(0x00)
+#define	M_EXTENDED	(0x01)
+#define	M_SAVE_DP	(0x02)
+#define	M_RESTORE_DP	(0x03)
+#define	M_DISCONNECT	(0x04)
+#define	M_ID_ERROR	(0x05)
+#define	M_ABORT		(0x06)
+#define	M_REJECT	(0x07)
+#define	M_NOOP		(0x08)
+#define	M_PARITY	(0x09)
+#define	M_LCOMPLETE	(0x0a)
+#define	M_FCOMPLETE	(0x0b)
+#define	M_RESET		(0x0c)
+#define	M_ABORT_TAG	(0x0d)
+#define	M_CLEAR_QUEUE	(0x0e)
+#define	M_INIT_REC	(0x0f)
+#define	M_REL_REC	(0x10)
+#define	M_TERMINATE	(0x11)
+#define	M_SIMPLE_TAG	(0x20)
+#define	M_HEAD_TAG	(0x21)
+#define	M_ORDERED_TAG	(0x22)
+#define	M_IGN_RESIDUE	(0x23)
+#define	M_IDENTIFY   	(0x80)
+
+#define	M_X_MODIFY_DP	(0x00)
+#define	M_X_SYNC_REQ	(0x01)
+#define	M_X_WIDE_REQ	(0x03)
+#define	M_X_PPR_REQ	(0x04)
+
+
+/*
+**	Status
+*/
+
+#define	S_GOOD		(0x00)
+#define	S_CHECK_COND	(0x02)
+#define	S_COND_MET	(0x04)
+#define	S_BUSY		(0x08)
+#define	S_INT		(0x10)
+#define	S_INT_COND_MET	(0x14)
+#define	S_CONFLICT	(0x18)
+#define	S_TERMINATED	(0x20)
+#define	S_QUEUE_FULL	(0x28)
+#define	S_ILLEGAL	(0xff)
+#define	S_SENSE		(0x80)
+
+/*
+ * Sense_keys
+ */
+
+#define SENSE_NO_SENSE				0x0
+#define SENSE_RECOVERED_ERROR	0x1
+#define SENSE_NOT_READY				0x2
+#define SENSE_MEDIUM_ERROR		0x3
+#define SENSE_HARDWARE_ERROR	0x4
+#define SENSE_ILLEGAL_REQUEST	0x5
+#define SENSE_UNIT_ATTENTION	0x6
+#define SENSE_DATA_PROTECT		0x7
+#define SENSE_BLANK_CHECK			0x8
+#define SENSE_VENDOR_SPECIFIC	0x9
+#define SENSE_COPY_ABORTED		0xA
+#define SENSE_ABORTED_COMMAND	0xB
+#define SENSE_VOLUME_OVERFLOW	0xD
+#define SENSE_MISCOMPARE			0xE
+
+
+#define SCSI_CHANGE_DEF	0x40		/* Change Definition (Optional) */
+#define SCSI_COMPARE		0x39		/* Compare (O) */
+#define SCSI_COPY			0x18		/* Copy (O) */
+#define SCSI_COP_VERIFY	0x3A		/* Copy and Verify (O) */
+#define SCSI_INQUIRY		0x12		/* Inquiry (MANDATORY) */
+#define SCSI_LOG_SELECT	0x4C		/* Log Select (O) */
+#define SCSI_LOG_SENSE	0x4D		/* Log Sense (O) */
+#define SCSI_MODE_SEL6	0x15		/* Mode Select 6-byte (Device Specific) */
+#define SCSI_MODE_SEL10	0x55		/* Mode Select 10-byte (Device Specific) */
+#define SCSI_MODE_SEN6	0x1A		/* Mode Sense 6-byte (Device Specific) */
+#define SCSI_MODE_SEN10	0x5A		/* Mode Sense 10-byte (Device Specific) */
+#define SCSI_READ_BUFF	0x3C		/* Read Buffer (O) */
+#define SCSI_REQ_SENSE	0x03		/* Request Sense (MANDATORY) */
+#define SCSI_SEND_DIAG	0x1D		/* Send Diagnostic (O) */
+#define SCSI_TST_U_RDY	0x00		/* Test Unit Ready (MANDATORY) */
+#define SCSI_WRITE_BUFF	0x3B		/* Write Buffer (O) */
+/***************************************************************************
+ *			  %%% Commands Unique to Direct Access Devices %%%
+ ***************************************************************************/
+#define SCSI_COMPARE		0x39		/* Compare (O) */
+#define SCSI_FORMAT		0x04		/* Format Unit (MANDATORY) */
+#define SCSI_LCK_UN_CAC	0x36		/* Lock Unlock Cache (O) */
+#define SCSI_PREFETCH	0x34		/* Prefetch (O) */
+#define SCSI_MED_REMOVL	0x1E		/* Prevent/Allow medium Removal (O) */
+#define SCSI_READ6		0x08		/* Read 6-byte (MANDATORY) */
+#define SCSI_READ10		0x28		/* Read 10-byte (MANDATORY) */
+#define SCSI_RD_CAPAC	0x25		/* Read Capacity (MANDATORY) */
+#define SCSI_RD_DEFECT	0x37		/* Read Defect Data (O) */
+#define SCSI_READ_LONG	0x3E		/* Read Long (O) */
+#define SCSI_REASS_BLK	0x07		/* Reassign Blocks (O) */
+#define SCSI_RCV_DIAG	0x1C		/* Receive Diagnostic Results (O) */
+#define SCSI_RELEASE	0x17		/* Release Unit (MANDATORY) */
+#define SCSI_REZERO		0x01		/* Rezero Unit (O) */
+#define SCSI_SRCH_DAT_E	0x31		/* Search Data Equal (O) */
+#define SCSI_SRCH_DAT_H	0x30		/* Search Data High (O) */
+#define SCSI_SRCH_DAT_L	0x32		/* Search Data Low (O) */
+#define SCSI_SEEK6		0x0B		/* Seek 6-Byte (O) */
+#define SCSI_SEEK10		0x2B		/* Seek 10-Byte (O) */
+#define SCSI_SEND_DIAG	0x1D		/* Send Diagnostics (MANDATORY) */
+#define SCSI_SET_LIMIT	0x33		/* Set Limits (O) */
+#define SCSI_START_STP	0x1B		/* Start/Stop Unit (O) */
+#define SCSI_SYNC_CACHE	0x35		/* Synchronize Cache (O) */
+#define SCSI_VERIFY		0x2F		/* Verify (O) */
+#define SCSI_WRITE6		0x0A		/* Write 6-Byte (MANDATORY) */
+#define SCSI_WRITE10	0x2A		/* Write 10-Byte (MANDATORY) */
+#define SCSI_WRT_VERIFY	0x2E		/* Write and Verify (O) */
+#define SCSI_WRITE_LONG	0x3F		/* Write Long (O) */
+#define SCSI_WRITE_SAME	0x41		/* Write Same (O) */
+
+
+/****************************************************************************
+ * decleration of functions which have to reside in the LowLevel Part Driver
+ */
+
+void scsi_print_error(ccb *pccb);
+int scsi_exec(ccb *pccb);
+void scsi_bus_reset(void);
+void scsi_low_level_init(int busdevfunc);
+
+
+/***************************************************************************
+ * functions residing inside cmd_scsi.c
+ */
+void scsi_init(void);
+
+
+#define SCSI_IDENTIFY					0xC0  /* not used */
+
+/* Hardware errors  */
+#define SCSI_SEL_TIME_OUT			 0x00000101	 /* Selection time out */
+#define SCSI_HNS_TIME_OUT			 0x00000102  /* Handshake */
+#define SCSI_MA_TIME_OUT	 		 0x00000103  /* Phase error */
+#define SCSI_UNEXP_DIS				 0x00000104  /* unexpected disconnect */
+
+#define SCSI_INT_STATE				 0x00010000  /* unknown Interrupt number is stored in 16 LSB */
+
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#endif /* _SCSI_H */
diff --git a/include/search.h b/include/search.h
new file mode 100755
index 0000000..ef53edb
--- /dev/null
+++ b/include/search.h
@@ -0,0 +1,104 @@
+/*
+ * Declarations for System V style searching functions.
+ * Copyright (C) 1995-1999, 2000 Free Software Foundation, Inc.
+ * This file is part of the GNU C Library.
+ *
+ * The GNU C Library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * The GNU C Library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with the GNU C Library; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307 USA.
+ */
+
+/*
+ * Based on code from uClibc-0.9.30.3
+ * Extensions for use within U-Boot
+ * Copyright (C) 2010 Wolfgang Denk <wd@denx.de>
+ */
+
+#ifndef _SEARCH_H
+#define	_SEARCH_H 1
+
+#include <stddef.h>
+
+#define __set_errno(val) do { errno = val; } while (0)
+
+/* Action which shall be performed in the call the hsearch.  */
+typedef enum {
+	FIND,
+	ENTER
+} ACTION;
+
+typedef struct entry {
+	const char *key;
+	char *data;
+} ENTRY;
+
+/* Opaque type for internal use.  */
+struct _ENTRY;
+
+/*
+ * Family of hash table handling functions.  The functions also
+ * have reentrant counterparts ending with _r.  The non-reentrant
+ * functions all work on a signle internal hashing table.
+ */
+
+/* Data type for reentrant functions.  */
+struct hsearch_data {
+	struct _ENTRY *table;
+	unsigned int size;
+	unsigned int filled;
+};
+
+/* Create a new hashing table which will at most contain NEL elements.  */
+extern int hcreate_r(size_t __nel, struct hsearch_data *__htab);
+
+/* Destroy current internal hashing table.  */
+extern void hdestroy_r(struct hsearch_data *__htab);
+
+/*
+ * Search for entry matching ITEM.key in internal hash table.  If
+ * ACTION is `FIND' return found entry or signal error by returning
+ * NULL.  If ACTION is `ENTER' replace existing data (if any) with
+ * ITEM.data.
+ * */
+extern int hsearch_r(ENTRY __item, ACTION __action, ENTRY ** __retval,
+		     struct hsearch_data *__htab);
+
+/*
+ * Search for an entry matching `MATCH'.  Otherwise, Same semantics
+ * as hsearch_r().
+ */
+extern int hmatch_r(const char *__match, int __last_idx, ENTRY ** __retval,
+		    struct hsearch_data *__htab);
+/*
+ * Search for an entry whose key or data contains `MATCH'.  Otherwise,
+ * Same semantics as hsearch_r().
+ */
+extern int hstrstr_r(const char *__match, int __last_idx, ENTRY ** __retval,
+		    struct hsearch_data *__htab);
+
+/* Search and delete entry matching ITEM.key in internal hash table. */
+extern int hdelete_r(const char *__key, struct hsearch_data *__htab);
+
+extern ssize_t hexport_r(struct hsearch_data *__htab,
+		     const char __sep, char **__resp, size_t __size,
+		     int argc, char * const argv[]);
+
+extern int himport_r(struct hsearch_data *__htab,
+		     const char *__env, size_t __size, const char __sep,
+		     int __flag);
+
+/* Flags for himport_r() */
+#define	H_NOCLEAR	1	/* do not clear hash table before importing */
+
+#endif /* search.h */
diff --git a/include/sed13806.h b/include/sed13806.h
new file mode 100755
index 0000000..216e788
--- /dev/null
+++ b/include/sed13806.h
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2002
+ * Stäubli Faverges - <www.staubli.com>
+ * Pierre AUBERT  p.aubert@staubli.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/* Video support for Epson SED13806 chipset                                  */
+
+
+#ifndef _SED13806_H_
+#define _SED13806_H_
+
+
+/* General definitions                                                       */
+#define FRAME_BUFFER_OFFSET        0x200000     /* Frame buffer offset */
+#define TOTAL_SPACE_SIZE           0x400000
+
+#define DEFAULT_VIDEO_MEMORY_SIZE  0x140000     /* Video Memory Size */
+
+#define HWCURSORSIZE 		   1024     /* Size of memory reserved
+						   for HW cursor*/
+
+/* Offset of chipset registers                                               */
+#define	BLT_CTRL0	(0x0100)
+#define	BLT_CTRL1	(0x0101)
+#define BLT_ROP		(0x0102)
+#define	BLT_OP		(0x0103)
+#define BLT_SRC_ADDR0	(0x0104)
+#define	BLT_SRC_ADDR1	(0x0105)
+#define	BLT_SRC_ADDR2	(0x0106)
+#define	BLT_DST_ADDR0	(0x0108)
+#define BLT_DST_ADDR1	(0x0109)
+#define	BLT_DST_ADDR2	(0x010A)
+#define BLT_MEM_OFF0	(0x010C)
+#define BLT_MEM_OFF1	(0x010D)
+#define BLT_WIDTH0	(0x0110)
+#define BLT_WIDTH1	(0x0111)
+#define BLT_HEIGHT0	(0x0112)
+#define BLT_HEIGHT1	(0x0113)
+#define	BLT_BGCOLOR0	(0x0114)
+#define	BLT_BGCOLOR1	(0x0115)
+#define	BLT_FGCOLOR0	(0x0118)
+#define BLT_FGCOLOR1	(0x0119)
+
+#define BLT_REG         (0x100000)
+
+/* Lookup table registers                                                    */
+#define REG_LUT_ADDR 0x1e2
+#define REG_LUT_DATA 0x1e4
+
+/* Cursor/Ink registers                                                      */
+#define LCD_CURSOR_CNTL         (0x0070)
+#define LCD_CURSOR_START        (0x0071)
+#define LCD_CURSOR_XL           (0x0072)
+#define LCD_CURSOR_XM           (0x0073)
+#define LCD_CURSOR_YL           (0x0074)
+#define LCD_CURSOR_YM           (0x0075)
+#define LCD_CURSOR_COL0_B       (0x0076)
+#define LCD_CURSOR_COL0_G       (0x0077)
+#define LCD_CURSOR_COL0_R       (0x0078)
+#define LCD_CURSOR_COL1_B       (0x007A)
+#define LCD_CURSOR_COL1_G       (0x007B)
+#define LCD_CURSOR_COL1_R       (0x007C)
+#define LCD_CURSOR_FIFO         (0x007E)
+
+typedef struct
+{
+    unsigned short      Index;
+    unsigned char       Value;
+} S1D_REGS;
+
+
+/* Board specific functions                                                  */
+unsigned int board_video_init (void);
+void board_validate_screen (unsigned int base);
+const S1D_REGS *board_get_regs (void);
+int board_get_width (void);
+int board_get_height (void);
+
+#endif /* _SED13806_H_ */
diff --git a/include/sed156x.h b/include/sed156x.h
new file mode 100755
index 0000000..e980975
--- /dev/null
+++ b/include/sed156x.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2004
+ *
+ * Pantelis Antoniou <panto@intracom.gr>
+ * Intracom S.A.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Video support for Epson SED156x chipset(s) */
+
+#ifndef SED156X_H
+#define SED156X_H
+
+void sed156x_init(void);
+void sed156x_clear(void);
+void sed156x_output_at(int x, int y, const char *str, int size);
+void sed156x_reverse_at(int x, int y, int size);
+void sed156x_sync(void);
+void sed156x_scroll(int dx, int dy);
+
+/* export display */
+extern const int sed156x_text_width;
+extern const int sed156x_text_height;
+
+#endif	/* SED156X_H */
diff --git a/include/serial.h b/include/serial.h
new file mode 100755
index 0000000..c8abb72
--- /dev/null
+++ b/include/serial.h
@@ -0,0 +1,37 @@
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+#define NAMESIZE 16
+#define CTLRSIZE 8
+
+struct serial_device {
+	char name[NAMESIZE];
+	char ctlr[CTLRSIZE];
+
+	int  (*init) (void);
+	void (*setbrg) (void);
+	int (*getc) (void);
+	int (*tstc) (void);
+	void (*putc) (const char c);
+	void (*puts) (const char *s);
+
+	struct serial_device *next;
+};
+
+extern struct serial_device serial_smc_device;
+extern struct serial_device serial_scc_device;
+extern struct serial_device * default_serial_console (void);
+
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
+   || defined(CONFIG_405EP)
+extern struct serial_device serial0_device;
+extern struct serial_device serial1_device;
+#endif
+
+
+extern void serial_initialize(void);
+extern void serial_devices_init(void);
+extern int serial_assign(char * name);
+extern void serial_reinit_all(void);
+
+#endif
diff --git a/include/sm501.h b/include/sm501.h
new file mode 100755
index 0000000..3e71dbb
--- /dev/null
+++ b/include/sm501.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2002
+ * Stäubli Faverges - <www.staubli.com>
+ * Pierre AUBERT  p.aubert@staubli.com
+ *
+ * (C) Copyright 2005
+ * Martin Krause TQ-Systems GmbH martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Basic video support for SMI SM501 "Voyager" graphic controller
+ */
+
+#ifndef _SM501_H_
+#define _SM501_H_
+
+#define PCI_VENDOR_SM		0x126f
+#define PCI_DEVICE_SM501	0x0501
+
+typedef struct {
+	unsigned int Index;
+	unsigned int Value;
+} SMI_REGS;
+
+/* Board specific functions                                                  */
+unsigned int board_video_init (void);
+void board_validate_screen (unsigned int base);
+const SMI_REGS *board_get_regs (void);
+int board_get_width (void);
+int board_get_height (void);
+unsigned int board_video_get_fb (void);
+
+#endif /* _SM501_H_ */
diff --git a/include/smiLynxEM.h b/include/smiLynxEM.h
new file mode 100755
index 0000000..017964b
--- /dev/null
+++ b/include/smiLynxEM.h
@@ -0,0 +1,179 @@
+/*
+ * (C) Copyright 1997-2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * smiLynxEM.h
+ * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator
+ *
+ *
+ *  modification history
+ *  --------------------
+ *  04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>.
+ */
+
+#ifndef _SMI_LYNX_EM_H_
+#define _SMI_LYNX_EM_H_
+
+/*
+ * SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external
+ */
+#define VIDEO_MEM_SIZE  0x400000
+
+/*
+ * Supported video modes for SMI Lynx E/EM/EM+
+ */
+#define VIDEO_MODES             7
+#define DUAL_800_600            0   /* SMI710:VGA1:75Hz     (pitch=1600) */
+				    /*        VGA2:60/120Hz (pitch=1600) */
+				    /* SMI810:VGA1:75Hz     (pitch=1600) */
+				    /*        VGA2:75Hz     (pitch=1600) */
+#define DUAL_1024_768           1   /* VGA1:75Hz VGA2:73Hz (pitch=2048)  */
+#define SINGLE_800_600          2   /* VGA1:75Hz (pitch=800)             */
+#define SINGLE_1024_768         3   /* VGA1:75Hz (pitch=1024)            */
+#define SINGLE_1280_1024        4   /* VGA1:75Hz (pitch=1280)            */
+#define TV_MODE_CCIR            5   /* VGA1:50Hz (h=720;v=576;pitch=720) */
+#define TV_MODE_EIA             6   /* VGA1:60Hz (h=720;v=484;pitch=720) */
+
+
+/*
+ * ISA mapped regs
+ */
+#define SMI_INDX_C4             (pGD->isaBase + 0x03c4)    /* index reg */
+#define SMI_DATA_C5             (pGD->isaBase + 0x03c5)    /* data reg */
+#define SMI_INDX_D4             (pGD->isaBase + 0x03d4)    /* index reg */
+#define SMI_DATA_D5             (pGD->isaBase + 0x03d5)    /* data reg */
+#define SMI_INDX_CE             (pGD->isaBase + 0x03ce)    /* index reg */
+#define SMI_DATA_CF             (pGD->isaBase + 0x03cf)    /* data reg */
+#define SMI_LOCK_REG            (pGD->isaBase + 0x03c3)    /* unlock/lock ext crt reg */
+#define SMI_MISC_REG            (pGD->isaBase + 0x03c2)    /* misc reg */
+#define SMI_LUT_MASK            (pGD->isaBase + 0x03c6)    /* lut mask reg */
+#define SMI_LUT_START           (pGD->isaBase + 0x03c8)    /* lut start index */
+#define SMI_LUT_RGB             (pGD->isaBase + 0x03c9)    /* lut colors auto incr.*/
+
+
+/*
+ * Video processor control
+ */
+typedef struct {
+    unsigned int   control;
+    unsigned int   colorKey;
+    unsigned int   colorKeyMask;
+    unsigned int   start;
+    unsigned short offset;
+    unsigned short width;
+    unsigned int   fifoPrio;
+    unsigned int   fifoERL;
+    unsigned int   YUVtoRGB;
+} SmiVideoProc;
+
+/*
+ * Video window control
+ */
+typedef struct {
+    unsigned short top;
+    unsigned short left;
+    unsigned short bottom;
+    unsigned short right;
+    unsigned int   srcStart;
+    unsigned short width;
+    unsigned short offset;
+    unsigned char  hStretch;
+    unsigned char  vStretch;
+} SmiVideoWin;
+
+/*
+ * Capture port control
+ */
+typedef struct {
+    unsigned int   control;
+    unsigned short topClip;
+    unsigned short leftClip;
+    unsigned short srcHeight;
+    unsigned short srcWidth;
+    unsigned int   srcBufStart1;
+    unsigned int   srcBufStart2;
+    unsigned short srcOffset;
+    unsigned short fifoControl;
+} SmiCapturePort;
+
+
+/******************************************************************************/
+/* Export Graphic Driver Control                                              */
+/******************************************************************************/
+
+typedef struct {
+    unsigned int isaBase;
+    unsigned int pciBase;
+    unsigned int dprBase;
+    unsigned int vprBase;
+    unsigned int cprBase;
+    unsigned int frameAdrs;
+    unsigned int memSize;
+    unsigned int mode;
+    unsigned int gdfIndex;
+    unsigned int gdfBytesPP;
+    unsigned int fg;
+    unsigned int bg;
+    unsigned int plnSizeX;
+    unsigned int plnSizeY;
+    unsigned int winSizeX;
+    unsigned int winSizeY;
+    char modeIdent[80];
+} GraphicDevice;
+
+extern GraphicDevice smi;
+
+
+/******************************************************************************/
+/* Export Graphic Functions                                                   */
+/******************************************************************************/
+
+void *video_hw_init (void);       /* returns GraphicDevice struct or NULL */
+
+void video_hw_bitblt (
+    unsigned int bpp,             /* bytes per pixel */
+    unsigned int src_x,           /* source pos x */
+    unsigned int src_y,           /* source pos y */
+    unsigned int dst_x,           /* dest pos x */
+    unsigned int dst_y,           /* dest pos y */
+    unsigned int dim_x,           /* frame width */
+    unsigned int dim_y            /* frame height */
+    );
+
+void video_hw_rectfill (
+    unsigned int bpp,             /* bytes per pixel */
+    unsigned int dst_x,           /* dest pos x */
+    unsigned int dst_y,           /* dest pos y */
+    unsigned int dim_x,           /* frame width */
+    unsigned int dim_y,           /* frame height */
+    unsigned int color            /* fill color */
+     );
+
+void video_set_lut (
+    unsigned int index,           /* color number */
+    unsigned char r,              /* red */
+    unsigned char g,              /* green */
+    unsigned char b               /* blue */
+    );
+
+#endif /*_SMI_LYNX_EM_H_ */
diff --git a/include/sparse.h b/include/sparse.h
new file mode 100755
index 0000000..56a81ac
--- /dev/null
+++ b/include/sparse.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2011
+ * Texas Instruments, <www.ti.com>
+ * Author: Vikram Pandita <vikram.pandita@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPARSE_H
+#define __SPARSE_H
+#include <asm-arm/types.h>
+
+#define __le32 u32
+#define __le16 u16
+
+/* This file is taken as such from Android repo */
+#include <sparse_format.h>
+
+u8
+do_unsparse(unsigned char init,
+				unsigned char *source,
+                u32 sector,
+                u32 section_size,
+                char *slot_no);
+#endif /* __SPARSE_H */
diff --git a/include/sparse_format.h b/include/sparse_format.h
new file mode 100755
index 0000000..ba13214
--- /dev/null
+++ b/include/sparse_format.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2010 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+typedef struct sparse_header {
+  __le32	magic;		/* 0xed26ff3a */
+  __le16	major_version;	/* (0x1) - reject images with higher major versions */
+  __le16	minor_version;	/* (0x0) - allow images with higer minor versions */
+  __le16	file_hdr_sz;	/* 28 bytes for first revision of the file format */
+  __le16	chunk_hdr_sz;	/* 12 bytes for first revision of the file format */
+  __le32	blk_sz;		/* block size in bytes, must be a multiple of 4 (4096) */
+  __le32	total_blks;	/* total blocks in the non-sparse output image */
+  __le32	total_chunks;	/* total chunks in the sparse input image */
+  __le32	image_checksum; /* CRC32 checksum of the original data, counting "don't care" */
+				/* as 0. Standard 802.3 polynomial, use a Public Domain */
+				/* table implementation */
+} sparse_header_t;
+
+#define SPARSE_HEADER_MAGIC	0xed26ff3a
+
+#define CHUNK_TYPE_RAW		0xCAC1
+#define CHUNK_TYPE_FILL		0xCAC2
+#define CHUNK_TYPE_DONT_CARE	0xCAC3
+
+typedef struct chunk_header {
+  __le16	chunk_type;	/* 0xCAC1 -> raw; 0xCAC2 -> fill; 0xCAC3 -> don't care */
+  __le16	reserved1;
+  __le32	chunk_sz;	/* in blocks in output image */
+  __le32	total_sz;	/* in bytes of chunk input file including chunk header and data */
+} chunk_header_t;
+
+/* Following a Raw or Fill chunk is data.  For a Raw chunk, it's the data in chunk_sz * blk_sz.
+ *  For a Fill chunk, it's 4 bytes of the fill data.
+ */
+
diff --git a/include/spartan2.h b/include/spartan2.h
new file mode 100755
index 0000000..d2e81e3
--- /dev/null
+++ b/include/spartan2.h
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _SPARTAN2_H_
+#define _SPARTAN2_H_
+
+#include <xilinx.h>
+
+extern int Spartan2_load( Xilinx_desc *desc, void *image, size_t size );
+extern int Spartan2_dump( Xilinx_desc *desc, void *buf, size_t bsize );
+extern int Spartan2_info( Xilinx_desc *desc );
+extern int Spartan2_reloc( Xilinx_desc *desc, ulong reloc_off );
+
+/* Slave Parallel Implementation function table */
+typedef struct {
+	Xilinx_pre_fn	pre;
+	Xilinx_pgm_fn	pgm;
+	Xilinx_init_fn	init;
+	Xilinx_err_fn	err;
+	Xilinx_done_fn	done;
+	Xilinx_clk_fn	clk;
+	Xilinx_cs_fn	cs;
+	Xilinx_wr_fn	wr;
+	Xilinx_rdata_fn	rdata;
+	Xilinx_wdata_fn	wdata;
+	Xilinx_busy_fn	busy;
+	Xilinx_abort_fn	abort;
+	Xilinx_post_fn	post;
+	int           	relocated;
+} Xilinx_Spartan2_Slave_Parallel_fns;
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	Xilinx_pre_fn	pre;
+	Xilinx_pgm_fn	pgm;
+	Xilinx_clk_fn	clk;
+	Xilinx_init_fn	init;
+	Xilinx_done_fn	done;
+	Xilinx_wr_fn	wr;
+	int           	relocated;
+} Xilinx_Spartan2_Slave_Serial_fns;
+
+/* Device Image Sizes
+ *********************************************************************/
+/* Spartan-II (2.5V) */
+#define XILINX_XC2S15_SIZE  	197728/8
+#define XILINX_XC2S30_SIZE  	336800/8
+#define XILINX_XC2S50_SIZE  	559232/8
+#define XILINX_XC2S100_SIZE 	781248/8
+#define XILINX_XC2S150_SIZE 	1040128/8
+
+/* Spartan-IIE (1.8V) */
+#define XILINX_XC2S50E_SIZE     630048/8
+#define XILINX_XC2S100E_SIZE    863840/8
+#define XILINX_XC2S150E_SIZE    1134496/8
+#define XILINX_XC2S200E_SIZE    1442016/8
+#define XILINX_XC2S300E_SIZE    1875648/8
+
+/* Descriptor Macros
+ *********************************************************************/
+/* Spartan-II devices */
+#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie }
+
+#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie }
+
+#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie }
+
+#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie }
+
+#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
+
+#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
+
+#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie }
+
+#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie }
+
+#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie }
+
+#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie }
+
+#endif /* _SPARTAN2_H_ */
diff --git a/include/spartan3.h b/include/spartan3.h
new file mode 100755
index 0000000..b14db03
--- /dev/null
+++ b/include/spartan3.h
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _SPARTAN3_H_
+#define _SPARTAN3_H_
+
+#include <xilinx.h>
+
+extern int Spartan3_load( Xilinx_desc *desc, void *image, size_t size );
+extern int Spartan3_dump( Xilinx_desc *desc, void *buf, size_t bsize );
+extern int Spartan3_info( Xilinx_desc *desc );
+extern int Spartan3_reloc( Xilinx_desc *desc, ulong reloc_off );
+
+/* Slave Parallel Implementation function table */
+typedef struct {
+	Xilinx_pre_fn	pre;
+	Xilinx_pgm_fn	pgm;
+	Xilinx_init_fn	init;
+	Xilinx_err_fn	err;
+	Xilinx_done_fn	done;
+	Xilinx_clk_fn	clk;
+	Xilinx_cs_fn	cs;
+	Xilinx_wr_fn	wr;
+	Xilinx_rdata_fn	rdata;
+	Xilinx_wdata_fn	wdata;
+	Xilinx_busy_fn	busy;
+	Xilinx_abort_fn	abort;
+	Xilinx_post_fn	post;
+	int           	relocated;
+} Xilinx_Spartan3_Slave_Parallel_fns;
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	Xilinx_pre_fn	pre;
+	Xilinx_pgm_fn	pgm;
+	Xilinx_clk_fn	clk;
+	Xilinx_init_fn	init;
+	Xilinx_done_fn	done;
+	Xilinx_wr_fn	wr;
+	int           	relocated;
+} Xilinx_Spartan3_Slave_Serial_fns;
+
+/* Device Image Sizes
+ *********************************************************************/
+/* Spartan-III (1.2V) */
+#define XILINX_XC3S50_SIZE  	439264/8
+#define XILINX_XC3S200_SIZE  	1047616/8
+#define XILINX_XC3S400_SIZE  	1699136/8
+#define XILINX_XC3S1000_SIZE 	3223488/8
+#define XILINX_XC3S1500_SIZE 	5214784/8
+#define XILINX_XC3S2000_SIZE 	7673024/8
+#define XILINX_XC3S4000_SIZE 	11316864/8
+#define XILINX_XC3S5000_SIZE 	13271936/8
+
+/* Descriptor Macros
+ *********************************************************************/
+/* Spartan-II devices */
+#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S2000E_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S4000E_SIZE, fn_table, cookie }
+
+#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Spartan3, iface, XILINX_XC3S5000E_SIZE, fn_table, cookie }
+
+#endif /* _SPARTAN3_H_ */
diff --git a/include/spd.h b/include/spd.h
new file mode 100755
index 0000000..54b60d1
--- /dev/null
+++ b/include/spd.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Serial Presence Detect (SPD) EEPROM format according to the
+ * Intel's PC SDRAM Serial Presence Detect (SPD) Specification,
+ * revision 1.2B, November 1999
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _SPD_H_
+#define _SPD_H_
+
+typedef struct spd_eeprom_s {
+	unsigned char info_size;   /*  0 # bytes written into serial memory */
+	unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
+	unsigned char mem_type;    /*  2 Fundamental memory type */
+	unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
+	unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
+	unsigned char nrows;       /*  5 # of Module Rows on this assembly */
+	unsigned char dataw_lsb;   /*  6 Data Width of this assembly */
+	unsigned char dataw_msb;   /*  7 ... Data Width continuation */
+	unsigned char voltage;     /*  8 Voltage intf std of this assembly */
+	unsigned char clk_cycle;   /*  9 SDRAM Cycle time at CL=X */
+	unsigned char clk_access;  /* 10 SDRAM Access from Clock at CL=X */
+	unsigned char config;      /* 11 DIMM Configuration type */
+	unsigned char refresh;     /* 12 Refresh Rate/Type */
+	unsigned char primw;       /* 13 Primary SDRAM Width */
+	unsigned char ecw;         /* 14 Error Checking SDRAM width */
+	unsigned char min_delay;   /* 15 for Back to Back Random Address */
+	unsigned char burstl;      /* 16 Burst Lengths Supported */
+	unsigned char nbanks;      /* 17 # of Banks on Each SDRAM Device */
+	unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
+	unsigned char cs_lat;      /* 19 CS# Latency */
+	unsigned char write_lat;   /* 20 Write Latency (aka Write Recovery) */
+	unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
+	unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
+	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time at CL=X-1 */
+	unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */
+	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time at CL=X-2 */
+	unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */
+	unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
+	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
+	unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
+	unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
+	unsigned char row_dens;    /* 31 Density of each row on module */
+	unsigned char ca_setup;    /* 32 Cmd + Addr signal input setup time */
+	unsigned char ca_hold;     /* 33 Cmd and Addr signal input hold time */
+	unsigned char data_setup;  /* 34 Data signal input setup time */
+	unsigned char data_hold;   /* 35 Data signal input hold time */
+	unsigned char twr;         /* 36 Write Recovery time tWR */
+	unsigned char twtr;        /* 37 Int write to read delay tWTR */
+	unsigned char trtp;        /* 38 Int read to precharge delay tRTP */
+	unsigned char mem_probe;   /* 39 Mem analysis probe characteristics */
+	unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
+	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
+	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
+	unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
+	unsigned char tdqsq;       /* 44 Max DQS to DQ skew */
+	unsigned char tqhs;        /* 45 Max Read DataHold skew tQHS */
+	unsigned char pll_relock;  /* 46 PLL Relock time */
+	unsigned char res[15];     /* 47-xx IDD in SPD and Reserved space */
+	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
+	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
+	unsigned char mid[8];      /* 64 Mfr's JEDEC ID code per JEP-108E */
+	unsigned char mloc;        /* 72 Manufacturing Location */
+	unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
+	unsigned char rev[2];      /* 91 Revision Code */
+	unsigned char mdate[2];    /* 93 Manufacturing Date */
+	unsigned char sernum[4];   /* 95 Assembly Serial Number */
+	unsigned char mspec[27];   /* 99 Manufacturer Specific Data */
+
+	/*
+	 * Open for Customer Use starting with byte 128.
+	 */
+	unsigned char freq;        /* 128 Intel spec: frequency */
+	unsigned char intel_cas;   /* 129 Intel spec: CAS# Latency support */
+} spd_eeprom_t;
+
+
+/*
+ * Byte 2 Fundamental Memory Types.
+ */
+#define SPD_MEMTYPE_FPM		(0x01)
+#define SPD_MEMTYPE_EDO		(0x02)
+#define SPD_MEMTYPE_PIPE_NIBBLE	(0x03)
+#define SPD_MEMTYPE_SDRAM	(0x04)
+#define SPD_MEMTYPE_ROM		(0x05)
+#define SPD_MEMTYPE_SGRAM	(0x06)
+#define SPD_MEMTYPE_DDR		(0x07)
+#define SPD_MEMTYPE_DDR2	(0x08)
+
+#endif /* _SPD_H_ */
diff --git a/include/spd_sdram.h b/include/spd_sdram.h
new file mode 100755
index 0000000..4e754ec
--- /dev/null
+++ b/include/spd_sdram.h
@@ -0,0 +1,6 @@
+#ifndef _SPD_SDRAM_H_
+#define _SPD_SDRAM_H_
+
+long int spd_sdram(int(read_spd)(uint addr));
+
+#endif
diff --git a/include/spi.h b/include/spi.h
new file mode 100755
index 0000000..03dc5bc
--- /dev/null
+++ b/include/spi.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2001
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPI_H_
+#define _SPI_H_
+
+/*
+ * The function call pointer type used to drive the chip select.
+ */
+typedef void (*spi_chipsel_type)(int cs);
+
+
+/*-----------------------------------------------------------------------
+ * Initialization, must be called once on start up.
+ */
+void spi_init(void);
+
+
+/*-----------------------------------------------------------------------
+ * SPI transfer
+ *
+ * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
+ * "bitlen" bits in the SPI MISO port.  That's just the way SPI works.
+ *
+ * The source of the outgoing bits is the "dout" parameter and the
+ * destination of the input bits is the "din" parameter.  Note that "dout"
+ * and "din" can point to the same memory location, in which case the
+ * input data overwrites the output data (since both are buffered by
+ * temporary variables, this is OK).
+ *
+ * If the chipsel() function is not NULL, it is called with a parameter
+ * of '1' (chip select active) at the start of the transfer and again with
+ * a parameter of '0' at the end of the transfer.
+ *
+ * If the chipsel() function _is_ NULL, it the responsibility of the
+ * caller to make the appropriate chip select active before calling
+ * spi_xfer() and making it inactive after spi_xfer() returns.
+ *
+ * spi_xfer() interface:
+ *   chipsel: Routine to call to set/clear the chip select:
+ *              if chipsel is NULL, it is not used.
+ *              if(cs),  make the chip select active (typically '0').
+ *              if(!cs), make the chip select inactive (typically '1').
+ *   dout:    Pointer to a string of bits to send out.  The bits are
+ *              held in a byte array and are sent MSB first.
+ *   din:     Pointer to a string of bits that will be filled in.
+ *   bitlen:  How many bits to write and read.
+ *
+ *   Returns: 0 on success, not 0 on failure
+ */
+int  spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din);
+
+#endif	/* _SPI_H_ */
diff --git a/include/status_led.h b/include/status_led.h
new file mode 100755
index 0000000..a56883b
--- /dev/null
+++ b/include/status_led.h
@@ -0,0 +1,360 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * The purpose of this code is to signal the operational status of a
+ * target which usually boots over the network; while running in
+ * PCBoot, a status LED is blinking. As soon as a valid BOOTP reply
+ * message has been received, the LED is turned off. The Linux
+ * kernel, once it is running, will start blinking the LED again,
+ * with another frequency.
+ */
+
+#ifndef _STATUS_LED_H_
+#define	_STATUS_LED_H_
+
+#ifdef CONFIG_STATUS_LED
+
+#define STATUS_LED_OFF		0
+#define STATUS_LED_BLINKING	1
+#define STATUS_LED_ON		2
+
+void status_led_tick (unsigned long timestamp);
+void status_led_set  (int led, int state);
+
+/*****  TQM8xxL  ********************************************************/
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_HMI10)
+# define STATUS_LED_PAR		im_cpm.cp_pbpar
+# define STATUS_LED_DIR		im_cpm.cp_pbdir
+# define STATUS_LED_ODR		im_cpm.cp_pbodr
+# define STATUS_LED_DAT		im_cpm.cp_pbdat
+
+# define STATUS_LED_BIT		0x00000001
+# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
+
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+/*****  MVS v1  **********************************************************/
+#elif (defined(CONFIG_MVS) && CONFIG_MVS < 2)
+# define STATUS_LED_PAR		im_ioport.iop_pdpar
+# define STATUS_LED_DIR		im_ioport.iop_pddir
+# undef  STATUS_LED_ODR
+# define STATUS_LED_DAT		im_ioport.iop_pddat
+
+# define STATUS_LED_BIT		0x00000001
+# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
+
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+/*****  ETX_094  ********************************************************/
+#elif defined(CONFIG_ETX094)
+
+# define STATUS_LED_PAR		im_ioport.iop_pdpar
+# define STATUS_LED_DIR		im_ioport.iop_pddir
+# undef  STATUS_LED_ODR
+# define STATUS_LED_DAT		im_ioport.iop_pddat
+
+# define STATUS_LED_BIT		0x00000001
+# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+/*****  GEN860T  *********************************************************/
+#elif defined(CONFIG_GEN860T)
+
+# define STATUS_LED_PAR			im_ioport.iop_papar
+# define STATUS_LED_DIR			im_ioport.iop_padir
+# define STATUS_LED_ODR			im_ioport.iop_paodr
+# define STATUS_LED_DAT			im_ioport.iop_padat
+
+# define STATUS_LED_BIT			0x0800	/* Red LED 0 is on PA.4	*/
+# define STATUS_LED_PERIOD		(CFG_HZ / 4)
+# define STATUS_LED_STATE		STATUS_LED_OFF
+# define STATUS_LED_BIT1		0x0400	/* Grn LED 1 is on PA.5	*/
+# define STATUS_LED_PERIOD1		(CFG_HZ / 8)
+# define STATUS_LED_STATE1		STATUS_LED_BLINKING
+# define STATUS_LED_BIT2		0x0080	/* Red LED 2 is on PA.8	*/
+# define STATUS_LED_PERIOD2		(CFG_HZ / 4)
+# define STATUS_LED_STATE2		STATUS_LED_OFF
+# define STATUS_LED_BIT3		0x0040	/* Grn LED 3 is on PA.9	*/
+# define STATUS_LED_PERIOD3		(CFG_HZ / 4)
+# define STATUS_LED_STATE3		STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE		1	/* LED on for bit == 1	*/
+# define STATUS_LED_BOOT		1	/* Boot status on LED 1	*/
+
+/*****  IVMS8  **********************************************************/
+#elif defined(CONFIG_IVMS8)
+
+# define STATUS_LED_PAR		im_cpm.cp_pbpar
+# define STATUS_LED_DIR		im_cpm.cp_pbdir
+# define STATUS_LED_ODR		im_cpm.cp_pbodr
+# define STATUS_LED_DAT		im_cpm.cp_pbdat
+
+# define STATUS_LED_BIT		0x00000010	/* LED 0 is on PB.27	*/
+# define STATUS_LED_PERIOD	(1 * CFG_HZ)
+# define STATUS_LED_STATE	STATUS_LED_OFF
+# define STATUS_LED_BIT1	0x00000020	/* LED 1 is on PB.26	*/
+# define STATUS_LED_PERIOD1	(1 * CFG_HZ)
+# define STATUS_LED_STATE1	STATUS_LED_OFF
+/* IDE LED usable for other purposes, too */
+# define STATUS_LED_BIT2	0x00000008	/* LED 2 is on PB.28	*/
+# define STATUS_LED_PERIOD2	(1 * CFG_HZ)
+# define STATUS_LED_STATE2	STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
+
+# define STATUS_ILOCK_SWITCH	0x00800000	/* ILOCK switch in IRQ4	*/
+
+# define STATUS_ILOCK_PERIOD	(CFG_HZ / 10)	/* about every 100 ms	*/
+
+# define STATUS_LED_YELLOW	0
+# define STATUS_LED_GREEN	1
+# define STATUS_LED_BOOT	2		/* IDE LED used for boot status */
+
+/*****  IVML24  *********************************************************/
+#elif defined(CONFIG_IVML24)
+
+# define STATUS_LED_PAR		im_cpm.cp_pbpar
+# define STATUS_LED_DIR		im_cpm.cp_pbdir
+# define STATUS_LED_ODR		im_cpm.cp_pbodr
+# define STATUS_LED_DAT		im_cpm.cp_pbdat
+
+# define STATUS_LED_BIT		0x00000010	/* LED 0 is on PB.27	*/
+# define STATUS_LED_PERIOD	(1 * CFG_HZ)
+# define STATUS_LED_STATE	STATUS_LED_OFF
+# define STATUS_LED_BIT1	0x00000020	/* LED 1 is on PB.26	*/
+# define STATUS_LED_PERIOD1	(1 * CFG_HZ)
+# define STATUS_LED_STATE1	STATUS_LED_OFF
+/* IDE LED usable for other purposes, too */
+# define STATUS_LED_BIT2	0x00000008	/* LED 2 is on PB.28	*/
+# define STATUS_LED_PERIOD2	(1 * CFG_HZ)
+# define STATUS_LED_STATE2	STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
+
+# define STATUS_ILOCK_SWITCH	0x00004000	/* ILOCK is on PB.17	*/
+
+# define STATUS_ILOCK_PERIOD	(CFG_HZ / 10)	/* about every 100 ms	*/
+
+# define STATUS_LED_YELLOW	0
+# define STATUS_LED_GREEN	1
+# define STATUS_LED_BOOT	2		/* IDE LED used for boot status */
+
+/*****  LANTEC  *********************************************************/
+#elif defined(CONFIG_LANTEC)
+
+# define STATUS_LED_PAR		im_ioport.iop_pdpar
+# define STATUS_LED_DIR		im_ioport.iop_pddir
+# undef  STATUS_LED_ODR
+# define STATUS_LED_DAT		im_ioport.iop_pddat
+
+# if CONFIG_LATEC < 2
+#  define STATUS_LED_BIT	0x1000
+# else
+#  define STATUS_LED_BIT	0x0800
+# endif
+# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0 */
+
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+/*****  PCU E  and  CCM  ************************************************/
+#elif (defined(CONFIG_PCU_E) || defined(CONFIG_CCM))
+
+# define STATUS_LED_PAR		im_cpm.cp_pbpar
+# define STATUS_LED_DIR		im_cpm.cp_pbdir
+# define STATUS_LED_ODR		im_cpm.cp_pbodr
+# define STATUS_LED_DAT		im_cpm.cp_pbdat
+
+# define STATUS_LED_BIT		0x00010000	/* green LED is on PB.15 */
+# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1 */
+
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+/*****  ICU862   ********************************************************/
+#elif defined(CONFIG_ICU862)
+
+# define STATUS_LED_PAR		im_ioport.iop_papar
+# define STATUS_LED_DIR		im_ioport.iop_padir
+# define STATUS_LED_ODR		im_ioport.iop_paodr
+# define STATUS_LED_DAT		im_ioport.iop_padat
+
+# define STATUS_LED_BIT		0x4000		/* LED 0 is on PA.1 */
+# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+# define STATUS_LED_BIT1	0x1000		/* LED 1 is on PA.3 */
+# define STATUS_LED_PERIOD1	(CFG_HZ)
+# define STATUS_LED_STATE1	STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
+
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+/*****  Someone else defines these  *************************************/
+#elif defined(STATUS_LED_PAR)
+
+  /*
+   * ADVICE: Define in your board configuration file rather than
+   * filling this file up with lots of custom board stuff.
+   */
+
+/*****  NetVia   ********************************************************/
+#elif defined(CONFIG_NETVIA)
+
+#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
+
+#define STATUS_LED_PAR		im_ioport.iop_pdpar
+#define STATUS_LED_DIR		im_ioport.iop_pddir
+#undef  STATUS_LED_ODR
+#define STATUS_LED_DAT		im_ioport.iop_pddat
+
+# define STATUS_LED_BIT		0x0080			/* PD.8 */
+# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_BIT1	0x0040			/* PD.9 */
+# define STATUS_LED_PERIOD1	(CFG_HZ / 2)
+# define STATUS_LED_STATE1	STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+#endif
+
+/*****  CMI   ********************************************************/
+#elif defined(CONFIG_CMI)
+# define STATUS_LED_DIR		im_mios.mios_mpiosm32ddr
+# define STATUS_LED_DAT		im_mios.mios_mpiosm32dr
+
+# define STATUS_LED_BIT		0x2000		/* Select one of the 16 possible*/
+						/* MIOS outputs */
+# define STATUS_LED_PERIOD	(CFG_HZ / 2)	/* Blinking periode is 500 ms */
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 0	*/
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+/*****  KUP4K, KUP4X  ****************************************************/
+#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) || defined(CONFIG_CCM)
+
+# define STATUS_LED_PAR		im_ioport.iop_papar
+# define STATUS_LED_DIR		im_ioport.iop_padir
+# define STATUS_LED_ODR		im_ioport.iop_paodr
+# define STATUS_LED_DAT		im_ioport.iop_padat
+
+# define STATUS_LED_BIT		0x00000300  /*  green + red    PA[8]=yellow,  PA[7]=red,  PA[6]=green */
+# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
+
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+#elif defined(CONFIG_SVM_SC8xx)
+# define STATUS_LED_PAR         im_cpm.cp_pbpar
+# define STATUS_LED_DIR         im_cpm.cp_pbdir
+# define STATUS_LED_ODR         im_cpm.cp_pbodr
+# define STATUS_LED_DAT         im_cpm.cp_pbdat
+
+# define STATUS_LED_BIT         0x00000001
+# define STATUS_LED_PERIOD      (CFG_HZ / 2)
+# define STATUS_LED_STATE       STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE      1               /* LED on for bit == 1  */
+
+# define STATUS_LED_BOOT        0               /* LED 0 used for boot status */
+
+/*****  RBC823    ********************************************************/
+#elif defined(CONFIG_RBC823)
+
+# define STATUS_LED_PAR         im_ioport.iop_pcpar
+# define STATUS_LED_DIR         im_ioport.iop_pcdir
+#  undef STATUS_LED_ODR
+# define STATUS_LED_DAT         im_ioport.iop_pcdat
+
+# define STATUS_LED_BIT         0x0002          /* LED 0 is on PC.14 */
+# define STATUS_LED_PERIOD      (CFG_HZ / 2)
+# define STATUS_LED_STATE       STATUS_LED_BLINKING
+# define STATUS_LED_BIT1        0x0004          /* LED 1 is on PC.13 */
+# define STATUS_LED_PERIOD1     (CFG_HZ)
+# define STATUS_LED_STATE1      STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE      1               /* LED on for bit == 1  */
+
+# define STATUS_LED_BOOT        0               /* LED 0 used for boot status */
+
+/*****  HMI10  **********************************************************/
+#elif defined(CONFIG_HMI10)
+# define STATUS_LED_PAR		im_ioport.iop_papar
+# define STATUS_LED_DIR		im_ioport.iop_padir
+# define STATUS_LED_ODR		im_ioport.iop_paodr
+# define STATUS_LED_DAT		im_ioport.iop_padat
+
+# define STATUS_LED_BIT		0x00000001	/* LED is on PA15 */
+# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
+
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+/*****  NetPhone   ********************************************************/
+#elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
+/* XXX empty just to avoid the error */
+/*****  STx XTc    ********************************************************/
+#elif defined(CONFIG_STXXTC)
+/* XXX empty just to avoid the error */
+/*****  sbc8240   ********************************************************/
+#elif defined(CONFIG_WRSBC8240)
+/* XXX empty just to avoid the error */
+/************************************************************************/
+#elif defined(CONFIG_NIOS2)
+/* XXX empty just to avoid the error */
+/************************************************************************/
+#else
+# error Status LED configuration missing
+#endif
+/************************************************************************/
+
+#ifndef CONFIG_BOARD_SPECIFIC_LED
+# include <asm/status_led.h>
+#endif
+
+#endif	/* CONFIG_STATUS_LED	*/
+
+#endif	/* _STATUS_LED_H_	*/
diff --git a/include/sym53c8xx.h b/include/sym53c8xx.h
new file mode 100755
index 0000000..0734fe4
--- /dev/null
+++ b/include/sym53c8xx.h
@@ -0,0 +1,578 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * Most of these definitions are derived from
+ * linux/drivers/scsi/sym53c8xx_defs.h
+ *
+ */
+
+#ifndef _SYM53C8XX_DEFS_H
+#define _SYM53C8XX_DEFS_H
+
+
+#define SCNTL0		0x00    /* full arb., ena parity, par->ATN  */
+
+#define SCNTL1		0x01    /* no reset                         */
+  #define   ISCON   0x10  /* connected to scsi		    				*/
+  #define   CRST    0x08  /* force reset                      */
+  #define   IARB    0x02  /* immediate arbitration            */
+
+#define SCNTL2		0x02    /* no disconnect expected           */
+	#define   SDU     0x80  /* cmd: disconnect will raise error */
+	#define   CHM     0x40  /* sta: chained mode                */
+	#define   WSS     0x08  /* sta: wide scsi send           [W]*/
+	#define   WSR     0x01  /* sta: wide scsi received       [W]*/
+
+#define SCNTL3		0x03    /* cnf system clock dependent       */
+	#define   EWS     0x08  /* cmd: enable wide scsi         [W]*/
+	#define   ULTRA   0x80  /* cmd: ULTRA enable                */
+				/* bits 0-2, 7 rsvd for C1010       */
+
+#define SCID			0x04		/* cnf host adapter scsi address    */
+	#define   RRE     0x40  /* r/w:e enable response to resel.  */
+	#define   SRE     0x20  /* r/w:e enable response to select  */
+
+#define SXFER			0x05		/* ### Sync speed and count         */
+				/* bits 6-7 rsvd for C1010          */
+
+#define SDID			0x06	/* ### Destination-ID               */
+
+#define GPREG			0x07	/* ??? IO-Pins                      */
+
+#define SFBR			0x08	/* ### First byte in phase          */
+
+#define SOCL			0x09
+	#define   CREQ	  0x80	/* r/w: SCSI-REQ                    */
+	#define   CACK	  0x40	/* r/w: SCSI-ACK                    */
+	#define   CBSY	  0x20	/* r/w: SCSI-BSY                    */
+	#define   CSEL	  0x10	/* r/w: SCSI-SEL                    */
+	#define   CATN	  0x08	/* r/w: SCSI-ATN                    */
+	#define   CMSG	  0x04	/* r/w: SCSI-MSG                    */
+	#define   CC_D	  0x02	/* r/w: SCSI-C_D                    */
+	#define   CI_O	  0x01	/* r/w: SCSI-I_O                    */
+
+#define SSID			0x0a
+
+#define SBCL			0x0b
+
+#define DSTAT			0x0c
+  #define   DFE     0x80  /* sta: dma fifo empty              */
+  #define   MDPE    0x40  /* int: master data parity error    */
+  #define   BF      0x20  /* int: script: bus fault           */
+  #define   ABRT    0x10  /* int: script: command aborted     */
+  #define   SSI     0x08  /* int: script: single step         */
+  #define   SIR     0x04  /* int: script: interrupt instruct. */
+  #define   IID     0x01  /* int: script: illegal instruct.   */
+
+#define SSTAT0		0x0d
+  #define   ILF     0x80  /* sta: data in SIDL register lsb   */
+  #define   ORF     0x40  /* sta: data in SODR register lsb   */
+  #define   OLF     0x20  /* sta: data in SODL register lsb   */
+  #define   AIP     0x10  /* sta: arbitration in progress     */
+  #define   LOA     0x08  /* sta: arbitration lost            */
+  #define   WOA     0x04  /* sta: arbitration won             */
+  #define   IRST    0x02  /* sta: scsi reset signal           */
+  #define   SDP     0x01  /* sta: scsi parity signal          */
+
+#define SSTAT1		0x0e
+	#define   FF3210  0xf0	/* sta: bytes in the scsi fifo      */
+
+#define SSTAT2		0x0f
+  #define   ILF1    0x80  /* sta: data in SIDL register msb[W]*/
+  #define   ORF1    0x40  /* sta: data in SODR register msb[W]*/
+  #define   OLF1    0x20  /* sta: data in SODL register msb[W]*/
+  #define   DM      0x04  /* sta: DIFFSENS mismatch (895/6 only) */
+  #define   LDSC    0x02  /* sta: disconnect & reconnect      */
+
+#define DSA				0x10		/* --> Base page                    */
+#define DSA1			0x11
+#define DSA2			0x12
+#define DSA3			0x13
+
+#define ISTAT			0x14	/* --> Main Command and status      */
+  #define   CABRT   0x80  /* cmd: abort current operation     */
+  #define   SRST    0x40  /* mod: reset chip                  */
+  #define   SIGP    0x20  /* r/w: message from host to ncr    */
+  #define   SEM     0x10  /* r/w: message between host + ncr  */
+  #define   CON     0x08  /* sta: connected to scsi           */
+  #define   INTF    0x04  /* sta: int on the fly (reset by wr)*/
+  #define   SIP     0x02  /* sta: scsi-interrupt              */
+  #define   DIP     0x01  /* sta: host/script interrupt       */
+
+
+#define CTEST0		0x18
+#define CTEST1		0x19
+#define CTEST2		0x1a
+	#define   CSIGP   0x40
+				/* bits 0-2,7 rsvd for C1010        */
+
+#define CTEST3		0x1b
+	#define   FLF     0x08  /* cmd: flush dma fifo              */
+	#define   CLF	  	0x04	/* cmd: clear dma fifo		    */
+	#define   FM      0x02  /* mod: fetch pin mode              */
+	#define   WRIE    0x01  /* mod: write and invalidate enable */
+				/* bits 4-7 rsvd for C1010          */
+
+#define DFIFO			0x20
+#define CTEST4		0x21
+	#define   BDIS    0x80  /* mod: burst disable               */
+	#define   MPEE    0x08  /* mod: master parity error enable  */
+
+#define CTEST5		0x22
+	#define   DFS     0x20  /* mod: dma fifo size               */
+				/* bits 0-1, 3-7 rsvd for C1010          */
+#define CTEST6		0x23
+
+#define DBC				0x24	/* ### Byte count and command       */
+#define DNAD			0x28	/* ### Next command register        */
+#define DSP				0x2c	/* --> Script Pointer               */
+#define DSPS			0x30	/* --> Script pointer save/opcode#2 */
+
+#define SCRATCHA	0x34  /* Temporary register a            */
+#define SCRATCHA1	0x35
+#define SCRATCHA2	0x36
+#define SCRATCHA3	0x37
+
+#define DMODE			0x38
+	#define   BL_2    0x80  /* mod: burst length shift value +2 */
+	#define   BL_1    0x40  /* mod: burst length shift value +1 */
+	#define   ERL     0x08  /* mod: enable read line            */
+	#define   ERMP    0x04  /* mod: enable read multiple        */
+	#define   BOF     0x02  /* mod: burst op code fetch         */
+	#define   MAN     0x01  /* mod: manual start				         */
+
+#define DIEN		0x39
+#define SBR			0x3a
+
+#define DCNTL		0x3b			/* --> Script execution control     */
+	#define   CLSE    0x80  /* mod: cache line size enable      */
+	#define   PFF     0x40  /* cmd: pre-fetch flush             */
+	#define   PFEN    0x20  /* mod: pre-fetch enable            */
+	#define   SSM     0x10  /* mod: single step mode            */
+	#define   IRQM    0x08  /* mod: irq mode (1 = totem pole !) */
+	#define   STD     0x04  /* cmd: start dma mode              */
+	#define   IRQD    0x02  /* mod: irq disable                 */
+	#define	  NOCOM   0x01	/* cmd: protect sfbr while reselect */
+				/* bits 0-1 rsvd for C1010          */
+
+#define ADDER			0x3c
+
+#define SIEN			0x40	/* -->: interrupt enable            */
+#define SIST			0x42	/* <--: interrupt status            */
+  #define   SBMC    0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
+  #define   STO     0x0400/* sta: timeout (select)            */
+  #define   GEN     0x0200/* sta: timeout (general)           */
+  #define   HTH     0x0100/* sta: timeout (handshake)         */
+  #define   MA      0x80  /* sta: phase mismatch              */
+  #define   CMP     0x40  /* sta: arbitration complete        */
+  #define   SEL     0x20  /* sta: selected by another device  */
+  #define   RSL     0x10  /* sta: reselected by another device*/
+  #define   SGE     0x08  /* sta: gross error (over/underflow)*/
+  #define   UDC     0x04  /* sta: unexpected disconnect       */
+  #define   RST     0x02  /* sta: scsi bus reset detected     */
+  #define   PAR     0x01  /* sta: scsi parity error           */
+
+#define SLPAR				0x44
+#define SWIDE				0x45
+#define MACNTL			0x46
+#define GPCNTL			0x47
+#define STIME0			0x48    /* cmd: timeout for select&handshake*/
+#define STIME1			0x49    /* cmd: timeout user defined        */
+#define RESPID			0x4a    /* sta: Reselect-IDs                */
+
+#define STEST0			0x4c
+
+#define STEST1			0x4d
+	#define   SCLK    0x80	/* Use the PCI clock as SCSI clock	*/
+	#define   DBLEN   0x08	/* clock doubler running		*/
+	#define   DBLSEL  0x04	/* clock doubler selected		*/
+
+
+#define STEST2			0x4e
+	#define   ROF     0x40	/* reset scsi offset (after gross error!) */
+	#define   EXT     0x02  /* extended filtering                     */
+
+#define STEST3			0x4f
+	#define   TE     0x80	/* c: tolerAnt enable */
+	#define   HSC    0x20	/* c: Halt SCSI Clock */
+	#define   CSF    0x02	/* c: clear scsi fifo */
+
+#define SIDL			0x50	/* Lowlevel: latched from scsi data */
+#define STEST4		0x52
+	#define SMODE  	0xc0	/* SCSI bus mode      (895/6 only) */
+	#define SMODE_HVD 0x40	/* High Voltage Differential       */
+	#define SMODE_SE  0x80	/* Single Ended                    */
+	#define SMODE_LVD 0xc0	/* Low Voltage Differential        */
+	#define LCKFRQ 0x20	/* Frequency Lock (895/6 only)     */
+				/* bits 0-5 rsvd for C1010          */
+
+#define SODL			0x54	/* Lowlevel: data out to scsi data  */
+
+#define SBDL			0x58	/* Lowlevel: data from scsi data    */
+
+
+/*-----------------------------------------------------------
+**
+**	Utility macros for the script.
+**
+**-----------------------------------------------------------
+*/
+
+#define REG(r) (r)
+
+/*-----------------------------------------------------------
+**
+**	SCSI phases
+**
+**	DT phases illegal for ncr driver.
+**
+**-----------------------------------------------------------
+*/
+
+#define	SCR_DATA_OUT	0x00000000
+#define	SCR_DATA_IN	0x01000000
+#define	SCR_COMMAND	0x02000000
+#define	SCR_STATUS	0x03000000
+#define SCR_DT_DATA_OUT	0x04000000
+#define SCR_DT_DATA_IN	0x05000000
+#define SCR_MSG_OUT	0x06000000
+#define SCR_MSG_IN      0x07000000
+
+#define SCR_ILG_OUT	0x04000000
+#define SCR_ILG_IN	0x05000000
+
+/*-----------------------------------------------------------
+**
+**	Data transfer via SCSI.
+**
+**-----------------------------------------------------------
+**
+**	MOVE_ABS (LEN)
+**	<<start address>>
+**
+**	MOVE_IND (LEN)
+**	<<dnad_offset>>
+**
+**	MOVE_TBL
+**	<<dnad_offset>>
+**
+**-----------------------------------------------------------
+*/
+
+#define OPC_MOVE          0x08000000
+
+#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
+#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
+#define SCR_MOVE_TBL     (0x10000000 | OPC_MOVE)
+
+#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
+#define SCR_CHMOV_IND(l) ((0x20000000) | (l))
+#define SCR_CHMOV_TBL     (0x10000000)
+
+
+/*-----------------------------------------------------------
+**
+**	Selection
+**
+**-----------------------------------------------------------
+**
+**	SEL_ABS | SCR_ID (0..15)    [ | REL_JMP]
+**	<<alternate_address>>
+**
+**	SEL_TBL | << dnad_offset>>  [ | REL_JMP]
+**	<<alternate_address>>
+**
+**-----------------------------------------------------------
+*/
+
+#define	SCR_SEL_ABS	0x40000000
+#define	SCR_SEL_ABS_ATN	0x41000000
+#define	SCR_SEL_TBL	0x42000000
+#define	SCR_SEL_TBL_ATN	0x43000000
+
+
+#define SCR_JMP_REL     0x04000000
+#define SCR_ID(id)	(((unsigned long)(id)) << 16)
+
+/*-----------------------------------------------------------
+**
+**	Waiting for Disconnect or Reselect
+**
+**-----------------------------------------------------------
+**
+**	WAIT_DISC
+**	dummy: <<alternate_address>>
+**
+**	WAIT_RESEL
+**	<<alternate_address>>
+**
+**-----------------------------------------------------------
+*/
+
+#define	SCR_WAIT_DISC	0x48000000
+#define SCR_WAIT_RESEL  0x50000000
+
+/*-----------------------------------------------------------
+**
+**	Bit Set / Reset
+**
+**-----------------------------------------------------------
+**
+**	SET (flags {|.. })
+**
+**	CLR (flags {|.. })
+**
+**-----------------------------------------------------------
+*/
+
+#define SCR_SET(f)     (0x58000000 | (f))
+#define SCR_CLR(f)     (0x60000000 | (f))
+
+#define	SCR_CARRY	0x00000400
+#define	SCR_TRG		0x00000200
+#define	SCR_ACK		0x00000040
+#define	SCR_ATN		0x00000008
+
+
+/*-----------------------------------------------------------
+**
+**	Memory to memory move
+**
+**-----------------------------------------------------------
+**
+**	COPY (bytecount)
+**	<< source_address >>
+**	<< destination_address >>
+**
+**	SCR_COPY   sets the NO FLUSH option by default.
+**	SCR_COPY_F does not set this option.
+**
+**	For chips which do not support this option,
+**	ncr_copy_and_bind() will remove this bit.
+**-----------------------------------------------------------
+*/
+
+#define SCR_NO_FLUSH 0x01000000
+
+#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
+#define SCR_COPY_F(n) (0xc0000000 | (n))
+
+/*-----------------------------------------------------------
+**
+**	Register move and binary operations
+**
+**-----------------------------------------------------------
+**
+**	SFBR_REG (reg, op, data)        reg  = SFBR op data
+**	<< 0 >>
+**
+**	REG_SFBR (reg, op, data)        SFBR = reg op data
+**	<< 0 >>
+**
+**	REG_REG  (reg, op, data)        reg  = reg op data
+**	<< 0 >>
+**
+**-----------------------------------------------------------
+**	On 810A, 860, 825A, 875, 895 and 896 chips the content
+**	of SFBR register can be used as data (SCR_SFBR_DATA).
+**	The 896 has additionnal IO registers starting at
+**	offset 0x80. Bit 7 of register offset is stored in
+**	bit 7 of the SCRIPTS instruction first DWORD.
+**-----------------------------------------------------------
+*/
+
+#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */
+
+#define SCR_SFBR_REG(reg,op,data) \
+	(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
+
+#define SCR_REG_SFBR(reg,op,data) \
+	(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
+
+#define SCR_REG_REG(reg,op,data) \
+	(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
+
+
+#define      SCR_LOAD   0x00000000
+#define      SCR_SHL    0x01000000
+#define      SCR_OR     0x02000000
+#define      SCR_XOR    0x03000000
+#define      SCR_AND    0x04000000
+#define      SCR_SHR    0x05000000
+#define      SCR_ADD    0x06000000
+#define      SCR_ADDC   0x07000000
+
+#define      SCR_SFBR_DATA   (0x00800000>>8ul)	/* Use SFBR as data */
+
+/*-----------------------------------------------------------
+**
+**	FROM_REG (reg)		  SFBR = reg
+**	<< 0 >>
+**
+**	TO_REG	 (reg)		  reg  = SFBR
+**	<< 0 >>
+**
+**	LOAD_REG (reg, data)	  reg  = <data>
+**	<< 0 >>
+**
+**	LOAD_SFBR(data) 	  SFBR = <data>
+**	<< 0 >>
+**
+**-----------------------------------------------------------
+*/
+
+#define	SCR_FROM_REG(reg) \
+	SCR_REG_SFBR(reg,SCR_OR,0)
+
+#define	SCR_TO_REG(reg) \
+	SCR_SFBR_REG(reg,SCR_OR,0)
+
+#define	SCR_LOAD_REG(reg,data) \
+	SCR_REG_REG(reg,SCR_LOAD,data)
+
+#define SCR_LOAD_SFBR(data) \
+	(SCR_REG_SFBR (gpreg, SCR_LOAD, data))
+
+/*-----------------------------------------------------------
+**
+**	LOAD  from memory   to register.
+**	STORE from register to memory.
+**
+**	Only supported by 810A, 860, 825A, 875, 895 and 896.
+**
+**-----------------------------------------------------------
+**
+**	LOAD_ABS (LEN)
+**	<<start address>>
+**
+**	LOAD_REL (LEN)        (DSA relative)
+**	<<dsa_offset>>
+**
+**-----------------------------------------------------------
+*/
+
+#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
+#define SCR_NO_FLUSH2	0x02000000
+#define SCR_DSA_REL2	0x10000000
+
+#define SCR_LOAD_R(reg, how, n) \
+	(0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
+
+#define SCR_STORE_R(reg, how, n) \
+	(0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
+
+#define SCR_LOAD_ABS(reg, n)	SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
+#define SCR_LOAD_REL(reg, n)	SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
+#define SCR_LOAD_ABS_F(reg, n)	SCR_LOAD_R(reg, 0, n)
+#define SCR_LOAD_REL_F(reg, n)	SCR_LOAD_R(reg, SCR_DSA_REL2, n)
+
+#define SCR_STORE_ABS(reg, n)	SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
+#define SCR_STORE_REL(reg, n)	SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
+#define SCR_STORE_ABS_F(reg, n)	SCR_STORE_R(reg, 0, n)
+#define SCR_STORE_REL_F(reg, n)	SCR_STORE_R(reg, SCR_DSA_REL2, n)
+
+
+/*-----------------------------------------------------------
+**
+**	Waiting for Disconnect or Reselect
+**
+**-----------------------------------------------------------
+**
+**	JUMP            [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<address>>
+**
+**	JUMPR           [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<distance>>
+**
+**	CALL            [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<address>>
+**
+**	CALLR           [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<distance>>
+**
+**	RETURN          [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<dummy>>
+**
+**	INT             [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<ident>>
+**
+**	INT_FLY         [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<ident>>
+**
+**	Conditions:
+**	     WHEN (phase)
+**	     IF   (phase)
+**	     CARRYSET
+**	     DATA (data, mask)
+**
+**-----------------------------------------------------------
+*/
+
+#define SCR_NO_OP       0x80000000
+#define SCR_JUMP        0x80080000
+#define SCR_JUMP64      0x80480000
+#define SCR_JUMPR       0x80880000
+#define SCR_CALL        0x88080000
+#define SCR_CALLR       0x88880000
+#define SCR_RETURN      0x90080000
+#define SCR_INT         0x98080000
+#define SCR_INT_FLY     0x98180000
+
+#define IFFALSE(arg)   (0x00080000 | (arg))
+#define IFTRUE(arg)    (0x00000000 | (arg))
+
+#define WHEN(phase)    (0x00030000 | (phase))
+#define IF(phase)      (0x00020000 | (phase))
+
+#define DATA(D)        (0x00040000 | ((D) & 0xff))
+#define MASK(D,M)      (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
+
+#define CARRYSET       (0x00200000)
+
+
+#define SIR_COMPLETE					 0x10000000
+/* script errors */
+#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001
+#define SIR_CMD_OUT_ILL_PH     0x00000002
+#define SIR_STATUS_ILL_PH			 0x00000003
+#define SIR_MSG_RECEIVED			 0x00000004
+#define SIR_DATA_IN_ERR        0x00000005
+#define SIR_DATA_OUT_ERR			 0x00000006
+#define SIR_SCRIPT_ERROR			 0x00000007
+#define SIR_MSG_OUT_NO_CMD		 0x00000008
+#define SIR_MSG_OVER7					 0x00000009
+/* Fly interrupt */
+#define INT_ON_FY							 0x00000080
+
+/* Hardware errors  are defined in scsi.h */
+
+#define SCSI_IDENTIFY					0xC0
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#endif
diff --git a/include/systemace.h b/include/systemace.h
new file mode 100755
index 0000000..be43d46
--- /dev/null
+++ b/include/systemace.h
@@ -0,0 +1,31 @@
+#ifndef __SYSTEMACE_H
+#define __SYSTEMACE_H
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (steve@picturel.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ident "$Id:$"
+
+#ifdef CONFIG_SYSTEMACE
+
+# include  <part.h>
+
+block_dev_desc_t *  systemace_get_dev(int dev);
+
+#endif	/* CONFIG_SYSTEMACE */
+#endif	/* __SYSTEMACE_H */
diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h
new file mode 100755
index 0000000..7d3b8c8
--- /dev/null
+++ b/include/ubi_uboot.h
@@ -0,0 +1,232 @@
+/*
+ * Header file for UBI support for U-Boot
+ *
+ * Adaptation from kernel to U-Boot
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __UBOOT_UBI_H
+#define __UBOOT_UBI_H
+
+#include <common.h>
+#include <compiler.h>
+#include <malloc.h>
+#include <div64.h>
+#include <linux/crc32.h>
+#include <linux/types.h>
+#include <linux/list.h>
+#include <linux/rbtree.h>
+#include <linux/string.h>
+#include <linux/mtd/ubi.h>
+
+#ifdef CONFIG_CMD_ONENAND
+#include <onenand_uboot.h>
+#endif
+
+#include <asm/errno.h>
+
+#define KERN_EMERG
+#define KERN_ALERT
+#define KERN_CRIT
+#define KERN_ERR
+#define KERN_WARNING
+#define KERN_NOTICE
+#define KERN_INFO
+#define KERN_DEBUG
+
+#define DPRINTK(format, args...)					\
+do {									\
+	printf("%s[%d]: " format "\n", __func__, __LINE__, ##args);	\
+} while (0)
+
+/* configurable */
+#define CONFIG_MTD_UBI_WL_THRESHOLD	4096
+#define CONFIG_MTD_UBI_BEB_RESERVE	1
+#define UBI_IO_DEBUG			0
+
+/* debug options (Linux: drivers/mtd/ubi/Kconfig.debug) */
+#undef CONFIG_MTD_UBI_DEBUG
+#undef CONFIG_MTD_UBI_DEBUG_PARANOID
+#undef CONFIG_MTD_UBI_DEBUG_MSG
+#undef CONFIG_MTD_UBI_DEBUG_MSG_EBA
+#undef CONFIG_MTD_UBI_DEBUG_MSG_WL
+#undef CONFIG_MTD_UBI_DEBUG_MSG_IO
+#undef CONFIG_MTD_UBI_DEBUG_MSG_BLD
+#define CONFIG_MTD_UBI_DEBUG_DISABLE_BGT
+
+/* build.c */
+#define get_device(...)
+#define put_device(...)
+#define ubi_sysfs_init(...)		0
+#define ubi_sysfs_close(...)		do { } while (0)
+static inline int is_power_of_2(unsigned long n)
+{
+	return (n != 0 && ((n & (n - 1)) == 0));
+}
+
+/* FIXME */
+#define MKDEV(...)			0
+#define MAJOR(dev)			0
+#define MINOR(dev)			0
+
+#define alloc_chrdev_region(...)	0
+#define unregister_chrdev_region(...)
+
+#define class_create(...)		__builtin_return_address(0)
+#define class_create_file(...)		0
+#define class_remove_file(...)
+#define class_destroy(...)
+#define misc_register(...)		0
+#define misc_deregister(...)
+
+/* vmt.c */
+#define device_register(...)		0
+#define volume_sysfs_init(...)		0
+#define volume_sysfs_close(...)		do { } while (0)
+
+/* kapi.c */
+
+/* eba.c */
+
+/* io.c */
+#define init_waitqueue_head(...)	do { } while (0)
+#define wait_event_interruptible(...)	0
+#define wake_up_interruptible(...)	do { } while (0)
+#define print_hex_dump(...)		do { } while (0)
+#define dump_stack(...)			do { } while (0)
+
+/* wl.c */
+#define task_pid_nr(x)			0
+#define set_freezable(...)		do { } while (0)
+#define try_to_freeze(...)		0
+#define set_current_state(...)		do { } while (0)
+#define kthread_should_stop(...)	0
+#define schedule()			do { } while (0)
+
+/* upd.c */
+static inline unsigned long copy_from_user(void *dest, const void *src,
+					   unsigned long count)
+{
+	memcpy((void *)dest, (void *)src, count);
+	return 0;
+}
+
+/* common */
+typedef int	spinlock_t;
+typedef int	wait_queue_head_t;
+#define spin_lock_init(...)
+#define spin_lock(...)
+#define spin_unlock(...)
+
+#define mutex_init(...)
+#define mutex_lock(...)
+#define mutex_unlock(...)
+
+#define init_rwsem(...)			do { } while (0)
+#define down_read(...)			do { } while (0)
+#define down_write(...)			do { } while (0)
+#define down_write_trylock(...)		1
+#define up_read(...)			do { } while (0)
+#define up_write(...)			do { } while (0)
+
+struct kmem_cache { int i; };
+#define kmem_cache_create(...)		1
+#define kmem_cache_alloc(obj, gfp)	malloc(sizeof(struct ubi_wl_entry))
+#define kmem_cache_free(obj, size)	free(size)
+#define kmem_cache_destroy(...)
+
+#define cond_resched()			do { } while (0)
+#define yield()				do { } while (0)
+
+#define KERN_WARNING
+#define KERN_ERR
+#define KERN_NOTICE
+#define KERN_DEBUG
+
+#define GFP_KERNEL			0
+#define GFP_NOFS			1
+
+#define __user
+#define __init
+#define __exit
+
+#define kthread_create(...)	__builtin_return_address(0)
+#define kthread_stop(...)	do { } while (0)
+#define wake_up_process(...)	do { } while (0)
+
+#define BUS_ID_SIZE		20
+
+struct rw_semaphore { int i; };
+struct device {
+	struct device		*parent;
+	struct class		*class;
+	char	bus_id[BUS_ID_SIZE];	/* position on parent bus */
+	dev_t			devt;	/* dev_t, creates the sysfs "dev" */
+	void	(*release)(struct device *dev);
+};
+struct mutex { int i; };
+struct kernel_param { int i; };
+
+struct cdev {
+	int owner;
+	dev_t dev;
+};
+#define cdev_init(...)		do { } while (0)
+#define cdev_add(...)		0
+#define cdev_del(...)		do { } while (0)
+
+#define MAX_ERRNO		4095
+#define IS_ERR_VALUE(x)		((x) >= (unsigned long)-MAX_ERRNO)
+
+static inline void *ERR_PTR(long error)
+{
+	return (void *) error;
+}
+
+static inline long PTR_ERR(const void *ptr)
+{
+	return (long) ptr;
+}
+
+static inline long IS_ERR(const void *ptr)
+{
+	return IS_ERR_VALUE((unsigned long)ptr);
+}
+
+/* Force a compilation error if condition is true */
+#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
+
+/* module */
+#define THIS_MODULE		0
+#define try_module_get(...)	1
+#define module_put(...)		do { } while (0)
+#define module_init(...)
+#define module_exit(...)
+#define EXPORT_SYMBOL(...)
+#define EXPORT_SYMBOL_GPL(...)
+#define module_param_call(...)
+#define MODULE_PARM_DESC(...)
+#define MODULE_VERSION(...)
+#define MODULE_DESCRIPTION(...)
+#define MODULE_AUTHOR(...)
+#define MODULE_LICENSE(...)
+
+#ifndef __UBIFS_H__
+#include "../fs/ubi/ubi.h"
+#endif
+
+/* functions */
+extern int ubi_mtd_param_parse(const char *val, struct kernel_param *kp);
+extern int ubi_init(void);
+extern void ubi_exit(void);
+extern void cmd_ubi_start(int start);
+extern void cmd_ubi_size(int size);
+extern struct ubi_device *ubi_devices[];
+
+#endif
diff --git a/include/universe.h b/include/universe.h
new file mode 100755
index 0000000..2892d31
--- /dev/null
+++ b/include/universe.h
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _universe_h
+#define _universe_h
+
+typedef struct _UNIVERSE UNIVERSE;
+typedef struct _SLAVE_IMAGE SLAVE_IMAGE;
+typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET;
+
+struct _SLAVE_IMAGE {
+	unsigned int ctl;      /* Control     */
+	unsigned int bs;       /* Base        */
+	unsigned int bd;       /* Bound       */
+	unsigned int to;       /* Translation */
+	unsigned int reserved;
+};
+
+struct _UNIVERSE {
+	unsigned int pci_id;
+	unsigned int pci_csr;
+	unsigned int pci_class;
+	unsigned int pci_misc0;
+	unsigned int pci_bs;
+	unsigned int spare0[10];
+	unsigned int pci_misc1;
+	unsigned int spare1[48];
+	SLAVE_IMAGE  lsi[4];
+	unsigned int spare2[8];
+	unsigned int scyc_ctl;
+	unsigned int scyc_addr;
+	unsigned int scyc_en;
+	unsigned int scyc_cmp;
+	unsigned int scyc_swp;
+	unsigned int lmisc;
+	unsigned int slsi;
+	unsigned int l_cmderr;
+	unsigned int laerr;
+	unsigned int spare3[27];
+	unsigned int dctl;
+	unsigned int dtbc;
+	unsigned int dla;
+	unsigned int spare4[1];
+	unsigned int dva;
+	unsigned int spare5[1];
+	unsigned int dcpp;
+	unsigned int spare6[1];
+	unsigned int dgcs;
+	unsigned int d_llue;
+	unsigned int spare7[54];
+	unsigned int lint_en;
+	unsigned int lint_stat;
+	unsigned int lint_map0;
+	unsigned int lint_map1;
+	unsigned int vint_en;
+	unsigned int vint_stat;
+	unsigned int vint_map0;
+	unsigned int vint_map1;
+	unsigned int statid;
+	unsigned int vx_statid[7];
+	unsigned int spare8[48];
+	unsigned int mast_ctl;
+	unsigned int misc_ctl;
+	unsigned int misc_stat;
+	unsigned int user_am;
+	unsigned int spare9[700];
+	SLAVE_IMAGE  vsi[4];
+	unsigned int spare10[8];
+	unsigned int vrai_ctl;
+	unsigned int vrai_bs;
+	unsigned int spare11[2];
+	unsigned int vcsr_ctl;
+	unsigned int vcsr_to;
+	unsigned int v_amerr;
+	unsigned int vaerr;
+	unsigned int spare12[25];
+	unsigned int vcsr_clr;
+	unsigned int vcsr_set;
+	unsigned int vcsr_bs;
+};
+
+#define IRQ_VOWN    0x0001
+#define IRQ_VIRQ1   0x0002
+#define IRQ_VIRQ2   0x0004
+#define IRQ_VIRQ3   0x0008
+#define IRQ_VIRQ4   0x0010
+#define IRQ_VIRQ5   0x0020
+#define IRQ_VIRQ6   0x0040
+#define IRQ_VIRQ7   0x0080
+#define IRQ_DMA     0x0100
+#define IRQ_LERR    0x0200
+#define IRQ_VERR    0x0400
+#define IRQ_res     0x0800
+#define IRQ_IACK    0x1000
+#define IRQ_SWINT   0x2000
+#define IRQ_SYSFAIL 0x4000
+#define IRQ_ACFAIL  0x8000
+
+struct _TDMA_CMD_PACKET {
+	unsigned int dctl;   /* DMA Control         */
+	unsigned int dtbc;   /* Transfer Byte Count */
+	unsigned int dlv;    /* PCI Address         */
+	unsigned int res1;   /* Reserved            */
+	unsigned int dva;    /* Vme Address         */
+	unsigned int res2;   /* Reserved            */
+	unsigned int dcpp;   /* Pointer to Numed Cmd Packet with rPN */
+	unsigned int res3;   /* Reserved                             */
+};
+
+#define VME_AM_A16		0x01
+#define VME_AM_A24		0x02
+#define VME_AM_A32		0x03
+#define VME_AM_Axx		0x03
+#define VME_AM_SUP		0x04
+#define VME_AM_DATA		0x10
+#define VME_AM_PROG		0x20
+#define VME_AM_Mxx		0x30
+
+#define VME_FLAG_D8             0x01
+#define VME_FLAG_D16            0x02
+#define VME_FLAG_D32            0x03
+#define VME_FLAG_Dxx		0x03
+
+#define PCI_MS_MEM		0x01
+#define PCI_MS_IO		0x02
+#define PCI_MS_CONFIG		0x03
+#define PCI_MS_Mxx		0x03
+
+#endif
diff --git a/include/usb.h b/include/usb.h
new file mode 100755
index 0000000..e7d77d6
--- /dev/null
+++ b/include/usb.h
@@ -0,0 +1,346 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+#ifndef _USB_H_
+#define _USB_H_
+#define LITTLEENDIAN		1	/* used by usb_uhci.c		*/
+#include <usb_defs.h>
+#include <usbdescriptors.h>
+
+/* Everything is aribtrary */
+#define USB_ALTSETTINGALLOC		4
+#define USB_MAXALTSETTING		128	/* Hard limit */
+
+#define USB_MAX_DEVICE			32
+#define USB_MAXCONFIG			8
+#define USB_MAXINTERFACES		8
+#define USB_MAXENDPOINTS		16
+#define USB_MAXCHILDREN		8	/* This is arbitrary */
+#define USB_MAX_HUB			16
+//Charles
+//#define USB_CNTL_TIMEOUT 100 /* 100ms timeout */
+#define USB_CNTL_TIMEOUT 0 /* 1ms x 5  timeout */
+
+/* device request (setup) */
+struct devrequest {
+	unsigned char requesttype;
+	unsigned char request;
+	unsigned short value;
+	unsigned short index;
+	unsigned short length;
+} __attribute__ ((packed));
+
+
+/* All standard descriptors have these 2 fields in common */
+struct usb_descriptor_header {
+	unsigned char  bLength;
+	unsigned char  bDescriptorType;
+} __attribute__ ((packed));
+
+/* Interface */
+struct usb_interface {
+	struct usb_interface_descriptor desc;
+
+	unsigned char	no_of_ep;
+	unsigned char	num_altsetting;
+	unsigned char	act_altsetting;
+
+	struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
+} __attribute__ ((packed));
+
+/* Configuration information.. */
+struct usb_config {
+	struct usb_configuration_descriptor desc;
+
+	unsigned char	no_of_if;	/* number of interfaces */
+	struct usb_interface if_desc[USB_MAXINTERFACES];
+} __attribute__ ((packed));
+
+
+enum {
+	/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
+	PACKET_SIZE_8   = 0,
+	PACKET_SIZE_16  = 1,
+	PACKET_SIZE_32  = 2,
+	PACKET_SIZE_64  = 3,
+};
+
+struct usb_device {
+	int devnum;			/* Device number on USB bus */
+	int	speed;			/* full/low/high */
+	int slow;			/* Slow device? */
+	char mf[32];			/* manufacturer */
+	char prod[32];			/* product */
+	char serial[32];		/* serial number */
+
+	int maxpacketsize;		/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
+	unsigned int toggle[2];		/* one bit for each endpoint ([0] = IN, [1] = OUT) */
+	unsigned int halted[2];		/* endpoint halts; one bit per endpoint # & direction; */
+			    /* [0] = IN, [1] = OUT */
+	int epmaxpacketin[16];		/* INput endpoint specific maximums */
+	int epmaxpacketout[16];		/* OUTput endpoint specific maximums */
+
+	int configno;			/* selected config number */
+	struct usb_device_descriptor descriptor; /* Device Descriptor */
+	struct usb_config config; /* config descriptor */
+	int have_langid;		/* whether string_langid is valid yet */
+	int string_langid;		/* language ID for strings */
+	int (*irq_handle)(struct usb_device *dev);
+	unsigned long irq_status;
+	int irq_act_len;		/* transfered bytes */
+	void *privptr;
+	/*
+	 * Child devices -  if this is a hub device
+	 * Each instance needs its own set of data structures.
+	 */
+	unsigned long status;
+	int act_len;			/* transfered bytes */
+	int maxchild;			/* Number of ports if hub */
+	int portnr;
+	struct usb_device *parent;
+	struct usb_device *children[USB_MAXCHILDREN];
+} __attribute__ ((packed)) ;
+
+/**********************************************************************
+ * this is how the lowlevel part communicate with the outer world
+ */
+//CharlesTu,2011.03.30,suppport uhci and ehci drivers.
+#if defined(CONFIG_USB_EHCI) ||defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined (CONFIG_USB_SL811HS)
+
+int usb_lowlevel_init(void);
+int usb_lowlevel_stop(void);
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len);
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+			int transfer_len,struct devrequest *setup);
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+			int transfer_len, int interval);
+//port routing
+void ehci_disable_port_owner(void);
+int uhci_lowlevel_init(void);
+int uhci_lowlevel_stop(void);
+int submit_uhci_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len);
+int submit_uhci_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+			int transfer_len,struct devrequest *setup);
+int submit_uhci_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+			int transfer_len, int interval);
+
+/* Defines */
+#define USB_UHCI_VEND_ID 0x8086
+#define USB_UHCI_DEV_ID	 0x7112
+#define usb_ehci_flag  1
+#define usb_uhci_flag  2
+#define usb_ctl_pipe  4
+#define usb_bulk_pipe  8
+#define usb_bulk_inquiry  0x10
+#else
+//#error USB Lowlevel not defined
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+
+#define USB_MAX_STOR_DEV 5
+block_dev_desc_t *usb_stor_get_dev(int index);
+int usb_stor_scan(int mode);
+void usb_stor_info(void);
+#endif
+
+
+#define USB_MAX_ETH_DEV 5
+#ifdef CONFIG_USB_HOST_ETHER
+int usb_host_eth_scan(int mode);
+#endif
+
+#ifdef CONFIG_USB_KEYBOARD
+
+int drv_usb_kbd_init(void);
+int usb_kbd_deregister(void);
+
+#endif
+/* routines */
+int usb_init(void); /* initialize the USB Controller */
+int usb_stop(void); /* stop the USB Controller */
+
+
+int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
+int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id);
+struct usb_device * usb_get_dev_index(int index);
+int usb_control_msg(struct usb_device *dev, unsigned int pipe,
+			unsigned char request, unsigned char requesttype,
+			unsigned short value, unsigned short index,
+			void *data, unsigned short size, int timeout);
+int usb_bulk_msg(struct usb_device *dev, unsigned int pipe,
+			void *data, int len, int *actual_length, int timeout);
+int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
+			void *buffer,int transfer_len, int interval);
+int usb_disable_asynch(int disable);
+int usb_maxpacket(struct usb_device *dev,unsigned long pipe);
+void __inline__ wait_ms(unsigned long ms);
+int usb_get_configuration_no(struct usb_device *dev,unsigned char *buffer,int cfgno);
+int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type, unsigned char id, void *buf, int size);
+int usb_get_class_descriptor(struct usb_device *dev, int ifnum,
+		unsigned char type, unsigned char id, void *buf, int size);
+int usb_clear_halt(struct usb_device *dev, int pipe);
+int usb_string(struct usb_device *dev, int index, char *buf, size_t size);
+int usb_set_interface(struct usb_device *dev, int interface, int alternate);
+int hub_port_reset(struct usb_device *dev, int port,	unsigned short *portstat);
+inline char *portspeed(int speed);
+
+/* big endian -> little endian conversion */
+/* some CPUs are already little endian e.g. the ARM920T */
+//#ifdef LITTLEENDIAN
+#define swap_16(x) ((unsigned short)(x))
+#define swap_32(x) ((unsigned long)(x))
+
+
+/*
+ * Calling this entity a "pipe" is glorifying it. A USB pipe
+ * is something embarrassingly simple: it basically consists
+ * of the following information:
+ *  - device number (7 bits)
+ *  - endpoint number (4 bits)
+ *  - current Data0/1 state (1 bit)
+ *  - direction (1 bit)
+ *  - speed (1 bit)
+ *  - max packet size (2 bits: 8, 16, 32 or 64)
+ *  - pipe type (2 bits: control, interrupt, bulk, isochronous)
+ *
+ * That's 18 bits. Really. Nothing more. And the USB people have
+ * documented these eighteen bits as some kind of glorious
+ * virtual data structure.
+ *
+ * Let's not fall in that trap. We'll just encode it as a simple
+ * unsigned int. The encoding is:
+ *
+ *  - max size:		bits 0-1	(00 = 8, 01 = 16, 10 = 32, 11 = 64)
+ *  - direction:	bit 7		(0 = Host-to-Device [Out], 1 = Device-to-Host [In])
+ *  - device:		bits 8-14
+ *  - endpoint:		bits 15-18
+ *  - Data0/1:		bit 19
+ *  - speed:		bit 26		(0 = Full, 1 = Low Speed 2 high speed)
+ *  - pipe type:	bits 30-31	(00 = isochronous, 01 = interrupt, 10 = control, 11 = bulk)
+ *
+ * Why? Because it's arbitrary, and whatever encoding we select is really
+ * up to us. This one happens to share a lot of bit positions with the UHCI
+ * specification, so that much of the uhci driver can just mask the bits
+ * appropriately.
+ */
+/* Create various pipes... */
+#define create_pipe(dev,endpoint) \
+		(((dev)->devnum << 8) | ((endpoint) << 15) | \
+		((dev)->speed << 26) | (dev)->maxpacketsize)
+#define default_pipe(dev) ((dev)->speed << 26)
+
+#define usb_sndctrlpipe(dev, endpoint)	((PIPE_CONTROL << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvctrlpipe(dev, endpoint)	((PIPE_CONTROL << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndisocpipe(dev, endpoint)	((PIPE_ISOCHRONOUS << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvisocpipe(dev, endpoint)	((PIPE_ISOCHRONOUS << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndbulkpipe(dev, endpoint)	((PIPE_BULK << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvbulkpipe(dev, endpoint)	((PIPE_BULK << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndintpipe(dev, endpoint)	((PIPE_INTERRUPT << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvintpipe(dev, endpoint)	((PIPE_INTERRUPT << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_snddefctrl(dev)		((PIPE_CONTROL << 30) | \
+					 default_pipe(dev))
+#define usb_rcvdefctrl(dev)		((PIPE_CONTROL << 30) | \
+					 default_pipe(dev) | \
+					 USB_DIR_IN)
+
+/* The D0/D1 toggle bits */
+#define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> ep) & 1)
+#define usb_dotoggle(dev, ep, out)  ((dev)->toggle[out] ^= (1 << ep))
+#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = \
+						((dev)->toggle[out] & \
+						 ~(1 << ep)) | ((bit) << ep))
+
+/* Endpoint halt control/status */
+#define usb_endpoint_out(ep_dir)	(((ep_dir >> 7) & 1) ^ 1)
+#define usb_endpoint_halt(dev, ep, out) ((dev)->halted[out] |= (1 << (ep)))
+#define usb_endpoint_running(dev, ep, out) ((dev)->halted[out] &= ~(1 << (ep)))
+#define usb_endpoint_halted(dev, ep, out) ((dev)->halted[out] & (1 << (ep)))
+
+#define usb_packetid(pipe)	(((pipe) & USB_DIR_IN) ? USB_PID_IN : \
+				 USB_PID_OUT)
+
+#define usb_pipeout(pipe)	((((pipe) >> 7) & 1) ^ 1)
+#define usb_pipein(pipe)	(((pipe) >> 7) & 1)
+#define usb_pipedevice(pipe)	(((pipe) >> 8) & 0x7f)
+#define usb_pipe_endpdev(pipe)	(((pipe) >> 8) & 0x7ff)
+#define usb_pipeendpoint(pipe)	(((pipe) >> 15) & 0xf)
+#define usb_pipedata(pipe)	(((pipe) >> 19) & 1)
+#define usb_pipespeed(pipe)	(((pipe) >> 26) & 3)
+#define usb_pipeslow(pipe)	(usb_pipespeed(pipe) == USB_SPEED_LOW)
+#define usb_pipetype(pipe)	(((pipe) >> 30) & 3)
+#define usb_pipeisoc(pipe)	(usb_pipetype((pipe)) == PIPE_ISOCHRONOUS)
+#define usb_pipeint(pipe)	(usb_pipetype((pipe)) == PIPE_INTERRUPT)
+#define usb_pipecontrol(pipe)	(usb_pipetype((pipe)) == PIPE_CONTROL)
+#define usb_pipebulk(pipe)	(usb_pipetype((pipe)) == PIPE_BULK)
+
+
+/*************************************************************************
+ * Hub Stuff
+ */
+struct usb_port_status {
+	unsigned short wPortStatus;
+	unsigned short wPortChange;
+} __attribute__ ((packed));
+
+struct usb_hub_status {
+	unsigned short wHubStatus;
+	unsigned short wHubChange;
+} __attribute__ ((packed));
+
+
+/* Hub descriptor */
+struct usb_hub_descriptor {
+	unsigned char  bLength;
+	unsigned char  bDescriptorType;
+	unsigned char  bNbrPorts;
+	unsigned short wHubCharacteristics;
+	unsigned char  bPwrOn2PwrGood;
+	unsigned char  bHubContrCurrent;
+	unsigned char  DeviceRemovable[(USB_MAXCHILDREN+1+7)/8];
+	unsigned char  PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8];
+		/* DeviceRemovable and PortPwrCtrlMask want to be variable-length
+	   bitmaps that hold max 255 entries. (bit0 is ignored) */
+} __attribute__ ((packed));
+
+
+struct usb_hub_device {
+	struct usb_device *pusb_dev;
+	struct usb_hub_descriptor desc;
+};
+
+#endif /*_USB_H_ */
diff --git a/include/usb_defs.h b/include/usb_defs.h
new file mode 100755
index 0000000..7c47408
--- /dev/null
+++ b/include/usb_defs.h
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+#ifndef _USB_DEFS_H_
+#define _USB_DEFS_H_
+
+/* USB constants */
+
+/* Device and/or Interface Class codes */
+#define USB_CLASS_PER_INTERFACE  0	/* for DeviceClass */
+#define USB_CLASS_AUDIO          1
+#define USB_CLASS_COMM           2
+#define USB_CLASS_HID            3
+#define USB_CLASS_PRINTER	       7
+#define USB_CLASS_MASS_STORAGE   8
+#define USB_CLASS_HUB            9
+#define USB_CLASS_DATA           10
+#define USB_CLASS_VENDOR_SPEC    0xff
+
+/* some HID sub classes */
+#define USB_SUB_HID_NONE        0
+#define USB_SUB_HID_BOOT        1
+
+/* some UID Protocols */
+#define USB_PROT_HID_NONE       0
+#define USB_PROT_HID_KEYBOARD   1
+#define USB_PROT_HID_MOUSE      2
+
+
+/* Sub STORAGE Classes */
+#define US_SC_RBC              1		/* Typically, flash devices */
+#define US_SC_8020             2		/* CD-ROM */
+#define US_SC_QIC              3		/* QIC-157 Tapes */
+#define US_SC_UFI              4		/* Floppy */
+#define US_SC_8070             5		/* Removable media */
+#define US_SC_SCSI             6		/* Transparent */
+#define US_SC_MIN              US_SC_RBC
+#define US_SC_MAX              US_SC_SCSI
+
+/* STORAGE Protocols */
+#define US_PR_CB               1		/* Control/Bulk w/o interrupt */
+#define US_PR_CBI              0		/* Control/Bulk/Interrupt */
+#define US_PR_BULK             0x50		/* bulk only */
+
+/* USB types */
+#define USB_TYPE_STANDARD   (0x00 << 5)
+#define USB_TYPE_CLASS      (0x01 << 5)
+#define USB_TYPE_VENDOR     (0x02 << 5)
+#define USB_TYPE_RESERVED   (0x03 << 5)
+
+/* USB recipients */
+#define USB_RECIP_DEVICE      0x00
+#define USB_RECIP_INTERFACE   0x01
+#define USB_RECIP_ENDPOINT    0x02
+#define USB_RECIP_OTHER       0x03
+
+/* USB directions */
+#define USB_DIR_OUT           0
+#define USB_DIR_IN            0x80
+//Charles
+/* USB device speeds */
+#define USB_SPEED_FULL		0x0	/* 12Mbps */
+#define USB_SPEED_LOW		0x1	/* 1.5Mbps */
+#define USB_SPEED_HIGH		0x2	/* 480Mbps */
+#define USB_SPEED_RESERVED	0x3
+
+
+/* Descriptor types */
+#define USB_DT_DEVICE        0x01
+#define USB_DT_CONFIG        0x02
+#define USB_DT_STRING        0x03
+#define USB_DT_INTERFACE     0x04
+#define USB_DT_ENDPOINT      0x05
+
+#define USB_DT_HID          (USB_TYPE_CLASS | 0x01)
+#define USB_DT_REPORT       (USB_TYPE_CLASS | 0x02)
+#define USB_DT_PHYSICAL     (USB_TYPE_CLASS | 0x03)
+#define USB_DT_HUB          (USB_TYPE_CLASS | 0x09)
+
+/* Descriptor sizes per descriptor type */
+#define USB_DT_DEVICE_SIZE      18
+#define USB_DT_CONFIG_SIZE      9
+#define USB_DT_INTERFACE_SIZE   9
+#define USB_DT_ENDPOINT_SIZE    7
+#define USB_DT_ENDPOINT_AUDIO_SIZE  9	/* Audio extension */
+#define USB_DT_HUB_NONVAR_SIZE  7
+#define USB_DT_HID_SIZE         9
+
+/* Endpoints */
+#define USB_ENDPOINT_NUMBER_MASK  0x0f	/* in bEndpointAddress */
+#define USB_ENDPOINT_DIR_MASK     0x80
+
+#define USB_ENDPOINT_XFERTYPE_MASK 0x03	/* in bmAttributes */
+#define USB_ENDPOINT_XFER_CONTROL  0
+#define USB_ENDPOINT_XFER_ISOC     1
+#define USB_ENDPOINT_XFER_BULK     2
+#define USB_ENDPOINT_XFER_INT      3
+
+/* USB Packet IDs (PIDs) */
+#define USB_PID_UNDEF_0             0xf0
+#define USB_PID_OUT                 0xe1
+#define USB_PID_ACK                 0xd2
+#define USB_PID_DATA0               0xc3
+#define USB_PID_UNDEF_4             0xb4
+#define USB_PID_SOF                 0xa5
+#define USB_PID_UNDEF_6             0x96
+#define USB_PID_UNDEF_7             0x87
+#define USB_PID_UNDEF_8             0x78
+#define USB_PID_IN                  0x69
+#define USB_PID_NAK                 0x5a
+#define USB_PID_DATA1               0x4b
+#define USB_PID_PREAMBLE            0x3c
+#define USB_PID_SETUP               0x2d
+#define USB_PID_STALL               0x1e
+#define USB_PID_UNDEF_F             0x0f
+
+/* Standard requests */
+#define USB_REQ_GET_STATUS          0x00
+#define USB_REQ_CLEAR_FEATURE       0x01
+#define USB_REQ_SET_FEATURE         0x03
+#define USB_REQ_SET_ADDRESS         0x05
+#define USB_REQ_GET_DESCRIPTOR      0x06
+#define USB_REQ_SET_DESCRIPTOR      0x07
+#define USB_REQ_GET_CONFIGURATION   0x08
+#define USB_REQ_SET_CONFIGURATION   0x09
+#define USB_REQ_GET_INTERFACE       0x0A
+#define USB_REQ_SET_INTERFACE       0x0B
+#define USB_REQ_SYNCH_FRAME         0x0C
+
+/* HID requests */
+#define USB_REQ_GET_REPORT          0x01
+#define USB_REQ_GET_IDLE            0x02
+#define USB_REQ_GET_PROTOCOL        0x03
+#define USB_REQ_SET_REPORT          0x09
+#define USB_REQ_SET_IDLE            0x0A
+#define USB_REQ_SET_PROTOCOL        0x0B
+
+
+/* "pipe" definitions */
+
+#define PIPE_ISOCHRONOUS    0
+#define PIPE_INTERRUPT      1
+#define PIPE_CONTROL        2
+#define PIPE_BULK           3
+#define PIPE_DEVEP_MASK     0x0007ff00
+
+#define USB_ISOCHRONOUS    0
+#define USB_INTERRUPT      1
+#define USB_CONTROL        2
+#define USB_BULK           3
+
+/* USB-status codes: */
+#define USB_ST_ACTIVE           0x1		/* TD is active */
+#define USB_ST_STALLED          0x2		/* TD is stalled */
+#define USB_ST_BUF_ERR          0x4		/* buffer error */
+#define USB_ST_BABBLE_DET       0x8		/* Babble detected */
+#define USB_ST_NAK_REC          0x10	/* NAK Received*/
+#define USB_ST_CRC_ERR          0x20	/* CRC/timeout Error */
+#define USB_ST_BIT_ERR          0x40	/* Bitstuff error */
+#define USB_ST_NOT_PROC         0x80000000L	/* Not yet processed */
+
+
+/*************************************************************************
+ * Hub defines
+ */
+
+/*
+ * Hub request types
+ */
+
+#define USB_RT_HUB	(USB_TYPE_CLASS | USB_RECIP_DEVICE)
+#define USB_RT_PORT	(USB_TYPE_CLASS | USB_RECIP_OTHER)
+
+/*
+ * Hub Class feature numbers
+ */
+#define C_HUB_LOCAL_POWER   0
+#define C_HUB_OVER_CURRENT  1
+
+/*
+ * Port feature numbers
+ */
+#define USB_PORT_FEAT_CONNECTION     0
+#define USB_PORT_FEAT_ENABLE         1
+#define USB_PORT_FEAT_SUSPEND        2
+#define USB_PORT_FEAT_OVER_CURRENT   3
+#define USB_PORT_FEAT_RESET          4
+#define USB_PORT_FEAT_POWER          8
+#define USB_PORT_FEAT_LOWSPEED       9
+#define USB_PORT_FEAT_C_CONNECTION   16
+#define USB_PORT_FEAT_C_ENABLE       17
+#define USB_PORT_FEAT_C_SUSPEND      18
+#define USB_PORT_FEAT_C_OVER_CURRENT 19
+#define USB_PORT_FEAT_C_RESET        20
+
+/* wPortStatus bits */
+#define USB_PORT_STAT_CONNECTION    0x0001
+#define USB_PORT_STAT_ENABLE        0x0002
+#define USB_PORT_STAT_SUSPEND       0x0004
+#define USB_PORT_STAT_OVERCURRENT   0x0008
+#define USB_PORT_STAT_RESET         0x0010
+#define USB_PORT_STAT_POWER         0x0100
+#define USB_PORT_STAT_LOW_SPEED     0x0200
+#define USB_PORT_STAT_HIGH_SPEED    0x0400	/* support for EHCI */
+#define USB_PORT_STAT_SPEED	\
+	(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED)
+
+/* wPortChange bits */
+#define USB_PORT_STAT_C_CONNECTION  0x0001
+#define USB_PORT_STAT_C_ENABLE      0x0002
+#define USB_PORT_STAT_C_SUSPEND     0x0004
+#define USB_PORT_STAT_C_OVERCURRENT 0x0008
+#define USB_PORT_STAT_C_RESET       0x0010
+
+/* wHubCharacteristics (masks) */
+#define HUB_CHAR_LPSM               0x0003
+#define HUB_CHAR_COMPOUND           0x0004
+#define HUB_CHAR_OCPM               0x0018
+
+/*
+ *Hub Status & Hub Change bit masks
+ */
+#define HUB_STATUS_LOCAL_POWER	0x0001
+#define HUB_STATUS_OVERCURRENT	0x0002
+
+#define HUB_CHANGE_LOCAL_POWER	0x0001
+#define HUB_CHANGE_OVERCURRENT	0x0002
+
+#endif /*_USB_DEFS_H_ */
diff --git a/include/usb_ether.h b/include/usb_ether.h
new file mode 100755
index 0000000..fd54156
--- /dev/null
+++ b/include/usb_ether.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __USB_ETHER_H__
+#define __USB_ETHER_H__
+
+#include <net.h>
+
+/*
+ *	IEEE 802.3 Ethernet magic constants.  The frame sizes omit the preamble
+ *	and FCS/CRC (frame check sequence).
+ */
+#define ETH_ALEN	6		/* Octets in one ethernet addr	 */
+#define ETH_HLEN	14		/* Total octets in header.	 */
+#define ETH_ZLEN	60		/* Min. octets in frame sans FCS */
+#define ETH_DATA_LEN	1500		/* Max. octets in payload	 */
+#define ETH_FRAME_LEN	PKTSIZE_ALIGN	/* Max. octets in frame sans FCS */
+#define ETH_FCS_LEN	4		/* Octets in the FCS		 */
+
+struct ueth_data {
+	/* eth info */
+	struct eth_device eth_dev;		/* used with eth_register */
+	int phy_id;						/* mii phy id */
+
+	/* usb info */
+	struct usb_device *pusb_dev;	/* this usb_device */
+	unsigned char	ifnum;			/* interface number */
+	unsigned char	ep_in;			/* in endpoint */
+	unsigned char	ep_out;			/* out ....... */
+	unsigned char	ep_int;			/* interrupt . */
+	unsigned char	subclass;		/* as in overview */
+	unsigned char	protocol;		/* .............. */
+	unsigned char	irqinterval;	/* Intervall for IRQ Pipe */
+
+	/* private fields for each driver can go here if needed */
+#ifdef CONFIG_USB_ETHER_SMSC95XX
+	size_t rx_urb_size;  /* maximum USB URB size */
+	u32 mac_cr;  /* MAC control register value */
+	int have_hwaddr;  /* 1 if we have a hardware MAC address */
+#endif
+};
+
+/*
+ * Function definitions for each USB ethernet driver go here, bracketed by
+ * #ifdef CONFIG_USB_ETHER_xxx...#endif
+ */
+#ifdef CONFIG_USB_ETHER_ASIX
+void asix_eth_before_probe(void);
+int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
+		      struct ueth_data *ss);
+int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+		      struct eth_device *eth);
+#endif
+
+#ifdef CONFIG_USB_ETHER_RTL8152
+void rtl8152_eth_before_probe(void);
+int rtl8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
+		      struct ueth_data *ss);
+int rtl8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+		      struct eth_device *eth);
+#endif
+
+
+#ifdef CONFIG_USB_ETHER_SMSC95XX
+void smsc95xx_eth_before_probe(void);
+int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
+			struct ueth_data *ss);
+int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+			struct eth_device *eth);
+#endif
+
+#endif /* __USB_ETHER_H__ */
diff --git a/include/usbdcore.h b/include/usbdcore.h
new file mode 100755
index 0000000..3dd9c8b
--- /dev/null
+++ b/include/usbdcore.h
@@ -0,0 +1,674 @@
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ *
+ * Based on linux/drivers/usbd/usbd.h
+ *
+ * Copyright (c) 2000, 2001, 2002 Lineo
+ * Copyright (c) 2001 Hewlett Packard
+ *
+ * By:
+ *	Stuart Lynne <sl@lineo.com>,
+ *	Tom Rushworth <tbr@lineo.com>,
+ *	Bruce Balden <balden@lineo.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __USBDCORE_H__
+#define __USBDCORE_H__
+
+#include <common.h>
+#include "usbdescriptors.h"
+
+
+#define MAX_URBS_QUEUED 5
+
+
+#if 1
+#define usberr(fmt,args...) serial_printf("ERROR: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args)
+#else
+#define usberr(fmt,args...) do{}while(0)
+#endif
+
+#if 0
+#define usbdbg(fmt,args...) serial_printf("debug: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args)
+#else
+#define usbdbg(fmt,args...) do{}while(0)
+#endif
+
+#if 0
+#define usbinfo(fmt,args...) serial_printf("info: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args)
+#else
+#define usbinfo(fmt,args...) do{}while(0)
+#endif
+
+#ifndef le16_to_cpu
+#define le16_to_cpu(x)	(x)
+#endif
+
+#ifndef inb
+#define inb(p)	     (*(volatile u8*)(p))
+#endif
+
+#ifndef outb
+#define outb(val,p)  (*(volatile u8*)(p) = (val))
+#endif
+
+#ifndef inw
+#define inw(p)	     (*(volatile u16*)(p))
+#endif
+
+#ifndef outw
+#define outw(val,p)  (*(volatile u16*)(p) = (val))
+#endif
+
+#ifndef inl
+#define inl(p)	     (*(volatile u32*)(p))
+#endif
+
+#ifndef outl
+#define outl(val,p)  (*(volatile u32*)(p) = (val))
+#endif
+
+#ifndef insw
+#define insw(p,to,len)	   mmio_insw(p,to,len)
+#endif
+
+#ifndef outsw
+#define outsw(p,from,len)  mmio_outsw(p,from,len)
+#endif
+
+#ifndef insb
+#define insb(p,to,len)	   mmio_insb(p,to,len)
+#endif
+
+#ifndef mmio_insw
+#define mmio_insw(r,b,l)	({	int __i ;  \
+					u16 *__b2;  \
+					__b2 = (u16 *) b;  \
+					for (__i = 0; __i < l; __i++) {	 \
+					  *(__b2 + __i) = inw(r);  \
+					};  \
+				})
+#endif
+
+#ifndef mmio_outsw
+#define mmio_outsw(r,b,l)	({	int __i; \
+					u16 *__b2; \
+					__b2 = (u16 *) b; \
+					for (__i = 0; __i < l; __i++) { \
+					    outw( *(__b2 + __i), r); \
+					} \
+				})
+#endif
+
+#ifndef mmio_insb
+#define mmio_insb(r,b,l)	({	int __i ;  \
+					u8 *__b2;  \
+					__b2 = (u8 *) b;  \
+					for (__i = 0; __i < l; __i++) {	 \
+					  *(__b2 + __i) = inb(r);  \
+					};  \
+				})
+#endif
+
+#ifndef MIN
+#define MIN(a,b) ((a) < (b) ? (a) : (b))
+#endif
+#ifndef MAX
+#define MAX(a,b) ((a) > (b) ? (a) : (b))
+#endif
+
+
+/*
+ * Structure member address manipulation macros.
+ * These are used by client code (code using the urb_link routines), since
+ * the urb_link structure is embedded in the client data structures.
+ *
+ * Note: a macro offsetof equivalent to member_offset is defined in stddef.h
+ *	 but this is kept here for the sake of portability.
+ *
+ * p2surround returns a pointer to the surrounding structure given
+ * type of the surrounding structure, the name memb of the structure
+ * member pointed at by ptr.  For example, if you have:
+ *
+ *	struct foo {
+ *	    int x;
+ *	    float y;
+ *	    char z;
+ *	} thingy;
+ *
+ *	char *cp = &thingy.z;
+ *
+ * then
+ *
+ *	&thingy == p2surround(struct foo, z, cp)
+ *
+ * Clear?
+ */
+#define _cv_(ptr)		  ((char*)(void*)(ptr))
+#define member_offset(type,memb)  (_cv_(&(((type*)0)->memb))-(char*)0)
+#define p2surround(type,memb,ptr) ((type*)(void*)(_cv_(ptr)-member_offset(type,memb)))
+
+struct urb;
+
+struct usb_endpoint_instance;
+struct usb_interface_instance;
+struct usb_configuration_instance;
+struct usb_device_instance;
+struct usb_bus_instance;
+
+/*
+ * Device and/or Interface Class codes
+ */
+#define USB_CLASS_PER_INTERFACE		0	/* for DeviceClass */
+#define USB_CLASS_AUDIO			1
+#define USB_CLASS_COMM			2
+#define USB_CLASS_HID			3
+#define USB_CLASS_PHYSICAL		5
+#define USB_CLASS_PRINTER		7
+#define USB_CLASS_MASS_STORAGE		8
+#define USB_CLASS_HUB			9
+#define USB_CLASS_DATA			10
+#define USB_CLASS_APP_SPEC		0xfe
+#define USB_CLASS_VENDOR_SPEC		0xff
+
+/*
+ * USB types
+ */
+#define USB_TYPE_STANDARD		(0x00 << 5)
+#define USB_TYPE_CLASS			(0x01 << 5)
+#define USB_TYPE_VENDOR			(0x02 << 5)
+#define USB_TYPE_RESERVED		(0x03 << 5)
+
+/*
+ * USB recipients
+ */
+#define USB_RECIP_DEVICE		0x00
+#define USB_RECIP_INTERFACE		0x01
+#define USB_RECIP_ENDPOINT		0x02
+#define USB_RECIP_OTHER			0x03
+
+/*
+ * USB directions
+ */
+#define USB_DIR_OUT			0
+#define USB_DIR_IN			0x80
+
+/*
+ * Descriptor types
+ */
+#define USB_DT_DEVICE			0x01
+#define USB_DT_CONFIG			0x02
+#define USB_DT_STRING			0x03
+#define USB_DT_INTERFACE		0x04
+#define USB_DT_ENDPOINT			0x05
+
+#define USB_DT_HID			(USB_TYPE_CLASS | 0x01)
+#define USB_DT_REPORT			(USB_TYPE_CLASS | 0x02)
+#define USB_DT_PHYSICAL			(USB_TYPE_CLASS | 0x03)
+#define USB_DT_HUB			(USB_TYPE_CLASS | 0x09)
+
+/*
+ * Descriptor sizes per descriptor type
+ */
+#define USB_DT_DEVICE_SIZE		18
+#define USB_DT_CONFIG_SIZE		9
+#define USB_DT_INTERFACE_SIZE		9
+#define USB_DT_ENDPOINT_SIZE		7
+#define USB_DT_ENDPOINT_AUDIO_SIZE	9	/* Audio extension */
+#define USB_DT_HUB_NONVAR_SIZE		7
+#define USB_DT_HID_SIZE			9
+
+/*
+ * Endpoints
+ */
+#define USB_ENDPOINT_NUMBER_MASK	0x0f	/* in bEndpointAddress */
+#define USB_ENDPOINT_DIR_MASK		0x80
+
+#define USB_ENDPOINT_XFERTYPE_MASK	0x03	/* in bmAttributes */
+#define USB_ENDPOINT_XFER_CONTROL	0
+#define USB_ENDPOINT_XFER_ISOC		1
+#define USB_ENDPOINT_XFER_BULK		2
+#define USB_ENDPOINT_XFER_INT		3
+
+/*
+ * USB Packet IDs (PIDs)
+ */
+#define USB_PID_UNDEF_0			       0xf0
+#define USB_PID_OUT			       0xe1
+#define USB_PID_ACK			       0xd2
+#define USB_PID_DATA0			       0xc3
+#define USB_PID_PING			       0xb4	/* USB 2.0 */
+#define USB_PID_SOF			       0xa5
+#define USB_PID_NYET			       0x96	/* USB 2.0 */
+#define USB_PID_DATA2			       0x87	/* USB 2.0 */
+#define USB_PID_SPLIT			       0x78	/* USB 2.0 */
+#define USB_PID_IN			       0x69
+#define USB_PID_NAK			       0x5a
+#define USB_PID_DATA1			       0x4b
+#define USB_PID_PREAMBLE		       0x3c	/* Token mode */
+#define USB_PID_ERR			       0x3c	/* USB 2.0: handshake mode */
+#define USB_PID_SETUP			       0x2d
+#define USB_PID_STALL			       0x1e
+#define USB_PID_MDATA			       0x0f	/* USB 2.0 */
+
+/*
+ * Standard requests
+ */
+#define USB_REQ_GET_STATUS		0x00
+#define USB_REQ_CLEAR_FEATURE		0x01
+#define USB_REQ_SET_FEATURE		0x03
+#define USB_REQ_SET_ADDRESS		0x05
+#define USB_REQ_GET_DESCRIPTOR		0x06
+#define USB_REQ_SET_DESCRIPTOR		0x07
+#define USB_REQ_GET_CONFIGURATION	0x08
+#define USB_REQ_SET_CONFIGURATION	0x09
+#define USB_REQ_GET_INTERFACE		0x0A
+#define USB_REQ_SET_INTERFACE		0x0B
+#define USB_REQ_SYNCH_FRAME		0x0C
+
+#define USBD_DEVICE_REQUESTS(x) (((unsigned int)x <= USB_REQ_SYNCH_FRAME) ? usbd_device_requests[x] : "UNKNOWN")
+
+/*
+ * HID requests
+ */
+#define USB_REQ_GET_REPORT		0x01
+#define USB_REQ_GET_IDLE		0x02
+#define USB_REQ_GET_PROTOCOL		0x03
+#define USB_REQ_SET_REPORT		0x09
+#define USB_REQ_SET_IDLE		0x0A
+#define USB_REQ_SET_PROTOCOL		0x0B
+
+
+/*
+ * USB Spec Release number
+ */
+
+#define USB_BCD_VERSION			0x0110
+
+
+/*
+ * Device Requests	(c.f Table 9-2)
+ */
+
+#define USB_REQ_DIRECTION_MASK		0x80
+#define USB_REQ_TYPE_MASK		0x60
+#define USB_REQ_RECIPIENT_MASK		0x1f
+
+#define USB_REQ_DEVICE2HOST		0x80
+#define USB_REQ_HOST2DEVICE		0x00
+
+#define USB_REQ_TYPE_STANDARD		0x00
+#define USB_REQ_TYPE_CLASS		0x20
+#define USB_REQ_TYPE_VENDOR		0x40
+
+#define USB_REQ_RECIPIENT_DEVICE	0x00
+#define USB_REQ_RECIPIENT_INTERFACE	0x01
+#define USB_REQ_RECIPIENT_ENDPOINT	0x02
+#define USB_REQ_RECIPIENT_OTHER		0x03
+
+/*
+ * get status bits
+ */
+
+#define USB_STATUS_SELFPOWERED		0x01
+#define USB_STATUS_REMOTEWAKEUP		0x02
+
+#define USB_STATUS_HALT			0x01
+
+/*
+ * descriptor types
+ */
+
+#define USB_DESCRIPTOR_TYPE_DEVICE			0x01
+#define USB_DESCRIPTOR_TYPE_CONFIGURATION		0x02
+#define USB_DESCRIPTOR_TYPE_STRING			0x03
+#define USB_DESCRIPTOR_TYPE_INTERFACE			0x04
+#define USB_DESCRIPTOR_TYPE_ENDPOINT			0x05
+#define USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER		0x06
+#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION	0x07
+#define USB_DESCRIPTOR_TYPE_INTERFACE_POWER		0x08
+#define USB_DESCRIPTOR_TYPE_HID				0x21
+#define USB_DESCRIPTOR_TYPE_REPORT			0x22
+
+#define USBD_DEVICE_DESCRIPTORS(x) (((unsigned int)x <= USB_DESCRIPTOR_TYPE_INTERFACE_POWER) ? \
+		usbd_device_descriptors[x] : "UNKNOWN")
+
+/*
+ * standard feature selectors
+ */
+#define USB_ENDPOINT_HALT		0x00
+#define USB_DEVICE_REMOTE_WAKEUP	0x01
+#define USB_TEST_MODE			0x02
+
+
+/* USB Requests
+ *
+ */
+
+struct usb_device_request {
+	u8 bmRequestType;
+	u8 bRequest;
+	u16 wValue;
+	u16 wIndex;
+	u16 wLength;
+} __attribute__ ((packed));
+
+
+/* USB Status
+ *
+ */
+typedef enum urb_send_status {
+	SEND_IN_PROGRESS,
+	SEND_FINISHED_OK,
+	SEND_FINISHED_ERROR,
+	RECV_READY,
+	RECV_OK,
+	RECV_ERROR
+} urb_send_status_t;
+
+/*
+ * Device State (c.f USB Spec 2.0 Figure 9-1)
+ *
+ * What state the usb device is in.
+ *
+ * Note the state does not change if the device is suspended, we simply set a
+ * flag to show that it is suspended.
+ *
+ */
+typedef enum usb_device_state {
+	STATE_INIT,		/* just initialized */
+	STATE_CREATED,		/* just created */
+	STATE_ATTACHED,		/* we are attached */
+	STATE_POWERED,		/* we have seen power indication (electrical bus signal) */
+	STATE_DEFAULT,		/* we been reset */
+	STATE_ADDRESSED,	/* we have been addressed (in default configuration) */
+	STATE_CONFIGURED,	/* we have seen a set configuration device command */
+	STATE_UNKNOWN,		/* destroyed */
+} usb_device_state_t;
+
+#define USBD_DEVICE_STATE(x) (((unsigned int)x <= STATE_UNKNOWN) ? usbd_device_states[x] : "UNKNOWN")
+
+/*
+ * Device status
+ *
+ * Overall state
+ */
+typedef enum usb_device_status {
+	USBD_OPENING,		/* we are currently opening */
+	USBD_OK,		/* ok to use */
+	USBD_SUSPENDED,		/* we are currently suspended */
+	USBD_CLOSING,		/* we are currently closing */
+} usb_device_status_t;
+
+#define USBD_DEVICE_STATUS(x) (((unsigned int)x <= USBD_CLOSING) ? usbd_device_status[x] : "UNKNOWN")
+
+/*
+ * Device Events
+ *
+ * These are defined in the USB Spec (c.f USB Spec 2.0 Figure 9-1).
+ *
+ * There are additional events defined to handle some extra actions we need
+ * to have handled.
+ *
+ */
+typedef enum usb_device_event {
+
+	DEVICE_UNKNOWN,		/* bi - unknown event */
+	DEVICE_INIT,		/* bi  - initialize */
+	DEVICE_CREATE,		/* bi  - */
+	DEVICE_HUB_CONFIGURED,	/* bi  - bus has been plugged int */
+	DEVICE_RESET,		/* bi  - hub has powered our port */
+
+	DEVICE_ADDRESS_ASSIGNED,	/* ep0 - set address setup received */
+	DEVICE_CONFIGURED,	/* ep0 - set configure setup received */
+	DEVICE_SET_INTERFACE,	/* ep0 - set interface setup received */
+
+	DEVICE_SET_FEATURE,	/* ep0 - set feature setup received */
+	DEVICE_CLEAR_FEATURE,	/* ep0 - clear feature setup received */
+
+	DEVICE_DE_CONFIGURED,	/* ep0 - set configure setup received for ?? */
+
+	DEVICE_BUS_INACTIVE,	/* bi  - bus in inactive (no SOF packets) */
+	DEVICE_BUS_ACTIVITY,	/* bi  - bus is active again */
+
+	DEVICE_POWER_INTERRUPTION,	/* bi  - hub has depowered our port */
+	DEVICE_HUB_RESET,	/* bi  - bus has been unplugged */
+	DEVICE_DESTROY,		/* bi  - device instance should be destroyed */
+
+	DEVICE_HOTPLUG,		/* bi  - a hotplug event has occured */
+
+	DEVICE_FUNCTION_PRIVATE,	/* function - private */
+
+} usb_device_event_t;
+
+
+typedef struct urb_link {
+	struct urb_link *next;
+	struct urb_link *prev;
+} urb_link;
+
+/* USB Data structure - for passing data around.
+ *
+ * This is used for both sending and receiving data.
+ *
+ * The callback function is used to let the function driver know when
+ * transmitted data has been sent.
+ *
+ * The callback function is set by the alloc_recv function when an urb is
+ * allocated for receiving data for an endpoint and used to call the
+ * function driver to inform it that data has arrived.
+ */
+
+#define URB_BUF_SIZE 128 /* in linux we'd malloc this, but in u-boot we prefer static data */
+struct urb {
+
+	struct usb_endpoint_instance *endpoint;
+	struct usb_device_instance *device;
+
+	struct usb_device_request device_request;	/* contents of received SETUP packet */
+
+	struct urb_link link;	/* embedded struct for circular doubly linked list of urbs */
+
+	u8* buffer;
+	unsigned int buffer_length;
+	unsigned int actual_length;
+
+	urb_send_status_t status;
+	int data;
+
+	u16 buffer_data[URB_BUF_SIZE];	/* data received (OUT) or being sent (IN) */
+};
+
+/* Endpoint configuration
+ *
+ * Per endpoint configuration data. Used to track which function driver owns
+ * an endpoint.
+ *
+ */
+struct usb_endpoint_instance {
+	int endpoint_address;	/* logical endpoint address */
+
+	/* control */
+	int status;		/* halted */
+	int state;		/* available for use by bus interface driver */
+
+	/* receive side */
+	struct urb_link rcv;	/* received urbs */
+	struct urb_link rdy;	/* empty urbs ready to receive */
+	struct urb *rcv_urb;	/* active urb */
+	int rcv_attributes;	/* copy of bmAttributes from endpoint descriptor */
+	int rcv_packetSize;	/* maximum packet size from endpoint descriptor */
+	int rcv_transferSize;	/* maximum transfer size from function driver */
+	int rcv_queue;
+
+	/* transmit side */
+	struct urb_link tx;	/* urbs ready to transmit */
+	struct urb_link done;	/* transmitted urbs */
+	struct urb *tx_urb;	/* active urb */
+	int tx_attributes;	/* copy of bmAttributes from endpoint descriptor */
+	int tx_packetSize;	/* maximum packet size from endpoint descriptor */
+	int tx_transferSize;	/* maximum transfer size from function driver */
+	int tx_queue;
+
+	int sent;		/* data already sent */
+	int last;		/* data sent in last packet XXX do we need this */
+};
+
+struct usb_alternate_instance {
+	struct usb_interface_descriptor *interface_descriptor;
+
+	int endpoints;
+	int *endpoint_transfersize_array;
+	struct usb_endpoint_descriptor **endpoints_descriptor_array;
+};
+
+struct usb_interface_instance {
+	int alternates;
+	struct usb_alternate_instance *alternates_instance_array;
+};
+
+struct usb_configuration_instance {
+	int interfaces;
+	struct usb_configuration_descriptor *configuration_descriptor;
+	struct usb_interface_instance *interface_instance_array;
+};
+
+
+/* USB Device Instance
+ *
+ * For each physical bus interface we create a logical device structure. This
+ * tracks all of the required state to track the USB HOST's view of the device.
+ *
+ * Keep track of the device configuration for a real physical bus interface,
+ * this includes the bus interface, multiple function drivers, the current
+ * configuration and the current state.
+ *
+ * This will show:
+ *	the specific bus interface driver
+ *	the default endpoint 0 driver
+ *	the configured function driver
+ *	device state
+ *	device status
+ *	endpoint list
+ */
+
+struct usb_device_instance {
+
+	/* generic */
+	char *name;
+	struct usb_device_descriptor *device_descriptor;	/* per device descriptor */
+
+	void (*event) (struct usb_device_instance *device, usb_device_event_t event, int data);
+	/* Do cdc device specific control requests */
+	
+	int (*cdc_recv_setup)(struct usb_device_request *request, struct urb *urb);
+	
+	/* bus interface */
+	struct usb_bus_instance *bus;	/* which bus interface driver */
+
+	/* configuration descriptors */
+	int configurations;
+	struct usb_configuration_instance *configuration_instance_array;
+
+	/* device state */
+	usb_device_state_t device_state;	/* current USB Device state */
+	usb_device_state_t device_previous_state;	/* current USB Device state */
+
+	u8 address;		/* current address (zero is default) */
+	u8 configuration;	/* current show configuration (zero is default) */
+	u8 interface;		/* current interface (zero is default) */
+	u8 alternate;		/* alternate flag */
+
+	usb_device_status_t status;	/* device status */
+
+	int urbs_queued;	/* number of submitted urbs */
+
+	/* Shouldn't need to make this atomic, all we need is a change indicator */
+	unsigned long usbd_rxtx_timestamp;
+	unsigned long usbd_last_rxtx_timestamp;
+	unsigned int speed;
+};
+
+/* Bus Interface configuration structure
+ *
+ * This is allocated for each configured instance of a bus interface driver.
+ *
+ * The privdata pointer may be used by the bus interface driver to store private
+ * per instance state information.
+ */
+struct usb_bus_instance {
+
+	struct usb_device_instance *device;
+	struct usb_endpoint_instance *endpoint_array;	/* array of available configured endpoints */
+
+	int max_endpoints;	/* maximimum number of rx enpoints */
+	unsigned char			maxpacketsize;
+
+	unsigned int serial_number;
+	char *serial_number_str;
+	void *privdata;		/* private data for the bus interface */
+
+};
+
+extern char *usbd_device_events[];
+extern char *usbd_device_states[];
+extern char *usbd_device_status[];
+extern char *usbd_device_requests[];
+extern char *usbd_device_descriptors[];
+
+void urb_link_init (urb_link * ul);
+void urb_detach (struct urb *urb);
+urb_link *first_urb_link (urb_link * hd);
+struct urb *first_urb (urb_link * hd);
+struct urb *first_urb_detached (urb_link * hd);
+void urb_append (urb_link * hd, struct urb *urb);
+
+struct urb *usbd_alloc_urb (struct usb_device_instance *device, struct usb_endpoint_instance *endpoint);
+void	    usbd_dealloc_urb (struct urb *urb);
+
+/*
+ * usbd_device_event is used by bus interface drivers to tell the higher layers that
+ * certain events have taken place.
+ */
+void usbd_device_event_irq (struct usb_device_instance *conf, usb_device_event_t, int);
+void usbd_device_event (struct usb_device_instance *conf, usb_device_event_t, int);
+
+/* descriptors
+ *
+ * Various ways of finding descriptors based on the current device and any
+ * possible configuration / interface / endpoint for it.
+ */
+struct usb_configuration_descriptor *usbd_device_configuration_descriptor (struct usb_device_instance *, int, int);
+struct usb_function_instance *usbd_device_function_instance (struct usb_device_instance *, unsigned int);
+struct usb_interface_instance *usbd_device_interface_instance (struct usb_device_instance *, int, int, int);
+struct usb_alternate_instance *usbd_device_alternate_instance (struct usb_device_instance *, int, int, int, int);
+struct usb_interface_descriptor *usbd_device_interface_descriptor (struct usb_device_instance *, int, int, int, int);
+struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor_index (struct usb_device_instance *, int, int, int, int, int);
+struct usb_class_descriptor *usbd_device_class_descriptor_index (struct usb_device_instance *, int, int, int, int, int);
+struct usb_class_report_descriptor *usbd_device_class_report_descriptor_index( struct usb_device_instance *, int , int , int , int , int );
+struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor (struct usb_device_instance *, int, int, int, int, int);
+int				usbd_device_endpoint_transfersize (struct usb_device_instance *, int, int, int, int, int);
+struct usb_string_descriptor *usbd_get_string (u8);
+struct usb_device_descriptor *usbd_device_device_descriptor (struct usb_device_instance *, int);
+
+int usbd_endpoint_halted (struct usb_device_instance *device, int endpoint);
+void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad);
+void usbd_tx_complete (struct usb_endpoint_instance *endpoint);
+
+#endif
diff --git a/include/usbdcore_ep0.h b/include/usbdcore_ep0.h
new file mode 100755
index 0000000..3bec106
--- /dev/null
+++ b/include/usbdcore_ep0.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ *
+ * Based on
+ * linux/drivers/usbd/ep0.c
+ *
+ * Copyright (c) 2000, 2001, 2002 Lineo
+ * Copyright (c) 2001 Hewlett Packard
+ *
+ * By:
+ *	Stuart Lynne <sl@lineo.com>,
+ *	Tom Rushworth <tbr@lineo.com>,
+ *	Bruce Balden <balden@lineo.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __USBDCORE_EP0_H__
+#define __USBDCORE_EP0_H__
+
+
+int ep0_recv_setup (struct urb *urb);
+
+
+#endif
diff --git a/include/usbdcore_omap1510.h b/include/usbdcore_omap1510.h
new file mode 100755
index 0000000..6ea3331
--- /dev/null
+++ b/include/usbdcore_omap1510.h
@@ -0,0 +1,183 @@
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ *
+ * Based on
+ * linux/drivers/usb/device/bi/omap.h
+ * Register definitions for TI OMAP1510 USB bus interface driver
+ *
+ * Author: MontaVista Software, Inc.
+ *	   source@mvista.com
+ *
+ * 2003 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __USBDCORE_OMAP1510_H__
+#define __USBDCORE_OMAP1510_H__
+
+
+/*
+ * 13.2 MPU Register Map
+ */
+
+/* Table 13-1. USB Function Module Registers (endpoint) */
+#define UDC_BASE		     0xFFFB4000
+#define UDC_OFFSET(offset)	     (UDC_BASE + (offset))
+#define UDC_REV			     UDC_OFFSET(0x0)	/* Revision */
+#define UDC_EP_NUM		     UDC_OFFSET(0x4)	/* Endpoint selection */
+#define UDC_DATA		     UDC_OFFSET(0x08)	/* Data */
+#define UDC_CTRL		     UDC_OFFSET(0x0C)	/* Control */
+#define UDC_STAT_FLG		     UDC_OFFSET(0x10)	/* Status flag */
+#define UDC_RXFSTAT		     UDC_OFFSET(0x14)	/* Receive FIFO status */
+#define UDC_SYSCON1		     UDC_OFFSET(0x18)	/* System configuration 1 */
+#define UDC_SYSCON2		     UDC_OFFSET(0x1C)	/* System configuration 2 */
+#define UDC_DEVSTAT		     UDC_OFFSET(0x20)	/* Device status */
+#define UDC_SOF			     UDC_OFFSET(0x24)	/* Start of frame */
+#define UDC_IRQ_EN		     UDC_OFFSET(0x28)	/* Interrupt enable */
+#define UDC_DMA_IRQ_EN		     UDC_OFFSET(0x2C)	/* DMA interrupt enable */
+#define UDC_IRQ_SRC		     UDC_OFFSET(0x30)	/* Interrupt source */
+#define UDC_EPN_STAT		     UDC_OFFSET(0x34)	/* Endpoint interrupt status */
+#define UDC_DMAN_STAT		     UDC_OFFSET(0x3C)	/* DMA endpoint interrupt status */
+
+/* IRQ_EN register fields */
+#define UDC_Sof_IE		     (1 << 7)	/* Start-of-frame interrupt enabled */
+#define UDC_EPn_RX_IE		     (1 << 5)	/* Receive endpoint interrupt enabled */
+#define UDC_EPn_TX_IE		     (1 << 4)	/* Transmit endpoint interrupt enabled */
+#define UDC_DS_Chg_IE		     (1 << 3)	/* Device state changed interrupt enabled */
+#define UDC_EP0_IE		     (1 << 0)	/* EP0 transaction interrupt enabled */
+
+/* IRQ_SRC register fields */
+#define UDC_TXn_Done		     (1 << 10)	/* Transmit DMA channel n done */
+#define UDC_RXn_Cnt		     (1 << 9)	/* Receive DMA channel n transactions count */
+#define UDC_RXn_EOT		     (1 << 8)	/* Receive DMA channel n end of transfer */
+#define UDC_SOF_Flg		     (1 << 7)	/* Start-of-frame interrupt flag */
+#define UDC_EPn_RX		     (1 << 5)	/* Endpoint n OUT transaction */
+#define UDC_EPn_TX		     (1 << 4)	/* Endpoint n IN transaction */
+#define UDC_DS_Chg		     (1 << 3)	/* Device state changed */
+#define UDC_Setup		     (1 << 2)	/* Setup transaction */
+#define UDC_EP0_RX		     (1 << 1)	/* EP0 OUT transaction */
+#define UDC_EP0_TX		     (1 << 0)	/* EP0 IN transaction */
+
+/* DEVSTAT register fields, 14.2.9 */
+#define UDC_R_WK_OK		     (1 << 6)	/* Remote wakeup granted */
+#define UDC_USB_Reset		     (1 << 5)	/* USB reset signalling is active */
+#define UDC_SUS			     (1 << 4)	/* Suspended state */
+#define UDC_CFG			     (1 << 3)	/* Configured state */
+#define UDC_ADD			     (1 << 2)	/* Addressed state */
+#define UDC_DEF			     (1 << 1)	/* Default state */
+#define UDC_ATT			     (1 << 0)	/* Attached state */
+
+/* SYSCON1 register fields */
+#define UDC_Cfg_Lock		     (1 << 8)	/* Device configuration locked */
+#define UDC_Nak_En		     (1 << 4)	/* NAK enable */
+#define UDC_Self_Pwr		     (1 << 2)	/* Device is self-powered */
+#define UDC_Soff_Dis		     (1 << 1)	/* Shutoff disabled */
+#define UDC_Pullup_En		     (1 << 0)	/* External pullup enabled */
+
+/* SYSCON2 register fields */
+#define UDC_Rmt_Wkp		     (1 << 6)	/* Remote wakeup */
+#define UDC_Stall_Cmd		     (1 << 5)	/* Stall endpoint */
+#define UDC_Dev_Cfg		     (1 << 3)	/* Device configured */
+#define UDC_Clr_Cfg		     (1 << 2)	/* Clear configured */
+
+/*
+ * Select and enable endpoints
+ */
+
+/* Table 13-1. USB Function Module Registers (endpoint configuration) */
+#define UDC_EPBASE		     UDC_OFFSET(0x80)	/* Endpoints base address */
+#define UDC_EP0			     UDC_EPBASE /* Control endpoint configuration */
+#define UDC_EP_RX_BASE		     UDC_OFFSET(0x84)	/* Receive endpoints base address */
+#define UDC_EP_RX(endpoint)	     (UDC_EP_RX_BASE + ((endpoint) - 1) * 4)
+#define UDC_EP_TX_BASE		     UDC_OFFSET(0xC4)	/* Transmit endpoints base address */
+#define UDC_EP_TX(endpoint)	     (UDC_EP_TX_BASE + ((endpoint) - 1) * 4)
+
+/* EP_NUM register fields */
+#define UDC_Setup_Sel		     (1 << 6)	/* Setup FIFO select */
+#define UDC_EP_Sel		     (1 << 5)	/* TX/RX FIFO select */
+#define UDC_EP_Dir		     (1 << 4)	/* Endpoint direction */
+
+/* CTRL register fields */
+#define UDC_Clr_Halt		     (1 << 7)	/* Clear halt endpoint */
+#define UDC_Set_Halt		     (1 << 6)	/* Set halt endpoint */
+#define UDC_Set_FIFO_En		     (1 << 2)	/* Set FIFO enable */
+#define UDC_Clr_EP		     (1 << 1)	/* Clear endpoint */
+#define UDC_Reset_EP		     (1 << 0)	/* Reset endpoint */
+
+/* STAT_FLG register fields */
+#define UDC_Miss_In		     (1 << 14)
+#define UDC_Data_Flush		     (1 << 13)
+#define UDC_ISO_Err		     (1 << 12)
+#define UDC_ISO_FIFO_Empty	     (1 << 9)
+#define UDC_ISO_FIFO_Full	     (1 << 8)
+#define UDC_EP_Halted		     (1 << 6)
+#define UDC_STALL		     (1 << 5)
+#define UDC_NAK			     (1 << 4)
+#define UDC_ACK			     (1 << 3)
+#define UDC_FIFO_En		     (1 << 2)
+#define UDC_Non_ISO_FIFO_Empty	     (1 << 1)
+#define UDC_Non_ISO_FIFO_Full	     (1 << 0)
+
+/* EPn_RX register fields */
+#define UDC_EPn_RX_Valid	     (1 << 15)	/* valid */
+#define UDC_EPn_RX_Db		     (1 << 14)	/* double-buffer */
+#define UDC_EPn_RX_Iso		     (1 << 11)	/* isochronous */
+
+/* EPn_TX register fields */
+#define UDC_EPn_TX_Valid	     (1 << 15)	/* valid */
+#define UDC_EPn_TX_Db		     (1 << 14)	/* double-buffer */
+#define UDC_EPn_TX_Iso		     (1 << 11)	/* isochronous */
+
+#define EP0_PACKETSIZE		     0x40
+
+/* physical to logical endpoint mapping
+ * Physical endpoints are an index into device->bus->endpoint_array.
+ * Logical endpoints are endpoints 0 to 15 IN and OUT as defined in
+ * the USB specification.
+ *
+ *	physical ep	logical ep	direction	endpoint_address
+ *	0		0		IN and OUT	0x00
+ *	1 to 15		1 to 15		OUT		0x01 to 0x0f
+ *	16 to 30	1 to 15		IN		0x81 to 0x8f
+ */
+#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80))
+#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a))
+
+/* MOD_CONF_CTRL_0 bits (FIXME: move to board hardware.h ?) */
+#define CONF_MOD_USB_W2FC_VBUS_MODE_R (1 << 17)
+
+/* Other registers (may be) related to USB */
+
+#define CLOCK_CTRL	    (0xFFFE0830)
+#define APLL_CTRL	    (0xFFFE084C)
+#define DPLL_CTRL	    (0xFFFE083C)
+#define SOFT_REQ	    (0xFFFE0834)
+#define STATUS_REQ	    (0xFFFE0840)
+
+/* FUNC_MUX_CTRL_0 bits related to USB */
+#define UDC_VBUS_CTRL	    (1 << 19)
+#define UDC_VBUS_MODE	    (1 << 18)
+
+
+void omap1510_udc_irq(void);
+void omap1510_udc_noniso_irq(void);
+
+
+/* Higher level functions for abstracting away from specific device */
+void udc_endpoint_write(struct usb_endpoint_instance *endpoint);
+
+int  udc_init (void);
+
+void udc_enable(struct usb_device_instance *device);
+void udc_disable(void);
+
+void udc_connect(void);
+void udc_disconnect(void);
+
+void udc_startup_events(struct usb_device_instance *device);
+void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, struct usb_endpoint_instance *endpoint);
+
+#endif
diff --git a/include/usbdescriptors.h b/include/usbdescriptors.h
new file mode 100755
index 0000000..8799667
--- /dev/null
+++ b/include/usbdescriptors.h
@@ -0,0 +1,506 @@
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ *
+ * Based on
+ * linux/drivers/usbd/usb-function.h - USB Function
+ *
+ * Copyright (c) 2000, 2001, 2002 Lineo
+ * Copyright (c) 2001 Hewlett Packard
+ *
+ * By:
+ *	Stuart Lynne <sl@lineo.com>,
+ *	Tom Rushworth <tbr@lineo.com>,
+ *	Bruce Balden <balden@lineo.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+/* USB Descriptors - Create a complete description of all of the
+ * function driver capabilities. These map directly to the USB descriptors.
+ *
+ * This heirarchy is created by the functions drivers and is passed to the
+ * usb-device driver when the function driver is registered.
+ *
+ *  device
+ *	configuration
+ *	     interface
+ *		alternate
+ *		     class
+ *		     class
+ *		alternate
+ *		     endpoint
+ *		     endpoint
+ *	     interface
+ *		alternate
+ *		     endpoint
+ *		     endpoint
+ *	configuration
+ *	     interface
+ *		alternate
+ *		     endpoint
+ *		     endpoint
+ *
+ *
+ * The configuration structures refer to the USB Configurations that will be
+ * made available to a USB HOST during the enumeration process.
+ *
+ * The USB HOST will select a configuration and optionally an interface with
+ * the usb set configuration and set interface commands.
+ *
+ * The selected interface (or the default interface if not specifically
+ * selected) will define the list of endpoints that will be used.
+ *
+ * The configuration and interfaces are stored in an array that is indexed
+ * by the specified configuratin or interface number minus one.
+ *
+ * A configuration number of zero is used to specify a return to the unconfigured
+ * state.
+ *
+ */
+
+
+#ifndef __USBDESCRIPTORS_H__
+#define __USBDESCRIPTORS_H__
+
+#include <asm/types.h>
+
+/*
+ * communications class types
+ *
+ * c.f. CDC  USB Class Definitions for Communications Devices
+ * c.f. WMCD USB CDC Subclass Specification for Wireless Mobile Communications Devices
+ *
+ */
+
+#define CLASS_BCD_VERSION		0x0110
+
+/* c.f. CDC 4.1 Table 14 */
+#define COMMUNICATIONS_DEVICE_CLASS	0x02
+
+/* c.f. CDC 4.2 Table 15 */
+#define COMMUNICATIONS_INTERFACE_CLASS_CONTROL	0x02
+#define COMMUNICATIONS_INTERFACE_CLASS_DATA		0x0A
+#define COMMUNICATIONS_INTERFACE_CLASS_VENDOR	0x0FF
+
+/* c.f. CDC 4.3 Table 16 */
+#define COMMUNICATIONS_NO_SUBCLASS	0x00
+#define COMMUNICATIONS_DLCM_SUBCLASS	0x01
+#define COMMUNICATIONS_ACM_SUBCLASS	0x02
+#define COMMUNICATIONS_TCM_SUBCLASS	0x03
+#define COMMUNICATIONS_MCCM_SUBCLASS	0x04
+#define COMMUNICATIONS_CCM_SUBCLASS	0x05
+#define COMMUNICATIONS_ENCM_SUBCLASS	0x06
+#define COMMUNICATIONS_ANCM_SUBCLASS	0x07
+
+/* c.f. WMCD 5.1 */
+#define COMMUNICATIONS_WHCM_SUBCLASS	0x08
+#define COMMUNICATIONS_DMM_SUBCLASS	0x09
+#define COMMUNICATIONS_MDLM_SUBCLASS	0x0a
+#define COMMUNICATIONS_OBEX_SUBCLASS	0x0b
+
+/* c.f. CDC 4.4 Table 17 */
+#define COMMUNICATIONS_NO_PROTOCOL		0x00
+#define COMMUNICATIONS_V25TER_PROTOCOL	0x01	/*Common AT Hayes compatible*/
+
+/* c.f. CDC 4.6 Table 18 */
+#define DATA_INTERFACE_CLASS		0x0a
+
+/* c.f. CDC 4.6 No Table */
+#define DATA_INTERFACE_SUBCLASS_NONE	0x00	/* No subclass pertinent */
+
+/* c.f. CDC 4.7 Table 19 */
+#define COMMUNICATIONS_NO_PROTOCOL	0x00
+
+
+/* c.f. CDC 5.2.3 Table 24 */
+#define CS_INTERFACE			0x24
+#define CS_ENDPOINT			0x25
+
+/*
+ * bDescriptorSubtypes
+ *
+ * c.f. CDC 5.2.3 Table 25
+ * c.f. WMCD 5.3 Table 5.3
+ */
+
+#define USB_ST_HEADER			0x00
+#define USB_ST_CMF			0x01
+#define USB_ST_ACMF			0x02
+#define USB_ST_DLMF			0x03
+#define USB_ST_TRF			0x04
+#define USB_ST_TCLF			0x05
+#define USB_ST_UF			0x06
+#define USB_ST_CSF			0x07
+#define USB_ST_TOMF			0x08
+#define USB_ST_USBTF			0x09
+#define USB_ST_NCT			0x0a
+#define USB_ST_PUF			0x0b
+#define USB_ST_EUF			0x0c
+#define USB_ST_MCMF			0x0d
+#define USB_ST_CCMF			0x0e
+#define USB_ST_ENF			0x0f
+#define USB_ST_ATMNF			0x10
+
+#define USB_ST_WHCM			0x11
+#define USB_ST_MDLM			0x12
+#define USB_ST_MDLMD			0x13
+#define USB_ST_DMM			0x14
+#define USB_ST_OBEX			0x15
+#define USB_ST_CS			0x16
+#define USB_ST_CSD			0x17
+#define USB_ST_TCM			0x18
+
+/* endpoint modifiers
+ * static struct usb_endpoint_description function_default_A_1[] = {
+ *
+ *     {this_endpoint: 0, attributes: CONTROL,	 max_size: 8,  polling_interval: 0 },
+ *     {this_endpoint: 1, attributes: BULK,	 max_size: 64, polling_interval: 0, direction: IN},
+ *     {this_endpoint: 2, attributes: BULK,	 max_size: 64, polling_interval: 0, direction: OUT},
+ *     {this_endpoint: 3, attributes: INTERRUPT, max_size: 8,  polling_interval: 0},
+ *
+ *
+ */
+#define OUT		0x00
+#define IN		0x80
+
+#define CONTROL		0x00
+#define ISOCHRONOUS	0x01
+#define BULK		0x02
+#define INTERRUPT	0x03
+
+
+/* configuration modifiers
+ */
+#define BMATTRIBUTE_RESERVED		0x80
+#define BMATTRIBUTE_SELF_POWERED	0x40
+
+/*
+ * standard usb descriptor structures
+ */
+
+struct usb_endpoint_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;	/* 0x5 */
+	u8 bEndpointAddress;
+	u8 bmAttributes;
+	u16 wMaxPacketSize;
+	u8 bInterval;
+} __attribute__ ((packed));
+
+struct usb_interface_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;	/* 0x04 */
+	u8 bInterfaceNumber;
+	u8 bAlternateSetting;
+	u8 bNumEndpoints;
+	u8 bInterfaceClass;
+	u8 bInterfaceSubClass;
+	u8 bInterfaceProtocol;
+	u8 iInterface;
+} __attribute__ ((packed));
+
+struct usb_configuration_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;	/* 0x2 */
+	u16 wTotalLength;
+	u8 bNumInterfaces;
+	u8 bConfigurationValue;
+	u8 iConfiguration;
+	u8 bmAttributes;
+	u8 bMaxPower;
+} __attribute__ ((packed));
+
+struct usb_device_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;	/* 0x01 */
+	u16 bcdUSB;
+	u8 bDeviceClass;
+	u8 bDeviceSubClass;
+	u8 bDeviceProtocol;
+	u8 bMaxPacketSize0;
+	u16 idVendor;
+	u16 idProduct;
+	u16 bcdDevice;
+	u8 iManufacturer;
+	u8 iProduct;
+	u8 iSerialNumber;
+	u8 bNumConfigurations;
+} __attribute__ ((packed));
+
+struct usb_string_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;	/* 0x03 */
+	u16 wData[0];
+} __attribute__ ((packed));
+
+struct usb_generic_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;
+} __attribute__ ((packed));
+
+
+/*
+ * communications class descriptor structures
+ *
+ * c.f. CDC 5.2 Table 25c
+ */
+
+struct usb_class_function_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;
+} __attribute__ ((packed));
+
+struct usb_class_function_descriptor_generic {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;
+	u8 bmCapabilities;
+} __attribute__ ((packed));
+
+struct usb_class_header_function_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x00 */
+	u16 bcdCDC;
+} __attribute__ ((packed));
+
+struct usb_class_call_management_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x01 */
+	u8 bmCapabilities;
+	u8 bDataInterface;
+} __attribute__ ((packed));
+
+struct usb_class_abstract_control_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x02 */
+	u8 bmCapabilities;
+} __attribute__ ((packed));
+
+struct usb_class_direct_line_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x03 */
+} __attribute__ ((packed));
+
+struct usb_class_telephone_ringer_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x04 */
+	u8 bRingerVolSeps;
+	u8 bNumRingerPatterns;
+} __attribute__ ((packed));
+
+struct usb_class_telephone_call_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x05 */
+	u8 bmCapabilities;
+} __attribute__ ((packed));
+
+struct usb_class_union_function_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x06 */
+	u8 bMasterInterface;
+	u8 bSlaveInterface0[0];
+} __attribute__ ((packed));
+
+struct usb_class_country_selection_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x07 */
+	u8 iCountryCodeRelDate;
+	u16 wCountryCode0[0];
+} __attribute__ ((packed));
+
+
+struct usb_class_telephone_operational_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x08 */
+	u8 bmCapabilities;
+} __attribute__ ((packed));
+
+
+struct usb_class_usb_terminal_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x09 */
+	u8 bEntityId;
+	u8 bInterfaceNo;
+	u8 bOutInterfaceNo;
+	u8 bmOptions;
+	u8 bChild0[0];
+} __attribute__ ((packed));
+
+struct usb_class_network_channel_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x0a */
+	u8 bEntityId;
+	u8 iName;
+	u8 bChannelIndex;
+	u8 bPhysicalInterface;
+} __attribute__ ((packed));
+
+struct usb_class_protocol_unit_function_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x0b */
+	u8 bEntityId;
+	u8 bProtocol;
+	u8 bChild0[0];
+} __attribute__ ((packed));
+
+struct usb_class_extension_unit_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x0c */
+	u8 bEntityId;
+	u8 bExtensionCode;
+	u8 iName;
+	u8 bChild0[0];
+} __attribute__ ((packed));
+
+struct usb_class_multi_channel_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x0d */
+	u8 bmCapabilities;
+} __attribute__ ((packed));
+
+struct usb_class_capi_control_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x0e */
+	u8 bmCapabilities;
+} __attribute__ ((packed));
+
+struct usb_class_ethernet_networking_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x0f */
+	u8 iMACAddress;
+	u32 bmEthernetStatistics;
+	u16 wMaxSegmentSize;
+	u16 wNumberMCFilters;
+	u8 bNumberPowerFilters;
+} __attribute__ ((packed));
+
+struct usb_class_atm_networking_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x10 */
+	u8 iEndSystermIdentifier;
+	u8 bmDataCapabilities;
+	u8 bmATMDeviceStatistics;
+	u16 wType2MaxSegmentSize;
+	u16 wType3MaxSegmentSize;
+	u16 wMaxVC;
+} __attribute__ ((packed));
+
+
+struct usb_class_mdlm_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x12 */
+	u16 bcdVersion;
+	u8 bGUID[16];
+} __attribute__ ((packed));
+
+struct usb_class_mdlmd_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x13 */
+	u8 bGuidDescriptorType;
+	u8 bDetailData[0];
+
+} __attribute__ ((packed));
+
+/*
+ * HID class descriptor structures
+ *
+ * c.f. HID 6.2.1
+ */
+
+struct usb_class_hid_descriptor {
+    u8	      bLength;
+    u8	      bDescriptorType;
+    u16	      bcdCDC;
+    u8	      bCountryCode;
+    u8	      bNumDescriptors;	/* 0x01 */
+    u8	      bDescriptorType0;
+    u16	      wDescriptorLength0;
+    /* optional descriptors are not supported. */
+} __attribute__((packed));
+
+struct usb_class_report_descriptor {
+    u8	      bLength;	/* dummy */
+    u8	      bDescriptorType;
+    u16	      wLength;
+    u8		bData[0];
+} __attribute__((packed));
+
+/*
+ * descriptor union structures
+ */
+
+struct usb_descriptor {
+	union {
+		struct usb_generic_descriptor generic;
+		struct usb_endpoint_descriptor endpoint;
+		struct usb_interface_descriptor interface;
+		struct usb_configuration_descriptor configuration;
+		struct usb_device_descriptor device;
+		struct usb_string_descriptor string;
+	} descriptor;
+
+} __attribute__ ((packed));
+
+struct usb_class_descriptor {
+	union {
+		struct usb_class_function_descriptor function;
+		struct usb_class_function_descriptor_generic generic;
+		struct usb_class_header_function_descriptor header_function;
+		struct usb_class_call_management_descriptor call_management;
+		struct usb_class_abstract_control_descriptor abstract_control;
+		struct usb_class_direct_line_descriptor direct_line;
+		struct usb_class_telephone_ringer_descriptor telephone_ringer;
+		struct usb_class_telephone_operational_descriptor telephone_operational;
+		struct usb_class_telephone_call_descriptor telephone_call;
+		struct usb_class_union_function_descriptor union_function;
+		struct usb_class_country_selection_descriptor country_selection;
+		struct usb_class_usb_terminal_descriptor usb_terminal;
+		struct usb_class_network_channel_descriptor network_channel;
+		struct usb_class_extension_unit_descriptor extension_unit;
+		struct usb_class_multi_channel_descriptor multi_channel;
+		struct usb_class_capi_control_descriptor capi_control;
+		struct usb_class_ethernet_networking_descriptor ethernet_networking;
+		struct usb_class_atm_networking_descriptor atm_networking;
+		struct usb_class_mdlm_descriptor mobile_direct;
+		struct usb_class_mdlmd_descriptor mobile_direct_detail;
+		struct usb_class_hid_descriptor hid;
+	} descriptor;
+
+} __attribute__ ((packed));
+
+#endif
diff --git a/include/usbdevice.h b/include/usbdevice.h
new file mode 100755
index 0000000..defb979
--- /dev/null
+++ b/include/usbdevice.h
@@ -0,0 +1,705 @@
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ *
+ * Based on linux/drivers/usbd/usbd.h
+ *
+ * Copyright (c) 2000, 2001, 2002 Lineo
+ * Copyright (c) 2001 Hewlett Packard
+ *
+ * By:
+ *	Stuart Lynne <sl@lineo.com>,
+ *	Tom Rushworth <tbr@lineo.com>,
+ *	Bruce Balden <balden@lineo.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __USBDCORE_H__
+#define __USBDCORE_H__
+
+#include <common.h>
+//#include "usbdescriptors.h"   //Charles
+
+
+#define MAX_URBS_QUEUED 5
+
+
+#if 1
+#define usberr(fmt,args...) serial_printf("ERROR: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args)
+#else
+#define usberr(fmt,args...) do{}while(0)
+#endif
+
+#if 1
+#define usbdbg(fmt,args...) serial_printf("debug: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args)
+#else
+#define usbdbg(fmt,args...) do{}while(0)
+#endif
+
+#if 1
+#define usbinfo(fmt,args...) serial_printf("info: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args)
+#else
+#define usbinfo(fmt,args...) do{}while(0)
+#endif
+
+#ifndef le16_to_cpu
+#define le16_to_cpu(x)	(x)
+#endif
+
+#ifndef inb
+#define inb(p)	     (*(volatile u8*)(p))
+#endif
+
+#ifndef outb
+#define outb(val,p)  (*(volatile u8*)(p) = (val))
+#endif
+
+#ifndef inw
+#define inw(p)	     (*(volatile u16*)(p))
+#endif
+
+#ifndef outw
+#define outw(val,p)  (*(volatile u16*)(p) = (val))
+#endif
+
+#ifndef inl
+#define inl(p)	     (*(volatile u32*)(p))
+#endif
+
+#ifndef outl
+#define outl(val,p)  (*(volatile u32*)(p) = (val))
+#endif
+
+#ifndef insw
+#define insw(p,to,len)	   mmio_insw(p,to,len)
+#endif
+
+#ifndef outsw
+#define outsw(p,from,len)  mmio_outsw(p,from,len)
+#endif
+
+#ifndef insb
+#define insb(p,to,len)	   mmio_insb(p,to,len)
+#endif
+
+#ifndef mmio_insw
+#define mmio_insw(r,b,l)	({	int __i ;  \
+					u16 *__b2;  \
+					__b2 = (u16 *) b;  \
+					for (__i = 0; __i < l; __i++) {	 \
+					  *(__b2 + __i) = inw(r);  \
+					};  \
+				})
+#endif
+
+#ifndef mmio_outsw
+#define mmio_outsw(r,b,l)	({	int __i; \
+					u16 *__b2; \
+					__b2 = (u16 *) b; \
+					for (__i = 0; __i < l; __i++) { \
+					    outw( *(__b2 + __i), r); \
+					} \
+				})
+#endif
+
+#ifndef mmio_insb
+#define mmio_insb(r,b,l)	({	int __i ;  \
+					u8 *__b2;  \
+					__b2 = (u8 *) b;  \
+					for (__i = 0; __i < l; __i++) {	 \
+					  *(__b2 + __i) = inb(r);  \
+					};  \
+				})
+#endif
+
+/*
+ * Structure member address manipulation macros.
+ * These are used by client code (code using the urb_link routines), since
+ * the urb_link structure is embedded in the client data structures.
+ *
+ * Note: a macro offsetof equivalent to member_offset is defined in stddef.h
+ *	 but this is kept here for the sake of portability.
+ *
+ * p2surround returns a pointer to the surrounding structure given
+ * type of the surrounding structure, the name memb of the structure
+ * member pointed at by ptr.  For example, if you have:
+ *
+ *	struct foo {
+ *	    int x;
+ *	    float y;
+ *	    char z;
+ *	} thingy;
+ *
+ *	char *cp = &thingy.z;
+ *
+ * then
+ *
+ *	&thingy == p2surround(struct foo, z, cp)
+ *
+ * Clear?
+ */
+#define _cv_(ptr)		  ((char*)(void*)(ptr))
+#define member_offset(type,memb)  (_cv_(&(((type*)0)->memb))-(char*)0)
+#define p2surround(type,memb,ptr) ((type*)(void*)(_cv_(ptr)-member_offset(type,memb)))
+
+struct urb;
+
+struct usb_endpoint_instance;
+struct usb_interface_instance;
+struct usb_configuration_instance;
+struct usb_device_instance;
+struct usb_bus_instance;
+
+/*
+ * Device and/or Interface Class codes
+ */
+#define USB_CLASS_PER_INTERFACE		0	/* for DeviceClass */
+#define USB_CLASS_AUDIO			1
+#define USB_CLASS_COMM			2
+#define USB_CLASS_HID			3
+#define USB_CLASS_PHYSICAL		5
+#define USB_CLASS_PRINTER		7
+#define USB_CLASS_MASS_STORAGE		8
+#define USB_CLASS_HUB			9
+#define USB_CLASS_DATA			10
+#define USB_CLASS_APP_SPEC		0xfe
+#define USB_CLASS_VENDOR_SPEC		0xff
+
+/*
+ * USB types
+ */
+#define USB_TYPE_STANDARD		(0x00 << 5)
+#define USB_TYPE_CLASS			(0x01 << 5)
+#define USB_TYPE_VENDOR			(0x02 << 5)
+#define USB_TYPE_RESERVED		(0x03 << 5)
+
+/*
+ * USB recipients
+ */
+#define USB_RECIP_DEVICE		0x00
+#define USB_RECIP_INTERFACE		0x01
+#define USB_RECIP_ENDPOINT		0x02
+#define USB_RECIP_OTHER			0x03
+
+/*
+ * USB directions
+ */
+#define USB_DIR_OUT			0
+#define USB_DIR_IN			0x80
+
+/*
+ * Descriptor types
+ */
+#define USB_DT_DEVICE			0x01
+#define USB_DT_CONFIG			0x02
+#define USB_DT_STRING			0x03
+#define USB_DT_INTERFACE		0x04
+#define USB_DT_ENDPOINT			0x05
+
+#define USB_DT_HID			(USB_TYPE_CLASS | 0x01)
+#define USB_DT_REPORT			(USB_TYPE_CLASS | 0x02)
+#define USB_DT_PHYSICAL			(USB_TYPE_CLASS | 0x03)
+#define USB_DT_HUB			(USB_TYPE_CLASS | 0x09)
+
+/*
+ * Descriptor sizes per descriptor type
+ */
+#define USB_DT_DEVICE_SIZE		18
+#define USB_DT_CONFIG_SIZE		9
+#define USB_DT_INTERFACE_SIZE		9
+#define USB_DT_ENDPOINT_SIZE		7
+#define USB_DT_ENDPOINT_AUDIO_SIZE	9	/* Audio extension */
+#define USB_DT_HUB_NONVAR_SIZE		7
+#define USB_DT_HID_SIZE			9
+
+/*
+ * Endpoints
+ */
+#define USB_ENDPOINT_NUMBER_MASK	0x0f	/* in bEndpointAddress */
+#define USB_ENDPOINT_DIR_MASK		0x80
+
+#define USB_ENDPOINT_XFERTYPE_MASK	0x03	/* in bmAttributes */
+#define USB_ENDPOINT_XFER_CONTROL	0
+#define USB_ENDPOINT_XFER_ISOC		1
+#define USB_ENDPOINT_XFER_BULK		2
+#define USB_ENDPOINT_XFER_INT		3
+
+/*
+ * USB Packet IDs (PIDs)
+ */
+#define USB_PID_UNDEF_0			       0xf0
+#define USB_PID_OUT			       0xe1
+#define USB_PID_ACK			       0xd2
+#define USB_PID_DATA0			       0xc3
+#define USB_PID_PING			       0xb4	/* USB 2.0 */
+#define USB_PID_SOF			       0xa5
+#define USB_PID_NYET			       0x96	/* USB 2.0 */
+#define USB_PID_DATA2			       0x87	/* USB 2.0 */
+#define USB_PID_SPLIT			       0x78	/* USB 2.0 */
+#define USB_PID_IN			       0x69
+#define USB_PID_NAK			       0x5a
+#define USB_PID_DATA1			       0x4b
+#define USB_PID_PREAMBLE		       0x3c	/* Token mode */
+#define USB_PID_ERR			       0x3c	/* USB 2.0: handshake mode */
+#define USB_PID_SETUP			       0x2d
+#define USB_PID_STALL			       0x1e
+#define USB_PID_MDATA			       0x0f	/* USB 2.0 */
+
+/*
+ * Standard requests
+ */
+#define USB_REQ_GET_STATUS		0x00
+#define USB_REQ_CLEAR_FEATURE		0x01
+#define USB_REQ_SET_FEATURE		0x03
+#define USB_REQ_SET_ADDRESS		0x05
+#define USB_REQ_GET_DESCRIPTOR		0x06
+#define USB_REQ_SET_DESCRIPTOR		0x07
+#define USB_REQ_GET_CONFIGURATION	0x08
+#define USB_REQ_SET_CONFIGURATION	0x09
+#define USB_REQ_GET_INTERFACE		0x0A
+#define USB_REQ_SET_INTERFACE		0x0B
+#define USB_REQ_SYNCH_FRAME		0x0C
+
+#define USBD_DEVICE_REQUESTS(x) (((unsigned int)x <= USB_REQ_SYNCH_FRAME) ? usbd_device_requests[x] : "UNKNOWN")
+
+/*
+ * HID requests
+ */
+#define USB_REQ_GET_REPORT		0x01
+#define USB_REQ_GET_IDLE		0x02
+#define USB_REQ_GET_PROTOCOL		0x03
+#define USB_REQ_SET_REPORT		0x09
+#define USB_REQ_SET_IDLE		0x0A
+#define USB_REQ_SET_PROTOCOL		0x0B
+
+
+/*
+ * USB Spec Release number
+ */
+
+#ifndef	USB_BCD_VERSION
+#define USB_BCD_VERSION			0x0110
+#endif
+
+
+/*
+ * Device Requests	(c.f Table 9-2)
+ */
+
+#define USB_REQ_DIRECTION_MASK		0x80
+#define USB_REQ_TYPE_MASK		0x60
+#define USB_REQ_RECIPIENT_MASK		0x1f
+
+#define USB_REQ_DEVICE2HOST		0x80
+#define USB_REQ_HOST2DEVICE		0x00
+
+#define USB_REQ_TYPE_STANDARD		0x00
+#define USB_REQ_TYPE_CLASS		0x20
+#define USB_REQ_TYPE_VENDOR		0x40
+
+#define USB_REQ_RECIPIENT_DEVICE	0x00
+#define USB_REQ_RECIPIENT_INTERFACE	0x01
+#define USB_REQ_RECIPIENT_ENDPOINT	0x02
+#define USB_REQ_RECIPIENT_OTHER		0x03
+
+/*
+ * get status bits
+ */
+
+#define USB_STATUS_SELFPOWERED		0x01
+#define USB_STATUS_REMOTEWAKEUP		0x02
+
+#define USB_STATUS_HALT			0x01
+
+/*
+ * descriptor types
+ */
+
+#define USB_DESCRIPTOR_TYPE_DEVICE			0x01
+#define USB_DESCRIPTOR_TYPE_CONFIGURATION		0x02
+#define USB_DESCRIPTOR_TYPE_STRING			0x03
+#define USB_DESCRIPTOR_TYPE_INTERFACE			0x04
+#define USB_DESCRIPTOR_TYPE_ENDPOINT			0x05
+#define USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER		0x06
+#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION	0x07
+#define USB_DESCRIPTOR_TYPE_INTERFACE_POWER		0x08
+#define USB_DESCRIPTOR_TYPE_HID				0x21
+#define USB_DESCRIPTOR_TYPE_REPORT			0x22
+
+#define USBD_DEVICE_DESCRIPTORS(x) (((unsigned int)x <= USB_DESCRIPTOR_TYPE_INTERFACE_POWER) ? \
+		usbd_device_descriptors[x] : "UNKNOWN")
+
+/*
+ * standard feature selectors
+ */
+#define USB_ENDPOINT_HALT		0x00
+#define USB_DEVICE_REMOTE_WAKEUP	0x01
+#define USB_TEST_MODE			0x02
+
+
+/* USB Requests
+ *
+ */
+ //Charles
+/*
+struct usb_device_request {
+	u8 bmRequestType;
+	u8 bRequest;
+	u16 wValue;
+	u16 wIndex;
+	u16 wLength;
+} __attribute__ ((packed));
+*/
+
+/* USB Status
+ *
+ */
+ /*
+typedef enum urb_send_status {
+	SEND_IN_PROGRESS,
+	SEND_FINISHED_OK,
+	SEND_FINISHED_ERROR,
+	RECV_READY,
+	RECV_OK,
+	RECV_ERROR
+} urb_send_status_t;
+*/
+/*
+ * Device State (c.f USB Spec 2.0 Figure 9-1)
+ *
+ * What state the usb device is in.
+ *
+ * Note the state does not change if the device is suspended, we simply set a
+ * flag to show that it is suspended.
+ *
+ */
+ /*
+typedef enum usb_device_state {
+	STATE_INIT,		
+	STATE_CREATED,		
+	STATE_ATTACHED,		
+	STATE_POWERED,		
+	STATE_DEFAULT,		
+	STATE_ADDRESSED,	
+	STATE_CONFIGURED,	
+	STATE_UNKNOWN,		
+} usb_device_state_t;
+*/
+#define USBD_DEVICE_STATE(x) (((unsigned int)x <= STATE_UNKNOWN) ? usbd_device_states[x] : "UNKNOWN")
+
+/*
+ * Device status
+ *
+ * Overall state
+ */
+ /*
+typedef enum usb_device_status {
+	USBD_OPENING,		
+	USBD_OK,		
+	USBD_SUSPENDED,		
+	USBD_CLOSING,		
+} usb_device_status_t;
+*/
+#define USBD_DEVICE_STATUS(x) (((unsigned int)x <= USBD_CLOSING) ? usbd_device_status[x] : "UNKNOWN")
+
+/*
+ * Device Events
+ *
+ * These are defined in the USB Spec (c.f USB Spec 2.0 Figure 9-1).
+ *
+ * There are additional events defined to handle some extra actions we need
+ * to have handled.
+ *
+ */
+//typedef enum usb_device_event {
+
+//	DEVICE_UNKNOWN,		/* bi - unknown event */
+//	DEVICE_INIT,		/* bi  - initialize */
+//	DEVICE_CREATE,		/* bi  - */
+//	DEVICE_HUB_CONFIGURED,	/* bi  - bus has been plugged int */
+//	DEVICE_RESET,		/* bi  - hub has powered our port */
+
+//	DEVICE_ADDRESS_ASSIGNED,	/* ep0 - set address setup received */
+//	DEVICE_CONFIGURED,	/* ep0 - set configure setup received */
+//	DEVICE_SET_INTERFACE,	/* ep0 - set interface setup received */
+
+//	DEVICE_SET_FEATURE,	/* ep0 - set feature setup received */
+//	DEVICE_CLEAR_FEATURE,	/* ep0 - clear feature setup received */
+
+//	DEVICE_DE_CONFIGURED,	/* ep0 - set configure setup received for ?? */
+
+//	DEVICE_BUS_INACTIVE,	/* bi  - bus in inactive (no SOF packets) */
+//	DEVICE_BUS_ACTIVITY,	/* bi  - bus is active again */
+
+//	DEVICE_POWER_INTERRUPTION,	/* bi  - hub has depowered our port */
+//	DEVICE_HUB_RESET,	/* bi  - bus has been unplugged */
+//	DEVICE_DESTROY,		/* bi  - device instance should be destroyed */
+
+//	DEVICE_HOTPLUG,		/* bi  - a hotplug event has occured */
+
+//	DEVICE_FUNCTION_PRIVATE,	/* function - private */
+
+//} usb_device_event_t;
+
+/*
+typedef struct urb_link {
+	struct urb_link *next;
+	struct urb_link *prev;
+} urb_link;
+*/
+/* USB Data structure - for passing data around.
+ *
+ * This is used for both sending and receiving data.
+ *
+ * The callback function is used to let the function driver know when
+ * transmitted data has been sent.
+ *
+ * The callback function is set by the alloc_recv function when an urb is
+ * allocated for receiving data for an endpoint and used to call the
+ * function driver to inform it that data has arrived.
+ */
+
+#if USB_BCD_VERSION == 0x0200
+#define URB_BUF_SIZE 2048 /* in linux we'd malloc this, but in u-boot we prefer static data */
+#else
+#define URB_BUF_SIZE 128 /* in linux we'd malloc this, but in u-boot we prefer static data */
+#endif
+
+/* Endpoint configuration
+ *
+ * Per endpoint configuration data. Used to track which function driver owns
+ * an endpoint.
+ *
+ */
+ /*
+struct usb_endpoint_instance {
+	int endpoint_address;	
+
+	
+	int status;		
+	int state;		
+
+	
+	struct urb_link rcv;	
+	struct urb_link rdy;	
+	struct urb *rcv_urb;	
+	int rcv_attributes;	
+	int rcv_packetSize;	
+	int rcv_transferSize;	
+	int rcv_queue;
+
+	
+	struct urb_link tx;	
+	struct urb_link done;	
+	struct urb *tx_urb;	
+	int tx_attributes;
+	int tx_packetSize;	
+	int tx_transferSize;	
+	int tx_queue;
+
+	int sent;		
+	int last;		
+};
+
+struct usb_alternate_instance {
+	struct usb_interface_descriptor *interface_descriptor;
+
+	int endpoints;
+	int *endpoint_transfersize_array;
+	struct usb_endpoint_descriptor **endpoints_descriptor_array;
+};
+
+struct usb_interface_instance {
+	int alternates;
+	struct usb_alternate_instance *alternates_instance_array;
+};
+
+struct usb_configuration_instance {
+	int interfaces;
+	struct usb_configuration_descriptor *configuration_descriptor;
+	struct usb_interface_instance *interface_instance_array;
+};
+*/
+
+/* USB Device Instance
+ *
+ * For each physical bus interface we create a logical device structure. This
+ * tracks all of the required state to track the USB HOST's view of the device.
+ *
+ * Keep track of the device configuration for a real physical bus interface,
+ * this includes the bus interface, multiple function drivers, the current
+ * configuration and the current state.
+ *
+ * This will show:
+ *	the specific bus interface driver
+ *	the default endpoint 0 driver
+ *	the configured function driver
+ *	device state
+ *	device status
+ *	endpoint list
+ */
+
+
+extern char *usbd_device_events[];
+extern char *usbd_device_states[];
+extern char *usbd_device_status[];
+extern char *usbd_device_requests[];
+extern char *usbd_device_descriptors[];
+
+void urb_link_init (urb_link * ul);
+void urb_detach (struct urb *urb);
+urb_link *first_urb_link (urb_link * hd);
+struct urb *first_urb (urb_link * hd);
+struct urb *first_urb_detached (urb_link * hd);
+void urb_append (urb_link * hd, struct urb *urb);
+
+struct urb *usbd_alloc_urb (struct usb_device_instance *device, struct usb_endpoint_instance *endpoint);
+void	    usbd_dealloc_urb (struct urb *urb);
+
+/*
+ * usbd_device_event is used by bus interface drivers to tell the higher layers that
+ * certain events have taken place.
+ */
+void usbd_device_event_irq (struct usb_device_instance *conf, usb_device_event_t, int);
+void usbd_device_event (struct usb_device_instance *conf, usb_device_event_t, int);
+
+/* descriptors
+ *
+ * Various ways of finding descriptors based on the current device and any
+ * possible configuration / interface / endpoint for it.
+ */
+struct usb_configuration_descriptor *usbd_device_configuration_descriptor (struct usb_device_instance *, int, int);
+struct usb_function_instance *usbd_device_function_instance (struct usb_device_instance *, unsigned int);
+struct usb_interface_instance *usbd_device_interface_instance (struct usb_device_instance *, int, int, int);
+struct usb_alternate_instance *usbd_device_alternate_instance (struct usb_device_instance *, int, int, int, int);
+struct usb_interface_descriptor *usbd_device_interface_descriptor (struct usb_device_instance *, int, int, int, int);
+struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor_index (struct usb_device_instance *, int, int, int, int, int);
+struct usb_class_descriptor *usbd_device_class_descriptor_index (struct usb_device_instance *, int, int, int, int, int);
+struct usb_class_report_descriptor *usbd_device_class_report_descriptor_index( struct usb_device_instance *, int , int , int , int , int );
+struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor (struct usb_device_instance *, int, int, int, int, int);
+int				usbd_device_endpoint_transfersize (struct usb_device_instance *, int, int, int, int, int);
+struct usb_string_descriptor *usbd_get_string (u8);
+struct usb_device_descriptor *usbd_device_device_descriptor (struct usb_device_instance *, int);
+
+int usbd_endpoint_halted (struct usb_device_instance *device, int endpoint);
+void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad);
+void usbd_tx_complete (struct usb_endpoint_instance *endpoint);
+
+/* These are macros used in debugging */
+#ifdef DEBUG
+static inline void print_urb(struct urb *u)
+{
+	serial_printf("urb %p\n", (u));
+	serial_printf("\tendpoint %p\n", u->endpoint);
+	serial_printf("\tdevice %p\n", u->device);
+	serial_printf("\tbuffer %p\n", u->buffer);
+	serial_printf("\tbuffer_length %d\n", u->buffer_length);
+	serial_printf("\tactual_length %d\n", u->actual_length);
+	serial_printf("\tstatus %d\n", u->status);
+	serial_printf("\tdata %d\n", u->data);
+}
+
+static inline void print_usb_device_request(struct usb_device_request *r)
+{
+	serial_printf("usb request\n");
+	serial_printf("\tbmRequestType 0x%2.2x\n", r->bmRequestType);
+	if ((r->bmRequestType & USB_REQ_DIRECTION_MASK) == 0)
+		serial_printf("\t\tDirection : To device\n");
+	else
+		serial_printf("\t\tDirection : To host\n");
+	if ((r->bmRequestType & USB_TYPE_STANDARD) == USB_TYPE_STANDARD)
+		serial_printf("\t\tType      : Standard\n");
+	if ((r->bmRequestType & USB_TYPE_CLASS) == USB_TYPE_CLASS)
+		serial_printf("\t\tType      : Standard\n");
+	if ((r->bmRequestType & USB_TYPE_VENDOR) == USB_TYPE_VENDOR)
+		serial_printf("\t\tType      : Standard\n");
+	if ((r->bmRequestType & USB_TYPE_RESERVED) == USB_TYPE_RESERVED)
+		serial_printf("\t\tType      : Standard\n");
+	if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
+	    USB_REQ_RECIPIENT_DEVICE)
+		serial_printf("\t\tRecipient : Device\n");
+	if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
+	    USB_REQ_RECIPIENT_INTERFACE)
+		serial_printf("\t\tRecipient : Interface\n");
+	if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
+	    USB_REQ_RECIPIENT_ENDPOINT)
+		serial_printf("\t\tRecipient : Endpoint\n");
+	if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
+	    USB_REQ_RECIPIENT_OTHER)
+		serial_printf("\t\tRecipient : Other\n");
+	serial_printf("\tbRequest      0x%2.2x\n", r->bRequest);
+	if (r->bRequest == USB_REQ_GET_STATUS)
+		serial_printf("\t\tGET_STATUS\n");
+	else if (r->bRequest == USB_REQ_SET_ADDRESS)
+		serial_printf("\t\tSET_ADDRESS\n");
+	else if (r->bRequest == USB_REQ_SET_FEATURE)
+		serial_printf("\t\tSET_FEATURE\n");
+	else if (r->bRequest == USB_REQ_GET_DESCRIPTOR)
+		serial_printf("\t\tGET_DESCRIPTOR\n");
+	else if (r->bRequest == USB_REQ_SET_CONFIGURATION)
+		serial_printf("\t\tSET_CONFIGURATION\n");
+	else if (r->bRequest == USB_REQ_SET_INTERFACE)
+		serial_printf("\t\tUSB_REQ_SET_INTERFACE\n");
+	else
+		serial_printf("\tUNKNOWN %d\n", r->bRequest);
+	serial_printf("\twValue        0x%4.4x\n", r->wValue);
+	if (r->bRequest == USB_REQ_GET_DESCRIPTOR) {
+		switch (r->wValue >> 8) {
+		case USB_DESCRIPTOR_TYPE_DEVICE:
+			serial_printf("\tDEVICE\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_CONFIGURATION:
+			serial_printf("\tCONFIGURATION\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_STRING:
+			serial_printf("\tSTRING\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_INTERFACE:
+			serial_printf("\tINTERFACE\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_ENDPOINT:
+			serial_printf("\tENDPOINT\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER:
+			serial_printf("\tDEVICE_QUALIFIER\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION:
+			serial_printf("\tOTHER_SPEED_CONFIGURATION\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_INTERFACE_POWER:
+			serial_printf("\tINTERFACE_POWER\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_HID:
+			serial_printf("\tHID\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_REPORT:
+			serial_printf("\tREPORT\n");
+			break;
+		default:
+			serial_printf("\tUNKNOWN TYPE\n");
+			break;
+		}
+	}
+	serial_printf("\twIndex        0x%4.4x\n", r->wIndex);
+	serial_printf("\twLength       0x%4.4x\n", r->wLength);
+}
+#else
+/* stubs */
+#define print_urb(u)
+#define print_usb_device_request(r)
+#endif /* DEBUG */
+#endif
diff --git a/include/version.h b/include/version.h
new file mode 100755
index 0000000..4f8b498
--- /dev/null
+++ b/include/version.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__VERSION_H__
+#define	__VERSION_H__
+
+#define	U_BOOT_VERSION	"U-Boot 1.1.4"
+
+#endif	/* __VERSION_H__ */
diff --git a/include/vfd_logo.h b/include/vfd_logo.h
new file mode 100755
index 0000000..c41867a
--- /dev/null
+++ b/include/vfd_logo.h
@@ -0,0 +1,1032 @@
+/*
+ * Automatically generated by "tools/bmp_logo"
+ *
+ * DO NOT EDIT
+ *
+ */
+
+
+#ifndef __VFD_LOGO_H__
+#define __VFD_LOGO_H__
+
+#define VFD_LOGO_WIDTH		112
+#define VFD_LOGO_HEIGHT		72
+#define VFD_LOGO_COLORS		0
+#define VFD_LOGO_OFFSET		0
+
+
+unsigned char vfd_test_logo_bitmap[] = {
+	0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD,
+	0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD,
+	0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDF, 0xDD, 0xDD, 0xFF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDF, 0xFD, 0xDD, 0xDF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD,
+	0xDD, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF,
+	0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD,
+	0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD,
+	0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDF, 0xDD, 0xDD, 0xFF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDF, 0xFD, 0xDD, 0xDF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD,
+	0xDD, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF,
+	0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD,
+	0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD,
+	0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDF, 0xDD, 0xDD, 0xFF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDF, 0xFD, 0xDD, 0xDF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD,
+	0xDD, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF,
+	0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD,
+	0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD,
+	0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDF, 0xDD, 0xDD, 0xFF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xFD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDF, 0xFD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xDF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFD, 0xDF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDF, 0xFD, 0xDD, 0xDF, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD,
+	0xDD, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xFF,
+	0xDD, 0xDD, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xFF, 0xFD, 0xDD, 0xDD, 0xFD,
+	0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD,
+	0xDD, 0xDD, 0xFF, 0xFF, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xDD, 0xDD, 0xDF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xDD, 0xDD, 0xDD,
+	0xDD, 0xDD, 0xDD, 0xDF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xDD, 0xDD, 0xDD,
+};
+
+unsigned char vfd_remote_logo_bitmap[] = {
+	0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99,
+	0x9F, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99,
+	0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99,
+	0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x9F, 0x99, 0x99, 0xFF, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xF9,
+	0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x9F, 0xF9, 0x99, 0x9F, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9,
+	0x99, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF,
+	0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99,
+	0x9F, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99,
+	0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99,
+	0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x9F, 0x99, 0x99, 0xFF, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xF9,
+	0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x9F, 0xF9, 0x99, 0x9F, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9,
+	0x99, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF,
+	0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99,
+	0x9F, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99,
+	0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99,
+	0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x9F, 0x99, 0x99, 0xFF, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xF9,
+	0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x9F, 0xF9, 0x99, 0x9F, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9,
+	0x99, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF,
+	0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99,
+	0x9F, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99,
+	0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0x99,
+	0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x9F, 0x99, 0x99, 0xFF, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xF9,
+	0x99, 0x9F, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF,
+	0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xF9, 0x99, 0x9F, 0xFF, 0xF9, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x9F, 0xF9,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0x9F, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x9F, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xF9, 0x9F, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x9F, 0xF9, 0x99, 0x9F, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9,
+	0x99, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0xFF,
+	0x99, 0x99, 0xFF, 0x99, 0x99, 0x99, 0x99, 0x99,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x9F, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0xFF, 0xF9, 0x99, 0x99, 0xF9,
+	0x99, 0x99, 0x99, 0x99, 0x9F, 0x99, 0x99, 0x99,
+	0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99,
+	0x99, 0x99, 0xFF, 0xFF, 0x99, 0x99, 0x9F, 0xFF,
+	0x99, 0x99, 0x9F, 0x99, 0x99, 0x99, 0x99, 0x99,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0x99, 0x99, 0x99, 0x99, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99,
+	0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xF9, 0x99, 0x99, 0x99, 0x99, 0x9F, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x99, 0x99, 0x99,
+	0x99, 0x99, 0x99, 0x9F, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xF9, 0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x9F,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x99, 0x99, 0x99,
+};
+
+#endif /* __VFD_LOGO_H__ */
diff --git a/include/video.h b/include/video.h
new file mode 100755
index 0000000..efcc682
--- /dev/null
+++ b/include/video.h
@@ -0,0 +1,19 @@
+/*
+** MPC823 Video Controller
+** =======================
+** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
+** AIRVENT SAM s.p.a - RIMINI(ITALY)
+**
+*/
+
+#ifndef _VIDEO_H_
+#define _VIDEO_H_
+
+/* Video functions */
+
+int	video_init	(void *videobase);
+void	video_putc	(const char c);
+void	video_puts	(const char *s);
+void	video_printf	(const char *fmt, ...);
+
+#endif
diff --git a/include/video_ad7176.h b/include/video_ad7176.h
new file mode 100755
index 0000000..92ddcb7
--- /dev/null
+++ b/include/video_ad7176.h
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _VIDEO_AD7176_H_
+#define _VIDEO_AD7176_H_
+
+#define VIDEO_ENCODER_NAME	"Analog Devices AD7176"
+
+#define VIDEO_ENCODER_I2C_RATE	100000	/* Max rate is 100 kHz		*/
+#define VIDEO_ENCODER_CB_Y_CR_Y		/* Use CB Y CR Y format...	*/
+
+#define VIDEO_MODE_YUYV		/* The only mode supported by this encoder */
+#undef	VIDEO_MODE_RGB
+#define VIDEO_MODE_BPP		16
+
+#ifdef	VIDEO_MODE_PAL
+#define VIDEO_ACTIVE_COLS	720
+#define VIDEO_ACTIVE_ROWS	576
+#define VIDEO_VISIBLE_COLS	640
+#define VIDEO_VISIBLE_ROWS	480
+#endif
+
+#ifdef	VIDEO_MODE_NTSC
+#define VIDEO_ACTIVE_COLS	720
+#define VIDEO_ACTIVE_ROWS	525
+#define VIDEO_VISIBLE_COLS	640
+#define VIDEO_VISIBLE_ROWS	400
+#endif
+
+static unsigned char video_encoder_data[] = {
+#ifdef VIDEO_MODE_NTSC
+					0x04, /* Mode Register 0	*/
+#ifdef VIDEO_DEBUG_COLORBARS
+					0x82,
+#else
+					0x02, /* Mode Register 1	*/
+#endif	/* VIDEO_DEBUG_COLORBARS */
+					0x16, /* Subcarrier Freq 0	*/
+					0x7c, /* Subcarrier Freq 1	*/
+					0xf0, /* Subcarrier Freq 2	*/
+					0x21, /* Subcarrier Freq 3	*/
+					0x00, /* Subcarrier phase	*/
+					0x02, /* Timing Register 0	*/
+					0x00, /* Extended Captioning 0	*/
+					0x00, /* Extended Captioning 1	*/
+					0x00, /* Closed Captioning 0	*/
+					0x00, /* Closed Captioning 1	*/
+					0x00, /* Timing Register 1	*/
+					0x08, /* Mode Register 2	*/
+					0x00, /* Pedestal Register 0	*/
+					0x00, /* Pedestal Register 1	*/
+					0x00, /* Pedestal Register 2	*/
+					0x00, /* Pedestal Register 3	*/
+					0x00  /* Mode Register 3	*/
+
+#endif	/* VIDEO_MODE_NTSC */
+
+#ifdef VIDEO_MODE_PAL
+					0x05, /* Mode Register 0	*/
+#ifdef VIDEO_DEBUG_COLORBARS
+					0x82,
+#else
+					0x02, /* Mode Register 1 (2)	*/
+#endif	/* VIDEO_DEBUG_COLORBARS */
+					0xcb, /* Subcarrier Freq 0	*/
+					0x8a, /* Subcarrier Freq 1	*/
+					0x09, /* Subcarrier Freq 2	*/
+					0x2a, /* Subcarrier Freq 3	*/
+					0x00, /* Subcarrier phase	*/
+					0x0a, /* Timing Register 0 (a)	*/
+					0x00, /* Extended Captioning 0	*/
+					0x00, /* Extended Captioning 1	*/
+					0x00, /* Closed Captioning 0	*/
+					0x00, /* Closed Captioning 1	*/
+					0x00, /* Timing Register 1	*/
+					0x08, /* Mode Register 2 (8)	*/
+					0x00, /* Pedestal Register 0	*/
+					0x00, /* Pedestal Register 1	*/
+					0x00, /* Pedestal Register 2	*/
+					0x00, /* Pedestal Register 3	*/
+					0x00  /* Mode Register 3	*/
+#endif	/* VIDEO_MODE_PAL */
+} ;
+
+#endif	/* _VIDEO_AD7176_H_ */
diff --git a/include/video_ad7177.h b/include/video_ad7177.h
new file mode 100755
index 0000000..de3863d
--- /dev/null
+++ b/include/video_ad7177.h
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _VIDEO_AD7177_H_
+#define _VIDEO_AD7177_H_
+
+/* #define VIDEO_DEBUG_DISABLE_COLORS	0 */
+
+#define VIDEO_ENCODER_NAME	"Analog Devices AD7177"
+
+#define VIDEO_ENCODER_I2C_RATE	100000	/* Max rate is 100 kHz		*/
+#define VIDEO_ENCODER_CB_Y_CR_Y		/* Use CB Y CR Y format...	*/
+
+#define VIDEO_MODE_YUYV		/* The only mode supported by this encoder */
+#undef	VIDEO_MODE_RGB
+#define VIDEO_MODE_BPP		16
+
+#ifdef	VIDEO_MODE_PAL
+#define VIDEO_ACTIVE_COLS	720
+#define VIDEO_ACTIVE_ROWS	576
+#define VIDEO_VISIBLE_COLS	640
+#define VIDEO_VISIBLE_ROWS	480
+#endif
+
+#ifdef	VIDEO_MODE_NTSC
+#define VIDEO_ACTIVE_COLS	720
+#define VIDEO_ACTIVE_ROWS	525
+#define VIDEO_VISIBLE_COLS	640
+#define VIDEO_VISIBLE_ROWS	400
+#endif
+
+static unsigned char
+    video_encoder_data[] = {
+#ifdef VIDEO_MODE_NTSC
+					0x04, /* Mode Register 0	*/
+#ifdef VIDEO_DEBUG_COLORBARS
+					0xc2,
+#else
+					0x42, /* Mode Register 1	*/
+#endif	/* VIDEO_DEBUG_COLORBARS */
+					0x16, /* Subcarrier Freq 0	*/
+					0x7c, /* Subcarrier Freq 1	*/
+					0xf0, /* Subcarrier Freq 2	*/
+					0x21, /* Subcarrier Freq 3	*/
+					0x00, /* Subcarrier phase	*/
+					0x02, /* Timing Register 0	*/
+					0x00, /* Extended Captioning 0	*/
+					0x00, /* Extended Captioning 1	*/
+					0x00, /* Closed Captioning 0	*/
+					0x00, /* Closed Captioning 1	*/
+					0x00, /* Timing Register 1	*/
+					0x08, /* Mode Register 2	*/
+					0x00, /* Pedestal Register 0	*/
+					0x00, /* Pedestal Register 1	*/
+					0x00, /* Pedestal Register 2	*/
+					0x00, /* Pedestal Register 3	*/
+					0x08, /* Mode Register 3	*/
+
+#endif	/* VIDEO_MODE_NTSC */
+
+#ifdef VIDEO_MODE_PAL
+#ifdef VIDEO_MODE_RGB_OUT
+
+					0x69, /* Mode Register 0	*/
+#ifdef VIDEO_DEBUG_COLORBARS
+					0xc0, /* Mode Register 1 (c0)	*/
+#else
+					0x40, /* Mode Register 1 (c0)	*/
+#endif	/* VIDEO_DEBUG_COLORBARS */
+					0xcb, /* Subcarrier Freq 0	*/
+					0x8a, /* Subcarrier Freq 1	*/
+					0x09, /* Subcarrier Freq 2	*/
+					0x2a, /* Subcarrier Freq 3	*/
+					0x00, /* Subcarrier phase	*/
+					0x02, /* Timing Register 0	*/
+					0x00, /* Extended Captioning 0	*/
+					0x00, /* Extended Captioning 1	*/
+					0x00, /* Closed Captioning 0	*/
+					0x00, /* Closed Captioning 1	*/
+					0x00, /* Timing Register 1	*/
+					0x28, /* Mode Register 2	*/
+					0x00, /* Pedestal Register 0	*/
+					0x00, /* Pedestal Register 1	*/
+					0x00, /* Pedestal Register 2	*/
+					0x00, /* Pedestal Register 3	*/
+					0x08, /* Mode Register 3	*/
+
+#else	/* ! VIDEO_MODE_RGB_OUT */
+
+					0x09, /* Mode Register 0 (was 01) */
+#ifdef VIDEO_DEBUG_COLORBARS
+					0xd8, /*			*/
+#else
+					0x59, /* Mode Register 1 (was 58) */
+#endif	/* VIDEO_DEBUG_COLORBARS */
+					0xcb, /* Subcarrier Freq 0	*/
+					0x8a, /* Subcarrier Freq 1	*/
+					0x09, /* Subcarrier Freq 2	*/
+					0x2a, /* Subcarrier Freq 3	*/
+					0x00, /* Subcarrier phase	*/
+					0x02, /* Timing Register 0 (was a) */
+					0x00, /* Extended Captioning 0	*/
+					0x00, /* Extended Captioning 1	*/
+					0x00, /* Closed Captioning 0	*/
+					0x00, /* Closed Captioning 1	*/
+					0x00, /* Timing Register 1	*/
+#ifdef VIDEO_DEBUG_LOWPOWER
+#ifdef VIDEO_DEBUG_DISABLE_COLORS
+					0x98, /* Mode Register 2	*/
+#else
+					0x88, /* Mode Register 2	*/
+#endif	/* VIDEO_DEBUG_DISABLE_COLORS */
+#else	/* ! VIDEO_DEBUG_LOWPOWER */
+#ifdef VIDEO_DEBUG_DISABLE_COLORS
+					0x18, /* Mode Register 2	*/
+#else
+					0x08, /* Mode Register 2	*/
+#endif	/* VIDEO_DEBUG_DISABLE_COLORS */
+#endif	/* VIDEO_DEBUG_LOWPOWER */
+					0x00, /* Pedestal Register 0	*/
+					0x00, /* Pedestal Register 1	*/
+					0x00, /* Pedestal Register 2	*/
+					0x00, /* Pedestal Register 3	*/
+					0x08  /* Mode Register 3	*/
+#endif	/* VIDEO_MODE_RGB_OUT */
+#endif	/* VIDEO_MODE_PAL */
+    } ;
+
+#endif	/* _VIDEO_AD7177_H_ */
diff --git a/include/video_ad7179.h b/include/video_ad7179.h
new file mode 100755
index 0000000..6a1ec86
--- /dev/null
+++ b/include/video_ad7179.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _VIDEO_AD7179_H_
+#define _VIDEO_AD7179_H_
+
+/*
+ * The video encoder data are board specific now!
+ */
+
+#if defined(CONFIG_RRVISION)
+#include "../board/RRvision/video_ad7179.h"
+#else
+#error "Please provide a board-specific video_ad7179.h"
+#endif
+
+#endif /* _VIDEO_AD7179_H_ */
diff --git a/include/video_easylogo.h b/include/video_easylogo.h
new file mode 100755
index 0000000..1e00818
--- /dev/null
+++ b/include/video_easylogo.h
@@ -0,0 +1,26 @@
+/*
+** video easylogo
+** ==============
+** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
+** AIRVENT SAM s.p.a - RIMINI(ITALY)
+**
+** This utility is still under construction!
+*/
+
+#ifndef _EASYLOGO_H_
+#define _EASYLOGO_H_
+
+#if 0
+#define ENABLE_ASCII_BANNERS
+#endif
+
+typedef struct {
+	unsigned char 	*data;
+	int		width;
+	int		height;
+	int		bpp;
+	int		pixel_size;
+	int		size;
+} fastimage_t ;
+
+#endif	/* _EASYLOGO_H_ */
diff --git a/include/video_fb.h b/include/video_fb.h
new file mode 100755
index 0000000..9825f0c
--- /dev/null
+++ b/include/video_fb.h
@@ -0,0 +1,115 @@
+										    /*
+ * (C) Copyright 1997-2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * smiLynxEM.h
+ * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator
+ *
+ *
+ *  modification history
+ *  --------------------
+ *  04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>.
+ */
+
+#ifndef _VIDEO_FB_H_
+#define _VIDEO_FB_H_
+
+#define CONSOLE_BG_COL            0x00
+#define CONSOLE_FG_COL            0xa0
+
+/*
+ * Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT
+ */
+#define GDF__8BIT_INDEX         0
+#define GDF_15BIT_555RGB        1
+#define GDF_16BIT_565RGB        2
+#define GDF_32BIT_X888RGB       3
+#define GDF_24BIT_888RGB        4
+#define GDF__8BIT_332RGB        5
+
+/******************************************************************************/
+/* Export Graphic Driver Control                                              */
+/******************************************************************************/
+
+typedef struct {
+    unsigned int isaBase;
+    unsigned int pciBase;
+    unsigned int dprBase;
+    unsigned int vprBase;
+    unsigned int cprBase;
+    unsigned int frameAdrs;
+    unsigned int memSize;
+    unsigned int mode;
+    unsigned int gdfIndex;
+    unsigned int gdfBytesPP;
+    unsigned int fg;
+    unsigned int bg;
+    unsigned int plnSizeX;
+    unsigned int plnSizeY;
+    unsigned int winSizeX;
+    unsigned int winSizeY;
+    char modeIdent[80];
+} GraphicDevice;
+
+
+/******************************************************************************/
+/* Export Graphic Functions                                                   */
+/******************************************************************************/
+
+void *video_hw_init (void);       /* returns GraphicDevice struct or NULL */
+
+#ifdef VIDEO_HW_BITBLT
+void video_hw_bitblt (
+    unsigned int bpp,             /* bytes per pixel */
+    unsigned int src_x,           /* source pos x */
+    unsigned int src_y,           /* source pos y */
+    unsigned int dst_x,           /* dest pos x */
+    unsigned int dst_y,           /* dest pos y */
+    unsigned int dim_x,           /* frame width */
+    unsigned int dim_y            /* frame height */
+    );
+#endif
+
+#ifdef VIDEO_HW_RECTFILL
+void video_hw_rectfill (
+    unsigned int bpp,             /* bytes per pixel */
+    unsigned int dst_x,           /* dest pos x */
+    unsigned int dst_y,           /* dest pos y */
+    unsigned int dim_x,           /* frame width */
+    unsigned int dim_y,           /* frame height */
+    unsigned int color            /* fill color */
+     );
+#endif
+
+void video_set_lut (
+    unsigned int index,           /* color number */
+    unsigned char r,              /* red */
+    unsigned char g,              /* green */
+    unsigned char b               /* blue */
+    );
+#ifdef CONFIG_VIDEO_HW_CURSOR
+void video_set_hw_cursor(int x, int y); /* x y in pixel */
+void video_init_hw_cursor(int font_width, int font_height);
+#endif
+
+#endif /*_VIDEO_FB_H_ */
diff --git a/include/video_font.h b/include/video_font.h
new file mode 100755
index 0000000..706e185
--- /dev/null
+++ b/include/video_font.h
@@ -0,0 +1,4644 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _VIDEO_FONT_
+#define _VIDEO_FONT_
+
+#define VIDEO_FONT_CHARS	256
+#define VIDEO_FONT_WIDTH	8
+#define VIDEO_FONT_HEIGHT	16
+#define VIDEO_FONT_SIZE		(VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT)
+
+static unsigned char video_fontdata[VIDEO_FONT_SIZE] = {
+
+	/* 0 0x00 '^@' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 1 0x01 '^A' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x81, /* 10000001 */
+	0xa5, /* 10100101 */
+	0x81, /* 10000001 */
+	0x81, /* 10000001 */
+	0xbd, /* 10111101 */
+	0x99, /* 10011001 */
+	0x81, /* 10000001 */
+	0x81, /* 10000001 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 2 0x02 '^B' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0xff, /* 11111111 */
+	0xdb, /* 11011011 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xc3, /* 11000011 */
+	0xe7, /* 11100111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 3 0x03 '^C' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x6c, /* 01101100 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0x7c, /* 01111100 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 4 0x04 '^D' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x7c, /* 01111100 */
+	0xfe, /* 11111110 */
+	0x7c, /* 01111100 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 5 0x05 '^E' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0xe7, /* 11100111 */
+	0xe7, /* 11100111 */
+	0xe7, /* 11100111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 6 0x06 '^F' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x7e, /* 01111110 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 7 0x07 '^G' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 8 0x08 '^H' */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xe7, /* 11100111 */
+	0xc3, /* 11000011 */
+	0xc3, /* 11000011 */
+	0xe7, /* 11100111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+
+	/* 9 0x09 '^I' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x42, /* 01000010 */
+	0x42, /* 01000010 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 10 0x0a '^J' */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xc3, /* 11000011 */
+	0x99, /* 10011001 */
+	0xbd, /* 10111101 */
+	0xbd, /* 10111101 */
+	0x99, /* 10011001 */
+	0xc3, /* 11000011 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+
+	/* 11 0x0b '^K' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1e, /* 00011110 */
+	0x0e, /* 00001110 */
+	0x1a, /* 00011010 */
+	0x32, /* 00110010 */
+	0x78, /* 01111000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 12 0x0c '^L' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 13 0x0d '^M' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3f, /* 00111111 */
+	0x33, /* 00110011 */
+	0x3f, /* 00111111 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x70, /* 01110000 */
+	0xf0, /* 11110000 */
+	0xe0, /* 11100000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 14 0x0e '^N' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7f, /* 01111111 */
+	0x63, /* 01100011 */
+	0x7f, /* 01111111 */
+	0x63, /* 01100011 */
+	0x63, /* 01100011 */
+	0x63, /* 01100011 */
+	0x63, /* 01100011 */
+	0x67, /* 01100111 */
+	0xe7, /* 11100111 */
+	0xe6, /* 11100110 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 15 0x0f '^O' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xdb, /* 11011011 */
+	0x3c, /* 00111100 */
+	0xe7, /* 11100111 */
+	0x3c, /* 00111100 */
+	0xdb, /* 11011011 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 16 0x10 '^P' */
+	0x00, /* 00000000 */
+	0x80, /* 10000000 */
+	0xc0, /* 11000000 */
+	0xe0, /* 11100000 */
+	0xf0, /* 11110000 */
+	0xf8, /* 11111000 */
+	0xfe, /* 11111110 */
+	0xf8, /* 11111000 */
+	0xf0, /* 11110000 */
+	0xe0, /* 11100000 */
+	0xc0, /* 11000000 */
+	0x80, /* 10000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 17 0x11 '^Q' */
+	0x00, /* 00000000 */
+	0x02, /* 00000010 */
+	0x06, /* 00000110 */
+	0x0e, /* 00001110 */
+	0x1e, /* 00011110 */
+	0x3e, /* 00111110 */
+	0xfe, /* 11111110 */
+	0x3e, /* 00111110 */
+	0x1e, /* 00011110 */
+	0x0e, /* 00001110 */
+	0x06, /* 00000110 */
+	0x02, /* 00000010 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 18 0x12 '^R' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 19 0x13 '^S' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 20 0x14 '^T' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7f, /* 01111111 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0x7b, /* 01111011 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 21 0x15 '^U' */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0x60, /* 01100000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x0c, /* 00001100 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 22 0x16 '^V' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 23 0x17 '^W' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 24 0x18 '^X' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 25 0x19 '^Y' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 26 0x1a '^Z' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0xfe, /* 11111110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 27 0x1b '^[' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xfe, /* 11111110 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 28 0x1c '^\' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 29 0x1d '^]' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x28, /* 00101000 */
+	0x6c, /* 01101100 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x28, /* 00101000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 30 0x1e '^^' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x7c, /* 01111100 */
+	0x7c, /* 01111100 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 31 0x1f '^_' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0x7c, /* 01111100 */
+	0x7c, /* 01111100 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 32 0x20 ' ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 33 0x21 '!' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 34 0x22 '"' */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x24, /* 00100100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 35 0x23 '#' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 36 0x24 '$' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc2, /* 11000010 */
+	0xc0, /* 11000000 */
+	0x7c, /* 01111100 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x86, /* 10000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 37 0x25 '%' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc2, /* 11000010 */
+	0xc6, /* 11000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc6, /* 11000110 */
+	0x86, /* 10000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 38 0x26 '&' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 39 0x27 ''' */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 40 0x28 '(' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 41 0x29 ')' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 42 0x2a '*' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0xff, /* 11111111 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 43 0x2b '+' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 44 0x2c ',' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 45 0x2d '-' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 46 0x2e '.' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 47 0x2f '/' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x02, /* 00000010 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0x80, /* 10000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 48 0x30 '0' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 49 0x31 '1' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x38, /* 00111000 */
+	0x78, /* 01111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 50 0x32 '2' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 51 0x33 '3' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x3c, /* 00111100 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 52 0x34 '4' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x1c, /* 00011100 */
+	0x3c, /* 00111100 */
+	0x6c, /* 01101100 */
+	0xcc, /* 11001100 */
+	0xfe, /* 11111110 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x1e, /* 00011110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 53 0x35 '5' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xfc, /* 11111100 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 54 0x36 '6' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xfc, /* 11111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 55 0x37 '7' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 56 0x38 '8' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 57 0x39 '9' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7e, /* 01111110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 58 0x3a ':' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 59 0x3b ';' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 60 0x3c '<' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x06, /* 00000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 61 0x3d '=' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 62 0x3e '>' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 63 0x3f '?' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 64 0x40 '@' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xde, /* 11011110 */
+	0xde, /* 11011110 */
+	0xde, /* 11011110 */
+	0xdc, /* 11011100 */
+	0xc0, /* 11000000 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 65 0x41 'A' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 66 0x42 'B' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfc, /* 11111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0xfc, /* 11111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 67 0x43 'C' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0xc2, /* 11000010 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc2, /* 11000010 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 68 0x44 'D' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xf8, /* 11111000 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0xf8, /* 11111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 69 0x45 'E' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x66, /* 01100110 */
+	0x62, /* 01100010 */
+	0x68, /* 01101000 */
+	0x78, /* 01111000 */
+	0x68, /* 01101000 */
+	0x60, /* 01100000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 70 0x46 'F' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x66, /* 01100110 */
+	0x62, /* 01100010 */
+	0x68, /* 01101000 */
+	0x78, /* 01111000 */
+	0x68, /* 01101000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 71 0x47 'G' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0xc2, /* 11000010 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xde, /* 11011110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x66, /* 01100110 */
+	0x3a, /* 00111010 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 72 0x48 'H' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 73 0x49 'I' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 74 0x4a 'J' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1e, /* 00011110 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 75 0x4b 'K' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xe6, /* 11100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0x78, /* 01111000 */
+	0x78, /* 01111000 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0xe6, /* 11100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 76 0x4c 'L' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xf0, /* 11110000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 77 0x4d 'M' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xee, /* 11101110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xd6, /* 11010110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 78 0x4e 'N' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xe6, /* 11100110 */
+	0xf6, /* 11110110 */
+	0xfe, /* 11111110 */
+	0xde, /* 11011110 */
+	0xce, /* 11001110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 79 0x4f 'O' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 80 0x50 'P' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfc, /* 11111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 81 0x51 'Q' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xd6, /* 11010110 */
+	0xde, /* 11011110 */
+	0x7c, /* 01111100 */
+	0x0c, /* 00001100 */
+	0x0e, /* 00001110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 82 0x52 'R' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfc, /* 11111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0xe6, /* 11100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 83 0x53 'S' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x60, /* 01100000 */
+	0x38, /* 00111000 */
+	0x0c, /* 00001100 */
+	0x06, /* 00000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 84 0x54 'T' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x5a, /* 01011010 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 85 0x55 'U' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 86 0x56 'V' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 87 0x57 'W' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xfe, /* 11111110 */
+	0xee, /* 11101110 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 88 0x58 'X' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x7c, /* 01111100 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x7c, /* 01111100 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 89 0x59 'Y' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 90 0x5a 'Z' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0x86, /* 10000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc2, /* 11000010 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 91 0x5b '[' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 92 0x5c '\' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x80, /* 10000000 */
+	0xc0, /* 11000000 */
+	0xe0, /* 11100000 */
+	0x70, /* 01110000 */
+	0x38, /* 00111000 */
+	0x1c, /* 00011100 */
+	0x0e, /* 00001110 */
+	0x06, /* 00000110 */
+	0x02, /* 00000010 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 93 0x5d ']' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 94 0x5e '^' */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 95 0x5f '_' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 96 0x60 '`' */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 97 0x61 'a' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 98 0x62 'b' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xe0, /* 11100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x78, /* 01111000 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 99 0x63 'c' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 100 0x64 'd' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1c, /* 00011100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x3c, /* 00111100 */
+	0x6c, /* 01101100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 101 0x65 'e' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 102 0x66 'f' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1c, /* 00011100 */
+	0x36, /* 00110110 */
+	0x32, /* 00110010 */
+	0x30, /* 00110000 */
+	0x78, /* 01111000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 103 0x67 'g' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x7c, /* 01111100 */
+	0x0c, /* 00001100 */
+	0xcc, /* 11001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+
+	/* 104 0x68 'h' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xe0, /* 11100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x6c, /* 01101100 */
+	0x76, /* 01110110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0xe6, /* 11100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 105 0x69 'i' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 106 0x6a 'j' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x00, /* 00000000 */
+	0x0e, /* 00001110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+
+	/* 107 0x6b 'k' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xe0, /* 11100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0x78, /* 01111000 */
+	0x78, /* 01111000 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0xe6, /* 11100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 108 0x6c 'l' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 109 0x6d 'm' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xec, /* 11101100 */
+	0xfe, /* 11111110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 110 0x6e 'n' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xdc, /* 11011100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 111 0x6f 'o' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 112 0x70 'p' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xdc, /* 11011100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x00, /* 00000000 */
+
+	/* 113 0x71 'q' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x7c, /* 01111100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x1e, /* 00011110 */
+	0x00, /* 00000000 */
+
+	/* 114 0x72 'r' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xdc, /* 11011100 */
+	0x76, /* 01110110 */
+	0x66, /* 01100110 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 115 0x73 's' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0x60, /* 01100000 */
+	0x38, /* 00111000 */
+	0x0c, /* 00001100 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 116 0x74 't' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0xfc, /* 11111100 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x36, /* 00110110 */
+	0x1c, /* 00011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 117 0x75 'u' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 118 0x76 'v' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 119 0x77 'w' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 120 0x78 'x' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 121 0x79 'y' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7e, /* 01111110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0xf8, /* 11111000 */
+	0x00, /* 00000000 */
+
+	/* 122 0x7a 'z' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xcc, /* 11001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 123 0x7b '{' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0e, /* 00001110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x70, /* 01110000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x0e, /* 00001110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 124 0x7c '|' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 125 0x7d '}' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x70, /* 01110000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x0e, /* 00001110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 126 0x7e '~' */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 127 0x7f '' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 128 0x80 '€' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0xc2, /* 11000010 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc2, /* 11000010 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 129 0x81 '�' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 130 0x82 '‚' */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 131 0x83 'ƒ' */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 132 0x84 '„' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 133 0x85 '…' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 134 0x86 '†' */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 135 0x87 '‡' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x18, /* 00011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 136 0x88 'ˆ' */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 137 0x89 '‰' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 138 0x8a 'Š' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 139 0x8b '‹' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 140 0x8c 'Œ' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 141 0x8d '�' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 142 0x8e 'Ž' */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 143 0x8f '�' */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 144 0x90 '�' */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x66, /* 01100110 */
+	0x62, /* 01100010 */
+	0x68, /* 01101000 */
+	0x78, /* 01111000 */
+	0x68, /* 01101000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 145 0x91 '‘' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xec, /* 11101100 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x7e, /* 01111110 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0x6e, /* 01101110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 146 0x92 '’' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3e, /* 00111110 */
+	0x6c, /* 01101100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xfe, /* 11111110 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xce, /* 11001110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 147 0x93 '“' */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 148 0x94 '”' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 149 0x95 '•' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 150 0x96 '–' */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x78, /* 01111000 */
+	0xcc, /* 11001100 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 151 0x97 '—' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 152 0x98 '˜' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7e, /* 01111110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+
+	/* 153 0x99 '™' */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 154 0x9a 'š' */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 155 0x9b '›' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 156 0x9c 'œ' */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x64, /* 01100100 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xe6, /* 11100110 */
+	0xfc, /* 11111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 157 0x9d '�' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 158 0x9e 'ž' */
+	0x00, /* 00000000 */
+	0xf8, /* 11111000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xf8, /* 11111000 */
+	0xc4, /* 11000100 */
+	0xcc, /* 11001100 */
+	0xde, /* 11011110 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 159 0x9f 'Ÿ' */
+	0x00, /* 00000000 */
+	0x0e, /* 00001110 */
+	0x1b, /* 00011011 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xd8, /* 11011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 160 0xa0 ' ' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 161 0xa1 '¡' */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 162 0xa2 '¢' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 163 0xa3 '£' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 164 0xa4 '¤' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0xdc, /* 11011100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 165 0xa5 '¥' */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xe6, /* 11100110 */
+	0xf6, /* 11110110 */
+	0xfe, /* 11111110 */
+	0xde, /* 11011110 */
+	0xce, /* 11001110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 166 0xa6 '¦' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x3e, /* 00111110 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 167 0xa7 '§' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 168 0xa8 '¨' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 169 0xa9 '©' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 170 0xaa 'ª' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 171 0xab '«' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0xe0, /* 11100000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xdc, /* 11011100 */
+	0x86, /* 10000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x3e, /* 00111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 172 0xac '¬' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0xe0, /* 11100000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x66, /* 01100110 */
+	0xce, /* 11001110 */
+	0x9a, /* 10011010 */
+	0x3f, /* 00111111 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 173 0xad '­' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 174 0xae '®' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x36, /* 00110110 */
+	0x6c, /* 01101100 */
+	0xd8, /* 11011000 */
+	0x6c, /* 01101100 */
+	0x36, /* 00110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 175 0xaf '¯' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xd8, /* 11011000 */
+	0x6c, /* 01101100 */
+	0x36, /* 00110110 */
+	0x6c, /* 01101100 */
+	0xd8, /* 11011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 176 0xb0 '°' */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+
+	/* 177 0xb1 '±' */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+
+	/* 178 0xb2 '²' */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+
+	/* 179 0xb3 '³' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 180 0xb4 '´' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 181 0xb5 'µ' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 182 0xb6 '¶' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf6, /* 11110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 183 0xb7 '·' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 184 0xb8 '¸' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 185 0xb9 '¹' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf6, /* 11110110 */
+	0x06, /* 00000110 */
+	0xf6, /* 11110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 186 0xba 'º' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 187 0xbb '»' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x06, /* 00000110 */
+	0xf6, /* 11110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 188 0xbc '¼' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf6, /* 11110110 */
+	0x06, /* 00000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 189 0xbd '½' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 190 0xbe '¾' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 191 0xbf '¿' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 192 0xc0 'À' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 193 0xc1 'Á' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 194 0xc2 'Â' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 195 0xc3 'Ã' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 196 0xc4 'Ä' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 197 0xc5 'Å' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 198 0xc6 'Æ' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 199 0xc7 'Ç' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x37, /* 00110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 200 0xc8 'È' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x37, /* 00110111 */
+	0x30, /* 00110000 */
+	0x3f, /* 00111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 201 0xc9 'É' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3f, /* 00111111 */
+	0x30, /* 00110000 */
+	0x37, /* 00110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 202 0xca 'Ê' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf7, /* 11110111 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 203 0xcb 'Ë' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0xf7, /* 11110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 204 0xcc 'Ì' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x37, /* 00110111 */
+	0x30, /* 00110000 */
+	0x37, /* 00110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 205 0xcd 'Í' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 206 0xce 'Î' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf7, /* 11110111 */
+	0x00, /* 00000000 */
+	0xf7, /* 11110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 207 0xcf 'Ï' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 208 0xd0 'Ð' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 209 0xd1 'Ñ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 210 0xd2 'Ò' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 211 0xd3 'Ó' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x3f, /* 00111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 212 0xd4 'Ô' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 213 0xd5 'Õ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 214 0xd6 'Ö' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3f, /* 00111111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 215 0xd7 '×' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xff, /* 11111111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 216 0xd8 'Ø' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 217 0xd9 'Ù' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 218 0xda 'Ú' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 219 0xdb 'Û' */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+
+	/* 220 0xdc 'Ü' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+
+	/* 221 0xdd 'Ý' */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+
+	/* 222 0xde 'Þ' */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+
+	/* 223 0xdf 'ß' */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 224 0xe0 'à' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xdc, /* 11011100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 225 0xe1 'á' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xd8, /* 11011000 */
+	0xcc, /* 11001100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xcc, /* 11001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 226 0xe2 'â' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 227 0xe3 'ã' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 228 0xe4 'ä' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 229 0xe5 'å' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 230 0xe6 'æ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+
+	/* 231 0xe7 'ç' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 232 0xe8 'è' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 233 0xe9 'é' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 234 0xea 'ê' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0xee, /* 11101110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 235 0xeb 'ë' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1e, /* 00011110 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x3e, /* 00111110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 236 0xec 'ì' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 237 0xed 'í' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x03, /* 00000011 */
+	0x06, /* 00000110 */
+	0x7e, /* 01111110 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0xf3, /* 11110011 */
+	0x7e, /* 01111110 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 238 0xee 'î' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1c, /* 00011100 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x7c, /* 01111100 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x1c, /* 00011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 239 0xef 'ï' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 240 0xf0 'ð' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 241 0xf1 'ñ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 242 0xf2 'ò' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 243 0xf3 'ó' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 244 0xf4 'ô' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0e, /* 00001110 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 245 0xf5 'õ' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 246 0xf6 'ö' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 247 0xf7 '÷' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 248 0xf8 'ø' */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 249 0xf9 'ù' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 250 0xfa 'ú' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 251 0xfb 'û' */
+	0x00, /* 00000000 */
+	0x0f, /* 00001111 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0xec, /* 11101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x3c, /* 00111100 */
+	0x1c, /* 00011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 252 0xfc 'ü' */
+	0x00, /* 00000000 */
+	0x6c, /* 01101100 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 253 0xfd 'ý' */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x32, /* 00110010 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 254 0xfe 'þ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 255 0xff 'ÿ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+};
+
+#endif
diff --git a/include/video_logo.h b/include/video_logo.h
new file mode 100755
index 0000000..c12e8f8
--- /dev/null
+++ b/include/video_logo.h
@@ -0,0 +1,1951 @@
+/* */
+/* Generated by EasyLogo, (C) 2000 by Paolo Scaffardi */
+/* */
+/* To use this, include it and call: easylogo_plot(screen,&u_boot_logo, width,x,y) */
+/* */
+/* Where:	'screen'	is the pointer to the frame buffer */
+/* 		'width'	is the screen width */
+/* 		'x'		is the horizontal position */
+/* 		'y'		is the vertical position */
+/* */
+
+#include <video_easylogo.h>
+
+#define	DEF_U_BOOT_LOGO_WIDTH		160
+#define	DEF_U_BOOT_LOGO_HEIGHT		96
+#define	DEF_U_BOOT_LOGO_PIXELS		15360
+#define	DEF_U_BOOT_LOGO_BPP		16
+#define	DEF_U_BOOT_LOGO_PIXEL_SIZE	2
+#define	DEF_U_BOOT_LOGO_SIZE		30720
+
+unsigned char DEF_U_BOOT_LOGO_DATA[DEF_U_BOOT_LOGO_SIZE] = {
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6,
+ 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7c, 0x4b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7c, 0x69, 0x80, 0xd5, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xb6, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7c, 0x69, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa1, 0xa5, 0x70, 0xcc, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x6d, 0xc7, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x69,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0x96, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0x96, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x55, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xa0,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0x96, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x84, 0xdb, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x91, 0xc3, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xc0, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0x96,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7e, 0x96, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7d, 0x80, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xa0, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x75, 0xd1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0xdb, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x91, 0xc3, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0xa7, 0x9a, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x51, 0xa5, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x51, 0xa5, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x69, 0x7f, 0x8b, 0x7d, 0x75, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xb6, 0x80, 0xe1, 0x7e, 0xaa, 0x7c, 0x69, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xb6,
+ 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xb6, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0xdb, 0x8f, 0xc7,
+ 0x54, 0xa9, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x54, 0xa9, 0x8c, 0xcc,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7c, 0x69, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7d, 0x75, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xa0, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x89, 0xd1, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x59, 0xae, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x69, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xc0, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7d, 0x80, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xd5, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xaa, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x89, 0xd1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x69, 0xc3, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x8f, 0xc7, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xd5, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xd5, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7c, 0x4b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x4c, 0x9f, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7c, 0x55, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xca, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x8c, 0xcc, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x9e, 0xa9, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa7, 0x9a, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa1, 0xa5, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0x96, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x9e, 0xa9, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x9e, 0xa9, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x8c, 0xcc, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xd5, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x4c, 0x9f, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x7c, 0xdb, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xca, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7e, 0x96, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xca, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0xa1, 0xa5, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa7, 0x9a, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7d, 0x80, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7c, 0xdb, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xca, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xd5, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7d, 0x80, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x7c, 0xdb, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x4c, 0x9f, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0x9d, 0xae, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xca, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0x96,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7d, 0x75, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xa0,
+ 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7d, 0x80, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0xdb, 0x97, 0xb8,
+ 0x51, 0xa5, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x51, 0xa5, 0x94, 0xbd,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7b, 0x60, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x7c, 0xdb, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7c, 0xdb, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x8c, 0xcc, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0xa7, 0x9a, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7b, 0x60, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x78, 0xd6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0xdb, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7c, 0x4b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xc0,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7c, 0x4b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xd5,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0x8c, 0xcc, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x89, 0xd1, 0x45, 0x95, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xb6,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xca, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x55, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa7, 0x9a,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x75, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0xa9, 0x95,
+ 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0x84, 0xdb, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x8f, 0xc7, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95, 0x45, 0x95, 0xa9, 0x95,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7c, 0x69, 0x7a, 0x3f, 0x7c, 0x4b, 0x7c, 0x69,
+ 0x7e, 0xaa, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7f, 0x8b, 0x7f, 0x8b, 0x7e, 0xaa, 0x80, 0xb6, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x75, 0xd1, 0x97, 0xb8,
+ 0x70, 0xcc, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x70, 0xcc, 0x97, 0xb8,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7d, 0x80, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f,
+ 0x80, 0xd5, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x69, 0x7c, 0x69, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x69, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7c, 0x55, 0x7a, 0x3f, 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7b, 0x60, 0x7c, 0x69, 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7e, 0x96, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x7c, 0x69, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f,
+ 0x7d, 0x80, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x7c, 0x4b,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7e, 0xa0, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xca, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x55,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7d, 0x75,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x75, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xca, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x80, 0xb6,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x80, 0xb6, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xb6,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x80, 0xd5, 0x7c, 0x55, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0x96, 0x7a, 0x3f, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f,
+ 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xb6,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x75, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7c, 0x69, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xb6,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x69,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0x96, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xb6,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xa0,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7b, 0x60, 0x7a, 0x3f, 0x7e, 0xaa, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xa0, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7d, 0x80, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7d, 0x75, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x7f, 0x8b,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xd5, 0x7a, 0x3f, 0x7c, 0x55, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7c, 0x55,
+ 0x7c, 0x4b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xc0, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x7d, 0x80, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7e, 0xaa, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xca, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7b, 0x60,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7b, 0x60, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7c, 0x69,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x7e, 0x96,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xca, 0x7a, 0x3f, 0x7d, 0x75, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x69, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f,
+ 0x7c, 0x69, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xc0, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x7c, 0x69, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7e, 0xaa, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xc0, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7b, 0x60, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7d, 0x80, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7f, 0x8b, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7b, 0x60, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xd5, 0x7a, 0x3f, 0x7d, 0x80, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x4b, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x7c, 0x69,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7c, 0x69, 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1
+};
+
+fastimage_t u_boot_logo = {
+		DEF_U_BOOT_LOGO_DATA,
+		DEF_U_BOOT_LOGO_WIDTH,
+		DEF_U_BOOT_LOGO_HEIGHT,
+		DEF_U_BOOT_LOGO_BPP,
+		DEF_U_BOOT_LOGO_PIXEL_SIZE,
+		DEF_U_BOOT_LOGO_SIZE
+};
diff --git a/include/virtex2.h b/include/virtex2.h
new file mode 100755
index 0000000..f59227b
--- /dev/null
+++ b/include/virtex2.h
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _VIRTEX2_H_
+#define _VIRTEX2_H_
+
+#include <xilinx.h>
+
+extern int Virtex2_load( Xilinx_desc *desc, void *image, size_t size );
+extern int Virtex2_dump( Xilinx_desc *desc, void *buf, size_t bsize );
+extern int Virtex2_info( Xilinx_desc *desc );
+extern int Virtex2_reloc( Xilinx_desc *desc, ulong reloc_off );
+
+/*
+ * Slave SelectMap Implementation function table.
+ */
+typedef struct {
+	Xilinx_pre_fn	pre;
+	Xilinx_pgm_fn	pgm;
+	Xilinx_init_fn	init;
+	Xilinx_err_fn	err;
+	Xilinx_done_fn	done;
+	Xilinx_clk_fn	clk;
+	Xilinx_cs_fn	cs;
+	Xilinx_wr_fn	wr;
+	Xilinx_rdata_fn	rdata;
+	Xilinx_wdata_fn	wdata;
+	Xilinx_busy_fn	busy;
+	Xilinx_abort_fn	abort;
+	Xilinx_post_fn	post;
+	int           	relocated;
+} Xilinx_Virtex2_Slave_SelectMap_fns;
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	Xilinx_pgm_fn	pgm;
+	Xilinx_clk_fn	clk;
+	Xilinx_rdata_fn	rdata;
+	Xilinx_wdata_fn	wdata;
+	int           	relocated;
+} Xilinx_Virtex2_Slave_Serial_fns;
+
+/* Device Image Sizes (in bytes)
+ *********************************************************************/
+#define XILINX_XC2V40_SIZE		(338208 / 8)
+#define XILINX_XC2V80_SIZE		(597408 / 8)
+#define XILINX_XC2V250_SIZE		(1591584 / 8)
+#define XILINX_XC2V500_SIZE		(2557857 / 8)
+#define XILINX_XC2V1000_SIZE	(3749408 / 8)
+#define XILINX_XC2V1500_SIZE	(5166240 / 8)
+#define XILINX_XC2V2000_SIZE	(6808352 / 8)
+#define XILINX_XC2V3000_SIZE	(9589408 / 8)
+#define XILINX_XC2V4000_SIZE	(14220192 / 8)
+#define XILINX_XC2V6000_SIZE	(19752096 / 8)
+#define XILINX_XC2V8000_SIZE	(26185120 / 8)
+#define XILINX_XC2V10000_SIZE	(33519264 / 8)
+
+/* Descriptor Macros
+ *********************************************************************/
+#define XILINX_XC2V40_DESC(iface, fn_table, cookie)	\
+{ Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie }
+
+#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
+{ Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie }
+
+#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
+{ Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie }
+
+#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
+{ Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie }
+
+#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie }
+
+#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
+{ Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie }
+
+#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie }
+
+#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie }
+
+#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie }
+
+#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie }
+
+#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie }
+
+#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
+{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
+
+#endif /* _VIRTEX2_H_ */
+
+/* vim: set ts=4 tw=78: */
diff --git a/include/w83c553f.h b/include/w83c553f.h
new file mode 100755
index 0000000..88ea9da
--- /dev/null
+++ b/include/w83c553f.h
@@ -0,0 +1,178 @@
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+ /* winbond access routines and defines*/
+
+/* from the winbond data sheet -
+ The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
+ Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller.
+*/
+
+/*ISA bridge configuration space*/
+
+#define W83C553F_VID		0x10AD
+#define W83C553F_DID		0x0565
+
+#define WINBOND_PCICONTR	0x40  /*pci control reg*/
+#define WINBOND_SGBAR		0x41  /*scatter/gather base address reg*/
+#define WINBOND_LBCR		0x42  /*Line Buffer Control reg*/
+#define WINBOND_IDEIRCR		0x43  /*IDE Interrupt Routing Control  Reg*/
+#define WINBOND_PCIIRCR		0x44  /*PCI Interrupt Routing Control Reg*/
+#define WINBOND_BTBAR		0x46  /*BIOS Timer Base Address Register*/
+#define WINBOND_IPADCR		0x48  /*ISA to PCI Address Decoder Control Register*/
+#define WINBOND_IRADCR		0x49  /*ISA ROM Address Decoder Control Register*/
+#define WINBOND_IPMHSAR		0x4a  /*ISA to PCI Memory Hole STart Address Register*/
+#define WINBOND_IPMHSR		0x4b  /*ISA to PCI Memory Hols Size Register*/
+#define WINBOND_CDR			0x4c  /*Clock Divisor Register*/
+#define WINBOND_CSCR		0x4d  /*Chip Select Control Register*/
+#define WINBOND_ATSCR		0x4e  /*AT System Control register*/
+#define WINBOND_ATBCR		0x4f  /*AT Bus ControL Register*/
+#define WINBOND_IRQBEE0R	0x60  /*IRQ Break Event Enable 0 Register*/
+#define WINBOND_IRQBEE1R	0x61  /*IRQ Break Event Enable 1 Register*/
+#define WINBOND_ABEER		0x62  /*Additional Break Event Enable Register*/
+#define WINBOND_DMABEER		0x63  /*DMA Break Event Enable Register*/
+
+#define WINDOND_IDECSR		0x40  /*IDE Control/Status Register, Function 1*/
+
+#define IPADCR_MBE512		0x1
+#define IPADCR_MBE640		0x2
+#define IPADCR_IPATOM4		0x10
+#define IPADCR_IPATOM5		0x20
+#define IPADCR_IPATOM6		0x40
+#define IPADCR_IPATOM7		0x80
+
+#define CSCR_UBIOSCSE		0x10
+#define CSCR_BIOSWP			0x20
+
+#define IDECSR_P0EN			0x01
+#define IDECSR_P0F16		0x02
+#define IDECSR_P1EN			0x10
+#define IDECSR_P1F16		0x20
+#define IDECSR_LEGIRQ		0x800
+
+/*
+ * Interrupt controller
+ */
+#define W83C553F_PIC1_ICW1	CFG_ISA_IO + 0x20
+#define W83C553F_PIC1_ICW2	CFG_ISA_IO + 0x21
+#define W83C553F_PIC1_ICW3	CFG_ISA_IO + 0x21
+#define W83C553F_PIC1_ICW4	CFG_ISA_IO + 0x21
+#define W83C553F_PIC1_OCW1	CFG_ISA_IO + 0x21
+#define W83C553F_PIC1_OCW2	CFG_ISA_IO + 0x20
+#define W83C553F_PIC1_OCW3	CFG_ISA_IO + 0x20
+#define W83C553F_PIC1_ELC	CFG_ISA_IO + 0x4D0
+#define W83C553F_PIC2_ICW1	CFG_ISA_IO + 0xA0
+#define W83C553F_PIC2_ICW2	CFG_ISA_IO + 0xA1
+#define W83C553F_PIC2_ICW3	CFG_ISA_IO + 0xA1
+#define W83C553F_PIC2_ICW4	CFG_ISA_IO + 0xA1
+#define W83C553F_PIC2_OCW1	CFG_ISA_IO + 0xA1
+#define W83C553F_PIC2_OCW2	CFG_ISA_IO + 0xA0
+#define W83C553F_PIC2_OCW3	CFG_ISA_IO + 0xA0
+#define W83C553F_PIC2_ELC	CFG_ISA_IO + 0x4D1
+
+#define W83C553F_TMR1_CMOD	CFG_ISA_IO + 0x43
+
+/*
+ * DMA controller
+ */
+#define W83C553F_DMA1	CFG_ISA_IO + 0x000	/* channel 0 - 3 */
+#define W83C553F_DMA2	CFG_ISA_IO + 0x0C0	/* channel 4 - 7 */
+
+/* command/status register bit definitions */
+
+#define W83C553F_CS_COM_DACKAL	(1<<7)	/* DACK# assert level */
+#define W83C553F_CS_COM_DREQSAL	(1<<6)	/* DREQ sense assert level */
+#define W83C553F_CS_COM_GAP	(1<<4)	/* group arbitration priority */
+#define W83C553F_CS_COM_CGE	(1<<2)	/* channel group enable */
+
+#define W83C553F_CS_STAT_CH0REQ	(1<<4)	/* channel 0 (4) DREQ status */
+#define W83C553F_CS_STAT_CH1REQ	(1<<5)	/* channel 1 (5) DREQ status */
+#define W83C553F_CS_STAT_CH2REQ	(1<<6)	/* channel 2 (6) DREQ status */
+#define W83C553F_CS_STAT_CH3REQ	(1<<7)	/* channel 3 (7) DREQ status */
+
+#define W83C553F_CS_STAT_CH0TC	(1<<0)	/* channel 0 (4) TC status */
+#define W83C553F_CS_STAT_CH1TC	(1<<1)	/* channel 1 (5) TC status */
+#define W83C553F_CS_STAT_CH2TC	(1<<2)	/* channel 2 (6) TC status */
+#define W83C553F_CS_STAT_CH3TC	(1<<3)	/* channel 3 (7) TC status */
+
+/* mode register bit definitions */
+
+#define W83C553F_MODE_TM_DEMAND	(0<<6)	/* transfer mode - demand */
+#define W83C553F_MODE_TM_SINGLE	(1<<6)	/* transfer mode - single */
+#define W83C553F_MODE_TM_BLOCK	(2<<6)	/* transfer mode - block */
+#define W83C553F_MODE_TM_CASCADE	(3<<6)	/* transfer mode - cascade */
+#define W83C553F_MODE_ADDRDEC	(1<<5)	/* address increment/decrement select */
+#define W83C553F_MODE_AUTOINIT	(1<<4)	/* autoinitialize enable */
+#define W83C553F_MODE_TT_VERIFY	(0<<2)	/* transfer type - verify */
+#define W83C553F_MODE_TT_WRITE	(1<<2)	/* transfer type - write */
+#define W83C553F_MODE_TT_READ	(2<<2)	/* transfer type - read */
+#define W83C553F_MODE_TT_ILLEGAL	(3<<2)	/* transfer type - illegal */
+#define W83C553F_MODE_CH0SEL	(0<<0)	/* channel 0 (4) select */
+#define W83C553F_MODE_CH1SEL	(1<<0)	/* channel 1 (5) select */
+#define W83C553F_MODE_CH2SEL	(2<<0)	/* channel 2 (6) select */
+#define W83C553F_MODE_CH3SEL	(3<<0)	/* channel 3 (7) select */
+
+/* request register bit definitions */
+
+#define W83C553F_REQ_CHSERREQ	(1<<2)	/* channel service request */
+#define W83C553F_REQ_CH0SEL	(0<<0)	/* channel 0 (4) select */
+#define W83C553F_REQ_CH1SEL	(1<<0)	/* channel 1 (5) select */
+#define W83C553F_REQ_CH2SEL	(2<<0)	/* channel 2 (6) select */
+#define W83C553F_REQ_CH3SEL	(3<<0)	/* channel 3 (7) select */
+
+/* write single mask bit register bit definitions */
+
+#define W83C553F_WSMB_CHMASKSEL	(1<<2)	/* channel mask select */
+#define W83C553F_WSMB_CH0SEL	(0<<0)	/* channel 0 (4) select */
+#define W83C553F_WSMB_CH1SEL	(1<<0)	/* channel 1 (5) select */
+#define W83C553F_WSMB_CH2SEL	(2<<0)	/* channel 2 (6) select */
+#define W83C553F_WSMB_CH3SEL	(3<<0)	/* channel 3 (7) select */
+
+/* read/write all mask bits register bit definitions */
+
+#define W83C553F_RWAMB_CH0MASK	(1<<0)	/* channel 0 (4) mask */
+#define W83C553F_RWAMB_CH1MASK	(1<<1)	/* channel 1 (5) mask */
+#define W83C553F_RWAMB_CH2MASK	(1<<2)	/* channel 2 (6) mask */
+#define W83C553F_RWAMB_CH3MASK	(1<<3)	/* channel 3 (7) mask */
+
+/* typedefs */
+
+#define W83C553F_DMA1_CS		0x8
+#define W83C553F_DMA1_WR		0x9
+#define W83C553F_DMA1_WSMB		0xA
+#define W83C553F_DMA1_WM		0xB
+#define W83C553F_DMA1_CBP		0xC
+#define W83C553F_DMA1_MC		0xD
+#define W83C553F_DMA1_CM		0xE
+#define W83C553F_DMA1_RWAMB		0xF
+
+#define W83C553F_DMA2_CS		0x10
+#define W83C553F_DMA2_WR		0x12
+#define W83C553F_DMA2_WSMB		0x14
+#define W83C553F_DMA2_WM		0x16
+#define W83C553F_DMA2_CBP		0x18
+#define W83C553F_DMA2_MC		0x1A
+#define W83C553F_DMA2_CM		0x1C
+#define W83C553F_DMA2_RWAMB		0x1E
+
+void initialise_w83c553f(void);
diff --git a/include/watchdog.h b/include/watchdog.h
new file mode 100755
index 0000000..9265be9
--- /dev/null
+++ b/include/watchdog.h
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen,  Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Watchdog functions and macros.
+ */
+#ifndef _WATCHDOG_H_
+#define _WATCHDOG_H_
+
+#if defined(CONFIG_HW_WATCHDOG) && defined(CONFIG_WATCHDOG)
+#  error "Configuration error: CONFIG_HW_WATCHDOG and CONFIG_WATCHDOG can't be used together."
+#endif
+
+#if defined(__ASSEMBLY__) && defined(__NIOS__)
+#  error "Configuration error: WATCHDOG_RESET inside assembler not supported for Nios platforms."
+#endif
+
+/*
+ * Hardware watchdog
+ */
+#ifdef CONFIG_HW_WATCHDOG
+	#if defined(__ASSEMBLY__)
+		#define WATCHDOG_RESET bl hw_watchdog_reset
+	#else
+		extern void hw_watchdog_reset(void);
+
+		#define WATCHDOG_RESET hw_watchdog_reset
+	#endif /* __ASSEMBLY__ */
+#else
+	/*
+	 * Maybe a software watchdog?
+	 */
+	#if defined(CONFIG_WATCHDOG)
+		#if defined(__ASSEMBLY__)
+			#define WATCHDOG_RESET bl watchdog_reset
+		#else
+			extern void watchdog_reset(void);
+
+			#define WATCHDOG_RESET watchdog_reset
+		#endif
+	#else
+		/*
+		 * No hardware or software watchdog.
+		 */
+		#if defined(__ASSEMBLY__)
+			#define WATCHDOG_RESET /*XXX DO_NOT_DEL_THIS_COMMENT*/
+		#else
+			#define WATCHDOG_RESET() {}
+		#endif /* __ASSEMBLY__ */
+	#endif /* CONFIG_WATCHDOG && !__ASSEMBLY__ */
+#endif /* CONFIG_HW_WATCHDOG */
+
+/*
+ * Prototypes from $(CPU)/cpu.c.
+ */
+
+/* MPC 8xx */
+#if (defined(CONFIG_8xx) || defined(CONFIG_MPC860)) && !defined(__ASSEMBLY__)
+	void reset_8xx_watchdog(volatile immap_t *immr);
+#endif
+
+/* MPC 5xx */
+#if defined(CONFIG_5xx) && !defined(__ASSEMBLY__)
+	void reset_5xx_watchdog(volatile immap_t *immr);
+#endif
+
+/* AMCC 4xx */
+#if defined(CONFIG_4xx) && !defined(__ASSEMBLY__)
+	void reset_4xx_watchdog(void);
+#endif
+
+#endif /* _WATCHDOG_H_ */
diff --git a/include/xilinx.h b/include/xilinx.h
new file mode 100755
index 0000000..3704e1d
--- /dev/null
+++ b/include/xilinx.h
@@ -0,0 +1,105 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <fpga.h>
+
+#ifndef _XILINX_H_
+#define _XILINX_H_
+
+/* Xilinx Model definitions
+ *********************************************************************/
+#define CFG_SPARTAN2 			CFG_FPGA_DEV( 0x1 )
+#define CFG_VIRTEX_E 			CFG_FPGA_DEV( 0x2 )
+#define CFG_VIRTEX2	 			CFG_FPGA_DEV( 0x4 )
+#define CFG_SPARTAN3 			CFG_FPGA_DEV( 0x8 )
+#define CFG_XILINX_SPARTAN2 	(CFG_FPGA_XILINX | CFG_SPARTAN2)
+#define CFG_XILINX_VIRTEX_E 	(CFG_FPGA_XILINX | CFG_VIRTEX_E)
+#define CFG_XILINX_VIRTEX2	 	(CFG_FPGA_XILINX | CFG_VIRTEX2)
+#define CFG_XILINX_SPARTAN3 	(CFG_FPGA_XILINX | CFG_SPARTAN3)
+/* XXX - Add new models here */
+
+
+/* Xilinx Interface definitions
+ *********************************************************************/
+#define CFG_XILINX_IF_SS	CFG_FPGA_IF( 0x1 )	/* slave serial 	*/
+#define CFG_XILINX_IF_MS	CFG_FPGA_IF( 0x2 )	/* master serial	*/
+#define CFG_XILINX_IF_SP	CFG_FPGA_IF( 0x4 )	/* slave parallel 	*/
+#define CFG_XILINX_IF_JTAG	CFG_FPGA_IF( 0x8 )	/* jtag				*/
+#define CFG_XILINX_IF_MSM	CFG_FPGA_IF( 0x10 )	/* master selectmap	*/
+#define CFG_XILINX_IF_SSM	CFG_FPGA_IF( 0x20 )	/* slave selectmap	*/
+
+/* Xilinx types
+ *********************************************************************/
+typedef enum {					/* typedef Xilinx_iface	*/
+	min_xilinx_iface_type,		/* low range check value */
+    slave_serial,				/* serial data and external clock */
+    master_serial,				/* serial data w/ internal clock (not used) */
+    slave_parallel,				/* parallel data w/ external latch */
+    jtag_mode,					/* jtag/tap serial (not used ) */
+	master_selectmap,			/* master SelectMap (virtex2)		*/
+	slave_selectmap,			/* slave SelectMap (virtex2)		*/
+    max_xilinx_iface_type		/* insert all new types before this */
+} Xilinx_iface;					/* end, typedef Xilinx_iface */
+
+typedef enum {					/* typedef Xilinx_Family */
+	min_xilinx_type,			/* low range check value */
+    Xilinx_Spartan2,			/* Spartan-II Family */
+    Xilinx_VirtexE,				/* Virtex-E Family */
+    Xilinx_Virtex2,				/* Virtex2 Family */
+    Xilinx_Spartan3,				/* Spartan-III Family */
+    max_xilinx_type				/* insert all new types before this */
+} Xilinx_Family;				/* end, typedef Xilinx_Family */
+
+typedef struct {				/* typedef Xilinx_desc */
+    Xilinx_Family    family;	/* part type */
+    Xilinx_iface     iface;		/* interface type */
+    size_t           size;		/* bytes of data part can accept */
+	void *           iface_fns;	/* interface function table */
+    int              cookie;	/* implementation specific cookie */
+} Xilinx_desc;					/* end, typedef Xilinx_desc */
+
+/* Generic Xilinx Functions
+ *********************************************************************/
+extern int xilinx_load( Xilinx_desc *desc, void *image, size_t size );
+extern int xilinx_dump( Xilinx_desc *desc, void *buf, size_t bsize );
+extern int xilinx_info( Xilinx_desc *desc );
+extern int xilinx_reloc( Xilinx_desc *desc, ulong reloc_offset );
+
+/* Board specific implementation specific function types
+ *********************************************************************/
+typedef int (*Xilinx_pgm_fn)( int assert_pgm, int flush, int cookie );
+typedef int (*Xilinx_init_fn)( int cookie );
+typedef int (*Xilinx_err_fn)( int cookie );
+typedef int (*Xilinx_done_fn)( int cookie );
+typedef int (*Xilinx_clk_fn)( int assert_clk, int flush, int cookie );
+typedef int (*Xilinx_cs_fn)( int assert_cs, int flush, int cookie );
+typedef int (*Xilinx_wr_fn)( int assert_write, int flush, int cookie );
+typedef int (*Xilinx_rdata_fn)( unsigned char *data, int cookie );
+typedef int (*Xilinx_wdata_fn)( unsigned char data, int flush, int cookie );
+typedef int (*Xilinx_busy_fn)( int cookie );
+typedef int (*Xilinx_abort_fn)( int cookie );
+typedef int (*Xilinx_pre_fn)( int cookie );
+typedef int (*Xilinx_post_fn)( int cookie );
+
+#endif  /* _XILINX_H_ */
diff --git a/include/zlib.h b/include/zlib.h
new file mode 100755
index 0000000..e441494
--- /dev/null
+++ b/include/zlib.h
@@ -0,0 +1,434 @@
+/*
+ * This file is derived from zlib.h and zconf.h from the zlib-0.95
+ * distribution by Jean-loup Gailly and Mark Adler, with some additions
+ * by Paul Mackerras to aid in implementing Deflate compression and
+ * decompression for PPP packets.
+ */
+
+/*
+ *  ==FILEVERSION 960122==
+ *
+ * This marker is used by the Linux installation script to determine
+ * whether an up-to-date version of this file is already installed.
+ */
+
+/* zlib.h -- interface of the 'zlib' general purpose compression library
+  version 0.95, Aug 16th, 1995.
+
+  Copyright (C) 1995 Jean-loup Gailly and Mark Adler
+
+  This software is provided 'as-is', without any express or implied
+  warranty.  In no event will the authors be held liable for any damages
+  arising from the use of this software.
+
+  Permission is granted to anyone to use this software for any purpose,
+  including commercial applications, and to alter it and redistribute it
+  freely, subject to the following restrictions:
+
+  1. The origin of this software must not be misrepresented; you must not
+     claim that you wrote the original software. If you use this software
+     in a product, an acknowledgment in the product documentation would be
+     appreciated but is not required.
+  2. Altered source versions must be plainly marked as such, and must not be
+     misrepresented as being the original software.
+  3. This notice may not be removed or altered from any source distribution.
+
+  Jean-loup Gailly        Mark Adler
+  gzip@prep.ai.mit.edu    madler@alumni.caltech.edu
+ */
+
+#ifndef _ZLIB_H
+#define _ZLIB_H
+
+/* #include "zconf.h" */	/* included directly here */
+
+/* zconf.h -- configuration of the zlib compression library
+ * Copyright (C) 1995 Jean-loup Gailly.
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+/* From: zconf.h,v 1.12 1995/05/03 17:27:12 jloup Exp */
+
+/*
+     The library does not install any signal handler. It is recommended to
+  add at least a handler for SIGSEGV when decompressing; the library checks
+  the consistency of the input data whenever possible but may go nuts
+  for some forms of corrupted input.
+ */
+
+/*
+ * Compile with -DMAXSEG_64K if the alloc function cannot allocate more
+ * than 64k bytes at a time (needed on systems with 16-bit int).
+ * Compile with -DUNALIGNED_OK if it is OK to access shorts or ints
+ * at addresses which are not a multiple of their size.
+ * Under DOS, -DFAR=far or -DFAR=__far may be needed.
+ */
+
+#ifndef STDC
+#  if defined(MSDOS) || defined(__STDC__) || defined(__cplusplus)
+#    define STDC
+#  endif
+#endif
+
+#ifdef	__MWERKS__ /* Metrowerks CodeWarrior declares fileno() in unix.h */
+#  include <unix.h>
+#endif
+
+/* Maximum value for memLevel in deflateInit2 */
+#ifndef MAX_MEM_LEVEL
+#  ifdef MAXSEG_64K
+#    define MAX_MEM_LEVEL 8
+#  else
+#    define MAX_MEM_LEVEL 9
+#  endif
+#endif
+
+#ifndef FAR
+#  define FAR
+#endif
+
+/* Maximum value for windowBits in deflateInit2 and inflateInit2 */
+#ifndef MAX_WBITS
+#  define MAX_WBITS   15 /* 32K LZ77 window */
+#endif
+
+/* The memory requirements for deflate are (in bytes):
+	    1 << (windowBits+2)   +  1 << (memLevel+9)
+ that is: 128K for windowBits=15  +  128K for memLevel = 8  (default values)
+ plus a few kilobytes for small objects. For example, if you want to reduce
+ the default memory requirements from 256K to 128K, compile with
+     make CFLAGS="-O -DMAX_WBITS=14 -DMAX_MEM_LEVEL=7"
+ Of course this will generally degrade compression (there's no free lunch).
+
+   The memory requirements for inflate are (in bytes) 1 << windowBits
+ that is, 32K for windowBits=15 (default value) plus a few kilobytes
+ for small objects.
+*/
+
+			/* Type declarations */
+
+#ifndef OF /* function prototypes */
+#  ifdef STDC
+#    define OF(args)  args
+#  else
+#    define OF(args)  ()
+#  endif
+#endif
+
+typedef unsigned char  Byte;  /* 8 bits */
+typedef unsigned int   uInt;  /* 16 bits or more */
+typedef unsigned long  uLong; /* 32 bits or more */
+
+typedef Byte FAR Bytef;
+typedef char FAR charf;
+typedef int FAR intf;
+typedef uInt FAR uIntf;
+typedef uLong FAR uLongf;
+
+#ifdef STDC
+   typedef void FAR *voidpf;
+   typedef void     *voidp;
+#else
+   typedef Byte FAR *voidpf;
+   typedef Byte     *voidp;
+#endif
+
+/* end of original zconf.h */
+
+#define ZLIB_VERSION "0.95P"
+
+/*
+     The 'zlib' compression library provides in-memory compression and
+  decompression functions, including integrity checks of the uncompressed
+  data.  This version of the library supports only one compression method
+  (deflation) but other algorithms may be added later and will have the same
+  stream interface.
+
+     For compression the application must provide the output buffer and
+  may optionally provide the input buffer for optimization. For decompression,
+  the application must provide the input buffer and may optionally provide
+  the output buffer for optimization.
+
+     Compression can be done in a single step if the buffers are large
+  enough (for example if an input file is mmap'ed), or can be done by
+  repeated calls of the compression function.  In the latter case, the
+  application must provide more input and/or consume the output
+  (providing more output space) before each call.
+*/
+
+typedef voidpf (*alloc_func) OF((voidpf opaque, uInt items, uInt size));
+typedef void   (*free_func)  OF((voidpf opaque, voidpf address, uInt nbytes));
+
+typedef void   (*cb_func)    OF((Bytef *buf, uInt len));
+
+struct internal_state;
+
+typedef struct z_stream_s {
+    Bytef    *next_in;  /* next input byte */
+    uInt     avail_in;  /* number of bytes available at next_in */
+    uLong    total_in;  /* total nb of input bytes read so far */
+
+    Bytef    *next_out; /* next output byte should be put there */
+    uInt     avail_out; /* remaining free space at next_out */
+    uLong    total_out; /* total nb of bytes output so far */
+
+    char     *msg;      /* last error message, NULL if no error */
+    struct internal_state FAR *state; /* not visible by applications */
+
+    alloc_func zalloc;  /* used to allocate the internal state */
+    free_func  zfree;   /* used to free the internal state */
+    voidp      opaque;  /* private data object passed to zalloc and zfree */
+
+    Byte     data_type; /* best guess about the data type: ascii or binary */
+
+    cb_func  outcb;	/* called regularly just before blocks of output */
+
+} z_stream;
+
+/*
+   The application must update next_in and avail_in when avail_in has
+   dropped to zero. It must update next_out and avail_out when avail_out
+   has dropped to zero. The application must initialize zalloc, zfree and
+   opaque before calling the init function. All other fields are set by the
+   compression library and must not be updated by the application.
+
+   The opaque value provided by the application will be passed as the first
+   parameter for calls of zalloc and zfree. This can be useful for custom
+   memory management. The compression library attaches no meaning to the
+   opaque value.
+
+   zalloc must return Z_NULL if there is not enough memory for the object.
+   On 16-bit systems, the functions zalloc and zfree must be able to allocate
+   exactly 65536 bytes, but will not be required to allocate more than this
+   if the symbol MAXSEG_64K is defined (see zconf.h). WARNING: On MSDOS,
+   pointers returned by zalloc for objects of exactly 65536 bytes *must*
+   have their offset normalized to zero. The default allocation function
+   provided by this library ensures this (see zutil.c). To reduce memory
+   requirements and avoid any allocation of 64K objects, at the expense of
+   compression ratio, compile the library with -DMAX_WBITS=14 (see zconf.h).
+
+   The fields total_in and total_out can be used for statistics or
+   progress reports. After compression, total_in holds the total size of
+   the uncompressed data and may be saved for use in the decompressor
+   (particularly if the decompressor wants to decompress everything in
+   a single step).
+*/
+
+			/* constants */
+
+#define Z_NO_FLUSH      0
+#define Z_PARTIAL_FLUSH 1
+#define Z_FULL_FLUSH    2
+#define Z_SYNC_FLUSH    3 /* experimental: partial_flush + byte align */
+#define Z_FINISH        4
+#define Z_PACKET_FLUSH	5
+/* See deflate() below for the usage of these constants */
+
+#define Z_OK            0
+#define Z_STREAM_END    1
+#define Z_ERRNO        (-1)
+#define Z_STREAM_ERROR (-2)
+#define Z_DATA_ERROR   (-3)
+#define Z_MEM_ERROR    (-4)
+#define Z_BUF_ERROR    (-5)
+/* error codes for the compression/decompression functions */
+
+#define Z_BEST_SPEED             1
+#define Z_BEST_COMPRESSION       9
+#define Z_DEFAULT_COMPRESSION  (-1)
+/* compression levels */
+
+#define Z_FILTERED            1
+#define Z_HUFFMAN_ONLY        2
+#define Z_DEFAULT_STRATEGY    0
+
+#define Z_BINARY   0
+#define Z_ASCII    1
+#define Z_UNKNOWN  2
+/* Used to set the data_type field */
+
+#define Z_NULL  0  /* for initializing zalloc, zfree, opaque */
+
+extern char *zlib_version;
+/* The application can compare zlib_version and ZLIB_VERSION for consistency.
+   If the first character differs, the library code actually used is
+   not compatible with the zlib.h header file used by the application.
+ */
+
+			/* basic functions */
+
+extern int inflateInit OF((z_stream *strm));
+/*
+     Initializes the internal stream state for decompression. The fields
+   zalloc and zfree must be initialized before by the caller.  If zalloc and
+   zfree are set to Z_NULL, inflateInit updates them to use default allocation
+   functions.
+
+     inflateInit returns Z_OK if success, Z_MEM_ERROR if there was not
+   enough memory.  msg is set to null if there is no error message.
+   inflateInit does not perform any decompression: this will be done by
+   inflate().
+*/
+
+
+extern int inflate OF((z_stream *strm, int flush));
+/*
+  Performs one or both of the following actions:
+
+  - Decompress more input starting at next_in and update next_in and avail_in
+    accordingly. If not all input can be processed (because there is not
+    enough room in the output buffer), next_in is updated and processing
+    will resume at this point for the next call of inflate().
+
+  - Provide more output starting at next_out and update next_out and avail_out
+    accordingly.  inflate() always provides as much output as possible
+    (until there is no more input data or no more space in the output buffer).
+
+  Before the call of inflate(), the application should ensure that at least
+  one of the actions is possible, by providing more input and/or consuming
+  more output, and updating the next_* and avail_* values accordingly.
+  The application can consume the uncompressed output when it wants, for
+  example when the output buffer is full (avail_out == 0), or after each
+  call of inflate().
+
+    If the parameter flush is set to Z_PARTIAL_FLUSH or Z_PACKET_FLUSH,
+  inflate flushes as much output as possible to the output buffer. The
+  flushing behavior of inflate is not specified for values of the flush
+  parameter other than Z_PARTIAL_FLUSH, Z_PACKET_FLUSH or Z_FINISH, but the
+  current implementation actually flushes as much output as possible
+  anyway.  For Z_PACKET_FLUSH, inflate checks that once all the input data
+  has been consumed, it is expecting to see the length field of a stored
+  block; if not, it returns Z_DATA_ERROR.
+
+    inflate() should normally be called until it returns Z_STREAM_END or an
+  error. However if all decompression is to be performed in a single step
+  (a single call of inflate), the parameter flush should be set to
+  Z_FINISH. In this case all pending input is processed and all pending
+  output is flushed; avail_out must be large enough to hold all the
+  uncompressed data. (The size of the uncompressed data may have been saved
+  by the compressor for this purpose.) The next operation on this stream must
+  be inflateEnd to deallocate the decompression state. The use of Z_FINISH
+  is never required, but can be used to inform inflate that a faster routine
+  may be used for the single inflate() call.
+
+    inflate() returns Z_OK if some progress has been made (more input
+  processed or more output produced), Z_STREAM_END if the end of the
+  compressed data has been reached and all uncompressed output has been
+  produced, Z_DATA_ERROR if the input data was corrupted, Z_STREAM_ERROR if
+  the stream structure was inconsistent (for example if next_in or next_out
+  was NULL), Z_MEM_ERROR if there was not enough memory, Z_BUF_ERROR if no
+  progress is possible or if there was not enough room in the output buffer
+  when Z_FINISH is used. In the Z_DATA_ERROR case, the application may then
+  call inflateSync to look for a good compression block.  */
+
+
+extern int inflateEnd OF((z_stream *strm));
+/*
+     All dynamically allocated data structures for this stream are freed.
+   This function discards any unprocessed input and does not flush any
+   pending output.
+
+     inflateEnd returns Z_OK if success, Z_STREAM_ERROR if the stream state
+   was inconsistent. In the error case, msg may be set but then points to a
+   static string (which must not be deallocated).
+*/
+
+			/* advanced functions */
+
+extern int inflateInit2 OF((z_stream *strm,
+			    int  windowBits));
+/*
+     This is another version of inflateInit with more compression options. The
+   fields next_out, zalloc and zfree must be initialized before by the caller.
+
+     The windowBits parameter is the base two logarithm of the maximum window
+   size (the size of the history buffer).  It should be in the range 8..15 for
+   this version of the library (the value 16 will be allowed soon). The
+   default value is 15 if inflateInit is used instead. If a compressed stream
+   with a larger window size is given as input, inflate() will return with
+   the error code Z_DATA_ERROR instead of trying to allocate a larger window.
+
+     If next_out is not null, the library will use this buffer for the history
+   buffer; the buffer must either be large enough to hold the entire output
+   data, or have at least 1<<windowBits bytes.  If next_out is null, the
+   library will allocate its own buffer (and leave next_out null). next_in
+   need not be provided here but must be provided by the application for the
+   next call of inflate().
+
+     If the history buffer is provided by the application, next_out must
+   never be changed by the application since the decompressor maintains
+   history information inside this buffer from call to call; the application
+   can only reset next_out to the beginning of the history buffer when
+   avail_out is zero and all output has been consumed.
+
+      inflateInit2 returns Z_OK if success, Z_MEM_ERROR if there was
+   not enough memory, Z_STREAM_ERROR if a parameter is invalid (such as
+   windowBits < 8). msg is set to null if there is no error message.
+   inflateInit2 does not perform any decompression: this will be done by
+   inflate().
+*/
+
+extern int inflateSync OF((z_stream *strm));
+/*
+    Skips invalid compressed data until the special marker (see deflate()
+  above) can be found, or until all available input is skipped. No output
+  is provided.
+
+    inflateSync returns Z_OK if the special marker has been found, Z_BUF_ERROR
+  if no more input was provided, Z_DATA_ERROR if no marker has been found,
+  or Z_STREAM_ERROR if the stream structure was inconsistent. In the success
+  case, the application may save the current current value of total_in which
+  indicates where valid compressed data was found. In the error case, the
+  application may repeatedly call inflateSync, providing more input each time,
+  until success or end of the input data.
+*/
+
+extern int inflateReset OF((z_stream *strm));
+/*
+     This function is equivalent to inflateEnd followed by inflateInit,
+   but does not free and reallocate all the internal decompression state.
+   The stream will keep attributes that may have been set by inflateInit2.
+
+      inflateReset returns Z_OK if success, or Z_STREAM_ERROR if the source
+   stream state was inconsistent (such as zalloc or state being NULL).
+*/
+
+extern int inflateIncomp OF((z_stream *strm));
+/*
+     This function adds the data at next_in (avail_in bytes) to the output
+   history without performing any output.  There must be no pending output,
+   and the decompressor must be expecting to see the start of a block.
+   Calling this function is equivalent to decompressing a stored block
+   containing the data at next_in (except that the data is not output).
+*/
+
+			/* checksum functions */
+
+/*
+     This function is not related to compression but is exported
+   anyway because it might be useful in applications using the
+   compression library.
+*/
+
+extern uLong adler32 OF((uLong adler, Bytef *buf, uInt len));
+
+/*
+     Update a running Adler-32 checksum with the bytes buf[0..len-1] and
+   return the updated checksum. If buf is NULL, this function returns
+   the required initial value for the checksum.
+   An Adler-32 checksum is almost as reliable as a CRC32 but can be computed
+   much faster. Usage example:
+
+     uLong adler = adler32(0L, Z_NULL, 0);
+
+     while (read_buffer(buffer, length) != EOF) {
+       adler = adler32(adler, buffer, length);
+     }
+     if (adler != original_adler) error();
+*/
+
+#ifndef _Z_UTIL_H
+    struct internal_state {int dummy;}; /* hack for buggy compilers */
+#endif
+
+#endif /* _ZLIB_H */