1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
index b3e37c448..a4edf1d90 100644
--- a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
+++ b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
@@ -149,7 +149,7 @@ module aeMB_ibuf (/*AUTOARG*/
 	rSTALL <= 1'h0;
 	// End of automatics
      end else begin
-	rSTALL <= #1 (!rSTALL & (fMUL | fBSF)) | (oena & rSTALL);	
+	rSTALL <= #1 (gena & !rSTALL & (fMUL | fBSF)) | (oena & rSTALL);	
      end
    
 endmodule // aeMB_ibuf
@@ -189,4 +189,4 @@ endmodule // aeMB_ibuf
  New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
  Fixed various minor data hazard bugs.
  Code compatible with -O0/1/2/3/s generated code.
-*/
-\ No newline at end of file
+*/