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authormatt2009-01-22 18:23:45 +0000
committermatt2009-01-22 18:23:45 +0000
commitf5fdfe3342750df3092bd0a8d39cb42b4d599012 (patch)
treee1571bad9e88108b0e5d2c9943553f568ddde2df /usrp2/fpga
parent8977bb20290ba518dce35a35e85d6b21caf265e9 (diff)
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trial fix for problem when 3 loads with 1 wait state are followed by a barrel shift or multiply. Shawn will let us know if this works.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10290 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'usrp2/fpga')
-rw-r--r--usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
index b3e37c448..a4edf1d90 100644
--- a/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
+++ b/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
@@ -149,7 +149,7 @@ module aeMB_ibuf (/*AUTOARG*/
rSTALL <= 1'h0;
// End of automatics
end else begin
- rSTALL <= #1 (!rSTALL & (fMUL | fBSF)) | (oena & rSTALL);
+ rSTALL <= #1 (gena & !rSTALL & (fMUL | fBSF)) | (oena & rSTALL);
end
endmodule // aeMB_ibuf
@@ -189,4 +189,4 @@ endmodule // aeMB_ibuf
New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.
-*/ \ No newline at end of file
+*/