summaryrefslogtreecommitdiff
path: root/usrp-hw/clockfix
diff options
context:
space:
mode:
Diffstat (limited to 'usrp-hw/clockfix')
-rw-r--r--usrp-hw/clockfix/clockfix.bom16
-rw-r--r--usrp-hw/clockfix/clockfix.net8
-rw-r--r--usrp-hw/clockfix/clockfix.pcb1209
-rw-r--r--usrp-hw/clockfix/clockfix.prj6
-rw-r--r--usrp-hw/clockfix/clockfix.sch333
-rw-r--r--usrp-hw/clockfix/gnetlistrc3
-rw-r--r--usrp-hw/clockfix/gschemrc3
-rwxr-xr-xusrp-hw/clockfix/netlist_cmd3
8 files changed, 1581 insertions, 0 deletions
diff --git a/usrp-hw/clockfix/clockfix.bom b/usrp-hw/clockfix/clockfix.bom
new file mode 100644
index 000000000..a7491898a
--- /dev/null
+++ b/usrp-hw/clockfix/clockfix.bom
@@ -0,0 +1,16 @@
+.START
+..device value footprint quantity refdes
+ADP3336 unknown MSOP8 1 U1
+CAPACITOR 0.1uF 0603 4 C1 C3 C5 C9
+CAPACITOR 1uF 0603 1 C4
+CAPACITOR 220pF 0603 2 C2 C8
+CAPACITOR 470pF 0603 1 C10
+CONNECTOR_2 unknown CONNECTOR 1 2 1 J1
+INDUCTOR unknown 1206 2 L1 L2
+POLARIZED_CAPACITOR 4.7uF 1206 2 C6 C7
+RESISTOR 140k 0603 1 R1
+RESISTOR 50 0603 1 R3
+RESISTOR 78.7k 0603 1 R2
+SMA5 unknown SMA_VERT 1 J2
+VCTCXO unknown CTS_OSC 1 X1
+.END
diff --git a/usrp-hw/clockfix/clockfix.net b/usrp-hw/clockfix/clockfix.net
new file mode 100644
index 000000000..06f66821a
--- /dev/null
+++ b/usrp-hw/clockfix/clockfix.net
@@ -0,0 +1,8 @@
+unnamed_net6 C10-2 R2-1 R1-2 U1-5
+unnamed_net5 U1-6 U1-7 U1-8 C5-1 L2-2 C6-1
+unnamed_net4 C1-1 J1-1 C2-1 L1-1
+unnamed_net3 L2-1 C3-1 C4-1 L1-2
+unnamed_net2 R3-2 J2-1
+GND R2-2 U1-4 J1-2 C5-2 C6-2 C3-2 C4-2 C2-2 C1-2 J2-5 J2-4 J2-3 J2-2 C7-2 C8-2 C9-2 X1-2
+DVDD C10-1 R1-1 U1-2 U1-3 U1-1 C7-1 C8-1 C9-1 X1-4 X1-1
+unnamed_net1 R3-1 X1-3
diff --git a/usrp-hw/clockfix/clockfix.pcb b/usrp-hw/clockfix/clockfix.pcb
new file mode 100644
index 000000000..0ff309b4b
--- /dev/null
+++ b/usrp-hw/clockfix/clockfix.pcb
@@ -0,0 +1,1209 @@
+# release: pcb-bin 1.99q
+# date: Thu Jun 23 11:37:18 2005
+# user: matt (Matt Ettus)
+# host: localhost.localdomain
+
+PCB["" 189999 49999]
+
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+ SymbolLine[1000 5000 2000 4000 800]
+ SymbolLine[2000 3000 2000 4000 800]
+)
+Symbol['w' 1200]
+(
+ SymbolLine[0 3000 0 4500 800]
+ SymbolLine[0 4500 500 5000 800]
+ SymbolLine[500 5000 1000 5000 800]
+ SymbolLine[1000 5000 1500 4500 800]
+ SymbolLine[1500 3000 1500 4500 800]
+ SymbolLine[1500 4500 2000 5000 800]
+ SymbolLine[2000 5000 2500 5000 800]
+ SymbolLine[2500 5000 3000 4500 800]
+ SymbolLine[3000 3000 3000 4500 800]
+)
+Symbol['x' 1200]
+(
+ SymbolLine[0 3000 2000 5000 800]
+ SymbolLine[0 5000 2000 3000 800]
+)
+Symbol['y' 1200]
+(
+ SymbolLine[0 3000 0 4500 800]
+ SymbolLine[0 4500 500 5000 800]
+ SymbolLine[2000 3000 2000 6000 800]
+ SymbolLine[1500 6500 2000 6000 800]
+ SymbolLine[500 6500 1500 6500 800]
+ SymbolLine[0 6000 500 6500 800]
+ SymbolLine[500 5000 1500 5000 800]
+ SymbolLine[1500 5000 2000 4500 800]
+)
+Symbol['z' 1200]
+(
+ SymbolLine[0 3000 2000 3000 800]
+ SymbolLine[0 5000 2000 3000 800]
+ SymbolLine[0 5000 2000 5000 800]
+)
+Symbol['{' 1200]
+(
+ SymbolLine[500 1500 1000 1000 800]
+ SymbolLine[500 1500 500 2500 800]
+ SymbolLine[0 3000 500 2500 800]
+ SymbolLine[0 3000 500 3500 800]
+ SymbolLine[500 3500 500 4500 800]
+ SymbolLine[500 4500 1000 5000 800]
+)
+Symbol['|' 1200]
+(
+ SymbolLine[0 1000 0 5000 800]
+)
+Symbol['}' 1200]
+(
+ SymbolLine[0 1000 500 1500 800]
+ SymbolLine[500 1500 500 2500 800]
+ SymbolLine[500 2500 1000 3000 800]
+ SymbolLine[500 3500 1000 3000 800]
+ SymbolLine[500 3500 500 4500 800]
+ SymbolLine[0 5000 500 4500 800]
+)
+Symbol['~' 1200]
+(
+ SymbolLine[0 3500 500 3000 800]
+ SymbolLine[500 3000 1000 3000 800]
+ SymbolLine[1000 3000 1500 3500 800]
+ SymbolLine[1500 3500 2000 3500 800]
+ SymbolLine[2000 3500 2500 3000 800]
+)
+Via[94000 3000 6000 2000 0 3500 "" "thermal(0)"]
+Via[103000 6000 6000 2000 0 3500 "" "thermal(0)"]
+Via[105000 40000 6000 2000 0 3500 "" "thermal(0)"]
+Via[118000 45000 6000 2000 0 3500 "" "thermal(0)"]
+Via[94000 14000 5999 1998 0 3500 "" "thermal(0)"]
+Via[83000 36000 5999 1996 0 3500 "" "thermal(0)"]
+Via[61000 42000 5999 1996 0 3500 "" "thermal(0)"]
+Via[23000 41000 5999 1996 0 3500 "" "thermal(0)"]
+Via[41000 41000 5999 1996 0 3500 "" "thermal(0)"]
+
+Element["" "0603" "C10" "470pF" 85000 9000 -14000 -2000 0 100 ""]
+(
+ Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"]
+ Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"]
+ ElementLine [4200 -2700 4200 2700 600]
+ ElementLine [-4200 -2700 4200 -2700 600]
+ ElementLine [-4200 -2700 -4200 2700 600]
+ ElementLine [-4200 2700 4200 2700 600]
+
+ )
+
+Element["" "0603" "R2" "78.7k" 85000 3000 -13000 -2000 0 100 ""]
+(
+ Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"]
+ Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"]
+ ElementLine [-4200 -2700 -4200 2700 600]
+ ElementLine [-4200 2700 4200 2700 600]
+ ElementLine [4200 -2700 4200 2700 600]
+ ElementLine [-4200 -2700 4200 -2700 600]
+
+ )
+
+Element["" "0603" "R1" "140k" 85000 15000 5000 -3000 0 100 ""]
+(
+ Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"]
+ Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"]
+ ElementLine [4200 -2700 4200 2700 600]
+ ElementLine [-4200 -2700 4200 -2700 600]
+ ElementLine [-4200 -2700 -4200 2700 600]
+ ElementLine [-4200 2700 4200 2700 600]
+
+ )
+
+Element["" "1206" "C7" "4.7uF" 103000 17000 -3000 -15000 0 100 ""]
+(
+ Pad[-1800 4800 1800 4800 4800 2000 5400 "1" "1" "square"]
+ Pad[-1800 -4800 1800 -4800 4800 2000 5400 "2" "2" "square"]
+ ElementLine [-5400 8400 5400 8400 1000]
+ ElementLine [5400 -8400 5400 8400 1000]
+ ElementLine [-5400 -8400 5400 -8400 1000]
+ ElementLine [-5400 -8400 -5400 8400 1000]
+
+ )
+
+Element["" "0603" "C5" "0.1uF" 57000 33000 -4000 5000 0 100 ""]
+(
+ Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+ Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+ ElementLine [-2700 -4200 2700 -4200 600]
+ ElementLine [-2700 -4200 -2700 4200 600]
+ ElementLine [-2700 4200 2700 4200 600]
+ ElementLine [2700 -4200 2700 4200 600]
+
+ )
+
+Element["" "1206" "L2" "unknown" 50000 22000 -3000 -12000 0 100 ""]
+(
+ Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" "square"]
+ Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" "square"]
+ ElementLine [-8400 -5400 -8400 5400 1000]
+ ElementLine [-8400 5400 8400 5400 1000]
+ ElementLine [8400 5400 8400 -5400 1000]
+ ElementLine [8400 -5400 -8400 -5400 1000]
+
+ )
+
+Element["" "0603" "C4" "1uF" 45000 33000 -3000 5000 0 100 ""]
+(
+ Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+ Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+ ElementLine [-2700 -4200 2700 -4200 600]
+ ElementLine [-2700 -4200 -2700 4200 600]
+ ElementLine [-2700 4200 2700 4200 600]
+ ElementLine [2700 -4200 2700 4200 600]
+
+ )
+
+Element["" "0603" "C3" "0.1uF" 38000 33000 -4000 5000 0 100 ""]
+(
+ Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+ Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+ ElementLine [-2700 -4200 2700 -4200 600]
+ ElementLine [-2700 -4200 -2700 4200 600]
+ ElementLine [-2700 4200 2700 4200 600]
+ ElementLine [2700 -4200 2700 4200 600]
+
+ )
+
+Element["" "CONNECTOR-1-2" "J1" "unknown" 10000 25000 -3000 -12000 0 100 ""]
+(
+ Pin[0 0 8500 3000 9100 5500 "1" "1" "square"]
+ Pin[0 10000 8500 3000 9100 5500 "2" "2" "thermal(0)"]
+ ElementLine [-5000 -5000 5000 -5000 2000]
+ ElementLine [-5000 -5000 -5000 15000 2000]
+ ElementLine [-5000 15000 5000 15000 2000]
+ ElementLine [5000 -5000 5000 15000 2000]
+ ElementLine [-5000 -5000 -5000 5000 1000]
+ ElementLine [-5000 5000 5000 5000 1000]
+
+ )
+
+Element["" "MSOP8" "U1" "unknown" 93000 28000 -18000 2000 0 100 ""]
+(
+ Pad[-700 0 1500 0 1600 3000 2200 "1" "1" "edge2"]
+ Pad[-700 -2600 1500 -2600 1600 3000 2200 "2" "2" "square,edge2"]
+ Pad[-700 -5100 1500 -5100 1600 3000 2200 "3" "3" "square,edge2"]
+ Pad[-700 -7700 1500 -7700 1600 3000 2200 "4" "4" "square,edge2"]
+ Pad[-17400 -7800 -15200 -7800 1600 3000 2200 "5" "5" "square"]
+ Pad[-17400 -5200 -15200 -5200 1600 3000 2200 "6" "6" "square"]
+ Pad[-17400 -2700 -15200 -2700 1600 3000 2200 "7" "7" "square"]
+ Pad[-17400 -100 -15200 -100 1600 3000 2200 "8" "8" "square"]
+ ElementLine [-9100 1200 2300 1200 1000]
+ ElementLine [-18200 1200 -6700 1200 1000]
+ ElementLine [-18200 -9000 -18200 1200 1000]
+ ElementLine [-18200 -9000 2300 -9000 1000]
+ ElementLine [2300 -9000 2300 1200 1000]
+ ElementArc [-7900 1200 1200 1200 180 180 1000]
+
+ )
+
+Element["" "1206" "C6" "4.7uF" 67000 30000 -3000 -15000 0 100 ""]
+(
+ Pad[-1800 -4800 1800 -4800 4800 2000 5400 "1" "1" "square"]
+ Pad[-1800 4800 1800 4800 4800 2000 5400 "2" "2" "square"]
+ ElementLine [-5400 -8400 5400 -8400 1000]
+ ElementLine [-5400 -8400 -5400 8400 1000]
+ ElementLine [-5400 8400 5400 8400 1000]
+ ElementLine [5400 -8400 5400 8400 1000]
+
+ )
+
+Element["" "0603" "C2" "220pF" 26000 32000 -3000 5000 0 100 ""]
+(
+ Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+ Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+ ElementLine [-2700 -4200 2700 -4200 600]
+ ElementLine [-2700 -4200 -2700 4200 600]
+ ElementLine [-2700 4200 2700 4200 600]
+ ElementLine [2700 -4200 2700 4200 600]
+
+ )
+
+Element["" "0603" "C1" "0.1uF" 20000 32000 -3000 5000 0 100 ""]
+(
+ Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+ Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+ ElementLine [-2700 -4200 2700 -4200 600]
+ ElementLine [-2700 -4200 -2700 4200 600]
+ ElementLine [-2700 4200 2700 4200 600]
+ ElementLine [2700 -4200 2700 4200 600]
+
+ )
+
+Element["" "1206" "L1" "unknown" 32000 22000 -3000 -12000 0 100 ""]
+(
+ Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" "square"]
+ Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" "square"]
+ ElementLine [-8400 -5400 -8400 5400 1000]
+ ElementLine [-8400 5400 8400 5400 1000]
+ ElementLine [8400 -5400 8400 5400 1000]
+ ElementLine [-8400 -5400 8400 -5400 1000]
+
+ )
+
+Element["" "0603" "R3" "50" 147000 33000 -3000 -10000 0 100 ""]
+(
+ Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"]
+ Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"]
+ ElementLine [-4200 -2700 -4200 2700 600]
+ ElementLine [-4200 2700 4200 2700 600]
+ ElementLine [4200 2700 4200 -2700 600]
+ ElementLine [4200 -2700 -4200 -2700 600]
+
+ )
+
+Element["" "SMA_VERT" "J2" "unknown" 170000 27000 -4000 -23000 0 100 ""]
+(
+ Pin[0 0 9500 3000 10100 6500 "1" "1" ""]
+ Pin[-10000 10000 9500 3000 10100 6500 "2" "2" "thermal(0)"]
+ Pin[-10000 -10000 9500 3000 10100 6500 "3" "3" "thermal(0)"]
+ Pin[10000 10000 9500 3000 10100 6500 "4" "4" "thermal(0)"]
+ Pin[10000 -10000 9500 3000 10100 6500 "5" "5" "thermal(0)"]
+ ElementLine [-16000 -16000 16000 -16000 1000]
+ ElementLine [16000 -16000 16000 16000 1000]
+ ElementLine [16000 16000 -16000 16000 1000]
+ ElementLine [-16000 16000 -16000 -16000 1000]
+
+ )
+
+Element["" "0603" "C8" "220pF" 91000 34000 5000 3000 1 100 ""]
+(
+ Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"]
+ Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"]
+ ElementLine [4200 -2700 4200 2700 600]
+ ElementLine [-4200 -2700 4200 -2700 600]
+ ElementLine [-4200 -2700 -4200 2700 600]
+ ElementLine [-4200 2700 4200 2700 600]
+
+ )
+
+Element["" "0603" "C9" "0.1uF" 107000 31000 -4000 5000 0 100 ""]
+(
+ Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"]
+ Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"]
+ ElementLine [2700 -4200 2700 4200 600]
+ ElementLine [-2700 4200 2700 4200 600]
+ ElementLine [-2700 -4200 -2700 4200 600]
+ ElementLine [-2700 -4200 2700 -4200 600]
+
+ )
+
+Element["" "CTS_OSC" "X1" "unknown" 118000 17000 5000 -12000 0 100 ""]
+(
+ Pad[15190 -20 17190 -20 7100 1596 8696 "" "4" "square,edge2"]
+ Pad[15190 19980 17190 19980 7100 1596 8696 "" "3" "square,edge2"]
+ Pad[-1310 -20 690 -20 7100 1596 8696 "" "1" "square"]
+ Pad[-1310 19980 690 19980 7100 1596 8696 "" "2" "square"]
+ ElementLine [7400 -2880 10370 -5850 699]
+ ElementLine [4300 -5980 7400 -2880 699]
+ ElementLine [4300 -6010 4300 -5980 699]
+ ElementLine [-7310 25980 23190 25980 699]
+ ElementLine [-7310 -6020 -7310 25980 699]
+ ElementLine [-7310 -6020 23190 -6020 699]
+ ElementLine [23190 -6020 23190 25980 699]
+
+ )
+Layer(1 "solder")
+(
+ Polygon("clearpoly")
+ (
+ [0 0] [190000 0] [190000 50000] [0 50000]
+ )
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+ Line[10000 25000 27000 25000 3000 2000 ""]
+ Line[19100 29600 20000 28700 4000 2000 ""]
+ Line[20000 28700 20000 25000 3000 2000 ""]
+ Line[26900 29600 26000 28700 4000 2000 ""]
+ Line[26000 28700 26000 25000 3000 2000 ""]
+ Line[36800 20200 38600 22000 4000 2000 ""]
+ Line[38600 22000 45000 22000 3000 2000 ""]
+ Line[37100 30600 38000 29700 3000 2000 ""]
+ Line[38000 29700 38000 25000 4000 2000 ""]
+ Line[44100 30600 45000 29700 3000 2000 ""]
+ Line[45000 29700 45000 25000 3000 2000 ""]
+ Line[54800 23800 56000 25000 3000 2000 ""]
+ Line[56000 25000 65000 25000 3000 2000 ""]
+ Line[56100 30600 59000 27700 3000 2000 ""]
+ Line[59000 27700 59000 26000 3000 2000 ""]
+ Line[68800 25200 70000 24000 3000 2000 ""]
+ Line[70000 24000 77000 24000 3000 2000 ""]
+ Line[77000 24000 77000 28000 3000 2000 ""]
+ Line[133190 16980 133170 17000 4000 2000 ""]
+ Line[133170 17000 117000 17000 3000 2000 ""]
+ Line[149400 32100 154500 27000 3000 2000 ""]
+ Line[154500 27000 170000 27000 3000 2000 ""]
+ Line[144600 32100 138700 38000 3000 2000 ""]
+ Line[138700 38000 134000 38000 4000 2000 ""]
+ Line[104800 21800 108600 18000 3000 2000 ""]
+ Line[108600 18000 117000 18000 3000 2000 ""]
+ Line[107900 28600 117000 19500 3000 2000 ""]
+ Line[117000 19500 117000 18000 4000 2000 ""]
+ Line[106100 28600 101000 23500 3000 2000 ""]
+ Line[101000 23500 101000 23000 3000 2000 ""]
+ Line[92300 22900 92400 23000 800 2000 ""]
+ Line[92400 23000 100000 23000 1300 2000 ""]
+ Line[92300 22900 92000 23200 800 2000 ""]
+ Line[92000 23200 92000 28000 1300 2000 ""]
+ Line[93400 33100 93000 32700 800 2000 ""]
+ Line[93000 32700 93000 28000 1300 2000 ""]
+ Line[106100 33400 106000 33500 3000 2000 ""]
+ Line[106000 33500 106000 39000 3000 2000 ""]
+ Line[116690 36980 118000 38290 4000 2000 ""]
+ Line[118000 38290 118000 44000 4000 2000 ""]
+ Line[101200 12200 102000 11400 4000 2000 ""]
+ Line[102000 11400 102000 6000 4000 2000 ""]
+ Line[87400 2100 88300 3000 3000 2000 ""]
+ Line[88300 3000 93000 3000 4000 2000 ""]
+ Line[75600 20200 80800 15000 1800 2000 ""]
+ Line[80800 15000 81000 15300 800 2000 ""]
+ Line[82000 14000 82000 4300 3000 2000 ""]
+ Line[87400 8100 88000 8700 2999 1998 ""]
+ Line[88000 8700 88000 21000 2999 1998 ""]
+ Line[88000 21000 92000 25000 2999 1998 ""]
+ Line[94000 14000 94000 20000 2499 1996 ""]
+ Line[88600 33100 85700 36000 2499 1996 ""]
+ Line[85700 36000 83000 36000 2499 1996 ""]
+ Line[61000 42000 66000 37000 2499 1996 ""]
+ Line[66000 37000 66000 35000 2499 1996 ""]
+ Line[25100 34400 24500 35000 2499 1996 ""]
+ Line[24500 35000 10000 35000 2499 1996 ""]
+ Line[37100 35400 41000 39300 2499 1996 ""]
+ Line[41000 39300 41000 41000 2499 1996 ""]
+ Line[44100 35400 42000 37500 2499 1996 ""]
+ Line[42000 37500 42000 42000 2499 1996 ""]
+ Line[41000 41000 42000 42000 2499 1996 ""]
+ Line[56100 35400 60000 39300 2499 1996 ""]
+ Line[60000 39300 60000 42000 2499 1996 ""]
+ Line[25100 34400 23000 36500 2500 2000 ""]
+ Line[23000 36500 23000 41000 2500 2000 ""]
+ Line[19100 34400 23000 38300 2500 2000 ""]
+ Line[23000 38300 23000 41000 2500 2000 ""]
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
+Layer(9 "silk")
+(
+)
+Layer(10 "silk")
+(
+)
+NetList()
+(
+ Net("unnamed_net6" "(unknown)")
+ (
+ Connect("C10-2")
+ Connect("R2-1")
+ Connect("R1-2")
+ Connect("U1-5")
+ )
+ Net("unnamed_net5" "(unknown)")
+ (
+ Connect("U1-6")
+ Connect("U1-7")
+ Connect("U1-8")
+ Connect("C5-1")
+ Connect("L2-2")
+ Connect("C6-1")
+ )
+ Net("unnamed_net4" "(unknown)")
+ (
+ Connect("C1-1")
+ Connect("J1-1")
+ Connect("C2-1")
+ Connect("L1-1")
+ )
+ Net("unnamed_net3" "(unknown)")
+ (
+ Connect("L2-1")
+ Connect("C3-1")
+ Connect("C4-1")
+ Connect("L1-2")
+ )
+ Net("unnamed_net2" "(unknown)")
+ (
+ Connect("R3-2")
+ Connect("J2-1")
+ )
+ Net("GND" "(unknown)")
+ (
+ Connect("R2-2")
+ Connect("U1-4")
+ Connect("J1-2")
+ Connect("C5-2")
+ Connect("C6-2")
+ Connect("C3-2")
+ Connect("C4-2")
+ Connect("C2-2")
+ Connect("C1-2")
+ Connect("J2-5")
+ Connect("J2-4")
+ Connect("J2-3")
+ Connect("J2-2")
+ Connect("C7-2")
+ Connect("C8-2")
+ Connect("C9-2")
+ Connect("X1-2")
+ )
+ Net("DVDD" "(unknown)")
+ (
+ Connect("C10-1")
+ Connect("R1-1")
+ Connect("U1-2")
+ Connect("U1-3")
+ Connect("U1-1")
+ Connect("C7-1")
+ Connect("C8-1")
+ Connect("C9-1")
+ Connect("X1-4")
+ Connect("X1-1")
+ )
+ Net("unnamed_net1" "(unknown)")
+ (
+ Connect("R3-1")
+ Connect("X1-3")
+ )
+)
diff --git a/usrp-hw/clockfix/clockfix.prj b/usrp-hw/clockfix/clockfix.prj
new file mode 100644
index 000000000..787910056
--- /dev/null
+++ b/usrp-hw/clockfix/clockfix.prj
@@ -0,0 +1,6 @@
+# List all schematics
+schematics clockfix.sch
+
+output-name clockfix
+
+elements-dir ../pkg/newlib
diff --git a/usrp-hw/clockfix/clockfix.sch b/usrp-hw/clockfix/clockfix.sch
new file mode 100644
index 000000000..fc0709bf7
--- /dev/null
+++ b/usrp-hw/clockfix/clockfix.sch
@@ -0,0 +1,333 @@
+v 20040111 1
+C 8200 23400 1 0 0 vctcxo.sym
+{
+T 59600 53500 5 10 1 1 0 6 1
+refdes=X1
+T 59300 52600 5 10 0 1 0 0 1
+footprint=CTS_OSC
+}
+C 57100 53600 1 0 0 generic-power.sym
+{
+T 57300 53850 5 10 1 1 0 3 1
+net=DVDD:1
+}
+C 57200 51600 1 0 0 gnd-1.sym
+C 57100 53300 1 270 0 capacitor-1.sym
+{
+T 56800 52500 5 10 1 1 0 0 1
+refdes=C9
+T 56800 52300 5 10 1 1 0 0 1
+value=0.1uF
+T 57100 53300 5 10 0 1 0 0 1
+footprint=0603
+}
+N 57300 52400 57300 51900 4
+N 57300 53300 57300 53600 4
+N 57300 53500 57700 53500 4
+N 57700 53500 57700 53000 4
+N 57700 53000 57900 53000 4
+N 57300 52100 57700 52100 4
+N 57700 52100 57700 52600 4
+N 57700 52600 57900 52600 4
+C 56300 53300 1 270 0 capacitor-1.sym
+{
+T 56000 52500 5 10 1 1 0 0 1
+refdes=C8
+T 55900 52300 5 10 1 1 0 0 1
+value=220pF
+T 56300 53300 5 10 0 1 0 0 1
+footprint=0603
+}
+N 56500 53500 56500 53300 4
+N 56500 52400 56500 52100 4
+C 60100 52800 1 270 0 generic-power.sym
+{
+T 60350 52600 5 10 1 1 270 3 1
+net=DVDD:1
+}
+N 59900 52600 60100 52600 4
+C 62500 52500 1 0 1 SMA-5.sym
+{
+T 62500 53300 5 10 1 1 0 6 1
+refdes=J2
+T 62500 52500 5 10 0 1 0 0 1
+footprint=SMA_VERT
+}
+C 60700 52900 1 0 0 resistor-1.sym
+{
+T 60900 53200 5 10 1 1 180 8 1
+refdes=R3
+T 60700 52900 5 10 0 1 180 8 1
+footprint=0603
+T 61300 52700 5 10 1 1 0 6 1
+value=50
+}
+N 62000 53000 61600 53000 4
+C 62300 52000 1 0 0 gnd-1.sym
+N 62400 52300 62400 52500 4
+B 53700 46300 11000 8500 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 77900 52800 5 10 0 0 0 0 1
+graphical=1
+B 53900 46500 10600 8100 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+L 55700 46500 55700 46300 15 0 0 0 -1 -1
+L 57700 46500 57700 46300 15 0 0 0 -1 -1
+L 59700 46500 59700 46300 15 0 0 0 -1 -1
+L 61700 46500 61700 46300 15 0 0 0 -1 -1
+L 63700 46500 63700 46300 15 0 0 0 -1 -1
+L 53900 48300 53700 48300 15 0 0 0 -1 -1
+L 53900 50300 53700 50300 15 0 0 0 -1 -1
+L 53900 52300 53700 52300 15 0 0 0 -1 -1
+L 53900 54300 53700 54300 15 0 0 0 -1 -1
+T 54700 46400 15 8 1 0 0 4 1
+1
+T 56700 46400 15 8 1 0 0 4 1
+2
+T 58700 46400 15 8 1 0 0 4 1
+3
+T 60700 46400 15 8 1 0 0 4 1
+4
+T 62700 46400 15 8 1 0 0 4 1
+5
+T 64200 46400 15 8 1 0 0 4 1
+6
+L 55700 54800 55700 54600 15 0 0 0 -1 -1
+L 57700 54800 57700 54600 15 0 0 0 -1 -1
+L 59700 54800 59700 54600 15 0 0 0 -1 -1
+L 61700 54800 61700 54600 15 0 0 0 -1 -1
+L 63700 54800 63700 54600 15 0 0 0 -1 -1
+T 56700 54700 15 8 1 0 0 4 1
+2
+T 54700 54700 15 8 1 0 0 4 1
+1
+T 58700 54700 15 8 1 0 0 4 1
+3
+T 60700 54700 15 8 1 0 0 4 1
+4
+T 62700 54700 15 8 1 0 0 4 1
+5
+T 64200 54700 15 8 1 0 0 4 1
+6
+T 53800 47300 15 8 1 0 0 4 1
+A
+T 53800 49300 15 8 1 0 0 4 1
+B
+T 53800 51300 15 8 1 0 0 4 1
+C
+T 53800 53300 15 8 1 0 0 4 1
+D
+T 53800 54500 15 8 1 0 0 4 1
+E
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diff --git a/usrp-hw/clockfix/gnetlistrc b/usrp-hw/clockfix/gnetlistrc
new file mode 100644
index 000000000..6bbd9c292
--- /dev/null
+++ b/usrp-hw/clockfix/gnetlistrc
@@ -0,0 +1,3 @@
+(component-library "../sym")
+(component-library "../sym/generated")
+
diff --git a/usrp-hw/clockfix/gschemrc b/usrp-hw/clockfix/gschemrc
new file mode 100644
index 000000000..6bbd9c292
--- /dev/null
+++ b/usrp-hw/clockfix/gschemrc
@@ -0,0 +1,3 @@
+(component-library "../sym")
+(component-library "../sym/generated")
+
diff --git a/usrp-hw/clockfix/netlist_cmd b/usrp-hw/clockfix/netlist_cmd
new file mode 100755
index 000000000..0196a1261
--- /dev/null
+++ b/usrp-hw/clockfix/netlist_cmd
@@ -0,0 +1,3 @@
+gsch2pcb clockfix.prj
+gnetlist -g partslist3 -o clockfix.bom clockfix.sch
+
generated by cgit (git 2.34.1) at 2024-12-22 08:22:26 +0000