diff options
Diffstat (limited to 'usrp-hw')
42 files changed, 34039 insertions, 0 deletions
diff --git a/usrp-hw/clockfix/clockfix.bom b/usrp-hw/clockfix/clockfix.bom new file mode 100644 index 000000000..a7491898a --- /dev/null +++ b/usrp-hw/clockfix/clockfix.bom @@ -0,0 +1,16 @@ +.START +..device value footprint quantity refdes +ADP3336 unknown MSOP8 1 U1 +CAPACITOR 0.1uF 0603 4 C1 C3 C5 C9 +CAPACITOR 1uF 0603 1 C4 +CAPACITOR 220pF 0603 2 C2 C8 +CAPACITOR 470pF 0603 1 C10 +CONNECTOR_2 unknown CONNECTOR 1 2 1 J1 +INDUCTOR unknown 1206 2 L1 L2 +POLARIZED_CAPACITOR 4.7uF 1206 2 C6 C7 +RESISTOR 140k 0603 1 R1 +RESISTOR 50 0603 1 R3 +RESISTOR 78.7k 0603 1 R2 +SMA5 unknown SMA_VERT 1 J2 +VCTCXO unknown CTS_OSC 1 X1 +.END diff --git a/usrp-hw/clockfix/clockfix.net b/usrp-hw/clockfix/clockfix.net new file mode 100644 index 000000000..06f66821a --- /dev/null +++ b/usrp-hw/clockfix/clockfix.net @@ -0,0 +1,8 @@ +unnamed_net6 C10-2 R2-1 R1-2 U1-5 +unnamed_net5 U1-6 U1-7 U1-8 C5-1 L2-2 C6-1 +unnamed_net4 C1-1 J1-1 C2-1 L1-1 +unnamed_net3 L2-1 C3-1 C4-1 L1-2 +unnamed_net2 R3-2 J2-1 +GND R2-2 U1-4 J1-2 C5-2 C6-2 C3-2 C4-2 C2-2 C1-2 J2-5 J2-4 J2-3 J2-2 C7-2 C8-2 C9-2 X1-2 +DVDD C10-1 R1-1 U1-2 U1-3 U1-1 C7-1 C8-1 C9-1 X1-4 X1-1 +unnamed_net1 R3-1 X1-3 diff --git a/usrp-hw/clockfix/clockfix.pcb b/usrp-hw/clockfix/clockfix.pcb new file mode 100644 index 000000000..0ff309b4b --- /dev/null +++ b/usrp-hw/clockfix/clockfix.pcb @@ -0,0 +1,1209 @@ +# release: pcb-bin 1.99q +# date: Thu Jun 23 11:37:18 2005 +# user: matt (Matt Ettus) +# host: localhost.localdomain + +PCB["" 189999 49999] + +Grid[1000.00000000 0 0 0] +Cursor[105639 74875 1.405715] +Thermal[0.500000] +DRC[699 400 699 499] +Flags(0x00000000000000d0) +Groups("1,s:4,c:2,3,5,6,7,8:") +Styles["Signal,1000,4000,2000,1000:Power,2500,6000,3500,1000:Fat,2499,5999,3499,998:Skinny,800,3600,2000,1000"] + +Symbol[' ' 1800] +( +) +Symbol['!' 1200] +( + SymbolLine[0 4500 0 5000 800] + SymbolLine[0 1000 0 3500 800] +) +Symbol['"' 1200] +( + SymbolLine[0 1000 0 2000 800] + SymbolLine[1000 1000 1000 2000 800] +) +Symbol['#' 1200] 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"1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + + ) + +Element["" "1206" "L2" "unknown" 50000 22000 -3000 -12000 0 100 ""] +( + Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" "square"] + Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" "square"] + ElementLine [-8400 -5400 -8400 5400 1000] + ElementLine [-8400 5400 8400 5400 1000] + ElementLine [8400 5400 8400 -5400 1000] + ElementLine [8400 -5400 -8400 -5400 1000] + + ) + +Element["" "0603" "C4" "1uF" 45000 33000 -3000 5000 0 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + + ) + +Element["" "0603" "C3" "0.1uF" 38000 33000 -4000 5000 0 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + + ) + +Element["" "CONNECTOR-1-2" "J1" "unknown" 10000 25000 -3000 -12000 0 100 ""] +( + Pin[0 0 8500 3000 9100 5500 "1" "1" "square"] + Pin[0 10000 8500 3000 9100 5500 "2" "2" "thermal(0)"] + ElementLine [-5000 -5000 5000 -5000 2000] + ElementLine [-5000 -5000 -5000 15000 2000] + ElementLine [-5000 15000 5000 15000 2000] + ElementLine [5000 -5000 5000 15000 2000] + ElementLine [-5000 -5000 -5000 5000 1000] + ElementLine [-5000 5000 5000 5000 1000] + + ) + +Element["" "MSOP8" "U1" "unknown" 93000 28000 -18000 2000 0 100 ""] +( + Pad[-700 0 1500 0 1600 3000 2200 "1" "1" "edge2"] + Pad[-700 -2600 1500 -2600 1600 3000 2200 "2" "2" "square,edge2"] + Pad[-700 -5100 1500 -5100 1600 3000 2200 "3" "3" "square,edge2"] + Pad[-700 -7700 1500 -7700 1600 3000 2200 "4" "4" "square,edge2"] + Pad[-17400 -7800 -15200 -7800 1600 3000 2200 "5" "5" "square"] + Pad[-17400 -5200 -15200 -5200 1600 3000 2200 "6" "6" "square"] + Pad[-17400 -2700 -15200 -2700 1600 3000 2200 "7" "7" "square"] + Pad[-17400 -100 -15200 -100 1600 3000 2200 "8" "8" "square"] + ElementLine [-9100 1200 2300 1200 1000] + ElementLine [-18200 1200 -6700 1200 1000] + ElementLine [-18200 -9000 -18200 1200 1000] + ElementLine [-18200 -9000 2300 -9000 1000] + ElementLine [2300 -9000 2300 1200 1000] + ElementArc [-7900 1200 1200 1200 180 180 1000] + + ) + +Element["" "1206" "C6" "4.7uF" 67000 30000 -3000 -15000 0 100 ""] +( + Pad[-1800 -4800 1800 -4800 4800 2000 5400 "1" "1" "square"] + Pad[-1800 4800 1800 4800 4800 2000 5400 "2" "2" "square"] + ElementLine [-5400 -8400 5400 -8400 1000] + ElementLine [-5400 -8400 -5400 8400 1000] + ElementLine [-5400 8400 5400 8400 1000] + ElementLine [5400 -8400 5400 8400 1000] + + ) + +Element["" "0603" "C2" "220pF" 26000 32000 -3000 5000 0 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + + ) + +Element["" "0603" "C1" "0.1uF" 20000 32000 -3000 5000 0 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + + ) + +Element["" "1206" "L1" "unknown" 32000 22000 -3000 -12000 0 100 ""] +( + Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" "square"] + Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" "square"] + ElementLine [-8400 -5400 -8400 5400 1000] + ElementLine [-8400 5400 8400 5400 1000] + ElementLine [8400 -5400 8400 5400 1000] + ElementLine [-8400 -5400 8400 -5400 1000] + + ) + +Element["" "0603" "R3" "50" 147000 33000 -3000 -10000 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 2700 4200 -2700 600] + ElementLine [4200 -2700 -4200 -2700 600] + + ) + +Element["" "SMA_VERT" "J2" "unknown" 170000 27000 -4000 -23000 0 100 ""] +( + Pin[0 0 9500 3000 10100 6500 "1" "1" ""] + Pin[-10000 10000 9500 3000 10100 6500 "2" "2" "thermal(0)"] + Pin[-10000 -10000 9500 3000 10100 6500 "3" "3" "thermal(0)"] + Pin[10000 10000 9500 3000 10100 6500 "4" "4" "thermal(0)"] + Pin[10000 -10000 9500 3000 10100 6500 "5" "5" "thermal(0)"] + ElementLine [-16000 -16000 16000 -16000 1000] + ElementLine [16000 -16000 16000 16000 1000] + ElementLine [16000 16000 -16000 16000 1000] + ElementLine [-16000 16000 -16000 -16000 1000] + + ) + +Element["" "0603" "C8" "220pF" 91000 34000 5000 3000 1 100 ""] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + + ) + +Element["" "0603" "C9" "0.1uF" 107000 31000 -4000 5000 0 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["" "CTS_OSC" "X1" "unknown" 118000 17000 5000 -12000 0 100 ""] +( + Pad[15190 -20 17190 -20 7100 1596 8696 "" "4" "square,edge2"] + Pad[15190 19980 17190 19980 7100 1596 8696 "" "3" "square,edge2"] + Pad[-1310 -20 690 -20 7100 1596 8696 "" "1" "square"] + Pad[-1310 19980 690 19980 7100 1596 8696 "" "2" "square"] + ElementLine [7400 -2880 10370 -5850 699] + ElementLine [4300 -5980 7400 -2880 699] + ElementLine [4300 -6010 4300 -5980 699] + ElementLine [-7310 25980 23190 25980 699] + ElementLine [-7310 -6020 -7310 25980 699] + ElementLine [-7310 -6020 23190 -6020 699] + ElementLine [23190 -6020 23190 25980 699] + + ) +Layer(1 "solder") +( + Polygon("clearpoly") + ( + [0 0] [190000 0] [190000 50000] [0 50000] + ) +) +Layer(2 "GND-sldr") +( +) +Layer(3 "Vcc-sldr") +( +) +Layer(4 "component") +( + Line[10000 25000 27000 25000 3000 2000 ""] + Line[19100 29600 20000 28700 4000 2000 ""] + Line[20000 28700 20000 25000 3000 2000 ""] + Line[26900 29600 26000 28700 4000 2000 ""] + Line[26000 28700 26000 25000 3000 2000 ""] + Line[36800 20200 38600 22000 4000 2000 ""] + Line[38600 22000 45000 22000 3000 2000 ""] + Line[37100 30600 38000 29700 3000 2000 ""] + Line[38000 29700 38000 25000 4000 2000 ""] + Line[44100 30600 45000 29700 3000 2000 ""] + Line[45000 29700 45000 25000 3000 2000 ""] + Line[54800 23800 56000 25000 3000 2000 ""] + Line[56000 25000 65000 25000 3000 2000 ""] + Line[56100 30600 59000 27700 3000 2000 ""] + Line[59000 27700 59000 26000 3000 2000 ""] + Line[68800 25200 70000 24000 3000 2000 ""] + Line[70000 24000 77000 24000 3000 2000 ""] + Line[77000 24000 77000 28000 3000 2000 ""] + Line[133190 16980 133170 17000 4000 2000 ""] + Line[133170 17000 117000 17000 3000 2000 ""] + Line[149400 32100 154500 27000 3000 2000 ""] + Line[154500 27000 170000 27000 3000 2000 ""] + Line[144600 32100 138700 38000 3000 2000 ""] + Line[138700 38000 134000 38000 4000 2000 ""] + Line[104800 21800 108600 18000 3000 2000 ""] + Line[108600 18000 117000 18000 3000 2000 ""] + Line[107900 28600 117000 19500 3000 2000 ""] + Line[117000 19500 117000 18000 4000 2000 ""] + Line[106100 28600 101000 23500 3000 2000 ""] + Line[101000 23500 101000 23000 3000 2000 ""] + Line[92300 22900 92400 23000 800 2000 ""] + Line[92400 23000 100000 23000 1300 2000 ""] + Line[92300 22900 92000 23200 800 2000 ""] + Line[92000 23200 92000 28000 1300 2000 ""] + Line[93400 33100 93000 32700 800 2000 ""] + Line[93000 32700 93000 28000 1300 2000 ""] + Line[106100 33400 106000 33500 3000 2000 ""] + Line[106000 33500 106000 39000 3000 2000 ""] + Line[116690 36980 118000 38290 4000 2000 ""] + Line[118000 38290 118000 44000 4000 2000 ""] + Line[101200 12200 102000 11400 4000 2000 ""] + Line[102000 11400 102000 6000 4000 2000 ""] + Line[87400 2100 88300 3000 3000 2000 ""] + Line[88300 3000 93000 3000 4000 2000 ""] + Line[75600 20200 80800 15000 1800 2000 ""] + Line[80800 15000 81000 15300 800 2000 ""] + Line[82000 14000 82000 4300 3000 2000 ""] + Line[87400 8100 88000 8700 2999 1998 ""] + Line[88000 8700 88000 21000 2999 1998 ""] + Line[88000 21000 92000 25000 2999 1998 ""] + Line[94000 14000 94000 20000 2499 1996 ""] + Line[88600 33100 85700 36000 2499 1996 ""] + Line[85700 36000 83000 36000 2499 1996 ""] + Line[61000 42000 66000 37000 2499 1996 ""] + Line[66000 37000 66000 35000 2499 1996 ""] + Line[25100 34400 24500 35000 2499 1996 ""] + Line[24500 35000 10000 35000 2499 1996 ""] + Line[37100 35400 41000 39300 2499 1996 ""] + Line[41000 39300 41000 41000 2499 1996 ""] + Line[44100 35400 42000 37500 2499 1996 ""] + Line[42000 37500 42000 42000 2499 1996 ""] + Line[41000 41000 42000 42000 2499 1996 ""] + Line[56100 35400 60000 39300 2499 1996 ""] + Line[60000 39300 60000 42000 2499 1996 ""] + Line[25100 34400 23000 36500 2500 2000 ""] + Line[23000 36500 23000 41000 2500 2000 ""] + Line[19100 34400 23000 38300 2500 2000 ""] + Line[23000 38300 23000 41000 2500 2000 ""] +) +Layer(5 "GND-comp") +( +) +Layer(6 "Vcc-comp") +( +) +Layer(7 "unused") +( +) +Layer(8 "unused") +( +) +Layer(9 "silk") +( +) +Layer(10 "silk") +( +) +NetList() +( + Net("unnamed_net6" "(unknown)") + ( + Connect("C10-2") + Connect("R2-1") + Connect("R1-2") + Connect("U1-5") + ) + Net("unnamed_net5" "(unknown)") + ( + Connect("U1-6") + Connect("U1-7") + Connect("U1-8") + Connect("C5-1") + Connect("L2-2") + Connect("C6-1") + ) + Net("unnamed_net4" "(unknown)") + ( + Connect("C1-1") + Connect("J1-1") + Connect("C2-1") + Connect("L1-1") + ) + Net("unnamed_net3" "(unknown)") + ( + Connect("L2-1") + Connect("C3-1") + Connect("C4-1") + Connect("L1-2") + ) + Net("unnamed_net2" "(unknown)") + ( + Connect("R3-2") + Connect("J2-1") + ) + Net("GND" "(unknown)") + ( + Connect("R2-2") + Connect("U1-4") + Connect("J1-2") + Connect("C5-2") + Connect("C6-2") + Connect("C3-2") + Connect("C4-2") + Connect("C2-2") + Connect("C1-2") + Connect("J2-5") + Connect("J2-4") + Connect("J2-3") + Connect("J2-2") + Connect("C7-2") + Connect("C8-2") + Connect("C9-2") + Connect("X1-2") + ) + Net("DVDD" "(unknown)") + ( + Connect("C10-1") + Connect("R1-1") + Connect("U1-2") + Connect("U1-3") + Connect("U1-1") + Connect("C7-1") + Connect("C8-1") + Connect("C9-1") + Connect("X1-4") + Connect("X1-1") + ) + Net("unnamed_net1" "(unknown)") + ( + Connect("R3-1") + Connect("X1-3") + ) +) diff --git a/usrp-hw/clockfix/clockfix.prj b/usrp-hw/clockfix/clockfix.prj new file mode 100644 index 000000000..787910056 --- /dev/null +++ b/usrp-hw/clockfix/clockfix.prj @@ -0,0 +1,6 @@ +# List all schematics +schematics clockfix.sch + +output-name clockfix + +elements-dir ../pkg/newlib diff --git a/usrp-hw/clockfix/clockfix.sch b/usrp-hw/clockfix/clockfix.sch new file mode 100644 index 000000000..fc0709bf7 --- /dev/null +++ b/usrp-hw/clockfix/clockfix.sch @@ -0,0 +1,333 @@ +v 20040111 1 +C 8200 23400 1 0 0 vctcxo.sym +{ +T 59600 53500 5 10 1 1 0 6 1 +refdes=X1 +T 59300 52600 5 10 0 1 0 0 1 +footprint=CTS_OSC +} +C 57100 53600 1 0 0 generic-power.sym +{ +T 57300 53850 5 10 1 1 0 3 1 +net=DVDD:1 +} +C 57200 51600 1 0 0 gnd-1.sym +C 57100 53300 1 270 0 capacitor-1.sym +{ +T 56800 52500 5 10 1 1 0 0 1 +refdes=C9 +T 56800 52300 5 10 1 1 0 0 1 +value=0.1uF +T 57100 53300 5 10 0 1 0 0 1 +footprint=0603 +} +N 57300 52400 57300 51900 4 +N 57300 53300 57300 53600 4 +N 57300 53500 57700 53500 4 +N 57700 53500 57700 53000 4 +N 57700 53000 57900 53000 4 +N 57300 52100 57700 52100 4 +N 57700 52100 57700 52600 4 +N 57700 52600 57900 52600 4 +C 56300 53300 1 270 0 capacitor-1.sym +{ +T 56000 52500 5 10 1 1 0 0 1 +refdes=C8 +T 55900 52300 5 10 1 1 0 0 1 +value=220pF +T 56300 53300 5 10 0 1 0 0 1 +footprint=0603 +} +N 56500 53500 56500 53300 4 +N 56500 52400 56500 52100 4 +C 60100 52800 1 270 0 generic-power.sym +{ +T 60350 52600 5 10 1 1 270 3 1 +net=DVDD:1 +} +N 59900 52600 60100 52600 4 +C 62500 52500 1 0 1 SMA-5.sym +{ +T 62500 53300 5 10 1 1 0 6 1 +refdes=J2 +T 62500 52500 5 10 0 1 0 0 1 +footprint=SMA_VERT +} +C 60700 52900 1 0 0 resistor-1.sym +{ +T 60900 53200 5 10 1 1 180 8 1 +refdes=R3 +T 60700 52900 5 10 0 1 180 8 1 +footprint=0603 +T 61300 52700 5 10 1 1 0 6 1 +value=50 +} +N 62000 53000 61600 53000 4 +C 62300 52000 1 0 0 gnd-1.sym +N 62400 52300 62400 52500 4 +B 53700 46300 11000 8500 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +T 77900 52800 5 10 0 0 0 0 1 +graphical=1 +B 53900 46500 10600 8100 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 55700 46500 55700 46300 15 0 0 0 -1 -1 +L 57700 46500 57700 46300 15 0 0 0 -1 -1 +L 59700 46500 59700 46300 15 0 0 0 -1 -1 +L 61700 46500 61700 46300 15 0 0 0 -1 -1 +L 63700 46500 63700 46300 15 0 0 0 -1 -1 +L 53900 48300 53700 48300 15 0 0 0 -1 -1 +L 53900 50300 53700 50300 15 0 0 0 -1 -1 +L 53900 52300 53700 52300 15 0 0 0 -1 -1 +L 53900 54300 53700 54300 15 0 0 0 -1 -1 +T 54700 46400 15 8 1 0 0 4 1 +1 +T 56700 46400 15 8 1 0 0 4 1 +2 +T 58700 46400 15 8 1 0 0 4 1 +3 +T 60700 46400 15 8 1 0 0 4 1 +4 +T 62700 46400 15 8 1 0 0 4 1 +5 +T 64200 46400 15 8 1 0 0 4 1 +6 +L 55700 54800 55700 54600 15 0 0 0 -1 -1 +L 57700 54800 57700 54600 15 0 0 0 -1 -1 +L 59700 54800 59700 54600 15 0 0 0 -1 -1 +L 61700 54800 61700 54600 15 0 0 0 -1 -1 +L 63700 54800 63700 54600 15 0 0 0 -1 -1 +T 56700 54700 15 8 1 0 0 4 1 +2 +T 54700 54700 15 8 1 0 0 4 1 +1 +T 58700 54700 15 8 1 0 0 4 1 +3 +T 60700 54700 15 8 1 0 0 4 1 +4 +T 62700 54700 15 8 1 0 0 4 1 +5 +T 64200 54700 15 8 1 0 0 4 1 +6 +T 53800 47300 15 8 1 0 0 4 1 +A +T 53800 49300 15 8 1 0 0 4 1 +B +T 53800 51300 15 8 1 0 0 4 1 +C +T 53800 53300 15 8 1 0 0 4 1 +D +T 53800 54500 15 8 1 0 0 4 1 +E +L 64700 48300 64500 48300 15 0 0 0 -1 -1 +L 64700 50300 64500 50300 15 0 0 0 -1 -1 +L 64700 52300 64500 52300 15 0 0 0 -1 -1 +L 64700 54300 64500 54300 15 0 0 0 -1 -1 +T 64600 54500 15 8 1 0 0 4 1 +E +T 64600 53300 15 8 1 0 0 4 1 +D +T 64600 51300 15 8 1 0 0 4 1 +C +T 64600 49300 15 8 1 0 0 4 1 +B +T 64600 47300 15 8 1 0 0 4 1 +A +L 60400 47100 60400 46500 15 0 0 0 -1 -1 +B 56900 46500 7600 1400 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 56900 47100 64500 47100 15 0 0 0 -1 -1 +T 57500 46900 9 10 1 1 0 0 1 +date=$Date: 2005/06/08 01:00:45 $ +T 61400 46900 9 10 1 1 0 0 1 +rev=$Revision: 1.1 $ +T 62900 46600 9 10 1 1 0 0 1 +auth=$Author: matt $ +T 57700 47200 9 10 1 1 0 0 1 +fname=$Source: /home/matt/usrp-hw-cvs/usrp-hw/clockfix/clockfix.sch,v $ +T 60700 47600 9 14 1 1 0 4 1 +title=USRP Clock Fix Board +T 57000 47200 15 8 1 0 0 0 1 +FILE: +T 60500 46900 15 8 1 0 0 0 1 +REVISION: +T 60500 46600 15 8 1 0 0 0 1 +DRAWN BY: +T 57000 46600 15 8 1 0 0 0 1 +PAGE +T 58700 46600 15 8 1 0 0 0 1 +OF +T 57000 47600 15 8 1 0 0 0 1 +TITLE +T 57000 46900 15 8 1 0 0 0 1 +DATE +T 57600 48300 8 10 0 0 0 0 1 +graphical=1 +T 57700 46600 9 10 1 0 0 0 1 +1 +T 59100 46600 9 10 1 0 0 0 1 +1 +N 59900 53000 60700 53000 4 +C 57000 50700 1 0 0 inductor-1.sym +{ +T 57700 51000 5 10 1 1 0 0 1 +refdes=L1 +T 57000 50700 5 10 0 1 0 0 1 +footprint=1206 +} +C 56200 50500 1 270 0 capacitor-1.sym +{ +T 56100 49700 5 10 1 1 0 0 1 +refdes=C1 +T 55900 49500 5 10 1 1 0 0 1 +value=0.1uF +T 56200 50500 5 10 0 1 0 0 1 +footprint=0603 +} +C 57100 50500 1 90 1 capacitor-1.sym +{ +T 57300 50400 5 10 1 1 0 6 1 +refdes=C2 +T 57000 50200 5 10 1 1 0 0 1 +value=220pF +T 57100 50500 5 10 0 1 0 6 1 +footprint=0603 +} +N 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000000000..e69de29bb --- /dev/null +++ b/usrp-hw/dbsrx/ChangeLog diff --git a/usrp-hw/dbsrx/dbsrx.pcb b/usrp-hw/dbsrx/dbsrx.pcb new file mode 100644 index 000000000..8265a6604 --- /dev/null +++ b/usrp-hw/dbsrx/dbsrx.pcb @@ -0,0 +1,3430 @@ +# release: pcb-bin 1.99q +# date: Mon Dec 12 15:52:53 2005 +# user: matt (Matt Ettus) +# host: localhost.localdomain + +PCB["RX Daughterboard" 275000 250000] + +Grid[500.00000000 0 0 1] +Cursor[196421 139220 3.195331] +Thermal[0.500000] +DRC[699 400 699 499] +Flags(0x0000000000001058) +Groups("1,s:4,c:2:3:5,6,7,8:") +Styles["Signal,798,3599,1798,798:Power,2499,5999,3499,999:Fat,3999,5999,3499,998:RF,1398,3099,1497,798"] + +Symbol[' ' 1800] +( +) +Symbol['!' 1200] +( + SymbolLine[0 3500 0 4000 800] + SymbolLine[0 0 0 2500 800] +) +Symbol['"' 1200] +( + SymbolLine[0 0 0 1000 800] + SymbolLine[1000 0 1000 1000 800] +) +Symbol['#' 1200] +( + SymbolLine[0 2500 2000 2500 800] + SymbolLine[0 1500 2000 1500 800] + SymbolLine[1500 1000 1500 3000 800] + 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89000 5999 1998 0 3499 "" "thermal(1)"] +Via[58500 100500 3499 1596 0 1497 "" "thermal(1)"] +Via[44000 85000 3499 1596 0 1497 "" "thermal(1)"] +Via[177000 135500 3599 1596 0 1798 "" ""] +Via[59000 94000 3499 1596 0 1497 "" ""] +Via[127500 123000 3499 1596 0 1497 "" ""] +Via[73000 90500 3499 1596 0 1497 "" ""] +Via[109000 123000 3499 1596 0 1497 "" ""] +Via[64500 113000 3499 1596 0 1497 "" ""] +Via[131500 126000 3499 1596 0 1497 "" ""] +Via[40000 107000 3499 1596 0 1497 "" ""] +Via[132500 145000 5999 1998 0 3499 "" "thermal(1)"] +Via[225000 115000 5999 1996 0 3499 "" "thermal(1)"] +Via[253500 142000 5999 1996 0 3499 "" "thermal(1)"] +Via[232000 106000 5999 1998 0 3499 "" "thermal(1)"] +Via[168500 181000 3599 1596 0 1798 "" ""] +Via[172500 186500 3599 1596 0 1798 "" ""] +Via[268000 49500 5999 1996 0 3499 "" "thermal(1)"] +Via[254500 47000 5999 1996 0 3499 "" "thermal(1)"] +Via[232500 40000 5999 1998 0 3499 "" "thermal(1)"] +Via[208000 196500 3599 1596 0 1798 "" "thermal(1)"] +Via[216500 45000 3599 1596 0 1798 "" "thermal(1)"] +Via[244000 50500 3599 1596 0 1798 "" ""] +Via[210000 55500 3599 1596 0 1798 "" ""] +Via[178000 123500 5999 1998 0 3499 "" ""] +Via[140000 159000 5999 1998 0 3499 "" ""] +Via[178500 236000 5999 1998 0 3499 "" "thermal(1)"] +Via[145000 237000 5999 1998 0 3499 "" "thermal(1)"] +Via[193500 38500 3599 1596 0 1798 "" ""] +Via[170500 45000 3599 1596 0 1798 "" "thermal(1)"] +Via[195000 139000 3599 1596 0 1798 "" "thermal(1)"] +Via[127000 162000 3599 1596 0 1798 "" "thermal(1)"] +Via[127000 167500 3599 1596 0 1798 "" "thermal(1)"] +Via[194500 49500 3599 1596 0 1798 "" ""] +Via[195000 34000 3599 1596 0 1798 "" ""] +Via[130000 131500 5999 1996 0 3499 "" ""] +Via[236000 78000 5999 1996 0 3499 "" ""] +Via[199000 169000 3099 1596 0 1497 "" "thermal(0,1)"] +Via[156500 190000 3499 1598 0 1497 "" "thermal(1)"] +Via[156500 164000 3499 1598 0 1497 "" "thermal(1)"] +Via[223500 193500 3599 1596 0 1798 "" "thermal(1)"] +Via[232000 183500 3599 1596 0 1798 "" "thermal(1)"] +Via[184500 219500 3599 1596 0 1798 "" "thermal(1)"] +Via[185000 204500 3599 1596 0 1798 "" "thermal(1)"] +Via[175500 167000 3599 1596 0 1798 "" "usetherm,thermal(2)"] +Via[217000 165000 3599 1596 0 1798 "" "usetherm,thermal(2)"] +Via[187500 50000 3599 1596 0 1798 "" "usetherm,thermal(2)"] +Via[212500 201500 3599 1596 0 1798 "" "usetherm,thermal(2)"] +Via[174000 213500 3599 1596 0 1798 "" "usetherm,thermal(2)"] +Via[180500 187500 3599 1596 0 1798 "" "usetherm,thermal(2)"] +Via[241500 42500 5999 1998 0 3499 "" "usetherm,thermal(2)"] +Via[264000 94500 5999 1996 0 3499 "" "usetherm,thermal(2)"] +Via[195500 155500 3599 1596 0 1798 "" "usetherm,thermal(2)"] +Via[188000 155500 3599 1596 0 1798 "" "usetherm,thermal(2)"] +Via[264500 117000 5999 1996 0 3499 "" "usetherm,thermal(2)"] +Via[139000 75000 3599 1596 0 1798 "" ""] +Via[149000 67500 3599 1596 0 1798 "" ""] +Via[208500 178500 3599 1596 0 1798 "" ""] +Via[122500 120500 3499 1596 0 1497 "" ""] +Via[141000 120000 3599 1596 0 1798 "" ""] +Via[137500 126500 3599 1596 0 1798 "" ""] +Via[143000 124500 3599 1596 0 1798 "" ""] +Via[188500 139500 3599 1596 0 1798 "" ""] +Via[211500 136500 3599 1596 0 1798 "" ""] +Via[232000 150000 3599 1596 0 1798 "" ""] +Via[228500 141000 3599 1596 0 1798 "" ""] +Via[205500 145500 3599 1596 0 1798 "" ""] +Via[239500 159500 3599 1596 0 1798 "" ""] +Via[159500 136500 3599 1596 0 1798 "" ""] +Via[159500 154000 3599 1596 0 1798 "" ""] +Via[201000 86500 3599 1596 0 1798 "" "thermal(1)"] +Via[189500 121500 3599 1596 0 1798 "" "thermal(1)"] +Via[207500 191500 3599 1596 0 1798 "" "usetherm,thermal(2)"] +Via[204500 159000 3599 1596 0 1798 "" "thermal(1)"] +Via[188000 169000 3099 1596 0 1497 "" "thermal(0,1)"] +Via[188000 172500 3099 1596 0 1497 "" "thermal(0,1)"] +Via[188000 176000 3099 1596 0 1497 "" "thermal(0,1)"] +Via[188000 179500 3099 1596 0 1497 "" "thermal(0,1)"] +Via[191000 178000 3099 1596 0 1497 "" "thermal(0,1)"] +Via[191000 174500 3099 1596 0 1497 "" "thermal(0,1)"] +Via[191000 170500 3099 1596 0 1497 "" "thermal(0,1)"] +Via[193500 168500 3099 1596 0 1497 "" "thermal(0,1)"] +Via[193500 172500 3099 1596 0 1497 "" "thermal(0,1)"] +Via[194000 176500 3099 1596 0 1497 "" "thermal(0,1)"] +Via[193500 180000 3099 1596 0 1497 "" "thermal(0,1)"] +Via[196500 178500 3099 1596 0 1497 "" "thermal(0,1)"] +Via[199500 180000 3099 1596 0 1497 "" "thermal(0,1)"] +Via[199000 176500 3099 1596 0 1497 "" "thermal(0,1)"] +Via[196500 174500 3099 1596 0 1497 "" "thermal(0,1)"] +Via[199000 172500 3099 1596 0 1497 "" "thermal(0,1)"] +Via[196000 170500 3099 1596 0 1497 "" "thermal(0,1)"] +Via[150500 189000 3099 1596 0 1497 "" "thermal(1)"] +Via[123000 174500 3099 1596 0 1497 "" "thermal(1)"] +Via[111500 160500 3099 1596 0 1497 "" "thermal(1)"] +Via[118500 160500 3099 1596 0 1497 "" "thermal(1)"] +Via[122000 165500 3099 1596 0 1497 "" "thermal(1)"] +Via[141000 185000 3099 1596 0 1497 "" "thermal(1)"] +Via[147000 184000 3099 1596 0 1497 "" "thermal(1)"] +Via[151500 185000 3099 1596 0 1497 "" "thermal(1)"] +Via[136500 193000 3099 1596 0 1497 "" "thermal(1)"] +Via[145500 191500 3099 1596 0 1497 "" "thermal(1)"] +Via[140000 198500 3099 1596 0 1497 "" "thermal(1)"] +Via[147000 199500 3099 1596 0 1497 "" "thermal(1)"] +Via[154500 201000 3099 1596 0 1497 "" "thermal(1)"] +Via[129500 174500 3099 1596 0 1497 "" "thermal(1)"] +Via[115000 123500 3599 1596 0 1798 "" ""] +Via[156000 52500 3599 1596 0 1798 "" ""] +Via[147500 208000 5999 1996 0 3499 "" "thermal(2)"] + +Element["" "0603" "R6" "1K" 200500 38500 -12000 -7000 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 3000 2400 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 3000 2400 "2" "2" "square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["onsolder" "0603" "C26" "100pF" 186500 82500 -5500 -15000 0 100 "auto"] +( + Pad[2400 -900 2400 900 2400 3000 2400 "1" "1" "auto,square"] + Pad[-2400 -900 -2400 900 2400 3000 2400 "2" "2" "auto,square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element["" "0603" "R7" "1K" 209500 38500 5500 -2000 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 3000 2400 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 3000 2400 "2" "2" "square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["" "0603" "C83" ".01uF" 201000 195500 -3500 18300 0 100 ""] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element["onsolder" "0603" "R10" "50" 208500 75000 -4500 -22500 1 100 "auto"] +( + Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" "auto,square"] + Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" "auto,square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["onsolder" "0603" "R15" "50" 194000 75000 -700 -22500 1 100 "auto"] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "auto,square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "auto,square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["" "0603" "R19" "250,_0.1%" 181000 81000 -1500 6300 0 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["" "0603" "R20" "250,_0.1%" 172500 81000 -11500 5800 0 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["" "0603" "C59" "3300pF" 192000 201500 -5000 16800 0 100 ""] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element["" "0603" "R9" "43.2" 159000 175500 -12500 -19500 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 3000 2400 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 3000 2400 "2" "2" "square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["" "CONNECTOR-1-2" "J100" "unknown" 103500 225000 -5500 17000 0 100 ""] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" "square"] + Pin[0 10000 6000 3000 6600 4000 "2" "2" "thermal(1)"] + ElementLine [-5000 5000 5000 5000 1000] + ElementLine [-5000 -5000 -5000 5000 1000] + ElementLine [5000 -5000 5000 15000 2000] + ElementLine [-5000 15000 5000 15000 2000] + ElementLine [-5000 -5000 -5000 15000 2000] + ElementLine [-5000 -5000 5000 -5000 2000] + + ) + +Element["" "CONNECTOR-8-2" "J25" "unknown" 8000 24000 27700 9900 0 100 ""] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" "square,edge2"] + Pin[0 -10000 6000 3000 6600 4000 "2" "2" "edge2,thermal(1)"] + Pin[10000 0 6000 3000 6600 4000 "3" "3" "edge2"] + Pin[10000 -10000 6000 3000 6600 4000 "4" "4" "edge2,thermal(1)"] + Pin[20000 0 6000 3000 6600 4000 "5" "5" "edge2"] + Pin[20000 -10000 6000 3000 6600 4000 "6" "6" "edge2,thermal(1)"] + Pin[30000 0 6000 3000 6600 4000 "7" "7" "edge2"] + Pin[30000 -10000 6000 3000 6600 4000 "8" "8" "edge2,thermal(1)"] + Pin[40000 0 6000 3000 6600 4000 "9" "9" "edge2"] + Pin[40000 -10000 6000 3000 6600 4000 "10" "10" "edge2,thermal(1)"] + Pin[50000 0 6000 3000 6600 4000 "11" "11" "edge2"] + Pin[50000 -10000 6000 3000 6600 4000 "12" "12" "edge2,thermal(1)"] + Pin[60000 0 6000 3000 6600 4000 "13" "13" "edge2"] + Pin[60000 -10000 6000 3000 6600 4000 "14" "14" "edge2,thermal(1)"] + Pin[70000 0 6000 3000 6600 4000 "15" "15" "edge2"] + Pin[70000 -10000 6000 3000 6600 4000 "16" "16" "edge2,thermal(1)"] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [-5000 -15000 75000 -15000 2000] + ElementLine [75000 -15000 75000 5000 2000] + ElementLine [-5000 5000 75000 5000 2000] + + ) + +Element["onsolder,lock" "PMC-REVERSE" "J2" "unknown" 94993 95811 -18000 9000 0 100 "auto"] +( + Pin[-6693 7189 7200 2000 7200 5800 "" "1" "hole,lock,edge2"] + Pin[128740 7189 7200 2000 7200 5800 "" "2" "hole,lock,edge2"] + Pad[0 9900 0 19000 2400 1000 3400 "" "1" "auto,lock,edge2"] + Pad[122047 -4622 122047 4478 2400 1000 3400 "" "64" "auto,lock"] + Pad[7874 9900 7874 19000 2400 1000 3400 "" "5" "auto,lock,edge2"] + Pad[3937 9900 3937 19000 2400 1000 3400 "" "3" "auto,lock,edge2"] + Pad[11811 9900 11811 19000 2400 1000 3400 "" "7" "auto,lock,edge2"] + Pad[0 -4622 0 4478 2400 1000 3400 "" "2" "auto,lock"] + Pad[15748 9900 15748 19000 2400 1000 3400 "" "9" "auto,lock,edge2"] + Pad[7874 -4622 7874 4478 2400 1000 3400 "" "6" "auto,lock"] + Pad[19685 9900 19685 19000 2400 1000 3400 "" "11" "auto,lock,edge2"] + Pad[11811 -4622 11811 4478 2400 1000 3400 "" "8" "auto,lock"] + Pad[23622 9900 23622 19000 2400 1000 3400 "" "13" "auto,lock,edge2"] + Pad[15748 -4622 15748 4478 2400 1000 3400 "" "10" "auto,lock"] + Pad[27559 9900 27559 19000 2400 1000 3400 "" "15" "auto,lock,edge2"] + Pad[19685 -4622 19685 4478 2400 1000 3400 "" "12" "auto,lock"] + Pad[31496 9900 31496 19000 2400 1000 3400 "" "17" "auto,lock,edge2"] + Pad[23622 -4622 23622 4478 2400 1000 3400 "" "14" "auto,lock"] + Pad[35433 9900 35433 19000 2400 1000 3400 "" "19" "auto,lock,edge2"] + Pad[27559 -4622 27559 4478 2400 1000 3400 "" "16" "auto,lock"] + Pad[39370 9900 39370 19000 2400 1000 3400 "" "21" "auto,lock,edge2"] + Pad[31496 -4622 31496 4478 2400 1000 3400 "" "18" "auto,lock"] + Pad[35433 -4622 35433 4478 2400 1000 3400 "" "20" "auto,lock"] + Pad[39370 -4622 39370 4478 2400 1000 3400 "" "22" "auto,lock"] + Pad[43307 -4622 43307 4478 2400 1000 3400 "" "24" "auto,lock"] + Pad[47244 -4622 47244 4478 2400 1000 3400 "" "26" "auto,lock"] + Pad[51181 -4622 51181 4478 2400 1000 3400 "" "28" "auto,lock"] + Pad[55118 -4622 55118 4478 2400 1000 3400 "" "30" "auto,lock"] + Pad[59055 -4622 59055 4478 2400 1000 3400 "" "32" "auto,lock"] + Pad[62992 -4622 62992 4478 2400 1000 3400 "" "34" "auto,lock"] + Pad[66929 -4622 66929 4478 2400 1000 3400 "" "36" "auto,lock"] + Pad[70866 -4622 70866 4478 2400 1000 3400 "" "38" "auto,lock"] + Pad[74803 -4622 74803 4478 2400 1000 3400 "" "40" "auto,lock"] + Pad[78740 -4622 78740 4478 2400 1000 3400 "" "42" "auto,lock"] + Pad[82677 -4622 82677 4478 2400 1000 3400 "" "44" "auto,lock"] + Pad[86614 -4622 86614 4478 2400 1000 3400 "" "46" "auto,lock"] + Pad[90551 -4622 90551 4478 2400 1000 3400 "" "48" "auto,lock"] + Pad[98425 -4622 98425 4478 2400 1000 3400 "" "52" "auto,lock"] + Pad[94488 -4622 94488 4478 2400 1000 3400 "" "50" "auto,lock"] + Pad[102362 -4622 102362 4478 2400 1000 3400 "" "54" "auto,lock"] + Pad[106299 -4622 106299 4478 2400 1000 3400 "" "56" "auto,lock"] + Pad[110236 -4622 110236 4478 2400 1000 3400 "" "58" "auto,lock"] + Pad[114173 -4622 114173 4478 2400 1000 3400 "" "60" "auto,lock"] + Pad[3937 -4622 3937 4478 2400 1000 3400 "" "4" "auto,lock"] + Pad[43307 9900 43307 19000 2400 1000 3400 "" "23" "auto,lock,edge2"] + Pad[47244 9900 47244 19000 2400 1000 3400 "" "25" "auto,lock,edge2"] + Pad[51181 9900 51181 19000 2400 1000 3400 "" "27" "auto,lock,edge2"] + Pad[55118 9900 55118 19000 2400 1000 3400 "" "29" "auto,lock,edge2"] + Pad[59055 9900 59055 19000 2400 1000 3400 "" "31" "auto,lock,edge2"] + Pad[62992 9900 62992 19000 2400 1000 3400 "" "33" "auto,lock,edge2"] + Pad[66929 9900 66929 19000 2400 1000 3400 "" "35" "auto,lock,edge2"] + Pad[70866 9900 70866 19000 2400 1000 3400 "" "37" "auto,lock,edge2"] + Pad[74803 9900 74803 19000 2400 1000 3400 "" "39" "auto,lock,edge2"] + Pad[78740 9900 78740 19000 2400 1000 3400 "" "41" "auto,lock,edge2"] + Pad[82677 9900 82677 19000 2400 1000 3400 "" "43" "auto,lock,edge2"] + Pad[86614 9900 86614 19000 2400 1000 3400 "" "45" "auto,lock,edge2"] + Pad[90551 9900 90551 19000 2400 1000 3400 "" "47" "auto,lock,edge2"] + Pad[94488 9900 94488 19000 2400 1000 3400 "" "49" "auto,lock,edge2"] + Pad[98425 9900 98425 19000 2400 1000 3400 "" "51" "auto,lock,edge2"] + Pad[102362 9900 102362 19000 2400 1000 3400 "" "53" "auto,lock,edge2"] + Pad[106299 9900 106299 19000 2400 1000 3400 "" "55" "auto,lock,edge2"] + Pad[110236 9900 110236 19000 2400 1000 3400 "" "57" "auto,lock,edge2"] + Pad[114173 9900 114173 19000 2400 1000 3400 "" "59" "auto,lock,edge2"] + Pad[118110 9900 118110 19000 2400 1000 3400 "" "61" "auto,lock,edge2"] + Pad[122047 9900 122047 19000 2400 1000 3400 "" "63" "auto,lock,edge2"] + Pad[118110 -4622 118110 4478 2400 1000 3400 "" "62" "auto,lock"] + ElementLine [134000 -9000 134000 24000 1000] + ElementLine [-11000 24000 134000 24000 1000] + ElementLine [-11000 -9000 134000 -9000 1000] + ElementLine [-11000 -9000 -11000 24000 1000] + + ) + +Element["" "0603" "C85" "22pF" 153000 62000 -2700 15500 1 100 ""] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["onsolder" "0603" "C25" "100pF" 195500 82500 -4000 -15000 0 100 "auto"] +( + Pad[-2400 -900 -2400 900 2400 3000 2400 "1" "1" "auto,square"] + Pad[2400 -900 2400 900 2400 3000 2400 "2" "2" "auto,square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["" "0603" "C99" "47pF" 126500 181000 -4500 3800 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["" "SO8" "U6" "unknown" 178500 62000 -2500 10500 0 100 ""] +( + Pad[7000 7500 13500 7500 2000 1000 3000 "1" "1" "square,edge2"] + Pad[7000 2500 13500 2500 2000 1000 3000 "2" "2" "square,edge2"] + Pad[7000 -2500 13500 -2500 2000 1000 3000 "3" "3" "square,edge2"] + Pad[7000 -7500 13500 -7500 2000 1000 3000 "4" "4" "square,edge2"] + Pad[-13500 -7500 -7000 -7500 2000 1000 3000 "5" "5" "square"] + Pad[-13500 -2500 -7000 -2500 2000 1000 3000 "6" "6" "square"] + Pad[-13500 2500 -7000 2500 2000 1000 3000 "7" "7" "square"] + Pad[-13500 7500 -7000 7500 2000 1000 3000 "8" "8" "square"] + ElementLine [-15500 9500 -2500 9500 1000] + ElementLine [2500 9500 15500 9500 1000] + ElementLine [-15500 -9500 -15500 9500 1000] + ElementLine [-15500 -9500 15500 -9500 1000] + ElementLine [15500 -9500 15500 9500 1000] + ElementArc [0 9500 2500 2500 180 180 1000] + + ) + +Element["onsolder" "1206" "L600" "unknown" 104000 133500 -23000 2400 0 100 "auto"] +( + Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" "auto,square"] + Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" "auto,square"] + ElementLine [-8400 5400 8400 5400 1000] + ElementLine [8400 -5400 8400 5400 1000] + ElementLine [-8400 -5400 8400 -5400 1000] + ElementLine [-8400 -5400 -8400 5400 1000] + + ) + +Element["" "0603" "R68" "250,_0.1%" 226000 81000 3400 -600 0 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["" "0603" "R13" "1K" 201000 201500 -4000 16300 0 100 ""] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element["" "QFN40_6_EP" "U3" "unknown" 193000 174000 -21200 7800 0 100 ""] +( + Pad[-12200 -8800 -10500 -8800 1100 3000 1700 "1" "1" ""] + Pad[-12200 -6800 -10500 -6800 1100 3000 1700 "2" "2" ""] + Pad[-12200 -4900 -10500 -4900 1100 3000 1700 "3" "3" ""] + Pad[-12200 -2900 -10500 -2900 1100 3000 1700 "4" "4" ""] + Pad[-12200 -900 -10500 -900 1100 3000 1700 "5" "5" ""] + Pad[-12200 900 -10500 900 1100 3000 1700 "6" "6" ""] + Pad[-12200 2900 -10500 2900 1100 3000 1700 "7" "7" ""] + Pad[-12200 4900 -10500 4900 1100 3000 1700 "8" "8" ""] + Pad[-12200 6800 -10500 6800 1100 3000 1700 "9" "9" ""] + Pad[-12200 8800 -10500 8800 1100 3000 1700 "10" "10" ""] + Pad[-8800 10500 -8800 12200 1100 3000 1700 "11" "11" "edge2"] + Pad[-6800 10500 -6800 12200 1100 3000 1700 "12" "12" "edge2"] + Pad[-4900 10500 -4900 12200 1100 3000 1700 "13" "13" "edge2"] + Pad[-2900 10500 -2900 12200 1100 3000 1700 "14" "14" "edge2"] + Pad[-900 10500 -900 12200 1100 3000 1700 "15" "15" "edge2"] + Pad[900 10500 900 12200 1100 3000 1700 "16" "16" "edge2"] + Pad[2900 10500 2900 12200 1100 3000 1700 "17" "17" "edge2"] + Pad[4900 10500 4900 12200 1100 3000 1700 "18" "18" "edge2"] + Pad[6800 10500 6800 12200 1100 3000 1700 "19" "19" "edge2"] + Pad[8800 10500 8800 12200 1100 3000 1700 "20" "20" "edge2"] + Pad[10500 8800 12200 8800 1100 3000 1700 "21" "21" "edge2"] + Pad[10500 6800 12200 6800 1100 3000 1700 "22" "22" "edge2"] + Pad[10500 4900 12200 4900 1100 3000 1700 "23" "23" "edge2"] + Pad[10500 2900 12200 2900 1100 3000 1700 "24" "24" "edge2"] + Pad[10500 900 12200 900 1100 3000 1700 "25" "25" "edge2"] + Pad[10500 -900 12200 -900 1100 3000 1700 "26" "26" "edge2"] + Pad[10500 -2900 12200 -2900 1100 3000 1700 "27" "27" "edge2"] + Pad[10500 -4900 12200 -4900 1100 3000 1700 "28" "28" "edge2"] + Pad[10500 -6800 12200 -6800 1100 3000 1700 "29" "29" "edge2"] + Pad[10500 -8800 12200 -8800 1100 3000 1700 "30" "30" "edge2"] + Pad[8800 -12200 8800 -10500 1100 3000 1700 "31" "31" ""] + Pad[6800 -12200 6800 -10500 1100 3000 1700 "32" "32" ""] + Pad[4900 -12200 4900 -10500 1100 3000 1700 "33" "33" ""] + Pad[2900 -12200 2900 -10500 1100 3000 1700 "34" "34" ""] + Pad[900 -12200 900 -10500 1100 3000 1700 "35" "35" ""] + Pad[-900 -12200 -900 -10500 1100 3000 1700 "36" "36" ""] + Pad[-2900 -12200 -2900 -10500 1100 3000 1700 "37" "37" ""] + Pad[-4900 -12200 -4900 -10500 1100 3000 1700 "38" "38" ""] + Pad[-6800 -12200 -6800 -10500 1100 3000 1700 "39" "39" ""] + Pad[-8800 -12200 -8800 -10500 1100 3000 1700 "40" "40" ""] + Pad[0 0 0 0 16100 3000 16700 "41" "41" "square,edge2"] + ElementLine [-13700 -13700 -15200 -15200 1000] + ElementLine [-13700 13700 13700 13700 1000] + ElementLine [-13700 -13700 -13700 13700 1000] + ElementLine [-13700 -13700 13700 -13700 1000] + ElementLine [13700 -13700 13700 13700 1000] + + ) + +Element["onsolder" "0603" "L100" "27nH" 104000 191500 -16000 8700 0 100 "auto"] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "auto,square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "auto,square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["" "0603" "R66" "250,_0.1%" 257000 62000 -1200 15500 1 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["" "0603" "R67" "250,_0.1%" 246500 79500 4500 -200 0 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["onsolder" "0603" "C100" ".1uF" 111000 201500 -1000 7700 0 100 "auto"] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "auto,square"] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "auto,square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 2700 -4200 -2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 2700 4200 -2700 600] + + ) + +Element["" "0603" "C84" ".1uF" 192000 207500 -5300 16300 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["" "SO8" "U5" "unknown" 236500 62000 -2500 11000 0 100 ""] +( + Pad[7000 7500 13500 7500 2000 1000 3000 "1" "1" "square,edge2"] + Pad[7000 2500 13500 2500 2000 1000 3000 "2" "2" "square,edge2"] + Pad[7000 -2500 13500 -2500 2000 1000 3000 "3" "3" "square,edge2"] + Pad[7000 -7500 13500 -7500 2000 1000 3000 "4" "4" "square,edge2"] + Pad[-13500 -7500 -7000 -7500 2000 1000 3000 "5" "5" "square"] + Pad[-13500 -2500 -7000 -2500 2000 1000 3000 "6" "6" "square"] + Pad[-13500 2500 -7000 2500 2000 1000 3000 "7" "7" "square"] + Pad[-13500 7500 -7000 7500 2000 1000 3000 "8" "8" "square"] + ElementLine [-15500 9500 -2500 9500 1000] + ElementLine [2500 9500 15500 9500 1000] + ElementLine [-15500 -9500 -15500 9500 1000] + ElementLine [-15500 -9500 15500 -9500 1000] + ElementLine [15500 -9500 15500 9500 1000] + ElementArc [0 9500 2500 2500 180 180 1000] + + ) + +Element["" "SC70_6" "U4" "unknown" 134100 175900 400 7600 0 100 ""] +( + Pad[-1000 0 1000 0 1500 3000 2100 "1" "1" "square"] + Pad[-1000 2600 1000 2600 1500 3000 2100 "2" "2" "square"] + Pad[-1000 5100 1000 5100 1500 3000 2100 "3" "3" "square"] + Pad[6000 5100 8000 5100 1500 3000 2100 "4" "4" "square,edge2"] + Pad[6000 2600 8000 2600 1500 3000 2100 "5" "5" "square,edge2"] + Pad[6000 0 8000 0 1500 3000 2100 "6" "6" "square,edge2"] + ElementLine [9400 -1400 9400 6600 1000] + ElementLine [-2500 6600 9400 6600 1000] + ElementLine [-2500 -1400 -2500 6600 1000] + ElementLine [-2500 -1400 9400 -1400 1000] + + ) + +Element["" "0603" "R14" "2.21K" 201000 207500 -4000 16300 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["onsolder" "0603" "R16" "50" 188000 75000 -4200 -22000 1 100 "auto"] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "auto,square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "auto,square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["" "0603" "C67" "22pF" 264000 62000 300 15000 1 100 ""] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["" "0603" "C61" ".1uF" 214900 183500 20600 -2100 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["onsolder" "0603" "C63" ".1uF" 154500 69500 -14000 1200 0 100 "auto"] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "auto,square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "auto,square"] + ElementLine [-2700 4200 -2700 -4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 4200 2700 -4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["onsolder" "0603" "C65" "100pF" 216000 82500 -2000 -14800 0 100 "auto"] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "auto,square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "auto,square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["onsolder" "0603" "R71" "50" 214500 75000 -200 -23500 1 100 "auto"] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "auto,square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "auto,square"] + ElementLine [-2700 4200 -2700 -4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 4200 2700 -4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["onsolder" "0603" "C64" "100pF" 207000 82500 -3500 -14800 0 100 "auto"] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "auto,square"] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "auto,square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element["" "0603" "R17" "250,_0.1%" 159000 62000 -2200 15500 1 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["" "CONNECTOR-8-2" "J24" "unknown" 104500 24000 -16200 -7100 0 100 ""] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" "square,edge2"] + Pin[0 -10000 6000 3000 6600 4000 "2" "2" "edge2,thermal(1)"] + Pin[10000 0 6000 3000 6600 4000 "3" "3" "edge2"] + Pin[10000 -10000 6000 3000 6600 4000 "4" "4" "edge2,thermal(1)"] + Pin[20000 0 6000 3000 6600 4000 "5" "5" "edge2"] + Pin[20000 -10000 6000 3000 6600 4000 "6" "6" "edge2,thermal(1)"] + Pin[30000 0 6000 3000 6600 4000 "7" "7" "edge2"] + Pin[30000 -10000 6000 3000 6600 4000 "8" "8" "edge2,thermal(1)"] + Pin[40000 0 6000 3000 6600 4000 "9" "9" "edge2"] + Pin[40000 -10000 6000 3000 6600 4000 "10" "10" "edge2,thermal(1)"] + Pin[50000 0 6000 3000 6600 4000 "11" "11" "edge2"] + Pin[50000 -10000 6000 3000 6600 4000 "12" "12" "edge2,thermal(1)"] + Pin[60000 0 6000 3000 6600 4000 "13" "13" "edge2"] + Pin[60000 -10000 6000 3000 6600 4000 "14" "14" "edge2,thermal(1)"] + Pin[70000 0 6000 3000 6600 4000 "15" "15" "edge2"] + Pin[70000 -10000 6000 3000 6600 4000 "16" "16" "edge2,thermal(1)"] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [-5000 -15000 75000 -15000 2000] + ElementLine [75000 -15000 75000 5000 2000] + ElementLine [-5000 5000 75000 5000 2000] + + ) + +Element["onsolder" "SO8" "U1" "unknown" 46000 105500 7000 9500 0 100 "auto"] +( + Pad[-1900 0 900 0 2000 3000 2000 "1" "1" "auto,square"] + Pad[-1900 -5000 900 -5000 2000 3000 2000 "2" "2" "auto,square"] + Pad[-1900 -10000 900 -10000 2000 3000 2000 "3" "3" "auto,square"] + Pad[-1900 -15000 900 -15000 2000 3000 2000 "4" "4" "auto,square"] + Pad[18500 -15000 21300 -15000 2000 3000 2000 "5" "5" "auto,square,edge2"] + Pad[18500 -10000 21300 -10000 2000 3000 2000 "6" "6" "auto,square,edge2"] + Pad[18500 -5000 21300 -5000 2000 3000 2000 "7" "7" "auto,square,edge2"] + Pad[18500 0 21300 0 2000 3000 2000 "8" "8" "auto,square,edge2"] + ElementLine [-2900 -17500 -2900 2500 1000] + ElementLine [-2900 -17500 22300 -17500 1000] + ElementLine [22300 -17500 22300 2500 1000] + ElementLine [7200 2500 22300 2500 1000] + ElementLine [-2900 2500 12200 2500 1000] + ElementArc [9700 2500 2500 2500 180 180 1000] + + ) + +Element["" "EIA6032" "C82" "100uF" 161000 227500 -4000 18200 0 100 ""] +( + Pad[-3900 -9400 3900 -9400 9700 2000 10300 "1" "1" "square"] + Pad[-3900 9400 3900 9400 9700 2000 10300 "2" "2" "square"] + ElementLine [11200 -13000 8700 -17800 1000] + ElementLine [11200 -13000 11200 16800 1000] + ElementLine [-11200 16800 11200 16800 1000] + ElementLine [-11200 -13000 -11200 16800 1000] + ElementLine [-8700 -17800 -11200 -13000 1000] + ElementLine [-8700 -17800 8700 -17800 2000] + + ) + +Element["" "0603" "C74" "1000pF" 169500 163500 -14000 -18700 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["" "0603" "C77" "1000pF" 211000 162000 -5000 -10700 0 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["" "0603" "C73" "47pF" 168000 169500 -12500 -18700 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["onsolder" "0603" "R21" "1K" 193500 128500 4500 2200 0 100 "auto"] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" "auto,square"] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" "auto,square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element["onsolder" "0603" "C261" "200pF" 162000 76000 5500 2200 0 100 "auto"] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "auto,square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "auto,square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["" "0603" "C76" "1000pF" 215000 195500 20000 -2700 0 100 ""] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element["" "0603" "C98" "10nF" 133500 162500 -6500 -14700 0 100 ""] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" "square"] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element["" "0603" "C79" "1000pF" 195000 145500 -3500 -13700 0 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["onsolder" "0603" "C78" "1000pF" 195000 145500 -400 -5600 3 100 "auto"] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "auto,square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "auto,square"] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["" "0603" "R93" "50" 224500 183500 22500 -2200 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["" "0603" "C68" ".1uF" 170500 155500 -3200 -5000 1 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element["" "0603" "C69" ".1uF" 181000 155000 -5000 -7700 0 100 ""] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" "square"] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" "square"] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element["" "0603" "C70" ".22uF" 190500 194000 -4500 18300 0 100 ""] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" "square"] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" "square"] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] 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Connect("R194-1") + Connect("C261-1") + Connect("R193-2") + Connect("C63-2") + ) + Net("unnamed_net28" "(unknown)") + ( + Connect("R93-1") + Connect("C61-2") + ) + Net("unnamed_net27" "(unknown)") + ( + Connect("C73-1") + Connect("R11-2") + ) + Net("unnamed_net26" "(unknown)") + ( + Connect("U4-6") + Connect("L98-2") + Connect("C96-1") + ) + Net("unnamed_net25" "(unknown)") + ( + Connect("U4-3") + Connect("C99-2") + ) + Net("unnamed_net24" "(unknown)") + ( + Connect("L100-2") + Connect("J3-1") + Connect("C99-1") + ) + Net("unnamed_net23" "(unknown)") + ( + Connect("R40-2") + Connect("C96-2") + Connect("R9-1") + ) + Net("unnamed_net22" "(unknown)") + ( + Connect("C72-1") + Connect("R9-2") + ) + Net("unnamed_net21" "(unknown)") + ( + Connect("R19-2") + Connect("U3-36") + ) + Net("unnamed_net20" "(unknown)") + ( + Connect("R20-2") + Connect("U3-37") + ) + Net("unnamed_net19" "(unknown)") + ( + Connect("R22-1") + Connect("R21-1") + Connect("C87-2") + Connect("U3-7") + ) + Net("unnamed_net18" "(unknown)") + ( + Connect("C73-2") + Connect("U3-4") + ) + Net("unnamed_net17" "(unknown)") + ( + Connect("C72-2") + Connect("U3-5") + ) + Net("VccVCO" "(unknown)") + ( + Connect("R12-1") + Connect("C82-1") + Connect("C80-1") + Connect("U3-13") + ) + Net("unnamed_net16" "(unknown)") + ( + Connect("C71-1") + Connect("U3-20") + ) + Net("unnamed_net15" "(unknown)") + ( + Connect("C70-1") + Connect("U3-14") + ) + Net("unnamed_net14" "(unknown)") + ( + Connect("C69-1") + Connect("U3-40") + ) + Net("unnamed_net13" "(unknown)") + ( + Connect("C69-2") + Connect("U3-39") + ) + Net("unnamed_net12" "(unknown)") + ( + Connect("C68-1") + Connect("U3-1") + ) + Net("unnamed_net11" "(unknown)") + ( + Connect("C68-2") + Connect("U3-2") + ) + Net("unnamed_net10" "(unknown)") + ( + Connect("C63-1") + Connect("C61-1") + Connect("U3-21") + ) + Net("unnamed_net9" "(unknown)") + ( + Connect("C83-2") + Connect("R14-2") + Connect("R13-1") + Connect("U3-17") + ) + Net("unnamed_net8" "(unknown)") + ( + Connect("R13-2") + Connect("C59-1") + Connect("U3-16") + ) + Net("unnamed_net7" "(unknown)") + ( + Connect("Q1-3") + Connect("U3-26") + ) + Net("unnamed_net6" "(unknown)") + ( + Connect("U3-34") + Connect("R68-2") + ) + Net("unnamed_net5" "(unknown)") + ( + Connect("U3-33") + Connect("R67-2") + ) + Net("5V_RF" "(unknown)") + ( + Connect("J101-2") + Connect("C182-1") + Connect("U2-3") + Connect("C28-1") + Connect("C27-1") + Connect("U6-3") + Connect("R12-2") + Connect("C81-1") + Connect("C79-2") + Connect("U3-38") + Connect("C78-2") + Connect("U3-35") + Connect("C77-2") + Connect("U3-30") + Connect("C76-2") + Connect("U3-19") + Connect("C75-2") + Connect("U3-12") + Connect("C74-2") + Connect("U3-3") + Connect("U5-3") + ) + Net("unnamed_net4" "(unknown)") + ( + Connect("C67-1") + Connect("R66-2") + Connect("R67-1") + Connect("U5-1") + ) + Net("unnamed_net3" "(unknown)") + ( + Connect("C66-1") + Connect("R65-2") + Connect("R68-1") + Connect("U5-8") + ) + Net("unnamed_net2" "(unknown)") + ( + Connect("C67-2") + Connect("R66-1") + Connect("U5-4") + Connect("R71-1") + ) + Net("unnamed_net1" "(unknown)") + ( + Connect("C66-2") + Connect("R65-1") + Connect("U5-5") + Connect("R10-1") + ) + Net("local_vref" "(unknown)") + ( + Connect("U6-2") + Connect("U5-2") + Connect("C124-1") + Connect("C24-1") + Connect("R7-1") + Connect("R6-2") + ) + Net("AUX_ADC_B1" "(unknown)") + ( + Connect("J2-61") + ) + Net("AUX_ADC_A1" "(unknown)") + ( + Connect("J2-59") + ) + Net("AUX_ADC_REF" "(unknown)") + ( + Connect("J2-57") + ) + Net("AUX_DAC_C" "(unknown)") + ( + Connect("J2-55") + ) + Net("AUX_DAC_B" "(unknown)") + ( + Connect("J2-53") + ) + Net("AUX_DAC_A" "(unknown)") + ( + Connect("R21-2") + Connect("J2-51") + ) + Net("AUX_DAC_D" "(unknown)") + ( + Connect("J2-49") + ) + Net("SEN_RX" "(unknown)") + ( + Connect("J2-35") + ) + Net("VINP_A" "(unknown)") + ( + Connect("C65-1") + Connect("R71-2") + Connect("J2-62") + ) + Net("VINN_A" "(unknown)") + ( + Connect("C64-1") + Connect("R10-2") + Connect("J2-60") + ) + Net("VREF" "(unknown)") + ( + Connect("J2-56") + ) + Net("VINN_B" "(unknown)") + ( + Connect("C25-1") + Connect("R15-2") + Connect("J2-52") + ) + Net("VINP_B" "(unknown)") + ( + Connect("C26-1") + Connect("R16-2") + Connect("J2-50") + ) + Net("AVDD" "(unknown)") + ( + Connect("C97-1") + Connect("L98-1") + Connect("C98-1") + Connect("R6-1") + Connect("J2-45") + Connect("J2-43") + Connect("J2-46") + Connect("J2-44") + ) + Net("AGND" "(unknown)") + ( + Connect("R93-2") + Connect("U4-1") + Connect("U4-2") + Connect("U4-5") + Connect("U4-4") + Connect("C184-1") + Connect("C183-1") + Connect("C182-2") + Connect("U2-4") + Connect("U2-2") + Connect("C100-1") + Connect("J100-2") + Connect("Q1-2") + Connect("J3-5") + Connect("J3-4") + Connect("J3-3") + Connect("J3-2") + Connect("C28-2") + Connect("C27-2") + Connect("C87-1") + Connect("U6-6") + Connect("C26-2") + Connect("C25-2") + Connect("C59-2") + Connect("C84-1") + Connect("C83-1") + Connect("C82-2") + Connect("C81-2") + Connect("C80-2") + Connect("C75-1") + Connect("C76-1") + Connect("C77-1") + Connect("C78-1") + Connect("C79-1") + Connect("C74-1") + Connect("R11-1") + Connect("R40-1") + Connect("C97-2") + Connect("C98-2") + Connect("C71-2") + Connect("C70-2") + Connect("U3-10") + Connect("U3-41") + Connect("U3-25") + Connect("U3-31") + Connect("U3-11") + Connect("U3-18") + Connect("U3-9") + Connect("U3-6") + Connect("U5-6") + Connect("C65-2") + Connect("C64-2") + Connect("C124-2") + Connect("R7-2") + Connect("C24-2") + Connect("J2-63") + Connect("J2-47") + Connect("J2-41") + Connect("J2-64") + Connect("J2-58") + Connect("J2-54") + Connect("J2-48") + Connect("J2-42") + ) + Net("io_rx_00" "(unknown)") + ( + Connect("R193-1") + Connect("J2-36") + ) + Net("io_rx_01" "(unknown)") + ( + Connect("J24-13") + Connect("J2-34") + ) + Net("io_rx_02" "(unknown)") + ( + Connect("J24-11") + Connect("J2-32") + ) + Net("io_rx_03" "(unknown)") + ( + Connect("R22-2") + Connect("J24-9") + Connect("J2-30") + ) + Net("io_rx_04" "(unknown)") + ( + Connect("J24-7") + Connect("J2-28") + ) + Net("SDI" "(unknown)") + ( + Connect("J2-33") + ) + Net("SDO" "(unknown)") + ( + Connect("J2-31") + ) + Net("SCLK" "(unknown)") + ( + Connect("J2-29") + ) + Net("RESET" "(unknown)") + ( + Connect("J2-27") + ) + Net("io_rx_05" "(unknown)") + ( + Connect("J24-5") + Connect("J2-26") + ) + Net("RS232_RXD" "(unknown)") + ( + Connect("J2-25") + ) + Net("io_rx_06" "(unknown)") + ( + Connect("J24-3") + Connect("J2-24") + ) + Net("RS232_TXD" "(unknown)") + ( + Connect("J2-23") + ) + Net("io_rx_07" "(unknown)") + ( + Connect("J24-1") + Connect("J2-22") + ) + Net("I2C_A0" "(unknown)") + ( + Connect("J2-21") + ) + Net("io_rx_08" "(unknown)") + ( + Connect("J25-15") + Connect("J2-20") + ) + Net("I2C_A1" "(unknown)") + ( + Connect("Q1-1") + Connect("U1-2") + Connect("J2-19") + ) + Net("io_rx_09" "(unknown)") + ( + Connect("J25-13") + Connect("J2-18") + ) + Net("SDA" "(unknown)") + ( + Connect("U3-27") + Connect("U1-5") + Connect("J2-17") + ) + Net("io_rx_10" "(unknown)") + ( + Connect("J25-11") + Connect("J2-16") + ) + Net("SCL" "(unknown)") + ( + Connect("U3-29") + Connect("U1-6") + Connect("J2-15") + ) + Net("io_rx_11" "(unknown)") + ( + Connect("J25-9") + Connect("J2-14") + ) + Net("io_rx_12" "(unknown)") + ( + Connect("J25-7") + Connect("J2-12") + ) + Net("clock_p" "(unknown)") + ( + Connect("R194-2") + Connect("J2-11") + ) + Net("io_rx_13" "(unknown)") + ( + Connect("J25-5") + Connect("J2-10") + ) + Net("io_rx_14" "(unknown)") + ( + Connect("J25-3") + Connect("J2-8") + ) + Net("DVDD" "(unknown)") + ( + Connect("U1-8") + Connect("U1-3") + Connect("U1-1") + Connect("J2-9") + Connect("J2-7") + ) + Net("io_rx_15" "(unknown)") + ( + Connect("J25-1") + Connect("J2-6") + ) + Net("6V" "(unknown)") + ( + Connect("L600-1") + Connect("C187-2") + Connect("J2-5") + Connect("J2-3") + ) + Net("DGND" "(unknown)") + ( + Connect("C261-2") + Connect("C187-1") + Connect("J25-6") + Connect("J25-4") + Connect("J25-14") + Connect("J25-12") + Connect("J25-10") + Connect("J25-16") + Connect("J25-8") + Connect("J25-2") + Connect("J24-6") + Connect("J24-4") + Connect("J24-14") + Connect("J24-12") + Connect("J24-10") + Connect("J24-16") + Connect("J24-8") + Connect("J24-2") + Connect("U1-4") + Connect("U1-7") + Connect("J2-37") + Connect("J2-38") + Connect("J2-2") + Connect("J2-1") + ) +) diff --git a/usrp-hw/dbsrx/dbsrx.prj b/usrp-hw/dbsrx/dbsrx.prj new file mode 100644 index 000000000..cbe51968e --- /dev/null +++ b/usrp-hw/dbsrx/dbsrx.prj @@ -0,0 +1,6 @@ +# List all schematics +schematics dbsrx.sch + +output-name dbsrx + +elements-dir ../pkg/newlib diff --git a/usrp-hw/dbsrx/dbsrx.sch b/usrp-hw/dbsrx/dbsrx.sch new file mode 100644 index 000000000..32ddb2ccd --- /dev/null +++ b/usrp-hw/dbsrx/dbsrx.sch @@ -0,0 +1,1688 @@ +v 20050820 1 +C 83700 45200 1 180 1 pmc64.sym +{ +T 84400 32000 5 10 1 1 0 2 1 +refdes=J2 +T 83700 45200 5 10 0 1 90 6 1 +footprint=PMC-REVERSE +} +N 85200 40100 86900 40100 4 +{ +T 85500 40100 5 10 1 1 0 0 1 +netname=RS232_RXD +} +N 85200 40500 86900 40500 4 +{ +T 85500 40500 5 10 1 1 0 0 1 +netname=RS232_TXD +} +C 83600 32300 1 90 0 generic-power.sym +{ +T 83350 32500 5 10 1 1 90 3 1 +net=AGND:1 +} +N 83600 32500 83800 32500 4 +N 85200 41300 86500 41300 4 +{ +T 85600 41300 5 10 1 1 0 0 1 +netname=I2C_A1 +} +N 85200 44900 85500 44900 4 +N 83800 44900 83500 44900 4 +C 85400 32700 1 270 0 generic-power.sym +{ +T 85650 32500 5 10 1 1 270 3 1 +net=AGND:1 +} +N 85400 32500 85200 32500 4 +N 85200 38100 86400 38100 4 +{ +T 85300 38100 5 10 1 1 0 0 1 +netname=SEN_RX +} +N 83800 37700 83600 37700 4 +N 85200 37700 85400 37700 4 +C 83600 36700 1 90 0 generic-power.sym +{ +T 83350 36900 5 10 1 1 90 3 1 +net=AGND:1 +} +N 83600 36900 83800 36900 4 +C 85400 37100 1 270 0 generic-power.sym +{ +T 85650 36900 5 10 1 1 270 3 1 +net=AGND:1 +} +N 85400 36900 85200 36900 4 +N 85200 33300 86800 33300 4 +{ +T 85200 33300 5 10 1 1 0 0 1 +netname=AUX_ADC_A1 +} +N 85200 32900 86800 32900 4 +{ +T 85200 32900 5 10 1 1 0 0 1 +netname=AUX_ADC_B1 +} +C 83600 33500 1 90 0 generic-power.sym +{ +T 83350 33700 5 10 1 1 90 3 1 +net=AGND:1 +} +N 83600 33700 83800 33700 4 +C 83600 34300 1 90 0 generic-power.sym +{ +T 83350 34500 5 10 1 1 90 3 1 +net=AGND:1 +} +N 83600 34500 83800 34500 4 +C 83600 35500 1 90 0 generic-power.sym +{ +T 83350 35700 5 10 1 1 90 3 1 +net=AGND:1 +} +N 83600 35700 83800 35700 4 +N 82200 32900 83800 32900 4 +{ +T 82200 32900 5 10 1 1 0 0 1 +netname=VINP_A +} +N 82200 33300 83800 33300 4 +{ +T 82200 33300 5 10 1 1 0 0 1 +netname=VINN_A +} +N 82200 35300 83800 35300 4 +{ +T 82200 35300 5 10 1 1 0 0 1 +netname=VINP_B +} +N 82200 34900 83800 34900 4 +{ +T 82200 34900 5 10 1 1 0 0 1 +netname=VINN_B +} +N 83800 34100 82200 34100 4 +{ +T 82300 34100 5 10 1 1 0 0 1 +netname=VREF +} +C 85400 35900 1 270 0 generic-power.sym +{ +T 85650 35700 5 10 1 1 270 3 1 +net=AGND:1 +} +N 85400 35700 85200 35700 4 +C 86000 36300 1 270 0 generic-power.sym +{ +T 86250 36100 5 10 1 1 270 3 1 +net=AVDD:1 +} +N 85200 36500 85700 36500 4 +N 85200 36100 86000 36100 4 +C 85700 36700 1 270 0 generic-power.sym +{ +T 85950 36500 5 10 1 1 270 3 1 +net=AVDD:1 +} +C 85900 44700 1 270 0 generic-power.sym +{ +T 86150 44500 5 10 1 1 270 3 1 +net=6V:1 +} +C 83000 36300 1 90 1 generic-power.sym +{ +T 82750 36100 5 10 1 1 90 3 1 +net=AVDD:1 +} +N 83800 36100 83000 36100 4 +N 83800 36500 83300 36500 4 +C 83300 36700 1 90 1 generic-power.sym +{ +T 83050 36500 5 10 1 1 90 3 1 +net=AVDD:1 +} +N 85200 44500 85900 44500 4 +N 85200 44100 85700 44100 4 +C 85700 43500 1 270 0 generic-power.sym +{ +T 85950 43300 5 10 1 1 270 3 1 +net=DVDD:1 +} +N 85200 43300 85700 43300 4 +N 85200 43700 85500 43700 4 +N 85700 44100 85700 44500 4 +N 85500 43700 85500 43300 4 +N 81800 44100 83800 44100 4 +{ +T 82100 44100 5 10 1 1 0 0 1 +netname=io_rx_15 +} +N 81800 43700 83800 43700 4 +{ +T 82100 43700 5 10 1 1 0 0 1 +netname=io_rx_14 +} +N 81800 42500 83800 42500 4 +{ +T 82100 42500 5 10 1 1 0 0 1 +netname=io_rx_11 +} +N 81800 43300 83800 43300 4 +{ +T 82100 43300 5 10 1 1 0 0 1 +netname=io_rx_13 +} +N 81800 42900 83800 42900 4 +{ +T 82100 42900 5 10 1 1 0 0 1 +netname=io_rx_12 +} +N 81800 41300 83800 41300 4 +{ +T 82100 41300 5 10 1 1 0 0 1 +netname=io_rx_08 +} +N 81800 42100 83800 42100 4 +{ +T 82100 42100 5 10 1 1 0 0 1 +netname=io_rx_10 +} +N 81800 41700 83800 41700 4 +{ +T 82100 41700 5 10 1 1 0 0 1 +netname=io_rx_09 +} +N 81800 40100 83800 40100 4 +{ +T 82100 40100 5 10 1 1 0 0 1 +netname=io_rx_05 +} +N 81800 40900 83800 40900 4 +{ +T 82100 40900 5 10 1 1 0 0 1 +netname=io_rx_07 +} +N 81800 40500 83800 40500 4 +{ +T 82100 40500 5 10 1 1 0 0 1 +netname=io_rx_06 +} +N 81800 38900 83800 38900 4 +{ +T 82100 38900 5 10 1 1 0 0 1 +netname=io_rx_02 +} +N 81800 39700 83800 39700 4 +{ +T 82100 39700 5 10 1 1 0 0 1 +netname=io_rx_04 +} +N 81800 39300 83800 39300 4 +{ +T 82100 39300 5 10 1 1 0 0 1 +netname=io_rx_03 +} +N 81800 38100 83800 38100 4 +{ +T 82100 38100 5 10 1 1 0 0 1 +netname=io_rx_00 +} +N 81800 38500 83800 38500 4 +{ +T 82100 38500 5 10 1 1 0 0 1 +netname=io_rx_01 +} +C 53600 29400 0 0 0 title-bordered-D.sym +T 82500 30300 5 10 1 1 0 0 1 +date=$Date: 2005/12/12 23:48:25 $ +T 84400 30000 5 10 1 1 0 0 1 +rev=$Revision: 1.10 $ +T 84500 29700 5 10 1 1 0 0 1 +auth=$Author: matt $ +T 80300 30000 5 10 1 1 0 0 1 +fname=$Source: /opt/usrp-hw-cvs/usrp-hw/dbsrx/dbsrx.sch,v $ +T 83700 30700 8 14 1 1 0 4 1 +title=DBS Tuner Daughterboard REV 2 +T 81300 29700 9 10 1 0 0 0 1 +1 +T 82100 29700 9 10 1 0 0 0 1 +1 +N 85200 42100 86300 42100 4 +{ +T 85500 42100 5 10 1 1 0 0 1 +netname=SCL +} +N 85200 41700 86300 41700 4 +{ +T 85500 41700 5 10 1 1 0 0 1 +netname=SDA +} +N 85200 39300 86600 39300 4 +{ +T 85600 39300 5 10 1 1 0 0 1 +netname=SCLK +} +N 85200 38900 86600 38900 4 +{ +T 85600 38900 5 10 1 1 0 0 1 +netname=SDO +} +N 85200 38500 86600 38500 4 +{ +T 85600 38500 5 10 1 1 0 0 1 +netname=SDI +} +N 85200 34900 86900 34900 4 +{ +T 85400 34900 5 10 1 1 0 0 1 +netname=AUX_DAC_A +} +N 85200 34500 86900 34500 4 +{ +T 85400 34500 5 10 1 1 0 0 1 +netname=AUX_DAC_B +} +N 85200 34100 86900 34100 4 +{ +T 85400 34100 5 10 1 1 0 0 1 +netname=AUX_DAC_C +} +N 85200 33700 86900 33700 4 +{ +T 85300 33700 5 10 1 1 0 0 1 +netname=AUX_ADC_REF +} +N 85200 35300 86900 35300 4 +{ +T 85400 35300 5 10 1 1 0 0 1 +netname=AUX_DAC_D +} +C 76600 30600 1 0 0 24Cxx-1.sym +{ +T 77100 31800 5 10 1 1 0 0 1 +refdes=U1 +T 76600 30600 5 10 0 1 0 0 1 +footprint=SO8 +T 76900 30400 5 10 1 1 0 0 1 +device=24LC024/SN +T 76900 30000 5 10 1 1 0 0 1 +net=DGND:4 +T 76900 30200 5 10 1 1 0 0 1 +net=DVDD:8 +} +N 77900 30900 79300 30900 4 +{ +T 78800 30900 5 10 1 1 0 0 1 +netname=SCL +} +N 77900 30700 79300 30700 4 +{ +T 78800 30700 5 10 1 1 0 0 1 +netname=SDA +} +N 77900 31100 78100 31100 4 +N 85200 40900 86500 40900 4 +{ +T 85600 40900 5 10 1 1 0 0 1 +netname=I2C_A0 +} +N 75600 31100 76600 31100 4 +{ +T 75700 31100 5 10 1 1 0 0 1 +netname=I2C_A1 +} +C 75600 30700 1 90 0 generic-power.sym +{ +T 75350 30900 5 10 1 1 90 3 1 +net=DVDD:1 +} +N 75600 30900 76600 30900 4 +N 74300 41400 73500 41400 4 +{ +T 74300 41400 5 10 1 1 0 6 1 +netname=VINP_A +} +N 74300 42400 73500 42400 4 +{ +T 74300 42400 5 10 1 1 0 6 1 +netname=VINN_A +} +C 66400 33500 1 90 1 generic-power.sym +{ +T 66150 33300 5 10 1 1 90 3 1 +net=AVDD:1 +} +C 69400 33500 1 270 0 generic-power.sym +{ +T 69650 33300 5 10 1 1 270 3 1 +net=AGND:1 +} +C 66700 33200 1 0 0 resistor-1.sym +{ +T 67300 33600 5 10 1 1 180 0 1 +refdes=R6 +T 67300 33100 5 10 1 1 180 0 1 +value=1K +T 66700 33200 5 10 0 1 0 0 1 +footprint=0603 +} +C 68000 32400 1 0 0 capacitor-1.sym +{ +T 68600 32700 5 10 1 1 0 0 1 +refdes=C24 +T 68600 32300 5 10 1 1 0 0 1 +value=.1uF +T 68000 32400 5 10 0 1 90 0 1 +footprint=0603 +} +C 68000 33200 1 0 0 resistor-1.sym +{ +T 68600 33600 5 10 1 1 180 0 1 +refdes=R7 +T 68600 33100 5 10 1 1 180 0 1 +value=1K +T 68000 33200 5 10 0 1 0 0 1 +footprint=0603 +} +N 66400 33300 66700 33300 4 +N 67600 33300 68000 33300 4 +N 68900 33300 69400 33300 4 +N 69100 32600 68900 32600 4 +N 67800 32600 68000 32600 4 +N 67800 33300 67800 34100 4 +C 72600 42300 1 0 0 resistor-1.sym +{ +T 73400 42700 5 10 1 1 180 0 1 +refdes=R10 +T 73300 42200 5 10 1 1 180 0 1 +value=50 +T 72600 42300 5 10 0 1 0 0 1 +footprint=0603 +} +C 72600 41300 1 0 0 resistor-1.sym +{ +T 73400 41700 5 10 1 1 180 0 1 +refdes=R71 +T 73300 41200 5 10 1 1 180 0 1 +value=50 +T 72600 41300 5 10 0 1 0 0 1 +footprint=0603 +} +C 74300 42200 1 0 0 capacitor-1.sym +{ +T 74900 42500 5 10 1 1 0 0 1 +refdes=C64 +T 74900 42100 5 10 1 1 0 0 1 +value=100pF +T 74300 42200 5 10 0 1 90 0 1 +footprint=0603 +} +C 74300 41200 1 0 0 capacitor-1.sym +{ +T 74900 41500 5 10 1 1 0 0 1 +refdes=C65 +T 74900 41100 5 10 1 1 0 0 1 +value=100pF +T 74300 41200 5 10 0 1 90 0 1 +footprint=0603 +} +N 75200 42400 75400 42400 4 +C 75500 41900 1 270 1 generic-power.sym +{ +T 75750 42100 5 10 1 1 270 3 1 +net=AGND:1 +} +N 72200 42400 72600 42400 4 +N 72200 41400 72600 41400 4 +T 81100 45500 9 20 1 0 0 0 1 +REVERSE PMC on BOTTOM!!!! +N 86600 39700 85200 39700 4 +{ +T 86200 39700 5 10 1 1 0 6 1 +netname=RESET +} +C 78800 36500 1 0 0 header16-1.sym +{ +T 79300 39800 5 10 1 1 0 0 1 +refdes=J24 +T 78800 36500 5 10 0 1 0 0 1 +footprint=CONNECTOR 8 2 +} +C 78800 32500 1 0 0 header16-1.sym +{ +T 79300 35800 5 10 1 1 0 0 1 +refdes=J25 +T 78800 32500 5 10 0 1 0 0 1 +footprint=CONNECTOR 8 2 +} +N 80200 38300 80500 38300 4 +N 80200 39500 80400 39500 4 +N 80400 39500 80400 38300 4 +N 80400 38300 80400 36700 4 +N 80400 36700 80200 36700 4 +N 80200 39100 80400 39100 4 +N 80200 38700 80400 38700 4 +N 80200 37900 80400 37900 4 +N 80200 37500 80400 37500 4 +N 80200 37100 80400 37100 4 +N 80200 34300 80500 34300 4 +N 80200 35500 80400 35500 4 +N 80400 35500 80400 34300 4 +N 80400 34300 80400 32700 4 +N 80400 32700 80200 32700 4 +N 80200 35100 80400 35100 4 +N 80200 34700 80400 34700 4 +N 80200 33900 80400 33900 4 +N 80200 33500 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1 +footprint=0603 +} +N 62600 41800 62900 41800 4 +N 62600 42200 63900 42200 4 +N 63900 42200 63900 41800 4 +N 63900 41800 63800 41800 4 +C 62900 40800 1 0 0 capacitor-1.sym +{ +T 63500 41100 5 10 1 1 0 0 1 +refdes=C69 +T 63500 40700 5 10 1 1 0 0 1 +value=.1uF +T 62900 40800 5 10 0 1 90 0 1 +footprint=0603 +} +N 62600 41000 62900 41000 4 +N 62600 41400 63900 41400 4 +N 63900 41400 63900 41000 4 +N 63900 41000 63800 41000 4 +C 63600 40400 1 0 0 capacitor-1.sym +{ +T 64200 40700 5 10 1 1 0 0 1 +refdes=C70 +T 64200 40300 5 10 1 1 0 0 1 +value=.22uF +T 63600 40400 5 10 0 1 90 0 1 +footprint=0603 +} +C 63000 40000 1 0 0 capacitor-1.sym +{ +T 63600 40300 5 10 1 1 0 0 1 +refdes=C71 +T 63600 39900 5 10 1 1 0 0 1 +value=.22uF +T 63000 40000 5 10 0 1 90 0 1 +footprint=0603 +} +N 62600 40200 63000 40200 4 +N 62600 40600 63600 40600 4 +C 65000 39600 1 180 0 generic-power.sym +{ +T 64800 39350 5 10 1 1 180 3 1 +net=AGND:1 +} +N 63900 40200 64800 40200 4 +N 64800 39600 64800 40600 4 +N 64800 40600 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5 10 1 1 0 0 1 +refdes=C74 +T 59200 42000 5 10 1 1 0 0 1 +value=1000pF +T 58600 42000 5 10 0 1 90 0 1 +footprint=0603 +} +C 58000 41600 1 0 0 capacitor-1.sym +{ +T 58600 41900 5 10 1 1 0 0 1 +refdes=C75 +T 58600 41600 5 10 1 1 0 0 1 +value=1000pF +T 58000 41600 5 10 0 1 90 0 1 +footprint=0603 +} +C 58600 40800 1 0 0 capacitor-1.sym +{ +T 59200 41100 5 10 1 1 0 0 1 +refdes=C76 +T 59200 40800 5 10 1 1 0 0 1 +value=1000pF +T 58600 40800 5 10 0 1 90 0 1 +footprint=0603 +} +C 58000 40400 1 0 0 capacitor-1.sym +{ +T 58600 40700 5 10 1 1 0 0 1 +refdes=C77 +T 58600 40400 5 10 1 1 0 0 1 +value=1000pF +T 58000 40400 5 10 0 1 90 0 1 +footprint=0603 +} +C 58900 40000 1 0 0 capacitor-1.sym +{ +T 59500 40300 5 10 1 1 0 0 1 +refdes=C78 +T 59500 40000 5 10 1 1 0 0 1 +value=1000pF +T 58900 40000 5 10 0 1 90 0 1 +footprint=0603 +} +C 58300 39600 1 0 0 capacitor-1.sym +{ +T 58900 39900 5 10 1 1 0 0 1 +refdes=C79 +T 58900 39600 5 10 1 1 0 0 1 +value=1000pF +T 58300 39600 5 10 0 1 90 0 1 +footprint=0603 +} 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1 180 5 1 +net=5V_RF:1 +} +C 56000 40100 1 0 1 capacitor-1.sym +{ +T 55400 40400 5 10 1 1 0 6 1 +refdes=C80 +T 55400 40100 5 10 1 1 0 6 1 +value=1000pF +T 56000 40100 5 10 0 1 90 2 1 +footprint=0603 +} +C 56000 41500 1 0 1 capacitor-1.sym +{ +T 55400 41800 5 10 1 1 0 6 1 +refdes=C81 +T 55400 41500 5 10 1 1 0 6 1 +value=1000pF +T 56000 41500 5 10 0 1 90 2 1 +footprint=0603 +} +C 56200 40500 1 270 1 resistor-1.sym +{ +T 56100 41000 5 10 1 1 0 6 1 +refdes=R12 +T 56100 40700 5 10 1 1 0 6 1 +value=4.7 +T 56200 40500 5 10 0 1 90 2 1 +footprint=0603 +} +C 56000 39600 1 0 1 capacitor-2.sym +{ +T 55400 39600 5 10 1 1 0 6 1 +refdes=C82 +T 56200 39600 5 10 1 1 0 6 1 +value=100uF +T 56000 39600 5 10 0 1 90 2 1 +footprint=EIA6032 +} +N 56300 41900 56300 41400 4 +N 56000 41700 56300 41700 4 +N 55100 41700 54500 41700 4 +N 54500 39800 55100 39800 4 +N 55100 40300 54500 40300 4 +N 56300 40500 56300 39800 4 +N 56000 40300 56300 40300 4 +C 54700 39500 1 180 0 generic-power.sym +{ +T 54500 39250 5 10 1 1 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10 1 1 0 0 1 +value=100pF +T 74300 47400 5 10 0 1 90 0 1 +footprint=0603 +} +N 75200 48600 75400 48600 4 +C 75500 48000 1 270 1 generic-power.sym +{ +T 75750 48200 5 10 1 1 270 3 1 +net=AGND:1 +} +N 72200 48600 72600 48600 4 +N 72200 47600 72600 47600 4 +C 70100 46700 1 0 0 ad813x.sym +{ +T 71400 49200 5 10 1 1 0 0 1 +refdes=U6 +} +C 70700 49500 1 0 0 generic-power.sym +{ +T 70900 49750 5 10 1 1 180 5 1 +net=5V_RF:1 +} +C 71100 46700 1 180 0 generic-power.sym +{ +T 70900 46450 5 10 1 1 180 3 1 +net=AGND:1 +} +N 70900 46700 70900 46800 4 +N 70900 49500 70900 49400 4 +C 71600 50400 1 180 0 resistor-1.sym +{ +T 71100 50000 5 10 1 1 0 0 1 +value=250, 0.1% +T 71600 50400 5 10 0 1 180 0 1 +footprint=0603 +T 71100 50500 5 10 1 1 0 0 1 +refdes=R17 +} +C 71600 46200 1 180 0 resistor-1.sym +{ +T 71100 45800 5 10 1 1 0 0 1 +value=250, 0.1% +T 71600 46200 5 10 0 1 180 0 1 +footprint=0603 +T 71100 46300 5 10 1 1 0 0 1 +refdes=R18 +} +C 69900 47700 1 180 0 resistor-1.sym +{ +T 69500 47300 5 10 1 1 0 0 1 +value=250, 0.1% +T 69900 47700 5 10 0 1 180 0 1 +footprint=0603 +T 69200 47300 5 10 1 1 0 0 1 +refdes=R19 +} +C 69900 48700 1 180 0 resistor-1.sym +{ +T 69600 48800 5 10 1 1 0 0 1 +value=250, 0.1% +T 69900 48700 5 10 0 1 180 0 1 +footprint=0603 +T 69200 48800 5 10 1 1 0 0 1 +refdes=R20 +} +N 68900 48100 70200 48100 4 +{ +T 69300 48100 5 10 1 1 0 0 1 +netname=local_vref +} +N 69900 47600 70200 47600 4 +N 70100 46100 70700 46100 4 +N 71600 46100 72400 46100 4 +N 69900 48600 70200 48600 4 +N 70100 50300 70700 50300 4 +N 71600 50300 72400 50300 4 +C 70700 51100 1 180 1 capacitor-1.sym +{ +T 70600 51000 5 10 1 1 0 0 1 +refdes=C85 +T 71300 51000 5 10 1 1 0 0 1 +value=22pF +T 67300 42700 5 10 0 1 270 2 1 +footprint=0603 +} +C 70700 45700 1 180 1 capacitor-1.sym +{ +T 70600 45600 5 10 1 1 0 0 1 +refdes=C86 +T 71300 45600 5 10 1 1 0 0 1 +value=22pF +T 70700 45700 5 10 0 1 270 2 1 +footprint=0603 +} +N 70100 45500 70100 47600 4 +N 70100 45500 70700 45500 4 +N 71600 45500 72400 45500 4 +N 72400 45500 72400 47600 4 +N 70100 48600 70100 50900 4 +N 70100 50900 70700 50900 4 +N 71600 50900 72400 50900 4 +N 72400 48600 72400 50900 4 +N 75400 48600 75400 47600 4 +N 75400 47600 75200 47600 4 +N 75400 48200 75500 48200 4 +N 67200 45300 67600 45300 4 +N 68100 47600 69000 47600 4 +N 67200 45700 68100 45700 4 +N 67200 46500 67600 46500 4 +N 68100 42400 69000 42400 4 +N 67200 46100 68100 46100 4 +N 72600 33400 72600 33700 4 +N 72600 33700 74100 33700 4 +N 72600 32300 72600 32600 4 +N 62700 45400 64100 45400 4 +{ +T 62800 45400 5 10 1 1 0 0 1 +netname=AUX_DAC_A +} +N 63000 45100 64100 45100 4 +{ +T 63200 45100 5 10 1 1 0 0 1 +netname=io_rx_03 +} +C 65000 45500 1 180 0 resistor-1.sym +{ +T 64600 45600 5 10 1 1 0 0 1 +value=1K +T 65000 45500 5 10 0 1 180 0 1 +footprint=0603 +T 64200 45600 5 10 1 1 0 0 1 +refdes=R21 +} +C 65000 45000 1 0 1 resistor-1.sym +{ +T 64600 44900 5 10 1 1 180 6 1 +value=NONE +T 65000 45000 5 10 0 1 0 6 1 +footprint=0603 +T 64200 44900 5 10 1 1 180 6 1 +refdes=R22 +} +C 64900 44000 1 270 1 capacitor-1.sym +{ +T 65200 44200 5 10 1 1 0 0 1 +refdes=C87 +T 65200 44600 5 10 1 1 0 0 1 +value=.01uF +T 64900 44000 5 10 0 1 0 2 1 +footprint=0603 +} +N 65200 45700 65100 45700 4 +N 65100 45700 65100 44900 4 +N 65000 45400 65100 45400 4 +N 65000 45100 65100 45100 4 +C 64900 43800 1 180 1 generic-power.sym +{ +T 65100 43550 5 10 1 1 180 3 1 +net=AGND:1 +} +N 65100 43800 65100 44000 4 +N 67600 46500 67600 48600 4 +N 67600 48600 69000 48600 4 +N 68100 46100 68100 47600 4 +N 68100 45700 68100 42400 4 +N 67600 45300 67600 41400 4 +N 67600 41400 69000 41400 4 +C 76500 46600 1 90 1 capacitor-1.sym +{ +T 76600 46200 5 10 1 1 0 0 1 +refdes=C27 +T 76600 46000 5 10 1 1 0 0 1 +value=.1uF +T 76500 46600 5 10 0 1 180 2 1 +footprint=0603 +} +C 77400 46600 1 90 1 capacitor-1.sym +{ +T 77500 46200 5 10 1 1 0 0 1 +refdes=C28 +T 77500 46000 5 10 1 1 0 0 1 +value=1000pF +T 77400 46600 5 10 0 1 180 2 1 +footprint=0603 +} +N 76300 46600 76300 46800 4 +N 76300 46800 77200 46800 4 +N 77200 46800 77200 46600 4 +N 76300 45700 76300 45500 4 +N 76300 45500 77200 45500 4 +N 77200 45500 77200 45700 4 +C 76500 46900 1 0 0 generic-power.sym +{ +T 76700 47150 5 10 1 1 180 5 1 +net=5V_RF:1 +} +N 76700 46900 76700 46800 4 +C 76900 45400 1 180 0 generic-power.sym +{ +T 76700 45150 5 10 1 1 180 3 1 +net=AGND:1 +} +N 76700 45400 76700 45500 4 +C 54400 46000 1 0 0 SMA-5.sym +{ +T 54400 46800 5 10 1 1 0 0 1 +refdes=J3 +T 54400 46000 5 10 0 1 0 0 1 +footprint=SMA_VERT +} +C 72100 32600 1 0 0 nmos-sot23.sym +{ +T 72800 33200 5 10 1 1 0 0 1 +refdes=Q1 +} +C 72800 32300 1 180 0 generic-power.sym +{ +T 72600 32050 5 10 1 1 180 3 1 +net=AGND:1 +} +C 78100 31300 1 270 0 generic-power.sym +{ +T 78350 31100 5 10 1 1 270 3 1 +net=DGND:1 +} +C 80500 34500 1 270 0 generic-power.sym +{ +T 80750 34300 5 10 1 1 270 3 1 +net=DGND:1 +} +C 80500 38500 1 270 0 generic-power.sym +{ +T 80750 38300 5 10 1 1 270 3 1 +net=DGND:1 +} +C 85500 45100 1 270 0 generic-power.sym +{ +T 85750 44900 5 10 1 1 270 3 1 +net=DGND:1 +} +C 83500 44700 1 90 0 generic-power.sym +{ +T 83250 44900 5 10 1 1 90 3 1 +net=DGND:1 +} +C 83600 37500 1 90 0 generic-power.sym +{ +T 83350 37700 5 10 1 1 90 3 1 +net=DGND:1 +} +C 85400 37900 1 270 0 generic-power.sym +{ +T 85650 37700 5 10 1 1 270 3 1 +net=DGND:1 +} +C 54000 43900 1 0 0 connector2-1.sym +{ +T 54000 44700 5 10 1 1 0 0 1 +refdes=J100 +T 54000 43900 5 10 0 1 0 0 1 +footprint=CONNECTOR 1 2 +} +C 55900 44800 1 90 0 inductor-1.sym +{ +T 55700 45300 5 10 1 1 180 0 1 +refdes=L100 +T 55900 44800 5 10 0 1 90 0 1 +footprint=0603 +T 55200 45000 5 10 1 1 0 0 1 +value=27nH +} +C 55600 43900 1 180 1 generic-power.sym +{ +T 55800 43650 5 10 1 1 180 3 1 +net=AGND:1 +} +N 55700 44400 55800 44400 4 +N 55800 44400 55800 44800 4 +N 55800 44100 55800 43900 4 +N 55800 45700 55800 46500 4 +C 56600 44300 1 270 1 capacitor-1.sym +{ +T 56900 44900 5 10 1 1 0 0 1 +refdes=C100 +T 57400 44500 5 10 1 1 0 6 1 +value=.1uF +T 56600 44300 5 10 0 1 0 2 1 +footprint=0603 +} +N 55700 44100 56800 44100 4 +N 56800 44100 56800 44300 4 +N 55800 44700 56200 44700 4 +N 56200 44700 56200 45400 4 +N 56800 45400 56800 45200 4 +C 82100 49600 1 270 0 lm2940imp.sym +{ +T 83600 49300 5 10 1 1 0 6 1 +refdes=U2 +} +C 83000 46900 1 180 0 generic-power.sym +{ +T 82800 46650 5 10 1 1 180 3 1 +net=AGND:1 +} +N 82600 47500 82600 47300 4 +N 83000 47300 83000 47500 4 +N 82800 46900 82800 47300 4 +C 79500 49900 1 0 0 generic-power.sym +{ +T 79700 50150 5 10 1 1 0 3 1 +net=6V:1 +} +N 79700 49200 79700 49900 4 +C 83900 49900 1 0 0 generic-power.sym +{ +T 84100 50150 5 10 1 1 180 5 1 +net=5V_RF:1 +} +N 84100 48900 84100 49900 4 +C 84300 48900 1 90 1 capacitor-2.sym +{ +T 84600 48100 5 10 1 1 0 6 1 +refdes=C182 +T 84700 48600 5 10 1 1 0 6 1 +value=22uF +T 84300 48900 5 10 0 1 180 2 1 +footprint=EIA6032 +} +N 84100 47300 84100 48000 4 +N 83000 49500 83000 49700 4 +N 83000 49700 84100 49700 4 +N 82600 49700 82600 49500 4 +C 79500 48300 1 270 1 capacitor-1.sym +{ +T 79300 48900 5 10 1 1 0 0 1 +refdes=C187 +T 79300 48500 5 10 1 1 0 0 1 +value=.1uF +T 79500 48300 5 10 0 1 0 2 1 +footprint=0603 +} +N 79700 48300 79700 47300 4 +C 57700 45800 1 0 0 mga82563.sym +{ +T 58300 47100 5 10 1 1 0 0 1 +refdes=U4 +T 58500 46500 5 10 0 1 0 0 1 +footprint=SC70_6 +} +C 59800 47700 1 270 0 inductor-1.sym +{ +T 60100 47200 5 10 1 1 0 0 1 +refdes=L98 +T 59800 47700 5 10 0 1 270 0 1 +footprint=0603 +T 60100 47000 5 10 1 1 0 0 1 +value=27nH +} +C 58700 45200 1 180 0 generic-power.sym +{ +T 58500 44950 5 10 1 1 180 3 1 +net=AGND:1 +} +N 58100 45800 58100 45500 4 +N 58100 45500 58900 45500 4 +N 58900 45500 58900 45800 4 +N 58600 45500 58600 45800 4 +N 58300 45500 58300 45800 4 +N 58500 45200 58500 45500 4 +C 68000 31800 1 0 0 capacitor-1.sym +{ +T 68600 32100 5 10 1 1 0 0 1 +refdes=C124 +T 68600 31700 5 10 1 1 0 0 1 +value=1000pF +T 68000 31800 5 10 0 1 90 0 1 +footprint=0603 +} +N 67800 32000 67800 33300 4 +N 67800 32000 68000 32000 4 +N 69100 32000 69100 33300 4 +N 69100 32000 68900 32000 4 +C 79800 49600 1 0 0 inductor-1.sym +{ +T 80000 49900 5 10 1 1 0 0 1 +refdes=L600 +T 79800 49600 5 10 0 1 0 0 1 +footprint=1206 +} +C 79900 47300 1 180 0 generic-power.sym +{ +T 79700 47050 5 10 1 1 180 3 1 +net=DGND:1 +} +C 80900 49600 1 0 0 inductor-1.sym +{ +T 81100 49900 5 10 1 1 0 0 1 +refdes=L601 +T 80900 49600 5 10 0 1 0 0 1 +footprint=1206 +} +N 82600 49700 81800 49700 4 +N 80900 49700 80700 49700 4 +N 79800 49700 79700 49700 4 +C 80600 48300 1 270 1 capacitor-1.sym +{ +T 80300 48900 5 10 1 1 0 0 1 +refdes=C183 +T 80400 48500 5 10 1 1 0 0 1 +value=.1uF +T 80600 48300 5 10 0 1 0 2 1 +footprint=0603 +} +N 80800 49700 80800 49200 4 +N 80800 47300 80800 48300 4 +N 80800 47300 84100 47300 4 +N 81900 47300 81900 48300 4 +C 81700 48300 1 270 1 capacitor-1.sym +{ +T 81400 48900 5 10 1 1 0 0 1 +refdes=C184 +T 81500 48500 5 10 1 1 0 0 1 +value=.1uF +T 81700 48300 5 10 0 1 0 2 1 +footprint=0603 +} +N 81900 49700 81900 49200 4 +C 75600 31100 1 90 0 generic-power.sym +{ +T 75350 31300 5 10 1 1 90 3 1 +net=DVDD:1 +} +N 75600 31300 76600 31300 4 +C 60100 48100 1 0 1 generic-power.sym +{ +T 59900 48350 5 10 1 1 0 3 1 +net=AVDD:1 +} +N 59900 37000 60600 37000 4 +C 57100 32500 1 270 0 resistor-1.sym +{ +T 57000 32000 5 10 1 1 0 6 1 +refdes=R93 +T 57000 31800 5 10 1 1 0 6 1 +value=50 +T 57100 32500 5 10 0 1 270 0 1 +footprint=0603 +} +C 55700 33300 1 270 0 capacitor-1.sym +{ +T 55900 33100 5 10 1 1 180 0 1 +refdes=C261 +T 55900 32600 5 10 1 1 0 6 1 +value=200pF +T 55700 33300 5 10 0 1 0 0 1 +footprint=0603 +} +C 54800 33700 1 0 0 resistor-1.sym +{ +T 55300 33600 5 10 1 1 90 6 1 +refdes=R193 +T 55500 33600 5 10 1 1 90 6 1 +value=10 +T 54800 33700 5 10 0 1 0 0 1 +footprint=0603 +} +N 55900 33300 55900 33800 4 +C 56100 32100 1 180 0 generic-power.sym +{ +T 55900 31850 5 10 1 1 180 3 1 +net=DGND:1 +} +N 55900 32100 55900 32400 4 +N 57000 33800 57600 33800 4 +N 55700 33800 56100 33800 4 +N 85200 42900 86300 42900 4 +{ +T 85500 42900 5 10 1 1 0 0 1 +netname=clock_p +} +N 53800 34000 54800 34000 4 +{ +T 54000 34000 5 10 1 1 0 0 1 +netname=clock_p +} +C 55700 34100 1 180 0 resistor-1.sym +{ +T 55600 34400 5 10 1 1 0 6 1 +refdes=R194 +T 55600 34200 5 10 1 1 0 6 1 +value=NONE +T 55700 34100 5 10 0 1 180 0 1 +footprint=0603 +} +N 55700 34000 55800 34000 4 +N 55800 34000 55800 33800 4 +C 59500 43800 1 0 1 connector2-1.sym +{ +T 59500 44600 5 10 1 1 0 6 1 +refdes=J101 +T 59500 43800 5 10 0 1 0 6 1 +footprint=CONNECTOR 1 2 +} +N 57600 44300 57600 45400 4 +N 56200 45400 57600 45400 4 +C 57600 44200 1 90 1 generic-power.sym +{ +T 57350 44000 5 10 1 1 270 5 1 +net=5V_RF:1 +} +N 57800 44300 57600 44300 4 +N 57800 44000 57600 44000 4 diff --git a/usrp-hw/dbsrx/gnetlistrc b/usrp-hw/dbsrx/gnetlistrc new file mode 100644 index 000000000..6bbd9c292 --- /dev/null +++ b/usrp-hw/dbsrx/gnetlistrc @@ -0,0 +1,3 @@ +(component-library "../sym") +(component-library "../sym/generated") + diff --git a/usrp-hw/dbsrx/gschemrc b/usrp-hw/dbsrx/gschemrc new file mode 100644 index 000000000..6bbd9c292 --- /dev/null +++ b/usrp-hw/dbsrx/gschemrc @@ -0,0 +1,3 @@ +(component-library "../sym") +(component-library "../sym/generated") + diff --git a/usrp-hw/dbsrx/netlist_cmd b/usrp-hw/dbsrx/netlist_cmd new file mode 100755 index 000000000..64f5d8af7 --- /dev/null +++ b/usrp-hw/dbsrx/netlist_cmd @@ -0,0 +1,3 @@ +gsch2pcb dbsrx.prj +gnetlist -g partslist3 -o dbsrx.bom dbsrx.sch + diff --git a/usrp-hw/rfx/common.sch b/usrp-hw/rfx/common.sch new file mode 100644 index 000000000..846421e94 --- /dev/null +++ b/usrp-hw/rfx/common.sch @@ -0,0 +1,683 @@ +v 20050820 1 +C 39500 25900 0 0 0 title-C.sym +C 53900 40600 1 0 1 BNC-1.sym +{ +T 53900 41400 5 10 1 1 0 6 1 +refdes=J200 +T 53900 40600 5 10 0 1 0 0 1 +footprint=SMA_VERT +} +C 54000 40300 1 180 0 generic-power.sym +{ +T 53800 40050 5 10 1 1 180 3 1 +net=AGND:1 +} +N 53800 40600 53800 40300 4 +C 44000 40500 1 180 0 capacitor-1.sym +{ +T 43700 40400 5 10 1 1 0 0 1 +refdes=C201 +T 44400 40100 5 10 1 1 0 6 1 +value=220pF +T 44000 40500 5 10 0 1 270 0 1 +footprint=0603 +} +C 42500 40900 1 180 1 capacitor-1.sym +{ +T 42900 40800 5 10 1 1 180 2 1 +refdes=C202 +T 42900 40500 5 10 1 1 180 2 1 +value=220pF +T 42500 40900 5 10 0 1 270 2 1 +footprint=0603 +} +C 43800 38400 1 180 1 generic-power.sym +{ +T 44000 38150 5 10 1 1 180 3 1 +net=AGND:1 +} +N 44000 40300 44500 40300 4 +N 44500 40700 43400 40700 4 +N 43100 40300 42000 40300 4 +{ +T 42100 40300 5 10 1 1 0 0 1 +netname=RF_TX +} +N 41200 30600 44800 30600 4 +{ +T 41500 30600 5 10 1 1 0 0 1 +netname=io_tx_06 +} +T 40300 26300 9 15 1 0 0 0 6 +Band +400 - 500 MHz +800 - 975 MHz +1.2 - 1.3 GHz +2.3 - 2.4 GHz +2.4 - 2.7 GHz +T 47100 26300 9 15 1 0 0 0 6 +Upconverter VCO +ADF4360-7 (Div by 2) +ADF4360-3 (Div by 2) +ADF4360-0 (Div by 2) +ADF4360-1 +ADF4360-0 +T 42900 26300 9 15 1 0 0 0 6 +Upconverter +AD8345 +AD8349 +AD8349 +AD8349 +AD8349 +T 44900 26300 9 15 1 0 0 0 6 +Downconverter +AD8348 +AD8347 +AD8347 +AD8347 +AD8347 +T 50300 26300 9 15 1 0 0 0 6 +Downconverter VCO +ADF4360-3 (Div by 2) +Same +Same +Same +Same +T 56600 26600 5 10 1 1 0 0 1 +date=$Date: 2006/01/09 23:16:07 $ +T 58500 26300 5 10 1 1 0 0 1 +rev=$Revision: 1.14 $ +T 58600 26000 5 10 1 1 0 0 1 +auth=$Author: matt $ +T 54400 26300 5 10 1 1 0 0 1 +fname=$Source: /opt/usrp-hw-cvs/usrp-hw/flex_xcvr/common.sch,v $ +T 57800 27000 8 14 1 1 0 4 1 +title=FlexRF Common +T 55400 26000 9 10 1 0 0 0 1 +1 +T 56200 26000 9 10 1 0 0 0 1 +3 +C 44400 38200 1 0 0 hmc174ms8.sym +{ +T 45700 41800 5 10 1 1 0 6 1 +refdes=U202 +} +C 46900 40900 1 0 0 capacitor-1.sym +{ +T 47300 41000 5 10 1 1 180 0 1 +refdes=C204 +T 48200 41000 5 10 1 1 180 0 1 +value=220pF +T 46900 40900 5 10 0 1 270 8 1 +footprint=0603 +} +N 46500 41100 46900 41100 4 +N 44100 41500 44100 41100 4 +N 44100 41100 44500 41100 4 +N 44000 38400 44000 39100 4 +N 44000 39100 44500 39100 4 +N 44500 38700 44000 38700 4 +T 46400 38600 9 10 1 0 0 0 2 +B high selects RF1 +A high selects RF2 +C 40800 35100 1 0 0 BNC-1.sym +{ +T 40800 35900 5 10 1 1 0 0 1 +refdes=J202 +T 40800 35100 5 10 0 1 0 6 1 +footprint=SMA_VERT +} +C 40700 34800 1 180 1 generic-power.sym +{ +T 40900 34550 5 10 1 1 180 3 1 +net=AGND:1 +} +N 40900 35100 40900 34800 4 +C 43400 35800 1 180 1 capacitor-1.sym +{ +T 43800 35700 5 10 1 1 180 2 1 +refdes=C206 +T 43800 35400 5 10 1 1 180 2 1 +value=220pF +T 43400 35800 5 10 0 1 270 2 1 +footprint=0603 +} +C 43800 33700 1 180 1 generic-power.sym +{ +T 44000 33450 5 10 1 1 180 3 1 +net=AGND:1 +} +N 44500 36000 41800 36000 4 +C 44400 33500 1 0 0 hmc174ms8.sym +{ +T 45700 37100 5 10 1 1 0 6 1 +refdes=U209 +} +C 46900 36200 1 0 0 capacitor-1.sym +{ +T 47300 36300 5 10 1 1 180 0 1 +refdes=C205 +T 48200 36300 5 10 1 1 180 0 1 +value=220pF +T 46900 36200 5 10 0 1 270 8 1 +footprint=0603 +} +N 46500 36400 46900 36400 4 +N 44100 36800 44100 36400 4 +N 44100 36400 44500 36400 4 +N 44000 33700 44000 34400 4 +N 44000 34400 44500 34400 4 +N 44500 34000 44000 34000 4 +T 46400 33900 9 10 1 0 0 0 2 +B high selects RF1 +A high selects RF2 +T 52700 41700 9 30 1 0 0 0 1 +TX/RX +T 40400 35400 9 30 1 0 0 6 1 +RX +N 49200 36400 47800 36400 4 +{ +T 49000 36400 5 10 1 1 0 6 1 +netname=RF_RX +} +N 41300 35600 43400 35600 4 +N 42500 40700 41800 40700 4 +N 41800 36000 41800 40700 4 +N 44300 35600 44500 35600 4 +T 54600 35800 9 10 1 0 0 0 22 +A1 B1 A2 B2 +0 0 0 0 All Off + +0 1 0 0 TX Only +0 1 1 0 TX Only + +0 1 0 1 Full Duplex TX and RX + +0 0 0 1 RX from secondary RX port +1 0 0 1 RX from secondary RX port +1 0 1 0 RX from primary TX/RX port + +0 0 1 0 Nothing +1 0 0 0 Nothing + +0 0 1 1 BAD! +0 1 1 1 BAD! +1 0 1 1 BAD! +1 1 0 0 BAD! +1 1 0 1 BAD! +1 1 1 0 BAD! +1 1 1 1 BAD! +C 41100 31600 1 270 0 resistor-1.sym +{ +T 41400 31100 5 10 1 1 0 0 1 +value=10K +T 41100 31600 5 10 0 1 270 0 1 +footprint=0603 +T 41400 30900 5 10 1 1 0 0 1 +refdes=R250 +} +C 52700 33000 1 90 1 capacitor-1.sym +{ +T 52900 32900 5 10 1 1 0 6 1 +refdes=C200 +T 52600 32700 5 10 1 1 0 0 1 +value=220pF +T 52700 33000 5 10 0 1 0 6 1 +footprint=0603 +} +N 52500 31800 52500 32100 4 +C 55200 33000 1 270 0 capacitor-2.sym +{ +T 54900 32200 5 10 1 1 0 0 1 +refdes=C208 +T 54900 32000 5 10 1 1 0 0 1 +value=4.7uF +T 55200 33000 5 10 0 1 0 0 1 +footprint=1206 +} +C 55800 31500 1 0 0 adp3336.sym +{ +T 57700 33700 5 10 1 1 0 6 1 +refdes=U203 +} +N 57900 32400 58100 32400 4 +N 58100 32400 58100 33200 4 +N 58100 32800 57900 32800 4 +C 58100 33700 1 0 0 generic-power.sym +{ +T 58300 33950 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +N 57900 33200 58300 33200 4 +C 53000 33000 1 270 0 capacitor-1.sym +{ +T 52700 32200 5 10 1 1 0 0 1 +refdes=C203 +T 52700 32000 5 10 1 1 0 0 1 +value=0.1uF +T 53000 33000 5 10 0 1 0 0 1 +footprint=0603 +} +C 53900 33000 1 90 1 capacitor-1.sym +{ +T 54100 32200 5 10 1 1 0 6 1 +refdes=C207 +T 54100 32000 5 10 1 1 0 6 1 +value=1uF +T 53900 33000 5 10 0 1 0 6 1 +footprint=0603 +} +N 53700 31800 53700 32100 4 +N 53700 33000 53700 33300 4 +N 53200 31800 53200 32100 4 +N 53200 33000 53200 33300 4 +C 53800 33200 1 0 0 inductor-1.sym +{ +T 54000 33500 5 10 1 1 0 0 1 +refdes=L202 +T 53800 33200 5 10 0 1 0 0 1 +footprint=1206 +} +C 54600 33000 1 270 0 capacitor-1.sym +{ +T 54300 32200 5 10 1 1 0 0 1 +refdes=C209 +T 54300 32000 5 10 1 1 0 0 1 +value=0.1uF +T 54600 33000 5 10 0 1 0 0 1 +footprint=0603 +} +N 55400 31800 55400 32100 4 +N 55400 33000 55400 33300 4 +N 54800 31800 54800 32100 4 +N 54800 33000 54800 33300 4 +N 53200 31400 53200 31800 4 +N 54700 33300 55700 33300 4 +N 55700 32800 55900 32800 4 +N 55700 33200 55900 33200 4 +N 55700 32400 55900 32400 4 +N 55700 32400 55700 33300 4 +N 52500 31800 55700 31800 4 +N 55700 31800 55700 32000 4 +N 55700 32000 55900 32000 4 +C 58200 33000 1 270 0 resistor-1.sym +{ +T 58500 32600 5 10 1 1 180 8 1 +refdes=R201 +T 58200 33000 5 10 0 1 90 8 1 +footprint=0603 +T 58500 32400 5 10 1 1 0 0 1 +value=140K +} +C 58200 31900 1 270 0 resistor-1.sym +{ +T 58500 31500 5 10 1 1 180 8 1 +refdes=R202 +T 58200 31900 5 10 0 1 90 8 1 +footprint=0603 +T 58500 31300 5 10 1 1 0 0 1 +value=78.7K +} +N 58300 30900 58300 31000 4 +N 57900 32000 58300 32000 4 +N 58300 31900 58300 32100 4 +N 58300 33000 58300 33700 4 +C 59200 33100 1 90 1 capacitor-1.sym +{ +T 59100 32800 5 10 1 1 0 0 1 +refdes=C210 +T 59100 32400 5 10 1 1 0 0 1 +value=470pF +T 59200 33100 5 10 0 1 0 6 1 +footprint=0603 +} +N 58300 32000 59000 32000 4 +N 59000 32000 59000 32200 4 +N 59000 33200 59000 33100 4 +N 52500 33300 53800 33300 4 +C 53400 31400 1 180 0 generic-power.sym +{ +T 53200 31150 5 10 1 1 180 3 1 +net=AGND:1 +} +C 58500 30900 1 180 0 generic-power.sym +{ +T 58300 30650 5 10 1 1 180 3 1 +net=AGND:1 +} +C 52700 33600 1 0 1 generic-power.sym +{ +T 52500 33850 5 10 1 1 180 5 1 +net=6V_RX:1 +} +N 52500 33000 52500 33600 4 +C 43900 41500 1 0 0 generic-power.sym +{ +T 44100 41750 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +C 43900 36800 1 0 0 generic-power.sym +{ +T 44100 37050 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +C 44800 29500 1 0 0 7404-3.sym +{ +T 46300 31500 5 10 1 1 0 0 1 +refdes=U204 +T 45200 29300 5 10 1 1 0 0 1 +net=3_3V_SW:14 +T 45200 29100 5 10 1 1 0 0 1 +net=AGND:7 +T 44800 29500 5 10 0 1 0 0 1 +footprint=SO14 +} +N 46800 30600 48200 30600 4 +{ +T 47300 30600 5 10 1 1 0 0 1 +netname=TX +} +N 46800 30300 48200 30300 4 +{ +T 47300 30300 5 10 1 1 0 0 1 +netname=RX +} +N 46800 30000 48200 30000 4 +{ +T 47300 30000 5 10 1 1 0 0 1 +netname=RX1 +} +N 46800 29700 48200 29700 4 +{ +T 47300 29700 5 10 1 1 0 0 1 +netname=RX2 +} +N 43100 39500 44500 39500 4 +{ +T 43600 39500 5 10 1 1 0 0 1 +netname=TX +} +N 43100 39900 44500 39900 4 +{ +T 43600 39900 5 10 1 1 0 0 1 +netname=RX +} +N 43100 35200 44500 35200 4 +{ +T 43600 35200 5 10 1 1 0 0 1 +netname=RX1 +} +N 43100 34800 44500 34800 4 +{ +T 43600 34800 5 10 1 1 0 0 1 +netname=RX2 +} +N 41200 29700 44800 29700 4 +{ +T 41700 29700 5 10 1 1 0 0 1 +netname=RX1 +} +N 41200 30300 44800 30300 4 +{ +T 41700 30300 5 10 1 1 0 0 1 +netname=TX +} +N 41200 30600 41200 30700 4 +C 41000 32100 1 0 0 generic-power.sym +{ +T 41200 32350 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +N 41200 31600 41200 32100 4 +C 41000 31600 1 90 1 resistor-1.sym +{ +T 40700 31100 5 10 1 1 0 6 1 +value=10K +T 41000 31600 5 10 0 1 270 2 1 +footprint=0603 +T 40700 30900 5 10 1 1 0 6 1 +refdes=R249 +} +N 41200 31900 40900 31900 4 +N 40900 31900 40900 31600 4 +N 40900 30700 40900 30000 4 +N 40900 30000 44800 30000 4 +{ +T 41500 30000 5 10 1 1 0 0 1 +netname=io_rx_06 +} +N 41200 31900 42200 31900 4 +N 42200 31900 42200 30900 4 +T 53700 34400 9 25 1 0 0 0 1 +Always On +C 49400 39900 1 90 0 capacitor-1.sym +{ +T 49300 40500 5 10 1 1 0 0 1 +refdes=C221 +T 49300 40100 5 10 1 1 0 0 1 +value=C221 +T 49400 39900 5 10 0 1 0 8 1 +footprint=0603 +} +C 49000 39900 1 90 0 inductor-1.sym +{ +T 48400 40500 5 10 1 1 0 0 1 +refdes=L221 +T 49000 39900 5 10 0 1 90 0 1 +footprint=0603 +T 48800 40200 5 10 1 1 0 6 1 +value=L221 +} +N 48900 39900 48900 39800 4 +N 48900 39800 49200 39800 4 +N 48900 40800 48900 40900 4 +N 48900 40900 49200 40900 4 +N 49200 40900 49200 40800 4 +C 51000 39900 1 90 0 capacitor-1.sym +{ +T 50900 40500 5 10 1 1 0 0 1 +refdes=C222 +T 50900 40100 5 10 1 1 0 0 1 +value=C222 +T 51000 39900 5 10 0 1 0 8 1 +footprint=0603 +} +C 50600 39900 1 90 0 inductor-1.sym +{ +T 49900 40500 5 10 1 1 0 0 1 +refdes=L222 +T 50600 39900 5 10 0 1 90 0 1 +footprint=0603 +T 50400 40200 5 10 1 1 0 6 1 +value=L222 +} +N 50500 39900 50500 39800 4 +N 50500 39800 50800 39800 4 +N 50800 39800 50800 39900 4 +N 50500 40800 50500 40900 4 +N 50500 40900 50800 40900 4 +N 50800 40900 50800 40800 4 +C 52600 39900 1 90 0 capacitor-1.sym +{ +T 52500 40500 5 10 1 1 0 0 1 +refdes=C223 +T 52500 40100 5 10 1 1 0 0 1 +value=C223 +T 52600 39900 5 10 0 1 0 8 1 +footprint=0603 +} +C 52200 39900 1 90 0 inductor-1.sym +{ +T 51500 40500 5 10 1 1 0 0 1 +refdes=L223 +T 52200 39900 5 10 0 1 90 0 1 +footprint=0603 +T 52000 40200 5 10 1 1 0 6 1 +value=L223 +} +N 52100 39800 52400 39800 4 +N 52400 39800 52400 39900 4 +N 52100 40800 52100 40900 4 +N 52100 40900 52400 40900 4 +N 52400 40900 52400 40800 4 +C 49400 40800 1 0 0 capacitor-1.sym +{ +T 49900 41100 5 10 1 1 0 0 1 +refdes=C224 +T 49400 41100 5 10 1 1 0 0 1 +value=C224 +T 49400 40800 5 10 0 1 270 8 1 +footprint=0603 +} +C 49400 41200 1 0 0 inductor-1.sym +{ +T 49900 41400 5 10 1 1 0 0 1 +refdes=L224 +T 49400 41200 5 10 0 1 0 0 1 +footprint=0603 +T 49400 41400 5 10 1 1 0 0 1 +value=L224 +} +N 49400 41300 49300 41300 4 +N 49300 41300 49300 41000 4 +N 49300 41000 49400 41000 4 +N 50300 41300 50400 41300 4 +N 50400 41300 50400 41000 4 +N 50400 41000 50300 41000 4 +C 51000 40800 1 0 0 capacitor-1.sym +{ +T 51500 41100 5 10 1 1 0 0 1 +refdes=C225 +T 51000 41100 5 10 1 1 0 0 1 +value=C225 +T 51000 40800 5 10 0 1 270 8 1 +footprint=0603 +} +C 51000 41200 1 0 0 inductor-1.sym +{ +T 51500 41400 5 10 1 1 0 0 1 +refdes=L225 +T 51000 41200 5 10 0 1 0 0 1 +footprint=0603 +T 51000 41400 5 10 1 1 0 0 1 +value=L225 +} +N 51000 41300 50900 41300 4 +N 50900 41300 50900 41000 4 +N 50900 41000 51000 41000 4 +N 51900 41300 52000 41300 4 +N 52000 41300 52000 41000 4 +N 52000 41000 51900 41000 4 +N 47800 41100 49300 41100 4 +N 50400 41100 50900 41100 4 +N 52000 41100 53400 41100 4 +N 52300 41100 52300 40900 4 +N 50700 41100 50700 40900 4 +N 49100 41100 49100 40900 4 +C 50700 39300 1 180 0 generic-power.sym +{ +T 50500 39050 5 10 1 1 180 3 1 +net=AGND:1 +} +N 49200 39500 49200 39900 4 +N 49200 39500 52100 39500 4 +N 52100 39500 52100 39900 4 +N 50700 39800 50700 39500 4 +N 50500 39500 50500 39300 4 +C 60300 33100 1 90 1 capacitor-1.sym +{ +T 60200 32800 5 10 1 1 0 0 1 +refdes=C240 +T 60200 32400 5 10 1 1 0 0 1 +value=1uF +T 60300 33100 5 10 0 1 0 6 1 +footprint=0603 +} +N 58300 33200 60100 33200 4 +N 60100 33200 60100 33100 4 +N 60100 32100 60100 32200 4 +C 60300 32100 1 180 0 generic-power.sym +{ +T 60100 31850 5 10 1 1 180 3 1 +net=AGND:1 +} +C 700 6000 1 0 0 saw0900-SAWTEK856327.sym +{ +T 52100 36100 5 10 1 1 0 6 1 +refdes=FIL2 +T 52200 35900 5 10 1 1 0 0 1 +value=FIL2 +} +C 700 8400 1 0 0 saw2400-SAWTEK855916.sym +{ +T 52100 38500 5 10 1 1 0 6 1 +refdes=FIL1 +T 52200 38200 5 10 1 1 0 0 1 +value=FIL1 +} +C 51700 34700 1 180 0 generic-power.sym +{ +T 51500 34450 5 10 1 1 180 3 1 +net=AGND:1 +} +N 51500 34900 51500 34700 4 +N 51300 34900 51300 34800 4 +N 51300 34800 51500 34800 4 +C 51700 37100 1 180 0 generic-power.sym +{ +T 51500 36850 5 10 1 1 180 3 1 +net=AGND:1 +} +N 51500 37300 51500 37100 4 +N 51300 37300 51300 37200 4 +N 51100 37300 51100 37200 4 +N 51100 37200 51500 37200 4 +N 51500 37200 51700 37200 4 +N 51700 37200 51700 37300 4 +N 53000 38000 52300 38000 4 +N 53000 35600 53000 41100 4 +N 53000 35600 52300 35600 4 +N 48300 41100 48300 38000 4 +N 48300 38000 50400 38000 4 +N 49800 38000 49800 35600 4 +N 49800 35600 50400 35600 4 +N 44800 30900 43700 30900 4 +{ +T 43900 30900 5 10 1 1 0 0 1 +netname=io_rx_07 +} +C 42800 30800 1 0 0 resistor-1.sym +{ +T 42900 30600 5 10 1 1 180 8 1 +refdes=R262 +T 42800 30800 5 10 0 1 180 8 1 +footprint=0603 +T 43300 30600 5 10 1 1 0 0 1 +value=3.32K +} +C 42700 31300 1 180 1 resistor-1.sym +{ +T 42700 31500 5 10 1 1 0 2 1 +refdes=R261 +T 42700 31300 5 10 0 1 0 2 1 +footprint=0603 +T 43200 31500 5 10 1 1 180 6 1 +value=3.32K +} +N 44800 31200 43600 31200 4 +{ +T 43900 31200 5 10 1 1 0 0 1 +netname=io_tx_07 +} +N 42200 30900 42800 30900 4 +N 42700 31200 42200 31200 4 +N 46800 31200 48200 31200 4 +{ +T 47200 31200 5 10 1 1 0 0 1 +netname=TX_PUP +} +N 46800 30900 48200 30900 4 +{ +T 47200 30900 5 10 1 1 0 0 1 +netname=RX_PUP +} diff --git a/usrp-hw/rfx/common2400.sch b/usrp-hw/rfx/common2400.sch new file mode 100644 index 000000000..3fcda52d7 --- /dev/null +++ b/usrp-hw/rfx/common2400.sch @@ -0,0 +1,538 @@ +v 20050820 1 +C 39500 25900 0 0 0 title-C.sym +C 52000 40600 1 0 1 BNC-1.sym +{ +T 52000 41400 5 10 1 1 0 6 1 +refdes=J200 +T 52000 40600 5 10 0 1 0 0 1 +footprint=SMA_VERT +} +C 52100 40300 1 180 0 generic-power.sym +{ +T 51900 40050 5 10 1 1 180 3 1 +net=AGND:1 +} +N 51900 40600 51900 40300 4 +C 44000 40500 1 180 0 capacitor-1.sym +{ +T 43700 40400 5 10 1 1 0 0 1 +refdes=C201 +T 44400 40100 5 10 1 1 0 6 1 +value=100pF +T 44000 40500 5 10 0 1 270 0 1 +footprint=0603 +} +C 42500 40900 1 180 1 capacitor-1.sym +{ +T 42900 40800 5 10 1 1 180 2 1 +refdes=C202 +T 42900 40500 5 10 1 1 180 2 1 +value=100pF +T 42500 40900 5 10 0 1 270 2 1 +footprint=0603 +} +C 43800 38400 1 180 1 generic-power.sym +{ +T 44000 38150 5 10 1 1 180 3 1 +net=AGND:1 +} +N 44000 40300 44500 40300 4 +N 44500 40700 43400 40700 4 +N 43100 40300 42000 40300 4 +{ +T 42100 40300 5 10 1 1 0 0 1 +netname=RF_TX +} +N 41200 30600 44800 30600 4 +{ +T 41500 30600 5 10 1 1 0 0 1 +netname=io_tx_06 +} +T 40300 26300 9 15 1 0 0 0 6 +Band +400 - 500 MHz +800 - 975 MHz +1.2 - 1.3 GHz +2.3 - 2.4 GHz +2.4 - 2.7 GHz +T 47100 26300 9 15 1 0 0 0 6 +Upconverter VCO +ADF4360-7 (Div by 2) +ADF4360-3 (Div by 2) +ADF4360-0 (Div by 2) +ADF4360-1 +ADF4360-0 +T 42900 26300 9 15 1 0 0 0 6 +Upconverter +AD8345 +AD8349 +AD8349 +AD8349 +AD8349 +T 44900 26300 9 15 1 0 0 0 6 +Downconverter +AD8348 +AD8347 +AD8347 +AD8347 +AD8347 +T 50300 26300 9 15 1 0 0 0 6 +Downconverter VCO +ADF4360-3 (Div by 2) +Same +Same +Same +Same +T 56600 26600 5 10 1 1 0 0 1 +date=$Date: 2006/03/10 02:20:13 $ +T 58500 26300 5 10 1 1 0 0 1 +rev=$Revision: 1.2 $ +T 58600 26000 5 10 1 1 0 0 1 +auth=$Author: matt $ +T 54400 26300 5 10 1 1 0 0 1 +fname=$Source: /opt/usrp-hw-cvs/usrp-hw/flex_xcvr/common2400.sch,v $ +T 57800 27000 8 14 1 1 0 4 1 +title=Flex2400 Common +T 55400 26000 9 10 1 0 0 0 1 +1 +T 56200 26000 9 10 1 0 0 0 1 +3 +C 44400 38200 1 0 0 hmc174ms8.sym +{ +T 45700 41800 5 10 1 1 0 6 1 +refdes=U202 +} +C 48800 40900 1 0 0 capacitor-1.sym +{ +T 49200 41000 5 10 1 1 180 0 1 +refdes=C204 +T 50100 41000 5 10 1 1 180 0 1 +value=NONE +T 48800 40900 5 10 0 1 270 8 1 +footprint=0603 +} +N 46500 41100 48800 41100 4 +N 44100 41500 44100 41100 4 +N 44100 41100 44500 41100 4 +N 44000 38400 44000 39100 4 +N 44000 39100 44500 39100 4 +N 44500 38700 44000 38700 4 +T 46400 38600 9 10 1 0 0 0 2 +B high selects RF1 +A high selects RF2 +C 40800 35100 1 0 0 BNC-1.sym +{ +T 40800 35900 5 10 1 1 0 0 1 +refdes=J202 +T 40800 35100 5 10 0 1 0 6 1 +footprint=SMA_VERT +} +C 40700 34800 1 180 1 generic-power.sym +{ +T 40900 34550 5 10 1 1 180 3 1 +net=AGND:1 +} +N 40900 35100 40900 34800 4 +C 43400 35800 1 180 1 capacitor-1.sym +{ +T 43800 35700 5 10 1 1 180 2 1 +refdes=C206 +T 43800 35400 5 10 1 1 180 2 1 +value=100pF +T 43400 35800 5 10 0 1 270 2 1 +footprint=0603 +} +C 43800 33700 1 180 1 generic-power.sym +{ +T 44000 33450 5 10 1 1 180 3 1 +net=AGND:1 +} +N 44500 36000 41800 36000 4 +C 44400 33500 1 0 0 hmc174ms8.sym +{ +T 45700 37100 5 10 1 1 0 6 1 +refdes=U209 +} +C 46900 36200 1 0 0 capacitor-1.sym +{ +T 47300 36300 5 10 1 1 180 0 1 +refdes=C205 +T 48200 36300 5 10 1 1 180 0 1 +value=100pF +T 46900 36200 5 10 0 1 270 8 1 +footprint=0603 +} +N 46500 36400 46900 36400 4 +N 44100 36800 44100 36400 4 +N 44100 36400 44500 36400 4 +N 44000 33700 44000 34400 4 +N 44000 34400 44500 34400 4 +N 44500 34000 44000 34000 4 +T 46400 33900 9 10 1 0 0 0 2 +B high selects RF1 +A high selects RF2 +T 50800 41700 9 30 1 0 0 0 1 +TX/RX +T 40400 35400 9 30 1 0 0 6 1 +RX +N 49200 36400 47800 36400 4 +{ +T 49000 36400 5 10 1 1 0 6 1 +netname=RF_RX +} +N 41300 35600 43400 35600 4 +N 42500 40700 41800 40700 4 +N 41800 36000 41800 40700 4 +N 44300 35600 44500 35600 4 +T 54600 35800 9 10 1 0 0 0 22 +A1 B1 A2 B2 +0 0 0 0 All Off + +0 1 0 0 TX Only +0 1 1 0 TX Only + +0 1 0 1 Full Duplex TX and RX + +0 0 0 1 RX from secondary RX port +1 0 0 1 RX from secondary RX port +1 0 1 0 RX from primary TX/RX port + +0 0 1 0 Nothing +1 0 0 0 Nothing + +0 0 1 1 BAD! +0 1 1 1 BAD! +1 0 1 1 BAD! +1 1 0 0 BAD! +1 1 0 1 BAD! +1 1 1 0 BAD! +1 1 1 1 BAD! +C 41100 31600 1 270 0 resistor-1.sym +{ +T 41400 31100 5 10 1 1 0 0 1 +value=10K +T 41100 31600 5 10 0 1 270 0 1 +footprint=0603 +T 41400 30900 5 10 1 1 0 0 1 +refdes=R250 +} +C 52700 33000 1 90 1 capacitor-1.sym +{ +T 52900 32900 5 10 1 1 0 6 1 +refdes=C200 +T 52600 32700 5 10 1 1 0 0 1 +value=220pF +T 52700 33000 5 10 0 1 0 6 1 +footprint=0603 +} +N 52500 31800 52500 32100 4 +C 55200 33000 1 270 0 capacitor-2.sym +{ +T 54900 32200 5 10 1 1 0 0 1 +refdes=C208 +T 54900 32000 5 10 1 1 0 0 1 +value=4.7uF +T 55200 33000 5 10 0 1 0 0 1 +footprint=1206 +} +C 55800 31500 1 0 0 adp3336.sym +{ +T 57700 33700 5 10 1 1 0 6 1 +refdes=U203 +} +N 57900 32400 58100 32400 4 +N 58100 32400 58100 33200 4 +N 58100 32800 57900 32800 4 +C 58100 33700 1 0 0 generic-power.sym +{ +T 58300 33950 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +N 57900 33200 58300 33200 4 +C 53000 33000 1 270 0 capacitor-1.sym +{ +T 52700 32200 5 10 1 1 0 0 1 +refdes=C203 +T 52700 32000 5 10 1 1 0 0 1 +value=0.1uF +T 53000 33000 5 10 0 1 0 0 1 +footprint=0603 +} +C 53900 33000 1 90 1 capacitor-1.sym +{ +T 54100 32200 5 10 1 1 0 6 1 +refdes=C207 +T 54100 32000 5 10 1 1 0 6 1 +value=1uF +T 53900 33000 5 10 0 1 0 6 1 +footprint=0603 +} +N 53700 31800 53700 32100 4 +N 53700 33000 53700 33300 4 +N 53200 31800 53200 32100 4 +N 53200 33000 53200 33300 4 +C 53800 33200 1 0 0 inductor-1.sym +{ +T 54000 33500 5 10 1 1 0 0 1 +refdes=L202 +T 53800 33200 5 10 0 1 0 0 1 +footprint=1206 +} +C 54600 33000 1 270 0 capacitor-1.sym +{ +T 54300 32200 5 10 1 1 0 0 1 +refdes=C209 +T 54300 32000 5 10 1 1 0 0 1 +value=0.1uF +T 54600 33000 5 10 0 1 0 0 1 +footprint=0603 +} +N 55400 31800 55400 32100 4 +N 55400 33000 55400 33300 4 +N 54800 31800 54800 32100 4 +N 54800 33000 54800 33300 4 +N 53200 31400 53200 31800 4 +N 54700 33300 55700 33300 4 +N 55700 32800 55900 32800 4 +N 55700 33200 55900 33200 4 +N 55700 32400 55900 32400 4 +N 55700 32400 55700 33300 4 +N 52500 31800 55700 31800 4 +N 55700 31800 55700 32000 4 +N 55700 32000 55900 32000 4 +C 58200 33000 1 270 0 resistor-1.sym +{ +T 58500 32600 5 10 1 1 180 8 1 +refdes=R201 +T 58200 33000 5 10 0 1 90 8 1 +footprint=0603 +T 58500 32400 5 10 1 1 0 0 1 +value=140K +} +C 58200 31900 1 270 0 resistor-1.sym +{ +T 58500 31500 5 10 1 1 180 8 1 +refdes=R202 +T 58200 31900 5 10 0 1 90 8 1 +footprint=0603 +T 58500 31300 5 10 1 1 0 0 1 +value=78.7K +} +N 58300 30900 58300 31000 4 +N 57900 32000 58300 32000 4 +N 58300 31900 58300 32100 4 +N 58300 33000 58300 33700 4 +C 59200 33100 1 90 1 capacitor-1.sym +{ +T 59100 32800 5 10 1 1 0 0 1 +refdes=C210 +T 59100 32400 5 10 1 1 0 0 1 +value=470pF +T 59200 33100 5 10 0 1 0 6 1 +footprint=0603 +} +N 58300 32000 59000 32000 4 +N 59000 32000 59000 32200 4 +N 59000 33200 59000 33100 4 +N 52500 33300 53800 33300 4 +C 53400 31400 1 180 0 generic-power.sym +{ +T 53200 31150 5 10 1 1 180 3 1 +net=AGND:1 +} +C 58500 30900 1 180 0 generic-power.sym +{ +T 58300 30650 5 10 1 1 180 3 1 +net=AGND:1 +} +C 52700 33600 1 0 1 generic-power.sym +{ +T 52500 33850 5 10 1 1 180 5 1 +net=6V_RX:1 +} +N 52500 33000 52500 33600 4 +C 43900 41500 1 0 0 generic-power.sym +{ +T 44100 41750 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +C 43900 36800 1 0 0 generic-power.sym +{ +T 44100 37050 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +C 44800 29500 1 0 0 7404-3.sym +{ +T 46300 31500 5 10 1 1 0 0 1 +refdes=U204 +T 45200 29300 5 10 1 1 0 0 1 +net=3_3V_SW:14 +T 45200 29100 5 10 1 1 0 0 1 +net=AGND:7 +T 44800 29500 5 10 0 1 0 0 1 +footprint=SO14 +} +N 46800 30600 48200 30600 4 +{ +T 47300 30600 5 10 1 1 0 0 1 +netname=TX +} +N 46800 30300 48200 30300 4 +{ +T 47300 30300 5 10 1 1 0 0 1 +netname=RX +} +N 46800 30000 48200 30000 4 +{ +T 47300 30000 5 10 1 1 0 0 1 +netname=RX1 +} +N 46800 29700 48200 29700 4 +{ +T 47300 29700 5 10 1 1 0 0 1 +netname=RX2 +} +N 43100 39500 44500 39500 4 +{ +T 43600 39500 5 10 1 1 0 0 1 +netname=TX +} +N 43100 39900 44500 39900 4 +{ +T 43600 39900 5 10 1 1 0 0 1 +netname=RX +} +N 43100 35200 44500 35200 4 +{ +T 43600 35200 5 10 1 1 0 0 1 +netname=RX1 +} +N 43100 34800 44500 34800 4 +{ +T 43600 34800 5 10 1 1 0 0 1 +netname=RX2 +} +N 41200 29700 44800 29700 4 +{ +T 41700 29700 5 10 1 1 0 0 1 +netname=RX1 +} +N 41200 30300 44800 30300 4 +{ +T 41700 30300 5 10 1 1 0 0 1 +netname=TX +} +N 41200 30600 41200 30700 4 +C 41000 32100 1 0 0 generic-power.sym +{ +T 41200 32350 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +N 41200 31600 41200 32100 4 +C 41000 31600 1 90 1 resistor-1.sym +{ +T 40700 31100 5 10 1 1 0 6 1 +value=10K +T 41000 31600 5 10 0 1 270 2 1 +footprint=0603 +T 40700 30900 5 10 1 1 0 6 1 +refdes=R249 +} +N 41200 31900 40900 31900 4 +N 40900 31900 40900 31600 4 +N 40900 30700 40900 30000 4 +N 40900 30000 44800 30000 4 +{ +T 41500 30000 5 10 1 1 0 0 1 +netname=io_rx_06 +} +T 53700 34400 9 25 1 0 0 0 1 +Always On +N 49700 41100 51500 41100 4 +C 60300 33100 1 90 1 capacitor-1.sym +{ +T 60200 32800 5 10 1 1 0 0 1 +refdes=C240 +T 60200 32400 5 10 1 1 0 0 1 +value=1uF +T 60300 33100 5 10 0 1 0 6 1 +footprint=0603 +} +N 58300 33200 60100 33200 4 +N 60100 33200 60100 33100 4 +N 60100 32100 60100 32200 4 +C 60300 32100 1 180 0 generic-power.sym +{ +T 60100 31850 5 10 1 1 180 3 1 +net=AGND:1 +} +C -1200 8400 1 0 0 saw2400-SAWTEK855916.sym +{ +T 50200 38500 5 10 1 1 0 6 1 +refdes=FIL1 +T 50300 38200 5 10 1 1 0 0 1 +value=FIL1 +} +C 49800 37100 1 180 0 generic-power.sym +{ +T 49600 36850 5 10 1 1 180 3 1 +net=AGND:1 +} +N 49600 37300 49600 37100 4 +N 49400 37300 49400 37200 4 +N 49200 37300 49200 37200 4 +N 49200 37200 49600 37200 4 +N 49600 37200 49800 37200 4 +N 49800 37200 49800 37300 4 +N 51100 38000 50400 38000 4 +N 51100 38000 51100 41100 4 +N 46700 41100 46700 38000 4 +N 46700 38000 48500 38000 4 +N 44800 30900 43700 30900 4 +{ +T 43900 30900 5 10 1 1 0 0 1 +netname=io_rx_07 +} +C 42800 30800 1 0 0 resistor-1.sym +{ +T 42900 30600 5 10 1 1 180 8 1 +refdes=R262 +T 42800 30800 5 10 0 1 180 8 1 +footprint=0603 +T 43300 30600 5 10 1 1 0 0 1 +value=3.32K +} +C 42700 31300 1 180 1 resistor-1.sym +{ +T 42700 31500 5 10 1 1 0 2 1 +refdes=R261 +T 42700 31300 5 10 0 1 0 2 1 +footprint=0603 +T 43200 31500 5 10 1 1 180 6 1 +value=3.32K +} +N 44800 31200 43600 31200 4 +{ +T 43900 31200 5 10 1 1 0 0 1 +netname=io_tx_07 +} +N 42200 30900 42800 30900 4 +N 42700 31200 42200 31200 4 +N 46800 31200 48200 31200 4 +{ +T 47200 31200 5 10 1 1 0 0 1 +netname=TX_PUP +} +N 46800 30900 48200 30900 4 +{ +T 47200 30900 5 10 1 1 0 0 1 +netname=RX_PUP +} +C 42500 32000 1 180 1 generic-power.sym +{ +T 42700 31750 5 10 1 1 180 3 1 +net=AGND:1 +} +N 42200 30900 42200 32100 4 +N 42200 32100 42700 32100 4 +N 42700 32100 42700 32000 4 diff --git a/usrp-hw/rfx/common400.sch b/usrp-hw/rfx/common400.sch new file mode 100644 index 000000000..2389104c0 --- /dev/null +++ b/usrp-hw/rfx/common400.sch @@ -0,0 +1,609 @@ +v 20050820 1 +C 39500 25900 0 0 0 title-C.sym +T 55500 28900 9 10 1 0 0 0 1 +Band Filter +C 53900 40600 1 0 1 BNC-1.sym +{ +T 53900 41400 5 10 1 1 0 6 1 +refdes=J200 +T 53900 40600 5 10 0 1 0 0 1 +footprint=SMA_VERT +} +C 54000 40300 1 180 0 generic-power.sym +{ +T 53800 40050 5 10 1 1 180 3 1 +net=AGND:1 +} +N 53800 40600 53800 40300 4 +C 44000 40500 1 180 0 capacitor-1.sym +{ +T 43700 40400 5 10 1 1 0 0 1 +refdes=C201 +T 44400 40100 5 10 1 1 0 6 1 +value=1000pF +T 44000 40500 5 10 0 1 270 0 1 +footprint=0603 +} +T 55500 28700 9 10 1 0 0 0 1 +Exposed paddle on Quad Mod +C 42500 40900 1 180 1 capacitor-1.sym +{ +T 42900 40800 5 10 1 1 180 2 1 +refdes=C202 +T 42900 40500 5 10 1 1 180 2 1 +value=1000pF +T 42500 40900 5 10 0 1 270 2 1 +footprint=0603 +} +C 43800 38400 1 180 1 generic-power.sym +{ +T 44000 38150 5 10 1 1 180 3 1 +net=AGND:1 +} +N 44000 40300 44500 40300 4 +N 44500 40700 43400 40700 4 +N 43100 40300 42000 40300 4 +{ +T 42100 40300 5 10 1 1 0 0 1 +netname=RF_TX +} +N 41200 30600 42600 30600 4 +{ +T 41500 30600 5 10 1 1 0 0 1 +netname=io_tx_06 +} +T 40300 26300 9 15 1 0 0 0 6 +Band +400 - 500 MHz +800 - 975 MHz +1.2 - 1.3 GHz +2.3 - 2.4 GHz +2.4 - 2.7 GHz +T 47100 26300 9 15 1 0 0 0 6 +Upconverter VCO +ADF4360-7 (Div by 2) +ADF4360-3 (Div by 2) +ADF4360-0 (Div by 2) +ADF4360-1 +ADF4360-0 +T 42900 26300 9 15 1 0 0 0 6 +Upconverter +AD8345 +AD8349 +AD8349 +AD8349 +AD8349 +T 44900 26300 9 15 1 0 0 0 6 +Downconverter +AD8348 +AD8347 +AD8347 +AD8347 +AD8347 +T 50300 26300 9 15 1 0 0 0 6 +Downconverter VCO +ADF4360-3 (Div by 2) +Same +Same +Same +Same +T 56600 26600 5 10 1 1 0 0 1 +date=$Date: 2005/12/13 20:27:08 $ +T 58500 26300 5 10 1 1 0 0 1 +rev=$Revision: 1.13 $ +T 58600 26000 5 10 1 1 0 0 1 +auth=$Author: matt $ +T 54400 26300 5 10 1 1 0 0 1 +fname=$Source: /opt/usrp-hw-cvs/usrp-hw/flex_xcvr/common400.sch,v $ +T 57800 27000 8 14 1 1 0 4 1 +title=Flex400 Common +T 55400 26000 9 10 1 0 0 0 1 +1 +T 56200 26000 9 10 1 0 0 0 1 +3 +C 44400 38200 1 0 0 hmc174ms8.sym +{ +T 46500 41600 5 10 1 1 0 6 1 +refdes=U202 +} +C 46900 40900 1 0 0 capacitor-1.sym +{ +T 47300 41000 5 10 1 1 180 0 1 +refdes=C204 +T 48200 41000 5 10 1 1 180 0 1 +value=1000pF +T 46900 40900 5 10 0 1 270 8 1 +footprint=0603 +} +N 46500 41100 46900 41100 4 +N 44100 41500 44100 41100 4 +N 44100 41100 44500 41100 4 +N 44000 38400 44000 39100 4 +N 44000 39100 44500 39100 4 +N 44500 38700 44000 38700 4 +T 46400 38600 9 10 1 0 0 0 2 +B high selects RF1 +A high selects RF2 +C 40800 35100 1 0 0 BNC-1.sym +{ +T 40800 35900 5 10 1 1 0 0 1 +refdes=J202 +T 40800 35100 5 10 0 1 0 6 1 +footprint=SMA_VERT +} +C 40700 34800 1 180 1 generic-power.sym +{ +T 40900 34550 5 10 1 1 180 3 1 +net=AGND:1 +} +N 40900 35100 40900 34800 4 +C 43400 35800 1 180 1 capacitor-1.sym +{ +T 43800 35700 5 10 1 1 180 2 1 +refdes=C206 +T 43800 35400 5 10 1 1 180 2 1 +value=1000pF +T 43400 35800 5 10 0 1 270 2 1 +footprint=0603 +} +C 43800 33700 1 180 1 generic-power.sym +{ +T 44000 33450 5 10 1 1 180 3 1 +net=AGND:1 +} +N 44500 36000 41800 36000 4 +C 44400 33500 1 0 0 hmc174ms8.sym +{ +T 46500 36900 5 10 1 1 0 6 1 +refdes=U209 +} +C 46900 36200 1 0 0 capacitor-1.sym +{ +T 47300 36300 5 10 1 1 180 0 1 +refdes=C205 +T 48200 36300 5 10 1 1 180 0 1 +value=1000pF +T 46900 36200 5 10 0 1 270 8 1 +footprint=0603 +} +N 46500 36400 46900 36400 4 +N 44100 36800 44100 36400 4 +N 44100 36400 44500 36400 4 +N 44000 33700 44000 34400 4 +N 44000 34400 44500 34400 4 +N 44500 34000 44000 34000 4 +T 46400 33900 9 10 1 0 0 0 2 +B high selects RF1 +A high selects RF2 +T 52700 41700 9 30 1 0 0 0 1 +TX/RX +T 40400 35400 9 30 1 0 0 6 1 +RX +N 49200 36400 47800 36400 4 +{ +T 49000 36400 5 10 1 1 0 6 1 +netname=RF_RX +} +N 41300 35600 43400 35600 4 +N 42500 40700 41800 40700 4 +N 41800 36000 41800 40700 4 +N 44300 35600 44500 35600 4 +T 54600 35800 9 10 1 0 0 0 22 +A1 B1 A2 B2 +0 0 0 0 All Off + +0 1 0 0 TX Only +0 1 1 0 TX Only + +0 1 0 1 Full Duplex TX and RX + +0 0 0 1 RX from secondary RX port +1 0 0 1 RX from secondary RX port +1 0 1 0 RX from primary TX/RX port + +0 0 1 0 Nothing +1 0 0 0 Nothing + +0 0 1 1 BAD! +0 1 1 1 BAD! +1 0 1 1 BAD! +1 1 0 0 BAD! +1 1 0 1 BAD! +1 1 1 0 BAD! +1 1 1 1 BAD! +C 41100 31600 1 270 0 resistor-1.sym +{ +T 41400 31100 5 10 1 1 0 0 1 +value=10K +T 41100 31600 5 10 0 1 270 0 1 +footprint=0603 +T 41400 30900 5 10 1 1 0 0 1 +refdes=R250 +} +C 52700 33000 1 90 1 capacitor-1.sym +{ +T 52900 32900 5 10 1 1 0 6 1 +refdes=C200 +T 52600 32700 5 10 1 1 0 0 1 +value=220pF +T 52700 33000 5 10 0 1 0 6 1 +footprint=0603 +} +N 52500 31800 52500 32100 4 +C 55200 33000 1 270 0 capacitor-2.sym +{ +T 54900 32200 5 10 1 1 0 0 1 +refdes=C208 +T 54900 32000 5 10 1 1 0 0 1 +value=4.7uF +T 55200 33000 5 10 0 1 0 0 1 +footprint=1206 +} +C 55800 31500 1 0 0 adp3336.sym +{ +T 57600 33700 5 10 1 1 0 6 1 +refdes=U203 +} +N 57900 32400 58100 32400 4 +N 58100 32400 58100 33200 4 +N 58100 32800 57900 32800 4 +C 58100 33700 1 0 0 generic-power.sym +{ +T 58300 33950 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +N 57900 33200 58300 33200 4 +C 53000 33000 1 270 0 capacitor-1.sym +{ +T 52700 32200 5 10 1 1 0 0 1 +refdes=C203 +T 52700 32000 5 10 1 1 0 0 1 +value=0.1uF +T 53000 33000 5 10 0 1 0 0 1 +footprint=0603 +} +C 53900 33000 1 90 1 capacitor-1.sym +{ +T 54100 32200 5 10 1 1 0 6 1 +refdes=C207 +T 54100 32000 5 10 1 1 0 6 1 +value=1uF +T 53900 33000 5 10 0 1 0 6 1 +footprint=0603 +} +N 53700 31800 53700 32100 4 +N 53700 33000 53700 33300 4 +N 53200 31800 53200 32100 4 +N 53200 33000 53200 33300 4 +C 53800 33200 1 0 0 inductor-1.sym +{ +T 54000 33500 5 10 1 1 0 0 1 +refdes=L202 +T 53800 33200 5 10 0 1 0 0 1 +footprint=1206 +} +C 54600 33000 1 270 0 capacitor-1.sym +{ +T 54300 32200 5 10 1 1 0 0 1 +refdes=C209 +T 54300 32000 5 10 1 1 0 0 1 +value=0.1uF +T 54600 33000 5 10 0 1 0 0 1 +footprint=0603 +} +N 55400 31800 55400 32100 4 +N 55400 33000 55400 33300 4 +N 54800 31800 54800 32100 4 +N 54800 33000 54800 33300 4 +N 53200 31400 53200 31800 4 +N 54700 33300 55700 33300 4 +N 55700 32800 55900 32800 4 +N 55700 33200 55900 33200 4 +N 55700 32400 55900 32400 4 +N 55700 32400 55700 33300 4 +N 52500 31800 55700 31800 4 +N 55700 31800 55700 32000 4 +N 55700 32000 55900 32000 4 +C 58200 33000 1 270 0 resistor-1.sym +{ +T 58500 32600 5 10 1 1 180 8 1 +refdes=R201 +T 58200 33000 5 10 0 1 90 8 1 +footprint=0603 +T 58500 32400 5 10 1 1 0 0 1 +value=140K +} +C 58200 31900 1 270 0 resistor-1.sym +{ +T 58500 31500 5 10 1 1 180 8 1 +refdes=R202 +T 58200 31900 5 10 0 1 90 8 1 +footprint=0603 +T 58500 31300 5 10 1 1 0 0 1 +value=78.7K +} +N 58300 30900 58300 31000 4 +N 57900 32000 58300 32000 4 +N 58300 31900 58300 32100 4 +N 58300 33000 58300 33700 4 +C 59200 33100 1 90 1 capacitor-1.sym +{ +T 59100 32800 5 10 1 1 0 0 1 +refdes=C210 +T 59100 32400 5 10 1 1 0 0 1 +value=470pF +T 59200 33100 5 10 0 1 0 6 1 +footprint=0603 +} +N 58300 32000 59000 32000 4 +N 59000 32000 59000 32200 4 +N 59000 33200 59000 33100 4 +N 52500 33300 53800 33300 4 +C 53400 31400 1 180 0 generic-power.sym +{ +T 53200 31150 5 10 1 1 180 3 1 +net=AGND:1 +} +C 58500 30900 1 180 0 generic-power.sym +{ +T 58300 30650 5 10 1 1 180 3 1 +net=AGND:1 +} +C 52700 33600 1 0 1 generic-power.sym +{ +T 52500 33850 5 10 1 1 180 5 1 +net=6V_RX:1 +} +N 52500 33000 52500 33600 4 +C 43900 41500 1 0 0 generic-power.sym +{ +T 44100 41750 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +C 43900 36800 1 0 0 generic-power.sym +{ +T 44100 37050 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +C 42600 29500 1 0 0 7404-3.sym +{ +T 44100 31500 5 10 1 1 0 0 1 +refdes=U204 +T 43000 29300 5 10 1 1 0 0 1 +net=3_3V_SW:14 +T 43000 29100 5 10 1 1 0 0 1 +net=AGND:7 +T 42600 29500 5 10 0 1 0 0 1 +footprint=SO14 +} +N 44600 30600 46000 30600 4 +{ +T 45100 30600 5 10 1 1 0 0 1 +netname=TX +} +N 44600 30300 46000 30300 4 +{ +T 45100 30300 5 10 1 1 0 0 1 +netname=RX +} +N 44600 30000 46000 30000 4 +{ +T 45100 30000 5 10 1 1 0 0 1 +netname=RX1 +} +N 44600 29700 46000 29700 4 +{ +T 45100 29700 5 10 1 1 0 0 1 +netname=RX2 +} +N 43100 39500 44500 39500 4 +{ +T 43600 39500 5 10 1 1 0 0 1 +netname=TX +} +N 43100 39900 44500 39900 4 +{ +T 43600 39900 5 10 1 1 0 0 1 +netname=RX +} +N 43100 35200 44500 35200 4 +{ +T 43600 35200 5 10 1 1 0 0 1 +netname=RX1 +} +N 43100 34800 44500 34800 4 +{ +T 43600 34800 5 10 1 1 0 0 1 +netname=RX2 +} +N 41200 29700 42600 29700 4 +{ +T 41700 29700 5 10 1 1 0 0 1 +netname=RX1 +} +N 41200 30300 42600 30300 4 +{ +T 41700 30300 5 10 1 1 0 0 1 +netname=TX +} +N 41200 30600 41200 30700 4 +C 41000 32100 1 0 0 generic-power.sym +{ +T 41200 32350 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +N 41200 31600 41200 32100 4 +C 41000 31600 1 90 1 resistor-1.sym +{ +T 40700 31100 5 10 1 1 0 6 1 +value=10K +T 41000 31600 5 10 0 1 270 2 1 +footprint=0603 +T 40700 30900 5 10 1 1 0 6 1 +refdes=R249 +} +N 41200 31900 40900 31900 4 +N 40900 31900 40900 31600 4 +N 40900 30700 40900 30000 4 +N 40900 30000 42600 30000 4 +{ +T 41500 30000 5 10 1 1 0 0 1 +netname=io_rx_06 +} +N 41200 31900 42200 31900 4 +N 42200 31900 42200 30900 4 +N 42200 30900 42600 30900 4 +N 42200 31200 42600 31200 4 +T 53700 34400 9 25 1 0 0 0 1 +Always On +C 49400 39900 1 90 0 capacitor-1.sym +{ +T 49300 40500 5 10 1 1 0 0 1 +refdes=C221 +T 49300 40100 5 10 1 1 0 0 1 +value=3.9pF +T 49400 39900 5 10 0 1 0 8 1 +footprint=0603 +} +C 49000 39900 1 90 0 inductor-1.sym +{ +T 48400 40500 5 10 1 1 0 0 1 +refdes=L221 +T 49000 39900 5 10 0 1 90 0 1 +footprint=0603 +T 48800 40200 5 10 1 1 0 6 1 +value=NONE +} +N 48900 39900 48900 39800 4 +N 48900 39800 49200 39800 4 +N 48900 40800 48900 40900 4 +N 48900 40900 49200 40900 4 +N 49200 40900 49200 40800 4 +C 51000 39900 1 90 0 capacitor-1.sym +{ +T 50900 40500 5 10 1 1 0 0 1 +refdes=C222 +T 50900 40100 5 10 1 1 0 0 1 +value=12pF +T 51000 39900 5 10 0 1 0 8 1 +footprint=0603 +} +C 50600 39900 1 90 0 inductor-1.sym +{ +T 49900 40500 5 10 1 1 0 0 1 +refdes=L222 +T 50600 39900 5 10 0 1 90 0 1 +footprint=0603 +T 50400 40200 5 10 1 1 0 6 1 +value=NONE +} +N 50500 39900 50500 39800 4 +N 50500 39800 50800 39800 4 +N 50800 39800 50800 39900 4 +N 50500 40800 50500 40900 4 +N 50500 40900 50800 40900 4 +N 50800 40900 50800 40800 4 +C 52600 39900 1 90 0 capacitor-1.sym +{ +T 52500 40500 5 10 1 1 0 0 1 +refdes=C223 +T 52500 40100 5 10 1 1 0 0 1 +value=3.9pF +T 52600 39900 5 10 0 1 0 8 1 +footprint=0603 +} +C 52200 39900 1 90 0 inductor-1.sym +{ +T 51500 40500 5 10 1 1 0 0 1 +refdes=L223 +T 52200 39900 5 10 0 1 90 0 1 +footprint=0603 +T 52000 40200 5 10 1 1 0 6 1 +value=NONE +} +N 52100 39800 52400 39800 4 +N 52400 39800 52400 39900 4 +N 52100 40800 52100 40900 4 +N 52100 40900 52400 40900 4 +N 52400 40900 52400 40800 4 +C 49400 40800 1 0 0 capacitor-1.sym +{ +T 49900 41100 5 10 1 1 0 0 1 +refdes=C224 +T 49400 41100 5 10 1 1 0 0 1 +value=NONE +T 49400 40800 5 10 0 1 270 8 1 +footprint=0603 +} +C 49400 41200 1 0 0 inductor-1.sym +{ +T 49900 41400 5 10 1 1 0 0 1 +refdes=L224 +T 49400 41200 5 10 0 1 0 0 1 +footprint=0603 +T 49400 41400 5 10 1 1 0 0 1 +value=22nH +} +N 49400 41300 49300 41300 4 +N 49300 41300 49300 41000 4 +N 49300 41000 49400 41000 4 +N 50300 41300 50400 41300 4 +N 50400 41300 50400 41000 4 +N 50400 41000 50300 41000 4 +C 51000 40800 1 0 0 capacitor-1.sym +{ +T 51500 41100 5 10 1 1 0 0 1 +refdes=C225 +T 51000 41100 5 10 1 1 0 0 1 +value=NONE +T 51000 40800 5 10 0 1 270 8 1 +footprint=0603 +} +C 51000 41200 1 0 0 inductor-1.sym +{ +T 51500 41400 5 10 1 1 0 0 1 +refdes=L225 +T 51000 41200 5 10 0 1 0 0 1 +footprint=0603 +T 51000 41400 5 10 1 1 0 0 1 +value=22nH +} +N 51000 41300 50900 41300 4 +N 50900 41300 50900 41000 4 +N 50900 41000 51000 41000 4 +N 51900 41300 52000 41300 4 +N 52000 41300 52000 41000 4 +N 52000 41000 51900 41000 4 +N 47800 41100 49300 41100 4 +N 50400 41100 50900 41100 4 +N 52000 41100 53400 41100 4 +N 52300 41100 52300 40900 4 +N 50700 41100 50700 40900 4 +N 49100 41100 49100 40900 4 +C 50700 39300 1 180 0 generic-power.sym +{ +T 50500 39050 5 10 1 1 180 3 1 +net=AGND:1 +} +N 49200 39500 49200 39900 4 +N 49200 39500 52100 39500 4 +N 52100 39500 52100 39900 4 +N 50700 39800 50700 39500 4 +N 50500 39500 50500 39300 4 +C 60300 33100 1 90 1 capacitor-1.sym +{ +T 60200 32800 5 10 1 1 0 0 1 +refdes=C240 +T 60200 32400 5 10 1 1 0 0 1 +value=1uF +T 60300 33100 5 10 0 1 0 6 1 +footprint=0603 +} +N 58300 33200 60100 33200 4 +N 60100 33200 60100 33100 4 +N 60100 32100 60100 32200 4 +C 60300 32100 1 180 0 generic-power.sym +{ +T 60100 31850 5 10 1 1 180 3 1 +net=AGND:1 +} diff --git a/usrp-hw/rfx/common900.sch b/usrp-hw/rfx/common900.sch new file mode 100644 index 000000000..92a964844 --- /dev/null +++ b/usrp-hw/rfx/common900.sch @@ -0,0 +1,535 @@ +v 20050820 1 +C 39500 25900 0 0 0 title-C.sym +C 52000 40600 1 0 1 BNC-1.sym +{ +T 52000 41400 5 10 1 1 0 6 1 +refdes=J200 +T 52000 40600 5 10 0 1 0 0 1 +footprint=SMA_VERT +} +C 52100 40300 1 180 0 generic-power.sym +{ +T 51900 40050 5 10 1 1 180 3 1 +net=AGND:1 +} +N 51900 40600 51900 40300 4 +C 44000 40500 1 180 0 capacitor-1.sym +{ +T 43700 40400 5 10 1 1 0 0 1 +refdes=C201 +T 44400 40100 5 10 1 1 0 6 1 +value=220pF +T 44000 40500 5 10 0 1 270 0 1 +footprint=0603 +} +C 42500 40900 1 180 1 capacitor-1.sym +{ +T 42900 40800 5 10 1 1 180 2 1 +refdes=C202 +T 42900 40500 5 10 1 1 180 2 1 +value=220pF +T 42500 40900 5 10 0 1 270 2 1 +footprint=0603 +} +C 43800 38400 1 180 1 generic-power.sym +{ +T 44000 38150 5 10 1 1 180 3 1 +net=AGND:1 +} +N 44000 40300 44500 40300 4 +N 44500 40700 43400 40700 4 +N 43100 40300 42000 40300 4 +{ +T 42100 40300 5 10 1 1 0 0 1 +netname=RF_TX +} +N 41200 30600 44800 30600 4 +{ +T 41500 30600 5 10 1 1 0 0 1 +netname=io_tx_06 +} +T 40300 26300 9 15 1 0 0 0 6 +Band +400 - 500 MHz +800 - 975 MHz +1.2 - 1.3 GHz +2.3 - 2.4 GHz +2.4 - 2.7 GHz +T 47100 26300 9 15 1 0 0 0 6 +Upconverter VCO +ADF4360-7 (Div by 2) +ADF4360-3 (Div by 2) +ADF4360-0 (Div by 2) +ADF4360-1 +ADF4360-0 +T 42900 26300 9 15 1 0 0 0 6 +Upconverter +AD8345 +AD8349 +AD8349 +AD8349 +AD8349 +T 44900 26300 9 15 1 0 0 0 6 +Downconverter +AD8348 +AD8347 +AD8347 +AD8347 +AD8347 +T 50300 26300 9 15 1 0 0 0 6 +Downconverter VCO +ADF4360-3 (Div by 2) +Same +Same +Same +Same +T 56600 26600 5 10 1 1 0 0 1 +date=$Date: 2006/03/10 05:27:22 $ +T 58500 26300 5 10 1 1 0 0 1 +rev=$Revision: 1.2 $ +T 58600 26000 5 10 1 1 0 0 1 +auth=$Author: matt $ +T 54400 26300 5 10 1 1 0 0 1 +fname=$Source: /opt/usrp-hw-cvs/usrp-hw/flex_xcvr/common900.sch,v $ +T 57800 27000 8 14 1 1 0 4 1 +title=Flex900 Common +T 55400 26000 9 10 1 0 0 0 1 +1 +T 56200 26000 9 10 1 0 0 0 1 +3 +C 44400 38200 1 0 0 hmc174ms8.sym +{ +T 45700 41800 5 10 1 1 0 6 1 +refdes=U202 +} +C 48800 40900 1 0 0 capacitor-1.sym +{ +T 49200 41000 5 10 1 1 180 0 1 +refdes=C204 +T 50100 41000 5 10 1 1 180 0 1 +value=NONE +T 48800 40900 5 10 0 1 270 8 1 +footprint=0603 +} +N 46500 41100 48800 41100 4 +N 44100 41500 44100 41100 4 +N 44100 41100 44500 41100 4 +N 44000 38400 44000 39100 4 +N 44000 39100 44500 39100 4 +N 44500 38700 44000 38700 4 +T 46400 38600 9 10 1 0 0 0 2 +B high selects RF1 +A high selects RF2 +C 40800 35100 1 0 0 BNC-1.sym +{ +T 40800 35900 5 10 1 1 0 0 1 +refdes=J202 +T 40800 35100 5 10 0 1 0 6 1 +footprint=SMA_VERT +} +C 40700 34800 1 180 1 generic-power.sym +{ +T 40900 34550 5 10 1 1 180 3 1 +net=AGND:1 +} +N 40900 35100 40900 34800 4 +C 43400 35800 1 180 1 capacitor-1.sym +{ +T 43800 35700 5 10 1 1 180 2 1 +refdes=C206 +T 43800 35400 5 10 1 1 180 2 1 +value=220pF +T 43400 35800 5 10 0 1 270 2 1 +footprint=0603 +} +C 43800 33700 1 180 1 generic-power.sym +{ +T 44000 33450 5 10 1 1 180 3 1 +net=AGND:1 +} +N 44500 36000 41800 36000 4 +C 44400 33500 1 0 0 hmc174ms8.sym +{ +T 45700 37100 5 10 1 1 0 6 1 +refdes=U209 +} +C 46900 36200 1 0 0 capacitor-1.sym +{ +T 47300 36300 5 10 1 1 180 0 1 +refdes=C205 +T 48200 36300 5 10 1 1 180 0 1 +value=220pF +T 46900 36200 5 10 0 1 270 8 1 +footprint=0603 +} +N 46500 36400 46900 36400 4 +N 44100 36800 44100 36400 4 +N 44100 36400 44500 36400 4 +N 44000 33700 44000 34400 4 +N 44000 34400 44500 34400 4 +N 44500 34000 44000 34000 4 +T 46400 33900 9 10 1 0 0 0 2 +B high selects RF1 +A high selects RF2 +T 50800 41700 9 30 1 0 0 0 1 +TX/RX +T 40400 35400 9 30 1 0 0 6 1 +RX +N 49200 36400 47800 36400 4 +{ +T 49000 36400 5 10 1 1 0 6 1 +netname=RF_RX +} +N 41300 35600 43400 35600 4 +N 42500 40700 41800 40700 4 +N 41800 36000 41800 40700 4 +N 44300 35600 44500 35600 4 +T 54600 35800 9 10 1 0 0 0 22 +A1 B1 A2 B2 +0 0 0 0 All Off + +0 1 0 0 TX Only +0 1 1 0 TX Only + +0 1 0 1 Full Duplex TX and RX + +0 0 0 1 RX from secondary RX port +1 0 0 1 RX from secondary RX port +1 0 1 0 RX from primary TX/RX port + +0 0 1 0 Nothing +1 0 0 0 Nothing + +0 0 1 1 BAD! +0 1 1 1 BAD! +1 0 1 1 BAD! +1 1 0 0 BAD! +1 1 0 1 BAD! +1 1 1 0 BAD! +1 1 1 1 BAD! +C 41100 31600 1 270 0 resistor-1.sym +{ +T 41400 31100 5 10 1 1 0 0 1 +value=10K +T 41100 31600 5 10 0 1 270 0 1 +footprint=0603 +T 41400 30900 5 10 1 1 0 0 1 +refdes=R250 +} +C 52700 33000 1 90 1 capacitor-1.sym +{ +T 52900 32900 5 10 1 1 0 6 1 +refdes=C200 +T 52600 32700 5 10 1 1 0 0 1 +value=220pF +T 52700 33000 5 10 0 1 0 6 1 +footprint=0603 +} +N 52500 31800 52500 32100 4 +C 55200 33000 1 270 0 capacitor-2.sym +{ +T 54900 32200 5 10 1 1 0 0 1 +refdes=C208 +T 54900 32000 5 10 1 1 0 0 1 +value=4.7uF +T 55200 33000 5 10 0 1 0 0 1 +footprint=1206 +} +C 55800 31500 1 0 0 adp3336.sym +{ +T 57700 33700 5 10 1 1 0 6 1 +refdes=U203 +} +N 57900 32400 58100 32400 4 +N 58100 32400 58100 33200 4 +N 58100 32800 57900 32800 4 +C 58100 33700 1 0 0 generic-power.sym +{ +T 58300 33950 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +N 57900 33200 58300 33200 4 +C 53000 33000 1 270 0 capacitor-1.sym +{ +T 52700 32200 5 10 1 1 0 0 1 +refdes=C203 +T 52700 32000 5 10 1 1 0 0 1 +value=0.1uF +T 53000 33000 5 10 0 1 0 0 1 +footprint=0603 +} +C 53900 33000 1 90 1 capacitor-1.sym +{ +T 54100 32200 5 10 1 1 0 6 1 +refdes=C207 +T 54100 32000 5 10 1 1 0 6 1 +value=1uF +T 53900 33000 5 10 0 1 0 6 1 +footprint=0603 +} +N 53700 31800 53700 32100 4 +N 53700 33000 53700 33300 4 +N 53200 31800 53200 32100 4 +N 53200 33000 53200 33300 4 +C 53800 33200 1 0 0 inductor-1.sym +{ +T 54000 33500 5 10 1 1 0 0 1 +refdes=L202 +T 53800 33200 5 10 0 1 0 0 1 +footprint=1206 +} +C 54600 33000 1 270 0 capacitor-1.sym +{ +T 54300 32200 5 10 1 1 0 0 1 +refdes=C209 +T 54300 32000 5 10 1 1 0 0 1 +value=0.1uF +T 54600 33000 5 10 0 1 0 0 1 +footprint=0603 +} +N 55400 31800 55400 32100 4 +N 55400 33000 55400 33300 4 +N 54800 31800 54800 32100 4 +N 54800 33000 54800 33300 4 +N 53200 31400 53200 31800 4 +N 54700 33300 55700 33300 4 +N 55700 32800 55900 32800 4 +N 55700 33200 55900 33200 4 +N 55700 32400 55900 32400 4 +N 55700 32400 55700 33300 4 +N 52500 31800 55700 31800 4 +N 55700 31800 55700 32000 4 +N 55700 32000 55900 32000 4 +C 58200 33000 1 270 0 resistor-1.sym +{ +T 58500 32600 5 10 1 1 180 8 1 +refdes=R201 +T 58200 33000 5 10 0 1 90 8 1 +footprint=0603 +T 58500 32400 5 10 1 1 0 0 1 +value=140K +} +C 58200 31900 1 270 0 resistor-1.sym +{ +T 58500 31500 5 10 1 1 180 8 1 +refdes=R202 +T 58200 31900 5 10 0 1 90 8 1 +footprint=0603 +T 58500 31300 5 10 1 1 0 0 1 +value=78.7K +} +N 58300 30900 58300 31000 4 +N 57900 32000 58300 32000 4 +N 58300 31900 58300 32100 4 +N 58300 33000 58300 33700 4 +C 59200 33100 1 90 1 capacitor-1.sym +{ +T 59100 32800 5 10 1 1 0 0 1 +refdes=C210 +T 59100 32400 5 10 1 1 0 0 1 +value=470pF +T 59200 33100 5 10 0 1 0 6 1 +footprint=0603 +} +N 58300 32000 59000 32000 4 +N 59000 32000 59000 32200 4 +N 59000 33200 59000 33100 4 +N 52500 33300 53800 33300 4 +C 53400 31400 1 180 0 generic-power.sym +{ +T 53200 31150 5 10 1 1 180 3 1 +net=AGND:1 +} +C 58500 30900 1 180 0 generic-power.sym +{ +T 58300 30650 5 10 1 1 180 3 1 +net=AGND:1 +} +C 52700 33600 1 0 1 generic-power.sym +{ +T 52500 33850 5 10 1 1 180 5 1 +net=6V_RX:1 +} +N 52500 33000 52500 33600 4 +C 43900 41500 1 0 0 generic-power.sym +{ +T 44100 41750 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +C 43900 36800 1 0 0 generic-power.sym +{ +T 44100 37050 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +C 44800 29500 1 0 0 7404-3.sym +{ +T 46300 31500 5 10 1 1 0 0 1 +refdes=U204 +T 45200 29300 5 10 1 1 0 0 1 +net=3_3V_SW:14 +T 45200 29100 5 10 1 1 0 0 1 +net=AGND:7 +T 44800 29500 5 10 0 1 0 0 1 +footprint=SO14 +} +N 46800 30600 48200 30600 4 +{ +T 47300 30600 5 10 1 1 0 0 1 +netname=TX +} +N 46800 30300 48200 30300 4 +{ +T 47300 30300 5 10 1 1 0 0 1 +netname=RX +} +N 46800 30000 48200 30000 4 +{ +T 47300 30000 5 10 1 1 0 0 1 +netname=RX1 +} +N 46800 29700 48200 29700 4 +{ +T 47300 29700 5 10 1 1 0 0 1 +netname=RX2 +} +N 43100 39500 44500 39500 4 +{ +T 43600 39500 5 10 1 1 0 0 1 +netname=TX +} +N 43100 39900 44500 39900 4 +{ +T 43600 39900 5 10 1 1 0 0 1 +netname=RX +} +N 43100 35200 44500 35200 4 +{ +T 43600 35200 5 10 1 1 0 0 1 +netname=RX1 +} +N 43100 34800 44500 34800 4 +{ +T 43600 34800 5 10 1 1 0 0 1 +netname=RX2 +} +N 41200 29700 44800 29700 4 +{ +T 41700 29700 5 10 1 1 0 0 1 +netname=RX1 +} +N 41200 30300 44800 30300 4 +{ +T 41700 30300 5 10 1 1 0 0 1 +netname=TX +} +N 41200 30600 41200 30700 4 +C 41000 32100 1 0 0 generic-power.sym +{ +T 41200 32350 5 10 1 1 0 3 1 +net=3_3V_SW:1 +} +N 41200 31600 41200 32100 4 +C 41000 31600 1 90 1 resistor-1.sym +{ +T 40700 31100 5 10 1 1 0 6 1 +value=10K +T 41000 31600 5 10 0 1 270 2 1 +footprint=0603 +T 40700 30900 5 10 1 1 0 6 1 +refdes=R249 +} +N 41200 31900 40900 31900 4 +N 40900 31900 40900 31600 4 +N 40900 30700 40900 30000 4 +N 40900 30000 44800 30000 4 +{ +T 41500 30000 5 10 1 1 0 0 1 +netname=io_rx_06 +} +T 53700 34400 9 25 1 0 0 0 1 +Always On +N 49700 41100 51500 41100 4 +C 60300 33100 1 90 1 capacitor-1.sym +{ +T 60200 32800 5 10 1 1 0 0 1 +refdes=C240 +T 60200 32400 5 10 1 1 0 0 1 +value=1uF +T 60300 33100 5 10 0 1 0 6 1 +footprint=0603 +} +N 58300 33200 60100 33200 4 +N 60100 33200 60100 33100 4 +N 60100 32100 60100 32200 4 +C 60300 32100 1 180 0 generic-power.sym +{ +T 60100 31850 5 10 1 1 180 3 1 +net=AGND:1 +} +C 49800 37100 1 180 0 generic-power.sym +{ +T 49600 36850 5 10 1 1 180 3 1 +net=AGND:1 +} +N 49600 37300 49600 37100 4 +N 49400 37300 49400 37200 4 +N 49400 37200 49600 37200 4 +N 51100 38000 50400 38000 4 +N 51100 38000 51100 41100 4 +N 46700 41100 46700 38000 4 +N 46700 38000 48500 38000 4 +N 44800 30900 43700 30900 4 +{ +T 43900 30900 5 10 1 1 0 0 1 +netname=io_rx_07 +} +C 42800 30800 1 0 0 resistor-1.sym +{ +T 42900 30600 5 10 1 1 180 8 1 +refdes=R262 +T 42800 30800 5 10 0 1 180 8 1 +footprint=0603 +T 43300 30600 5 10 1 1 0 0 1 +value=3.32K +} +C 42700 31300 1 180 1 resistor-1.sym +{ +T 42700 31500 5 10 1 1 0 2 1 +refdes=R261 +T 42700 31300 5 10 0 1 0 2 1 +footprint=0603 +T 43200 31500 5 10 1 1 180 6 1 +value=3.32K +} +N 44800 31200 43600 31200 4 +{ +T 43900 31200 5 10 1 1 0 0 1 +netname=io_tx_07 +} +N 42200 30900 42800 30900 4 +N 42700 31200 42200 31200 4 +N 46800 31200 48200 31200 4 +{ +T 47200 31200 5 10 1 1 0 0 1 +netname=TX_PUP +} +N 46800 30900 48200 30900 4 +{ +T 47200 30900 5 10 1 1 0 0 1 +netname=RX_PUP +} +C 42500 32000 1 180 1 generic-power.sym +{ +T 42700 31750 5 10 1 1 180 3 1 +net=AGND:1 +} +N 42200 30900 42200 32100 4 +N 42200 32100 42700 32100 4 +N 42700 32100 42700 32000 4 +C -1200 8400 1 0 0 saw0900-SAWTEK856327.sym +{ +T 50200 38500 5 10 1 1 0 6 1 +refdes=FIL1 +T 50300 38300 5 10 1 1 0 0 1 +value=FIL1 +} diff --git a/usrp-hw/rfx/rcv.sch b/usrp-hw/rfx/rcv.sch new file mode 100644 index 000000000..79273ff1b --- /dev/null +++ b/usrp-hw/rfx/rcv.sch @@ -0,0 +1,2099 @@ +v 20050820 1 +C 68100 43300 1 180 1 pmc64.sym +{ +T 68800 30100 5 10 1 1 0 2 1 +refdes=J1 +T 68100 43300 5 10 0 1 90 6 1 +footprint=PMC-REVERSE +} +C 68000 30400 1 90 0 generic-power.sym +{ +T 67750 30600 5 10 1 1 90 3 1 +net=AGND:1 +} +N 68000 30600 68200 30600 4 +N 69600 39400 70900 39400 4 +{ +T 69900 39400 5 10 1 1 0 0 1 +netname=I2C_A1_RX +} +N 69600 43000 69900 43000 4 +N 68200 43000 67600 43000 4 +C 69800 30800 1 270 0 generic-power.sym +{ +T 70050 30600 5 10 1 1 270 3 1 +net=AGND:1 +} +N 69800 30600 69600 30600 4 +N 68200 35800 68000 35800 4 +N 69600 35800 69800 35800 4 +C 68000 34800 1 90 0 generic-power.sym +{ +T 67750 35000 5 10 1 1 90 3 1 +net=AGND:1 +} +N 68000 35000 68200 35000 4 +C 69800 35200 1 270 0 generic-power.sym +{ +T 70050 35000 5 10 1 1 270 3 1 +net=AGND:1 +} +N 69800 35000 69600 35000 4 +C 67600 31600 1 90 0 generic-power.sym +{ +T 67350 31800 5 10 1 1 90 3 1 +net=AGND:1 +} +N 67600 31800 68200 31800 4 +C 68000 32400 1 90 0 generic-power.sym +{ +T 67750 32600 5 10 1 1 90 3 1 +net=AGND:1 +} +N 68000 32600 68200 32600 4 +C 67600 33600 1 90 0 generic-power.sym +{ +T 67350 33800 5 10 1 1 90 3 1 +net=AGND:1 +} +N 67600 33800 68200 33800 4 +N 67200 31000 68200 31000 4 +{ +T 67400 31000 5 10 1 1 0 0 1 +netname=VINP_A +} +N 67200 31400 68200 31400 4 +{ +T 67400 31400 5 10 1 1 0 0 1 +netname=VINN_A +} +N 67200 33400 68200 33400 4 +{ +T 67400 33400 5 10 1 1 0 0 1 +netname=VINP_B +} +N 67200 33000 68200 33000 4 +{ +T 67400 33000 5 10 1 1 0 0 1 +netname=VINN_B +} +C 69800 34000 1 270 0 generic-power.sym +{ +T 70050 33800 5 10 1 1 270 3 1 +net=AGND:1 +} +N 69800 33800 69600 33800 4 +C 70300 42800 1 270 0 generic-power.sym +{ +T 70550 42600 5 10 1 1 270 3 1 +net=6V_RX:1 +} +N 69600 42600 70300 42600 4 +N 69600 42200 70100 42200 4 +C 70100 41600 1 270 0 generic-power.sym +{ +T 70350 41400 5 10 1 1 270 3 1 +net=DVDD_RX:1 +} +N 69600 41400 70100 41400 4 +N 69600 41800 69900 41800 4 +N 70100 42200 70100 42600 4 +N 69900 41800 69900 41400 4 +N 66200 42200 68200 42200 4 +{ +T 66500 42200 5 10 1 1 0 0 1 +netname=io_rx_15 +} +N 66200 41800 68200 41800 4 +{ +T 66500 41800 5 10 1 1 0 0 1 +netname=io_rx_14 +} +N 66200 40600 68200 40600 4 +{ +T 66500 40600 5 10 1 1 0 0 1 +netname=io_rx_11 +} +N 66200 41400 68200 41400 4 +{ +T 66500 41400 5 10 1 1 0 0 1 +netname=io_rx_13 +} +N 66200 41000 68200 41000 4 +{ +T 66500 41000 5 10 1 1 0 0 1 +netname=io_rx_12 +} +N 66200 39400 68200 39400 4 +{ +T 66500 39400 5 10 1 1 0 0 1 +netname=io_rx_08 +} +N 66200 40200 68200 40200 4 +{ +T 66500 40200 5 10 1 1 0 0 1 +netname=io_rx_10 +} +N 66200 39800 68200 39800 4 +{ +T 66500 39800 5 10 1 1 0 0 1 +netname=io_rx_09 +} +N 66200 38200 68200 38200 4 +{ +T 66500 38200 5 10 1 1 0 0 1 +netname=io_rx_05 +} +N 66200 39000 68200 39000 4 +{ +T 66500 39000 5 10 1 1 0 0 1 +netname=io_rx_07 +} +N 66200 38600 68200 38600 4 +{ +T 66500 38600 5 10 1 1 0 0 1 +netname=io_rx_06 +} +N 66200 37000 68200 37000 4 +{ +T 66500 37000 5 10 1 1 0 0 1 +netname=io_rx_02 +} +N 66200 37800 68200 37800 4 +{ +T 66500 37800 5 10 1 1 0 0 1 +netname=io_rx_04 +} +N 66200 37400 68200 37400 4 +{ +T 66500 37400 5 10 1 1 0 0 1 +netname=io_rx_03 +} +N 66200 36200 68200 36200 4 +{ +T 66500 36200 5 10 1 1 0 0 1 +netname=io_rx_00 +} +N 66200 36600 68200 36600 4 +{ +T 66500 36600 5 10 1 1 0 0 1 +netname=io_rx_01 +} +C 65600 29400 0 0 0 title-bordered-D.sym +T 94500 30300 5 10 1 1 0 0 1 +date=$Date: 2006/01/09 23:17:04 $ +T 96400 30000 5 10 1 1 0 0 1 +rev=$Revision: 1.5 $ +T 96500 29700 5 10 1 1 0 0 1 +auth=$Author: matt $ +T 92300 30000 5 10 1 1 0 0 1 +fname=$Source: /opt/usrp-hw-cvs/usrp-hw/flex_xcvr/rcv.sch,v $ +T 95700 30700 8 14 1 1 0 4 1 +title=FlexRF Receiver +T 93300 29700 9 10 1 0 0 0 1 +2 +T 94100 29700 9 10 1 0 0 0 1 +3 +N 69600 40200 70700 40200 4 +{ +T 69900 40200 5 10 1 1 0 0 1 +netname=SCL_RX +} +N 69600 39800 70700 39800 4 +{ +T 69900 39800 5 10 1 1 0 0 1 +netname=SDA_RX +} +N 69600 33000 71300 33000 4 +{ +T 69800 33000 5 10 1 1 0 0 1 +netname=AUX_DAC_A_RX +} +C 83800 30600 1 0 0 24Cxx-1.sym +{ +T 84300 31800 5 10 1 1 0 0 1 +refdes=U1 +T 83800 30600 5 10 0 1 0 0 1 +footprint=SO8 +T 84100 30400 5 10 1 1 0 0 1 +device=24LC025B +T 84100 30000 5 10 1 1 0 0 1 +net=DGND_RX:4 +T 84100 30200 5 10 1 1 0 0 1 +net=DVDD_RX:8 +} +N 85100 30900 86500 30900 4 +{ +T 85300 30900 5 10 1 1 0 0 1 +netname=SCL_RX +} +N 85100 30700 86500 30700 4 +{ +T 85300 30700 5 10 1 1 0 0 1 +netname=SDA_RX +} +N 85100 31100 86000 31100 4 +N 69600 39000 70900 39000 4 +{ +T 69900 39000 5 10 1 1 0 0 1 +netname=I2C_A0_RX +} +N 82600 31100 83800 31100 4 +{ +T 82700 31100 5 10 1 1 0 0 1 +netname=I2C_A1_RX +} +N 82600 31300 83800 31300 4 +{ +T 82700 31300 5 10 1 1 0 0 1 +netname=I2C_A0_RX +} +C 82800 30700 1 90 0 generic-power.sym +{ +T 82550 30900 5 10 1 1 90 3 1 +net=DVDD_RX:1 +} +N 82800 30900 83800 30900 4 +N 72800 48700 73900 48700 4 +{ +T 73100 48700 5 10 1 1 0 0 1 +netname=RF_RX +} +C 91300 40300 1 0 0 adf4360-ANLG.sym +{ +T 92600 43200 5 10 1 1 0 6 1 +refdes=U3 +} +C 86600 35800 1 0 0 adf4360-DIG.sym +{ +T 87800 38300 5 10 1 1 0 6 1 +refdes=U3 +} +C 89000 34600 1 270 0 adf4360-PWR.sym +{ +T 89600 34300 5 10 1 1 0 6 1 +refdes=U3 +} +C 90700 31900 1 180 0 generic-power.sym +{ +T 90500 31650 5 10 1 1 180 3 1 +net=AGND:1 +} +C 90900 35200 1 0 0 generic-power.sym +{ +T 91100 35450 5 10 1 1 180 5 1 +net=3_3V_SYN_RX:1 +} +N 89500 32500 89500 32200 4 +N 91500 32200 91500 32500 4 +N 91100 32200 91100 32500 4 +N 90700 32200 90700 32500 4 +N 90300 32200 90300 32500 4 +N 89900 32200 89900 32500 4 +N 90500 31900 90500 32200 4 +C 94300 31900 1 180 0 generic-power.sym +{ +T 94100 31650 5 10 1 1 180 3 1 +net=AGND:1 +} +N 95100 32200 95100 32500 4 +N 94700 32200 94700 32500 4 +N 94300 32200 94300 32500 4 +N 93900 32200 93900 32500 4 +N 94100 31900 94100 32200 4 +C 98600 34000 1 90 1 capacitor-1.sym +{ +T 98500 33800 5 10 1 1 180 6 1 +refdes=C57 +T 98500 33400 5 10 1 1 180 6 1 +value=1000pF +T 98600 34000 5 10 0 1 180 2 1 +footprint=0603 +} +C 97100 34000 1 90 1 capacitor-1.sym +{ +T 97000 33800 5 10 1 1 180 6 1 +refdes=C58 +T 97000 33400 5 10 1 1 180 6 1 +value=1000pF +T 97100 34000 5 10 0 1 180 2 1 +footprint=0603 +} +C 96300 34000 1 90 1 capacitor-1.sym +{ +T 96200 33800 5 10 1 1 180 6 1 +refdes=C59 +T 96200 33400 5 10 1 1 180 6 1 +value=.01uF +T 96300 34000 5 10 0 1 180 2 1 +footprint=0603 +} +C 97900 34000 1 90 1 capacitor-1.sym +{ +T 97800 33800 5 10 1 1 180 6 1 +refdes=C60 +T 97800 33400 5 10 1 1 180 6 1 +value=.01uF +T 97900 34000 5 10 0 1 180 2 1 +footprint=0603 +} +N 93900 32200 98400 32200 4 +N 98400 32200 98400 33100 4 +N 97700 32200 97700 33100 4 +N 96900 32200 96900 33100 4 +N 96100 32200 96100 33100 4 +N 98400 34000 98400 35100 4 +N 98400 35100 94300 35100 4 +N 94300 35100 94300 34500 4 +N 94700 35100 94700 34500 4 +N 95100 35100 95100 34500 4 +N 96100 34000 96100 35100 4 +N 96900 34000 96900 35100 4 +N 97700 34000 97700 35100 4 +N 91500 34500 91500 34800 4 +N 90700 34800 90700 34500 4 +N 91100 34500 91100 34800 4 +N 91100 34800 91100 35200 4 +C 87600 34000 1 90 1 capacitor-1.sym +{ +T 87500 33800 5 10 1 1 180 6 1 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/dev/null +++ b/usrp-hw/tvrx/ChangeLog diff --git a/usrp-hw/tvrx/gnetlistrc b/usrp-hw/tvrx/gnetlistrc new file mode 100644 index 000000000..6bbd9c292 --- /dev/null +++ b/usrp-hw/tvrx/gnetlistrc @@ -0,0 +1,3 @@ +(component-library "../sym") +(component-library "../sym/generated") + diff --git a/usrp-hw/tvrx/gschemrc b/usrp-hw/tvrx/gschemrc new file mode 100644 index 000000000..6bbd9c292 --- /dev/null +++ b/usrp-hw/tvrx/gschemrc @@ -0,0 +1,3 @@ +(component-library "../sym") +(component-library "../sym/generated") + diff --git a/usrp-hw/tvrx/netlist_cmd b/usrp-hw/tvrx/netlist_cmd new file mode 100755 index 000000000..c22fad425 --- /dev/null +++ b/usrp-hw/tvrx/netlist_cmd @@ -0,0 +1,3 @@ +gsch2pcb tvrx.prj +gnetlist -g partslist3 -o tvrx.bom tvrx.sch + diff --git a/usrp-hw/tvrx/tvrx.pcb b/usrp-hw/tvrx/tvrx.pcb new file mode 100644 index 000000000..58f7cf27b --- /dev/null +++ b/usrp-hw/tvrx/tvrx.pcb @@ -0,0 +1,2270 @@ +# release: pcb-bin 1.99p +# date: Mon Feb 28 17:13:08 2005 +# user: matt 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2000 3500 800] +) +Symbol['V' 1200] +( + SymbolLine[0 0 0 3000 800] + SymbolLine[0 3000 1000 4000 800] + SymbolLine[1000 4000 2000 3000 800] + SymbolLine[2000 0 2000 3000 800] +) +Symbol['W' 1200] +( + SymbolLine[0 0 0 4000 800] + SymbolLine[0 4000 1500 2500 800] + SymbolLine[1500 2500 3000 4000 800] + SymbolLine[3000 0 3000 4000 800] +) +Symbol['X' 1200] +( + SymbolLine[0 0 0 500 800] + SymbolLine[0 500 2500 3000 800] + SymbolLine[2500 3000 2500 4000 800] + SymbolLine[0 3000 0 4000 800] + SymbolLine[0 3000 2500 500 800] + SymbolLine[2500 0 2500 500 800] +) +Symbol['Y' 1200] +( + SymbolLine[0 0 0 500 800] + SymbolLine[0 500 1000 1500 800] + SymbolLine[1000 1500 2000 500 800] + SymbolLine[2000 0 2000 500 800] + SymbolLine[1000 1500 1000 4000 800] +) +Symbol['Z' 1200] +( + SymbolLine[0 0 2500 0 800] + SymbolLine[2500 0 2500 500 800] + SymbolLine[0 3000 2500 500 800] + SymbolLine[0 3000 0 4000 800] + SymbolLine[0 4000 2500 4000 800] +) +Symbol['[' 1200] +( + SymbolLine[0 0 500 0 800] + SymbolLine[0 0 0 4000 800] + SymbolLine[0 4000 500 4000 800] +) +Symbol['\' 1200] +( + SymbolLine[0 500 3000 3500 800] +) +Symbol[']' 1200] +( + SymbolLine[0 0 500 0 800] + SymbolLine[500 0 500 4000 800] + SymbolLine[0 4000 500 4000 800] +) +Symbol['^' 1200] +( + SymbolLine[0 500 500 0 800] + SymbolLine[500 0 1000 500 800] +) +Symbol['_' 1200] +( + SymbolLine[0 4000 2000 4000 800] +) +Symbol['a' 1200] +( + SymbolLine[1500 2000 2000 2500 800] + SymbolLine[500 2000 1500 2000 800] + SymbolLine[0 2500 500 2000 800] + SymbolLine[0 2500 0 3500 800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[2000 2000 2000 3500 800] + SymbolLine[2000 3500 2500 4000 800] + SymbolLine[500 4000 1500 4000 800] + SymbolLine[1500 4000 2000 3500 800] +) +Symbol['b' 1200] +( + SymbolLine[0 0 0 4000 800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[500 4000 1500 4000 800] + SymbolLine[1500 4000 2000 3500 800] + SymbolLine[2000 2500 2000 3500 800] + SymbolLine[1500 2000 2000 2500 800] + SymbolLine[500 2000 1500 2000 800] + SymbolLine[0 2500 500 2000 800] +) +Symbol['c' 1200] +( + SymbolLine[500 2000 2000 2000 800] + SymbolLine[0 2500 500 2000 800] + SymbolLine[0 2500 0 3500 800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[500 4000 2000 4000 800] +) +Symbol['d' 1200] +( + SymbolLine[2000 0 2000 4000 800] + SymbolLine[1500 4000 2000 3500 800] + SymbolLine[500 4000 1500 4000 800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[0 2500 0 3500 800] + SymbolLine[0 2500 500 2000 800] + SymbolLine[500 2000 1500 2000 800] + SymbolLine[1500 2000 2000 2500 800] +) +Symbol['e' 1200] +( + SymbolLine[500 4000 2000 4000 800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[0 2500 0 3500 800] + SymbolLine[0 2500 500 2000 800] + SymbolLine[500 2000 1500 2000 800] + SymbolLine[1500 2000 2000 2500 800] + SymbolLine[0 3000 2000 3000 800] + SymbolLine[2000 3000 2000 2500 800] +) +Symbol['f' 1000] +( + SymbolLine[500 500 500 4000 800] + SymbolLine[500 500 1000 0 800] + SymbolLine[1000 0 1500 0 800] + SymbolLine[0 2000 1000 2000 800] +) +Symbol['g' 1200] +( + SymbolLine[1500 2000 2000 2500 800] + SymbolLine[500 2000 1500 2000 800] + SymbolLine[0 2500 500 2000 800] + SymbolLine[0 2500 0 3500 800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[500 4000 1500 4000 800] + SymbolLine[1500 4000 2000 3500 800] + SymbolLine[0 5000 500 5500 800] + SymbolLine[500 5500 1500 5500 800] + SymbolLine[1500 5500 2000 5000 800] + SymbolLine[2000 2000 2000 5000 800] +) +Symbol['h' 1200] +( + SymbolLine[0 0 0 4000 800] + SymbolLine[0 2500 500 2000 800] + SymbolLine[500 2000 1500 2000 800] + SymbolLine[1500 2000 2000 2500 800] + SymbolLine[2000 2500 2000 4000 800] +) +Symbol['i' 1000] +( + SymbolLine[0 1000 0 1500 800] + SymbolLine[0 2500 0 4000 800] +) +Symbol['j' 1000] +( + SymbolLine[500 1000 500 1500 800] + SymbolLine[500 2500 500 5000 800] + SymbolLine[0 5500 500 5000 800] +) +Symbol['k' 1200] +( + SymbolLine[0 0 0 4000 800] + SymbolLine[0 2500 1500 4000 800] + SymbolLine[0 2500 1000 1500 800] +) +Symbol['l' 1000] +( + SymbolLine[0 0 0 3500 800] + SymbolLine[0 3500 500 4000 800] +) +Symbol['m' 1200] +( + SymbolLine[500 2500 500 4000 800] + SymbolLine[500 2500 1000 2000 800] + SymbolLine[1000 2000 1500 2000 800] + SymbolLine[1500 2000 2000 2500 800] + SymbolLine[2000 2500 2000 4000 800] + SymbolLine[2000 2500 2500 2000 800] + SymbolLine[2500 2000 3000 2000 800] + SymbolLine[3000 2000 3500 2500 800] + SymbolLine[3500 2500 3500 4000 800] + SymbolLine[0 2000 500 2500 800] +) +Symbol['n' 1200] +( + SymbolLine[500 2500 500 4000 800] + SymbolLine[500 2500 1000 2000 800] + SymbolLine[1000 2000 1500 2000 800] + SymbolLine[1500 2000 2000 2500 800] + SymbolLine[2000 2500 2000 4000 800] + SymbolLine[0 2000 500 2500 800] +) +Symbol['o' 1200] +( + SymbolLine[0 2500 0 3500 800] + SymbolLine[0 2500 500 2000 800] + SymbolLine[500 2000 1500 2000 800] + SymbolLine[1500 2000 2000 2500 800] + SymbolLine[2000 2500 2000 3500 800] + SymbolLine[1500 4000 2000 3500 800] + SymbolLine[500 4000 1500 4000 800] + SymbolLine[0 3500 500 4000 800] +) +Symbol['p' 1200] +( + SymbolLine[500 2500 500 5500 800] + SymbolLine[0 2000 500 2500 800] + SymbolLine[500 2500 1000 2000 800] + SymbolLine[1000 2000 2000 2000 800] + SymbolLine[2000 2000 2500 2500 800] + SymbolLine[2500 2500 2500 3500 800] + SymbolLine[2000 4000 2500 3500 800] + SymbolLine[1000 4000 2000 4000 800] + SymbolLine[500 3500 1000 4000 800] +) +Symbol['q' 1200] +( + SymbolLine[2000 2500 2000 5500 800] + SymbolLine[1500 2000 2000 2500 800] + SymbolLine[500 2000 1500 2000 800] + SymbolLine[0 2500 500 2000 800] + SymbolLine[0 2500 0 3500 800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[500 4000 1500 4000 800] + SymbolLine[1500 4000 2000 3500 800] +) +Symbol['r' 1200] +( + SymbolLine[500 2500 500 4000 800] + SymbolLine[500 2500 1000 2000 800] + SymbolLine[1000 2000 2000 2000 800] + SymbolLine[0 2000 500 2500 800] +) +Symbol['s' 1200] +( + SymbolLine[500 4000 2000 4000 800] + SymbolLine[2000 4000 2500 3500 800] + SymbolLine[2000 3000 2500 3500 800] + SymbolLine[500 3000 2000 3000 800] + SymbolLine[0 2500 500 3000 800] + SymbolLine[0 2500 500 2000 800] + SymbolLine[500 2000 2000 2000 800] + SymbolLine[2000 2000 2500 2500 800] + SymbolLine[0 3500 500 4000 800] +) +Symbol['t' 1000] +( + SymbolLine[500 0 500 3500 800] + SymbolLine[500 3500 1000 4000 800] + SymbolLine[0 1500 1000 1500 800] +) +Symbol['u' 1200] +( + SymbolLine[0 2000 0 3500 800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[500 4000 1500 4000 800] + SymbolLine[1500 4000 2000 3500 800] + SymbolLine[2000 2000 2000 3500 800] +) +Symbol['v' 1200] +( + SymbolLine[0 2000 0 3000 800] + SymbolLine[0 3000 1000 4000 800] + SymbolLine[1000 4000 2000 3000 800] + SymbolLine[2000 2000 2000 3000 800] +) +Symbol['w' 1200] +( + SymbolLine[0 2000 0 3500 800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[500 4000 1000 4000 800] + SymbolLine[1000 4000 1500 3500 800] + SymbolLine[1500 2000 1500 3500 800] + SymbolLine[1500 3500 2000 4000 800] + SymbolLine[2000 4000 2500 4000 800] + SymbolLine[2500 4000 3000 3500 800] + SymbolLine[3000 2000 3000 3500 800] +) +Symbol['x' 1200] +( + SymbolLine[0 2000 2000 4000 800] + SymbolLine[0 4000 2000 2000 800] +) +Symbol['y' 1200] +( + SymbolLine[0 2000 0 3500 800] + SymbolLine[0 3500 500 4000 800] + SymbolLine[2000 2000 2000 5000 800] + SymbolLine[1500 5500 2000 5000 800] + SymbolLine[500 5500 1500 5500 800] + SymbolLine[0 5000 500 5500 800] + SymbolLine[500 4000 1500 4000 800] + SymbolLine[1500 4000 2000 3500 800] +) +Symbol['z' 1200] +( + SymbolLine[0 2000 2000 2000 800] + SymbolLine[0 4000 2000 2000 800] + SymbolLine[0 4000 2000 4000 800] +) +Symbol['{' 1200] +( + SymbolLine[500 500 1000 0 800] + SymbolLine[500 500 500 1500 800] + SymbolLine[0 2000 500 1500 800] + SymbolLine[0 2000 500 2500 800] + SymbolLine[500 2500 500 3500 800] + SymbolLine[500 3500 1000 4000 800] +) +Symbol['|' 1200] +( + SymbolLine[0 0 0 4000 800] +) +Symbol['}' 1200] +( + SymbolLine[0 0 500 500 800] + SymbolLine[500 500 500 1500 800] + SymbolLine[500 1500 1000 2000 800] + SymbolLine[500 2500 1000 2000 800] + SymbolLine[500 2500 500 3500 800] + SymbolLine[0 4000 500 3500 800] +) +Symbol['~' 1200] +( + SymbolLine[0 2500 500 2000 800] + SymbolLine[500 2000 1000 2000 800] + SymbolLine[1000 2000 1500 2500 800] + SymbolLine[1500 2500 2000 2500 800] + SymbolLine[2000 2500 2500 2000 800] +) +Via[70000 235000 13200 2000 11000 12800 "" 0x0800000a] +Via[315000 235000 13200 2000 11000 12800 "" 0x0800000a] +Via[315000 15000 13200 2000 11000 12800 "" 0x0800000a] +Via[213000 120500 4500 1600 0 2000 "" 0x08000002] +Via[232500 79500 6000 2000 0 2800 "" 0x08080002] +Via[217000 83000 4500 1600 0 2000 "" 0x08000002] +Via[221000 127500 4500 1600 0 2000 "" 0x08000002] +Via[213000 74500 4500 1600 0 2000 "" 0x08000002] +Via[79500 191000 6000 2000 0 3500 "" 0x08080002] +Via[222000 72500 6000 2000 0 3500 "" 0x08080002] +Via[101500 231000 4000 2000 0 2000 "" 0x08080002] +Via[248500 83000 4000 2000 0 2000 "" 0x08080002] +Via[279000 92500 6000 2000 0 3500 "" 0x08080002] +Via[262500 156500 4000 2000 0 2000 "" 0x08080002] +Via[241500 167500 4000 2000 0 2000 "" 0x08080002] +Via[191000 164500 4000 2000 0 2000 "" 0x08080002] +Via[208500 135000 4000 2000 0 2000 "" 0x08080002] +Via[141500 91000 6000 2000 0 3500 "" 0x08080002] +Via[160000 133000 6000 2000 0 3500 "" 0x08080002] +Via[187500 153500 4000 2000 0 2000 "" 0x08080002] +Via[288500 188500 6000 2000 0 3500 "" 0x08080002] +Via[136541 161000 6000 2000 0 3500 "" 0x08000002] +Via[227500 145000 4000 2000 0 2000 "" 0x08000002] +Via[173000 129000 4000 2000 0 2000 "" 0x08000002] +Via[194500 135000 4000 2000 0 2000 "" 0x08000002] +Via[176000 228500 4000 2000 0 2000 "" 0x08000002] +Via[197000 220500 4000 2000 0 2000 "" 0x08000002] +Via[148000 233000 6000 2000 0 2800 "" 0x08000002] +Via[139500 151000 6000 2000 0 2800 "" 0x08000002] +Via[145000 169500 6000 2000 0 3500 "" 0x08000002] +Via[172500 187500 6000 2000 0 3500 "" 0x08080002] +Via[79500 82500 3600 2000 0 2000 "" 0x09000002] +Via[57000 163500 3600 2000 0 2000 "" 0x09090002] +Via[57000 145500 3600 2000 0 2000 "" 0x09090002] +Via[57000 127500 3600 2000 0 2000 "" 0x09090002] +Via[56500 109500 3600 2000 0 2000 "" 0x09090002] +Via[57000 96500 3600 2000 0 2000 "" 0x09090002] +Via[56500 76000 3600 2000 0 2000 "" 0x09090002] +Via[72500 75000 3600 2000 0 2000 "" 0x09090002] +Via[87000 74500 3600 2000 0 2000 "" 0x09090002] +Via[104000 72500 3600 2000 0 2000 "" 0x09090002] +Via[100500 105000 3600 2000 0 2000 "" 0x09090002] +Via[57000 58000 3600 2000 0 2000 "" 0x09000002] +Via[63000 47500 3600 2000 0 2000 "" 0x09000002] +Via[238500 177000 6000 2000 0 3500 "" 0x08000002] + +Element[0x00000080 "0603" "R6" "1.6K" 104000 219000 -3000 10000 0 100 0x00000080] +( + Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" 0x00000180] + Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" 0x00000180] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element[0x00000080 "0603" "R9" "10K" 203400 150500 -11400 1800 0 100 0x00000080] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element[0x00000080 "0603" "R10" "0" 270500 69500 -2000 -15500 1 100 0x00000080] +( + Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" 0x00000180] + Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" 0x00000180] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element[0x00000080 "0603" "R17" "0" 263500 69000 -2200 -15500 1 100 0x00000080] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" 0x00000180] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element[0x00000080 "0603" "C3" ".1uF" 254500 158500 7500 2700 0 100 0x00000080] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element[0x00000000 "MT4937DI5" "U2" "unknown" 312500 202000 -8000 13500 0 100 0x00000000] +( + Pin[-297800 -700 7500 2000 8100 5000 "" "18" 0x08004001] + Pin[-280300 -700 7500 2000 8100 5000 "" "17" 0x08004001] + Pin[-262800 -700 7500 2000 8100 5000 "" "16" 0x08004001] + Pin[-245300 -700 7500 2000 8100 5000 "" "15" 0x08004001] + Pin[-227800 -700 7500 2000 8100 5000 "" "14" 0x08004001] + Pin[-210300 -700 7500 2000 8100 5000 "" "13" 0x08004001] + Pin[-192800 -700 7500 2000 8100 5000 "" "12" 0x08004001] + Pin[-175300 -700 7500 2000 8100 5000 "" "11" 0x08004001] + Pin[-157800 -700 7500 2000 8100 5000 "" "10" 0x08004001] + Pin[-140300 -700 7500 2000 8100 5000 "" "9" 0x08004001] + Pin[-122800 -700 7500 2000 8100 5000 "" "8" 0x08004001] + Pin[-105300 -700 7500 2000 8100 5000 "" "7" 0x08004001] + Pin[-87800 -700 7500 2000 8100 5000 "" "6" 0x08004001] + Pin[-70300 -700 7500 2000 8100 5000 "" "5" 0x08084001] + Pin[-52800 -700 7500 2000 8100 5000 "" "4" 0x08004001] + Pin[-35300 -700 7500 2000 8100 5000 "" "3" 0x08004001] + Pin[-17800 -700 7500 2000 8100 5000 "" "2" 0x08004001] + Pin[-300 -700 7500 2000 8100 5000 "" "1" 0x08004001] + Pin[-303400 -10900 14000 2000 14600 11000 "" "21" 0x08004001] + Pin[-303400 -147500 21000 2000 21600 11000 "" "22" 0x08084001] + Pin[5300 -147500 21000 2000 21600 11000 "" "23" 0x08084001] + Pin[5300 -10900 14000 2000 14600 11000 "" "24" 0x08004001] + ElementLine [-312200 9000 -312200 11400 1500] + ElementLine [-311600 11300 14400 11300 1500] + ElementLine [14400 -156600 14400 11300 1500] + ElementLine [14700 -156900 14400 -156600 1500] + ElementLine [14400 -157200 14700 -156900 1500] + ElementLine [-312200 -157200 14400 -157200 1500] + ElementLine [-312200 -157200 -312200 9200 1500] + + ) + +Element[0x00000080 "SO8" "U1" "unknown" 187500 128500 -3000 -4000 0 100 0x00000080] +( + Pad[-900 0 1900 0 2000 3000 2000 "1" "1" 0x00004080] + Pad[-900 5000 1900 5000 2000 3000 2000 "2" "2" 0x00004180] + Pad[-900 10000 1900 10000 2000 3000 2000 "3" "3" 0x00004180] + Pad[-900 15000 1900 15000 2000 3000 2000 "4" "4" 0x00004180] + Pad[-21300 15000 -18500 15000 2000 3000 2000 "5" "5" 0x00000180] + Pad[-21300 10000 -18500 10000 2000 3000 2000 "6" "6" 0x00000180] + Pad[-21300 5000 -18500 5000 2000 3000 2000 "7" "7" 0x00000180] + Pad[-21300 0 -18500 0 2000 3000 2000 "8" "8" 0x00000180] + ElementLine [2900 17500 2900 -2500 1000] + ElementLine [-22300 17500 2900 17500 1000] + ElementLine [-22300 17500 -22300 -2500 1000] + ElementLine [-22300 -2500 -7200 -2500 1000] + ElementLine [-12200 -2500 2900 -2500 1000] + ElementArc [-9700 -2500 2500 2500 0 180 1000] + + ) + +Element[0x00000080 "0603" "C1" ".1uF" 270500 79000 5000 -2300 0 100 0x00000080] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000000 "CONNECTOR-8-2" "J24" "unknown" 184500 23500 -16200 -7100 0 100 0x00000000] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" 0x08004101] + Pin[0 -10000 6000 3000 6600 4000 "2" "2" 0x080a4001] + Pin[10000 0 6000 3000 6600 4000 "3" "3" 0x08004001] + Pin[10000 -10000 6000 3000 6600 4000 "4" "4" 0x080a4001] + Pin[20000 0 6000 3000 6600 4000 "5" "5" 0x08004001] + Pin[20000 -10000 6000 3000 6600 4000 "6" "6" 0x080a4001] + Pin[30000 0 6000 3000 6600 4000 "7" "7" 0x08004001] + Pin[30000 -10000 6000 3000 6600 4000 "8" "8" 0x080a4001] + Pin[40000 0 6000 3000 6600 4000 "9" "9" 0x08004001] + Pin[40000 -10000 6000 3000 6600 4000 "10" "10" 0x080a4001] + Pin[50000 0 6000 3000 6600 4000 "11" "11" 0x08004001] + Pin[50000 -10000 6000 3000 6600 4000 "12" "12" 0x080a4001] + Pin[60000 0 6000 3000 6600 4000 "13" "13" 0x08004001] + Pin[60000 -10000 6000 3000 6600 4000 "14" "14" 0x080a4001] + Pin[70000 0 6000 3000 6600 4000 "15" "15" 0x08004001] + Pin[70000 -10000 6000 3000 6600 4000 "16" "16" 0x080a4001] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [-5000 -15000 75000 -15000 2000] + ElementLine [75000 -15000 75000 5000 2000] + ElementLine [-5000 5000 75000 5000 2000] + + ) + +Element[0x00000080 "0603" "C2" ".1uF" 263500 79000 -10500 -3300 0 100 0x00000080] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000080 "0603" "R4" "2.2K" 140500 219500 -3500 9700 0 100 0x00000080] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000080 "SOT23" "Q1" "unknown" 163000 228500 -6000 8800 0 100 0x00000080] +( + Pad[0 -300 0 300 3400 3000 4000 "1" "1" 0x00004180] + Pad[-7800 -300 -7800 300 3400 3000 4000 "2" "2" 0x00004180] + Pad[-3900 -8500 -3900 -7900 3400 3000 4000 "3" "3" 0x00000180] + ElementLine [-10300 -11000 2500 -11000 1000] + ElementLine [-10300 2900 -10300 -11000 1000] + ElementLine [-10300 2900 2500 2900 1000] + ElementLine [2500 2900 2500 -11000 1000] + + ) + +Element[0x00000080 "0603" "R1" "NONE" 148000 224500 -3000 9700 0 100 0x00000080] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000080 "0603" "R2" "2.2K" 171000 218000 -4000 9700 0 100 0x00000080] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000080 "0603" "C5" "10pF" 279000 82000 6000 2200 0 100 0x00000080] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [4200 2700 -4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 2700 -4200 -2700 600] + + ) + +Element[0x00000080 "0603" "C6" "10pF" 255000 82000 -12000 2200 0 100 0x00000080] +( + Pad[2400 -900 2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[-2400 -900 -2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + + ) + +Element[0x00000000 "CONNECTOR-8-2" "J25" "unknown" 89000 24000 -15800 -5600 0 100 0x00000000] +( + Pin[0 0 6000 3000 6600 4000 "1" "1" 0x08004101] + Pin[0 -10000 6000 3000 6600 4000 "2" "2" 0x080a4001] + Pin[10000 0 6000 3000 6600 4000 "3" "3" 0x08004001] + Pin[10000 -10000 6000 3000 6600 4000 "4" "4" 0x080a4001] + Pin[20000 0 6000 3000 6600 4000 "5" "5" 0x08004001] + Pin[20000 -10000 6000 3000 6600 4000 "6" "6" 0x080a4001] + Pin[30000 0 6000 3000 6600 4000 "7" "7" 0x08004001] + Pin[30000 -10000 6000 3000 6600 4000 "8" "8" 0x080a4001] + Pin[40000 0 6000 3000 6600 4000 "9" "9" 0x08004001] + Pin[40000 -10000 6000 3000 6600 4000 "10" "10" 0x080a4001] + Pin[50000 0 6000 3000 6600 4000 "11" "11" 0x08004001] + Pin[50000 -10000 6000 3000 6600 4000 "12" "12" 0x080a4001] + Pin[60000 0 6000 3000 6600 4000 "13" "13" 0x08004001] + Pin[60000 -10000 6000 3000 6600 4000 "14" "14" 0x080a4001] + Pin[70000 0 6000 3000 6600 4000 "15" "15" 0x08004001] + Pin[70000 -10000 6000 3000 6600 4000 "16" "16" 0x080a4001] + ElementLine [-5000 -5000 5000 -5000 1000] + ElementLine [5000 -5000 5000 5000 1000] + ElementLine [-5000 -15000 -5000 5000 2000] + ElementLine [-5000 -15000 75000 -15000 2000] + ElementLine [75000 -15000 75000 5000 2000] + ElementLine [-5000 5000 75000 5000 2000] + + ) + +Element[0x00000080 "PMC-REVERSE" "J2" "unknown" 149993 95811 -18000 9000 0 100 0x00000080] +( + Pin[-6693 7189 7200 2000 7200 5800 "" "1" 0x08004009] + Pin[128740 7189 7200 2000 7200 5800 "" "2" 0x08004009] + Pad[0 9900 0 19000 2400 1000 3400 "" "1" 0x00004080] + Pad[122047 -4622 122047 4478 2400 1000 3400 "" "64" 0x00000080] + Pad[7874 9900 7874 19000 2400 1000 3400 "" "5" 0x00004080] + Pad[3937 9900 3937 19000 2400 1000 3400 "" "3" 0x00004080] + Pad[11811 9900 11811 19000 2400 1000 3400 "" "7" 0x00004080] + Pad[0 -4622 0 4478 2400 1000 3400 "" "2" 0x00000080] + Pad[15748 9900 15748 19000 2400 1000 3400 "" "9" 0x00004080] + Pad[7874 -4622 7874 4478 2400 1000 3400 "" "6" 0x00000080] + Pad[19685 9900 19685 19000 2400 1000 3400 "" "11" 0x00004080] + Pad[11811 -4622 11811 4478 2400 1000 3400 "" "8" 0x00000080] + Pad[23622 9900 23622 19000 2400 1000 3400 "" "13" 0x00004080] + Pad[15748 -4622 15748 4478 2400 1000 3400 "" "10" 0x00000080] + Pad[27559 9900 27559 19000 2400 1000 3400 "" "15" 0x00004080] + Pad[19685 -4622 19685 4478 2400 1000 3400 "" "12" 0x00000080] + Pad[31496 9900 31496 19000 2400 1000 3400 "" "17" 0x00004080] + Pad[23622 -4622 23622 4478 2400 1000 3400 "" "14" 0x00000080] + Pad[35433 9900 35433 19000 2400 1000 3400 "" "19" 0x00004080] + Pad[27559 -4622 27559 4478 2400 1000 3400 "" "16" 0x00000080] + Pad[39370 9900 39370 19000 2400 1000 3400 "" "21" 0x00004080] + Pad[31496 -4622 31496 4478 2400 1000 3400 "" "18" 0x00000080] + Pad[35433 -4622 35433 4478 2400 1000 3400 "" "20" 0x00000080] + Pad[39370 -4622 39370 4478 2400 1000 3400 "" "22" 0x00000080] + Pad[43307 -4622 43307 4478 2400 1000 3400 "" "24" 0x00000080] + Pad[47244 -4622 47244 4478 2400 1000 3400 "" "26" 0x00000080] + Pad[51181 -4622 51181 4478 2400 1000 3400 "" "28" 0x00000080] + Pad[55118 -4622 55118 4478 2400 1000 3400 "" "30" 0x00000080] + Pad[59055 -4622 59055 4478 2400 1000 3400 "" "32" 0x00000080] + Pad[62992 -4622 62992 4478 2400 1000 3400 "" "34" 0x00000080] + Pad[66929 -4622 66929 4478 2400 1000 3400 "" "36" 0x00000080] + Pad[70866 -4622 70866 4478 2400 1000 3400 "" "38" 0x00000080] + Pad[74803 -4622 74803 4478 2400 1000 3400 "" "40" 0x00000080] + Pad[78740 -4622 78740 4478 2400 1000 3400 "" "42" 0x00000080] + Pad[82677 -4622 82677 4478 2400 1000 3400 "" "44" 0x00000080] + Pad[86614 -4622 86614 4478 2400 1000 3400 "" "46" 0x00000080] + Pad[90551 -4622 90551 4478 2400 1000 3400 "" "48" 0x00000080] + Pad[98425 -4622 98425 4478 2400 1000 3400 "" "52" 0x00000080] + Pad[94488 -4622 94488 4478 2400 1000 3400 "" "50" 0x00000080] + Pad[102362 -4622 102362 4478 2400 1000 3400 "" "54" 0x00000080] + Pad[106299 -4622 106299 4478 2400 1000 3400 "" "56" 0x00000080] + Pad[110236 -4622 110236 4478 2400 1000 3400 "" "58" 0x00000080] + Pad[114173 -4622 114173 4478 2400 1000 3400 "" "60" 0x00000080] + Pad[3937 -4622 3937 4478 2400 1000 3400 "" "4" 0x00000080] + Pad[43307 9900 43307 19000 2400 1000 3400 "" "23" 0x00004080] + Pad[47244 9900 47244 19000 2400 1000 3400 "" "25" 0x00004080] + Pad[51181 9900 51181 19000 2400 1000 3400 "" "27" 0x00004080] + Pad[55118 9900 55118 19000 2400 1000 3400 "" "29" 0x00004080] + Pad[59055 9900 59055 19000 2400 1000 3400 "" "31" 0x00004080] + Pad[62992 9900 62992 19000 2400 1000 3400 "" "33" 0x00004080] + Pad[66929 9900 66929 19000 2400 1000 3400 "" "35" 0x00004080] + Pad[70866 9900 70866 19000 2400 1000 3400 "" "37" 0x00004080] + Pad[74803 9900 74803 19000 2400 1000 3400 "" "39" 0x00004080] + Pad[78740 9900 78740 19000 2400 1000 3400 "" "41" 0x00004080] + Pad[82677 9900 82677 19000 2400 1000 3400 "" "43" 0x00004080] + Pad[86614 9900 86614 19000 2400 1000 3400 "" "45" 0x00004080] + Pad[90551 9900 90551 19000 2400 1000 3400 "" "47" 0x00004080] + Pad[94488 9900 94488 19000 2400 1000 3400 "" "49" 0x00004080] + Pad[98425 9900 98425 19000 2400 1000 3400 "" "51" 0x00004080] + Pad[102362 9900 102362 19000 2400 1000 3400 "" "53" 0x00004080] + Pad[106299 9900 106299 19000 2400 1000 3400 "" "55" 0x00004080] + Pad[110236 9900 110236 19000 2400 1000 3400 "" "57" 0x00004080] + Pad[114173 9900 114173 19000 2400 1000 3400 "" "59" 0x00004080] + Pad[118110 9900 118110 19000 2400 1000 3400 "" "61" 0x00004080] + Pad[122047 9900 122047 19000 2400 1000 3400 "" "63" 0x00004080] + Pad[118110 -4622 118110 4478 2400 1000 3400 "" "62" 0x00000080] + ElementLine [134000 -9000 134000 24000 1000] + ElementLine [-11000 24000 134000 24000 1000] + ElementLine [-11000 -9000 134000 -9000 1000] + ElementLine [-11000 -9000 -11000 24000 1000] + + ) + +Element[0x00000080 "0603" "R7" "10K" 252000 147500 6000 -2000 0 100 0x00000080] +( + Pad[-900 -2400 900 -2400 2400 3000 2400 "1" "1" 0x00000180] + Pad[-900 2400 900 2400 2400 3000 2400 "2" "2" 0x00000180] + ElementLine [-2700 4200 -2700 -4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 4200 2700 -4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element[0x00000080 "0603" "R11" "NONE" 221000 135500 4000 2200 0 100 0x00000080] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000080 "0603" "R12" "10K" 243500 133000 6000 2200 0 100 0x00000080] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000080 "0603" "C4" ".1uF" 202500 162500 -3500 8200 0 100 0x00000080] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element[0x00000080 "0603" "R16" "10K" 201000 141500 5000 700 0 100 0x00000080] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000080 "0603" "R13" "NONE" 209500 127000 -12500 700 0 100 0x00000080] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000080 "SO8" "U4" "unknown" 228000 153000 -3500 16000 0 100 0x00000080] +( + Pad[7000 -7500 13500 -7500 2000 1000 3000 "1" "1" 0x00004180] + Pad[7000 -2500 13500 -2500 2000 1000 3000 "2" "2" 0x00004180] + Pad[7000 2500 13500 2500 2000 1000 3000 "3" "3" 0x00004180] + Pad[7000 7500 13500 7500 2000 1000 3000 "4" "4" 0x00004180] + Pad[-13500 7500 -7000 7500 2000 1000 3000 "5" "5" 0x00000180] + Pad[-13500 2500 -7000 2500 2000 1000 3000 "6" "6" 0x00000180] + Pad[-13500 -2500 -7000 -2500 2000 1000 3000 "7" "7" 0x00000180] + Pad[-13500 -7500 -7000 -7500 2000 1000 3000 "8" "8" 0x00000180] + ElementLine [-15500 -9500 -2500 -9500 1000] + ElementLine [2500 -9500 15500 -9500 1000] + ElementLine [-15500 -9500 -15500 9500 1000] + ElementLine [-15500 9500 15500 9500 1000] + ElementLine [15500 -9500 15500 9500 1000] + ElementArc [0 -9500 2500 2500 0 180 1000] + + ) + +Element[0x00000080 "0603" "R14" "10K" 244500 124500 6500 2200 0 100 0x00000080] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element[0x00000080 "0603" "R8" "10K" 263000 150500 6000 2200 0 100 0x00000080] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [4200 2700 -4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 2700 -4200 -2700 600] + + ) + +Element[0x00000080 "SOT23" "Q2" "unknown" 132000 230000 -7000 8300 0 100 0x00000080] +( + Pad[0 -300 0 300 3400 3000 4000 "1" "1" 0x00004180] + Pad[-7800 -300 -7800 300 3400 3000 4000 "2" "2" 0x00004180] + Pad[-3900 -8500 -3900 -7900 3400 3000 4000 "3" "3" 0x00000180] + ElementLine [-10300 -11000 2500 -11000 1000] + ElementLine [-10300 -11000 -10300 2900 1000] + ElementLine [-10300 2900 2500 2900 1000] + ElementLine [2500 -11000 2500 2900 1000] + + ) + +Element[0x00000080 "0603" "R3" "NONE" 116500 225500 -4500 9700 0 100 0x00000080] +( + Pad[-900 2400 900 2400 2400 2000 3000 "1" "1" 0x00000180] + Pad[-900 -2400 900 -2400 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000080 "0603" "R5" "1K" 96000 219000 -4000 10000 0 100 0x00000080] +( + Pad[-900 2400 900 2400 2400 3000 2400 "1" "1" 0x00000180] + Pad[-900 -2400 900 -2400 2400 3000 2400 "2" "2" 0x00000180] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + + ) + +Element[0x00000080 "SOT223" "U3" "unknown" 116800 117400 -5300 14600 0 100 0x00000080] +( + Pad[0 -3300 0 3300 5600 3000 6200 "1" "1" 0x00004180] + Pad[-9000 -3300 -9000 3300 5600 3000 6200 "2" "2" 0x00004180] + Pad[-18100 -3300 -18100 3300 5600 3000 6200 "3" "3" 0x00004180] + Pad[-13500 -24400 -4500 -24400 12200 3000 12800 "4" "4" 0x00004180] + ElementLine [-23300 -32900 5200 -32900 1000] + ElementLine [-23300 -32900 -23300 8500 1000] + ElementLine [-23300 8500 5200 8500 1000] + ElementLine [5200 -32900 5200 8500 1000] + + ) + +Element[0x00000080 "EIA6032" "C82" "22uF" 76000 104000 -6000 24800 0 100 0x00000080] +( + Pad[-3900 9400 3900 9400 9700 2000 10300 "1" "1" 0x00000180] + Pad[-3900 -9400 3900 -9400 9700 2000 10300 "2" "2" 0x00000180] + ElementLine [11200 13000 8700 17800 1000] + ElementLine [11200 -16800 11200 13000 1000] + ElementLine [-11200 -16800 11200 -16800 1000] + ElementLine [-11200 -16800 -11200 13000 1000] + ElementLine [-8700 17800 -11200 13000 1000] + ElementLine [-8700 17800 8700 17800 2000] + + ) + +Element[0x00000080 "0603" "C83" ".1uF" 127500 105500 -2000 10700 0 100 0x00000080] +( + Pad[-900 -2400 900 -2400 2400 2000 3000 "1" "1" 0x00000180] + Pad[-900 2400 900 2400 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [-2700 -4200 -2700 4200 600] + ElementLine [-2700 4200 2700 4200 600] + ElementLine [2700 -4200 2700 4200 600] + ElementLine [-2700 -4200 2700 -4200 600] + + ) + +Element[0x00000080 "1206" "C102" "4.7uF" 281500 179000 10000 2400 0 100 0x00000080] +( + Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" 0x00000180] + Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" 0x00000180] + ElementLine [-8400 5400 8400 5400 1000] + ElementLine [8400 -5400 8400 5400 1000] + ElementLine [-8400 -5400 8400 -5400 1000] + ElementLine [-8400 -5400 -8400 5400 1000] + + ) + +Element[0x00000080 "0603" "C101" "470pF" 279500 189500 6000 1700 0 100 0x00000080] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [-4200 2700 4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 -2700 -4200 2700 600] + + ) + +Element[0x00000080 "1206" "C104" "4.7uF" 234000 216500 11000 1900 0 100 0x00000080] +( + Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" 0x00000180] + Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" 0x00000180] + ElementLine [8400 5400 -8400 5400 1000] + ElementLine [8400 -5400 8400 5400 1000] + ElementLine [-8400 -5400 8400 -5400 1000] + ElementLine [-8400 5400 -8400 -5400 1000] + + ) + +Element[0x00000080 "0603" "C103" "470pF" 233000 192500 6200 0 3 100 0x00000080] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [4200 2700 -4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 2700 -4200 -2700 600] + + ) + +Element[0x00000080 "1206" "C106" "4.7uF" 159500 184000 10000 2900 0 100 0x00000080] +( + Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" 0x00000180] + Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" 0x00000180] + ElementLine [8400 5400 -8400 5400 1000] + ElementLine [8400 -5400 8400 5400 1000] + ElementLine [-8400 -5400 8400 -5400 1000] + ElementLine [-8400 5400 -8400 -5400 1000] + + ) + +Element[0x000000c0 "0603" "C105" "470pF" 157500 193500 5500 1200 0 100 0x00000080] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [4200 2700 -4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 2700 -4200 -2700 600] + + ) + +Element[0x00000080 "1206" "C108" "4.7uF" 74000 180500 -22500 1400 0 100 0x00000080] +( + Pad[-4800 -1800 -4800 1800 4800 2000 5400 "1" "1" 0x00000180] + Pad[4800 -1800 4800 1800 4800 2000 5400 "2" "2" 0x00000180] + ElementLine [8400 5400 -8400 5400 1000] + ElementLine [8400 -5400 8400 5400 1000] + ElementLine [-8400 -5400 8400 -5400 1000] + ElementLine [-8400 5400 -8400 -5400 1000] + + ) + +Element[0x000000c0 "0603" "C107" "470pF" 70500 190500 -18500 1700 0 100 0x00000080] +( + Pad[-2400 -900 -2400 900 2400 2000 3000 "1" "1" 0x00000180] + Pad[2400 -900 2400 900 2400 2000 3000 "2" "2" 0x00000180] + ElementLine [4200 2700 -4200 2700 600] + ElementLine [4200 -2700 4200 2700 600] + ElementLine [-4200 -2700 4200 -2700 600] + ElementLine [-4200 2700 -4200 -2700 600] + + ) +Layer(1 "solder") +( + Line[209000 49000 209000 93000 1000 2000 0x00000000] + Line[109000 24000 166000 81000 1000 2000 0x00000000] + Line[244500 23500 213000 55000 1000 2000 0x00000000] + Line[119000 24000 170000 75000 1000 2000 0x00000000] + Line[213000 55000 213000 91500 1000 2000 0x00000000] + Line[129000 24000 174000 69000 1000 2000 0x00000000] + Line[234500 23500 209000 49000 1000 2000 0x00000000] + Line[139000 24000 177000 62000 1000 2000 0x00000000] + Line[177000 62000 177000 93000 1000 2000 0x00000000] + Line[149000 24000 182000 57000 1000 2000 0x00000000] + Line[182000 57000 182000 93000 1000 2000 0x00000000] + Line[159000 24000 185000 50000 1000 2000 0x00000000] + Line[185000 50000 185000 93000 1000 2000 0x00000000] + Line[184500 23500 189000 28000 1000 2000 0x00000000] + Line[189000 28000 189000 93000 1000 2000 0x00000000] + Line[194500 23500 193000 25000 1000 2000 0x00000000] + Line[216922 61078 216922 92000 1000 2000 0x00000000] + Line[193000 25000 193000 91000 1000 2000 0x00000000] + Line[204500 23500 197000 31000 1000 2000 0x00000000] + Line[197000 31000 197000 96000 1000 2000 0x00000000] + Line[214500 23500 201000 37000 1000 2000 0x00000000] + Line[254500 23500 216922 61078 1000 2000 0x00000000] + Line[201000 37000 201000 92000 1000 2000 0x00000000] + Line[224500 23500 205000 43000 1000 2000 0x00000000] + Line[99000 24000 162000 87000 1000 2000 0x00000000] + Line[205000 43000 205000 91000 1000 2000 0x00000000] + Line[174000 69000 174000 92000 1000 2000 0x00000000] + Line[170000 75000 170000 93500 1000 2000 0x00000000] + Line[166000 81000 166000 93000 1000 2000 0x00000000] + Line[162000 87000 162000 93500 1000 2000 0x00000000] + Line[157867 91189 90178 23500 1000 2000 0x00000000] + Line[90178 23500 89000 23500 1000 2000 0x00000000] + Line[264166 91189 263500 90523 1000 2000 0x00000000] + Line[263500 90523 263500 81500 1000 2000 0x00000000] + Line[263500 81500 263000 82000 1000 2000 0x00000000] + Line[263000 82000 257500 82000 1000 2000 0x00000000] + Line[268103 91189 269000 90292 1000 2000 0x00000000] + Line[269000 90292 269000 81500 1000 2000 0x00000000] + Line[269000 81500 276000 81500 1000 2000 0x00000000] + Line[262600 76600 263500 75700 1000 2000 0x00000000] + Line[263500 75700 263500 72000 1000 2000 0x00000000] + Line[269600 76600 270000 76200 1000 2000 0x00000000] + Line[270000 76200 270000 72000 1000 2000 0x00000000] + Line[171900 220400 167000 220000 1000 2000 0x00000000] + Line[167000 220000 159500 220000 1000 2000 0x00000000] + Line[270500 63500 270500 66500 1000 2000 0x00000020] + Line[105500 244000 76000 214500 800 1600 0x00000000] + Line[154700 201300 169400 216000 2500 2000 0x00000020] + Line[117400 223100 118500 222000 1000 2000 0x00000000] + Line[148900 222100 150500 220500 1000 2000 0x00000000] + Line[150500 220500 158500 220500 1000 2000 0x00000000] + Line[241500 160500 241500 167500 1000 2000 0x00000020] + Line[117200 229500 125000 229500 1000 2000 0x00000000] + Line[141500 222000 118500 222000 1000 2000 0x00000000] + Line[117400 223100 119700 220800 1000 2000 0x00000000] + Line[119700 220800 119700 201300 1000 2000 0x00000000] + Line[95100 216600 95200 216500 1000 2000 0x00000000] + Line[95200 216500 103500 216500 1000 2000 0x00000000] + Line[103500 216500 102500 215500 1000 2000 0x00000000] + Line[102500 215500 102500 201500 1000 2000 0x00000000] + Line[189363 114811 189500 114948 1000 2000 0x00000000] + Line[189500 114948 189500 128500 1000 2000 0x00000000] + Line[185426 114811 184000 116237 1000 2000 0x00000000] + Line[184000 116237 184000 130500 1000 2000 0x00000000] + Line[184000 130500 187500 134000 1000 2000 0x00000000] + Line[187500 134000 188000 134000 1000 2000 0x00000000] + Line[183000 138000 187500 133500 1000 2000 0x00000000] + Line[180000 244000 105500 244000 800 1600 0x00000000] + Line[49500 201000 49500 200500 800 1600 0x00000000] + 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Connect("C106-1") + Connect("C105-1") + Connect("C104-1") + Connect("C103-1") + Connect("C102-1") + Connect("C101-1") + Connect("U2-6") + Connect("U2-10") + Connect("U2-15") + Connect("U2-3") + ) + Net("ifagc" "(unknown)") + ( + Connect("R7-1") + Connect("U4-1") + Connect("U2-16") + ) + Net("rfagc" "(unknown)") + ( + Connect("R9-1") + Connect("U4-7") + Connect("U2-7") + ) + Net("unnamed_net4" "(unknown)") + ( + Connect("U2-18") + Connect("R17-1") + ) + Net("unnamed_net3" "(unknown)") + ( + Connect("C2-2") + Connect("R17-2") + ) + Net("unnamed_net2" "(unknown)") + ( + Connect("U2-17") + Connect("R10-1") + ) + Net("unnamed_net1" "(unknown)") + ( + Connect("C1-2") + Connect("R10-2") + ) + Net("AUX_ADC_B1" "(unknown)") + ( + Connect("J2-61") + ) + Net("AUX_ADC_A1" "(unknown)") + ( + Connect("J2-59") + ) + Net("AUX_ADC_REF" "(unknown)") + ( + Connect("J2-57") + ) + Net("AUX_DAC_C" "(unknown)") + ( + Connect("J2-55") + ) + Net("AUX_DAC_B" "(unknown)") + ( + Connect("R14-2") + Connect("J2-53") + ) + Net("AUX_DAC_A" "(unknown)") + ( + Connect("R12-2") + Connect("J2-51") + ) + Net("AUX_DAC_D" "(unknown)") + ( + Connect("J2-49") + ) + Net("SEN_RX" "(unknown)") + ( + Connect("J2-35") + ) + Net("VINP_A" "(unknown)") + ( + Connect("C1-1") + Connect("C5-1") + Connect("J2-62") + ) + Net("VINN_A" "(unknown)") + ( + Connect("C2-1") + Connect("C6-1") + Connect("J2-60") + ) + Net("VREF" "(unknown)") + ( + Connect("J2-56") + ) + Net("VINN_B" "(unknown)") + ( + Connect("J2-52") + ) + Net("VINP_B" "(unknown)") + ( + Connect("J2-50") + ) + Net("AVDD" "(unknown)") + ( + Connect("J2-45") + Connect("J2-43") + Connect("J2-46") + Connect("J2-44") + ) + Net("AGND" "(unknown)") + ( + Connect("C105-2") + Connect("C106-2") + Connect("C107-2") + Connect("C108-2") + Connect("C103-2") + Connect("C104-2") + Connect("C101-2") + Connect("C102-2") + Connect("C83-1") + Connect("C82-2") + Connect("U3-4") + Connect("U3-2") + Connect("C4-1") + Connect("C3-1") + Connect("R16-2") + Connect("R8-2") + Connect("U4-4") + Connect("R5-1") + Connect("U2-24") + Connect("U2-23") + Connect("U2-22") + Connect("U2-21") + Connect("U2-5") + Connect("C6-2") + Connect("C5-2") + Connect("U1-4") + Connect("U1-7") + Connect("J2-63") + Connect("J2-47") + Connect("J2-41") + Connect("J2-64") + Connect("J2-58") + Connect("J2-54") + Connect("J2-48") + Connect("J2-42") + ) + Net("io_rx_00" "(unknown)") + ( + Connect("R11-2") + Connect("J24-15") + Connect("J2-36") + ) + Net("io_rx_01" "(unknown)") + ( + Connect("R13-2") + Connect("J24-13") + Connect("J2-34") + ) + Net("io_rx_02" "(unknown)") + ( + Connect("J24-11") + Connect("J2-32") + ) + Net("io_rx_03" "(unknown)") + ( + Connect("J24-9") + Connect("J2-30") + ) + Net("io_rx_04" "(unknown)") + ( + Connect("J24-7") + Connect("J2-28") + ) + Net("SDI" "(unknown)") + ( + Connect("J2-33") + ) + Net("SDO" "(unknown)") + ( + Connect("J2-31") + ) + Net("SCLK" "(unknown)") + ( + Connect("J2-29") + ) + Net("RESET" "(unknown)") + ( + Connect("J2-27") + ) + Net("io_rx_05" "(unknown)") + ( + Connect("J24-5") + Connect("J2-26") + ) + Net("RS232_RXD" "(unknown)") + ( + Connect("J2-25") + ) + Net("io_rx_06" "(unknown)") + ( + Connect("J24-3") + Connect("J2-24") + ) + Net("RS232_TXD" "(unknown)") + ( + Connect("J2-23") + ) + Net("io_rx_07" "(unknown)") + ( + Connect("J24-1") + Connect("J2-22") + ) + Net("I2C_A0" "(unknown)") + ( + Connect("U1-1") + Connect("J2-21") + ) + Net("io_rx_08" "(unknown)") + ( + Connect("J25-15") + Connect("J2-20") + ) + Net("I2C_A1" "(unknown)") + ( + Connect("R6-2") + Connect("U1-2") + Connect("J2-19") + ) + Net("io_rx_09" "(unknown)") + ( + Connect("J25-13") + Connect("J2-18") + ) + Net("SDA" "(unknown)") + ( + Connect("R3-1") + Connect("Q2-2") + Connect("U1-5") + Connect("J2-17") + ) + Net("io_rx_10" "(unknown)") + ( + Connect("J25-11") + Connect("J2-16") + ) + Net("SCL" "(unknown)") + ( + Connect("R1-1") + Connect("Q1-2") + Connect("U1-6") + Connect("J2-15") + ) + Net("io_rx_11" "(unknown)") + ( + Connect("J25-9") + Connect("J2-14") + ) + Net("io_rx_12" "(unknown)") + ( + Connect("J25-7") + Connect("J2-12") + ) + Net("io_rx_13" "(unknown)") + ( + Connect("J25-5") + Connect("J2-10") + ) + Net("io_rx_14" "(unknown)") + ( + Connect("J25-3") + Connect("J2-8") + ) + Net("DVDD" "(unknown)") + ( + Connect("Q2-1") + Connect("Q1-1") + Connect("U1-8") + Connect("U1-3") + Connect("J2-9") + Connect("J2-7") + ) + Net("io_rx_15" "(unknown)") + ( + Connect("J25-1") + Connect("J2-6") + ) + Net("6V" "(unknown)") + ( + Connect("C83-2") + Connect("U3-1") + Connect("J2-5") + Connect("J2-3") + ) + Net("GND" "(unknown)") + ( + Connect("J25-6") + Connect("J25-4") + Connect("J25-14") + Connect("J25-12") + Connect("J25-10") + Connect("J25-16") + Connect("J25-8") + Connect("J25-2") + Connect("J24-6") + Connect("J24-4") + Connect("J24-14") + Connect("J24-12") + Connect("J24-10") + Connect("J24-16") + Connect("J24-8") + Connect("J24-2") + Connect("J2-37") + Connect("J2-38") + Connect("J2-2") + Connect("J2-1") + ) +) diff --git a/usrp-hw/tvrx/tvrx.prj b/usrp-hw/tvrx/tvrx.prj new file mode 100644 index 000000000..fd0810781 --- /dev/null +++ b/usrp-hw/tvrx/tvrx.prj @@ -0,0 +1,6 @@ +# List all schematics +schematics tvrx.sch + +output-name tvrx + +elements-dir ../pkg/newlib diff --git a/usrp-hw/tvrx/tvrx.sch b/usrp-hw/tvrx/tvrx.sch new file mode 100644 index 000000000..c2cb9b332 --- /dev/null +++ b/usrp-hw/tvrx/tvrx.sch @@ -0,0 +1,1073 @@ +v 20050820 1 +C 83700 45200 1 180 1 pmc64.sym +{ +T 84400 32000 5 10 1 1 0 2 1 +refdes=J2 +T 83700 45200 5 10 0 1 90 6 1 +footprint=PMC-REVERSE +} +N 85200 40100 86900 40100 4 +{ +T 85500 40100 5 10 1 1 0 0 1 +netname=RS232_RXD +} +N 85200 40500 86900 40500 4 +{ +T 85500 40500 5 10 1 1 0 0 1 +netname=RS232_TXD +} +C 83600 32300 1 90 0 generic-power.sym +{ +T 83350 32500 5 10 1 1 90 3 1 +net=AGND:1 +} +N 83600 32500 83800 32500 4 +N 85200 41300 86500 41300 4 +{ +T 85600 41300 5 10 1 1 0 0 1 +netname=I2C_A1 +} +C 85400 32700 1 270 0 generic-power.sym +{ +T 85650 32500 5 10 1 1 270 3 1 +net=AGND:1 +} +N 85400 32500 85200 32500 4 +N 85200 38100 86400 38100 4 +{ +T 85300 38100 5 10 1 1 0 0 1 +netname=SEN_RX +} +C 83600 36700 1 90 0 generic-power.sym +{ +T 83350 36900 5 10 1 1 90 3 1 +net=AGND:1 +} +N 83600 36900 83800 36900 4 +C 85400 37100 1 270 0 generic-power.sym +{ +T 85650 36900 5 10 1 1 270 3 1 +net=AGND:1 +} +N 85400 36900 85200 36900 4 +N 85200 33300 86800 33300 4 +{ +T 85200 33300 5 10 1 1 0 0 1 +netname=AUX_ADC_A1 +} +N 85200 32900 86800 32900 4 +{ +T 85200 32900 5 10 1 1 0 0 1 +netname=AUX_ADC_B1 +} +C 83600 33500 1 90 0 generic-power.sym +{ +T 83350 33700 5 10 1 1 90 3 1 +net=AGND:1 +} +N 83600 33700 83800 33700 4 +C 83600 34300 1 90 0 generic-power.sym +{ +T 83350 34500 5 10 1 1 90 3 1 +net=AGND:1 +} +N 83600 34500 83800 34500 4 +C 83600 35500 1 90 0 generic-power.sym +{ +T 83350 35700 5 10 1 1 90 3 1 +net=AGND:1 +} +N 83600 35700 83800 35700 4 +N 82200 32900 83800 32900 4 +{ +T 82200 32900 5 10 1 1 0 0 1 +netname=VINP_A +} +N 82200 33300 83800 33300 4 +{ +T 82200 33300 5 10 1 1 0 0 1 +netname=VINN_A +} +N 82200 35300 83800 35300 4 +{ +T 82200 35300 5 10 1 1 0 0 1 +netname=VINP_B +} +N 82200 34900 83800 34900 4 +{ +T 82200 34900 5 10 1 1 0 0 1 +netname=VINN_B +} +N 83800 34100 82200 34100 4 +{ +T 82300 34100 5 10 1 1 0 0 1 +netname=VREF +} +C 85400 35900 1 270 0 generic-power.sym +{ +T 85650 35700 5 10 1 1 270 3 1 +net=AGND:1 +} +N 85400 35700 85200 35700 4 +C 86000 36300 1 270 0 generic-power.sym +{ +T 86250 36100 5 10 1 1 270 3 1 +net=AVDD:1 +} +N 85200 36500 85700 36500 4 +N 85200 36100 86000 36100 4 +C 85700 36700 1 270 0 generic-power.sym +{ +T 85950 36500 5 10 1 1 270 3 1 +net=AVDD:1 +} +C 85900 44700 1 270 0 generic-power.sym +{ +T 86150 44500 5 10 1 1 270 3 1 +net=6V:1 +} +C 83000 36300 1 90 1 generic-power.sym +{ +T 82750 36100 5 10 1 1 90 3 1 +net=AVDD:1 +} +N 83800 36100 83000 36100 4 +N 83800 36500 83300 36500 4 +C 83300 36700 1 90 1 generic-power.sym +{ +T 83050 36500 5 10 1 1 90 3 1 +net=AVDD:1 +} +N 85200 44500 85900 44500 4 +N 85200 44100 85700 44100 4 +C 85700 43500 1 270 0 generic-power.sym +{ +T 85950 43300 5 10 1 1 270 3 1 +net=DVDD:1 +} +N 85200 43300 85700 43300 4 +N 85200 43700 85500 43700 4 +N 85700 44100 85700 44500 4 +N 85500 43700 85500 43300 4 +N 81800 44100 83800 44100 4 +{ +T 82100 44100 5 10 1 1 0 0 1 +netname=io_rx_15 +} +N 81800 43700 83800 43700 4 +{ +T 82100 43700 5 10 1 1 0 0 1 +netname=io_rx_14 +} +N 81800 42500 83800 42500 4 +{ +T 82100 42500 5 10 1 1 0 0 1 +netname=io_rx_11 +} +N 81800 43300 83800 43300 4 +{ +T 82100 43300 5 10 1 1 0 0 1 +netname=io_rx_13 +} +N 81800 42900 83800 42900 4 +{ +T 82100 42900 5 10 1 1 0 0 1 +netname=io_rx_12 +} +N 81800 41300 83800 41300 4 +{ +T 82100 41300 5 10 1 1 0 0 1 +netname=io_rx_08 +} +N 81800 42100 83800 42100 4 +{ +T 82100 42100 5 10 1 1 0 0 1 +netname=io_rx_10 +} +N 81800 41700 83800 41700 4 +{ +T 82100 41700 5 10 1 1 0 0 1 +netname=io_rx_09 +} +N 81800 40100 83800 40100 4 +{ +T 82100 40100 5 10 1 1 0 0 1 +netname=io_rx_05 +} +N 81800 40900 83800 40900 4 +{ +T 82100 40900 5 10 1 1 0 0 1 +netname=io_rx_07 +} +N 81800 40500 83800 40500 4 +{ +T 82100 40500 5 10 1 1 0 0 1 +netname=io_rx_06 +} +N 81800 38900 83800 38900 4 +{ +T 82100 38900 5 10 1 1 0 0 1 +netname=io_rx_02 +} +N 81800 39700 83800 39700 4 +{ +T 82100 39700 5 10 1 1 0 0 1 +netname=io_rx_04 +} +N 81800 39300 83800 39300 4 +{ +T 82100 39300 5 10 1 1 0 0 1 +netname=io_rx_03 +} +N 81800 38100 83800 38100 4 +{ +T 82100 38100 5 10 1 1 0 0 1 +netname=io_rx_00 +} +N 81800 38500 83800 38500 4 +{ +T 82100 38500 5 10 1 1 0 0 1 +netname=io_rx_01 +} +C 65600 29400 0 0 0 title-bordered-C.sym +T 82500 30300 5 10 1 1 0 0 1 +date=$Date: 2005/12/19 02:52:55 $ +T 84400 30000 5 10 1 1 0 0 1 +rev=$Revision: 1.5 $ +T 84500 29700 5 10 1 1 0 0 1 +auth=$Author: matt $ +T 80300 30000 5 10 1 1 0 0 1 +fname=$Source: /opt/usrp-hw-cvs/usrp-hw/tvrx/tvrx.sch,v $ +T 83700 30700 8 14 1 1 0 4 1 +title=TV Tuner Daughterboard +T 81300 29700 9 10 1 0 0 0 1 +1 +T 82100 29700 9 10 1 0 0 0 1 +1 +N 85200 42100 86300 42100 4 +{ +T 85500 42100 5 10 1 1 0 0 1 +netname=SCL +} +N 85200 41700 86300 41700 4 +{ +T 85500 41700 5 10 1 1 0 0 1 +netname=SDA +} +N 85200 39300 86600 39300 4 +{ +T 85600 39300 5 10 1 1 0 0 1 +netname=SCLK +} +N 85200 38900 86600 38900 4 +{ +T 85600 38900 5 10 1 1 0 0 1 +netname=SDO +} +N 85200 38500 86600 38500 4 +{ +T 85600 38500 5 10 1 1 0 0 1 +netname=SDI +} +N 85200 34900 86900 34900 4 +{ +T 85400 34900 5 10 1 1 0 0 1 +netname=AUX_DAC_A +} +N 85200 34500 86900 34500 4 +{ +T 85400 34500 5 10 1 1 0 0 1 +netname=AUX_DAC_B +} +N 85200 34100 86900 34100 4 +{ +T 85400 34100 5 10 1 1 0 0 1 +netname=AUX_DAC_C +} +N 85200 33700 86900 33700 4 +{ +T 85300 33700 5 10 1 1 0 0 1 +netname=AUX_ADC_REF +} +N 85200 35300 86900 35300 4 +{ +T 85400 35300 5 10 1 1 0 0 1 +netname=AUX_DAC_D +} +C 72500 42900 1 0 0 24Cxx-1.sym +{ +T 73000 44100 5 10 1 1 0 0 1 +refdes=U1 +T 72500 42900 5 10 0 1 0 0 1 +footprint=SO8 +T 72800 42700 5 10 1 1 0 0 1 +device=24LC025B +T 72800 42300 5 10 1 1 0 0 1 +net=AGND:4 +T 72800 42500 5 10 1 1 0 0 1 +net=DVDD:8 +} +N 73800 43200 75200 43200 4 +{ +T 74700 43200 5 10 1 1 0 0 1 +netname=SCL +} +N 73800 43000 75200 43000 4 +{ +T 74700 43000 5 10 1 1 0 0 1 +netname=SDA +} +N 73800 43400 74000 43400 4 +N 85200 40900 86500 40900 4 +{ +T 85600 40900 5 10 1 1 0 0 1 +netname=I2C_A0 +} +N 71500 43400 72500 43400 4 +{ +T 71600 43400 5 10 1 1 0 0 1 +netname=I2C_A1 +} +N 71500 43600 72500 43600 4 +{ +T 71600 43600 5 10 1 1 0 0 1 +netname=I2C_A0 +} +C 71500 43000 1 90 0 generic-power.sym +{ +T 71250 43200 5 10 1 1 90 3 1 +net=DVDD:1 +} +N 71500 43200 72500 43200 4 +N 69200 38200 70200 38200 4 +{ +T 69200 38200 5 10 1 1 0 0 1 +netname=VINP_A +} +N 69600 37800 70600 37800 4 +{ +T 69600 37800 5 10 1 1 0 0 1 +netname=VINN_A +} +C 72200 38100 1 0 1 resistor-1.sym +{ +T 71200 38500 5 10 1 1 180 6 1 +refdes=R10 +T 71900 38500 5 10 1 1 180 6 1 +value=0 +T 72200 38100 5 10 0 1 0 6 1 +footprint=0603 +} +C 72600 37700 1 0 1 resistor-1.sym +{ +T 72000 38100 5 10 1 1 180 6 1 +refdes=R17 +T 72400 38100 5 10 1 1 180 6 1 +value=0 +T 72600 37700 5 10 0 1 0 6 1 +footprint=0603 +} +C 69200 38000 1 0 1 capacitor-1.sym +{ +T 68600 38300 5 10 1 1 0 6 1 +refdes=C5 +T 68600 37900 5 10 1 1 0 6 1 +value=10pF +T 69200 38000 5 10 0 1 90 2 1 +footprint=0603 +} +C 69600 37600 1 0 1 capacitor-1.sym +{ +T 69000 37900 5 10 1 1 0 6 1 +refdes=C6 +T 69000 37500 5 10 1 1 0 6 1 +value=10pF +T 69600 37600 5 10 0 1 90 2 1 +footprint=0603 +} +C 68100 38000 1 90 0 generic-power.sym +{ +T 67850 38200 5 10 1 1 270 5 1 +net=AGND:1 +} +N 68300 38200 68100 38200 4 +C 68500 37600 1 90 0 generic-power.sym +{ +T 68250 37800 5 10 1 1 270 5 1 +net=AGND:1 +} +N 68700 37800 68500 37800 4 +N 72800 38200 72200 38200 4 +N 72800 37800 72600 37800 4 +T 81100 45500 9 20 1 0 0 0 1 +REVERSE PMC on BOTTOM!!!! +N 86600 39700 85200 39700 4 +{ +T 86200 39700 5 10 1 1 0 6 1 +netname=RESET +} +C 79700 35400 1 0 0 header16-1.sym +{ +T 80200 38700 5 10 1 1 0 0 1 +refdes=J24 +T 79700 35400 5 10 0 1 0 0 1 +footprint=CONNECTOR 8 2 +} +C 79700 31400 1 0 0 header16-1.sym +{ +T 80200 34700 5 10 1 1 0 0 1 +refdes=J25 +T 79700 31400 5 10 0 1 0 0 1 +footprint=CONNECTOR 8 2 +} +N 81100 37200 81400 37200 4 +C 81700 37100 1 90 0 gnd-1.sym +N 81100 38400 81300 38400 4 +N 81300 38400 81300 37200 4 +N 81300 37200 81300 35600 4 +N 81300 35600 81100 35600 4 +N 81100 38000 81300 38000 4 +N 81100 37600 81300 37600 4 +N 81100 36800 81300 36800 4 +N 81100 36400 81300 36400 4 +N 81100 36000 81300 36000 4 +N 81100 33200 81400 33200 4 +C 81700 33100 1 90 0 gnd-1.sym +N 81100 34400 81300 34400 4 +N 81300 34400 81300 33200 4 +N 81300 33200 81300 31600 4 +N 81300 31600 81100 31600 4 +N 81100 34000 81300 34000 4 +N 81100 33600 81300 33600 4 +N 81100 32800 81300 32800 4 +N 81100 32400 81300 32400 4 +N 81100 32000 81300 32000 4 +N 78000 34400 79700 34400 4 +{ +T 78500 34400 5 10 1 1 0 0 1 +netname=io_rx_15 +} +N 78000 32800 79700 32800 4 +{ +T 78500 32800 5 10 1 1 0 0 1 +netname=io_rx_11 +} +N 78000 33600 79700 33600 4 +{ +T 78500 33600 5 10 1 1 0 0 1 +netname=io_rx_13 +} +N 78000 32000 79700 32000 4 +{ +T 78500 32000 5 10 1 1 0 0 1 +netname=io_rx_09 +} +N 78100 37600 79700 37600 4 +{ +T 78500 37600 5 10 1 1 0 0 1 +netname=io_rx_05 +} +N 78100 38400 79700 38400 4 +{ +T 78500 38400 5 10 1 1 0 0 1 +netname=io_rx_07 +} +N 78100 36800 79700 36800 4 +{ +T 78500 36800 5 10 1 1 0 0 1 +netname=io_rx_03 +} +N 78100 36000 79700 36000 4 +{ +T 78500 36000 5 10 1 1 0 0 1 +netname=io_rx_01 +} +N 78000 34000 79700 34000 4 +{ +T 78500 34000 5 10 1 1 0 0 1 +netname=io_rx_14 +} +N 78000 33200 79700 33200 4 +{ +T 78500 33200 5 10 1 1 0 0 1 +netname=io_rx_12 +} +N 78000 31600 79700 31600 4 +{ +T 78500 31600 5 10 1 1 0 0 1 +netname=io_rx_08 +} +N 78000 32400 79700 32400 4 +{ +T 78500 32400 5 10 1 1 0 0 1 +netname=io_rx_10 +} +N 78100 38000 79700 38000 4 +{ +T 78500 38000 5 10 1 1 0 0 1 +netname=io_rx_06 +} +N 78100 36400 79700 36400 4 +{ +T 78500 36400 5 10 1 1 0 0 1 +netname=io_rx_02 +} +N 78100 37200 79700 37200 4 +{ +T 78500 37200 5 10 1 1 0 0 1 +netname=io_rx_04 +} +N 78100 35600 79700 35600 4 +{ +T 78500 35600 5 10 1 1 0 0 1 +netname=io_rx_00 +} +C 72700 34100 1 0 0 mt4937di5.sym +{ +T 73700 40900 5 10 1 1 0 6 1 +refdes=U2 +} +C 75400 40600 1 0 0 generic-power.sym +{ +T 75600 40850 5 10 1 1 180 5 1 +net=5V_RF:1 +} +N 74800 40200 75600 40200 4 +N 75600 37700 75600 40600 4 +N 75600 39000 74800 39000 4 +N 75600 39400 74800 39400 4 +N 75600 39800 74800 39800 4 +N 72800 40200 71500 40200 4 +{ +T 71600 40200 5 10 1 1 0 0 1 +netname=rfagc +} +N 72800 39800 71500 39800 4 +{ +T 71600 39800 5 10 1 1 0 0 1 +netname=ifagc +} +N 66100 44400 66700 44400 4 +{ +T 66300 44400 5 10 1 1 0 0 1 +netname=SCL +} +N 68200 41300 69200 41300 4 +{ +T 68300 41300 5 10 1 1 0 0 1 +netname=I2C_A1 +} +C 66700 44900 1 270 0 nmos-sot23.sym +{ +T 67100 44900 5 10 1 1 0 0 1 +refdes=Q1 +} +C 66700 45000 1 0 0 generic-power.sym +{ +T 66900 45250 5 10 1 1 0 3 1 +net=DVDD:1 +} +C 67700 45500 1 0 0 generic-power.sym +{ +T 67900 45750 5 10 1 1 180 5 1 +net=5V_RF:1 +} +N 66900 45000 66900 44900 4 +C 66700 44000 1 0 0 resistor-1.sym +{ +T 67100 43900 5 10 1 1 270 0 1 +value=NONE +T 66700 44000 5 10 0 1 0 0 1 +footprint=0603 +T 67300 43900 5 10 1 1 270 0 1 +refdes=R1 +} +C 68000 44500 1 90 0 resistor-1.sym +{ +T 68100 44900 5 10 1 1 0 0 1 +value=2.2K +T 68000 44500 5 10 0 1 90 0 1 +footprint=0603 +T 68100 45100 5 10 1 1 0 0 1 +refdes=R2 +} +N 66500 44400 66500 44100 4 +N 67500 44400 68800 44400 4 +{ +T 68000 44400 5 10 1 1 0 0 1 +netname=SCL_5V +} +N 67900 45400 67900 45500 4 +N 67800 44100 67800 44400 4 +N 67900 44500 67900 44400 4 +N 67800 44100 67600 44100 4 +N 66700 44100 66500 44100 4 +N 67800 42900 68400 42900 4 +{ +T 68000 42900 5 10 1 1 0 0 1 +netname=SDA +} +C 68400 43400 1 270 0 nmos-sot23.sym +{ +T 68800 43400 5 10 1 1 0 0 1 +refdes=Q2 +} +C 68400 43500 1 0 0 generic-power.sym +{ +T 68600 43750 5 10 1 1 0 3 1 +net=DVDD:1 +} +C 69400 44000 1 0 0 generic-power.sym +{ +T 69600 44250 5 10 1 1 180 5 1 +net=5V_RF:1 +} +N 68600 43500 68600 43400 4 +C 68400 42500 1 0 0 resistor-1.sym +{ +T 68800 42400 5 10 1 1 270 0 1 +value=NONE +T 68400 42500 5 10 0 1 0 0 1 +footprint=0603 +T 69000 42400 5 10 1 1 270 0 1 +refdes=R3 +} +C 69700 43000 1 90 0 resistor-1.sym +{ +T 69800 43400 5 10 1 1 0 0 1 +value=2.2K +T 69700 43000 5 10 0 1 90 0 1 +footprint=0603 +T 69800 43600 5 10 1 1 0 0 1 +refdes=R4 +} +N 68200 42900 68200 42600 4 +N 69200 42900 70500 42900 4 +{ +T 69700 42900 5 10 1 1 0 0 1 +netname=SDA_5V +} +N 69600 43900 69600 44000 4 +N 69500 42600 69500 42900 4 +N 69600 43000 69600 42900 4 +N 69500 42600 69300 42600 4 +N 68400 42600 68200 42600 4 +N 71500 39000 72800 39000 4 +{ +T 72000 39000 5 10 1 1 0 0 1 +netname=SCL_5V +} +N 71500 38600 72800 38600 4 +{ +T 72000 38600 5 10 1 1 0 0 1 +netname=SDA_5V +} +T 70700 44900 9 20 1 0 0 0 1 +Add 470 pF and 4.7uF to each VSx +C 75300 34500 1 180 0 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72150 32700 5 10 1 1 90 3 1 +net=AGND:1 +} +N 74700 32500 75500 32500 4 +{ +T 75000 32500 5 10 1 1 0 0 1 +netname=rfagc +} +N 73700 32700 73500 32700 4 +N 73600 32700 73600 33200 4 +N 72400 32700 72600 32700 4 +N 73600 33200 73800 33200 4 +N 74700 33200 74900 33200 4 +N 74900 33200 74900 32500 4 +N 74800 36200 75100 36200 4 +N 75100 34500 75100 36200 4 +N 66600 34500 68000 34500 4 +{ +T 66900 34500 5 10 1 1 0 0 1 +netname=io_rx_00 +} +N 71300 32100 72500 32100 4 +{ +T 71600 32100 5 10 1 1 0 0 1 +netname=io_rx_01 +} +C 68900 32900 1 270 1 capacitor-1.sym +{ +T 69000 33500 5 10 1 1 90 0 1 +refdes=C3 +T 69300 33500 5 10 1 1 90 0 1 +value=.1uF +T 68900 32900 5 10 0 1 0 2 1 +footprint=0603 +} +C 68900 34400 1 0 1 resistor-1.sym +{ +T 68100 34800 5 10 1 1 180 6 1 +refdes=R11 +T 68400 34800 5 10 1 1 180 6 1 +value=NONE +T 68900 34400 5 10 0 1 0 6 1 +footprint=0603 +} +C 68900 33900 1 0 1 resistor-1.sym +{ +T 68100 34300 5 10 1 1 180 6 1 +refdes=R12 +T 68600 34300 5 10 1 1 180 6 1 +value=10K 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+value=22uF +T 80400 43200 5 10 0 1 180 2 1 +footprint=EIA6032 +} +N 80200 41600 80200 42300 4 +N 79100 43800 79100 44000 4 +N 79100 44000 80200 44000 4 +N 77900 44000 78700 44000 4 +N 78700 44000 78700 43800 4 +C 77700 42600 1 270 1 capacitor-1.sym +{ +T 77500 43200 5 10 1 1 0 0 1 +refdes=C83 +T 77500 42800 5 10 1 1 0 0 1 +value=.1uF +T 77700 42600 5 10 0 1 0 2 1 +footprint=0603 +} +N 77900 42600 77900 41600 4 +N 77900 41600 80200 41600 4 +C 76200 40300 1 180 1 capacitor-2.sym +{ +T 76800 40200 5 10 1 1 180 8 1 +refdes=C102 +T 76600 40200 5 10 1 1 0 6 1 +value=4.7uF +T 76200 40300 5 10 0 1 270 2 1 +footprint=1206 +} +C 76200 40300 1 0 0 capacitor-1.sym +{ +T 77200 40600 5 10 1 1 0 6 1 +refdes=C101 +T 76500 40600 5 10 1 1 0 6 1 +value=470pF +T 76200 40300 5 10 0 1 90 0 1 +footprint=0603 +} +C 76200 39500 1 180 1 capacitor-2.sym +{ +T 76800 39400 5 10 1 1 180 8 1 +refdes=C104 +T 76600 39400 5 10 1 1 0 6 1 +value=4.7uF +T 76200 39500 5 10 0 1 270 2 1 +footprint=1206 +} +C 76200 39500 1 0 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38900 75600 38900 4 +N 76200 38500 75600 38500 4 +N 76200 38100 75600 38100 4 +N 76200 37700 75600 37700 4 +C 77600 37500 1 180 0 generic-power.sym +{ +T 77400 37250 5 10 1 1 180 3 1 +net=AGND:1 +} +N 77400 37500 77400 40500 4 +N 77400 40500 77100 40500 4 +N 77400 40100 77100 40100 4 +N 77400 39300 77100 39300 4 +N 77400 39700 77100 39700 4 +N 77400 37700 77100 37700 4 +N 77400 38100 77100 38100 4 +N 77400 38500 77100 38500 4 +N 77400 38900 77100 38900 4 diff --git a/usrp-hw/usrp/ChangeLog b/usrp-hw/usrp/ChangeLog new file mode 100644 index 000000000..36856e6be --- /dev/null +++ b/usrp-hw/usrp/ChangeLog @@ -0,0 +1,79 @@ +2004-11-22 Matt Ettus <matt@ettus.com> + + * fpga.sch : + - Added R2001-R2005. + - Jumpers to gnd for TXBLANK. + - Unpopulated resistors for redoing SPI, shared with io_tx_a/b[15] + +2004-11-03 Matt Ettus <matt@ettus.com> + + * fpga.sch : Removed J900 and J902 which were to test the FX2 bus. + The lines were just too long. + +2004-10-27 Matt Ettus <matt@ettus.com> + + * power.sch : Removed text note + + * dboard.sch : Swapped RS-232 so that each board gets a pair, shared between RX and TX + + * interface.sch : + - Removed U410 (MAX232) and associated caps + - Rerouted RS232 signals so they go out as CMOS levels + - Removed J645 which was PE[2:0] + + * fpga.sch : + - Redid FX2 bus interface probe pins on J900 + - Added J902 with FX2 data bus + +2004-10-23 Matt Ettus <matt@ettus.com> + + * netlist_cmd : + - Added command script for generating a netlist + * power.sch : + - Added J1001 for ground testpoints + - Added C0603 footprint to a bunch of caps. + +2004-10-10 Matt Ettus <matt@ettus.com> + + * fpga.sch : + - Remove io_tx_b_15 from VCXO tuning, remove R800,R803,R876,C800,C804 + - Connect X2.1 to DVDD + - Removed nets CLKOUT1_x and CLKOUT2_x + - Removed R801, R802, R857 -- CLK120 now goes straight to FPGA + - Removed J901 + - Split CLK120 into CLK_FPGA, CLK_CODEC_A, and CLK_CODEC_B, each with proper source and sink terminations. Use 50 ohm lines. + - Added R1011-R1016 and C1014-C1016 for terminations + - Added MYSTERY_SIGNAL to replace one RX_SYNC + - Moved SDO to where TX_BLANK was + - Moved SDI to one RX_SYNC + - Moved SEN_FPGA to where RESET was + + * dboard.sch : + - Removed CLKOUT1_x and CLKOUT2_x + - Removed io_[tx,rx]_x_16 which never did anything + + * interface.sch : + - Added MYSTERY_SIGNAL input to INT4 + + * power.sch : + - Removed D501 + - Added C1020 for more decoupling of 5V + - Increased value of C502 to 100 uF + +2004-10-08 Matt Ettus <matt@ettus.com> + + * interface.sch : + - Reset on PC0 is now RESET_CODEC + - Tool changed format of Text items + - NB - Need to find pin for RESET_FPGA. Maybe PE0,1,2 or FX2_1. Send rest to dboard? + + * dboard.sch : + - R701, R702 changed from 2K to 4K, to fit what the datasheet tells us. + - R1001,R1002,R1003,R1004,C1001,C1002,C1003,C1004 added to do sigma delta filtering on the motherboard + - Net SIGDEL_x no longer goes to dboard. It gets filtered, and AUX_DAC_D_x is sent + - RESET on CODECs and Dboards is now RESET_CODEC + - Tool changed format of Text items + - NB - Should we avoid sending REFIO_x to the dboards for sig integrity? + - NB - Get rid of io_tx/rx_x_16 + - NB - Find a bit 15 for io buses + diff --git a/usrp-hw/usrp/dboard.sch b/usrp-hw/usrp/dboard.sch new file mode 100644 index 000000000..3a6a9bc94 --- /dev/null +++ b/usrp-hw/usrp/dboard.sch @@ -0,0 +1,1604 @@ +v 20040111 1 +C 30600 17800 1 0 0 ad986X-ACTRL.sym +{ +T 81300 48100 5 10 1 1 0 6 1 +refdes=U602 +} +C 38400 17800 1 0 0 ad986X-AUX.sym +{ +T 89100 48100 5 10 1 1 0 6 1 +refdes=U602 +} +C 32400 13600 1 0 0 ad986X-CTRL.sym +{ +T 83200 43900 5 10 1 1 0 6 1 +refdes=U602 +} +C 79100 36200 1 270 1 pmc64.sym +{ +T 92300 36900 5 10 1 1 90 2 1 +refdes=J669 +T 79100 36200 5 10 0 1 0 0 1 +footprint=pmc +} +C 79100 31000 1 270 1 pmc64.sym +{ +T 92300 31700 5 10 1 1 90 2 1 +refdes=J668 +T 79100 31000 5 10 0 1 180 6 1 +footprint=pmc +} +C 77900 47200 1 90 1 generic-power.sym +{ +T 77650 47000 5 10 1 1 270 5 1 +net=AGND_2:1 +} +C 79200 46800 1 0 1 capacitor-1.sym +{ +T 78600 46800 5 10 1 1 0 6 1 +refdes=C714 +T 78200 47200 5 10 1 1 180 6 1 +value=0.1uF +T 79200 46800 5 10 0 1 90 2 1 +footprint=0603 +} +N 80300 47000 79200 47000 4 +N 78300 47000 77900 47000 4 +C 79200 47500 1 180 1 resistor-1.sym +{ +T 80200 47500 5 10 1 1 0 6 1 +value=4K +T 79200 47500 5 10 0 1 180 6 1 +footprint=0603 +T 79300 47500 5 10 1 1 0 6 1 +refdes=R702 +} +N 80300 47400 80100 47400 4 +N 79200 47400 78100 47400 4 +N 78100 47400 78100 47000 4 +C 84900 47000 1 270 0 generic-power.sym +{ +T 85150 46800 5 10 1 1 270 3 1 +net=AGND_2:1 +} +C 84600 46400 1 180 0 capacitor-1.sym +{ +T 83600 46300 5 10 1 1 0 0 1 +refdes=C702 +T 83600 46000 5 10 1 1 0 0 1 +value=0.1uF +T 84600 46400 5 10 0 1 270 0 1 +footprint=0603 +} +N 82300 46600 82500 46600 4 +N 82500 46600 82500 46200 4 +N 82300 46200 83700 46200 4 +N 82300 47400 83700 47400 4 +N 82500 47400 82500 47000 4 +N 82500 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1 1 0 0 1 +netname=io_tx_b_15 +} +N 68300 52100 68300 54700 4 +{ +T 68300 52900 5 10 1 1 90 0 1 +netname=io_tx_a_15 +} +N 68300 54700 68800 54700 4 +C 61100 46000 1 0 0 SMA-5.sym +{ +T 61100 46800 5 10 1 1 0 0 1 +refdes=J2001 +T 61100 46000 5 10 0 1 0 6 1 +footprint=SMA_VERT +} +C 62900 46400 1 0 1 resistor-1.sym +{ +T 62700 46700 5 10 1 1 180 2 1 +refdes=R2027 +T 62900 46400 5 10 0 1 180 2 1 +footprint=0603 +T 62300 46200 5 10 1 1 0 0 1 +value=50 +} +N 61600 46500 62000 46500 4 +N 62900 46500 63900 46500 4 +C 61300 45500 1 0 1 gnd-1.sym +N 61200 45800 61200 46000 4 diff --git a/usrp-hw/usrp/gnetlistrc b/usrp-hw/usrp/gnetlistrc new file mode 100644 index 000000000..6bbd9c292 --- /dev/null +++ b/usrp-hw/usrp/gnetlistrc @@ -0,0 +1,3 @@ +(component-library "../sym") +(component-library "../sym/generated") + diff --git a/usrp-hw/usrp/gschemrc b/usrp-hw/usrp/gschemrc new file mode 100644 index 000000000..6bbd9c292 --- /dev/null +++ b/usrp-hw/usrp/gschemrc @@ -0,0 +1,3 @@ +(component-library "../sym") +(component-library "../sym/generated") + diff --git a/usrp-hw/usrp/interface.sch b/usrp-hw/usrp/interface.sch new file mode 100644 index 000000000..f5b72f8a1 --- /dev/null +++ b/usrp-hw/usrp/interface.sch @@ -0,0 +1,450 @@ +v 20040111 1 +C 17200 44300 1 0 0 cy7c68013-tq100-CTRL.sym +{ +T 68200 74600 5 10 1 1 0 6 1 +refdes=U412 +} +C 114700 36300 1 0 1 cy7c68013-tq100-MISC.sym +{ +T 63800 66600 5 10 1 1 0 0 1 +refdes=U412 +} +C 16300 92600 1 180 1 cy7c68013-tq100-PC.sym +{ +T 67100 66400 5 10 1 1 180 0 1 +refdes=U412 +} +C 21600 93000 1 180 1 ep1c12-pq240-CFG.sym +{ +T 72500 67200 5 10 1 1 180 0 1 +refdes=U101 +} +C 7000 97300 1 180 1 ep1c12-pq240-JTAG.sym +{ +T 57800 69500 5 10 1 1 180 0 1 +refdes=U101 +} +C 59500 65900 1 0 0 24Cxx-1.sym +{ +T 60000 67100 5 10 1 1 0 0 1 +refdes=U413 +T 59500 65900 5 10 0 1 0 0 1 +footprint=SO8 +T 59800 65700 5 10 1 1 0 0 1 +device=24LC02B +T 59800 65300 5 10 1 1 0 0 1 +net=GND:4 +T 59800 65500 5 10 1 1 0 0 1 +net=DVDD:8 +} +C 70800 66000 1 90 0 generic-power.sym +{ +T 70550 66200 5 10 1 1 90 3 1 +net=DVDD:1 +} +C 70600 65900 1 270 0 gnd-1.sym +N 71300 65800 70900 65800 4 +N 70800 66200 71300 66200 4 +C 70600 66700 1 270 0 gnd-1.sym +N 71300 66600 70900 66600 4 +N 68000 65000 71300 65000 4 +N 68000 64600 71300 64600 4 +N 68000 64200 71300 64200 4 +N 71300 63800 68000 63800 4 +N 71300 63400 68000 63400 4 +C 68800 69900 1 0 0 generic-power.sym +{ +T 69000 70150 5 10 1 1 0 3 1 +net=DVDD:1 +} +C 68000 68100 1 270 0 led-1.sym +{ +T 67600 67300 5 10 1 1 0 0 1 +refdes=D402 +} +C 68600 67500 1 270 0 led-1.sym +{ +T 68200 66700 5 10 1 1 0 0 1 +refdes=D403 +} +C 70200 67300 1 90 0 resistor-1.sym +{ +T 70500 67700 5 10 1 1 180 0 1 +value=10K +T 70200 67300 5 10 0 1 90 0 1 +footprint=0603 +T 70200 67300 5 10 1 1 0 0 1 +refdes=R101 +} +C 69900 66700 1 90 0 resistor-1.sym +{ +T 70200 67100 5 10 1 1 180 0 1 +value=10K +T 69900 66700 5 10 0 1 90 0 1 +footprint=0603 +T 69900 66700 5 10 1 1 0 0 1 +refdes=R102 +} +C 69600 67000 1 90 0 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+date=$Date: 2004/10/27 23:28:42 $ +T 71400 60300 5 10 1 1 0 0 1 +rev=$Revision: 1.5 $ +T 71500 60000 5 10 1 1 0 0 1 +auth=$Author: matt $ +T 67300 60300 5 10 1 1 0 0 1 +fname=$RCSfile: interface.sch,v $ +T 70700 61000 8 14 1 1 0 4 1 +title=USRP FPGA/FX2 Interface +T 68300 60000 9 10 1 0 0 0 1 +2 +T 69100 60000 9 10 1 0 0 0 1 +4 +N 65000 64700 65500 64700 4 +N 65500 64700 65500 66800 4 +{ +T 65500 64800 5 10 1 1 90 0 1 +netname=MYSTERY_SIGNAL +} diff --git a/usrp-hw/usrp/netlist_cmd b/usrp-hw/usrp/netlist_cmd new file mode 100755 index 000000000..234de1238 --- /dev/null +++ b/usrp-hw/usrp/netlist_cmd @@ -0,0 +1,3 @@ +gnetlist -g pads -o usrp_mboard.net power.sch fpga.sch interface.sch dboard.sch +gnetlist -g partslist3 -o usrp_mboard.bom power.sch fpga.sch interface.sch dboard.sch + diff --git a/usrp-hw/usrp/power.sch b/usrp-hw/usrp/power.sch new file mode 100644 index 000000000..57cebf365 --- /dev/null +++ b/usrp-hw/usrp/power.sch @@ -0,0 +1,1983 @@ +v 20040111 1 +C 26600 109300 1 270 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