diff options
Diffstat (limited to 'gr-sounder/src/fpga/lib')
| -rw-r--r-- | gr-sounder/src/fpga/lib/Makefile.am | 30 | ||||
| -rw-r--r-- | gr-sounder/src/fpga/lib/dac_interface.v | 60 | ||||
| -rw-r--r-- | gr-sounder/src/fpga/lib/dacpll.v | 291 | ||||
| -rw-r--r-- | gr-sounder/src/fpga/lib/lfsr.v | 46 | ||||
| -rwxr-xr-x | gr-sounder/src/fpga/lib/lfsr_constants.v | 51 | ||||
| -rw-r--r-- | gr-sounder/src/fpga/lib/sounder.v | 86 | ||||
| -rw-r--r-- | gr-sounder/src/fpga/lib/sounder_rx.v | 84 | ||||
| -rw-r--r-- | gr-sounder/src/fpga/lib/sounder_tx.v | 45 |
8 files changed, 693 insertions, 0 deletions
diff --git a/gr-sounder/src/fpga/lib/Makefile.am b/gr-sounder/src/fpga/lib/Makefile.am new file mode 100644 index 000000000..450981f1a --- /dev/null +++ b/gr-sounder/src/fpga/lib/Makefile.am @@ -0,0 +1,30 @@ +# +# Copyright 2007 Free Software Foundation, Inc. +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +include $(top_srcdir)/Makefile.common + +EXTRA_DIST = \ + dac_interface.v \ + dacpll.v \ + sounder.v \ + sounder_rx.v \ + sounder_tx.v + diff --git a/gr-sounder/src/fpga/lib/dac_interface.v b/gr-sounder/src/fpga/lib/dac_interface.v new file mode 100644 index 000000000..b97ffa77f --- /dev/null +++ b/gr-sounder/src/fpga/lib/dac_interface.v @@ -0,0 +1,60 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2007 Corgan Enterprises LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +`include "../top/config.vh" + +module dac_interface(clk_i,rst_i,ena_i,strobe_i,tx_i_i,tx_q_i,tx_data_o,tx_sync_o); + input clk_i; + input rst_i; + input ena_i; + input strobe_i; + + input [15:0] tx_i_i; + input [15:0] tx_q_i; + + output [15:0] tx_data_o; + output tx_sync_o; + +`ifdef TX_RATE_MAX + wire clk128; + reg clk64_d; + reg [15:0] tx_data_o; + + // Create a 128 MHz clock + dacpll pll128(.areset(rst_i),.inclk0(clk_i),.c0(clk128)); + + // Register the clk64 clock in the clk128 domain + always @(posedge clk128) + clk64_d <= clk_i; + + // Register the tx data in the clk128 domain + always @(posedge clk128) + tx_data_o <= clk64_d ? tx_i_i : tx_q_i; + + assign tx_sync_o = clk64_d; + + +`else // !`ifdef TX_RATE_MAX + assign tx_data_o = strobe_i ? tx_q_i : tx_i_i; + assign tx_sync_o = strobe_i; +`endif // !`ifdef TX_RATE_MAX + +endmodule // dac_interface diff --git a/gr-sounder/src/fpga/lib/dacpll.v b/gr-sounder/src/fpga/lib/dacpll.v new file mode 100644 index 000000000..25f584f4f --- /dev/null +++ b/gr-sounder/src/fpga/lib/dacpll.v @@ -0,0 +1,291 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: dacpll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 7.0 Build 33 02/05/2007 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2007 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module dacpll ( + areset, + inclk0, + c0); + + input areset; + input inclk0; + output c0; + + wire [5:0] sub_wire0; + wire [0:0] sub_wire4 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire sub_wire2 = inclk0; + wire [1:0] sub_wire3 = {sub_wire4, sub_wire2}; + + altpll altpll_component ( + .inclk (sub_wire3), + .areset (areset), + .clk (sub_wire0), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b1), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbout (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 2, + altpll_component.clk0_phase_shift = "0000", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 15625, + altpll_component.intended_device_family = "Cyclone", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.ppf TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.inc FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.cmp FALSE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll.bsf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_inst.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_bb.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_waveforms.html TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL dacpll_wave*.jpg FALSE FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/gr-sounder/src/fpga/lib/lfsr.v b/gr-sounder/src/fpga/lib/lfsr.v new file mode 100644 index 000000000..6ae967ba9 --- /dev/null +++ b/gr-sounder/src/fpga/lib/lfsr.v @@ -0,0 +1,46 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2007 Corgan Enterprises LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +module lfsr(clk_i,rst_i,ena_i,strobe_i,mask_i,pn_o); + parameter width = 16; + + input clk_i; + input rst_i; + input ena_i; + input strobe_i; + input [width-1:0] mask_i; + + output pn_o; + + reg [width-1:0] shifter; + + wire parity = ^(shifter & mask_i); + + always @(posedge clk_i) + if (rst_i | ~ena_i) + shifter <= 1; + else + if (strobe_i) + shifter <= {shifter[width-2:0],parity}; + + assign pn_o = shifter[0]; + +endmodule // lfsr diff --git a/gr-sounder/src/fpga/lib/lfsr_constants.v b/gr-sounder/src/fpga/lib/lfsr_constants.v new file mode 100755 index 000000000..79fcb1a2b --- /dev/null +++ b/gr-sounder/src/fpga/lib/lfsr_constants.v @@ -0,0 +1,51 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2007 Corgan Enterprises LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +module lfsr_constants(degree_i,mask_o,len_o); + input wire [4:0] degree_i; + output reg [15:0] mask_o; + output wire [15:0] len_o; + + assign len_o = (16'b1 << degree_i) - 1; + + always @* + case (degree_i) + 5'd00: mask_o = 16'h0000; + 5'd01: mask_o = 16'h0001; + 5'd02: mask_o = 16'h0003; + 5'd03: mask_o = 16'h0005; + 5'd04: mask_o = 16'h0009; + 5'd05: mask_o = 16'h0012; + 5'd06: mask_o = 16'h0021; + 5'd07: mask_o = 16'h0041; + 5'd08: mask_o = 16'h008E; + 5'd09: mask_o = 16'h0108; + 5'd10: mask_o = 16'h0204; + 5'd11: mask_o = 16'h0402; + 5'd12: mask_o = 16'h0829; + 5'd13: mask_o = 16'h100D; + 5'd14: mask_o = 16'h2015; + 5'd15: mask_o = 16'h4001; + 5'd16: mask_o = 16'h8016; + default: mask_o = 16'h0000; + endcase // case(degree_i) + +endmodule // lfsr_constants diff --git a/gr-sounder/src/fpga/lib/sounder.v b/gr-sounder/src/fpga/lib/sounder.v new file mode 100644 index 000000000..ea4007cb8 --- /dev/null +++ b/gr-sounder/src/fpga/lib/sounder.v @@ -0,0 +1,86 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2007 Corgan Enterprises LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +`include "../../../../usrp/firmware/include/fpga_regs_common.v" +`include "../../../../usrp/firmware/include/fpga_regs_standard.v" + +module sounder(clk_i,saddr_i,sdata_i,s_strobe_i,tx_rst_i,tx_enable_i,tx_strobe_i, + tx_dac_i_o,tx_dac_q_o, + rx_rst_i,rx_enable_i,rx_strobe_i,rx_strobe_o, + rx_adc_i_i,rx_adc_q_i,rx_imp_i_o,rx_imp_q_o); + + // System interface + input clk_i; // Master clock @ 64 MHz + input [6:0] saddr_i; // Configuration bus address + input [31:0] sdata_i; // Configuration bus data + input s_strobe_i; // Configuration bus write + + // Transmit subsystem + input tx_rst_i; // Independent subsystem reset + input tx_enable_i; // Turn on transmitter functionality + input tx_strobe_i; // Generate an transmitter output sample + output [15:0] tx_dac_i_o; // I channel transmitter output to DAC + output [15:0] tx_dac_q_o; // Q channel transmitter output to DAC + + // Receive subsystem + input rx_rst_i; // Independent subsystem reset + input rx_enable_i; // Turn on receiver functionality + input rx_strobe_i; // Indicates receive sample ready from ADC + output rx_strobe_o; // Indicates output samples ready for Rx FIFO + input [15:0] rx_adc_i_i; // I channel input from ADC + input [15:0] rx_adc_q_i; // Q channel input from ADC + output [15:0] rx_imp_i_o; // I channel impulse response to Rx FIFO + output [15:0] rx_imp_q_o; // Q channel impulse response to Rx FIFO + + // Configuration + wire [4:0] degree; // LFSR register length + wire [15:0] mask; // LFSR parity mask + wire [15:0] len; // PN code sequence length + wire loopback; // Enable digital loopback + + // Loopback implementation + wire [15:0] tx_i, tx_q, rx_i, rx_q; // Internal transmit and receive data bus + + assign tx_dac_i_o = loopback ? 16'b0 : tx_i; + assign tx_dac_q_o = loopback ? 16'b0 : tx_q; + assign rx_i = loopback ? tx_i : rx_adc_i_i; + assign rx_q = loopback ? tx_q : rx_adc_q_i; + + setting_reg #(`FR_USER_0) sr_lfsr_degree + ( .clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(degree) ); + + setting_reg #(`FR_USER_1) sr_mode + ( .clock(clk_i),.reset(1'b0),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i), + .out({loopback}) ); + + lfsr_constants constants(.degree_i(degree),.mask_o(mask),.len_o(len)); + + sounder_tx transmitter + ( .clk_i(clk_i),.rst_i(tx_rst_i),.ena_i(tx_enable_i),.strobe_i(tx_strobe_i),.mask_i(mask), + .tx_i_o(tx_i),.tx_q_o(tx_q) ); + + sounder_rx receiver + ( .clk_i(clk_i),.rst_i(rx_rst_i),.ena_i(rx_enable_i), + .rx_strobe_i(rx_strobe_i),.tx_strobe_i(tx_strobe_i),.mask_i(mask),.len_i(len), + .rx_in_i_i(rx_i),.rx_in_q_i(rx_q),.rx_i_o(rx_imp_i_o),.rx_q_o(rx_imp_q_o), + .rx_strobe_o(rx_strobe_o) ); + +endmodule // sounder diff --git a/gr-sounder/src/fpga/lib/sounder_rx.v b/gr-sounder/src/fpga/lib/sounder_rx.v new file mode 100644 index 000000000..b7c5f4878 --- /dev/null +++ b/gr-sounder/src/fpga/lib/sounder_rx.v @@ -0,0 +1,84 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2007 Corgan Enterprises LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +module sounder_rx(clk_i,rst_i,ena_i,rx_strobe_i,tx_strobe_i,mask_i,len_i, + rx_in_i_i,rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o); + + input clk_i; // Master clock + input rst_i; // Subsystem reset + input ena_i; // Subsystem enable + input rx_strobe_i; // Strobe every received sample + input tx_strobe_i; // Strobe every transmitted sample + + input [15:0] mask_i; // PN code LFSR mask + input [15:0] len_i; // PN code LFSR sequence length + input [15:0] rx_in_i_i; // I channel on receive + input [15:0] rx_in_q_i; // Q channel on receive + + output [15:0] rx_i_o; // I channel of impulse response + output [15:0] rx_q_o; // Q channel of impulse response + output rx_strobe_o; // Impulse response value ready + + // LFSR phase counter + reg [15:0] count; + wire cycle = (count == (len_i - 1)); + + always @(posedge clk_i) + if (rst_i | ~ena_i) + count <= 16'b0; + else + if (cycle) + count <= 16'b0; + else + count <= count + 16'b1; + + // Retard LFSR phase once per cycle + wire lfsr_strobe = (tx_strobe_i & ~cycle); + + // Recreate local reference of transmitted PN code + wire pn; + lfsr reference + ( .clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(lfsr_strobe),.mask_i(mask_i),.pn_o(pn) ); + + wire [31:0] rx_i_ext, rx_q_ext; + sign_extend #(16,32) i_extend(rx_in_i_i, rx_i_ext); + sign_extend #(16,32) q_extend(rx_in_q_i, rx_q_ext); + + reg [31:0] accum; + always @(posedge clk_i) + if (rst_i | ~ena_i) + accum <= 32'b0; + else + if (rx_strobe_i) + if (cycle) + accum <= 32'b0; + else + if (pn) + accum <= accum + rx_i_ext; + else + accum <= accum - rx_i_ext; + + assign rx_i_o = accum[31:16]; + assign rx_q_o = accum[15:0]; + assign rx_strobe_o = rx_strobe_i & cycle; + +endmodule // sounder_rx + diff --git a/gr-sounder/src/fpga/lib/sounder_tx.v b/gr-sounder/src/fpga/lib/sounder_tx.v new file mode 100644 index 000000000..d5300fecb --- /dev/null +++ b/gr-sounder/src/fpga/lib/sounder_tx.v @@ -0,0 +1,45 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2007 Corgan Enterprises LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA +// + +`include "../../../../usrp/firmware/include/fpga_regs_common.v" +`include "../../../../usrp/firmware/include/fpga_regs_standard.v" + +`define MAX_VALUE 16'h7FFF // 2s complement +`define MIN_VALUE 16'h8000 + +module sounder_tx(clk_i,rst_i,ena_i,strobe_i,mask_i,tx_i_o,tx_q_o); + input clk_i; + input rst_i; + input ena_i; + input strobe_i; + input [15:0] mask_i; + output [15:0] tx_i_o; + output [15:0] tx_q_o; + + wire pn; + + lfsr pn_code + ( .clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i),.mask_i(mask_i),.pn_o(pn) ); + + assign tx_i_o = pn ? `MAX_VALUE : `MIN_VALUE; // Bipolar + assign tx_q_o = 16'b0; + +endmodule // sounder_tx |