Fix for fifo overruns on eth rx in full duplex. Now send re-pause long before pause is done. Reenabled RMON for the time being

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10746 221aa14e-8319-0410-a670-987f0aec2ac5

3 files changed, 14 insertions, 6 deletions

diff --git a/usrp2/fpga/eth/rtl/verilog/MAC_top.v b/usrp2/fpga/eth/rtl/verilog/MAC_top.v
index 13f17aa13..4e5b0db0a 100644
--- a/usrp2/fpga/eth/rtl/verilog/MAC_top.v
+++ b/usrp2/fpga/eth/rtl/verilog/MAC_top.v
@@ -137,7 +137,7 @@ module MAC_top
    wire [15:0] rx_fifo_space;

    wire        pause_apply, pause_quanta_sub;

    wire        xon_gen, xoff_gen, xon_gen_complete, xoff_gen_complete;

-   wire [15:0] fc_hwmark, fc_lwmark;

+   wire [15:0] fc_hwmark, fc_lwmark, fc_padtime;

    

   //PHY interface

   wire [7:0]  MTxD;

@@ -332,6 +332,7 @@ module MAC_top
       .pause_quanta_set         ( pause_quanta_set          ),

       .fc_hwmark (fc_hwmark),

       .fc_lwmark (fc_lwmark),

+      .fc_padtime (fc_padtime),

       // From RX side

       .rx_clk(MAC_rx_clk_div),

       .rx_fifo_space (rx_fifo_space),    // Decide if we need to send a PAUSE

@@ -342,7 +343,7 @@ module MAC_top
       .xoff_gen_complete (xoff_gen_complete), 

       .xon_gen_complete(xon_gen_complete)

       );

-/*   

+

   RMON U_RMON(

     .Clk                 ( CLK_I                ),

     .Reset               ( RST_I                ),

@@ -365,7 +366,7 @@ module MAC_top
     .CPU_rd_grant        ( CPU_rd_grant         ),

     .CPU_rd_dout         ( CPU_rd_dout          )

   );

-*/

+

    Phy_int U_Phy_int(

     .rst_mac_rx  ( rst_mac_rx   ),

     .rst_mac_tx  ( rst_mac_tx   ),

@@ -478,6 +479,7 @@ module MAC_top
     .tx_pause_en              ( tx_pause_en               ),

     .fc_hwmark                ( fc_hwmark                 ),

     .fc_lwmark                ( fc_lwmark                 ),

+    .fc_padtime               ( fc_padtime                ),

 		    

     // RMON host interface

     .CPU_rd_addr              ( CPU_rd_addr               ),

@@ -507,7 +509,7 @@ module MAC_top
     .UpdateMIIRX_DATAReg      ( UpdateMIIRX_DATAReg       )

   );

 

-   assign     debug0 = {xon_gen, xoff_gen, Tx_en, Rx_dv};

+   assign     debug0 = {xon_gen, xoff_gen, xon_gen_complete, xoff_gen_complete, debug_rx[3:0]};

    //assign     debug0 = {{debug_rx[3:0], xon_gen, xon_gen_complete, xoff_gen, xoff_gen_complete},

    //			{1'b0,Rx_mac_err,Rx_mac_empty,Rx_mac_rd,Rx_mac_sop,Rx_mac_eop,Rx_mac_BE[1:0]},

    //			{rx_fifo_space}};

diff --git a/usrp2/fpga/eth/rtl/verilog/Reg_int.v b/usrp2/fpga/eth/rtl/verilog/Reg_int.v
index f1bea2316..bdf73d8e5 100644
--- a/usrp2/fpga/eth/rtl/verilog/Reg_int.v
+++ b/usrp2/fpga/eth/rtl/verilog/Reg_int.v
@@ -43,6 +43,7 @@ module Reg_int (
   output            tx_pause_en,

   output [15:0]     fc_hwmark,

   output [15:0]     fc_lwmark,

+  output [15:0]     fc_padtime,

 		

   // RMON host interface

   output [5:0]      CPU_rd_addr,

@@ -141,6 +142,9 @@ module Reg_int (
   RegCPUData #( 13 ) U_0_037( MIIADDRESS                   , 7'd037, 13'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[12:0] );

   RegCPUData #( 16 ) U_0_038( MIITX_DATA                   , 7'd038, 16'h0000, RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );

 

+   // New FC register

+  RegCPUData #( 16 ) U_0_041( fc_padtime                   , 7'd041, 1'h0,     RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );

+

   // Asserted in first clock of 2-cycle access, negated otherwise

   wire Access = ~ACK_O & STB_I & CYC_I;

 

@@ -231,6 +235,7 @@ module Reg_int (
             7'd38: DAT_O <= MIITX_DATA;

             7'd39: DAT_O <= MIIRX_DATA;

             7'd40: DAT_O <= MIISTATUS;

+            7'd41: DAT_O <= fc_padtime;

           endcase

       end

 

diff --git a/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v b/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v
index 7ded9e08b..6654c626b 100644
--- a/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v
+++ b/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v
@@ -8,6 +8,7 @@ module flow_ctrl_rx
    input [15:0] pause_quanta_set,

    input [15:0] fc_hwmark,

    input [15:0] fc_lwmark,

+   input [15:0] fc_padtime,

    // From MAC_rx_ctrl

    input        rx_clk,

    input [15:0] rx_fifo_space,

@@ -70,13 +71,13 @@ module flow_ctrl_rx
      else if (xon_int | xon_int_d1)

        xon_gen     <=1;                     

 

-   wire [15:0] pq_reduced = pause_quanta_set - 2;

+   wire [21:0] pq_reduced = {pause_quanta_set,6'd0} - {6'd0,fc_padtime};

    

    always @(posedge tx_clk or posedge rst)

      if(rst)

        countdown <= 0;

      else if(xoff_gen)

-       countdown <= {pq_reduced,6'd0};

+       countdown <= pq_reduced;

      else if(xon_gen)

        countdown <= 0;

      else if(countdown != 0)