diff options
| author | Tom | 2009-10-06 10:40:39 -0700 |
|---|---|---|
| committer | Tom | 2009-10-06 10:40:39 -0700 |
| commit | bbd3df51732b2b63ae9d20e9fddd12229cf6b2ef (patch) | |
| tree | dbf63fb638238e389ad970f2f4443299491e8fc6 /usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v | |
| parent | 314726ae7457b37f442a2751285b75b0d616c0f4 (diff) | |
| parent | 3f8026a00c261c788357b3a04f5b338a6cda4d0e (diff) | |
| download | gnuradio-bbd3df51732b2b63ae9d20e9fddd12229cf6b2ef.tar.gz gnuradio-bbd3df51732b2b63ae9d20e9fddd12229cf6b2ef.tar.bz2 gnuradio-bbd3df51732b2b63ae9d20e9fddd12229cf6b2ef.zip | |
Merge branch 'master' into sync
Conflicts:
gr-utils/src/python/gr_plot_qt.py
gr-utils/src/python/pyqt_plot.py
gr-utils/src/python/pyqt_plot.ui
Diffstat (limited to 'usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v')
| -rw-r--r-- | usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v | 71 |
1 files changed, 0 insertions, 71 deletions
diff --git a/usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v b/usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v deleted file mode 100644 index 994907d44..000000000 --- a/usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v +++ /dev/null @@ -1,71 +0,0 @@ -//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_clk_div2.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
-//// ////
-//// Author(s): ////
-//// - Jon Gao (gaojon@yahoo.com) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: CLK_DIV2.v,v $
-// Revision 1.3 2006/01/19 14:07:56 maverickist
-// verification is complete.
-//
-// Revision 1.2 2005/12/16 06:44:20 Administrator
-// replaced tab with space.
-// passed 9.6k length frame test.
-//
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
-// no message
-//
-
-
-//////////////////////////////////////////////////////////////////////
-// This file can only used for simulation .
-// You need to replace it with your own element according to technology
-//////////////////////////////////////////////////////////////////////
-
-module eth_clk_div2 (
- input Reset,
- input IN,
- output reg OUT
-);
-
-always @ (posedge IN or posedge Reset)
- if (Reset)
- OUT <= 0;
- else
- OUT <= ~OUT;
-
-endmodule
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