From ab47612cf0b6f2226d192fbc9db80c5b225a4f2d Mon Sep 17 00:00:00 2001
From: Matt Ettus
Date: Thu, 10 Sep 2009 23:11:44 -0700
Subject: Remove old mac.  Good riddance.

---
 usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v | 71 --------------------------
 1 file changed, 71 deletions(-)
 delete mode 100644 usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v

(limited to 'usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v')

diff --git a/usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v b/usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v
deleted file mode 100644
index 994907d44..000000000
--- a/usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v
+++ /dev/null
@@ -1,71 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  eth_clk_div2.v                                              ////
-////                                                              ////
-////  This file is part of the Ethernet IP core project           ////
-////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - Jon Gao (gaojon@yahoo.com)                            ////
-////                                                              ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// Copyright (C) 2001 Authors                                   ////
-////                                                              ////
-//// This source file may be used and distributed without         ////
-//// restriction provided that this copyright statement is not    ////
-//// removed from the file and that any derivative work contains  ////
-//// the original copyright notice and the associated disclaimer. ////
-////                                                              ////
-//// This source file is free software; you can redistribute it   ////
-//// and/or modify it under the terms of the GNU Lesser General   ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any   ////
-//// later version.                                               ////
-////                                                              ////
-//// This source is distributed in the hope that it will be       ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
-//// PURPOSE.  See the GNU Lesser General Public License for more ////
-//// details.                                                     ////
-////                                                              ////
-//// You should have received a copy of the GNU Lesser General    ////
-//// Public License along with this source; if not, download it   ////
-//// from http://www.opencores.org/lgpl.shtml                     ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-//                                                                    
-// CVS Revision History                                               
-//                                                                    
-// $Log: CLK_DIV2.v,v $
-// Revision 1.3  2006/01/19 14:07:56  maverickist
-// verification is complete.
-//
-// Revision 1.2  2005/12/16 06:44:20  Administrator
-// replaced tab with space.
-// passed 9.6k length frame test.
-//
-// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
-// no message
-// 
-
-
-//////////////////////////////////////////////////////////////////////
-// This file can only used for simulation .
-// You need to replace it with your own element according to technology
-//////////////////////////////////////////////////////////////////////
-
-module eth_clk_div2 (
-  input       Reset,
-  input       IN,
-  output  reg OUT
-);
-
-always @ (posedge IN or posedge Reset)
-  if (Reset)
-    OUT <= 0;
-  else
-    OUT <= ~OUT;
-    
-endmodule
-- 
cgit