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| author | Johnathan Corgan | 2010-02-28 12:47:43 -0800 |
|---|---|---|
| committer | Johnathan Corgan | 2010-02-28 12:47:43 -0800 |
| commit | a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 (patch) | |
| tree | 77121ca27b951f9bd687dbba33f6a9383ac74d5a /usrp2/fpga/control_lib/SYSCTRL.sav | |
| parent | db29a2cfc18554ae0a3c55a4e13dc4cbfa86317f (diff) | |
| download | gnuradio-a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3.tar.gz gnuradio-a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3.tar.bz2 gnuradio-a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3.zip | |
Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git
...under the 'usrp1' and 'usrp2' top-level directories.
Diffstat (limited to 'usrp2/fpga/control_lib/SYSCTRL.sav')
| -rw-r--r-- | usrp2/fpga/control_lib/SYSCTRL.sav | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/usrp2/fpga/control_lib/SYSCTRL.sav b/usrp2/fpga/control_lib/SYSCTRL.sav deleted file mode 100644 index 43bfef10e..000000000 --- a/usrp2/fpga/control_lib/SYSCTRL.sav +++ /dev/null @@ -1,24 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-11.026821 2450 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -system_control_tb.aux_clk -@29 -system_control_tb.clk_fpga -@28 -system_control_tb.dsp_clk -system_control_tb.dsp_rst -system_control_tb.proc_rst -system_control_tb.rl_done -system_control_tb.rl_rst -system_control_tb.wb_clk -system_control_tb.wb_rst -system_control_tb.system_control.POR -@22 -system_control_tb.system_control.POR_ctr[3:0] -@28 -system_control_tb.clock_ready -system_control_tb.system_control.half_clk -system_control_tb.system_control.fin_ret_half -system_control_tb.system_control.fin_ret_aux -system_control_tb.system_control.gate_dsp_clk |