From a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 Mon Sep 17 00:00:00 2001
From: Johnathan Corgan
Date: Sun, 28 Feb 2010 12:47:43 -0800
Subject: Remove usrp1 and usrp2 FPGA files.  These are now hosted at:

git://ettus.sourcerepo.com/ettus/fpga.git

...under the 'usrp1' and 'usrp2' top-level directories.
---
 usrp2/fpga/control_lib/SYSCTRL.sav | 24 ------------------------
 1 file changed, 24 deletions(-)
 delete mode 100644 usrp2/fpga/control_lib/SYSCTRL.sav

(limited to 'usrp2/fpga/control_lib/SYSCTRL.sav')

diff --git a/usrp2/fpga/control_lib/SYSCTRL.sav b/usrp2/fpga/control_lib/SYSCTRL.sav
deleted file mode 100644
index 43bfef10e..000000000
--- a/usrp2/fpga/control_lib/SYSCTRL.sav
+++ /dev/null
@@ -1,24 +0,0 @@
-[size] 1400 971
-[pos] -1 -1
-*-11.026821 2450 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-@28
-system_control_tb.aux_clk
-@29
-system_control_tb.clk_fpga
-@28
-system_control_tb.dsp_clk
-system_control_tb.dsp_rst
-system_control_tb.proc_rst
-system_control_tb.rl_done
-system_control_tb.rl_rst
-system_control_tb.wb_clk
-system_control_tb.wb_rst
-system_control_tb.system_control.POR
-@22
-system_control_tb.system_control.POR_ctr[3:0]
-@28
-system_control_tb.clock_ready
-system_control_tb.system_control.half_clk
-system_control_tb.system_control.fin_ret_half
-system_control_tb.system_control.fin_ret_aux
-system_control_tb.system_control.gate_dsp_clk
-- 
cgit