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authorJohnathan Corgan2010-02-28 12:47:43 -0800
committerJohnathan Corgan2010-02-28 12:47:43 -0800
commita2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 (patch)
tree77121ca27b951f9bd687dbba33f6a9383ac74d5a /usrp/fpga/models/bustri.v
parentdb29a2cfc18554ae0a3c55a4e13dc4cbfa86317f (diff)
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Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git ...under the 'usrp1' and 'usrp2' top-level directories.
Diffstat (limited to 'usrp/fpga/models/bustri.v')
-rw-r--r--usrp/fpga/models/bustri.v17
1 files changed, 0 insertions, 17 deletions
diff --git a/usrp/fpga/models/bustri.v b/usrp/fpga/models/bustri.v
deleted file mode 100644
index 6e5a0f74c..000000000
--- a/usrp/fpga/models/bustri.v
+++ /dev/null
@@ -1,17 +0,0 @@
-
-// Model for tristate bus on altera
-// FIXME do we really need to use a megacell for this?
-
-module bustri (data,
- enabledt,
- tridata);
-
- input [15:0] data;
- input enabledt;
- inout [15:0] tridata;
-
- assign tridata = enabledt ? data :16'bz;
-
-endmodule // bustri
-
-