diff options
| author | jcorgan | 2008-07-25 00:02:08 +0000 |
|---|---|---|
| committer | jcorgan | 2008-07-25 00:02:08 +0000 |
| commit | 777479a5e44c5aadba2c3b1dd6416ee897853042 (patch) | |
| tree | 291a9f982f29c84f727befb79850877000224b55 /gr-gpio/src/fpga/top/usrp_gpio.qsf | |
| parent | e01ee204490910b3712eb030e2d398498802128d (diff) | |
| download | gnuradio-777479a5e44c5aadba2c3b1dd6416ee897853042.tar.gz gnuradio-777479a5e44c5aadba2c3b1dd6416ee897853042.tar.bz2 gnuradio-777479a5e44c5aadba2c3b1dd6416ee897853042.zip | |
Adds alternative integrate and dump decimator to gr-gpio.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9009 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'gr-gpio/src/fpga/top/usrp_gpio.qsf')
| -rw-r--r-- | gr-gpio/src/fpga/top/usrp_gpio.qsf | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/gr-gpio/src/fpga/top/usrp_gpio.qsf b/gr-gpio/src/fpga/top/usrp_gpio.qsf index 4132dccad..cfdcd552b 100644 --- a/gr-gpio/src/fpga/top/usrp_gpio.qsf +++ b/gr-gpio/src/fpga/top/usrp_gpio.qsf @@ -375,6 +375,9 @@ set_global_assignment -name VERILOG_FILE ../lib/gpio_input.v set_global_assignment -name VERILOG_FILE ../lib/io_pins.v
set_global_assignment -name VERILOG_FILE ../lib/rx_chain_dig.v
set_global_assignment -name VERILOG_FILE ../lib/tx_chain_dig.v
+set_global_assignment -name VERILOG_FILE ../lib/integrator.v
+set_global_assignment -name VERILOG_FILE ../lib/integ_shifter.v
+set_global_assignment -name VERILOG_FILE ../lib/rx_chain.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cic_dec_shifter.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
@@ -394,7 +397,6 @@ set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_inter set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cic_int_shifter.v
-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_chain.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v
set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v
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