Adds alternative integrate and dump decimator to gr-gpio.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9009 221aa14e-8319-0410-a670-987f0aec2ac5

14 files changed, 395 insertions, 20 deletions

diff --git a/gr-gpio/src/fpga/Makefile.am b/gr-gpio/src/fpga/Makefile.am
index 363f19f3d..2b6f2585e 100644
--- a/gr-gpio/src/fpga/Makefile.am
+++ b/gr-gpio/src/fpga/Makefile.am
@@ -19,4 +19,5 @@
 # Boston, MA 02110-1301, USA.
 # 
 
-SUBDIRS = include lib top
+SUBDIRS = include lib top rbf
+
diff --git a/gr-gpio/src/fpga/include/Makefile.am b/gr-gpio/src/fpga/include/Makefile.am
index 70920c3b1..e4baf3506 100644
--- a/gr-gpio/src/fpga/include/Makefile.am
+++ b/gr-gpio/src/fpga/include/Makefile.am
@@ -20,5 +20,6 @@
 # 
 
 EXTRA_DIST = \
-    common_config_2rxhb_2txdig.vh \
+    common_config_2rxhb_2tx_dig.vh \
+    common_config_2rxint_2tx_dig.vh \
     common_config_bottom.vh
diff --git a/gr-gpio/src/fpga/include/common_config_2rxhb_2txdig.vh b/gr-gpio/src/fpga/include/common_config_2rxhb_2tx_dig.vh
index 580082c92..580082c92 100644
--- a/gr-gpio/src/fpga/include/common_config_2rxhb_2txdig.vh
+++ b/gr-gpio/src/fpga/include/common_config_2rxhb_2tx_dig.vh
diff --git a/gr-gpio/src/fpga/include/common_config_2rxint_2tx_dig.vh b/gr-gpio/src/fpga/include/common_config_2rxint_2tx_dig.vh
new file mode 100644
index 000000000..01995543b
--- /dev/null
+++ b/gr-gpio/src/fpga/include/common_config_2rxint_2tx_dig.vh
@@ -0,0 +1,77 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2006,2007 Matt Ettus
+//  Copyright (C) 2008 Corgan Enterprises LLC
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// ------------------------------------------------------------
+// If TX_ON is not defined, there is *no* transmit circuitry built
+  `define TX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD
+// to respectively enable 1, 2 or 4 transmit channels.
+// [Please note that only TX_SINGLE and TX_DUAL are currently valid]
+//`define TX_SINGLE
+  `define TX_DUAL
+//`define TX_QUAD
+
+// ------------------------------------------------------------
+// If TX_DIG_ON is defined each transmit channel sends its I lsb and Q lsb to gpio pins
+// The lsb bits of the analog output signal are truncated
+  `define TX_DIG_ON
+// ------------------------------------------------------------
+// Define TX_HB_ON to enable the transmit halfband filter
+// [Not implemented]
+//`define TX_HB_ON
+
+// ------------------------------------------------------------
+// IF RX_ON is not defined, there is *no* receive circuitry built
+  `define RX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD
+// to respectively define 1, 2 or 4 receive channels.
+
+//`define RX_SINGLE
+  `define RX_DUAL
+//`define RX_QUAD
+
+// ------------------------------------------------------------
+// Define RX_HB_ON to enable the receive halfband filter
+// `define RX_HB_ON
+
+// ------------------------------------------------------------
+// Define RX_NCO_ON to enable the receive Numerical Controlled Osc
+  `define RX_NCO_ON
+
+// ------------------------------------------------------------
+// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter
+// This is mutually exclusive with RX_INTEG_ON
+//  `define RX_CIC_ON
+
+// ------------------------------------------------------------
+// Define RX_INTEG_ON to enable the receive single stage integrate and dump
+// This is mutually exclusive with RX_CIC_ON
+  `define RX_INTEG_ON
+
+// ------------------------------------------------------------
+// If RX_DIG_ON is defined each receive channel sends has its I lsb and Q lsb replaced by digital input from gpio pins
+// So the analog signals are truncated to 15  bits 
+  `define RX_DIG_ON
diff --git a/gr-gpio/src/fpga/lib/Makefile.am b/gr-gpio/src/fpga/lib/Makefile.am
index db5fbd4ad..2bed79c29 100644
--- a/gr-gpio/src/fpga/lib/Makefile.am
+++ b/gr-gpio/src/fpga/lib/Makefile.am
@@ -25,4 +25,7 @@ EXTRA_DIST = 		\
     gpio_input.v 	\
     io_pins.v		\
     rx_chain_dig.v 	\
-    tx_chain_dig.v
\ No newline at end of file
+    tx_chain_dig.v      \
+    integrator.v        \
+    integ_shifter.v     \
+    rx_chain.v
\ No newline at end of file
diff --git a/gr-gpio/src/fpga/lib/integ_shifter.v b/gr-gpio/src/fpga/lib/integ_shifter.v
new file mode 100644
index 000000000..1ad0504cb
--- /dev/null
+++ b/gr-gpio/src/fpga/lib/integ_shifter.v
@@ -0,0 +1,68 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//  Copyright (C) 2008 Corgan Enterprises LLC
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+// NOTE: This only works for a max decim rate of 256
+// NOTE: Signal "rate" is ONE LESS THAN the actual rate
+
+module integ_shifter(rate,signal_in,signal_out);
+    parameter bw = 16;
+    parameter maxbitgain = 8;
+   
+    input [7:0] rate;
+    input       wire [bw+maxbitgain-1:0] signal_in;
+    output      reg [bw-1:0] signal_out;
+
+    reg [3:0] bitgain;
+
+    // Nearest without overflow -- ceil(log2(rate+1))
+    always @*
+      if (rate >= 8'd128)
+        bitgain = 8;
+      else if (rate >= 8'd64)
+        bitgain = 7;
+      else if (rate >= 8'd32)
+        bitgain = 6;
+      else if (rate >= 8'd16)
+        bitgain = 5;
+      else if (rate >= 8'd8)
+        bitgain = 4;
+      else if (rate >= 8'd4)
+        bitgain = 3;
+      else if (rate >= 8'd2)
+        bitgain = 2;
+      else
+        bitgain = 1;
+
+   always @*
+     case(bitgain)
+       5'd1 : signal_out = signal_in[1+bw-1:1];
+       5'd2 : signal_out = signal_in[2+bw-1:2];
+       5'd3 : signal_out = signal_in[3+bw-1:3];
+       5'd4 : signal_out = signal_in[4+bw-1:4];
+       5'd5 : signal_out = signal_in[5+bw-1:5];
+       5'd6 : signal_out = signal_in[6+bw-1:6];
+       5'd7 : signal_out = signal_in[7+bw-1:7];
+       default : signal_out = signal_in[8+bw-1:8];
+     endcase // case(shift)
+
+endmodule // integ_shifter
diff --git a/gr-gpio/src/fpga/lib/integrator.v b/gr-gpio/src/fpga/lib/integrator.v
new file mode 100644
index 000000000..22357a565
--- /dev/null
+++ b/gr-gpio/src/fpga/lib/integrator.v
@@ -0,0 +1,75 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//  Copyright (C) 2008 Corgan Enterprises LLC
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Integrate and dump decimation filter
+// 
+// Functionally equivalent to single-stage CIC decimator, simpler code
+// Results in single sample impulse response at decimated rate
+
+module integrator
+  ( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
+   parameter bw = 16;
+   parameter maxbitgain = 8;
+   
+   input       clock;
+   input       reset;
+   input       enable;
+   input [7:0] rate;
+   input       strobe_in;
+   input       strobe_out;	
+
+   input  [bw-1:0] signal_in;
+   wire   [bw-1:0] signal_out_unreg;
+   output [bw-1:0] signal_out;
+   reg    [bw-1:0] signal_out;
+
+   wire [bw+maxbitgain-1:0] signal_in_ext;
+   reg  [bw+maxbitgain-1:0] accum;
+   reg  [bw+maxbitgain-1:0] dump;
+
+   sign_extend #(bw,bw+maxbitgain) 
+      ext_input (.in(signal_in),.out(signal_in_ext));
+   
+   // Integrate samples, dump on strobe out
+   always @(posedge clock)
+     if (reset | ~enable)
+       begin
+	 accum <= 0;
+	 dump <= 0;
+       end
+     else if (enable && strobe_in)
+        if (~strobe_out)
+	   accum <= accum + signal_in_ext;
+        else
+	   begin
+	     dump <= accum;
+	     accum <= signal_in_ext;
+           end
+   
+   // Normalize for integration bit gain
+   integ_shifter #(bw)
+	shifter(rate,dump,signal_out_unreg);
+
+   always @(posedge clock)
+     signal_out <= #1 signal_out_unreg;
+   
+endmodule // integrator
diff --git a/gr-gpio/src/fpga/lib/rx_chain.v b/gr-gpio/src/fpga/lib/rx_chain.v
new file mode 100644
index 000000000..172e978de
--- /dev/null
+++ b/gr-gpio/src/fpga/lib/rx_chain.v
@@ -0,0 +1,121 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Following defines conditionally include RX path circuitry
+
+`include "config.vh"	// resolved relative to project root
+
+module rx_chain
+  (input clock,
+   input reset,
+   input enable,
+   input wire [7:0] decim_rate,
+   input sample_strobe,
+   input decimator_strobe,
+   output wire hb_strobe,
+   input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
+   input wire [15:0] i_in,
+   input wire [15:0] q_in,
+   output wire [15:0] i_out,
+   output wire [15:0] q_out,
+   output wire [15:0] debugdata,output wire [15:0] debugctrl
+   );
+
+   parameter FREQADDR = 0;
+   parameter PHASEADDR = 0;
+   
+   wire [31:0] phase;
+   wire [15:0] bb_i, bb_q;
+   wire [15:0] hb_in_i, hb_in_q;
+   
+   assign	debugdata = hb_in_i;
+
+`ifdef RX_NCO_ON
+    phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
+     (.clk(clock),.reset(reset),.enable(enable),
+      .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+      .strobe(sample_strobe),.phase(phase) );
+
+   cordic rx_cordic
+     ( .clock(clock),.reset(reset),.enable(enable), 
+       .xi(i_in),.yi(q_in),.zi(phase[31:16]),
+       .xo(bb_i),.yo(bb_q),.zo() );
+`else
+   assign bb_i = i_in;
+   assign bb_q = q_in;
+   assign sample_strobe = 1;
+`endif // !`ifdef RX_NCO_ON
+
+`ifdef RX_INTEG_ON
+   integrator integ_decim_i_0
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+       .signal_in(bb_i),.signal_out(i_out) );
+
+   assign hb_strobe = decimator_strobe;
+`else
+`ifdef RX_CIC_ON
+   cic_decim cic_decim_i_0
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+       .signal_in(bb_i),.signal_out(hb_in_i) );
+`else
+   assign hb_in_i = bb_i;
+   assign decimator_strobe = sample_strobe;
+`endif
+   
+`ifdef RX_HB_ON
+   halfband_decim hbd_i_0
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .strobe_in(decimator_strobe),.strobe_out(hb_strobe),
+       .data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
+`else
+   assign i_out = hb_in_i;
+   assign hb_strobe = decimator_strobe;
+`endif
+`endif // RX_INTEG_ON
+
+`ifdef RX_INTEG_ON
+   integrator integ_decim_q_0
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+       .signal_in(bb_q),.signal_out(q_out) );
+`else   
+`ifdef RX_CIC_ON
+   cic_decim cic_decim_q_0
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
+       .signal_in(bb_q),.signal_out(hb_in_q) );
+`else
+   assign hb_in_q = bb_q;
+`endif
+
+`ifdef RX_HB_ON
+   halfband_decim hbd_q_0
+     ( .clock(clock),.reset(reset),.enable(enable),
+       .strobe_in(decimator_strobe),.strobe_out(),
+       .data_in(hb_in_q),.data_out(q_out) );   
+`else
+   assign q_out = hb_in_q;
+`endif
+`endif // RX_INTEG_ON
+
+endmodule // rx_chain
diff --git a/gr-gpio/src/fpga/rbf/Makefile.am b/gr-gpio/src/fpga/rbf/Makefile.am
new file mode 100644
index 000000000..0bc4311a1
--- /dev/null
+++ b/gr-gpio/src/fpga/rbf/Makefile.am
@@ -0,0 +1,37 @@
+#
+# Copyright 2008 Free Software Foundation, Inc.
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+include $(top_srcdir)/Makefile.common
+
+RBFS = \
+	std_2rxhb_2tx_dig.rbf \
+	std_2rxint_2tx_dig.rbf
+
+datadir = $(prefix)/share/usrp
+datarev2dir = $(datadir)/rev2
+datarev4dir = $(datadir)/rev4
+
+datarev2_DATA = $(RBFS)
+
+datarev4_DATA = $(RBFS)
+
+EXTRA_DIST = \
+	$(RBFS)
diff --git a/gr-gpio/src/fpga/top/usrp_gpio.rbf b/gr-gpio/src/fpga/rbf/std_2rxhb_2tx_dig.rbf
index 5d1c9c7d2..5d1c9c7d2 100644
--- a/gr-gpio/src/fpga/top/usrp_gpio.rbf
+++ b/gr-gpio/src/fpga/rbf/std_2rxhb_2tx_dig.rbf
diff --git a/gr-gpio/src/fpga/rbf/std_2rxint_2tx_dig.rbf b/gr-gpio/src/fpga/rbf/std_2rxint_2tx_dig.rbf
new file mode 100644
index 000000000..60e194eee
--- /dev/null
+++ b/gr-gpio/src/fpga/rbf/std_2rxint_2tx_dig.rbf
diff --git a/gr-gpio/src/fpga/top/Makefile.am b/gr-gpio/src/fpga/top/Makefile.am
index 7362ea2c8..8cf8f40bd 100644
--- a/gr-gpio/src/fpga/top/Makefile.am
+++ b/gr-gpio/src/fpga/top/Makefile.am
@@ -21,18 +21,6 @@
 
 include $(top_srcdir)/Makefile.common
 
-datadir = $(prefix)/share/usrp
-
-datarev2dir = $(datadir)/rev2
-
-datarev4dir = $(datadir)/rev4
-
-datarev2_DATA = usrp_gpio.rbf
-
-datarev4_DATA = usrp_gpio.rbf
-
-RBFS = usrp_gpio.rbf
-
 EXTRA_DIST = \
 	config.vh    \
 	usrp_gpio.csf \
@@ -40,8 +28,7 @@ EXTRA_DIST = \
 	usrp_gpio.psf \
 	usrp_gpio.qpf \
 	usrp_gpio.qsf \
-	usrp_gpio.v   \
-	$(RBFS)
+	usrp_gpio.v
 
 MOSTLYCLEANFILES = 	\
 	db/*		\
diff --git a/gr-gpio/src/fpga/top/config.vh b/gr-gpio/src/fpga/top/config.vh
index 5fd4fefb0..d40e75d2f 100644
--- a/gr-gpio/src/fpga/top/config.vh
+++ b/gr-gpio/src/fpga/top/config.vh
@@ -35,10 +35,13 @@
 //`include "../include/common_config_1rxhb_1tx.vh"
 
 // Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels
-//  `include "../include/common_config_2rxhb_2tx.vh"
+//`include "../include/common_config_2rxhb_2tx.vh"
 
 // Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels with digital output (lsb of I and Q) on gpio pins
-  `include "../include/common_config_2rxhb_2txdig.vh"
+//`include "../include/common_config_2rxhb_2tx_dig.vh"
+
+// Uncomment this for 2 rx channels (w/o halfband, but w/integrator) & 2 tx channels, with streaming GPIO
+  `include "../include/common_config_2rxint_2tx_dig.vh"
 
 // Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels
 //`include "../include/common_config_4rx_0tx.vh"
diff --git a/gr-gpio/src/fpga/top/usrp_gpio.qsf b/gr-gpio/src/fpga/top/usrp_gpio.qsf
index 4132dccad..cfdcd552b 100644
--- a/gr-gpio/src/fpga/top/usrp_gpio.qsf
+++ b/gr-gpio/src/fpga/top/usrp_gpio.qsf
@@ -375,6 +375,9 @@ set_global_assignment -name VERILOG_FILE ../lib/gpio_input.v
 set_global_assignment -name VERILOG_FILE ../lib/io_pins.v

 set_global_assignment -name VERILOG_FILE ../lib/rx_chain_dig.v

 set_global_assignment -name VERILOG_FILE ../lib/tx_chain_dig.v

+set_global_assignment -name VERILOG_FILE ../lib/integrator.v

+set_global_assignment -name VERILOG_FILE ../lib/integ_shifter.v

+set_global_assignment -name VERILOG_FILE ../lib/rx_chain.v

 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/atr_delay.v

 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cic_dec_shifter.v

 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v

@@ -394,7 +397,6 @@ set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/adc_inter
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/setting_reg.v

 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/bidir_reg.v

 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cic_int_shifter.v

-set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_chain.v

 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/gen_sync.v

 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/master_control.v

 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rx_buffer.v